diff options
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 52 |
1 files changed, 30 insertions, 22 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index defc166379d2..69f2c242797f 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -24,6 +24,9 @@ | |||
| 24 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 | 24 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 |
| 25 | #define PPC_FEATURE_ARCH_2_05 0x00001000 | 25 | #define PPC_FEATURE_ARCH_2_05 0x00001000 |
| 26 | 26 | ||
| 27 | #define PPC_FEATURE_TRUE_LE 0x00000002 | ||
| 28 | #define PPC_FEATURE_PPC_LE 0x00000001 | ||
| 29 | |||
| 27 | #ifdef __KERNEL__ | 30 | #ifdef __KERNEL__ |
| 28 | #ifndef __ASSEMBLY__ | 31 | #ifndef __ASSEMBLY__ |
| 29 | 32 | ||
| @@ -111,6 +114,8 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 111 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 114 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
| 112 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | 115 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) |
| 113 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 116 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
| 117 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) | ||
| 118 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | ||
| 114 | 119 | ||
| 115 | #ifdef __powerpc64__ | 120 | #ifdef __powerpc64__ |
| 116 | /* Add the 64b processor unique features in the top half of the word */ | 121 | /* Add the 64b processor unique features in the top half of the word */ |
| @@ -197,92 +202,95 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 197 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) | 202 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) |
| 198 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 203 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 199 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 204 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
| 200 | CPU_FTR_MAYBE_CAN_NAP) | 205 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 201 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 206 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 202 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE) | 207 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ |
| 208 | CPU_FTR_PPC_LE) | ||
| 203 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 209 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 204 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 210 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 205 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 211 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 206 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 212 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 207 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 213 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 208 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 214 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 215 | CPU_FTR_PPC_LE) | ||
| 209 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 216 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 210 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 217 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 211 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) | 218 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 219 | CPU_FTR_PPC_LE) | ||
| 212 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 220 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 213 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 221 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 214 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 222 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 215 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) | 223 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
| 216 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 224 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 217 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 225 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 218 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 226 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 219 | CPU_FTR_NO_DPM) | 227 | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
| 220 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 228 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 221 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 229 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 222 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 230 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 223 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) | 231 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
| 224 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 232 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
| 225 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ | 233 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ |
| 226 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 234 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 227 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) | 235 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
| 228 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 236 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 229 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 237 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 230 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 238 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 231 | CPU_FTR_MAYBE_CAN_NAP) | 239 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 232 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 240 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 233 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 241 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 234 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 242 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 235 | CPU_FTR_MAYBE_CAN_NAP) | 243 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 236 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 244 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 237 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 245 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 238 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 246 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 239 | CPU_FTR_NEED_COHERENT) | 247 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 240 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 248 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 241 | CPU_FTR_USE_TB | \ | 249 | CPU_FTR_USE_TB | \ |
| 242 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 250 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 243 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 251 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 244 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 252 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 245 | CPU_FTR_NEED_COHERENT) | 253 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 246 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 254 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 247 | CPU_FTR_USE_TB | \ | 255 | CPU_FTR_USE_TB | \ |
| 248 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 256 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 249 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 257 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 250 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT) | 258 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 251 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 259 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 252 | CPU_FTR_USE_TB | \ | 260 | CPU_FTR_USE_TB | \ |
| 253 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 261 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
| 254 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | 262 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ |
| 255 | CPU_FTR_NEED_COHERENT) | 263 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 256 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 264 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 257 | CPU_FTR_USE_TB | \ | 265 | CPU_FTR_USE_TB | \ |
| 258 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 266 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 259 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 267 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 260 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 268 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 261 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS) | 269 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
| 262 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 270 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 263 | CPU_FTR_USE_TB | \ | 271 | CPU_FTR_USE_TB | \ |
| 264 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 272 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 265 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 273 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 266 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 274 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 267 | CPU_FTR_NEED_COHERENT) | 275 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 268 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 276 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 269 | CPU_FTR_USE_TB | \ | 277 | CPU_FTR_USE_TB | \ |
| 270 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 278 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 271 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 279 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 272 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 280 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 273 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC) | 281 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) |
| 274 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 282 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 275 | CPU_FTR_USE_TB | \ | 283 | CPU_FTR_USE_TB | \ |
| 276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 284 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 277 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 285 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 278 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 286 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 279 | CPU_FTR_NEED_COHERENT) | 287 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 280 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 288 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 281 | CPU_FTR_USE_TB | \ | 289 | CPU_FTR_USE_TB | \ |
| 282 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 290 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 283 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 291 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 284 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 292 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 285 | CPU_FTR_NEED_COHERENT) | 293 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 286 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 294 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 287 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | 295 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
| 288 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 296 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
| @@ -312,7 +320,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 312 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) | 320 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
| 313 | #ifdef __powerpc64__ | 321 | #ifdef __powerpc64__ |
| 314 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 322 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 315 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR) | 323 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
| 316 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 324 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 317 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 325 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ |
| 318 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | 326 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
| @@ -330,7 +338,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 330 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 338 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 331 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 339 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 332 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 340 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 333 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE) | 341 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) |
| 334 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 342 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 335 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 343 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 336 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 344 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |