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-rw-r--r--include/asm-powerpc/cputable.h427
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diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
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1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
5#include <asm/ppc_asm.h> /* for ASM_CONST */
6
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
18#define PPC_FEATURE_NO_TB 0x00100000
19
20#ifdef __KERNEL__
21#ifndef __ASSEMBLY__
22
23/* This structure can grow, it's real size is used by head.S code
24 * via the mkdefs mechanism.
25 */
26struct cpu_spec;
27struct op_powerpc_model;
28
29typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
30
31struct cpu_spec {
32 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
33 unsigned int pvr_mask;
34 unsigned int pvr_value;
35
36 char *cpu_name;
37 unsigned long cpu_features; /* Kernel features */
38 unsigned int cpu_user_features; /* Userland features */
39
40 /* cache line sizes */
41 unsigned int icache_bsize;
42 unsigned int dcache_bsize;
43
44 /* number of performance monitor counters */
45 unsigned int num_pmcs;
46
47 /* this is called to initialize various CPU bits like L1 cache,
48 * BHT, SPD, etc... from head.S before branching to identify_machine
49 */
50 cpu_setup_t cpu_setup;
51
52 /* Used by oprofile userspace to select the right counters */
53 char *oprofile_cpu_type;
54
55 /* Processor specific oprofile operations */
56 struct op_powerpc_model *oprofile_model;
57};
58
59extern struct cpu_spec *cur_cpu_spec;
60
61extern void identify_cpu(unsigned long offset, unsigned long cpu);
62extern void do_cpu_ftr_fixups(unsigned long offset);
63
64#endif /* __ASSEMBLY__ */
65
66/* CPU kernel features */
67
68/* Retain the 32b definitions all use bottom half of word */
69#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
70#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
71#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
72#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
73#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
74#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
75#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
76#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
77#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
78#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
79#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
80#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
81#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
82#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
83#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
84#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
85#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
86#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
87#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
88#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
89
90#ifdef __powerpc64__
91/* Add the 64b processor unique features in the top half of the word */
92#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
93#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
94#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
95#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
96#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
97#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
98#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
99#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
100#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
101#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
102#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
103#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
104#else
105/* ensure on 32b processors the flags are available for compiling but
106 * don't do anything */
107#define CPU_FTR_SLB ASM_CONST(0x0)
108#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
109#define CPU_FTR_TLBIEL ASM_CONST(0x0)
110#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
111#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
112#define CPU_FTR_IABR ASM_CONST(0x0)
113#define CPU_FTR_MMCRA ASM_CONST(0x0)
114#define CPU_FTR_CTRL ASM_CONST(0x0)
115#define CPU_FTR_SMT ASM_CONST(0x0)
116#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
117#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
118#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
119#endif
120
121#ifndef __ASSEMBLY__
122
123#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
124 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
125 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
126
127/* iSeries doesn't support large pages */
128#ifdef CONFIG_PPC_ISERIES
129#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
130#else
131#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
132#endif /* CONFIG_PPC_ISERIES */
133
134/* We only set the altivec features if the kernel was compiled with altivec
135 * support
136 */
137#ifdef CONFIG_ALTIVEC
138#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
139#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
140#else
141#define CPU_FTR_ALTIVEC_COMP 0
142#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
143#endif
144
145/* We need to mark all pages as being coherent if we're SMP or we
146 * have a 74[45]x and an MPC107 host bridge.
147 */
148#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
149#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
150#else
151#define CPU_FTR_COMMON 0
152#endif
153
154/* The powersave features NAP & DOZE seems to confuse BDI when
155 debugging. So if a BDI is used, disable theses
156 */
157#ifndef CONFIG_BDI_SWITCH
158#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
159#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
160#else
161#define CPU_FTR_MAYBE_CAN_DOZE 0
162#define CPU_FTR_MAYBE_CAN_NAP 0
163#endif
164
165#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
166 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
167 !defined(CONFIG_BOOKE))
168
169enum {
170 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
171 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
172 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
173 CPU_FTR_MAYBE_CAN_NAP,
174 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
175 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
176 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
177 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
178 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
179 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
180 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
181 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
182 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
183 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
184 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
185 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
186 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
187 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
188 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
189 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
190 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
191 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
192 CPU_FTR_NO_DPM,
193 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
195 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
196 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
197 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
198 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
199 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
200 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
201 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
202 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
203 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
204 CPU_FTR_MAYBE_CAN_NAP,
205 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
206 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
207 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
208 CPU_FTR_MAYBE_CAN_NAP,
209 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
210 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
211 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
212 CPU_FTR_NEED_COHERENT,
213 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
214 CPU_FTR_USE_TB |
215 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
216 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
217 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
218 CPU_FTR_NEED_COHERENT,
219 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
220 CPU_FTR_USE_TB |
221 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
222 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
223 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
224 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
225 CPU_FTR_USE_TB |
226 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
227 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
228 CPU_FTR_NEED_COHERENT,
229 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
230 CPU_FTR_USE_TB |
231 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
232 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
233 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
234 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
235 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
239 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
240 CPU_FTR_NEED_COHERENT,
241 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
242 CPU_FTR_USE_TB |
243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
245 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
246 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
247 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
248 CPU_FTR_USE_TB |
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
252 CPU_FTR_NEED_COHERENT,
253 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
254 CPU_FTR_USE_TB |
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
256 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
258 CPU_FTR_NEED_COHERENT,
259 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
260 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
261 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
262 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
263 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
264 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
265 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
266 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
267 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
268 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
269 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
270 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
271 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
272 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
273 CPU_FTR_MAYBE_CAN_NAP,
274 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
275 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
276 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
277 CPU_FTRS_E200 = CPU_FTR_USE_TB,
278 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
279 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
280 CPU_FTR_BIG_PHYS,
281 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
282#ifdef __powerpc64__
283 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
284 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
285 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
286 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
287 CPU_FTR_MMCRA | CPU_FTR_CTRL,
288 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
289 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
290 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
291 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
292 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
293 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
294 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
295 CPU_FTR_MMCRA | CPU_FTR_SMT |
296 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
297 CPU_FTR_MMCRA_SIHV,
298 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
299 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
300 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
301 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
302 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
303#endif
304
305 CPU_FTRS_POSSIBLE =
306#if CLASSIC_PPC
307 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
308 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
309 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
310 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
311 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
312 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
313 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
314 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
315#else
316 CPU_FTRS_GENERIC_32 |
317#endif
318#ifdef CONFIG_PPC64BRIDGE
319 CPU_FTRS_POWER3_32 |
320#endif
321#ifdef CONFIG_POWER4
322 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
323#endif
324#ifdef CONFIG_8xx
325 CPU_FTRS_8XX |
326#endif
327#ifdef CONFIG_40x
328 CPU_FTRS_40X |
329#endif
330#ifdef CONFIG_44x
331 CPU_FTRS_44X |
332#endif
333#ifdef CONFIG_E200
334 CPU_FTRS_E200 |
335#endif
336#ifdef CONFIG_E500
337 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
338#endif
339#ifdef __powerpc64__
340 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
341 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
342#endif
343 0,
344
345 CPU_FTRS_ALWAYS =
346#if CLASSIC_PPC
347 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
348 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
349 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
350 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
351 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
352 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
353 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
354 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
355#else
356 CPU_FTRS_GENERIC_32 &
357#endif
358#ifdef CONFIG_PPC64BRIDGE
359 CPU_FTRS_POWER3_32 &
360#endif
361#ifdef CONFIG_POWER4
362 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
363#endif
364#ifdef CONFIG_8xx
365 CPU_FTRS_8XX &
366#endif
367#ifdef CONFIG_40x
368 CPU_FTRS_40X &
369#endif
370#ifdef CONFIG_44x
371 CPU_FTRS_44X &
372#endif
373#ifdef CONFIG_E200
374 CPU_FTRS_E200 &
375#endif
376#ifdef CONFIG_E500
377 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
378#endif
379#ifdef __powerpc64__
380 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
381 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
382#endif
383 CPU_FTRS_POSSIBLE,
384};
385
386static inline int cpu_has_feature(unsigned long feature)
387{
388 return (CPU_FTRS_ALWAYS & feature) ||
389 (CPU_FTRS_POSSIBLE
390 & cur_cpu_spec->cpu_features
391 & feature);
392}
393
394#endif /* !__ASSEMBLY__ */
395
396#ifdef __ASSEMBLY__
397
398#define BEGIN_FTR_SECTION 98:
399
400#ifndef __powerpc64__
401#define END_FTR_SECTION(msk, val) \
40299: \
403 .section __ftr_fixup,"a"; \
404 .align 2; \
405 .long msk; \
406 .long val; \
407 .long 98b; \
408 .long 99b; \
409 .previous
410#else /* __powerpc64__ */
411#define END_FTR_SECTION(msk, val) \
41299: \
413 .section __ftr_fixup,"a"; \
414 .align 3; \
415 .llong msk; \
416 .llong val; \
417 .llong 98b; \
418 .llong 99b; \
419 .previous
420#endif /* __powerpc64__ */
421
422#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
423#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
424#endif /* __ASSEMBLY__ */
425
426#endif /* __KERNEL__ */
427#endif /* __ASM_POWERPC_CPUTABLE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-04 00:08:31 -0500