diff options
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 111 |
1 files changed, 48 insertions, 63 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 82d595a52109..3dc8e2dfca84 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -111,7 +111,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 111 | /* CPU kernel features */ | 111 | /* CPU kernel features */ |
| 112 | 112 | ||
| 113 | /* Retain the 32b definitions all use bottom half of word */ | 113 | /* Retain the 32b definitions all use bottom half of word */ |
| 114 | #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) | 114 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001) |
| 115 | #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) | 115 | #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) |
| 116 | #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) | 116 | #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) |
| 117 | #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) | 117 | #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) |
| @@ -135,6 +135,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 135 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) | 135 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) |
| 136 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | 136 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) |
| 137 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) | 137 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) |
| 138 | #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) | ||
| 138 | 139 | ||
| 139 | /* | 140 | /* |
| 140 | * Add the 64-bit processor unique features in the top half of the word; | 141 | * Add the 64-bit processor unique features in the top half of the word; |
| @@ -154,7 +155,6 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 154 | #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) | 155 | #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) |
| 155 | #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) | 156 | #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) |
| 156 | #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) | 157 | #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) |
| 157 | #define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000) | ||
| 158 | #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) | 158 | #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) |
| 159 | #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) | 159 | #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) |
| 160 | #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) | 160 | #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) |
| @@ -206,164 +206,149 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 206 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | 206 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ |
| 207 | !defined(CONFIG_BOOKE)) | 207 | !defined(CONFIG_BOOKE)) |
| 208 | 208 | ||
| 209 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) | 209 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \ |
| 210 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 210 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) |
| 211 | #define CPU_FTRS_603 (CPU_FTR_COMMON | \ | ||
| 211 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 212 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
| 212 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 213 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 213 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 214 | #define CPU_FTRS_604 (CPU_FTR_COMMON | \ |
| 214 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ | 215 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ |
| 215 | CPU_FTR_PPC_LE) | 216 | CPU_FTR_PPC_LE) |
| 216 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 217 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ |
| 217 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 218 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 218 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 219 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 219 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 220 | #define CPU_FTRS_740 (CPU_FTR_COMMON | \ |
| 220 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 221 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 221 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 222 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 222 | CPU_FTR_PPC_LE) | 223 | CPU_FTR_PPC_LE) |
| 223 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 224 | #define CPU_FTRS_750 (CPU_FTR_COMMON | \ |
| 224 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 225 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 225 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 226 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 226 | CPU_FTR_PPC_LE) | 227 | CPU_FTR_PPC_LE) |
| 227 | #define CPU_FTRS_750CL (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 228 | #define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS) |
| 228 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 229 | #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) |
| 229 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 230 | #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) |
| 230 | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | 231 | #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \ |
| 231 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 232 | CPU_FTR_HAS_HIGH_BATS) |
| 232 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 233 | #define CPU_FTRS_750GX (CPU_FTRS_750FX) |
| 233 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 234 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ |
| 234 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) | ||
| 235 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
| 236 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | ||
| 237 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | ||
| 238 | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) | ||
| 239 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
| 240 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | ||
| 241 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | ||
| 242 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | ||
| 243 | #define CPU_FTRS_750GX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
| 244 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | ||
| 245 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | ||
| 246 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | ||
| 247 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | ||
| 248 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 235 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 249 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 236 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 250 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 237 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 251 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 238 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ |
| 252 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 239 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 253 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 240 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 254 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 241 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 255 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 242 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ |
| 256 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 243 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 257 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 244 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 258 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 245 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 259 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 246 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ |
| 260 | CPU_FTR_USE_TB | \ | 247 | CPU_FTR_USE_TB | \ |
| 261 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 248 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 262 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 249 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 263 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 250 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 264 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 251 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 265 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 252 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ |
| 266 | CPU_FTR_USE_TB | \ | 253 | CPU_FTR_USE_TB | \ |
| 267 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 254 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 268 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 255 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 269 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 256 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 270 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 257 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ |
| 271 | CPU_FTR_USE_TB | \ | 258 | CPU_FTR_USE_TB | \ |
| 272 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 259 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
| 273 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | 260 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ |
| 274 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 261 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 275 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 262 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ |
| 276 | CPU_FTR_USE_TB | \ | 263 | CPU_FTR_USE_TB | \ |
| 277 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 264 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 278 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 265 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 279 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 266 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 280 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | 267 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
| 281 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 268 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ |
| 282 | CPU_FTR_USE_TB | \ | 269 | CPU_FTR_USE_TB | \ |
| 283 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 270 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 284 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 271 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 285 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 272 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 286 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 273 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 287 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 274 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ |
| 288 | CPU_FTR_USE_TB | \ | 275 | CPU_FTR_USE_TB | \ |
| 289 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 290 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 277 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 291 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 278 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 292 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) | 279 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) |
| 293 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 280 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ |
| 294 | CPU_FTR_USE_TB | \ | 281 | CPU_FTR_USE_TB | \ |
| 295 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 282 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 296 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 283 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 297 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 284 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 298 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 285 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 299 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 286 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ |
| 300 | CPU_FTR_USE_TB | \ | 287 | CPU_FTR_USE_TB | \ |
| 301 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 288 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 302 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 289 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 303 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 290 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 304 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 291 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 305 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 292 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ |
| 306 | CPU_FTR_USE_TB | \ | 293 | CPU_FTR_USE_TB | \ |
| 307 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 294 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 308 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 295 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 309 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 296 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 310 | CPU_FTR_PPC_LE) | 297 | CPU_FTR_PPC_LE) |
| 311 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 298 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ |
| 312 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | 299 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
| 313 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 300 | #define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE | \ |
| 314 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) | 301 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) |
| 315 | #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 302 | #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ |
| 316 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 303 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ |
| 317 | CPU_FTR_COMMON) | 304 | CPU_FTR_COMMON) |
| 318 | #define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | 305 | #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
| 319 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 306 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ |
| 320 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) | 307 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) |
| 321 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | 308 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \ |
| 322 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | 309 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) |
| 323 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) | 310 | #define CPU_FTRS_8XX (CPU_FTR_USE_TB) |
| 324 | #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 311 | #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) |
| 325 | CPU_FTR_NODSISRALIGN) | 312 | #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) |
| 326 | #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 313 | #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ |
| 327 | CPU_FTR_NODSISRALIGN) | 314 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) |
| 328 | #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) | 315 | #define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) |
| 329 | #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 316 | #define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \ |
| 330 | CPU_FTR_NODSISRALIGN) | ||
| 331 | #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | ||
| 332 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) | 317 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) |
| 333 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) | 318 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
| 334 | 319 | ||
| 335 | /* 64-bit CPUs */ | 320 | /* 64-bit CPUs */ |
| 336 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 321 | #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ |
| 337 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) | 322 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
| 338 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 323 | #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ |
| 339 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 324 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ |
| 340 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | 325 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
| 341 | #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 326 | #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \ |
| 342 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 327 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 343 | CPU_FTR_MMCRA) | 328 | CPU_FTR_MMCRA) |
| 344 | #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 329 | #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \ |
| 345 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 330 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 346 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) | 331 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) |
| 347 | #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 332 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \ |
| 348 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 333 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 349 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 334 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 350 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 335 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 351 | CPU_FTR_PURR) | 336 | CPU_FTR_PURR) |
| 352 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 337 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \ |
| 353 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 338 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 354 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 339 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 355 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 340 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 356 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 341 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
| 357 | CPU_FTR_DSCR) | 342 | CPU_FTR_DSCR) |
| 358 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 343 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | \ |
| 359 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 344 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 360 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 345 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 361 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG) | 346 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG) |
| 362 | #define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 347 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \ |
| 363 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 348 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 364 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ | 349 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ |
| 365 | CPU_FTR_PURR | CPU_FTR_REAL_LE) | 350 | CPU_FTR_PURR | CPU_FTR_REAL_LE) |
| 366 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 351 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \ |
| 367 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | 352 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) |
| 368 | 353 | ||
| 369 | #ifdef __powerpc64__ | 354 | #ifdef __powerpc64__ |