diff options
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 748bc1805da9..3608259c49cf 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -148,7 +148,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 148 | 148 | ||
| 149 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ | 149 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
| 150 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ | 150 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ |
| 151 | CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) | 151 | CPU_FTR_NODSISRALIGN) |
| 152 | 152 | ||
| 153 | /* iSeries doesn't support large pages */ | 153 | /* iSeries doesn't support large pages */ |
| 154 | #ifdef CONFIG_PPC_ISERIES | 154 | #ifdef CONFIG_PPC_ISERIES |
| @@ -313,24 +313,25 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 313 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 313 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ |
| 314 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | 314 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
| 315 | #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 315 | #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 316 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA) | 316 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 317 | CPU_FTR_MMCRA) | ||
| 317 | #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 318 | #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 318 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 319 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 319 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) | 320 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) |
| 320 | #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 321 | #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 321 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 322 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 322 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 323 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 323 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 324 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 324 | CPU_FTR_PURR) | 325 | CPU_FTR_PURR) |
| 325 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 326 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 326 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 327 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 327 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 328 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 328 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 329 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 329 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) | 330 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) |
| 330 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 331 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 331 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 332 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 332 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 333 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 333 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) | 334 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) |
| 334 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | 335 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 335 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | 336 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) |
| 336 | #endif | 337 | #endif |