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-rw-r--r--include/asm-powerpc/cputable.h27
1 files changed, 18 insertions, 9 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 6fe5c9d4ca3b..e870b5393175 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -50,6 +50,12 @@ enum powerpc_oprofile_type {
50 PPC_OPROFILE_CELL = 5, 50 PPC_OPROFILE_CELL = 5,
51}; 51};
52 52
53enum powerpc_pmc_type {
54 PPC_PMC_DEFAULT = 0,
55 PPC_PMC_IBM = 1,
56 PPC_PMC_PA6T = 2,
57};
58
53struct cpu_spec { 59struct cpu_spec {
54 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 60 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
55 unsigned int pvr_mask; 61 unsigned int pvr_mask;
@@ -65,6 +71,7 @@ struct cpu_spec {
65 71
66 /* number of performance monitor counters */ 72 /* number of performance monitor counters */
67 unsigned int num_pmcs; 73 unsigned int num_pmcs;
74 enum powerpc_pmc_type pmc_type;
68 75
69 /* this is called to initialize various CPU bits like L1 cache, 76 /* this is called to initialize various CPU bits like L1 cache,
70 * BHT, SPD, etc... from head.S before branching to identify_machine 77 * BHT, SPD, etc... from head.S before branching to identify_machine
@@ -126,6 +133,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
126#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 133#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
127#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 134#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
128#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 135#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
136#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
129 137
130/* 138/*
131 * Add the 64-bit processor unique features in the top half of the word; 139 * Add the 64-bit processor unique features in the top half of the word;
@@ -152,6 +160,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
152#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
153#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
154#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
155 164
156#ifndef __ASSEMBLY__ 165#ifndef __ASSEMBLY__
157 166
@@ -295,6 +304,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
295#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 304#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
296 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ 305 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
297 CPU_FTR_COMMON) 306 CPU_FTR_COMMON)
307#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
308 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
309 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
298#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 310#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
299 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) 311 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
300#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) 312#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
@@ -330,13 +342,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 342 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
331 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 343 CPU_FTR_MMCRA | CPU_FTR_SMT | \
332 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 344 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
333 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE) 345 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
334#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 346 CPU_FTR_DSCR)
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
336 CPU_FTR_MMCRA | CPU_FTR_SMT | \
337 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
338 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
339 CPU_FTR_SPURR | CPU_FTR_REAL_LE)
340#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 347#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 348 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
342 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 349 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -364,7 +371,8 @@ enum {
364 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 371 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
365 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 372 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
366 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 373 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
367 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 | 374 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
375 CPU_FTRS_CLASSIC32 |
368#else 376#else
369 CPU_FTRS_GENERIC_32 | 377 CPU_FTRS_GENERIC_32 |
370#endif 378#endif
@@ -403,7 +411,8 @@ enum {
403 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 411 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
404 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 412 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
405 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 413 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
406 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 & 414 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
415 CPU_FTRS_CLASSIC32 &
407#else 416#else
408 CPU_FTRS_GENERIC_32 & 417 CPU_FTRS_GENERIC_32 &
409#endif 418#endif