diff options
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 5638518968c3..fe45f6f3a4be 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -102,38 +102,40 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 102 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | 102 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) |
| 103 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 103 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
| 104 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | 104 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) |
| 105 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 105 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
| 106 | 106 | ||
| 107 | #ifdef __powerpc64__ | 107 | #ifdef __powerpc64__ |
| 108 | /* Add the 64b processor unique features in the top half of the word */ | 108 | /* Add the 64b processor unique features in the top half of the word */ |
| 109 | #define CPU_FTR_SLB ASM_CONST(0x0000000100000000) | 109 | #define CPU_FTR_SLB ASM_CONST(0x0000000100000000) |
| 110 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) | 110 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) |
| 111 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) | 111 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) |
| 112 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) | 112 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) |
| 113 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) | 113 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) |
| 114 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) | 114 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) |
| 115 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) | 115 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) |
| 116 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) | 116 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) |
| 117 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) | 117 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) |
| 118 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) | 118 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) |
| 119 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) | 119 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) |
| 120 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) | 120 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) |
| 121 | #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000) | 121 | #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000) |
| 122 | #define CPU_FTR_PURR ASM_CONST(0x0000400000000000) | ||
| 122 | #else | 123 | #else |
| 123 | /* ensure on 32b processors the flags are available for compiling but | 124 | /* ensure on 32b processors the flags are available for compiling but |
| 124 | * don't do anything */ | 125 | * don't do anything */ |
| 125 | #define CPU_FTR_SLB ASM_CONST(0x0) | 126 | #define CPU_FTR_SLB ASM_CONST(0x0) |
| 126 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) | 127 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) |
| 127 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) | 128 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) |
| 128 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) | 129 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) |
| 129 | #define CPU_FTR_IABR ASM_CONST(0x0) | 130 | #define CPU_FTR_IABR ASM_CONST(0x0) |
| 130 | #define CPU_FTR_MMCRA ASM_CONST(0x0) | 131 | #define CPU_FTR_MMCRA ASM_CONST(0x0) |
| 131 | #define CPU_FTR_CTRL ASM_CONST(0x0) | 132 | #define CPU_FTR_CTRL ASM_CONST(0x0) |
| 132 | #define CPU_FTR_SMT ASM_CONST(0x0) | 133 | #define CPU_FTR_SMT ASM_CONST(0x0) |
| 133 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0) | 134 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0) |
| 134 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0) | 135 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0) |
| 135 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0) | 136 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0) |
| 136 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0) | 137 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0) |
| 138 | #define CPU_FTR_PURR ASM_CONST(0x0) | ||
| 137 | #endif | 139 | #endif |
| 138 | 140 | ||
| 139 | #ifndef __ASSEMBLY__ | 141 | #ifndef __ASSEMBLY__ |
| @@ -318,7 +320,7 @@ enum { | |||
| 318 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | 320 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | |
| 319 | CPU_FTR_MMCRA | CPU_FTR_SMT | | 321 | CPU_FTR_MMCRA | CPU_FTR_SMT | |
| 320 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | | 322 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | |
| 321 | CPU_FTR_MMCRA_SIHV, | 323 | CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR, |
| 322 | CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 324 | CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | |
| 323 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | 325 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | |
| 324 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | | 326 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | |