1 files changed, 9 insertions, 4 deletions

diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 64210549f56b..99d12ff6346c 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -117,6 +117,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0000100000000000)
 #define CPU_FTR_PAUSE_ZERO              ASM_CONST(0x0000200000000000)
+#define CPU_FTR_PURR                    ASM_CONST(0x0000400000000000)
 #else
 /* ensure on 32b processors the flags are available for compiling but
  * don't do anything */
@@ -132,6 +133,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0)
+#define CPU_FTR_PURR                    ASM_CONST(0x0)
 #endif
 
 #ifndef __ASSEMBLY__
@@ -159,9 +161,11 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 74[45]x and an MPC107 host bridge.
+ * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
+ * it for PCI "streaming/prefetch" to work properly.
  */
-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
+        || defined(CONFIG_PPC_83xx)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 #else
 #define CPU_FTR_COMMON                  0
@@ -277,7 +281,8 @@ enum {
         CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
         CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
-            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS |
+            CPU_FTR_COMMON,
         CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
         CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
@@ -313,7 +318,7 @@ enum {
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
             CPU_FTR_MMCRA | CPU_FTR_SMT |
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
-            CPU_FTR_MMCRA_SIHV,
+            CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR,
         CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |