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1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM1__
18#define __CPM1__
19
20#include <asm/8xx_immap.h>
21#include <asm/ptrace.h>
22#include <asm/cpm.h>
23
24/* CPM Command register.
25*/
26#define CPM_CR_RST ((ushort)0x8000)
27#define CPM_CR_OPCODE ((ushort)0x0f00)
28#define CPM_CR_CHAN ((ushort)0x00f0)
29#define CPM_CR_FLG ((ushort)0x0001)
30
31/* Some commands (there are more...later)
32*/
33#define CPM_CR_INIT_TRX ((ushort)0x0000)
34#define CPM_CR_INIT_RX ((ushort)0x0001)
35#define CPM_CR_INIT_TX ((ushort)0x0002)
36#define CPM_CR_HUNT_MODE ((ushort)0x0003)
37#define CPM_CR_STOP_TX ((ushort)0x0004)
38#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
39#define CPM_CR_RESTART_TX ((ushort)0x0006)
40#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
41#define CPM_CR_SET_GADDR ((ushort)0x0008)
42#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
43
44/* Channel numbers.
45*/
46#define CPM_CR_CH_SCC1 ((ushort)0x0000)
47#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
48#define CPM_CR_CH_SCC2 ((ushort)0x0004)
49#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
50#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
51#define CPM_CR_CH_SCC3 ((ushort)0x0008)
52#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
53#define CPM_CR_CH_SCC4 ((ushort)0x000c)
54#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
55
56#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
57
58#ifndef CONFIG_PPC_CPM_NEW_BINDING
59/* The dual ported RAM is multi-functional. Some areas can be (and are
60 * being) used for microcode. There is an area that can only be used
61 * as data ram for buffer descriptors, which is all we use right now.
62 * Currently the first 512 and last 256 bytes are used for microcode.
63 */
64#define CPM_DATAONLY_BASE ((uint)0x0800)
65#define CPM_DATAONLY_SIZE ((uint)0x0700)
66#define CPM_DP_NOSPACE ((uint)0x7fffffff)
67#endif
68
69/* Export the base address of the communication processor registers
70 * and dual port ram.
71 */
72extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
73
74#ifdef CONFIG_PPC_CPM_NEW_BINDING
75#define cpm_dpalloc cpm_muram_alloc
76#define cpm_dpfree cpm_muram_free
77#define cpm_dpram_addr cpm_muram_addr
78#define cpm_dpram_phys cpm_muram_dma
79#else
80extern unsigned long cpm_dpalloc(uint size, uint align);
81extern int cpm_dpfree(unsigned long offset);
82extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
83extern void cpm_dpdump(void);
84extern void *cpm_dpram_addr(unsigned long offset);
85extern uint cpm_dpram_phys(u8 *addr);
86#endif
87
88extern void cpm_setbrg(uint brg, uint rate);
89
90extern void cpm_load_patch(cpm8xx_t *cp);
91
92extern void cpm_reset(void);
93
94/* Parameter RAM offsets.
95*/
96#define PROFF_SCC1 ((uint)0x0000)
97#define PROFF_IIC ((uint)0x0080)
98#define PROFF_SCC2 ((uint)0x0100)
99#define PROFF_SPI ((uint)0x0180)
100#define PROFF_SCC3 ((uint)0x0200)
101#define PROFF_SMC1 ((uint)0x0280)
102#define PROFF_SCC4 ((uint)0x0300)
103#define PROFF_SMC2 ((uint)0x0380)
104
105/* Define enough so I can at least use the serial port as a UART.
106 * The MBX uses SMC1 as the host serial port.
107 */
108typedef struct smc_uart {
109 ushort smc_rbase; /* Rx Buffer descriptor base address */
110 ushort smc_tbase; /* Tx Buffer descriptor base address */
111 u_char smc_rfcr; /* Rx function code */
112 u_char smc_tfcr; /* Tx function code */
113 ushort smc_mrblr; /* Max receive buffer length */
114 uint smc_rstate; /* Internal */
115 uint smc_idp; /* Internal */
116 ushort smc_rbptr; /* Internal */
117 ushort smc_ibc; /* Internal */
118 uint smc_rxtmp; /* Internal */
119 uint smc_tstate; /* Internal */
120 uint smc_tdp; /* Internal */
121 ushort smc_tbptr; /* Internal */
122 ushort smc_tbc; /* Internal */
123 uint smc_txtmp; /* Internal */
124 ushort smc_maxidl; /* Maximum idle characters */
125 ushort smc_tmpidl; /* Temporary idle counter */
126 ushort smc_brklen; /* Last received break length */
127 ushort smc_brkec; /* rcv'd break condition counter */
128 ushort smc_brkcr; /* xmt break count register */
129 ushort smc_rmask; /* Temporary bit mask */
130 char res1[8]; /* Reserved */
131 ushort smc_rpbase; /* Relocation pointer */
132} smc_uart_t;
133
134/* Function code bits.
135*/
136#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
137
138/* SMC uart mode register.
139*/
140#define SMCMR_REN ((ushort)0x0001)
141#define SMCMR_TEN ((ushort)0x0002)
142#define SMCMR_DM ((ushort)0x000c)
143#define SMCMR_SM_GCI ((ushort)0x0000)
144#define SMCMR_SM_UART ((ushort)0x0020)
145#define SMCMR_SM_TRANS ((ushort)0x0030)
146#define SMCMR_SM_MASK ((ushort)0x0030)
147#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
148#define SMCMR_REVD SMCMR_PM_EVEN
149#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
150#define SMCMR_BS SMCMR_PEN
151#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
152#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
153#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
154
155/* SMC2 as Centronics parallel printer. It is half duplex, in that
156 * it can only receive or transmit. The parameter ram values for
157 * each direction are either unique or properly overlap, so we can
158 * include them in one structure.
159 */
160typedef struct smc_centronics {
161 ushort scent_rbase;
162 ushort scent_tbase;
163 u_char scent_cfcr;
164 u_char scent_smask;
165 ushort scent_mrblr;
166 uint scent_rstate;
167 uint scent_r_ptr;
168 ushort scent_rbptr;
169 ushort scent_r_cnt;
170 uint scent_rtemp;
171 uint scent_tstate;
172 uint scent_t_ptr;
173 ushort scent_tbptr;
174 ushort scent_t_cnt;
175 uint scent_ttemp;
176 ushort scent_max_sl;
177 ushort scent_sl_cnt;
178 ushort scent_character1;
179 ushort scent_character2;
180 ushort scent_character3;
181 ushort scent_character4;
182 ushort scent_character5;
183 ushort scent_character6;
184 ushort scent_character7;
185 ushort scent_character8;
186 ushort scent_rccm;
187 ushort scent_rccr;
188} smc_cent_t;
189
190/* Centronics Status Mask Register.
191*/
192#define SMC_CENT_F ((u_char)0x08)
193#define SMC_CENT_PE ((u_char)0x04)
194#define SMC_CENT_S ((u_char)0x02)
195
196/* SMC Event and Mask register.
197*/
198#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
199#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
200#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
201#define SMCM_BSY ((unsigned char)0x04)
202#define SMCM_TX ((unsigned char)0x02)
203#define SMCM_RX ((unsigned char)0x01)
204
205/* Baud rate generators.
206*/
207#define CPM_BRG_RST ((uint)0x00020000)
208#define CPM_BRG_EN ((uint)0x00010000)
209#define CPM_BRG_EXTC_INT ((uint)0x00000000)
210#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
211#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
212#define CPM_BRG_ATB ((uint)0x00002000)
213#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
214#define CPM_BRG_DIV16 ((uint)0x00000001)
215
216/* SI Clock Route Register
217*/
218#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
219#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
220#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
221#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
222#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
223#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
224#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
225#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
226
227/* SCCs.
228*/
229#define SCC_GSMRH_IRP ((uint)0x00040000)
230#define SCC_GSMRH_GDE ((uint)0x00010000)
231#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
232#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
233#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
234#define SCC_GSMRH_REVD ((uint)0x00002000)
235#define SCC_GSMRH_TRX ((uint)0x00001000)
236#define SCC_GSMRH_TTX ((uint)0x00000800)
237#define SCC_GSMRH_CDP ((uint)0x00000400)
238#define SCC_GSMRH_CTSP ((uint)0x00000200)
239#define SCC_GSMRH_CDS ((uint)0x00000100)
240#define SCC_GSMRH_CTSS ((uint)0x00000080)
241#define SCC_GSMRH_TFL ((uint)0x00000040)
242#define SCC_GSMRH_RFW ((uint)0x00000020)
243#define SCC_GSMRH_TXSY ((uint)0x00000010)
244#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
245#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
246#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
247#define SCC_GSMRH_RTSM ((uint)0x00000002)
248#define SCC_GSMRH_RSYN ((uint)0x00000001)
249
250#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
251#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
252#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
253#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
254#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
255#define SCC_GSMRL_TCI ((uint)0x10000000)
256#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
257#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
258#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
259#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
260#define SCC_GSMRL_RINV ((uint)0x02000000)
261#define SCC_GSMRL_TINV ((uint)0x01000000)
262#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
263#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
264#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
265#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
266#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
267#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
268#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
269#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
270#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
271#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
272#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
273#define SCC_GSMRL_TEND ((uint)0x00040000)
274#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
275#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
276#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
277#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
278#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
279#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
280#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
281#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
282#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
283#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
284#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
285#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
286#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
287#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
288#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
289#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
290#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
291#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
292#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
293#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
294#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
295#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
296#define SCC_GSMRL_ENR ((uint)0x00000020)
297#define SCC_GSMRL_ENT ((uint)0x00000010)
298#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
299#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
300#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
301#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
302#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
303#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
304#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
305#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
306#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
307#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
308#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
309
310#define SCC_TODR_TOD ((ushort)0x8000)
311
312/* SCC Event and Mask register.
313*/
314#define SCCM_TXE ((unsigned char)0x10)
315#define SCCM_BSY ((unsigned char)0x04)
316#define SCCM_TX ((unsigned char)0x02)
317#define SCCM_RX ((unsigned char)0x01)
318
319typedef struct scc_param {
320 ushort scc_rbase; /* Rx Buffer descriptor base address */
321 ushort scc_tbase; /* Tx Buffer descriptor base address */
322 u_char scc_rfcr; /* Rx function code */
323 u_char scc_tfcr; /* Tx function code */
324 ushort scc_mrblr; /* Max receive buffer length */
325 uint scc_rstate; /* Internal */
326 uint scc_idp; /* Internal */
327 ushort scc_rbptr; /* Internal */
328 ushort scc_ibc; /* Internal */
329 uint scc_rxtmp; /* Internal */
330 uint scc_tstate; /* Internal */
331 uint scc_tdp; /* Internal */
332 ushort scc_tbptr; /* Internal */
333 ushort scc_tbc; /* Internal */
334 uint scc_txtmp; /* Internal */
335 uint scc_rcrc; /* Internal */
336 uint scc_tcrc; /* Internal */
337} sccp_t;
338
339/* Function code bits.
340*/
341#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
342
343/* CPM Ethernet through SCCx.
344 */
345typedef struct scc_enet {
346 sccp_t sen_genscc;
347 uint sen_cpres; /* Preset CRC */
348 uint sen_cmask; /* Constant mask for CRC */
349 uint sen_crcec; /* CRC Error counter */
350 uint sen_alec; /* alignment error counter */
351 uint sen_disfc; /* discard frame counter */
352 ushort sen_pads; /* Tx short frame pad character */
353 ushort sen_retlim; /* Retry limit threshold */
354 ushort sen_retcnt; /* Retry limit counter */
355 ushort sen_maxflr; /* maximum frame length register */
356 ushort sen_minflr; /* minimum frame length register */
357 ushort sen_maxd1; /* maximum DMA1 length */
358 ushort sen_maxd2; /* maximum DMA2 length */
359 ushort sen_maxd; /* Rx max DMA */
360 ushort sen_dmacnt; /* Rx DMA counter */
361 ushort sen_maxb; /* Max BD byte count */
362 ushort sen_gaddr1; /* Group address filter */
363 ushort sen_gaddr2;
364 ushort sen_gaddr3;
365 ushort sen_gaddr4;
366 uint sen_tbuf0data0; /* Save area 0 - current frame */
367 uint sen_tbuf0data1; /* Save area 1 - current frame */
368 uint sen_tbuf0rba; /* Internal */
369 uint sen_tbuf0crc; /* Internal */
370 ushort sen_tbuf0bcnt; /* Internal */
371 ushort sen_paddrh; /* physical address (MSB) */
372 ushort sen_paddrm;
373 ushort sen_paddrl; /* physical address (LSB) */
374 ushort sen_pper; /* persistence */
375 ushort sen_rfbdptr; /* Rx first BD pointer */
376 ushort sen_tfbdptr; /* Tx first BD pointer */
377 ushort sen_tlbdptr; /* Tx last BD pointer */
378 uint sen_tbuf1data0; /* Save area 0 - current frame */
379 uint sen_tbuf1data1; /* Save area 1 - current frame */
380 uint sen_tbuf1rba; /* Internal */
381 uint sen_tbuf1crc; /* Internal */
382 ushort sen_tbuf1bcnt; /* Internal */
383 ushort sen_txlen; /* Tx Frame length counter */
384 ushort sen_iaddr1; /* Individual address filter */
385 ushort sen_iaddr2;
386 ushort sen_iaddr3;
387 ushort sen_iaddr4;
388 ushort sen_boffcnt; /* Backoff counter */
389
390 /* NOTE: Some versions of the manual have the following items
391 * incorrectly documented. Below is the proper order.
392 */
393 ushort sen_taddrh; /* temp address (MSB) */
394 ushort sen_taddrm;
395 ushort sen_taddrl; /* temp address (LSB) */
396} scc_enet_t;
397
398/* SCC Event register as used by Ethernet.
399*/
400#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
401#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
402#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
403#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
404#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
405#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
406
407/* SCC Mode Register (PMSR) as used by Ethernet.
408*/
409#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
410#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
411#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
412#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
413#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
414#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
415#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
416#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
417#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
418#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
419#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
420#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
421#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
422
423/* SCC as UART
424*/
425typedef struct scc_uart {
426 sccp_t scc_genscc;
427 char res1[8]; /* Reserved */
428 ushort scc_maxidl; /* Maximum idle chars */
429 ushort scc_idlc; /* temp idle counter */
430 ushort scc_brkcr; /* Break count register */
431 ushort scc_parec; /* receive parity error counter */
432 ushort scc_frmec; /* receive framing error counter */
433 ushort scc_nosec; /* receive noise counter */
434 ushort scc_brkec; /* receive break condition counter */
435 ushort scc_brkln; /* last received break length */
436 ushort scc_uaddr1; /* UART address character 1 */
437 ushort scc_uaddr2; /* UART address character 2 */
438 ushort scc_rtemp; /* Temp storage */
439 ushort scc_toseq; /* Transmit out of sequence char */
440 ushort scc_char1; /* control character 1 */
441 ushort scc_char2; /* control character 2 */
442 ushort scc_char3; /* control character 3 */
443 ushort scc_char4; /* control character 4 */
444 ushort scc_char5; /* control character 5 */
445 ushort scc_char6; /* control character 6 */
446 ushort scc_char7; /* control character 7 */
447 ushort scc_char8; /* control character 8 */
448 ushort scc_rccm; /* receive control character mask */
449 ushort scc_rccr; /* receive control character register */
450 ushort scc_rlbc; /* receive last break character */
451} scc_uart_t;
452
453/* SCC Event and Mask registers when it is used as a UART.
454*/
455#define UART_SCCM_GLR ((ushort)0x1000)
456#define UART_SCCM_GLT ((ushort)0x0800)
457#define UART_SCCM_AB ((ushort)0x0200)
458#define UART_SCCM_IDL ((ushort)0x0100)
459#define UART_SCCM_GRA ((ushort)0x0080)
460#define UART_SCCM_BRKE ((ushort)0x0040)
461#define UART_SCCM_BRKS ((ushort)0x0020)
462#define UART_SCCM_CCR ((ushort)0x0008)
463#define UART_SCCM_BSY ((ushort)0x0004)
464#define UART_SCCM_TX ((ushort)0x0002)
465#define UART_SCCM_RX ((ushort)0x0001)
466
467/* The SCC PMSR when used as a UART.
468*/
469#define SCU_PSMR_FLC ((ushort)0x8000)
470#define SCU_PSMR_SL ((ushort)0x4000)
471#define SCU_PSMR_CL ((ushort)0x3000)
472#define SCU_PSMR_UM ((ushort)0x0c00)
473#define SCU_PSMR_FRZ ((ushort)0x0200)
474#define SCU_PSMR_RZS ((ushort)0x0100)
475#define SCU_PSMR_SYN ((ushort)0x0080)
476#define SCU_PSMR_DRT ((ushort)0x0040)
477#define SCU_PSMR_PEN ((ushort)0x0010)
478#define SCU_PSMR_RPM ((ushort)0x000c)
479#define SCU_PSMR_REVP ((ushort)0x0008)
480#define SCU_PSMR_TPM ((ushort)0x0003)
481#define SCU_PSMR_TEVP ((ushort)0x0002)
482
483/* CPM Transparent mode SCC.
484 */
485typedef struct scc_trans {
486 sccp_t st_genscc;
487 uint st_cpres; /* Preset CRC */
488 uint st_cmask; /* Constant mask for CRC */
489} scc_trans_t;
490
491/* IIC parameter RAM.
492*/
493typedef struct iic {
494 ushort iic_rbase; /* Rx Buffer descriptor base address */
495 ushort iic_tbase; /* Tx Buffer descriptor base address */
496 u_char iic_rfcr; /* Rx function code */
497 u_char iic_tfcr; /* Tx function code */
498 ushort iic_mrblr; /* Max receive buffer length */
499 uint iic_rstate; /* Internal */
500 uint iic_rdp; /* Internal */
501 ushort iic_rbptr; /* Internal */
502 ushort iic_rbc; /* Internal */
503 uint iic_rxtmp; /* Internal */
504 uint iic_tstate; /* Internal */
505 uint iic_tdp; /* Internal */
506 ushort iic_tbptr; /* Internal */
507 ushort iic_tbc; /* Internal */
508 uint iic_txtmp; /* Internal */
509 char res1[4]; /* Reserved */
510 ushort iic_rpbase; /* Relocation pointer */
511 char res2[2]; /* Reserved */
512} iic_t;
513
514/* SPI parameter RAM.
515*/
516typedef struct spi {
517 ushort spi_rbase; /* Rx Buffer descriptor base address */
518 ushort spi_tbase; /* Tx Buffer descriptor base address */
519 u_char spi_rfcr; /* Rx function code */
520 u_char spi_tfcr; /* Tx function code */
521 ushort spi_mrblr; /* Max receive buffer length */
522 uint spi_rstate; /* Internal */
523 uint spi_rdp; /* Internal */
524 ushort spi_rbptr; /* Internal */
525 ushort spi_rbc; /* Internal */
526 uint spi_rxtmp; /* Internal */
527 uint spi_tstate; /* Internal */
528 uint spi_tdp; /* Internal */
529 ushort spi_tbptr; /* Internal */
530 ushort spi_tbc; /* Internal */
531 uint spi_txtmp; /* Internal */
532 uint spi_res;
533 ushort spi_rpbase; /* Relocation pointer */
534 ushort spi_res2;
535} spi_t;
536
537/* SPI Mode register.
538*/
539#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
540#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
541#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
542#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
543#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
544#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
545#define SPMODE_EN ((ushort)0x0100) /* Enable */
546#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
547#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
548#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
549#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
550#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
551
552/* SPIE fields */
553#define SPIE_MME 0x20
554#define SPIE_TXE 0x10
555#define SPIE_BSY 0x04
556#define SPIE_TXB 0x02
557#define SPIE_RXB 0x01
558
559/*
560 * RISC Controller Configuration Register definitons
561 */
562#define RCCR_TIME 0x8000 /* RISC Timer Enable */
563#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
564#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
565
566/* RISC Timer Parameter RAM offset */
567#define PROFF_RTMR ((uint)0x01B0)
568
569typedef struct risc_timer_pram {
570 unsigned short tm_base; /* RISC Timer Table Base Address */
571 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
572 unsigned short r_tmr; /* RISC Timer Mode Register */
573 unsigned short r_tmv; /* RISC Timer Valid Register */
574 unsigned long tm_cmd; /* RISC Timer Command Register */
575 unsigned long tm_cnt; /* RISC Timer Internal Count */
576} rt_pram_t;
577
578/* Bits in RISC Timer Command Register */
579#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
580#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
581#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
582#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
583#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
584
585/* CPM interrupts. There are nearly 32 interrupts generated by CPM
586 * channels or devices. All of these are presented to the PPC core
587 * as a single interrupt. The CPM interrupt handler dispatches its
588 * own handlers, in a similar fashion to the PPC core handler. We
589 * use the table as defined in the manuals (i.e. no special high
590 * priority and SCC1 == SCCa, etc...).
591 */
592#define CPMVEC_NR 32
593#define CPMVEC_PIO_PC15 ((ushort)0x1f)
594#define CPMVEC_SCC1 ((ushort)0x1e)
595#define CPMVEC_SCC2 ((ushort)0x1d)
596#define CPMVEC_SCC3 ((ushort)0x1c)
597#define CPMVEC_SCC4 ((ushort)0x1b)
598#define CPMVEC_PIO_PC14 ((ushort)0x1a)
599#define CPMVEC_TIMER1 ((ushort)0x19)
600#define CPMVEC_PIO_PC13 ((ushort)0x18)
601#define CPMVEC_PIO_PC12 ((ushort)0x17)
602#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
603#define CPMVEC_IDMA1 ((ushort)0x15)
604#define CPMVEC_IDMA2 ((ushort)0x14)
605#define CPMVEC_TIMER2 ((ushort)0x12)
606#define CPMVEC_RISCTIMER ((ushort)0x11)
607#define CPMVEC_I2C ((ushort)0x10)
608#define CPMVEC_PIO_PC11 ((ushort)0x0f)
609#define CPMVEC_PIO_PC10 ((ushort)0x0e)
610#define CPMVEC_TIMER3 ((ushort)0x0c)
611#define CPMVEC_PIO_PC9 ((ushort)0x0b)
612#define CPMVEC_PIO_PC8 ((ushort)0x0a)
613#define CPMVEC_PIO_PC7 ((ushort)0x09)
614#define CPMVEC_TIMER4 ((ushort)0x07)
615#define CPMVEC_PIO_PC6 ((ushort)0x06)
616#define CPMVEC_SPI ((ushort)0x05)
617#define CPMVEC_SMC1 ((ushort)0x04)
618#define CPMVEC_SMC2 ((ushort)0x03)
619#define CPMVEC_PIO_PC5 ((ushort)0x02)
620#define CPMVEC_PIO_PC4 ((ushort)0x01)
621#define CPMVEC_ERROR ((ushort)0x00)
622
623/* CPM interrupt configuration vector.
624*/
625#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
626#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
627#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
628#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
629#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
630#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
631#define CICR_IEN ((uint)0x00000080) /* Int. enable */
632#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
633
634#define IMAP_ADDR (get_immrbase())
635
636#define CPM_PIN_INPUT 0
637#define CPM_PIN_OUTPUT 1
638#define CPM_PIN_PRIMARY 0
639#define CPM_PIN_SECONDARY 2
640#define CPM_PIN_GPIO 4
641#define CPM_PIN_OPENDRAIN 8
642
643enum cpm_port {
644 CPM_PORTA,
645 CPM_PORTB,
646 CPM_PORTC,
647 CPM_PORTD,
648 CPM_PORTE,
649};
650
651void cpm1_set_pin(enum cpm_port port, int pin, int flags);
652
653enum cpm_clk_dir {
654 CPM_CLK_RX,
655 CPM_CLK_TX,
656 CPM_CLK_RTX
657};
658
659enum cpm_clk_target {
660 CPM_CLK_SCC1,
661 CPM_CLK_SCC2,
662 CPM_CLK_SCC3,
663 CPM_CLK_SCC4,
664 CPM_CLK_SMC1,
665 CPM_CLK_SMC2,
666};
667
668enum cpm_clk {
669 CPM_BRG1, /* Baud Rate Generator 1 */
670 CPM_BRG2, /* Baud Rate Generator 2 */
671 CPM_BRG3, /* Baud Rate Generator 3 */
672 CPM_BRG4, /* Baud Rate Generator 4 */
673 CPM_CLK1, /* Clock 1 */
674 CPM_CLK2, /* Clock 2 */
675 CPM_CLK3, /* Clock 3 */
676 CPM_CLK4, /* Clock 4 */
677 CPM_CLK5, /* Clock 5 */
678 CPM_CLK6, /* Clock 6 */
679 CPM_CLK7, /* Clock 7 */
680 CPM_CLK8, /* Clock 8 */
681};
682
683int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
684
685#endif /* __CPM1__ */
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