diff options
Diffstat (limited to 'include/asm-powerpc/bitops.h')
-rw-r--r-- | include/asm-powerpc/bitops.h | 41 |
1 files changed, 16 insertions, 25 deletions
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h index dc25c53704d5..5727229b0444 100644 --- a/include/asm-powerpc/bitops.h +++ b/include/asm-powerpc/bitops.h | |||
@@ -40,6 +40,7 @@ | |||
40 | 40 | ||
41 | #include <linux/compiler.h> | 41 | #include <linux/compiler.h> |
42 | #include <asm/atomic.h> | 42 | #include <asm/atomic.h> |
43 | #include <asm/asm-compat.h> | ||
43 | #include <asm/synch.h> | 44 | #include <asm/synch.h> |
44 | 45 | ||
45 | /* | 46 | /* |
@@ -52,16 +53,6 @@ | |||
52 | #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) | 53 | #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) |
53 | #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) | 54 | #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) |
54 | 55 | ||
55 | #ifdef CONFIG_PPC64 | ||
56 | #define LARXL "ldarx" | ||
57 | #define STCXL "stdcx." | ||
58 | #define CNTLZL "cntlzd" | ||
59 | #else | ||
60 | #define LARXL "lwarx" | ||
61 | #define STCXL "stwcx." | ||
62 | #define CNTLZL "cntlzw" | ||
63 | #endif | ||
64 | |||
65 | static __inline__ void set_bit(int nr, volatile unsigned long *addr) | 56 | static __inline__ void set_bit(int nr, volatile unsigned long *addr) |
66 | { | 57 | { |
67 | unsigned long old; | 58 | unsigned long old; |
@@ -69,10 +60,10 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr) | |||
69 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); | 60 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); |
70 | 61 | ||
71 | __asm__ __volatile__( | 62 | __asm__ __volatile__( |
72 | "1:" LARXL " %0,0,%3 # set_bit\n" | 63 | "1:" PPC_LLARX "%0,0,%3 # set_bit\n" |
73 | "or %0,%0,%2\n" | 64 | "or %0,%0,%2\n" |
74 | PPC405_ERR77(0,%3) | 65 | PPC405_ERR77(0,%3) |
75 | STCXL " %0,0,%3\n" | 66 | PPC_STLCX "%0,0,%3\n" |
76 | "bne- 1b" | 67 | "bne- 1b" |
77 | : "=&r"(old), "=m"(*p) | 68 | : "=&r"(old), "=m"(*p) |
78 | : "r"(mask), "r"(p), "m"(*p) | 69 | : "r"(mask), "r"(p), "m"(*p) |
@@ -86,10 +77,10 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr) | |||
86 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); | 77 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); |
87 | 78 | ||
88 | __asm__ __volatile__( | 79 | __asm__ __volatile__( |
89 | "1:" LARXL " %0,0,%3 # set_bit\n" | 80 | "1:" PPC_LLARX "%0,0,%3 # clear_bit\n" |
90 | "andc %0,%0,%2\n" | 81 | "andc %0,%0,%2\n" |
91 | PPC405_ERR77(0,%3) | 82 | PPC405_ERR77(0,%3) |
92 | STCXL " %0,0,%3\n" | 83 | PPC_STLCX "%0,0,%3\n" |
93 | "bne- 1b" | 84 | "bne- 1b" |
94 | : "=&r"(old), "=m"(*p) | 85 | : "=&r"(old), "=m"(*p) |
95 | : "r"(mask), "r"(p), "m"(*p) | 86 | : "r"(mask), "r"(p), "m"(*p) |
@@ -103,10 +94,10 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr) | |||
103 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); | 94 | unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); |
104 | 95 | ||
105 | __asm__ __volatile__( | 96 | __asm__ __volatile__( |
106 | "1:" LARXL " %0,0,%3 # set_bit\n" | 97 | "1:" PPC_LLARX "%0,0,%3 # change_bit\n" |
107 | "xor %0,%0,%2\n" | 98 | "xor %0,%0,%2\n" |
108 | PPC405_ERR77(0,%3) | 99 | PPC405_ERR77(0,%3) |
109 | STCXL " %0,0,%3\n" | 100 | PPC_STLCX "%0,0,%3\n" |
110 | "bne- 1b" | 101 | "bne- 1b" |
111 | : "=&r"(old), "=m"(*p) | 102 | : "=&r"(old), "=m"(*p) |
112 | : "r"(mask), "r"(p), "m"(*p) | 103 | : "r"(mask), "r"(p), "m"(*p) |
@@ -122,10 +113,10 @@ static __inline__ int test_and_set_bit(unsigned long nr, | |||
122 | 113 | ||
123 | __asm__ __volatile__( | 114 | __asm__ __volatile__( |
124 | EIEIO_ON_SMP | 115 | EIEIO_ON_SMP |
125 | "1:" LARXL " %0,0,%3 # test_and_set_bit\n" | 116 | "1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n" |
126 | "or %1,%0,%2 \n" | 117 | "or %1,%0,%2 \n" |
127 | PPC405_ERR77(0,%3) | 118 | PPC405_ERR77(0,%3) |
128 | STCXL " %1,0,%3 \n" | 119 | PPC_STLCX "%1,0,%3 \n" |
129 | "bne- 1b" | 120 | "bne- 1b" |
130 | ISYNC_ON_SMP | 121 | ISYNC_ON_SMP |
131 | : "=&r" (old), "=&r" (t) | 122 | : "=&r" (old), "=&r" (t) |
@@ -144,10 +135,10 @@ static __inline__ int test_and_clear_bit(unsigned long nr, | |||
144 | 135 | ||
145 | __asm__ __volatile__( | 136 | __asm__ __volatile__( |
146 | EIEIO_ON_SMP | 137 | EIEIO_ON_SMP |
147 | "1:" LARXL " %0,0,%3 # test_and_clear_bit\n" | 138 | "1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n" |
148 | "andc %1,%0,%2 \n" | 139 | "andc %1,%0,%2 \n" |
149 | PPC405_ERR77(0,%3) | 140 | PPC405_ERR77(0,%3) |
150 | STCXL " %1,0,%3 \n" | 141 | PPC_STLCX "%1,0,%3 \n" |
151 | "bne- 1b" | 142 | "bne- 1b" |
152 | ISYNC_ON_SMP | 143 | ISYNC_ON_SMP |
153 | : "=&r" (old), "=&r" (t) | 144 | : "=&r" (old), "=&r" (t) |
@@ -166,10 +157,10 @@ static __inline__ int test_and_change_bit(unsigned long nr, | |||
166 | 157 | ||
167 | __asm__ __volatile__( | 158 | __asm__ __volatile__( |
168 | EIEIO_ON_SMP | 159 | EIEIO_ON_SMP |
169 | "1:" LARXL " %0,0,%3 # test_and_change_bit\n" | 160 | "1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n" |
170 | "xor %1,%0,%2 \n" | 161 | "xor %1,%0,%2 \n" |
171 | PPC405_ERR77(0,%3) | 162 | PPC405_ERR77(0,%3) |
172 | STCXL " %1,0,%3 \n" | 163 | PPC_STLCX "%1,0,%3 \n" |
173 | "bne- 1b" | 164 | "bne- 1b" |
174 | ISYNC_ON_SMP | 165 | ISYNC_ON_SMP |
175 | : "=&r" (old), "=&r" (t) | 166 | : "=&r" (old), "=&r" (t) |
@@ -184,9 +175,9 @@ static __inline__ void set_bits(unsigned long mask, unsigned long *addr) | |||
184 | unsigned long old; | 175 | unsigned long old; |
185 | 176 | ||
186 | __asm__ __volatile__( | 177 | __asm__ __volatile__( |
187 | "1:" LARXL " %0,0,%3 # set_bit\n" | 178 | "1:" PPC_LLARX "%0,0,%3 # set_bits\n" |
188 | "or %0,%0,%2\n" | 179 | "or %0,%0,%2\n" |
189 | STCXL " %0,0,%3\n" | 180 | PPC_STLCX "%0,0,%3\n" |
190 | "bne- 1b" | 181 | "bne- 1b" |
191 | : "=&r" (old), "=m" (*addr) | 182 | : "=&r" (old), "=m" (*addr) |
192 | : "r" (mask), "r" (addr), "m" (*addr) | 183 | : "r" (mask), "r" (addr), "m" (*addr) |
@@ -268,7 +259,7 @@ static __inline__ int __ilog2(unsigned long x) | |||
268 | { | 259 | { |
269 | int lz; | 260 | int lz; |
270 | 261 | ||
271 | asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x)); | 262 | asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x)); |
272 | return BITS_PER_LONG - 1 - lz; | 263 | return BITS_PER_LONG - 1 - lz; |
273 | } | 264 | } |
274 | 265 | ||