1 files changed, 241 insertions, 0 deletions
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
new file mode 100644
index 000000000000..0763c2982fb0
--- /dev/null
+++ b/include/asm-parisc/pci.h
@@ -0,0 +1,241 @@
+#ifndef __ASM_PARISC_PCI_H
+#define __ASM_PARISC_PCI_H
+#include <linux/config.h>
+#include <asm/scatterlist.h>
+/*
+** HP PCI platforms generally support multiple bus adapters.
+**    (workstations 1-~4, servers 2-~32)
+**
+** Newer platforms number the busses across PCI bus adapters *sparsely*.
+** E.g. 0, 8, 16, ...
+**
+** Under a PCI bus, most HP platforms support PPBs up to two or three
+** levels deep. See "Bit3" product line. 
+*/
+#define PCI_MAX_BUSSES  256
+/*
+** pci_hba_data (aka H2P_OBJECT in HP/UX)
+**
+** This is the "common" or "base" data structure which HBA drivers
+** (eg Dino or LBA) are required to place at the top of their own
+** platform_data structure.  I've heard this called "C inheritance" too.
+**
+** Data needed by pcibios layer belongs here.
+*/
+struct pci_hba_data {
+        void __iomem   *base_addr;      /* aka Host Physical Address */
+        const struct parisc_device *dev; /* device from PA bus walk */
+        struct pci_bus *hba_bus;        /* primary PCI bus below HBA */
+        int             hba_num;        /* I/O port space access "key" */
+        struct resource bus_num;        /* PCI bus numbers */
+        struct resource io_space;       /* PIOP */
+        struct resource lmmio_space;    /* bus addresses < 4Gb */
+        struct resource elmmio_space;   /* additional bus addresses < 4Gb */
+        struct resource gmmio_space;    /* bus addresses > 4Gb */
+        /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
+         * elmmio_space and gmmio_space as a contiguous array of
+         * resources.  This #define represents the array size */
+        #define DINO_MAX_LMMIO_RESOURCES        3
+        unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
+        void *          iommu;          /* IOMMU this device is under */
+        /* REVISIT - spinlock to protect resources? */
+        #define HBA_NAME_SIZE 16
+        char io_name[HBA_NAME_SIZE];
+        char lmmio_name[HBA_NAME_SIZE];
+        char elmmio_name[HBA_NAME_SIZE];
+        char gmmio_name[HBA_NAME_SIZE];
+};
+#define HBA_DATA(d)             ((struct pci_hba_data *) (d))
+/* 
+** We support 2^16 I/O ports per HBA.  These are set up in the form
+** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
+** space address.
+*/
+#define HBA_PORT_SPACE_BITS     16
+#define HBA_PORT_BASE(h)        ((h) << HBA_PORT_SPACE_BITS)
+#define HBA_PORT_SPACE_SIZE     (1UL << HBA_PORT_SPACE_BITS)
+#define PCI_PORT_HBA(a)         ((a) >> HBA_PORT_SPACE_BITS)
+#define PCI_PORT_ADDR(a)        ((a) & (HBA_PORT_SPACE_SIZE - 1))
+#if CONFIG_64BIT
+#define PCI_F_EXTEND            0xffffffff00000000UL
+#define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
+/* We need to know if an address is LMMMIO or GMMIO.
+ * LMMIO requires mangling and GMMIO we must use as-is.
+ */
+static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
+{
+        return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
+}
+/*
+** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
+** See pcibios.c for more conversions used by Generic PCI code.
+*/
+#define PCI_BUS_ADDR(hba,a)     (PCI_IS_LMMIO(hba,a)    \
+                ?  ((a) - hba->lmmio_space_offset)      /* mangle LMMIO */ \
+                : (a))                                  /* GMMIO */
+#define PCI_HOST_ADDR(hba,a)    ((a) + hba->lmmio_space_offset)
+#else   /* !CONFIG_64BIT */
+#define PCI_BUS_ADDR(hba,a)     (a)
+#define PCI_HOST_ADDR(hba,a)    (a)
+#define PCI_F_EXTEND            0UL
+#define PCI_IS_LMMIO(hba,a)     (1)     /* 32-bit doesn't support GMMIO */
+#endif /* !CONFIG_64BIT */
+/*
+** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
+** (This eliminates some of the warnings).
+*/
+struct pci_bus;
+struct pci_dev;
+/*
+ * If the PCI device's view of memory is the same as the CPU's view of memory,
+ * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#ifdef CONFIG_PA20
+/* All PA-2.0 machines have an IOMMU. */
+#define PCI_DMA_BUS_IS_PHYS     0
+#define parisc_has_iommu()      do { } while (0)
+#else
+#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
+extern int parisc_bus_is_phys;  /* in arch/parisc/kernel/setup.c */
+#define PCI_DMA_BUS_IS_PHYS     parisc_bus_is_phys
+#define parisc_has_iommu()      do { parisc_bus_is_phys = 0; } while (0)
+#else
+#define PCI_DMA_BUS_IS_PHYS     1
+#define parisc_has_iommu()      do { } while (0)
+#endif
+#endif  /* !CONFIG_PA20 */
+/*
+** Most PCI devices (eg Tulip, NCR720) also export the same registers
+** to both MMIO and I/O port space.  Due to poor performance of I/O Port
+** access under HP PCI bus adapters, strongly reccomend use of MMIO
+** address space.
+**
+** While I'm at it more PA programming notes:
+**
+** 1) MMIO stores (writes) are posted operations. This means the processor
+**    gets an "ACK" before the write actually gets to the device. A read
+**    to the same device (or typically the bus adapter above it) will
+**    force in-flight write transaction(s) out to the targeted device
+**    before the read can complete.
+**
+** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
+**    respect to DMA on all platforms. Ie PIO data can reach the processor
+**    before in-flight DMA reaches memory. Since most SMP PA platforms
+**    are I/O coherent, it generally doesn't matter...but sometimes
+**    it does.
+**
+** I've helped device driver writers debug both types of problems.
+*/
+struct pci_port_ops {
+          u8 (*inb)  (struct pci_hba_data *hba, u16 port);
+         u16 (*inw)  (struct pci_hba_data *hba, u16 port);
+         u32 (*inl)  (struct pci_hba_data *hba, u16 port);
+        void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
+        void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
+        void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
+};
+struct pci_bios_ops {
+        void (*init)(void);
+        void (*fixup_bus)(struct pci_bus *bus);
+};
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+/*
+** Stuff declared in arch/parisc/kernel/pci.c
+*/
+extern struct pci_port_ops *pci_port;
+extern struct pci_bios_ops *pci_bios;
+extern int pci_post_reset_delay;        /* delay after de-asserting #RESET */
+extern int pci_hba_count;
+extern struct pci_hba_data *parisc_pci_hba[];
+#ifdef CONFIG_PCI
+extern void pcibios_register_hba(struct pci_hba_data *);
+extern void pcibios_set_master(struct pci_dev *);
+#else
+extern inline void pcibios_register_hba(struct pci_hba_data *x)
+{
+}
+#endif
+/*
+ * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
+ *   0 == check if bridge is numbered before re-numbering.
+ *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
+ *
+ *   We *should* set this to zero for "legacy" platforms and one
+ *   for PAT platforms.
+ *
+ *   But legacy platforms also need to renumber the busses below a Host
+ *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
+ *   bus of a C200 resulted in the secondary bus being numbered as 1.
+ *   The second PCI host bus controller's root bus had already been
+ *   assigned bus number 1 by firmware and sysfs complained.
+ *
+ *   Firmware isn't doing anything wrong here since each controller
+ *   is its own PCI domain.  It's simpler and easier for us to renumber
+ *   the busses rather than treat each Dino as a separate PCI domain.
+ *   Eventually, we may want to introduce PCI domains for Superdome or
+ *   rp7420/8420 boxes and then revisit this issue.
+ */
+#define pcibios_assign_all_busses()     (1)
+#define pcibios_scan_all_fns(a, b)      (0)
+#define PCIBIOS_MIN_IO          0x10
+#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */
+/* Don't support DAC yet. */
+#define pci_dac_dma_supported(pci_dev, mask)   (0)
+/* export the pci_ DMA API in terms of the dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+extern void
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+                         struct resource *res);
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+#endif /* __ASM_PARISC_PCI_H */

diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h new file mode 100644 index 000000000000..0763c2982fb0 --- /dev/null +++ b/include/asm-parisc/pci.h
@@ -0,0 +1,241 @@
	1	#ifndef __ASM_PARISC_PCI_H
	2	#define __ASM_PARISC_PCI_H
	3
	4	#include <linux/config.h>
	5	#include <asm/scatterlist.h>
	6
	7
	8
	9	/*
	10	** HP PCI platforms generally support multiple bus adapters.
	11	** (workstations 1-~4, servers 2-~32)
	12	**
	13	** Newer platforms number the busses across PCI bus adapters sparsely.
	14	** E.g. 0, 8, 16, ...
	15	**
	16	** Under a PCI bus, most HP platforms support PPBs up to two or three
	17	** levels deep. See "Bit3" product line.
	18	*/
	19	#define PCI_MAX_BUSSES 256
	20
	21	/*
	22	** pci_hba_data (aka H2P_OBJECT in HP/UX)
	23	**
	24	** This is the "common" or "base" data structure which HBA drivers
	25	** (eg Dino or LBA) are required to place at the top of their own
	26	** platform_data structure. I've heard this called "C inheritance" too.
	27	**
	28	** Data needed by pcibios layer belongs here.
	29	*/
	30	struct pci_hba_data {
	31	void __iomem base_addr; / aka Host Physical Address */
	32	const struct parisc_device dev; / device from PA bus walk */
	33	struct pci_bus hba_bus; / primary PCI bus below HBA */
	34	int hba_num; /* I/O port space access "key" */
	35	struct resource bus_num; /* PCI bus numbers */
	36	struct resource io_space; /* PIOP */
	37	struct resource lmmio_space; /* bus addresses < 4Gb */
	38	struct resource elmmio_space; /* additional bus addresses < 4Gb */
	39	struct resource gmmio_space; /* bus addresses > 4Gb */
	40
	41	/* NOTE: Dino code assumes it can use all of the lmmio_space,
	42	* elmmio_space and gmmio_space as a contiguous array of
	43	* resources. This #define represents the array size */
	44	#define DINO_MAX_LMMIO_RESOURCES 3
	45
	46	unsigned long lmmio_space_offset; /* CPU view - PCI view */
	47	void * iommu; /* IOMMU this device is under */
	48	/* REVISIT - spinlock to protect resources? */
	49
	50	#define HBA_NAME_SIZE 16
	51	char io_name[HBA_NAME_SIZE];
	52	char lmmio_name[HBA_NAME_SIZE];
	53	char elmmio_name[HBA_NAME_SIZE];
	54	char gmmio_name[HBA_NAME_SIZE];
	55	};
	56
	57	#define HBA_DATA(d) ((struct pci_hba_data *) (d))
	58
	59	/*
	60	** We support 2^16 I/O ports per HBA. These are set up in the form
	61	** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
	62	** space address.
	63	*/
	64	#define HBA_PORT_SPACE_BITS 16
	65
	66	#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
	67	#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
	68
	69	#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
	70	#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
	71
	72	#if CONFIG_64BIT
	73	#define PCI_F_EXTEND 0xffffffff00000000UL
	74	#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a)
	75
	76	/* We need to know if an address is LMMMIO or GMMIO.
	77	* LMMIO requires mangling and GMMIO we must use as-is.
	78	*/
	79	static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
	80	{
	81	return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
	82	}
	83
	84	/*
	85	** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
	86	** See pcibios.c for more conversions used by Generic PCI code.
	87	*/
	88	#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \
	89	? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \
	90	: (a)) /* GMMIO */
	91	#define PCI_HOST_ADDR(hba,a) ((a) + hba->lmmio_space_offset)
	92
	93	#else /* !CONFIG_64BIT */
	94
	95	#define PCI_BUS_ADDR(hba,a) (a)
	96	#define PCI_HOST_ADDR(hba,a) (a)
	97	#define PCI_F_EXTEND 0UL
	98	#define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */
	99
	100	#endif /* !CONFIG_64BIT */
	101
	102	/*
	103	** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
	104	** (This eliminates some of the warnings).
	105	*/
	106	struct pci_bus;
	107	struct pci_dev;
	108
	109	/*
	110	* If the PCI device's view of memory is the same as the CPU's view of memory,
	111	* PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use
	112	* this boolean for bounce buffer decisions.
	113	*/
	114	#ifdef CONFIG_PA20
	115	/* All PA-2.0 machines have an IOMMU. */
	116	#define PCI_DMA_BUS_IS_PHYS 0
	117	#define parisc_has_iommu() do { } while (0)
	118	#else
	119
	120	#if defined(CONFIG_IOMMU_CCIO) \|\| defined(CONFIG_IOMMU_SBA)
	121	extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */
	122	#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys
	123	#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0)
	124	#else
	125	#define PCI_DMA_BUS_IS_PHYS 1
	126	#define parisc_has_iommu() do { } while (0)
	127	#endif
	128
	129	#endif /* !CONFIG_PA20 */
	130
	131
	132	/*
	133	** Most PCI devices (eg Tulip, NCR720) also export the same registers
	134	** to both MMIO and I/O port space. Due to poor performance of I/O Port
	135	** access under HP PCI bus adapters, strongly reccomend use of MMIO
	136	** address space.
	137	**
	138	** While I'm at it more PA programming notes:
	139	**
	140	** 1) MMIO stores (writes) are posted operations. This means the processor
	141	** gets an "ACK" before the write actually gets to the device. A read
	142	** to the same device (or typically the bus adapter above it) will
	143	** force in-flight write transaction(s) out to the targeted device
	144	** before the read can complete.
	145	**
	146	** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
	147	** respect to DMA on all platforms. Ie PIO data can reach the processor
	148	** before in-flight DMA reaches memory. Since most SMP PA platforms
	149	** are I/O coherent, it generally doesn't matter...but sometimes
	150	** it does.
	151	**
	152	** I've helped device driver writers debug both types of problems.
	153	*/
	154	struct pci_port_ops {
	155	u8 (inb) (struct pci_hba_data hba, u16 port);
	156	u16 (inw) (struct pci_hba_data hba, u16 port);
	157	u32 (inl) (struct pci_hba_data hba, u16 port);
	158	void (outb) (struct pci_hba_data hba, u16 port, u8 data);
	159	void (outw) (struct pci_hba_data hba, u16 port, u16 data);
	160	void (outl) (struct pci_hba_data hba, u16 port, u32 data);
	161	};
	162
	163
	164	struct pci_bios_ops {
	165	void (*init)(void);
	166	void (fixup_bus)(struct pci_bus bus);
	167	};
	168
	169	/* pci_unmap_{single,page} is not a nop, thus... */
	170	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
	171	dma_addr_t ADDR_NAME;
	172	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
	173	__u32 LEN_NAME;
	174	#define pci_unmap_addr(PTR, ADDR_NAME) \
	175	((PTR)->ADDR_NAME)
	176	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
	177	(((PTR)->ADDR_NAME) = (VAL))
	178	#define pci_unmap_len(PTR, LEN_NAME) \
	179	((PTR)->LEN_NAME)
	180	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
	181	(((PTR)->LEN_NAME) = (VAL))
	182
	183	/*
	184	** Stuff declared in arch/parisc/kernel/pci.c
	185	*/
	186	extern struct pci_port_ops *pci_port;
	187	extern struct pci_bios_ops *pci_bios;
	188	extern int pci_post_reset_delay; /* delay after de-asserting #RESET */
	189	extern int pci_hba_count;
	190	extern struct pci_hba_data *parisc_pci_hba[];
	191
	192	#ifdef CONFIG_PCI
	193	extern void pcibios_register_hba(struct pci_hba_data *);
	194	extern void pcibios_set_master(struct pci_dev *);
	195	#else
	196	extern inline void pcibios_register_hba(struct pci_hba_data *x)
	197	{
	198	}
	199	#endif
	200
	201	/*
	202	* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
	203	* 0 == check if bridge is numbered before re-numbering.
	204	* 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
	205	*
	206	* We should set this to zero for "legacy" platforms and one
	207	* for PAT platforms.
	208	*
	209	* But legacy platforms also need to renumber the busses below a Host
	210	* Bus controller. Adding a 4-port Tulip card on the first PCI root
	211	* bus of a C200 resulted in the secondary bus being numbered as 1.
	212	* The second PCI host bus controller's root bus had already been
	213	* assigned bus number 1 by firmware and sysfs complained.
	214	*
	215	* Firmware isn't doing anything wrong here since each controller
	216	* is its own PCI domain. It's simpler and easier for us to renumber
	217	* the busses rather than treat each Dino as a separate PCI domain.
	218	* Eventually, we may want to introduce PCI domains for Superdome or
	219	* rp7420/8420 boxes and then revisit this issue.
	220	*/
	221	#define pcibios_assign_all_busses() (1)
	222	#define pcibios_scan_all_fns(a, b) (0)
	223
	224	#define PCIBIOS_MIN_IO 0x10
	225	#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
	226
	227	/* Don't support DAC yet. */
	228	#define pci_dac_dma_supported(pci_dev, mask) (0)
	229
	230	/* export the pci_ DMA API in terms of the dma_ one */
	231	#include <asm-generic/pci-dma-compat.h>
	232
	233	extern void
	234	pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
	235	struct resource *res);
	236
	237	static inline void pcibios_add_platform_entries(struct pci_dev *dev)
	238	{
	239	}
	240
	241	#endif /* __ASM_PARISC_PCI_H */