1 files changed, 63 insertions, 8 deletions

diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
index 30b023411fef..3ce3440d1b0c 100644
--- a/include/asm-parisc/assembly.h
+++ b/include/asm-parisc/assembly.h
@@ -21,7 +21,9 @@
 #ifndef _PARISC_ASSEMBLY_H
 #define _PARISC_ASSEMBLY_H
 
-#ifdef __LP64__
+#define CALLEE_FLOAT_FRAME_SIZE 80
+
+#ifdef CONFIG_64BIT
 #define LDREG   ldd
 #define STREG   std
 #define LDREGX  ldd,s
@@ -30,8 +32,8 @@
 #define SHRREG  shrd
 #define RP_OFFSET       16
 #define FRAME_SIZE      128
-#define CALLEE_SAVE_FRAME_SIZE  144
-#else
+#define CALLEE_REG_FRAME_SIZE   144
+#else   /* CONFIG_64BIT */
 #define LDREG   ldw
 #define STREG   stw
 #define LDREGX  ldwx,s
@@ -40,9 +42,11 @@
 #define SHRREG  shr
 #define RP_OFFSET       20
 #define FRAME_SIZE      64
-#define CALLEE_SAVE_FRAME_SIZE  128
+#define CALLEE_REG_FRAME_SIZE   128
 #endif
 
+#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
+
 #ifdef CONFIG_PA20
 #define BL              b,l
 # ifdef CONFIG_64BIT
@@ -300,9 +304,35 @@
         fldd,mb -8(\regs),       %fr0
         .endm
 
+        .macro  callee_save_float
+        fstd,ma  %fr12, 8(%r30)
+        fstd,ma  %fr13, 8(%r30)
+        fstd,ma  %fr14, 8(%r30)
+        fstd,ma  %fr15, 8(%r30)
+        fstd,ma  %fr16, 8(%r30)
+        fstd,ma  %fr17, 8(%r30)
+        fstd,ma  %fr18, 8(%r30)
+        fstd,ma  %fr19, 8(%r30)
+        fstd,ma  %fr20, 8(%r30)
+        fstd,ma  %fr21, 8(%r30)
+        .endm
+
+        .macro  callee_rest_float
+        fldd,mb -8(%r30),   %fr21
+        fldd,mb -8(%r30),   %fr20
+        fldd,mb -8(%r30),   %fr19
+        fldd,mb -8(%r30),   %fr18
+        fldd,mb -8(%r30),   %fr17
+        fldd,mb -8(%r30),   %fr16
+        fldd,mb -8(%r30),   %fr15
+        fldd,mb -8(%r30),   %fr14
+        fldd,mb -8(%r30),   %fr13
+        fldd,mb -8(%r30),   %fr12
+        .endm
+
 #ifdef __LP64__
         .macro  callee_save
-        std,ma    %r3,  CALLEE_SAVE_FRAME_SIZE(%r30)
+        std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl     %cr27, %r3
         std       %r4,  -136(%r30)
         std       %r5,  -128(%r30)
@@ -340,13 +370,13 @@
         ldd     -128(%r30),    %r5
         ldd     -136(%r30),    %r4
         mtctl   %r3, %cr27
-        ldd,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),    %r3
+        ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
         .endm
 
 #else /* ! __LP64__ */
 
         .macro  callee_save
-        stw,ma   %r3,   CALLEE_SAVE_FRAME_SIZE(%r30)
+        stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
         mfctl    %cr27, %r3
         stw      %r4,   -124(%r30)
         stw      %r5,   -120(%r30)
@@ -384,7 +414,7 @@
         ldw     -120(%r30),   %r5
         ldw     -124(%r30),   %r4
         mtctl   %r3, %cr27
-        ldw,mb  -CALLEE_SAVE_FRAME_SIZE(%r30),   %r3
+        ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
         .endm
 #endif /* ! __LP64__ */
 
@@ -450,5 +480,30 @@
         REST_CR (%cr22, PT_PSW  (\regs))
         .endm
 
+
+        /* First step to create a "relied upon translation"
+         * See PA 2.0 Arch. page F-4 and F-5.
+         *
+         * The ssm was originally necessary due to a "PCxT bug".
+         * But someone decided it needed to be added to the architecture
+         * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
+         * It's been carried forward into PA 2.0 Arch as well. :^(
+         *
+         * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
+         * rsm/ssm prevents the ifetch unit from speculatively fetching
+         * instructions past this line in the code stream.
+         * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
+         */
+        .macro  pcxt_ssm_bug
+        rsm     PSW_SM_I,%r0
+        nop     /* 1 */
+        nop     /* 2 */
+        nop     /* 3 */
+        nop     /* 4 */
+        nop     /* 5 */
+        nop     /* 6 */
+        nop     /* 7 */
+        .endm
+
 #endif /* __ASSEMBLY__ */
 #endif