1 files changed, 160 insertions, 0 deletions
diff --git a/include/asm-mn10300/serial-regs.h b/include/asm-mn10300/serial-regs.h
new file mode 100644
index 000000000000..6498469e93ac
--- /dev/null
+++ b/include/asm-mn10300/serial-regs.h
@@ -0,0 +1,160 @@
+/* MN10300 on-board serial port module registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SERIAL_REGS_H
+#define _ASM_SERIAL_REGS_H
+#include <asm/cpu-regs.h>
+#include <asm/intctl-regs.h>
+#ifdef __KERNEL__
+/* serial port 0 */
+#define SC0CTR                  __SYSREG(0xd4002000, u16)       /* control reg */
+#define SC01CTR_CK              0x0007  /* clock source select */
+#define SC0CTR_CK_TM8UFLOW_8    0x0000  /* - 1/8 timer 8 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM9UFLOW_8    0x0000  /* - 1/8 timer 9 underflow (serial port 1 only) */
+#define SC01CTR_CK_IOCLK_8      0x0001  /* - 1/8 IOCLK */
+#define SC01CTR_CK_IOCLK_32     0x0002  /* - 1/32 IOCLK */
+#define SC0CTR_CK_TM2UFLOW_2    0x0003  /* - 1/2 timer 2 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM3UFLOW_2    0x0003  /* - 1/2 timer 3 underflow (serial port 1 only) */
+#define SC0CTR_CK_TM0UFLOW_8    0x0004  /* - 1/8 timer 1 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM1UFLOW_8    0x0004  /* - 1/8 timer 2 underflow (serial port 1 only) */
+#define SC0CTR_CK_TM2UFLOW_8    0x0005  /* - 1/8 timer 2 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM3UFLOW_8    0x0005  /* - 1/8 timer 3 underflow (serial port 1 only) */
+#define SC01CTR_CK_EXTERN_8     0x0006  /* - 1/8 external closk */
+#define SC01CTR_CK_EXTERN       0x0007  /* - external closk */
+#define SC01CTR_STB             0x0008  /* stop bit select */
+#define SC01CTR_STB_1BIT        0x0000  /* - 1 stop bit */
+#define SC01CTR_STB_2BIT        0x0008  /* - 2 stop bits */
+#define SC01CTR_PB              0x0070  /* parity bit select */
+#define SC01CTR_PB_NONE         0x0000  /* - no parity */
+#define SC01CTR_PB_FIXED0       0x0040  /* - fixed at 0 */
+#define SC01CTR_PB_FIXED1       0x0050  /* - fixed at 1 */
+#define SC01CTR_PB_EVEN         0x0060  /* - even parity */
+#define SC01CTR_PB_ODD          0x0070  /* - odd parity */
+#define SC01CTR_CLN             0x0080  /* character length */
+#define SC01CTR_CLN_7BIT        0x0000  /* - 7 bit chars */
+#define SC01CTR_CLN_8BIT        0x0080  /* - 8 bit chars */
+#define SC01CTR_TOE             0x0100  /* T input output enable */
+#define SC01CTR_OD              0x0200  /* bit order select */
+#define SC01CTR_OD_LSBFIRST     0x0000  /* - LSB first */
+#define SC01CTR_OD_MSBFIRST     0x0200  /* - MSB first */
+#define SC01CTR_MD              0x0c00  /* mode select */
+#define SC01CTR_MD_STST_SYNC    0x0000  /* - start-stop synchronous */
+#define SC01CTR_MD_CLOCK_SYNC1  0x0400  /* - clock synchronous 1 */
+#define SC01CTR_MD_I2C          0x0800  /* - I2C mode */
+#define SC01CTR_MD_CLOCK_SYNC2  0x0c00  /* - clock synchronous 2 */
+#define SC01CTR_IIC             0x1000  /* I2C mode select */
+#define SC01CTR_BKE             0x2000  /* break transmit enable */
+#define SC01CTR_RXE             0x4000  /* receive enable */
+#define SC01CTR_TXE             0x8000  /* transmit enable */
+#define SC0ICR                  __SYSREG(0xd4002004, u8)        /* interrupt control reg */
+#define SC01ICR_DMD             0x80    /* output data mode */
+#define SC01ICR_TD              0x20    /* transmit DMA trigger cause */
+#define SC01ICR_TI              0x10    /* transmit interrupt cause */
+#define SC01ICR_RES             0x04    /* receive error select */
+#define SC01ICR_RI              0x01    /* receive interrupt cause */
+#define SC0TXB                  __SYSREG(0xd4002008, u8)        /* transmit buffer reg */
+#define SC0RXB                  __SYSREG(0xd4002009, u8)        /* receive buffer reg */
+#define SC0STR                  __SYSREG(0xd400200c, u16)       /* status reg */
+#define SC01STR_OEF             0x0001  /* overrun error found */
+#define SC01STR_PEF             0x0002  /* parity error found */
+#define SC01STR_FEF             0x0004  /* framing error found */
+#define SC01STR_RBF             0x0010  /* receive buffer status */
+#define SC01STR_TBF             0x0020  /* transmit buffer status */
+#define SC01STR_RXF             0x0040  /* receive status */
+#define SC01STR_TXF             0x0080  /* transmit status */
+#define SC01STR_STF             0x0100  /* I2C start sequence found */
+#define SC01STR_SPF             0x0200  /* I2C stop sequence found */
+#define SC0RXIRQ                20      /* timer 0 Receive IRQ */
+#define SC0TXIRQ                21      /* timer 0 Transmit IRQ */
+#define SC0RXICR                GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
+#define SC0TXICR                GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
+/* serial port 1 */
+#define SC1CTR                  __SYSREG(0xd4002010, u16)       /* serial port 1 control */
+#define SC1ICR                  __SYSREG(0xd4002014, u8)        /* interrupt control reg */
+#define SC1TXB                  __SYSREG(0xd4002018, u8)        /* transmit buffer reg */
+#define SC1RXB                  __SYSREG(0xd4002019, u8)        /* receive buffer reg */
+#define SC1STR                  __SYSREG(0xd400201c, u16)       /* status reg */
+#define SC1RXIRQ                22      /* timer 1 Receive IRQ */
+#define SC1TXIRQ                23      /* timer 1 Transmit IRQ */
+#define SC1RXICR                GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
+#define SC1TXICR                GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
+/* serial port 2 */
+#define SC2CTR                  __SYSREG(0xd4002020, u16)       /* control reg */
+#define SC2CTR_CK               0x0003  /* clock source select */
+#define SC2CTR_CK_TM10UFLOW     0x0000  /* - timer 10 underflow */
+#define SC2CTR_CK_TM2UFLOW      0x0001  /* - timer 2 underflow */
+#define SC2CTR_CK_EXTERN        0x0002  /* - external closk */
+#define SC2CTR_CK_TM3UFLOW      0x0003  /* - timer 3 underflow */
+#define SC2CTR_STB              0x0008  /* stop bit select */
+#define SC2CTR_STB_1BIT         0x0000  /* - 1 stop bit */
+#define SC2CTR_STB_2BIT         0x0008  /* - 2 stop bits */
+#define SC2CTR_PB               0x0070  /* parity bit select */
+#define SC2CTR_PB_NONE          0x0000  /* - no parity */
+#define SC2CTR_PB_FIXED0        0x0040  /* - fixed at 0 */
+#define SC2CTR_PB_FIXED1        0x0050  /* - fixed at 1 */
+#define SC2CTR_PB_EVEN          0x0060  /* - even parity */
+#define SC2CTR_PB_ODD           0x0070  /* - odd parity */
+#define SC2CTR_CLN              0x0080  /* character length */
+#define SC2CTR_CLN_7BIT         0x0000  /* - 7 bit chars */
+#define SC2CTR_CLN_8BIT         0x0080  /* - 8 bit chars */
+#define SC2CTR_TWE              0x0100  /* transmit wait enable (enable XCTS control) */
+#define SC2CTR_OD               0x0200  /* bit order select */
+#define SC2CTR_OD_LSBFIRST      0x0000  /* - LSB first */
+#define SC2CTR_OD_MSBFIRST      0x0200  /* - MSB first */
+#define SC2CTR_TWS              0x1000  /* transmit wait select */
+#define SC2CTR_TWS_XCTS_HIGH    0x0000  /* - interrupt TX when XCTS high */
+#define SC2CTR_TWS_XCTS_LOW     0x1000  /* - interrupt TX when XCTS low */
+#define SC2CTR_BKE              0x2000  /* break transmit enable */
+#define SC2CTR_RXE              0x4000  /* receive enable */
+#define SC2CTR_TXE              0x8000  /* transmit enable */
+#define SC2ICR                  __SYSREG(0xd4002024, u8)        /* interrupt control reg */
+#define SC2ICR_TD               0x20    /* transmit DMA trigger cause */
+#define SC2ICR_TI               0x10    /* transmit interrupt cause */
+#define SC2ICR_RES              0x04    /* receive error select */
+#define SC2ICR_RI               0x01    /* receive interrupt cause */
+#define SC2TXB                  __SYSREG(0xd4002018, u8)        /* transmit buffer reg */
+#define SC2RXB                  __SYSREG(0xd4002019, u8)        /* receive buffer reg */
+#define SC2STR                  __SYSREG(0xd400201c, u8)        /* status reg */
+#define SC2STR_OEF              0x0001  /* overrun error found */
+#define SC2STR_PEF              0x0002  /* parity error found */
+#define SC2STR_FEF              0x0004  /* framing error found */
+#define SC2STR_CTS              0x0008  /* XCTS input pin status (0 means high) */
+#define SC2STR_RBF              0x0010  /* receive buffer status */
+#define SC2STR_TBF              0x0020  /* transmit buffer status */
+#define SC2STR_RXF              0x0040  /* receive status */
+#define SC2STR_TXF              0x0080  /* transmit status */
+#define SC2TIM                  __SYSREG(0xd400202d, u8)        /* status reg */
+#define SC2RXIRQ                24      /* serial 2 Receive IRQ */
+#define SC2TXIRQ                25      /* serial 2 Transmit IRQ */
+#define SC2RXICR                GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
+#define SC2TXICR                GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
+#endif /* __KERNEL__ */
+#endif /* _ASM_SERIAL_REGS_H */

diff --git a/include/asm-mn10300/serial-regs.h b/include/asm-mn10300/serial-regs.h new file mode 100644 index 000000000000..6498469e93ac --- /dev/null +++ b/include/asm-mn10300/serial-regs.h
@@ -0,0 +1,160 @@
	1	/* MN10300 on-board serial port module registers
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public Licence
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the Licence, or (at your option) any later version.
	10	*/
	11
	12	#ifndef _ASM_SERIAL_REGS_H
	13	#define _ASM_SERIAL_REGS_H
	14
	15	#include <asm/cpu-regs.h>
	16	#include <asm/intctl-regs.h>
	17
	18	#ifdef __KERNEL__
	19
	20	/* serial port 0 */
	21	#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
	22	#define SC01CTR_CK 0x0007 /* clock source select */
	23	#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
	24	#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
	25	#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
	26	#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
	27	#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
	28	#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
	29	#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */
	30	#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */
	31	#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
	32	#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
	33	#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
	34	#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
	35	#define SC01CTR_STB 0x0008 /* stop bit select */
	36	#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */
	37	#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */
	38	#define SC01CTR_PB 0x0070 /* parity bit select */
	39	#define SC01CTR_PB_NONE 0x0000 /* - no parity */
	40	#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
	41	#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
	42	#define SC01CTR_PB_EVEN 0x0060 /* - even parity */
	43	#define SC01CTR_PB_ODD 0x0070 /* - odd parity */
	44	#define SC01CTR_CLN 0x0080 /* character length */
	45	#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
	46	#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
	47	#define SC01CTR_TOE 0x0100 /* T input output enable */
	48	#define SC01CTR_OD 0x0200 /* bit order select */
	49	#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */
	50	#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */
	51	#define SC01CTR_MD 0x0c00 /* mode select */
	52	#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */
	53	#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */
	54	#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */
	55	#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */
	56	#define SC01CTR_IIC 0x1000 /* I2C mode select */
	57	#define SC01CTR_BKE 0x2000 /* break transmit enable */
	58	#define SC01CTR_RXE 0x4000 /* receive enable */
	59	#define SC01CTR_TXE 0x8000 /* transmit enable */
	60
	61	#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
	62	#define SC01ICR_DMD 0x80 /* output data mode */
	63	#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */
	64	#define SC01ICR_TI 0x10 /* transmit interrupt cause */
	65	#define SC01ICR_RES 0x04 /* receive error select */
	66	#define SC01ICR_RI 0x01 /* receive interrupt cause */
	67
	68	#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
	69	#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
	70
	71	#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
	72	#define SC01STR_OEF 0x0001 /* overrun error found */
	73	#define SC01STR_PEF 0x0002 /* parity error found */
	74	#define SC01STR_FEF 0x0004 /* framing error found */
	75	#define SC01STR_RBF 0x0010 /* receive buffer status */
	76	#define SC01STR_TBF 0x0020 /* transmit buffer status */
	77	#define SC01STR_RXF 0x0040 /* receive status */
	78	#define SC01STR_TXF 0x0080 /* transmit status */
	79	#define SC01STR_STF 0x0100 /* I2C start sequence found */
	80	#define SC01STR_SPF 0x0200 /* I2C stop sequence found */
	81
	82	#define SC0RXIRQ 20 /* timer 0 Receive IRQ */
	83	#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */
	84
	85	#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
	86	#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
	87
	88	/* serial port 1 */
	89	#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
	90	#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
	91	#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
	92	#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
	93	#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
	94
	95	#define SC1RXIRQ 22 /* timer 1 Receive IRQ */
	96	#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */
	97
	98	#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
	99	#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
	100
	101	/* serial port 2 */
	102	#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
	103	#define SC2CTR_CK 0x0003 /* clock source select */
	104	#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */
	105	#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */
	106	#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */
	107	#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */
	108	#define SC2CTR_STB 0x0008 /* stop bit select */
	109	#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */
	110	#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */
	111	#define SC2CTR_PB 0x0070 /* parity bit select */
	112	#define SC2CTR_PB_NONE 0x0000 /* - no parity */
	113	#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
	114	#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
	115	#define SC2CTR_PB_EVEN 0x0060 /* - even parity */
	116	#define SC2CTR_PB_ODD 0x0070 /* - odd parity */
	117	#define SC2CTR_CLN 0x0080 /* character length */
	118	#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
	119	#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
	120	#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */
	121	#define SC2CTR_OD 0x0200 /* bit order select */
	122	#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */
	123	#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */
	124	#define SC2CTR_TWS 0x1000 /* transmit wait select */
	125	#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */
	126	#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */
	127	#define SC2CTR_BKE 0x2000 /* break transmit enable */
	128	#define SC2CTR_RXE 0x4000 /* receive enable */
	129	#define SC2CTR_TXE 0x8000 /* transmit enable */
	130
	131	#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */
	132	#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */
	133	#define SC2ICR_TI 0x10 /* transmit interrupt cause */
	134	#define SC2ICR_RES 0x04 /* receive error select */
	135	#define SC2ICR_RI 0x01 /* receive interrupt cause */
	136
	137	#define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
	138	#define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
	139	#define SC2STR __SYSREG(0xd400201c, u8) /* status reg */
	140	#define SC2STR_OEF 0x0001 /* overrun error found */
	141	#define SC2STR_PEF 0x0002 /* parity error found */
	142	#define SC2STR_FEF 0x0004 /* framing error found */
	143	#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */
	144	#define SC2STR_RBF 0x0010 /* receive buffer status */
	145	#define SC2STR_TBF 0x0020 /* transmit buffer status */
	146	#define SC2STR_RXF 0x0040 /* receive status */
	147	#define SC2STR_TXF 0x0080 /* transmit status */
	148
	149	#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */
	150
	151	#define SC2RXIRQ 24 /* serial 2 Receive IRQ */
	152	#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */
	153
	154	#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
	155	#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
	156
	157
	158	#endif /* __KERNEL__ */
	159
	160	#endif /* _ASM_SERIAL_REGS_H */