1 files changed, 0 insertions, 86 deletions
diff --git a/include/asm-mn10300/rtc-regs.h b/include/asm-mn10300/rtc-regs.h
deleted file mode 100644
index c42deefaec11..000000000000
--- a/include/asm-mn10300/rtc-regs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* MN10300 on-chip Real-Time Clock registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_RTC_REGS_H
-#define _ASM_RTC_REGS_H
-#include <asm/intctl-regs.h>
-#ifdef __KERNEL__
-#define RTSCR                   __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
-#define RTSAR                   __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
-#define RTMCR                   __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
-#define RTMAR                   __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
-#define RTHCR                   __SYSREG(0xd8600004, u8) /* RTC hours count reg */
-#define RTHAR                   __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
-#define RTDWCR                  __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
-#define RTDMCR                  __SYSREG(0xd8600007, u8) /* RTC days count reg */
-#define RTMTCR                  __SYSREG(0xd8600008, u8) /* RTC months count reg */
-#define RTYCR                   __SYSREG(0xd8600009, u8) /* RTC years count reg */
-#define RTCRA                   __SYSREG(0xd860000a, u8)/* RTC control reg A */
-#define RTCRA_RS                0x0f    /* periodic timer interrupt cycle setting */
-#define RTCRA_RS_NONE           0x00    /* - off */
-#define RTCRA_RS_3_90625ms      0x01    /* - 3.90625ms  (1/256s) */
-#define RTCRA_RS_7_8125ms       0x02    /* - 7.8125ms   (1/128s) */
-#define RTCRA_RS_122_070us      0x03    /* - 122.070us  (1/8192s) */
-#define RTCRA_RS_244_141us      0x04    /* - 244.141us  (1/4096s) */
-#define RTCRA_RS_488_281us      0x05    /* - 488.281us  (1/2048s) */
-#define RTCRA_RS_976_5625us     0x06    /* - 976.5625us (1/1024s) */
-#define RTCRA_RS_1_953125ms     0x07    /* - 1.953125ms (1/512s) */
-#define RTCRA_RS_3_90624ms      0x08    /* - 3.90624ms  (1/256s) */
-#define RTCRA_RS_7_8125ms_b     0x09    /* - 7.8125ms   (1/128s) */
-#define RTCRA_RS_15_625ms       0x0a    /* - 15.625ms   (1/64s) */
-#define RTCRA_RS_31_25ms        0x0b    /* - 31.25ms    (1/32s) */
-#define RTCRA_RS_62_5ms         0x0c    /* - 62.5ms     (1/16s) */
-#define RTCRA_RS_125ms          0x0d    /* - 125ms      (1/8s) */
-#define RTCRA_RS_250ms          0x0e    /* - 250ms      (1/4s) */
-#define RTCRA_RS_500ms          0x0f    /* - 500ms      (1/2s) */
-#define RTCRA_DVR               0x40    /* divider reset */
-#define RTCRA_UIP               0x80    /* clock update flag */
-#define RTCRB                   __SYSREG(0xd860000b, u8) /* RTC control reg B */
-#define RTCRB_DSE               0x01    /* daylight savings time enable */
-#define RTCRB_TM                0x02    /* time format */
-#define RTCRB_TM_12HR           0x00    /* - 12 hour format */
-#define RTCRB_TM_24HR           0x02    /* - 24 hour format */
-#define RTCRB_DM                0x04    /* numeric value format */
-#define RTCRB_DM_BCD            0x00    /* - BCD */
-#define RTCRB_DM_BINARY         0x04    /* - binary */
-#define RTCRB_UIE               0x10    /* update interrupt disable */
-#define RTCRB_AIE               0x20    /* alarm interrupt disable */
-#define RTCRB_PIE               0x40    /* periodic interrupt disable */
-#define RTCRB_SET               0x80    /* clock update enable */
-#define RTSRC                   __SYSREG(0xd860000c, u8) /* RTC status reg C */
-#define RTSRC_UF                0x10    /* update end interrupt flag */
-#define RTSRC_AF                0x20    /* alarm interrupt flag */
-#define RTSRC_PF                0x40    /* periodic interrupt flag */
-#define RTSRC_IRQF              0x80    /* interrupt flag */
-#define RTIRQ                   32
-#define RTICR                   GxICR(RTIRQ)
-/*
- * MC146818 RTC compatibility defs for the MN10300 on-chip RTC
- */
-#define RTC_PORT(x)             0xd8600000
-#define RTC_ALWAYS_BCD          1       /* RTC operates in binary mode */
-#define CMOS_READ(addr)         __SYSREG(0xd8600000 + (addr), u8)
-#define CMOS_WRITE(val, addr)   \
-        do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0)
-#define RTC_IRQ                 RTIRQ
-#endif /* __KERNEL__ */
-#endif /* _ASM_RTC_REGS_H */

diff --git a/include/asm-mn10300/rtc-regs.h b/include/asm-mn10300/rtc-regs.h deleted file mode 100644 index c42deefaec11..000000000000 --- a/include/asm-mn10300/rtc-regs.h +++ /dev/null
@@ -1,86 +0,0 @@
1	/* MN10300 on-chip Real-Time Clock registers
2	*
3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4	* Written by David Howells (dhowells@redhat.com)
5	*
6	* This program is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU General Public Licence
8	* as published by the Free Software Foundation; either version
9	* 2 of the Licence, or (at your option) any later version.
10	*/
11	#ifndef _ASM_RTC_REGS_H
12	#define _ASM_RTC_REGS_H
13
14	#include <asm/intctl-regs.h>
15
16	#ifdef __KERNEL__
17
18	#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
19	#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
20	#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
21	#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
22	#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
23	#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
24	#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
25	#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
26	#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
27	#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */
28
29	#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */
30	#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */
31	#define RTCRA_RS_NONE 0x00 /* - off */
32	#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */
33	#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */
34	#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */
35	#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */
36	#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */
37	#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */
38	#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */
39	#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */
40	#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */
41	#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */
42	#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */
43	#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */
44	#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */
45	#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */
46	#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */
47	#define RTCRA_DVR 0x40 /* divider reset */
48	#define RTCRA_UIP 0x80 /* clock update flag */
49
50	#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */
51	#define RTCRB_DSE 0x01 /* daylight savings time enable */
52	#define RTCRB_TM 0x02 /* time format */
53	#define RTCRB_TM_12HR 0x00 /* - 12 hour format */
54	#define RTCRB_TM_24HR 0x02 /* - 24 hour format */
55	#define RTCRB_DM 0x04 /* numeric value format */
56	#define RTCRB_DM_BCD 0x00 /* - BCD */
57	#define RTCRB_DM_BINARY 0x04 /* - binary */
58	#define RTCRB_UIE 0x10 /* update interrupt disable */
59	#define RTCRB_AIE 0x20 /* alarm interrupt disable */
60	#define RTCRB_PIE 0x40 /* periodic interrupt disable */
61	#define RTCRB_SET 0x80 /* clock update enable */
62
63	#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */
64	#define RTSRC_UF 0x10 /* update end interrupt flag */
65	#define RTSRC_AF 0x20 /* alarm interrupt flag */
66	#define RTSRC_PF 0x40 /* periodic interrupt flag */
67	#define RTSRC_IRQF 0x80 /* interrupt flag */
68
69	#define RTIRQ 32
70	#define RTICR GxICR(RTIRQ)
71
72	/*
73	* MC146818 RTC compatibility defs for the MN10300 on-chip RTC
74	*/
75	#define RTC_PORT(x) 0xd8600000
76	#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
77
78	#define CMOS_READ(addr) __SYSREG(0xd8600000 + (addr), u8)
79	#define CMOS_WRITE(val, addr) \
80	do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0)
81
82	#define RTC_IRQ RTIRQ
83
84	#endif /* __KERNEL__ */
85
86	#endif /* _ASM_RTC_REGS_H */