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-rw-r--r--include/asm-mips/asmmacro-32.h2
-rw-r--r--include/asm-mips/asmmacro-64.h2
-rw-r--r--include/asm-mips/irq.h3
-rw-r--r--include/asm-mips/sim.h2
-rw-r--r--include/asm-mips/spinlock.h75
-rw-r--r--include/asm-mips/spinlock_types.h20
-rw-r--r--include/asm-mips/stackframe.h2
-rw-r--r--include/asm-mips/vr41xx/tb0287.h43
8 files changed, 94 insertions, 55 deletions
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
index ac8823df2554..11daf5ceb7b4 100644
--- a/include/asm-mips/asmmacro-32.h
+++ b/include/asm-mips/asmmacro-32.h
@@ -7,7 +7,7 @@
7#ifndef _ASM_ASMMACRO_32_H 7#ifndef _ASM_ASMMACRO_32_H
8#define _ASM_ASMMACRO_32_H 8#define _ASM_ASMMACRO_32_H
9 9
10#include <asm/offset.h> 10#include <asm/asm-offsets.h>
11#include <asm/regdef.h> 11#include <asm/regdef.h>
12#include <asm/fpregdef.h> 12#include <asm/fpregdef.h>
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
index bbed35511f5a..559c355b9b86 100644
--- a/include/asm-mips/asmmacro-64.h
+++ b/include/asm-mips/asmmacro-64.h
@@ -8,7 +8,7 @@
8#ifndef _ASM_ASMMACRO_64_H 8#ifndef _ASM_ASMMACRO_64_H
9#define _ASM_ASMMACRO_64_H 9#define _ASM_ASMMACRO_64_H
10 10
11#include <asm/offset.h> 11#include <asm/asm-offsets.h>
12#include <asm/regdef.h> 12#include <asm/regdef.h>
13#include <asm/fpregdef.h> 13#include <asm/fpregdef.h>
14#include <asm/mipsregs.h> 14#include <asm/mipsregs.h>
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index b90b11d0b886..3f2470e9e678 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -49,7 +49,4 @@ do { \
49 49
50extern void arch_init_irq(void); 50extern void arch_init_irq(void);
51 51
52struct irqaction;
53int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
54
55#endif /* _ASM_IRQ_H */ 52#endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 3ccfe09fa744..9c2af1b00e19 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -11,7 +11,7 @@
11 11
12#include <linux/config.h> 12#include <linux/config.h>
13 13
14#include <asm/offset.h> 14#include <asm/asm-offsets.h>
15 15
16#define __str2(x) #x 16#define __str2(x) #x
17#define __str(x) __str2(x) 17#define __str(x) __str2(x)
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 114d3eb98a6a..4d0135b11156 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -16,20 +16,10 @@
16 * Your basic SMP spinlocks, allowing only a single CPU anywhere 16 * Your basic SMP spinlocks, allowing only a single CPU anywhere
17 */ 17 */
18 18
19typedef struct { 19#define __raw_spin_is_locked(x) ((x)->lock != 0)
20 volatile unsigned int lock; 20#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
21#ifdef CONFIG_PREEMPT 21#define __raw_spin_unlock_wait(x) \
22 unsigned int break_lock; 22 do { cpu_relax(); } while ((x)->lock)
23#endif
24} spinlock_t;
25
26#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
27
28#define spin_lock_init(x) do { (x)->lock = 0; } while(0)
29
30#define spin_is_locked(x) ((x)->lock != 0)
31#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
32#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
33 23
34/* 24/*
35 * Simple spin lock operations. There are two variants, one clears IRQ's 25 * Simple spin lock operations. There are two variants, one clears IRQ's
@@ -38,13 +28,13 @@ typedef struct {
38 * We make no fairness assumptions. They have a cost. 28 * We make no fairness assumptions. They have a cost.
39 */ 29 */
40 30
41static inline void _raw_spin_lock(spinlock_t *lock) 31static inline void __raw_spin_lock(raw_spinlock_t *lock)
42{ 32{
43 unsigned int tmp; 33 unsigned int tmp;
44 34
45 if (R10000_LLSC_WAR) { 35 if (R10000_LLSC_WAR) {
46 __asm__ __volatile__( 36 __asm__ __volatile__(
47 " .set noreorder # _raw_spin_lock \n" 37 " .set noreorder # __raw_spin_lock \n"
48 "1: ll %1, %2 \n" 38 "1: ll %1, %2 \n"
49 " bnez %1, 1b \n" 39 " bnez %1, 1b \n"
50 " li %1, 1 \n" 40 " li %1, 1 \n"
@@ -58,7 +48,7 @@ static inline void _raw_spin_lock(spinlock_t *lock)
58 : "memory"); 48 : "memory");
59 } else { 49 } else {
60 __asm__ __volatile__( 50 __asm__ __volatile__(
61 " .set noreorder # _raw_spin_lock \n" 51 " .set noreorder # __raw_spin_lock \n"
62 "1: ll %1, %2 \n" 52 "1: ll %1, %2 \n"
63 " bnez %1, 1b \n" 53 " bnez %1, 1b \n"
64 " li %1, 1 \n" 54 " li %1, 1 \n"
@@ -72,10 +62,10 @@ static inline void _raw_spin_lock(spinlock_t *lock)
72 } 62 }
73} 63}
74 64
75static inline void _raw_spin_unlock(spinlock_t *lock) 65static inline void __raw_spin_unlock(raw_spinlock_t *lock)
76{ 66{
77 __asm__ __volatile__( 67 __asm__ __volatile__(
78 " .set noreorder # _raw_spin_unlock \n" 68 " .set noreorder # __raw_spin_unlock \n"
79 " sync \n" 69 " sync \n"
80 " sw $0, %0 \n" 70 " sw $0, %0 \n"
81 " .set\treorder \n" 71 " .set\treorder \n"
@@ -84,13 +74,13 @@ static inline void _raw_spin_unlock(spinlock_t *lock)
84 : "memory"); 74 : "memory");
85} 75}
86 76
87static inline unsigned int _raw_spin_trylock(spinlock_t *lock) 77static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
88{ 78{
89 unsigned int temp, res; 79 unsigned int temp, res;
90 80
91 if (R10000_LLSC_WAR) { 81 if (R10000_LLSC_WAR) {
92 __asm__ __volatile__( 82 __asm__ __volatile__(
93 " .set noreorder # _raw_spin_trylock \n" 83 " .set noreorder # __raw_spin_trylock \n"
94 "1: ll %0, %3 \n" 84 "1: ll %0, %3 \n"
95 " ori %2, %0, 1 \n" 85 " ori %2, %0, 1 \n"
96 " sc %2, %1 \n" 86 " sc %2, %1 \n"
@@ -104,7 +94,7 @@ static inline unsigned int _raw_spin_trylock(spinlock_t *lock)
104 : "memory"); 94 : "memory");
105 } else { 95 } else {
106 __asm__ __volatile__( 96 __asm__ __volatile__(
107 " .set noreorder # _raw_spin_trylock \n" 97 " .set noreorder # __raw_spin_trylock \n"
108 "1: ll %0, %3 \n" 98 "1: ll %0, %3 \n"
109 " ori %2, %0, 1 \n" 99 " ori %2, %0, 1 \n"
110 " sc %2, %1 \n" 100 " sc %2, %1 \n"
@@ -129,24 +119,13 @@ static inline unsigned int _raw_spin_trylock(spinlock_t *lock)
129 * read-locks. 119 * read-locks.
130 */ 120 */
131 121
132typedef struct { 122static inline void __raw_read_lock(raw_rwlock_t *rw)
133 volatile unsigned int lock;
134#ifdef CONFIG_PREEMPT
135 unsigned int break_lock;
136#endif
137} rwlock_t;
138
139#define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
140
141#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
142
143static inline void _raw_read_lock(rwlock_t *rw)
144{ 123{
145 unsigned int tmp; 124 unsigned int tmp;
146 125
147 if (R10000_LLSC_WAR) { 126 if (R10000_LLSC_WAR) {
148 __asm__ __volatile__( 127 __asm__ __volatile__(
149 " .set noreorder # _raw_read_lock \n" 128 " .set noreorder # __raw_read_lock \n"
150 "1: ll %1, %2 \n" 129 "1: ll %1, %2 \n"
151 " bltz %1, 1b \n" 130 " bltz %1, 1b \n"
152 " addu %1, 1 \n" 131 " addu %1, 1 \n"
@@ -160,7 +139,7 @@ static inline void _raw_read_lock(rwlock_t *rw)
160 : "memory"); 139 : "memory");
161 } else { 140 } else {
162 __asm__ __volatile__( 141 __asm__ __volatile__(
163 " .set noreorder # _raw_read_lock \n" 142 " .set noreorder # __raw_read_lock \n"
164 "1: ll %1, %2 \n" 143 "1: ll %1, %2 \n"
165 " bltz %1, 1b \n" 144 " bltz %1, 1b \n"
166 " addu %1, 1 \n" 145 " addu %1, 1 \n"
@@ -177,13 +156,13 @@ static inline void _raw_read_lock(rwlock_t *rw)
177/* Note the use of sub, not subu which will make the kernel die with an 156/* Note the use of sub, not subu which will make the kernel die with an
178 overflow exception if we ever try to unlock an rwlock that is already 157 overflow exception if we ever try to unlock an rwlock that is already
179 unlocked or is being held by a writer. */ 158 unlocked or is being held by a writer. */
180static inline void _raw_read_unlock(rwlock_t *rw) 159static inline void __raw_read_unlock(raw_rwlock_t *rw)
181{ 160{
182 unsigned int tmp; 161 unsigned int tmp;
183 162
184 if (R10000_LLSC_WAR) { 163 if (R10000_LLSC_WAR) {
185 __asm__ __volatile__( 164 __asm__ __volatile__(
186 "1: ll %1, %2 # _raw_read_unlock \n" 165 "1: ll %1, %2 # __raw_read_unlock \n"
187 " sub %1, 1 \n" 166 " sub %1, 1 \n"
188 " sc %1, %0 \n" 167 " sc %1, %0 \n"
189 " beqzl %1, 1b \n" 168 " beqzl %1, 1b \n"
@@ -193,7 +172,7 @@ static inline void _raw_read_unlock(rwlock_t *rw)
193 : "memory"); 172 : "memory");
194 } else { 173 } else {
195 __asm__ __volatile__( 174 __asm__ __volatile__(
196 " .set noreorder # _raw_read_unlock \n" 175 " .set noreorder # __raw_read_unlock \n"
197 "1: ll %1, %2 \n" 176 "1: ll %1, %2 \n"
198 " sub %1, 1 \n" 177 " sub %1, 1 \n"
199 " sc %1, %0 \n" 178 " sc %1, %0 \n"
@@ -206,13 +185,13 @@ static inline void _raw_read_unlock(rwlock_t *rw)
206 } 185 }
207} 186}
208 187
209static inline void _raw_write_lock(rwlock_t *rw) 188static inline void __raw_write_lock(raw_rwlock_t *rw)
210{ 189{
211 unsigned int tmp; 190 unsigned int tmp;
212 191
213 if (R10000_LLSC_WAR) { 192 if (R10000_LLSC_WAR) {
214 __asm__ __volatile__( 193 __asm__ __volatile__(
215 " .set noreorder # _raw_write_lock \n" 194 " .set noreorder # __raw_write_lock \n"
216 "1: ll %1, %2 \n" 195 "1: ll %1, %2 \n"
217 " bnez %1, 1b \n" 196 " bnez %1, 1b \n"
218 " lui %1, 0x8000 \n" 197 " lui %1, 0x8000 \n"
@@ -226,7 +205,7 @@ static inline void _raw_write_lock(rwlock_t *rw)
226 : "memory"); 205 : "memory");
227 } else { 206 } else {
228 __asm__ __volatile__( 207 __asm__ __volatile__(
229 " .set noreorder # _raw_write_lock \n" 208 " .set noreorder # __raw_write_lock \n"
230 "1: ll %1, %2 \n" 209 "1: ll %1, %2 \n"
231 " bnez %1, 1b \n" 210 " bnez %1, 1b \n"
232 " lui %1, 0x8000 \n" 211 " lui %1, 0x8000 \n"
@@ -241,26 +220,26 @@ static inline void _raw_write_lock(rwlock_t *rw)
241 } 220 }
242} 221}
243 222
244static inline void _raw_write_unlock(rwlock_t *rw) 223static inline void __raw_write_unlock(raw_rwlock_t *rw)
245{ 224{
246 __asm__ __volatile__( 225 __asm__ __volatile__(
247 " sync # _raw_write_unlock \n" 226 " sync # __raw_write_unlock \n"
248 " sw $0, %0 \n" 227 " sw $0, %0 \n"
249 : "=m" (rw->lock) 228 : "=m" (rw->lock)
250 : "m" (rw->lock) 229 : "m" (rw->lock)
251 : "memory"); 230 : "memory");
252} 231}
253 232
254#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) 233#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
255 234
256static inline int _raw_write_trylock(rwlock_t *rw) 235static inline int __raw_write_trylock(raw_rwlock_t *rw)
257{ 236{
258 unsigned int tmp; 237 unsigned int tmp;
259 int ret; 238 int ret;
260 239
261 if (R10000_LLSC_WAR) { 240 if (R10000_LLSC_WAR) {
262 __asm__ __volatile__( 241 __asm__ __volatile__(
263 " .set noreorder # _raw_write_trylock \n" 242 " .set noreorder # __raw_write_trylock \n"
264 " li %2, 0 \n" 243 " li %2, 0 \n"
265 "1: ll %1, %3 \n" 244 "1: ll %1, %3 \n"
266 " bnez %1, 2f \n" 245 " bnez %1, 2f \n"
@@ -277,7 +256,7 @@ static inline int _raw_write_trylock(rwlock_t *rw)
277 : "memory"); 256 : "memory");
278 } else { 257 } else {
279 __asm__ __volatile__( 258 __asm__ __volatile__(
280 " .set noreorder # _raw_write_trylock \n" 259 " .set noreorder # __raw_write_trylock \n"
281 " li %2, 0 \n" 260 " li %2, 0 \n"
282 "1: ll %1, %3 \n" 261 "1: ll %1, %3 \n"
283 " bnez %1, 2f \n" 262 " bnez %1, 2f \n"
diff --git a/include/asm-mips/spinlock_types.h b/include/asm-mips/spinlock_types.h
new file mode 100644
index 000000000000..ce26c5048b15
--- /dev/null
+++ b/include/asm-mips/spinlock_types.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_SPINLOCK_TYPES_H
2#define _ASM_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile unsigned int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index fb42f99f8527..7b5e64600bc8 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -15,7 +15,7 @@
15 15
16#include <asm/asm.h> 16#include <asm/asm.h>
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/offset.h> 18#include <asm/asm-offsets.h>
19 19
20 .macro SAVE_AT 20 .macro SAVE_AT
21 .set push 21 .set push
diff --git a/include/asm-mips/vr41xx/tb0287.h b/include/asm-mips/vr41xx/tb0287.h
new file mode 100644
index 000000000000..dd9832313afe
--- /dev/null
+++ b/include/asm-mips/vr41xx/tb0287.h
@@ -0,0 +1,43 @@
1/*
2 * tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
3 *
4 * Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp>
5 *
6 * This code is largely based on tb0219.h.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __TANBAC_TB0287_H
23#define __TANBAC_TB0287_H
24
25#include <asm/vr41xx/vr41xx.h>
26
27/*
28 * General-Purpose I/O Pin Number
29 */
30#define TB0287_PCI_SLOT_PIN 2
31#define TB0287_SM501_PIN 3
32#define TB0287_SIL680A_PIN 8
33#define TB0287_RTL8110_PIN 13
34
35/*
36 * Interrupt Number
37 */
38#define TB0287_PCI_SLOT_IRQ GIU_IRQ(TB0287_PCI_SLOT_PIN)
39#define TB0287_SM501_IRQ GIU_IRQ(TB0287_SM501_PIN)
40#define TB0287_SIL680A_IRQ GIU_IRQ(TB0287_SIL680A_PIN)
41#define TB0287_RTL8110_IRQ GIU_IRQ(TB0287_RTL8110_PIN)
42
43#endif /* __TANBAC_TB0287_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-09 05:23:51 -0500