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-rw-r--r--include/asm-mips/atomic.h12
-rw-r--r--include/asm-mips/cpu-features.h3
-rw-r--r--include/asm-mips/cpu-info.h1
-rw-r--r--include/asm-mips/hazards.h180
-rw-r--r--include/asm-mips/io.h36
-rw-r--r--include/asm-mips/r4kcache.h3
-rw-r--r--include/asm-mips/sibyte/sb1250.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h5
-rw-r--r--include/asm-mips/smp.h11
-rw-r--r--include/asm-mips/system.h8
-rw-r--r--include/asm-mips/vga.h3
11 files changed, 174 insertions, 90 deletions
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 654b97d3e13a..2c8b853376c9 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -250,7 +250,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
250 " subu %0, %1, %3 \n" 250 " subu %0, %1, %3 \n"
251 " bltz %0, 1f \n" 251 " bltz %0, 1f \n"
252 " sc %0, %2 \n" 252 " sc %0, %2 \n"
253 " .set noreorder \n"
253 " beqzl %0, 1b \n" 254 " beqzl %0, 1b \n"
255 " subu %0, %1, %3 \n"
256 " .set reorder \n"
254 " sync \n" 257 " sync \n"
255 "1: \n" 258 "1: \n"
256 " .set mips0 \n" 259 " .set mips0 \n"
@@ -266,7 +269,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
266 " subu %0, %1, %3 \n" 269 " subu %0, %1, %3 \n"
267 " bltz %0, 1f \n" 270 " bltz %0, 1f \n"
268 " sc %0, %2 \n" 271 " sc %0, %2 \n"
272 " .set noreorder \n"
269 " beqz %0, 1b \n" 273 " beqz %0, 1b \n"
274 " subu %0, %1, %3 \n"
275 " .set reorder \n"
270 " sync \n" 276 " sync \n"
271 "1: \n" 277 "1: \n"
272 " .set mips0 \n" 278 " .set mips0 \n"
@@ -598,7 +604,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
598 " dsubu %0, %1, %3 \n" 604 " dsubu %0, %1, %3 \n"
599 " bltz %0, 1f \n" 605 " bltz %0, 1f \n"
600 " scd %0, %2 \n" 606 " scd %0, %2 \n"
607 " .set noreorder \n"
601 " beqzl %0, 1b \n" 608 " beqzl %0, 1b \n"
609 " dsubu %0, %1, %3 \n"
610 " .set reorder \n"
602 " sync \n" 611 " sync \n"
603 "1: \n" 612 "1: \n"
604 " .set mips0 \n" 613 " .set mips0 \n"
@@ -614,7 +623,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
614 " dsubu %0, %1, %3 \n" 623 " dsubu %0, %1, %3 \n"
615 " bltz %0, 1f \n" 624 " bltz %0, 1f \n"
616 " scd %0, %2 \n" 625 " scd %0, %2 \n"
626 " .set noreorder \n"
617 " beqz %0, 1b \n" 627 " beqz %0, 1b \n"
628 " dsubu %0, %1, %3 \n"
629 " .set reorder \n"
618 " sync \n" 630 " sync \n"
619 "1: \n" 631 "1: \n"
620 " .set mips0 \n" 632 " .set mips0 \n"
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 78c9cc2735d5..3f2b6d9ac45e 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -96,6 +96,9 @@
96#ifndef cpu_has_ic_fills_f_dc 96#ifndef cpu_has_ic_fills_f_dc
97#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 97#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
98#endif 98#endif
99#ifndef cpu_has_pindexed_dcache
100#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
101#endif
99 102
100/* 103/*
101 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 104 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index d5cf519f8fcc..140be1c67da7 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -39,6 +39,7 @@ struct cache_desc {
39#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ 39#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
40#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ 40#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
41#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ 41#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
42#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42 43
43struct cpuinfo_mips { 44struct cpuinfo_mips {
44 unsigned long udelay_val; 45 unsigned long udelay_val;
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 6111a0ce58c4..feb29a793888 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -3,7 +3,9 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle 6 * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
7 */ 9 */
8#ifndef _ASM_HAZARDS_H 10#ifndef _ASM_HAZARDS_H
9#define _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H
@@ -74,8 +76,7 @@
74#define irq_disable_hazard 76#define irq_disable_hazard
75 _ehb 77 _ehb
76 78
77#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ 79#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
78 defined(CONFIG_CPU_SB1)
79 80
80/* 81/*
81 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 82 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -99,13 +100,13 @@
99#else /* __ASSEMBLY__ */ 100#else /* __ASSEMBLY__ */
100 101
101__asm__( 102__asm__(
102 " .macro _ssnop \n\t" 103 " .macro _ssnop \n"
103 " sll $0, $0, 1 \n\t" 104 " sll $0, $0, 1 \n"
104 " .endm \n\t" 105 " .endm \n"
105 " \n\t" 106 " \n"
106 " .macro _ehb \n\t" 107 " .macro _ehb \n"
107 " sll $0, $0, 3 \n\t" 108 " sll $0, $0, 3 \n"
108 " .endm \n\t"); 109 " .endm \n");
109 110
110#ifdef CONFIG_CPU_RM9000 111#ifdef CONFIG_CPU_RM9000
111 112
@@ -117,17 +118,21 @@ __asm__(
117 118
118#define mtc0_tlbw_hazard() \ 119#define mtc0_tlbw_hazard() \
119 __asm__ __volatile__( \ 120 __asm__ __volatile__( \
120 ".set\tmips32\n\t" \ 121 " .set mips32 \n" \
121 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ 122 " _ssnop \n" \
122 ".set\tmips0") 123 " _ssnop \n" \
124 " _ssnop \n" \
125 " _ssnop \n" \
126 " .set mips0 \n")
123 127
124#define tlbw_use_hazard() \ 128#define tlbw_use_hazard() \
125 __asm__ __volatile__( \ 129 __asm__ __volatile__( \
126 ".set\tmips32\n\t" \ 130 " .set mips32 \n" \
127 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ 131 " _ssnop \n" \
128 ".set\tmips0") 132 " _ssnop \n" \
129 133 " _ssnop \n" \
130#define back_to_back_c0_hazard() do { } while (0) 134 " _ssnop \n" \
135 " .set mips0 \n")
131 136
132#else 137#else
133 138
@@ -136,15 +141,25 @@ __asm__(
136 */ 141 */
137#define mtc0_tlbw_hazard() \ 142#define mtc0_tlbw_hazard() \
138 __asm__ __volatile__( \ 143 __asm__ __volatile__( \
139 ".set noreorder\n\t" \ 144 " .set noreorder \n" \
140 "nop; nop; nop; nop; nop; nop;\n\t" \ 145 " nop \n" \
141 ".set reorder\n\t") 146 " nop \n" \
147 " nop \n" \
148 " nop \n" \
149 " nop \n" \
150 " nop \n" \
151 " .set reorder \n")
142 152
143#define tlbw_use_hazard() \ 153#define tlbw_use_hazard() \
144 __asm__ __volatile__( \ 154 __asm__ __volatile__( \
145 ".set noreorder\n\t" \ 155 " .set noreorder \n" \
146 "nop; nop; nop; nop; nop; nop;\n\t" \ 156 " nop \n" \
147 ".set reorder\n\t") 157 " nop \n" \
158 " nop \n" \
159 " nop \n" \
160 " nop \n" \
161 " nop \n" \
162 " .set reorder \n")
148 163
149#endif 164#endif
150 165
@@ -156,49 +171,26 @@ __asm__(
156 171
157#ifdef CONFIG_CPU_MIPSR2 172#ifdef CONFIG_CPU_MIPSR2
158 173
159__asm__( 174__asm__(" .macro irq_enable_hazard \n"
160 " .macro\tirq_enable_hazard \n\t" 175 " _ehb \n"
161 " _ehb \n\t" 176 " .endm \n"
162 " .endm \n\t" 177 " \n"
163 " \n\t" 178 " .macro irq_disable_hazard \n"
164 " .macro\tirq_disable_hazard \n\t" 179 " _ehb \n"
165 " _ehb \n\t" 180 " .endm \n");
166 " .endm \n\t"
167 " \n\t"
168 " .macro\tback_to_back_c0_hazard \n\t"
169 " _ehb \n\t"
170 " .endm");
171
172#define irq_enable_hazard() \
173 __asm__ __volatile__( \
174 "irq_enable_hazard")
175 181
176#define irq_disable_hazard() \ 182#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
177 __asm__ __volatile__( \
178 "irq_disable_hazard")
179
180#define back_to_back_c0_hazard() \
181 __asm__ __volatile__( \
182 "back_to_back_c0_hazard")
183
184#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
185 defined(CONFIG_CPU_SB1)
186 183
187/* 184/*
188 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 185 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
189 */ 186 */
190 187
191__asm__( 188__asm__(
192 " .macro\tirq_enable_hazard \n\t" 189 " .macro irq_enable_hazard \n"
193 " .endm \n\t" 190 " .endm \n"
194 " \n\t" 191 " \n"
195 " .macro\tirq_disable_hazard \n\t" 192 " .macro irq_disable_hazard \n"
196 " .endm"); 193 " .endm \n");
197
198#define irq_enable_hazard() do { } while (0)
199#define irq_disable_hazard() do { } while (0)
200
201#define back_to_back_c0_hazard() do { } while (0)
202 194
203#else 195#else
204 196
@@ -209,29 +201,63 @@ __asm__(
209 */ 201 */
210 202
211__asm__( 203__asm__(
212 " # \n\t" 204 " # \n"
213 " # There is a hazard but we do not care \n\t" 205 " # There is a hazard but we do not care \n"
214 " # \n\t" 206 " # \n"
215 " .macro\tirq_enable_hazard \n\t" 207 " .macro\tirq_enable_hazard \n"
216 " .endm \n\t" 208 " .endm \n"
217 " \n\t" 209 " \n"
218 " .macro\tirq_disable_hazard \n\t" 210 " .macro\tirq_disable_hazard \n"
219 " _ssnop; _ssnop; _ssnop \n\t" 211 " _ssnop \n"
220 " .endm"); 212 " _ssnop \n"
213 " _ssnop \n"
214 " .endm \n");
221 215
222#define irq_enable_hazard() do { } while (0) 216#endif
217
218#define irq_enable_hazard() \
219 __asm__ __volatile__("irq_enable_hazard")
223#define irq_disable_hazard() \ 220#define irq_disable_hazard() \
224 __asm__ __volatile__( \ 221 __asm__ __volatile__("irq_disable_hazard")
225 "irq_disable_hazard")
226 222
227#define back_to_back_c0_hazard() \ 223
228 __asm__ __volatile__( \ 224/*
229 " .set noreorder \n" \ 225 * Back-to-back hazards -
230 " nop; nop; nop \n" \ 226 *
231 " .set reorder \n") 227 * What is needed to separate a move to cp0 from a subsequent read from the
228 * same cp0 register?
229 */
230#ifdef CONFIG_CPU_MIPSR2
231
232__asm__(" .macro back_to_back_c0_hazard \n"
233 " _ehb \n"
234 " .endm \n");
235
236#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
237 defined(CONFIG_CPU_SB1)
238
239__asm__(" .macro back_to_back_c0_hazard \n"
240 " .endm \n");
241
242#else
243
244__asm__(" .macro back_to_back_c0_hazard \n"
245 " .set noreorder \n"
246 " _ssnop \n"
247 " _ssnop \n"
248 " _ssnop \n"
249 " .set reorder \n"
250 " .endm");
232 251
233#endif 252#endif
234 253
254#define back_to_back_c0_hazard() \
255 __asm__ __volatile__("back_to_back_c0_hazard")
256
257
258/*
259 * Instruction execution hazard
260 */
235#ifdef CONFIG_CPU_MIPSR2 261#ifdef CONFIG_CPU_MIPSR2
236/* 262/*
237 * gcc has a tradition of misscompiling the previous construct using the 263 * gcc has a tradition of misscompiling the previous construct using the
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 5a4c8a54b8f4..ba1d7bbc15d2 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH 6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com> 10 * Author: Maciej W. Rozycki <macro@mips.com>
@@ -103,8 +103,20 @@
103 */ 103 */
104extern const unsigned long mips_io_port_base; 104extern const unsigned long mips_io_port_base;
105 105
106#define set_io_port_base(base) \ 106/*
107 do { * (unsigned long *) &mips_io_port_base = (base); } while (0) 107 * Gcc will generate code to load the value of mips_io_port_base after each
108 * function call which may be fairly wasteful in some cases. So we don't
109 * play quite by the book. We tell gcc mips_io_port_base is a long variable
110 * which solves the code generation issue. Now we need to violate the
111 * aliasing rules a little to make initialization possible and finally we
112 * will need the barrier() to fight side effects of the aliasing chat.
113 * This trickery will eventually collapse under gcc's optimizer. Oh well.
114 */
115static inline void set_io_port_base(unsigned long base)
116{
117 * (unsigned long *) &mips_io_port_base = base;
118 barrier();
119}
108 120
109/* 121/*
110 * Thanks to James van Artsdalen for a better timing-fix than 122 * Thanks to James van Artsdalen for a better timing-fix than
@@ -283,6 +295,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
283 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 295 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
284 296
285/* 297/*
298 * ioremap_cachable - map bus memory into CPU space
299 * @offset: bus address of the memory
300 * @size: size of the resource to map
301 *
302 * ioremap_nocache performs a platform specific sequence of operations to
303 * make bus memory CPU accessible via the readb/readw/readl/writeb/
304 * writew/writel functions and the other mmio helpers. The returned
305 * address is not guaranteed to be usable directly as a virtual
306 * address.
307 *
308 * This version of ioremap ensures that the memory is marked cachable by
309 * the CPU. Also enables full write-combining. Useful for some
310 * memory-like regions on I/O busses.
311 */
312#define ioremap_cachable(offset, size) \
313 __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
314
315/*
286 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 316 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
287 * requests a cachable mapping, ioremap_uncached_accelerated requests a 317 * requests a cachable mapping, ioremap_uncached_accelerated requests a
288 * mapping using the uncached accelerated mode which isn't supported on 318 * mapping using the uncached accelerated mode which isn't supported on
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 9632c27dad15..0bcb79a58ee9 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
257 \ 257 \
258static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ 258static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
259{ \ 259{ \
260 unsigned long start = page; \ 260 unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
261 unsigned long start = INDEX_BASE + (page & indexmask); \
261 unsigned long end = start + PAGE_SIZE; \ 262 unsigned long end = start + PAGE_SIZE; \
262 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ 263 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
263 unsigned long ws_end = current_cpu_data.desc.ways << \ 264 unsigned long ws_end = current_cpu_data.desc.ways << \
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index a474c29cd701..b09e16c93ca0 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -45,8 +45,8 @@ extern unsigned int soc_type;
45extern unsigned int periph_rev; 45extern unsigned int periph_rev;
46extern unsigned int zbbus_mhz; 46extern unsigned int zbbus_mhz;
47 47
48extern void sb1250_hpt_setup(void);
48extern void sb1250_time_init(void); 49extern void sb1250_time_init(void);
49extern unsigned long sb1250_gettimeoffset(void);
50extern void sb1250_mask_irq(int cpu, int irq); 50extern void sb1250_mask_irq(int cpu, int irq);
51extern void sb1250_unmask_irq(int cpu, int irq); 51extern void sb1250_unmask_irq(int cpu, int irq);
52extern void sb1250_smp_finish(void); 52extern void sb1250_smp_finish(void);
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index a667bc14a7cd..f4178bdcfcb0 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -359,14 +359,15 @@
359 */ 359 */
360 360
361#define V_SCD_TIMER_FREQ 1000000 361#define V_SCD_TIMER_FREQ 1000000
362#define V_SCD_TIMER_WIDTH 23
362 363
363#define S_SCD_TIMER_INIT 0 364#define S_SCD_TIMER_INIT 0
364#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 365#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
365#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 366#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
366#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 367#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
367 368
368#define S_SCD_TIMER_CNT 0 369#define S_SCD_TIMER_CNT 0
369#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 370#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
370#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 371#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
371#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 372#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
372 373
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 5618f1e12f40..75c6fe7c2126 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -58,7 +58,9 @@ static inline int num_booting_cpus(void)
58 return cpus_weight(cpu_callout_map); 58 return cpus_weight(cpu_callout_map);
59} 59}
60 60
61/* These are defined by the board-specific code. */ 61/*
62 * These are defined by the board-specific code.
63 */
62 64
63/* 65/*
64 * Cause the function described by call_data to be executed on the passed 66 * Cause the function described by call_data to be executed on the passed
@@ -79,7 +81,12 @@ extern void prom_boot_secondary(int cpu, struct task_struct *idle);
79extern void prom_init_secondary(void); 81extern void prom_init_secondary(void);
80 82
81/* 83/*
82 * Detect available CPUs, populate phys_cpu_present_map before smp_init 84 * Populate cpu_possible_map before smp_init, called from setup_arch.
85 */
86extern void plat_smp_setup(void);
87
88/*
89 * Called after init_IRQ but before __cpu_up.
83 */ 90 */
84extern void prom_prepare_cpus(unsigned int max_cpus); 91extern void prom_prepare_cpus(unsigned int max_cpus);
85 92
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index e8e5d4143377..ddae9bae31af 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -322,7 +322,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
322#endif 322#endif
323 "2: \n" 323 "2: \n"
324 " .set pop \n" 324 " .set pop \n"
325 : "=&r" (retval), "=m" (*m) 325 : "=&r" (retval), "=R" (*m)
326 : "R" (*m), "Jr" (old), "Jr" (new) 326 : "R" (*m), "Jr" (old), "Jr" (new)
327 : "memory"); 327 : "memory");
328 } else if (cpu_has_llsc) { 328 } else if (cpu_has_llsc) {
@@ -342,7 +342,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
342#endif 342#endif
343 "2: \n" 343 "2: \n"
344 " .set pop \n" 344 " .set pop \n"
345 : "=&r" (retval), "=m" (*m) 345 : "=&r" (retval), "=R" (*m)
346 : "R" (*m), "Jr" (old), "Jr" (new) 346 : "R" (*m), "Jr" (old), "Jr" (new)
347 : "memory"); 347 : "memory");
348 } else { 348 } else {
@@ -379,7 +379,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
379#endif 379#endif
380 "2: \n" 380 "2: \n"
381 " .set pop \n" 381 " .set pop \n"
382 : "=&r" (retval), "=m" (*m) 382 : "=&r" (retval), "=R" (*m)
383 : "R" (*m), "Jr" (old), "Jr" (new) 383 : "R" (*m), "Jr" (old), "Jr" (new)
384 : "memory"); 384 : "memory");
385 } else if (cpu_has_llsc) { 385 } else if (cpu_has_llsc) {
@@ -397,7 +397,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
397#endif 397#endif
398 "2: \n" 398 "2: \n"
399 " .set pop \n" 399 " .set pop \n"
400 : "=&r" (retval), "=m" (*m) 400 : "=&r" (retval), "=R" (*m)
401 : "R" (*m), "Jr" (old), "Jr" (new) 401 : "R" (*m), "Jr" (old), "Jr" (new)
402 : "memory"); 402 : "memory");
403 } else { 403 } else {
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index ca5cec97e167..34755c0a6398 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -26,6 +26,9 @@
26 * <linux/vt_buffer.h> has already done the right job for us. 26 * <linux/vt_buffer.h> has already done the right job for us.
27 */ 27 */
28 28
29#undef scr_writew
30#undef scr_readw
31
29static inline void scr_writew(u16 val, volatile u16 *addr) 32static inline void scr_writew(u16 val, volatile u16 *addr)
30{ 33{
31 *addr = cpu_to_le16(val); 34 *addr = cpu_to_le16(val);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 08:59:04 -0500