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-rw-r--r--include/asm-mips/asmmacro.h4
-rw-r--r--include/asm-mips/bitops.h4
-rw-r--r--include/asm-mips/ddb5xxx/ddb5477.h6
-rw-r--r--include/asm-mips/fpregdef.h4
-rw-r--r--include/asm-mips/fpu.h8
-rw-r--r--include/asm-mips/ip32/mace.h8
-rw-r--r--include/asm-mips/lasat/serial.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h2
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h2
-rw-r--r--include/asm-mips/mach-jazz/floppy.h2
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h4
-rw-r--r--include/asm-mips/r4kcache.h68
-rw-r--r--include/asm-mips/rtc.h2
-rw-r--r--include/asm-mips/sgi/gio.h2
-rw-r--r--include/asm-mips/sgi/hpc3.h4
-rw-r--r--include/asm-mips/sgi/ioc.h4
-rw-r--r--include/asm-mips/sgi/ip22.h2
-rw-r--r--include/asm-mips/sgi/mc.h6
-rw-r--r--include/asm-mips/sibyte/carmel.h12
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h38
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h42
-rw-r--r--include/asm-mips/sibyte/sb1250_genbus.h24
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h24
-rw-r--r--include/asm-mips/sibyte/sb1250_l2c.h22
-rw-r--r--include/asm-mips/sibyte/sb1250_ldt.h32
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h26
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h28
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h68
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h36
-rw-r--r--include/asm-mips/sibyte/sb1250_smbus.h24
-rw-r--r--include/asm-mips/sibyte/sb1250_syncser.h12
-rw-r--r--include/asm-mips/sibyte/sb1250_uart.h30
-rw-r--r--include/asm-mips/sigcontext.h4
-rw-r--r--include/asm-mips/socket.h2
-rw-r--r--include/asm-mips/statfs.h2
-rw-r--r--include/asm-mips/titan_dep.h2
-rw-r--r--include/asm-mips/tx4927/tx4927.h52
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h4
-rw-r--r--include/asm-mips/vr41xx/vrc4173.h4
-rw-r--r--include/asm-mips/war.h4
-rw-r--r--include/asm-mips/xxs1500.h2
41 files changed, 315 insertions, 315 deletions
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 40ceedcf454e..30b18ea6cb11 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -7,10 +7,10 @@
7 */ 7 */
8#ifndef _ASM_ASMMACRO_H 8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H 9#define _ASM_ASMMACRO_H
10 10
11#include <linux/config.h> 11#include <linux/config.h>
12#include <asm/hazards.h> 12#include <asm/hazards.h>
13 13
14#ifdef CONFIG_32BIT 14#ifdef CONFIG_32BIT
15#include <asm/asmmacro-32.h> 15#include <asm/asmmacro-32.h>
16#endif 16#endif
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index bc136dcfdbe6..eb8d79dba11c 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -20,13 +20,13 @@
20#define SZLONG_MASK 31UL 20#define SZLONG_MASK 31UL
21#define __LL "ll " 21#define __LL "ll "
22#define __SC "sc " 22#define __SC "sc "
23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
24#elif (_MIPS_SZLONG == 64) 24#elif (_MIPS_SZLONG == 64)
25#define SZLONG_LOG 6 25#define SZLONG_LOG 6
26#define SZLONG_MASK 63UL 26#define SZLONG_MASK 63UL
27#define __LL "lld " 27#define __LL "lld "
28#define __SC "scd " 28#define __SC "scd "
29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
30#endif 30#endif
31 31
32#ifdef __KERNEL__ 32#ifdef __KERNEL__
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
index ae3e2a38fd5f..a438548e6ef3 100644
--- a/include/asm-mips/ddb5xxx/ddb5477.h
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
247 * All PCI irq but INTC are active low. 247 * All PCI irq but INTC are active low.
248 */ 248 */
249 249
250/* 250/*
251 * irq number block assignment 251 * irq number block assignment
252 */ 252 */
253 253
@@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
285#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ 285#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
286#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ 286#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
287#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ 287#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
288#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) 288#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
289#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ 289#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
290#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ 290#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
291#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ 291#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
@@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
301/* 301/*
302 * i2859 irq assignment 302 * i2859 irq assignment
303 */ 303 */
304#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) 304#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
305#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ 305#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
306#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) 306#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
307#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ 307#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
index 1d9aa0979181..2b5fddc8f487 100644
--- a/include/asm-mips/fpregdef.h
+++ b/include/asm-mips/fpregdef.h
@@ -13,7 +13,7 @@
13#define _ASM_FPREGDEF_H 13#define _ASM_FPREGDEF_H
14 14
15#include <asm/sgidefs.h> 15#include <asm/sgidefs.h>
16 16
17#if _MIPS_SIM == _MIPS_SIM_ABI32 17#if _MIPS_SIM == _MIPS_SIM_ABI32
18 18
19/* 19/*
@@ -56,7 +56,7 @@
56#define fcr31 $31 /* FPU status register */ 56#define fcr31 $31 /* FPU status register */
57 57
58#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 58#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
59 59
60#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 60#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
61 61
62#define fv0 $f0 /* return value */ 62#define fv0 $f0 /* return value */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index 6cb38d5c0407..ea24e733b1bc 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -82,7 +82,7 @@ do { \
82 82
83static inline int is_fpu_owner(void) 83static inline int is_fpu_owner(void)
84{ 84{
85 return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 85 return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
86} 86}
87 87
88static inline void own_fpu(void) 88static inline void own_fpu(void)
@@ -90,7 +90,7 @@ static inline void own_fpu(void)
90 if (cpu_has_fpu) { 90 if (cpu_has_fpu) {
91 __enable_fpu(); 91 __enable_fpu();
92 KSTK_STATUS(current) |= ST0_CU1; 92 KSTK_STATUS(current) |= ST0_CU1;
93 set_thread_flag(TIF_USEDFPU); 93 set_thread_flag(TIF_USEDFPU);
94 } 94 }
95} 95}
96 96
@@ -98,7 +98,7 @@ static inline void lose_fpu(void)
98{ 98{
99 if (cpu_has_fpu) { 99 if (cpu_has_fpu) {
100 KSTK_STATUS(current) &= ~ST0_CU1; 100 KSTK_STATUS(current) &= ~ST0_CU1;
101 clear_thread_flag(TIF_USEDFPU); 101 clear_thread_flag(TIF_USEDFPU);
102 __disable_fpu(); 102 __disable_fpu();
103 } 103 }
104} 104}
@@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk)
127static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) 127static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
128{ 128{
129 if (cpu_has_fpu) { 129 if (cpu_has_fpu) {
130 if ((tsk == current) && is_fpu_owner()) 130 if ((tsk == current) && is_fpu_owner())
131 _save_fp(current); 131 _save_fp(current);
132 return tsk->thread.fpu.hard.fpr; 132 return tsk->thread.fpu.hard.fpr;
133 } 133 }
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 2b7b0fdeac19..432011b16c26 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -94,7 +94,7 @@ struct mace_video {
94 unsigned long xxx; /* later... */ 94 unsigned long xxx; /* later... */
95}; 95};
96 96
97/* 97/*
98 * Ethernet interface 98 * Ethernet interface
99 */ 99 */
100struct mace_ethernet { 100struct mace_ethernet {
@@ -129,7 +129,7 @@ struct mace_ethernet {
129 volatile unsigned long rx_fifo; 129 volatile unsigned long rx_fifo;
130}; 130};
131 131
132/* 132/*
133 * Peripherals 133 * Peripherals
134 */ 134 */
135 135
@@ -251,7 +251,7 @@ struct mace_timers {
251 timer_reg audio_out2; 251 timer_reg audio_out2;
252 timer_reg video_in1; 252 timer_reg video_in1;
253 timer_reg video_in2; 253 timer_reg video_in2;
254 timer_reg video_out; 254 timer_reg video_out;
255}; 255};
256 256
257struct mace_perif { 257struct mace_perif {
@@ -272,7 +272,7 @@ struct mace_perif {
272}; 272};
273 273
274 274
275/* 275/*
276 * ISA peripherals 276 * ISA peripherals
277 */ 277 */
278 278
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index 21d0fb7cee64..9e88c7669c7a 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -1,13 +1,13 @@
1#include <asm/lasat/lasat.h> 1#include <asm/lasat/lasat.h>
2 2
3/* Lasat 100 boards serial configuration */ 3/* Lasat 100 boards serial configuration */
4#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) 4#define LASAT_BASE_BAUD_100 ( 7372800 / 16 )
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000 5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2 6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8 7#define LASATINT_UART_100 8
8 8
9/* * LASAT 200 boards serial configuration */ 9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) 10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) 11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3 12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13 13#define LASATINT_UART_200 13
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 2b36ea346910..148bae2fa7d3 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1383#define PCI_IO_START 0 1383#define PCI_IO_START 0
1384#define PCI_IO_END 0 1384#define PCI_IO_END 0
1385#define PCI_MEM_START 0 1385#define PCI_MEM_START 0
1386#define PCI_MEM_END 0 1386#define PCI_MEM_END 0
1387#define PCI_FIRST_DEVFN 0 1387#define PCI_FIRST_DEVFN 0
1388#define PCI_LAST_DEVFN 0 1388#define PCI_LAST_DEVFN 0
1389#endif 1389#endif
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 4691398a414f..efafe65258b6 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -23,7 +23,7 @@
23 * 23 *
24 * ######################################################################## 24 * ########################################################################
25 * 25 *
26 * 26 *
27 */ 27 */
28#ifndef __ASM_DB1X00_H 28#ifndef __ASM_DB1X00_H
29#define __ASM_DB1X00_H 29#define __ASM_DB1X00_H
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
index 8cf0d042c864..c9dad99b1232 100644
--- a/include/asm-mips/mach-jazz/floppy.h
+++ b/include/asm-mips/mach-jazz/floppy.h
@@ -92,7 +92,7 @@ static inline int fd_request_irq(void)
92 return request_irq(FLOPPY_IRQ, floppy_interrupt, 92 return request_irq(FLOPPY_IRQ, floppy_interrupt,
93 SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); 93 SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
94} 94}
95 95
96static inline void fd_free_irq(void) 96static inline void fd_free_irq(void)
97{ 97{
98 free_irq(FLOPPY_IRQ, NULL); 98 free_irq(FLOPPY_IRQ, NULL);
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index d6c779747b3c..ff6d40c87a25 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -33,11 +33,11 @@
33#define PCI_BOARD_REG 0xAE000010 33#define PCI_BOARD_REG 0xAE000010
34#define PCMCIA_BOARD_REG 0xAE000010 34#define PCMCIA_BOARD_REG 0xAE000010
35 #define PC_DEASSERT_RST 0x80 35 #define PC_DEASSERT_RST 0x80
36 #define PC_DRV_EN 0x10 36 #define PC_DRV_EN 0x10
37#define PB1500_G_CONTROL 0xAE000014 37#define PB1500_G_CONTROL 0xAE000014
38#define PB1500_RST_VDDI 0xAE00001C 38#define PB1500_RST_VDDI 0xAE00001C
39#define PB1500_LEDS 0xAE000018 39#define PB1500_LEDS 0xAE000018
40 40
41#define PB1500_HEX_LED 0xAF000004 41#define PB1500_HEX_LED 0xAF000004
42#define PB1500_HEX_LED_BLANK 0xAF000008 42#define PB1500_HEX_LED_BLANK 0xAF000008
43 43
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index da03a32c1ca7..5bea49feec66 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -171,11 +171,11 @@ static inline void blast_dcache16(void)
171 unsigned long start = INDEX_BASE; 171 unsigned long start = INDEX_BASE;
172 unsigned long end = start + current_cpu_data.dcache.waysize; 172 unsigned long end = start + current_cpu_data.dcache.waysize;
173 unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; 173 unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
174 unsigned long ws_end = current_cpu_data.dcache.ways << 174 unsigned long ws_end = current_cpu_data.dcache.ways <<
175 current_cpu_data.dcache.waybit; 175 current_cpu_data.dcache.waybit;
176 unsigned long ws, addr; 176 unsigned long ws, addr;
177 177
178 for (ws = 0; ws < ws_end; ws += ws_inc) 178 for (ws = 0; ws < ws_end; ws += ws_inc)
179 for (addr = start; addr < end; addr += 0x200) 179 for (addr = start; addr < end; addr += 0x200)
180 cache16_unroll32(addr|ws,Index_Writeback_Inv_D); 180 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
181} 181}
@@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page)
200 current_cpu_data.dcache.waybit; 200 current_cpu_data.dcache.waybit;
201 unsigned long ws, addr; 201 unsigned long ws, addr;
202 202
203 for (ws = 0; ws < ws_end; ws += ws_inc) 203 for (ws = 0; ws < ws_end; ws += ws_inc)
204 for (addr = start; addr < end; addr += 0x200) 204 for (addr = start; addr < end; addr += 0x200)
205 cache16_unroll32(addr|ws,Index_Writeback_Inv_D); 205 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
206} 206}
207 207
@@ -214,8 +214,8 @@ static inline void blast_icache16(void)
214 current_cpu_data.icache.waybit; 214 current_cpu_data.icache.waybit;
215 unsigned long ws, addr; 215 unsigned long ws, addr;
216 216
217 for (ws = 0; ws < ws_end; ws += ws_inc) 217 for (ws = 0; ws < ws_end; ws += ws_inc)
218 for (addr = start; addr < end; addr += 0x200) 218 for (addr = start; addr < end; addr += 0x200)
219 cache16_unroll32(addr|ws,Index_Invalidate_I); 219 cache16_unroll32(addr|ws,Index_Invalidate_I);
220} 220}
221 221
@@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page)
239 current_cpu_data.icache.waybit; 239 current_cpu_data.icache.waybit;
240 unsigned long ws, addr; 240 unsigned long ws, addr;
241 241
242 for (ws = 0; ws < ws_end; ws += ws_inc) 242 for (ws = 0; ws < ws_end; ws += ws_inc)
243 for (addr = start; addr < end; addr += 0x200) 243 for (addr = start; addr < end; addr += 0x200)
244 cache16_unroll32(addr|ws,Index_Invalidate_I); 244 cache16_unroll32(addr|ws,Index_Invalidate_I);
245} 245}
246 246
@@ -249,11 +249,11 @@ static inline void blast_scache16(void)
249 unsigned long start = INDEX_BASE; 249 unsigned long start = INDEX_BASE;
250 unsigned long end = start + current_cpu_data.scache.waysize; 250 unsigned long end = start + current_cpu_data.scache.waysize;
251 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; 251 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
252 unsigned long ws_end = current_cpu_data.scache.ways << 252 unsigned long ws_end = current_cpu_data.scache.ways <<
253 current_cpu_data.scache.waybit; 253 current_cpu_data.scache.waybit;
254 unsigned long ws, addr; 254 unsigned long ws, addr;
255 255
256 for (ws = 0; ws < ws_end; ws += ws_inc) 256 for (ws = 0; ws < ws_end; ws += ws_inc)
257 for (addr = start; addr < end; addr += 0x200) 257 for (addr = start; addr < end; addr += 0x200)
258 cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); 258 cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
259} 259}
@@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page)
278 current_cpu_data.scache.waybit; 278 current_cpu_data.scache.waybit;
279 unsigned long ws, addr; 279 unsigned long ws, addr;
280 280
281 for (ws = 0; ws < ws_end; ws += ws_inc) 281 for (ws = 0; ws < ws_end; ws += ws_inc)
282 for (addr = start; addr < end; addr += 0x200) 282 for (addr = start; addr < end; addr += 0x200)
283 cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); 283 cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
284} 284}
285 285
@@ -318,8 +318,8 @@ static inline void blast_dcache32(void)
318 current_cpu_data.dcache.waybit; 318 current_cpu_data.dcache.waybit;
319 unsigned long ws, addr; 319 unsigned long ws, addr;
320 320
321 for (ws = 0; ws < ws_end; ws += ws_inc) 321 for (ws = 0; ws < ws_end; ws += ws_inc)
322 for (addr = start; addr < end; addr += 0x400) 322 for (addr = start; addr < end; addr += 0x400)
323 cache32_unroll32(addr|ws,Index_Writeback_Inv_D); 323 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
324} 324}
325 325
@@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page)
343 current_cpu_data.dcache.waybit; 343 current_cpu_data.dcache.waybit;
344 unsigned long ws, addr; 344 unsigned long ws, addr;
345 345
346 for (ws = 0; ws < ws_end; ws += ws_inc) 346 for (ws = 0; ws < ws_end; ws += ws_inc)
347 for (addr = start; addr < end; addr += 0x400) 347 for (addr = start; addr < end; addr += 0x400)
348 cache32_unroll32(addr|ws,Index_Writeback_Inv_D); 348 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
349} 349}
350 350
@@ -357,8 +357,8 @@ static inline void blast_icache32(void)
357 current_cpu_data.icache.waybit; 357 current_cpu_data.icache.waybit;
358 unsigned long ws, addr; 358 unsigned long ws, addr;
359 359
360 for (ws = 0; ws < ws_end; ws += ws_inc) 360 for (ws = 0; ws < ws_end; ws += ws_inc)
361 for (addr = start; addr < end; addr += 0x400) 361 for (addr = start; addr < end; addr += 0x400)
362 cache32_unroll32(addr|ws,Index_Invalidate_I); 362 cache32_unroll32(addr|ws,Index_Invalidate_I);
363} 363}
364 364
@@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page)
383 unsigned long ws, addr; 383 unsigned long ws, addr;
384 384
385 for (ws = 0; ws < ws_end; ws += ws_inc) 385 for (ws = 0; ws < ws_end; ws += ws_inc)
386 for (addr = start; addr < end; addr += 0x400) 386 for (addr = start; addr < end; addr += 0x400)
387 cache32_unroll32(addr|ws,Index_Invalidate_I); 387 cache32_unroll32(addr|ws,Index_Invalidate_I);
388} 388}
389 389
@@ -392,11 +392,11 @@ static inline void blast_scache32(void)
392 unsigned long start = INDEX_BASE; 392 unsigned long start = INDEX_BASE;
393 unsigned long end = start + current_cpu_data.scache.waysize; 393 unsigned long end = start + current_cpu_data.scache.waysize;
394 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; 394 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
395 unsigned long ws_end = current_cpu_data.scache.ways << 395 unsigned long ws_end = current_cpu_data.scache.ways <<
396 current_cpu_data.scache.waybit; 396 current_cpu_data.scache.waybit;
397 unsigned long ws, addr; 397 unsigned long ws, addr;
398 398
399 for (ws = 0; ws < ws_end; ws += ws_inc) 399 for (ws = 0; ws < ws_end; ws += ws_inc)
400 for (addr = start; addr < end; addr += 0x400) 400 for (addr = start; addr < end; addr += 0x400)
401 cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); 401 cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
402} 402}
@@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page)
421 current_cpu_data.scache.waybit; 421 current_cpu_data.scache.waybit;
422 unsigned long ws, addr; 422 unsigned long ws, addr;
423 423
424 for (ws = 0; ws < ws_end; ws += ws_inc) 424 for (ws = 0; ws < ws_end; ws += ws_inc)
425 for (addr = start; addr < end; addr += 0x400) 425 for (addr = start; addr < end; addr += 0x400)
426 cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); 426 cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
427} 427}
428 428
@@ -461,8 +461,8 @@ static inline void blast_icache64(void)
461 current_cpu_data.icache.waybit; 461 current_cpu_data.icache.waybit;
462 unsigned long ws, addr; 462 unsigned long ws, addr;
463 463
464 for (ws = 0; ws < ws_end; ws += ws_inc) 464 for (ws = 0; ws < ws_end; ws += ws_inc)
465 for (addr = start; addr < end; addr += 0x800) 465 for (addr = start; addr < end; addr += 0x800)
466 cache64_unroll32(addr|ws,Index_Invalidate_I); 466 cache64_unroll32(addr|ws,Index_Invalidate_I);
467} 467}
468 468
@@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page)
487 unsigned long ws, addr; 487 unsigned long ws, addr;
488 488
489 for (ws = 0; ws < ws_end; ws += ws_inc) 489 for (ws = 0; ws < ws_end; ws += ws_inc)
490 for (addr = start; addr < end; addr += 0x800) 490 for (addr = start; addr < end; addr += 0x800)
491 cache64_unroll32(addr|ws,Index_Invalidate_I); 491 cache64_unroll32(addr|ws,Index_Invalidate_I);
492} 492}
493 493
@@ -496,11 +496,11 @@ static inline void blast_scache64(void)
496 unsigned long start = INDEX_BASE; 496 unsigned long start = INDEX_BASE;
497 unsigned long end = start + current_cpu_data.scache.waysize; 497 unsigned long end = start + current_cpu_data.scache.waysize;
498 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; 498 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
499 unsigned long ws_end = current_cpu_data.scache.ways << 499 unsigned long ws_end = current_cpu_data.scache.ways <<
500 current_cpu_data.scache.waybit; 500 current_cpu_data.scache.waybit;
501 unsigned long ws, addr; 501 unsigned long ws, addr;
502 502
503 for (ws = 0; ws < ws_end; ws += ws_inc) 503 for (ws = 0; ws < ws_end; ws += ws_inc)
504 for (addr = start; addr < end; addr += 0x800) 504 for (addr = start; addr < end; addr += 0x800)
505 cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); 505 cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
506} 506}
@@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page)
525 current_cpu_data.scache.waybit; 525 current_cpu_data.scache.waybit;
526 unsigned long ws, addr; 526 unsigned long ws, addr;
527 527
528 for (ws = 0; ws < ws_end; ws += ws_inc) 528 for (ws = 0; ws < ws_end; ws += ws_inc)
529 for (addr = start; addr < end; addr += 0x800) 529 for (addr = start; addr < end; addr += 0x800)
530 cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); 530 cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
531} 531}
532 532
@@ -561,11 +561,11 @@ static inline void blast_scache128(void)
561 unsigned long start = INDEX_BASE; 561 unsigned long start = INDEX_BASE;
562 unsigned long end = start + current_cpu_data.scache.waysize; 562 unsigned long end = start + current_cpu_data.scache.waysize;
563 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; 563 unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
564 unsigned long ws_end = current_cpu_data.scache.ways << 564 unsigned long ws_end = current_cpu_data.scache.ways <<
565 current_cpu_data.scache.waybit; 565 current_cpu_data.scache.waybit;
566 unsigned long ws, addr; 566 unsigned long ws, addr;
567 567
568 for (ws = 0; ws < ws_end; ws += ws_inc) 568 for (ws = 0; ws < ws_end; ws += ws_inc)
569 for (addr = start; addr < end; addr += 0x1000) 569 for (addr = start; addr < end; addr += 0x1000)
570 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); 570 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
571} 571}
@@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page)
590 current_cpu_data.scache.waybit; 590 current_cpu_data.scache.waybit;
591 unsigned long ws, addr; 591 unsigned long ws, addr;
592 592
593 for (ws = 0; ws < ws_end; ws += ws_inc) 593 for (ws = 0; ws < ws_end; ws += ws_inc)
594 for (addr = start; addr < end; addr += 0x1000) 594 for (addr = start; addr < end; addr += 0x1000)
595 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); 595 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
596} 596}
597 597
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 31c0c2347f4f..3c4b637fd925 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-mips/rtc.h 2 * include/asm-mips/rtc.h
3 * 3 *
4 * (Really an interface for drivers/char/genrtc.c) 4 * (Really an interface for drivers/char/genrtc.c)
5 * 5 *
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
index a38d66f99872..889cf028c95d 100644
--- a/include/asm-mips/sgi/gio.h
+++ b/include/asm-mips/sgi/gio.h
@@ -16,7 +16,7 @@
16 * 16 *
17 * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have 17 * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
18 * three physical connectors, but only two slots, GFX and EXP0. 18 * three physical connectors, but only two slots, GFX and EXP0.
19 * 19 *
20 * There is 10MB of GIO address space for GIO64 slot devices 20 * There is 10MB of GIO address space for GIO64 slot devices
21 * slot# slot type address range size 21 * slot# slot type address range size
22 * ----- --------- ----------------------- ----- 22 * ----- --------- ----------------------- -----
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index a5b988d7327a..ac3dfc7af5b0 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -221,7 +221,7 @@ struct hpc3_regs {
221#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ 221#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
222 222
223 u32 _unused1[0x14000/4 - 5]; /* padding */ 223 u32 _unused1[0x14000/4 - 5]; /* padding */
224 224
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */ 225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ 226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
227 u32 _unused2[0x7c00/4]; 227 u32 _unused2[0x7c00/4];
@@ -304,7 +304,7 @@ struct hpc3_regs {
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */ 304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */
305}; 305};
306 306
307/* 307/*
308 * It is possible to have two HPC3's within the address space on 308 * It is possible to have two HPC3's within the address space on
309 * one machine, though only having one is more likely on an Indy. 309 * one machine, though only having one is more likely on an Indy.
310 */ 310 */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index 169187f53fbc..f3e3dc9bb732 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -16,7 +16,7 @@
16#include <linux/types.h> 16#include <linux/types.h>
17#include <asm/sgi/pi1.h> 17#include <asm/sgi/pi1.h>
18 18
19/* 19/*
20 * All registers are 8-bit wide alligned on 32-bit boundary. Bad things 20 * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
21 * happen if you try word access them. You have been warned. 21 * happen if you try word access them. You have been warned.
22 */ 22 */
@@ -138,7 +138,7 @@ struct sgioc_regs {
138 u8 _sysid[3]; 138 u8 _sysid[3];
139 volatile u8 sysid; 139 volatile u8 sysid;
140#define SGIOC_SYSID_FULLHOUSE 0x01 140#define SGIOC_SYSID_FULLHOUSE 0x01
141#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 141#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
142#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) 142#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1)
143 u32 _unused2; 143 u32 _unused2;
144 u8 _read[3]; 144 u8 _read[3];
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 97d73adb4e40..bbfc05c3cab9 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -12,7 +12,7 @@
12#ifndef _SGI_IP22_H 12#ifndef _SGI_IP22_H
13#define _SGI_IP22_H 13#define _SGI_IP22_H
14 14
15/* 15/*
16 * These are the virtual IRQ numbers, we divide all IRQ's into 16 * These are the virtual IRQ numbers, we divide all IRQ's into
17 * 'spaces', the 'space' determines where and how to enable/disable 17 * 'spaces', the 'space' determines where and how to enable/disable
18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups 18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index fd98f930607c..c52f7834c7c8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -182,14 +182,14 @@ struct sgimc_regs {
182 volatile u32 dtlb_hi3; 182 volatile u32 dtlb_hi3;
183 u32 _unused33; 183 u32 _unused33;
184 volatile u32 dtlb_lo3; 184 volatile u32 dtlb_lo3;
185 185
186 u32 _unused34[0x0392]; 186 u32 _unused34[0x0392];
187 187
188 u32 _unused35; 188 u32 _unused35;
189 volatile u32 rpsscounter; /* Chirps at 100ns */ 189 volatile u32 rpsscounter; /* Chirps at 100ns */
190 190
191 u32 _unused36[0x1000/4-2*4]; 191 u32 _unused36[0x1000/4-2*4];
192 192
193 u32 _unused37; 193 u32 _unused37;
194 volatile u32 maddronly; /* Address DMA goes at */ 194 volatile u32 maddronly; /* Address DMA goes at */
195 u32 _unused38; 195 u32 _unused38;
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 7ac5da13ce8a..b5e7dae19f0f 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -25,12 +25,12 @@
25 25
26#define SIBYTE_BOARD_NAME "Carmel" 26#define SIBYTE_BOARD_NAME "Carmel"
27 27
28#define GPIO_PHY_INTERRUPT 2 28#define GPIO_PHY_INTERRUPT 2
29#define GPIO_NONMASKABLE_INT 3 29#define GPIO_NONMASKABLE_INT 3
30#define GPIO_CF_INSERTED 6 30#define GPIO_CF_INSERTED 6
31#define GPIO_MONTEREY_RESET 7 31#define GPIO_MONTEREY_RESET 7
32#define GPIO_QUADUART_INT 8 32#define GPIO_QUADUART_INT 8
33#define GPIO_CF_INT 9 33#define GPIO_CF_INT 9
34#define GPIO_FPGA_CCLK 10 34#define GPIO_FPGA_CCLK 10
35#define GPIO_FPGA_DOUT 11 35#define GPIO_FPGA_DOUT 11
36#define GPIO_FPGA_DIN 12 36#define GPIO_FPGA_DIN 12
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 96088fb074a4..40ef97c76c8b 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Global constants and macros File: sb1250_defs.h 4 * Global constants and macros File: sb1250_defs.h
5 * 5 *
6 * This file contains macros and definitions used by the other 6 * This file contains macros and definitions used by the other
7 * include files. 7 * include files.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -105,7 +105,7 @@
105#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 105#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00
106#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 106#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100
107 107
108/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ 108/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
109#define SIBYTE_HDR_FMASK(chip, pass) \ 109#define SIBYTE_HDR_FMASK(chip, pass) \
110 (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) 110 (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
111#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ 111#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
@@ -150,31 +150,31 @@
150 150
151/* ********************************************************************* 151/* *********************************************************************
152 * Naming schemes for constants in these files: 152 * Naming schemes for constants in these files:
153 * 153 *
154 * M_xxx MASK constant (identifies bits in a register). 154 * M_xxx MASK constant (identifies bits in a register).
155 * For multi-bit fields, all bits in the field will 155 * For multi-bit fields, all bits in the field will
156 * be set. 156 * be set.
157 * 157 *
158 * K_xxx "Code" constant (value for data in a multi-bit 158 * K_xxx "Code" constant (value for data in a multi-bit
159 * field). The value is right justified. 159 * field). The value is right justified.
160 * 160 *
161 * V_xxx "Value" constant. This is the same as the 161 * V_xxx "Value" constant. This is the same as the
162 * corresponding "K_xxx" constant, except it is 162 * corresponding "K_xxx" constant, except it is
163 * shifted to the correct position in the register. 163 * shifted to the correct position in the register.
164 * 164 *
165 * S_xxx SHIFT constant. This is the number of bits that 165 * S_xxx SHIFT constant. This is the number of bits that
166 * a field value (code) needs to be shifted 166 * a field value (code) needs to be shifted
167 * (towards the left) to put the value in the right 167 * (towards the left) to put the value in the right
168 * position for the register. 168 * position for the register.
169 * 169 *
170 * A_xxx ADDRESS constant. This will be a physical 170 * A_xxx ADDRESS constant. This will be a physical
171 * address. Use the PHYS_TO_K1 macro to generate 171 * address. Use the PHYS_TO_K1 macro to generate
172 * a K1SEG address. 172 * a K1SEG address.
173 * 173 *
174 * R_xxx RELATIVE offset constant. This is an offset from 174 * R_xxx RELATIVE offset constant. This is an offset from
175 * an A_xxx constant (usually the first register in 175 * an A_xxx constant (usually the first register in
176 * a group). 176 * a group).
177 * 177 *
178 * G_xxx(X) GET value. This macro obtains a multi-bit field 178 * G_xxx(X) GET value. This macro obtains a multi-bit field
179 * from a register, masks it, and shifts it to 179 * from a register, masks it, and shifts it to
180 * the bottom of the register (retrieving a K_xxx 180 * the bottom of the register (retrieving a K_xxx
@@ -189,7 +189,7 @@
189 189
190 190
191/* 191/*
192 * Cast to 64-bit number. Presumably the syntax is different in 192 * Cast to 64-bit number. Presumably the syntax is different in
193 * assembly language. 193 * assembly language.
194 * 194 *
195 * Note: you'll need to define uint32_t and uint64_t in your headers. 195 * Note: you'll need to define uint32_t and uint64_t in your headers.
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index f1b08d32338d..3cdb48f50ed0 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -1,24 +1,24 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * DMA definitions File: sb1250_dma.h 4 * DMA definitions File: sb1250_dma.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * programming the SB1250's DMA controllers, both the data mover 7 * programming the SB1250's DMA controllers, both the data mover
8 * and the Ethernet DMA. 8 * and the Ethernet DMA.
9 * 9 *
10 * SB1250 specification level: User's manual 1/02/02 10 * SB1250 specification level: User's manual 1/02/02
11 * 11 *
12 * Author: Mitch Lichtenberg 12 * Author: Mitch Lichtenberg
13 * 13 *
14 ********************************************************************* 14 *********************************************************************
15 * 15 *
16 * Copyright 2000,2001,2002,2003 16 * Copyright 2000,2001,2002,2003
17 * Broadcom Corporation. All rights reserved. 17 * Broadcom Corporation. All rights reserved.
18 * 18 *
19 * This program is free software; you can redistribute it and/or 19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as 20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of 21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version. 22 * the License, or (at your option) any later version.
23 * 23 *
24 * This program is distributed in the hope that it will be useful, 24 * This program is distributed in the hope that it will be useful,
@@ -28,7 +28,7 @@
28 * 28 *
29 * You should have received a copy of the GNU General Public License 29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software 30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA 32 * MA 02111-1307 USA
33 ********************************************************************* */ 33 ********************************************************************* */
34 34
@@ -43,9 +43,9 @@
43 * DMA Registers 43 * DMA Registers
44 ********************************************************************* */ 44 ********************************************************************* */
45 45
46/* 46/*
47 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) 47 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
48 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 48 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
49 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 49 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
50 * Registers: DMA_CONFIG0_SER_x_RX 50 * Registers: DMA_CONFIG0_SER_x_RX
51 * Registers: DMA_CONFIG0_SER_x_TX 51 * Registers: DMA_CONFIG0_SER_x_TX
@@ -98,7 +98,7 @@
98 98
99/* 99/*
100 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) 100 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
101 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 101 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
102 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 102 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
103 * Registers: DMA_CONFIG1_SER_x_RX 103 * Registers: DMA_CONFIG1_SER_x_RX
104 * Registers: DMA_CONFIG1_SER_x_TX 104 * Registers: DMA_CONFIG1_SER_x_TX
@@ -152,11 +152,11 @@
152/* 152/*
153 * DMA Descriptor Count Registers (Table 7-8) 153 * DMA Descriptor Count Registers (Table 7-8)
154 */ 154 */
155 155
156/* No bitfields */ 156/* No bitfields */
157 157
158 158
159/* 159/*
160 * Current Descriptor Address Register (Table 7-11) 160 * Current Descriptor Address Register (Table 7-11)
161 */ 161 */
162 162
@@ -275,14 +275,14 @@
275#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) 275#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
276#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) 276#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
277 277
278/* 278/*
279 * Ethernet Descriptor Status Bits (Table 7-15) 279 * Ethernet Descriptor Status Bits (Table 7-15)
280 */ 280 */
281 281
282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
284 284
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
286/* Note: BADTCPCS is actually in DSCR_B options field */ 286/* Note: BADTCPCS is actually in DSCR_B options field */
287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288#endif /* 1250 PASS2 || 112x PASS1 */ 288#endif /* 1250 PASS2 || 112x PASS1 */
@@ -324,7 +324,7 @@
324 324
325#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) 325#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
326 326
327/* 327/*
328 * Ethernet Transmit Options (Table 7-17) 328 * Ethernet Transmit Options (Table 7-17)
329 */ 329 */
330 330
@@ -377,7 +377,7 @@
377 * Data Mover Registers 377 * Data Mover Registers
378 ********************************************************************* */ 378 ********************************************************************* */
379 379
380/* 380/*
381 * Data Mover Descriptor Base Address Register (Table 7-22) 381 * Data Mover Descriptor Base Address Register (Table 7-22)
382 * Register: DM_DSCR_BASE_0 382 * Register: DM_DSCR_BASE_0
383 * Register: DM_DSCR_BASE_1 383 * Register: DM_DSCR_BASE_1
@@ -414,7 +414,7 @@
414#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) 414#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
415#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) 415#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
416 416
417/* 417/*
418 * Data Mover Descriptor Count Register (Table 7-25) 418 * Data Mover Descriptor Count Register (Table 7-25)
419 */ 419 */
420 420
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index 0d9dfac3d7db..f1f509f295c4 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Generic Bus Constants File: sb1250_genbus.h 4 * Generic Bus Constants File: sb1250_genbus.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the SB1250's Generic Bus interface 7 * manipulating the SB1250's Generic Bus interface
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index c3f74df211f4..e173e2ea4c98 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Interrupt Mapper definitions File: sb1250_int.h 4 * Interrupt Mapper definitions File: sb1250_int.h
5 * 5 *
6 * This module contains constants for manipulating the SB1250's 6 * This module contains constants for manipulating the SB1250's
7 * interrupt mapper and definitions for the interrupt sources. 7 * interrupt mapper and definitions for the interrupt sources.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -43,7 +43,7 @@
43 43
44/* 44/*
45 * Interrupt sources (Table 4-8, UM 0.2) 45 * Interrupt sources (Table 4-8, UM 0.2)
46 * 46 *
47 * First, the interrupt numbers. 47 * First, the interrupt numbers.
48 */ 48 */
49 49
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 799db828d963..8afe8e01581b 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * L2 Cache constants and macros File: sb1250_l2c.h 4 * L2 Cache constants and macros File: sb1250_l2c.h
5 * 5 *
6 * This module contains constants useful for manipulating the 6 * This module contains constants useful for manipulating the
7 * level 2 cache. 7 * level 2 cache.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index d8753885df17..f2617ded0a8f 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * LDT constants File: sb1250_ldt.h 4 * LDT constants File: sb1250_ldt.h
5 * 5 *
6 * This module contains constants and macros to describe 6 * This module contains constants and macros to describe
7 * the LDT interface on the SB1250. 7 * the LDT interface on the SB1250.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -155,7 +155,7 @@
155 155
156/* 156/*
157 * LDT Status Register (Table 8-14). Note that these constants 157 * LDT Status Register (Table 8-14). Note that these constants
158 * assume you've read the command and status register 158 * assume you've read the command and status register
159 * together (32-bit read at offset 0x04) 159 * together (32-bit read at offset 0x04)
160 * 160 *
161 * These bits also apply to the secondary status 161 * These bits also apply to the secondary status
@@ -183,8 +183,8 @@
183#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) 183#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
184 184
185/* 185/*
186 * Bridge Control Register (Table 8-16). Note that these 186 * Bridge Control Register (Table 8-16). Note that these
187 * constants assume you've read the register as a 32-bit 187 * constants assume you've read the register as a 32-bit
188 * read (offset 0x3C) 188 * read (offset 0x3C)
189 */ 189 */
190 190
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 81f603f03a98..18e74e43f4a2 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * MAC constants and macros File: sb1250_mac.h 4 * MAC constants and macros File: sb1250_mac.h
5 * 5 *
6 * This module contains constants and macros for the SB1250's 6 * This module contains constants and macros for the SB1250's
7 * ethernet controllers. 7 * ethernet controllers.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -311,7 +311,7 @@
311 311
312/* 312/*
313 * These constants are used to configure the fields within the Frame 313 * These constants are used to configure the fields within the Frame
314 * Configuration Register. 314 * Configuration Register.
315 */ 315 */
316 316
317#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 317#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
@@ -393,7 +393,7 @@
393 * Register: MAC_INT_MASK_2 393 * Register: MAC_INT_MASK_2
394 */ 394 */
395 395
396/* 396/*
397 * Use these constants to shift the appropriate channel 397 * Use these constants to shift the appropriate channel
398 * into the CH0 position so the same tests can be used 398 * into the CH0 position so the same tests can be used
399 * on each channel. 399 * on each channel.
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 93a48334b874..1dd41c927996 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Memory Controller constants File: sb1250_mc.h 4 * Memory Controller constants File: sb1250_mc.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * programming the memory controller. 7 * programming the memory controller.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -166,7 +166,7 @@
166 166
167#define K_MC_REF_RATE_100MHz 0x62 167#define K_MC_REF_RATE_100MHz 0x62
168#define K_MC_REF_RATE_133MHz 0x81 168#define K_MC_REF_RATE_133MHz 0x81
169#define K_MC_REF_RATE_200MHz 0xC4 169#define K_MC_REF_RATE_200MHz 0xC4
170 170
171#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 171#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
172#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 172#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
@@ -228,7 +228,7 @@
228 V_MC_ADDR_DRIVE_DEFAULT | \ 228 V_MC_ADDR_DRIVE_DEFAULT | \
229 V_MC_DATA_DRIVE_DEFAULT | \ 229 V_MC_DATA_DRIVE_DEFAULT | \
230 V_MC_CLOCK_DRIVE_DEFAULT | \ 230 V_MC_CLOCK_DRIVE_DEFAULT | \
231 V_MC_REF_RATE_DEFAULT 231 V_MC_REF_RATE_DEFAULT
232 232
233 233
234 234
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 5d496c6faba6..9db80cd13a79 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Register Definitions File: sb1250_regs.h 4 * Register Definitions File: sb1250_regs.h
5 * 5 *
6 * This module contains the addresses of the on-chip peripherals 6 * This module contains the addresses of the on-chip peripherals
7 * on the SB1250. 7 * on the SB1250.
8 * 8 *
9 * SB1250 specification level: 01/02/2002 9 * SB1250 specification level: 01/02/2002
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -40,20 +40,20 @@
40 40
41/* ********************************************************************* 41/* *********************************************************************
42 * Some general notes: 42 * Some general notes:
43 * 43 *
44 * For the most part, when there is more than one peripheral 44 * For the most part, when there is more than one peripheral
45 * of the same type on the SOC, the constants below will be 45 * of the same type on the SOC, the constants below will be
46 * offsets from the base of each peripheral. For example, 46 * offsets from the base of each peripheral. For example,
47 * the MAC registers are described as offsets from the first 47 * the MAC registers are described as offsets from the first
48 * MAC register, and there will be a MAC_REGISTER() macro 48 * MAC register, and there will be a MAC_REGISTER() macro
49 * to calculate the base address of a given MAC. 49 * to calculate the base address of a given MAC.
50 * 50 *
51 * The information in this file is based on the SB1250 SOC 51 * The information in this file is based on the SB1250 SOC
52 * manual version 0.2, July 2000. 52 * manual version 0.2, July 2000.
53 ********************************************************************* */ 53 ********************************************************************* */
54 54
55 55
56/* ********************************************************************* 56/* *********************************************************************
57 * Memory Controller Registers 57 * Memory Controller Registers
58 ********************************************************************* */ 58 ********************************************************************* */
59 59
@@ -101,7 +101,7 @@
101#define R_MC_TEST_ECC 0x0000000420 101#define R_MC_TEST_ECC 0x0000000420
102#define R_MC_MCLK_CFG 0x0000000500 102#define R_MC_MCLK_CFG 0x0000000500
103 103
104/* ********************************************************************* 104/* *********************************************************************
105 * L2 Cache Control Registers 105 * L2 Cache Control Registers
106 ********************************************************************* */ 106 ********************************************************************* */
107 107
@@ -126,7 +126,7 @@
126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
127 127
128 128
129/* ********************************************************************* 129/* *********************************************************************
130 * PCI Interface Registers 130 * PCI Interface Registers
131 ********************************************************************* */ 131 ********************************************************************* */
132 132
@@ -134,7 +134,7 @@
134#define A_PCI_TYPE01_HEADER 0x00DE000800 134#define A_PCI_TYPE01_HEADER 0x00DE000800
135 135
136 136
137/* ********************************************************************* 137/* *********************************************************************
138 * Ethernet DMA and MACs 138 * Ethernet DMA and MACs
139 ********************************************************************* */ 139 ********************************************************************* */
140 140
@@ -184,7 +184,7 @@
184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \
185 (reg)) 185 (reg))
186 186
187/* 187/*
188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
189 */ 189 */
190 190
@@ -259,7 +259,7 @@
259#define MAC_CHMAP_COUNT 4 259#define MAC_CHMAP_COUNT 4
260 260
261 261
262/* ********************************************************************* 262/* *********************************************************************
263 * DUART Registers 263 * DUART Registers
264 ********************************************************************* */ 264 ********************************************************************* */
265 265
@@ -363,7 +363,7 @@
363#endif /* 1250 PASS2 || 112x PASS1 */ 363#endif /* 1250 PASS2 || 112x PASS1 */
364 364
365 365
366/* ********************************************************************* 366/* *********************************************************************
367 * Synchronous Serial Registers 367 * Synchronous Serial Registers
368 ********************************************************************* */ 368 ********************************************************************* */
369 369
@@ -397,7 +397,7 @@
397 (reg)) 397 (reg))
398 398
399 399
400/* 400/*
401 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 401 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
402 */ 402 */
403 403
@@ -457,7 +457,7 @@
457#define R_SER_RMON_RX_ERRORS 0x000001F0 457#define R_SER_RMON_RX_ERRORS 0x000001F0
458#define R_SER_RMON_RX_BADADDR 0x000001F8 458#define R_SER_RMON_RX_BADADDR 0x000001F8
459 459
460/* ********************************************************************* 460/* *********************************************************************
461 * Generic Bus Registers 461 * Generic Bus Registers
462 ********************************************************************* */ 462 ********************************************************************* */
463 463
@@ -513,7 +513,7 @@
513#define R_IO_PCMCIA_CFG 0x0A60 513#define R_IO_PCMCIA_CFG 0x0A60
514#define R_IO_PCMCIA_STATUS 0x0A70 514#define R_IO_PCMCIA_STATUS 0x0A70
515 515
516/* ********************************************************************* 516/* *********************************************************************
517 * GPIO Registers 517 * GPIO Registers
518 ********************************************************************* */ 518 ********************************************************************* */
519 519
@@ -537,7 +537,7 @@
537#define R_GPIO_PIN_CLR 0x30 537#define R_GPIO_PIN_CLR 0x30
538#define R_GPIO_PIN_SET 0x38 538#define R_GPIO_PIN_SET 0x38
539 539
540/* ********************************************************************* 540/* *********************************************************************
541 * SMBus Registers 541 * SMBus Registers
542 ********************************************************************* */ 542 ********************************************************************* */
543 543
@@ -573,7 +573,7 @@
573#define R_SMB_CONTROL 0x0000000060 573#define R_SMB_CONTROL 0x0000000060
574#define R_SMB_PEC 0x0000000070 574#define R_SMB_PEC 0x0000000070
575 575
576/* ********************************************************************* 576/* *********************************************************************
577 * Timer Registers 577 * Timer Registers
578 ********************************************************************* */ 578 ********************************************************************* */
579 579
@@ -641,7 +641,7 @@
641#endif /* 1250 PASS2 || 112x PASS1 */ 641#endif /* 1250 PASS2 || 112x PASS1 */
642 642
643 643
644/* ********************************************************************* 644/* *********************************************************************
645 * System Control Registers 645 * System Control Registers
646 ********************************************************************* */ 646 ********************************************************************* */
647 647
@@ -649,7 +649,7 @@
649#define A_SCD_SYSTEM_CFG 0x0010020008 649#define A_SCD_SYSTEM_CFG 0x0010020008
650#define A_SCD_SYSTEM_MANUF 0x0010038000 650#define A_SCD_SYSTEM_MANUF 0x0010038000
651 651
652/* ********************************************************************* 652/* *********************************************************************
653 * System Address Trap Registers 653 * System Address Trap Registers
654 ********************************************************************* */ 654 ********************************************************************* */
655 655
@@ -672,7 +672,7 @@
672#endif /* 1250 PASS2 || 112x PASS1 */ 672#endif /* 1250 PASS2 || 112x PASS1 */
673 673
674 674
675/* ********************************************************************* 675/* *********************************************************************
676 * System Interrupt Mapper Registers 676 * System Interrupt Mapper Registers
677 ********************************************************************* */ 677 ********************************************************************* */
678 678
@@ -701,7 +701,7 @@
701#define R_IMR_INTERRUPT_MAP_BASE 0x0200 701#define R_IMR_INTERRUPT_MAP_BASE 0x0200
702#define R_IMR_INTERRUPT_MAP_COUNT 64 702#define R_IMR_INTERRUPT_MAP_COUNT 64
703 703
704/* ********************************************************************* 704/* *********************************************************************
705 * System Performance Counter Registers 705 * System Performance Counter Registers
706 ********************************************************************* */ 706 ********************************************************************* */
707 707
@@ -711,7 +711,7 @@
711#define A_SCD_PERF_CNT_2 0x00100204E0 711#define A_SCD_PERF_CNT_2 0x00100204E0
712#define A_SCD_PERF_CNT_3 0x00100204E8 712#define A_SCD_PERF_CNT_3 0x00100204E8
713 713
714/* ********************************************************************* 714/* *********************************************************************
715 * System Bus Watcher Registers 715 * System Bus Watcher Registers
716 ********************************************************************* */ 716 ********************************************************************* */
717 717
@@ -726,13 +726,13 @@
726#define A_BUS_L2_ERRORS 0x00100208C0 726#define A_BUS_L2_ERRORS 0x00100208C0
727#define A_BUS_MEM_IO_ERRORS 0x00100208C8 727#define A_BUS_MEM_IO_ERRORS 0x00100208C8
728 728
729/* ********************************************************************* 729/* *********************************************************************
730 * System Debug Controller Registers 730 * System Debug Controller Registers
731 ********************************************************************* */ 731 ********************************************************************* */
732 732
733#define A_SCD_JTAG_BASE 0x0010000000 733#define A_SCD_JTAG_BASE 0x0010000000
734 734
735/* ********************************************************************* 735/* *********************************************************************
736 * System Trace Buffer Registers 736 * System Trace Buffer Registers
737 ********************************************************************* */ 737 ********************************************************************* */
738 738
@@ -755,7 +755,7 @@
755#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 755#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
756#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 756#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
757 757
758/* ********************************************************************* 758/* *********************************************************************
759 * System Generic DMA Registers 759 * System Generic DMA Registers
760 ********************************************************************* */ 760 ********************************************************************* */
761 761
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 22e8041959e2..dbbd682fb47e 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * SCD Constants and Macros File: sb1250_scd.h 4 * SCD Constants and Macros File: sb1250_scd.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module on the 1250. 7 * manipulating the System Control and Debug module on the 1250.
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -130,40 +130,40 @@
130/* System Manufacturing Register 130/* System Manufacturing Register
131* Register: SCD_SYSTEM_MANUF 131* Register: SCD_SYSTEM_MANUF
132*/ 132*/
133 133
134/* Wafer ID: bits 31:0 */ 134/* Wafer ID: bits 31:0 */
135#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 135#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
136#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 136#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
137#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 137#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
138#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 138#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
139 139
140#define S_SYS_BIN _SB_MAKE64(32) 140#define S_SYS_BIN _SB_MAKE64(32)
141#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 141#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
142#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) 142#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN)
143#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 143#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
144 144
145/* Wafer ID: bits 39:36 */ 145/* Wafer ID: bits 39:36 */
146#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 146#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
147#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 147#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
148#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 148#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
149#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 149#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
150 150
151/* Wafer ID: bits 39:0 */ 151/* Wafer ID: bits 39:0 */
152#define S_SYS_WAFERID_300 _SB_MAKE64(0) 152#define S_SYS_WAFERID_300 _SB_MAKE64(0)
153#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 153#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)
154#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 154#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
155#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 155#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
156 156
157#define S_SYS_XPOS _SB_MAKE64(40) 157#define S_SYS_XPOS _SB_MAKE64(40)
158#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 158#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)
159#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 159#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)
160#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 160#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
161 161
162#define S_SYS_YPOS _SB_MAKE64(46) 162#define S_SYS_YPOS _SB_MAKE64(46)
163#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 163#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
164#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 164#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
165#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 165#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
166 166
167/* 167/*
168 * System Config Register (Table 4-2) 168 * System Config Register (Table 4-2)
169 * Register: SCD_SYSTEM_CFG 169 * Register: SCD_SYSTEM_CFG
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 287cbfe9efa2..335c53e92936 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * SMBUS Constants File: sb1250_smbus.h 4 * SMBUS Constants File: sb1250_smbus.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the SB1250's SMbus devices. 7 * manipulating the SB1250's SMbus devices.
8 * 8 *
9 * SB1250 specification level: 01/02/2002 9 * SB1250 specification level: 01/02/2002
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index 8d5e8edd3c4b..fa2760d38b8b 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -7,17 +7,17 @@
7 * manipulating the SB1250's Synchronous Serial 7 * manipulating the SB1250's Synchronous Serial
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 7655d6945cca..923ea4f44e0f 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * UART Constants File: sb1250_uart.h 4 * UART Constants File: sb1250_uart.h
5 * 5 *
6 * This module contains constants and macros useful for 6 * This module contains constants and macros useful for
7 * manipulating the SB1250's UARTs 7 * manipulating the SB1250's UARTs
8 * 8 *
9 * SB1250 specification level: User's manual 1/02/02 9 * SB1250 specification level: User's manual 1/02/02
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -37,7 +37,7 @@
37 37
38#include "sb1250_defs.h" 38#include "sb1250_defs.h"
39 39
40/* ********************************************************************** 40/* **********************************************************************
41 * DUART Registers 41 * DUART Registers
42 ********************************************************************** */ 42 ********************************************************************** */
43 43
@@ -145,7 +145,7 @@
145#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 145#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
146#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 146#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
147 147
148#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 148#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
149 149
150/* 150/*
151 * DUART Status Register (Table 10-6) 151 * DUART Status Register (Table 10-6)
@@ -165,7 +165,7 @@
165 165
166/* 166/*
167 * DUART Baud Rate Register (Table 10-7) 167 * DUART Baud Rate Register (Table 10-7)
168 * Register: DUART_CLK_SEL_A 168 * Register: DUART_CLK_SEL_A
169 * Register: DUART_CLK_SEL_B 169 * Register: DUART_CLK_SEL_B
170 */ 170 */
171 171
@@ -332,7 +332,7 @@
332 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 332 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
333 333
334#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 334#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
335/* 335/*
336 * Full Interrupt Control Register 336 * Full Interrupt Control Register
337 */ 337 */
338 338
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index 18939e84b6f2..f7fbebaa0744 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -10,7 +10,7 @@
10#define _ASM_SIGCONTEXT_H 10#define _ASM_SIGCONTEXT_H
11 11
12#include <asm/sgidefs.h> 12#include <asm/sgidefs.h>
13 13
14#if _MIPS_SIM == _MIPS_SIM_ABI32 14#if _MIPS_SIM == _MIPS_SIM_ABI32
15 15
16/* 16/*
@@ -38,7 +38,7 @@ struct sigcontext {
38}; 38};
39 39
40#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 40#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
41 41
42#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 42#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
43 43
44/* 44/*
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index d478a86294ee..753b6620e6fa 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -82,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
82 * @SOCK_STREAM - stream (connection) socket 82 * @SOCK_STREAM - stream (connection) socket
83 * @SOCK_RAW - raw socket 83 * @SOCK_RAW - raw socket
84 * @SOCK_RDM - reliably-delivered message 84 * @SOCK_RDM - reliably-delivered message
85 * @SOCK_SEQPACKET - sequential packet socket 85 * @SOCK_SEQPACKET - sequential packet socket
86 * @SOCK_PACKET - linux specific way of getting packets at the dev level. 86 * @SOCK_PACKET - linux specific way of getting packets at the dev level.
87 * For writing rarp and other similar things on the user level. 87 * For writing rarp and other similar things on the user level.
88 */ 88 */
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
index 5076fec65780..c3ddf973c1c0 100644
--- a/include/asm-mips/statfs.h
+++ b/include/asm-mips/statfs.h
@@ -57,7 +57,7 @@ struct statfs64 {
57}; 57};
58 58
59#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 59#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
60 60
61#if _MIPS_SIM == _MIPS_SIM_ABI64 61#if _MIPS_SIM == _MIPS_SIM_ABI64
62 62
63struct statfs64 { /* Same as struct statfs */ 63struct statfs64 { /* Same as struct statfs */
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
index fd9599e40a0a..fee1908c65d2 100644
--- a/include/asm-mips/titan_dep.h
+++ b/include/asm-mips/titan_dep.h
@@ -228,4 +228,4 @@ extern unsigned long ocd_base;
228#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) 228#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
229#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) 229#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
230 230
231#endif 231#endif
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 5d939db6e220..3bb7f0087d68 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -45,14 +45,14 @@
45 45
46 46
47/* TX4927 SDRAM controller (64-bit registers) */ 47/* TX4927 SDRAM controller (64-bit registers) */
48#define TX4927_SDRAMC_BASE 0x8000 48#define TX4927_SDRAMC_BASE 0x8000
49#define TX4927_SDRAMC_SDCCR0 0x8000 49#define TX4927_SDRAMC_SDCCR0 0x8000
50#define TX4927_SDRAMC_SDCCR1 0x8008 50#define TX4927_SDRAMC_SDCCR1 0x8008
51#define TX4927_SDRAMC_SDCCR2 0x8010 51#define TX4927_SDRAMC_SDCCR2 0x8010
52#define TX4927_SDRAMC_SDCCR3 0x8018 52#define TX4927_SDRAMC_SDCCR3 0x8018
53#define TX4927_SDRAMC_SDCTR 0x8040 53#define TX4927_SDRAMC_SDCTR 0x8040
54#define TX4927_SDRAMC_SDCMD 0x8058 54#define TX4927_SDRAMC_SDCMD 0x8058
55#define TX4927_SDRAMC_LIMIT 0x8fff 55#define TX4927_SDRAMC_LIMIT 0x8fff
56 56
57 57
58/* TX4927 external bus controller (64-bit registers) */ 58/* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
289 289
290 290
291/* TX4927 serial port 0 (32-bit registers) */ 291/* TX4927 serial port 0 (32-bit registers) */
292#define TX4927_SIO0_BASE 0xf300 292#define TX4927_SIO0_BASE 0xf300
293#define TX4927_SIO0_SILCR0 0xf300 293#define TX4927_SIO0_SILCR0 0xf300
294#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 294#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
295#define TX4927_SIO0_SILCR0_RWUB BM_15_15 295#define TX4927_SIO0_SILCR0_RWUB BM_15_15
296#define TX4927_SIO0_SILCR0_TWUB BM_14_14 296#define TX4927_SIO0_SILCR0_TWUB BM_14_14
@@ -309,7 +309,7 @@
309#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) 309#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
310#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 310#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
311#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 311#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
312#define TX4927_SIO0_SIDICR0 0xf304 312#define TX4927_SIO0_SIDICR0 0xf304
313#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 313#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
314#define TX4927_SIO0_SIDICR0_TDE BM_15_15 314#define TX4927_SIO0_SIDICR0_TDE BM_15_15
315#define TX4927_SIO0_SIDICR0_RDE BM_14_14 315#define TX4927_SIO0_SIDICR0_RDE BM_14_14
@@ -330,7 +330,7 @@
330#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 330#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
331#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 331#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
332#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 332#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
333#define TX4927_SIO0_SIDISR0 0xf308 333#define TX4927_SIO0_SIDISR0 0xf308
334#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 334#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
335#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 335#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
336#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 336#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
@@ -344,7 +344,7 @@
344#define TX4927_SIO0_SIDISR0_STIS BM_06_06 344#define TX4927_SIO0_SIDISR0_STIS BM_06_06
345#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 345#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
346#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 346#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
347#define TX4927_SIO0_SISCISR0 0xf30c 347#define TX4927_SIO0_SISCISR0 0xf30c
348#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 348#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
349#define TX4927_SIO0_SISCISR0_OERS BM_05_05 349#define TX4927_SIO0_SISCISR0_OERS BM_05_05
350#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 350#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
@@ -352,7 +352,7 @@
352#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 352#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
353#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 353#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
354#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 354#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
355#define TX4927_SIO0_SIFCR0 0xf310 355#define TX4927_SIO0_SIFCR0 0xf310
356#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 356#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
357#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 357#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
358#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 358#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
@@ -370,7 +370,7 @@
370#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 370#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
371#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 371#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
372#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 372#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
373#define TX4927_SIO0_SIFLCR0 0xf314 373#define TX4927_SIO0_SIFLCR0 0xf314
374#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 374#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
375#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 375#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
376#define TX4927_SIO0_SIFLCR0_TES BM_11_11 376#define TX4927_SIO0_SIFLCR0_TES BM_11_11
@@ -381,7 +381,7 @@
381#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 381#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
382#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 382#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
383#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 383#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
384#define TX4927_SIO0_SIBGR0 0xf318 384#define TX4927_SIO0_SIBGR0 0xf318
385#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 385#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
386#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 386#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
387#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) 387#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
@@ -389,28 +389,28 @@
389#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 389#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
390#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 390#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
391#define TX4927_SIO0_SIBGR0_BRD BM_00_07 391#define TX4927_SIO0_SIBGR0_BRD BM_00_07
392#define TX4927_SIO0_SITFIF00 0xf31c 392#define TX4927_SIO0_SITFIF00 0xf31c
393#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 393#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
394#define TX4927_SIO0_SITFIF00_TXD BM_00_07 394#define TX4927_SIO0_SITFIF00_TXD BM_00_07
395#define TX4927_SIO0_SIRFIFO0 0xf320 395#define TX4927_SIO0_SIRFIFO0 0xf320
396#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 396#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
397#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 397#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
398#define TX4927_SIO0_SIRFIFO0 0xf320 398#define TX4927_SIO0_SIRFIFO0 0xf320
399#define TX4927_SIO0_LIMIT 0xf3ff 399#define TX4927_SIO0_LIMIT 0xf3ff
400 400
401 401
402/* TX4927 serial port 1 (32-bit registers) */ 402/* TX4927 serial port 1 (32-bit registers) */
403#define TX4927_SIO1_BASE 0xf400 403#define TX4927_SIO1_BASE 0xf400
404#define TX4927_SIO1_SILCR1 0xf400 404#define TX4927_SIO1_SILCR1 0xf400
405#define TX4927_SIO1_SIDICR1 0xf404 405#define TX4927_SIO1_SIDICR1 0xf404
406#define TX4927_SIO1_SIDISR1 0xf408 406#define TX4927_SIO1_SIDISR1 0xf408
407#define TX4927_SIO1_SISCISR1 0xf40c 407#define TX4927_SIO1_SISCISR1 0xf40c
408#define TX4927_SIO1_SIFCR1 0xf410 408#define TX4927_SIO1_SIFCR1 0xf410
409#define TX4927_SIO1_SIFLCR1 0xf414 409#define TX4927_SIO1_SIFLCR1 0xf414
410#define TX4927_SIO1_SIBGR1 0xf418 410#define TX4927_SIO1_SIBGR1 0xf418
411#define TX4927_SIO1_SITFIF01 0xf41c 411#define TX4927_SIO1_SITFIF01 0xf41c
412#define TX4927_SIO1_SIRFIFO1 0xf420 412#define TX4927_SIO1_SIRFIFO1 0xf420
413#define TX4927_SIO1_LIMIT 0xf4ff 413#define TX4927_SIO1_LIMIT 0xf4ff
414 414
415 415
416/* TX4927 parallel port (32-bit registers) */ 416/* TX4927 parallel port (32-bit registers) */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 170433492246..165f6b8b217f 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 6 * Copyright (C) 2000-2001 Toshiba Corporation
7 */ 7 */
8#ifndef __ASM_TX4927_TX4927_PCI_H 8#ifndef __ASM_TX4927_TX4927_PCI_H
9#define __ASM_TX4927_TX4927_PCI_H 9#define __ASM_TX4927_TX4927_PCI_H
10 10
11#define TX4927_CCFG_TOE 0x00004000 11#define TX4927_CCFG_TOE 0x00004000
12 12
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
index 58e193c51b45..bb7a85c186e4 100644
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ b/include/asm-mips/vr41xx/vrc4173.h
@@ -21,8 +21,8 @@
21 * along with this program; if not, write to the Free Software 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */ 23 */
24#ifndef __NEC_VRC4173_H 24#ifndef __NEC_VRC4173_H
25#define __NEC_VRC4173_H 25#define __NEC_VRC4173_H
26 26
27#include <linux/config.h> 27#include <linux/config.h>
28#include <asm/io.h> 28#include <asm/io.h>
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c4a704121343..04ee53b34c2e 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
113 */ 113 */
114#define BCM1250_M3_WAR 1 114#define BCM1250_M3_WAR 1
115 115
116/* 116/*
117 * This is a DUART workaround related to glitches around register accesses 117 * This is a DUART workaround related to glitches around register accesses
118 */ 118 */
119#define SIBYTE_1956_WAR 1 119#define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
122 122
123/* 123/*
124 * Fill buffers not flushed on CACHE instructions 124 * Fill buffers not flushed on CACHE instructions
125 * 125 *
126 * Hit_Invalidate_I cacheops invalidate an icache line but the refill 126 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
127 * for that line can get stale data from the fill buffer instead of 127 * for that line can get stale data from the fill buffer instead of
128 * accessing memory if the previous icache miss was also to that line. 128 * accessing memory if the previous icache miss was also to that line.
diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h
index 75c0ddfeca13..4d84a90b0f20 100644
--- a/include/asm-mips/xxs1500.h
+++ b/include/asm-mips/xxs1500.h
@@ -22,7 +22,7 @@
22 * 22 *
23 * ######################################################################## 23 * ########################################################################
24 * 24 *
25 * 25 *
26 */ 26 */
27#ifndef __ASM_XXS1500_H 27#ifndef __ASM_XXS1500_H
28#define __ASM_XXS1500_H 28#define __ASM_XXS1500_H