360 files changed, 57431 insertions, 0 deletions

diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
new file mode 100644
index 000000000000..285f78488ccb
--- /dev/null
+++ b/include/asm-mips/8253pit.h
@@ -0,0 +1,10 @@
+/*
+ * 8253/8254 Programmable Interval Timer
+ */
+
+#ifndef _8253PIT_H
+#define _8253PIT_H
+
+#define PIT_TICK_RATE   1193182UL
+
+#endif
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h
new file mode 100644
index 000000000000..e42b3093e903
--- /dev/null
+++ b/include/asm-mips/a.out.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_A_OUT_H
+#define _ASM_A_OUT_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#endif
+
+struct exec
+{
+        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
+        unsigned a_text;        /* length of text, in bytes */
+        unsigned a_data;        /* length of data, in bytes */
+        unsigned a_bss;         /* length of uninitialized data area for
+                                    file, in bytes */
+        unsigned a_syms;        /* length of symbol table data in file,
+                                   in bytes */
+        unsigned a_entry;       /* start address */
+        unsigned a_trsize;      /* length of relocation info for text, in
+                                    bytes */
+        unsigned a_drsize;      /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_MIPS32
+#define STACK_TOP       TASK_SIZE
+#endif
+#ifdef CONFIG_MIPS64
+#define STACK_TOP       (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
+#endif
+
+#endif
+
+#endif /* _ASM_A_OUT_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
new file mode 100644
index 000000000000..2caa8c427204
--- /dev/null
+++ b/include/asm-mips/addrspace.h
@@ -0,0 +1,187 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ADDRSPACE_H
+#define _ASM_ADDRSPACE_H
+
+#include <linux/config.h>
+#include <spaces.h>
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#else
+#define _ATYPE_         __PTRDIFF_TYPE__
+#define _ATYPE32_       int
+#define _ATYPE64_       long long
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_               (_ATYPE_)(_ATYPE32_)    /* widen if necessary */
+#define _ACAST64_               (_ATYPE64_)             /* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)                ((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)            ((_ACAST32_ (a)) & 0x1fffffff)
+#define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
+
+#ifdef CONFIG_MIPS64
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG                  0x0000000000000000
+#define XKSSEG                  0x4000000000000000
+#define XKPHYS                  0x8000000000000000
+#define XKSEG                   0xc000000000000000
+#define CKSEG0                  0xffffffff80000000
+#define CKSEG1                  0xffffffffa0000000
+#define CKSSEG                  0xffffffffc0000000
+#define CKSEG3                  0xffffffffe0000000
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)            (CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)            (CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)            (CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)            (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG                   0x00000000
+#define KSEG0                   0x80000000
+#define KSEG1                   0xa0000000
+#define KSEG2                   0xc0000000
+#define KSEG3                   0xe0000000
+
+#define CKUSEG                  0x00000000
+#define CKSEG0                  0x80000000
+#define CKSEG1                  0xa0000000
+#define CKSEG2                  0xc0000000
+#define CKSEG3                  0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2   0
+#define K_CALG_COH_SHRL1_NOL2   1
+#define K_CALG_UNCACHED         2
+#define K_CALG_NONCOHERENT      3
+#define K_CALG_COH_EXCL         4
+#define K_CALG_COH_SHAREABLE    5
+#define K_CALG_NOTUSED          6
+#define K_CALG_UNCACHED_ACCEL   7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
+#define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
+#define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm,a)            (0x8000000000000000 | ((cm)<<59) | (a))
+
+#if defined (CONFIG_CPU_R4300)                                          \
+    || defined (CONFIG_CPU_R4X00)                                       \
+    || defined (CONFIG_CPU_R5000)                                       \
+    || defined (CONFIG_CPU_NEVADA)                                      \
+    || defined (CONFIG_CPU_TX49XX)                                      \
+    || defined (CONFIG_CPU_MIPS64)
+#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define K0SIZE                  0x0000001000000000      /* 2^^36 */
+#define K1SIZE                  0x0000001000000000      /* 2^^36 */
+#define K2SIZE                  0x000000ff80000000
+#define KSEGSIZE                0x000000ff80000000      /* max syssegsz */
+#define TO_PHYS_MASK            0x0000000fffffffff      /* 2^^36 - 1 */
+#endif
+
+#if defined (CONFIG_CPU_R8000)
+/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
+#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define K0SIZE                  0x0000010000000000      /* 2^^40 */
+#define K1SIZE                  0x0000010000000000      /* 2^^40 */
+#define K2SIZE                  0x0001000000000000
+#define KSEGSIZE                0x0000010000000000      /* max syssegsz */
+#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#endif
+
+#if defined (CONFIG_CPU_R10000)
+#define KUSIZE                  0x0000010000000000      /* 2^^40 */
+#define KUSIZE_64               0x0000010000000000      /* 2^^40 */
+#define K0SIZE                  0x0000010000000000      /* 2^^40 */
+#define K1SIZE                  0x0000010000000000      /* 2^^40 */
+#define K2SIZE                  0x00000fff80000000
+#define KSEGSIZE                0x00000fff80000000      /* max syssegsz */
+#define TO_PHYS_MASK            0x000000ffffffffff      /* 2^^40 - 1 */
+#endif
+
+/*
+ * Further names for SGI source compatibility.  These are stolen from
+ * IRIX's <sys/mips_addrspace.h>.
+ */
+#define KUBASE                  0
+#define KUSIZE_32               0x0000000080000000      /* KUSIZE
+                                                           for a 32 bit proc */
+#define K0BASE_EXL_WR           0xa800000000000000      /* exclusive on write */
+#define K0BASE_NONCOH           0x9800000000000000      /* noncoherent */
+#define K0BASE_EXL              0xa000000000000000      /* exclusive */
+
+#ifndef CONFIG_CPU_R8000
+
+/*
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
+ */
+
+#define COMPAT_K1BASE32         0xffffffffa0000000
+#define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)          (_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)           (_ACAST64_ (x) | CAC_BASE)
+
+#endif /* _ASM_ADDRSPACE_H */
diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/arc/hinv.h
new file mode 100644
index 000000000000..ee792bf04002
--- /dev/null
+++ b/include/asm-mips/arc/hinv.h
@@ -0,0 +1,174 @@
+/*
+ * ARCS hardware/memory inventory/configuration and system ID definitions.
+ */
+#ifndef _ASM_ARC_HINV_H
+#define _ASM_ARC_HINV_H
+
+#include <asm/arc/types.h>
+
+/* configuration query defines */
+typedef enum configclass {
+        SystemClass,
+        ProcessorClass,
+        CacheClass,
+#ifndef _NT_PROM
+        MemoryClass,
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass
+#else   /* _NT_PROM */
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass,
+        MemoryClass
+#endif  /* _NT_PROM */
+} CONFIGCLASS;
+
+typedef enum configtype {
+        ARC,
+        CPU,
+        FPU,
+        PrimaryICache,
+        PrimaryDCache,
+        SecondaryICache,
+        SecondaryDCache,
+        SecondaryCache,
+#ifndef _NT_PROM
+        Memory,
+#endif
+        EISAAdapter,
+        TCAdapter,
+        SCSIAdapter,
+        DTIAdapter,
+        MultiFunctionAdapter,
+        DiskController,
+        TapeController,
+        CDROMController,
+        WORMController,
+        SerialController,
+        NetworkController,
+        DisplayController,
+        ParallelController,
+        PointerController,
+        KeyboardController,
+        AudioController,
+        OtherController,
+        DiskPeripheral,
+        FloppyDiskPeripheral,
+        TapePeripheral,
+        ModemPeripheral,
+        MonitorPeripheral,
+        PrinterPeripheral,
+        PointerPeripheral,
+        KeyboardPeripheral,
+        TerminalPeripheral,
+        LinePeripheral,
+        NetworkPeripheral,
+#ifdef  _NT_PROM
+        Memory,
+#endif
+        OtherPeripheral,
+
+        /* new stuff for IP30 */
+        /* added without moving anything */
+        /* except ANONYMOUS. */
+
+        XTalkAdapter,
+        PCIAdapter,
+        GIOAdapter,
+        TPUAdapter,
+
+        Anonymous
+} CONFIGTYPE;
+
+typedef enum {
+        Failed = 1,
+        ReadOnly = 2,
+        Removable = 4,
+        ConsoleIn = 8,
+        ConsoleOut = 16,
+        Input = 32,
+        Output = 64
+} IDENTIFIERFLAG;
+
+#ifndef NULL                    /* for GetChild(NULL); */
+#define NULL    0
+#endif
+
+union key_u {
+        struct {
+#ifdef  _MIPSEB
+                unsigned char  c_bsize;         /* block size in lines */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned short c_size;          /* cache size in 4K pages */
+#else   /* _MIPSEL */
+                unsigned short c_size;          /* cache size in 4K pages */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned char  c_bsize;         /* block size in lines */
+#endif  /* _MIPSEL */
+        } cache;
+        ULONG FullKey;
+};
+
+#if _MIPS_SIM == _ABI64
+#define SGI_ARCS_VERS   64                      /* sgi 64-bit version */
+#define SGI_ARCS_REV    0                       /* rev .00 */
+#else
+#define SGI_ARCS_VERS   1                       /* first version */
+#define SGI_ARCS_REV    10                      /* rev .10, 3/04/92 */
+#endif
+
+typedef struct component {
+        CONFIGCLASS     Class;
+        CONFIGTYPE      Type;
+        IDENTIFIERFLAG  Flags;
+        USHORT          Version;
+        USHORT          Revision;
+        ULONG           Key;
+        ULONG           AffinityMask;
+        ULONG           ConfigurationDataSize;
+        ULONG           IdentifierLength;
+        char            *Identifier;
+} COMPONENT;
+
+/* internal structure that holds pathname parsing data */
+struct cfgdata {
+        char *name;                     /* full name */
+        int minlen;                     /* minimum length to match */
+        CONFIGTYPE type;                /* type of token */
+};
+
+/* System ID */
+typedef struct systemid {
+        CHAR VendorId[8];
+        CHAR ProductId[8];
+} SYSTEMID;
+
+/* memory query functions */
+typedef enum memorytype {
+        ExceptionBlock,
+        SPBPage,                        /* ARCS == SystemParameterBlock */
+#ifndef _NT_PROM
+        FreeContiguous,
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent
+#else   /* _NT_PROM */
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent,
+        FreeContiguous
+#endif  /* _NT_PROM */
+} MEMORYTYPE;
+
+typedef struct memorydescriptor {
+        MEMORYTYPE      Type;
+        LONG            BasePage;
+        LONG            PageCount;
+} MEMORYDESCRIPTOR;
+
+#endif /* _ASM_ARC_HINV_H */
diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/arc/types.h
new file mode 100644
index 000000000000..bbb725c366fb
--- /dev/null
+++ b/include/asm-mips/arc/types.h
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ARC_TYPES_H
+#define _ASM_ARC_TYPES_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_ARC32
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__SI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__SI__)));
+typedef void            VOID;
+
+/* The pointer types.  Note that we're using a 64-bit compiler but all
+   pointer in the ARC structures are only 32-bit, so we need some disgusting
+   workarounds.  Keep your vomit bag handy.  */
+typedef LONG            _PCHAR;
+typedef LONG            _PSHORT;
+typedef LONG            _PLARGE_INTEGER;
+typedef LONG            _PLONG;
+typedef LONG            _PUCHAR;
+typedef LONG            _PUSHORT;
+typedef LONG            _PULONG;
+typedef LONG            _PVOID;
+
+#endif /* CONFIG_ARC32 */
+
+#ifdef CONFIG_ARC64
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__DI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__DI__)));
+typedef void            VOID;
+
+/* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
+   live is sane ...  */
+typedef CHAR            *_PCHAR;
+typedef SHORT           *_PSHORT;
+typedef LARGE_INTEGER   *_PLARGE_INTEGER;
+typedef LONG            *_PLONG;
+typedef UCHAR           *_PUCHAR;
+typedef USHORT          *_PUSHORT;
+typedef ULONG           *_PULONG;
+typedef VOID            *_PVOID;
+
+#endif /* CONFIG_ARC64  */
+
+typedef CHAR            *PCHAR;
+typedef SHORT           *PSHORT;
+typedef LARGE_INTEGER   *PLARGE_INTEGER;
+typedef LONG            *PLONG;
+typedef UCHAR           *PUCHAR;
+typedef USHORT          *PUSHORT;
+typedef ULONG           *PULONG;
+typedef VOID            *PVOID;
+
+/*
+ * Return type of ArcGetDisplayStatus()
+ */
+typedef struct {
+        USHORT  CursorXPosition;
+        USHORT  CursorYPosition;
+        USHORT  CursorMaxXPosition;
+        USHORT  CursorMaxYPosition;
+        USHORT  ForegroundColor;
+        USHORT  BackgroundColor;
+        UCHAR   HighIntensity;
+        UCHAR   Underscored;
+        UCHAR   ReverseVideo;
+} DISPLAY_STATUS;
+
+#endif /* _ASM_ARC_TYPES_H */
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
new file mode 100644
index 000000000000..f53237772985
--- /dev/null
+++ b/include/asm-mips/asm.h
@@ -0,0 +1,396 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_ASM_H
+#define __ASM_ASM_H
+
+#include <linux/config.h>
+#include <asm/sgidefs.h>
+
+#ifndef CAT
+#ifdef __STDC__
+#define __CAT(str1,str2) str1##str2
+#else
+#define __CAT(str1,str2) str1/**/str2
+#endif
+#define CAT(str1,str2) __CAT(str1,str2)
+#endif
+
+/*
+ * PIC specific declarations
+ * Not used for the kernel but here seems to be the right place.
+ */
+#ifdef __PIC__
+#define CPRESTORE(register)                             \
+                .cprestore register
+#define CPADD(register)                                 \
+                .cpadd  register
+#define CPLOAD(register)                                \
+                .cpload register
+#else
+#define CPRESTORE(register)
+#define CPADD(register)
+#define CPLOAD(register)
+#endif
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define LEAF(symbol)                                    \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol,@function;               \
+                .ent    symbol,0;                       \
+symbol:         .frame  sp,0,ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define NESTED(symbol, framesize, rpc)                  \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol,@function;               \
+                .ent    symbol,0;                       \
+symbol:         .frame  sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define END(function)                                   \
+                .end    function;                       \
+                .size   function,.-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)                                  \
+                .globl  symbol;                         \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)                                 \
+                .globl  symbol;                         \
+                .type   symbol,@function;               \
+symbol:
+
+/*
+ * ABS - export absolute symbol
+ */
+#define ABS(symbol,value)                               \
+                .globl  symbol;                         \
+symbol          =       value
+
+#define PANIC(msg)                                      \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0,8f;                          \
+                jal     panic;                          \
+9:              b       9b;                             \
+                .set    pop;                            \
+                TEXT(msg)
+
+/*
+ * Print formatted string
+ */
+#define PRINT(string)                                   \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0,8f;                          \
+                jal     printk;                         \
+                .set    pop;                            \
+                TEXT(string)
+
+#define TEXT(msg)                                       \
+                .pushsection .data;                     \
+8:              .asciiz msg;                            \
+                .popsection;
+
+/*
+ * Build text tables
+ */
+#define TTABLE(string)                                  \
+                .pushsection .text;                     \
+                .word   1f;                             \
+                .popsection                             \
+                .pushsection .data;                     \
+1:              .asciiz string;                         \
+                .popsection
+
+/*
+ * MIPS IV pref instruction.
+ * Use with .set noreorder only!
+ *
+ * MIPS IV implementations are free to treat this as a nop.  The R5000
+ * is one of them.  So we should have an option not to use this instruction.
+ */
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define PREF(hint,addr)                                 \
+                .set    push;                           \
+                .set    mips4;                          \
+                pref    hint,addr;                      \
+                .set    pop
+
+#define PREFX(hint,addr)                                \
+                .set    push;                           \
+                .set    mips4;                          \
+                prefx   hint,addr;                      \
+                .set    pop
+
+#else /* !CONFIG_CPU_HAS_PREFETCH */
+
+#define PREF(hint,addr)
+#define PREFX(hint,addr)
+
+#endif /* !CONFIG_CPU_HAS_PREFETCH */
+
+/*
+ * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
+#define MOVN(rd,rs,rt)                                  \
+                .set    push;                           \
+                .set    reorder;                        \
+                beqz    rt,9f;                          \
+                move    rd,rs;                          \
+                .set    pop;                            \
+9:
+#define MOVZ(rd,rs,rt)                                  \
+                .set    push;                           \
+                .set    reorder;                        \
+                bnez    rt,9f;                          \
+                move    rd,rs;                          \
+                .set    pop;                            \
+9:
+#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
+#define MOVN(rd,rs,rt)                                  \
+                .set    push;                           \
+                .set    noreorder;                      \
+                bnezl   rt,9f;                          \
+                 move   rd,rs;                          \
+                .set    pop;                            \
+9:
+#define MOVZ(rd,rs,rt)                                  \
+                .set    push;                           \
+                .set    noreorder;                      \
+                beqzl   rt,9f;                          \
+                 move   rd,rs;                          \
+                .set    pop;                            \
+9:
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#define MOVN(rd,rs,rt)                                  \
+                movn    rd,rs,rt
+#define MOVZ(rd,rs,rt)                                  \
+                movz    rd,rs,rt
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define ALSZ    7
+#define ALMASK  ~7
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define ALSZ    15
+#define ALMASK  ~15
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#ifdef __mips64
+#define SZREG   8
+#else
+#define SZREG   4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define REG_S           sw
+#define REG_L           lw
+#define REG_SUBU        subu
+#define REG_ADDU        addu
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define REG_S           sd
+#define REG_L           ld
+#define REG_SUBU        dsubu
+#define REG_ADDU        daddu
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+#define INT_ADD         add
+#define INT_ADDU        addu
+#define INT_ADDI        addi
+#define INT_ADDIU       addiu
+#define INT_SUB         sub
+#define INT_SUBU        subu
+#define INT_L           lw
+#define INT_S           sw
+#define INT_SLL         sll
+#define INT_SLLV        sllv
+#define INT_SRL         srl
+#define INT_SRLV        srlv
+#define INT_SRA         sra
+#define INT_SRAV        srav
+#endif
+
+#if (_MIPS_SZINT == 64)
+#define INT_ADD         dadd
+#define INT_ADDU        daddu
+#define INT_ADDI        daddi
+#define INT_ADDIU       daddiu
+#define INT_SUB         dsub
+#define INT_SUBU        dsubu
+#define INT_L           ld
+#define INT_S           sd
+#define INT_SLL         dsll
+#define INT_SLLV        dsllv
+#define INT_SRL         dsrl
+#define INT_SRLV        dsrlv
+#define INT_SRA         dsra
+#define INT_SRAV        dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+#define LONG_ADD        add
+#define LONG_ADDU       addu
+#define LONG_ADDI       addi
+#define LONG_ADDIU      addiu
+#define LONG_SUB        sub
+#define LONG_SUBU       subu
+#define LONG_L          lw
+#define LONG_S          sw
+#define LONG_SLL        sll
+#define LONG_SLLV       sllv
+#define LONG_SRL        srl
+#define LONG_SRLV       srlv
+#define LONG_SRA        sra
+#define LONG_SRAV       srav
+
+#define LONG            .word
+#define LONGSIZE        4
+#define LONGMASK        3
+#define LONGLOG         2
+#endif
+
+#if (_MIPS_SZLONG == 64)
+#define LONG_ADD        dadd
+#define LONG_ADDU       daddu
+#define LONG_ADDI       daddi
+#define LONG_ADDIU      daddiu
+#define LONG_SUB        dsub
+#define LONG_SUBU       dsubu
+#define LONG_L          ld
+#define LONG_S          sd
+#define LONG_SLL        dsll
+#define LONG_SLLV       dsllv
+#define LONG_SRL        dsrl
+#define LONG_SRLV       dsrlv
+#define LONG_SRA        dsra
+#define LONG_SRAV       dsrav
+
+#define LONG            .dword
+#define LONGSIZE        8
+#define LONGMASK        7
+#define LONGLOG         3
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD         add
+#define PTR_ADDU        addu
+#define PTR_ADDI        addi
+#define PTR_ADDIU       addiu
+#define PTR_SUB         sub
+#define PTR_SUBU        subu
+#define PTR_L           lw
+#define PTR_S           sw
+#define PTR_LA          la
+#define PTR_SLL         sll
+#define PTR_SLLV        sllv
+#define PTR_SRL         srl
+#define PTR_SRLV        srlv
+#define PTR_SRA         sra
+#define PTR_SRAV        srav
+
+#define PTR_SCALESHIFT  2
+
+#define PTR             .word
+#define PTRSIZE         4
+#define PTRLOG          2
+#endif
+
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD         dadd
+#define PTR_ADDU        daddu
+#define PTR_ADDI        daddi
+#define PTR_ADDIU       daddiu
+#define PTR_SUB         dsub
+#define PTR_SUBU        dsubu
+#define PTR_L           ld
+#define PTR_S           sd
+#define PTR_LA          dla
+#define PTR_SLL         dsll
+#define PTR_SLLV        dsllv
+#define PTR_SRL         dsrl
+#define PTR_SRLV        dsrlv
+#define PTR_SRA         dsra
+#define PTR_SRAV        dsrav
+
+#define PTR_SCALESHIFT  3
+
+#define PTR             .dword
+#define PTRSIZE         8
+#define PTRLOG          3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define MFC0            mfc0
+#define MTC0            mtc0
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define MFC0            dmfc0
+#define MTC0            dmtc0
+#endif
+
+#define SSNOP           sll zero,zero,1
+
+#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
new file mode 100644
index 000000000000..ac8823df2554
--- /dev/null
+++ b/include/asm-mips/asmmacro-32.h
@@ -0,0 +1,158 @@
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1998, 1999, 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_32_H
+#define _ASM_ASMMACRO_32_H
+
+#include <asm/offset.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  fpu_save_double thread status tmp1=t0 tmp2
+        cfc1    \tmp1,  fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp1, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_save_single thread tmp=t0
+        cfc1    \tmp,  fcr31
+        swc1    $f0,  THREAD_FPR0(\thread)
+        swc1    $f1,  THREAD_FPR1(\thread)
+        swc1    $f2,  THREAD_FPR2(\thread)
+        swc1    $f3,  THREAD_FPR3(\thread)
+        swc1    $f4,  THREAD_FPR4(\thread)
+        swc1    $f5,  THREAD_FPR5(\thread)
+        swc1    $f6,  THREAD_FPR6(\thread)
+        swc1    $f7,  THREAD_FPR7(\thread)
+        swc1    $f8,  THREAD_FPR8(\thread)
+        swc1    $f9,  THREAD_FPR9(\thread)
+        swc1    $f10, THREAD_FPR10(\thread)
+        swc1    $f11, THREAD_FPR11(\thread)
+        swc1    $f12, THREAD_FPR12(\thread)
+        swc1    $f13, THREAD_FPR13(\thread)
+        swc1    $f14, THREAD_FPR14(\thread)
+        swc1    $f15, THREAD_FPR15(\thread)
+        swc1    $f16, THREAD_FPR16(\thread)
+        swc1    $f17, THREAD_FPR17(\thread)
+        swc1    $f18, THREAD_FPR18(\thread)
+        swc1    $f19, THREAD_FPR19(\thread)
+        swc1    $f20, THREAD_FPR20(\thread)
+        swc1    $f21, THREAD_FPR21(\thread)
+        swc1    $f22, THREAD_FPR22(\thread)
+        swc1    $f23, THREAD_FPR23(\thread)
+        swc1    $f24, THREAD_FPR24(\thread)
+        swc1    $f25, THREAD_FPR25(\thread)
+        swc1    $f26, THREAD_FPR26(\thread)
+        swc1    $f27, THREAD_FPR27(\thread)
+        swc1    $f28, THREAD_FPR28(\thread)
+        swc1    $f29, THREAD_FPR29(\thread)
+        swc1    $f30, THREAD_FPR30(\thread)
+        swc1    $f31, THREAD_FPR31(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_restore_double thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  fpu_restore_single thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        lwc1    $f0,  THREAD_FPR0(\thread)
+        lwc1    $f1,  THREAD_FPR1(\thread)
+        lwc1    $f2,  THREAD_FPR2(\thread)
+        lwc1    $f3,  THREAD_FPR3(\thread)
+        lwc1    $f4,  THREAD_FPR4(\thread)
+        lwc1    $f5,  THREAD_FPR5(\thread)
+        lwc1    $f6,  THREAD_FPR6(\thread)
+        lwc1    $f7,  THREAD_FPR7(\thread)
+        lwc1    $f8,  THREAD_FPR8(\thread)
+        lwc1    $f9,  THREAD_FPR9(\thread)
+        lwc1    $f10, THREAD_FPR10(\thread)
+        lwc1    $f11, THREAD_FPR11(\thread)
+        lwc1    $f12, THREAD_FPR12(\thread)
+        lwc1    $f13, THREAD_FPR13(\thread)
+        lwc1    $f14, THREAD_FPR14(\thread)
+        lwc1    $f15, THREAD_FPR15(\thread)
+        lwc1    $f16, THREAD_FPR16(\thread)
+        lwc1    $f17, THREAD_FPR17(\thread)
+        lwc1    $f18, THREAD_FPR18(\thread)
+        lwc1    $f19, THREAD_FPR19(\thread)
+        lwc1    $f20, THREAD_FPR20(\thread)
+        lwc1    $f21, THREAD_FPR21(\thread)
+        lwc1    $f22, THREAD_FPR22(\thread)
+        lwc1    $f23, THREAD_FPR23(\thread)
+        lwc1    $f24, THREAD_FPR24(\thread)
+        lwc1    $f25, THREAD_FPR25(\thread)
+        lwc1    $f26, THREAD_FPR26(\thread)
+        lwc1    $f27, THREAD_FPR27(\thread)
+        lwc1    $f28, THREAD_FPR28(\thread)
+        lwc1    $f29, THREAD_FPR29(\thread)
+        lwc1    $f30, THREAD_FPR30(\thread)
+        lwc1    $f31, THREAD_FPR31(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_32_H */
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
new file mode 100644
index 000000000000..bbed35511f5a
--- /dev/null
+++ b/include/asm-mips/asmmacro-64.h
@@ -0,0 +1,140 @@
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1998, 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ASMMACRO_64_H
+#define _ASM_ASMMACRO_64_H
+
+#include <asm/offset.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  fpu_save_16even thread tmp=t0
+        cfc1    \tmp, fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_save_16odd thread
+        sdc1    $f1,  THREAD_FPR1(\thread)
+        sdc1    $f3,  THREAD_FPR3(\thread)
+        sdc1    $f5,  THREAD_FPR5(\thread)
+        sdc1    $f7,  THREAD_FPR7(\thread)
+        sdc1    $f9,  THREAD_FPR9(\thread)
+        sdc1    $f11, THREAD_FPR11(\thread)
+        sdc1    $f13, THREAD_FPR13(\thread)
+        sdc1    $f15, THREAD_FPR15(\thread)
+        sdc1    $f17, THREAD_FPR17(\thread)
+        sdc1    $f19, THREAD_FPR19(\thread)
+        sdc1    $f21, THREAD_FPR21(\thread)
+        sdc1    $f23, THREAD_FPR23(\thread)
+        sdc1    $f25, THREAD_FPR25(\thread)
+        sdc1    $f27, THREAD_FPR27(\thread)
+        sdc1    $f29, THREAD_FPR29(\thread)
+        sdc1    $f31, THREAD_FPR31(\thread)
+        .endm
+
+        .macro  fpu_save_double thread status tmp1 tmp2
+        sll     \tmp2, \tmp1, 5
+        bgez    \tmp2, 2f
+        fpu_save_16odd \thread
+2:
+        fpu_save_16even \thread \tmp1                   # clobbers t1
+        .endm
+
+        .macro  fpu_restore_16even thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  fpu_restore_16odd thread
+        ldc1    $f1,  THREAD_FPR1(\thread)
+        ldc1    $f3,  THREAD_FPR3(\thread)
+        ldc1    $f5,  THREAD_FPR5(\thread)
+        ldc1    $f7,  THREAD_FPR7(\thread)
+        ldc1    $f9,  THREAD_FPR9(\thread)
+        ldc1    $f11, THREAD_FPR11(\thread)
+        ldc1    $f13, THREAD_FPR13(\thread)
+        ldc1    $f15, THREAD_FPR15(\thread)
+        ldc1    $f17, THREAD_FPR17(\thread)
+        ldc1    $f19, THREAD_FPR19(\thread)
+        ldc1    $f21, THREAD_FPR21(\thread)
+        ldc1    $f23, THREAD_FPR23(\thread)
+        ldc1    $f25, THREAD_FPR25(\thread)
+        ldc1    $f27, THREAD_FPR27(\thread)
+        ldc1    $f29, THREAD_FPR29(\thread)
+        ldc1    $f31, THREAD_FPR31(\thread)
+        .endm
+
+        .macro  fpu_restore_double thread tmp
+        mfc0    t0, CP0_STATUS
+        sll     t1, t0, 5
+        bgez    t1, 1f                          # 16 register mode?
+
+        fpu_restore_16odd a0
+1:      fpu_restore_16even a0, t0               # clobbers t0
+        .endm
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_64_H */
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
new file mode 100644
index 000000000000..37a460aa0378
--- /dev/null
+++ b/include/asm-mips/asmmacro.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_H
+#define _ASM_ASMMACRO_H
+ 
+#include <linux/config.h>
+#include <asm/hazards.h>
+ 
+#ifdef CONFIG_MIPS32
+#include <asm/asmmacro-32.h>
+#endif
+#ifdef CONFIG_MIPS64
+#include <asm/asmmacro-64.h>
+#endif
+
+        .macro  local_irq_enable reg=t0
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_enable_hazard
+        .endm
+
+        .macro  local_irq_disable reg=t0
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        xori    \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_disable_hazard
+        .endm
+
+#ifdef CONFIG_CPU_SB1
+        .macro  fpu_enable_hazard
+        .set    push
+        .set    noreorder
+        .set    mips2
+        SSNOP
+        bnezl   $0, .+4
+         SSNOP
+        .set    pop
+        .endm
+#else
+        .macro  fpu_enable_hazard
+        .endm
+#endif
+
+#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
new file mode 100644
index 000000000000..7d89e87bc8c6
--- /dev/null
+++ b/include/asm-mips/atomic.h
@@ -0,0 +1,653 @@
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ * But use these as seldom as possible since they are much more slower
+ * than regular operations.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 99, 2000, 03, 04 by Ralf Baechle
+ */
+
+/*
+ * As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in
+ * <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
+ * main big wrapper ...
+ */
+#include <linux/config.h>
+#include <linux/spinlock.h>
+
+#ifndef _ASM_ATOMIC_H
+#define _ASM_ATOMIC_H
+
+#include <asm/cpu-features.h>
+#include <asm/war.h>
+
+extern spinlock_t atomic_lock;
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)    { (i) }
+
+/*
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+#define atomic_read(v)          ((v)->counter)
+
+/*
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+#define atomic_set(v,i)         ((v)->counter = (i))
+
+/*
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static __inline__ void atomic_add(int i, atomic_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %1          # atomic_add            \n"
+                "       addu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %1          # atomic_add            \n"
+                "       addu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                v->counter += i;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+}
+
+/*
+ * atomic_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static __inline__ void atomic_sub(int i, atomic_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %1          # atomic_sub            \n"
+                "       subu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %1          # atomic_sub            \n"
+                "       subu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                v->counter -= i;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+}
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ int atomic_add_return(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_add_return     \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_add_return     \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result += i;
+                v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+static __inline__ int atomic_sub_return(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_sub_return     \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_sub_return     \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result -= i;
+                v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+/*
+ * atomic_sub_if_positive - add integer to atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically test @v and decrement if it is greater than 0.
+ * The function returns the old value of @v minus 1.
+ */
+static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
+                "       subu    %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       sc      %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       sync                                            \n"
+                "1:                                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
+                "       subu    %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       sc      %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       sync                                            \n"
+                "1:                                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result -= i;
+                if (result >= 0)
+                        v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+#define atomic_dec_return(v) atomic_sub_return(1,(v))
+#define atomic_inc_return(v) atomic_add_return(1,(v))
+
+/*
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+/*
+ * atomic_dec_and_test - decrement by 1 and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+
+/*
+ * atomic_dec_if_positive - decrement by 1 if old value positive
+ * @v: pointer of type atomic_t
+ */
+#define atomic_dec_if_positive(v)       atomic_sub_if_positive(1, v)
+
+/*
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc(v) atomic_add(1,(v))
+
+/*
+ * atomic_dec - decrement and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic_dec(v) atomic_sub(1,(v))
+
+/*
+ * atomic_add_negative - add and test if negative
+ * @v: pointer of type atomic_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
+
+#ifdef CONFIG_MIPS64
+
+typedef struct { volatile __s64 counter; } atomic64_t;
+
+#define ATOMIC64_INIT(i)    { (i) }
+
+/*
+ * atomic64_read - read atomic variable
+ * @v: pointer of type atomic64_t
+ *
+ */
+#define atomic64_read(v)        ((v)->counter)
+
+/*
+ * atomic64_set - set atomic variable
+ * @v: pointer of type atomic64_t
+ * @i: required value
+ */
+#define atomic64_set(v,i)       ((v)->counter = (i))
+
+/*
+ * atomic64_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically adds @i to @v.
+ */
+static __inline__ void atomic64_add(long i, atomic64_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %1          # atomic64_add          \n"
+                "       addu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %1          # atomic64_add          \n"
+                "       addu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                v->counter += i;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+}
+
+/*
+ * atomic64_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static __inline__ void atomic64_sub(long i, atomic64_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %1          # atomic64_sub          \n"
+                "       subu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %1          # atomic64_sub          \n"
+                "       subu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                v->counter -= i;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+}
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ long atomic64_add_return(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_add_return   \n"
+                "       addu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_add_return   \n"
+                "       addu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result += i;
+                v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_sub_return   \n"
+                "       subu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_sub_return   \n"
+                "       subu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sync                                            \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result -= i;
+                v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+/*
+ * atomic64_sub_if_positive - add integer to atomic variable
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically test @v and decrement if it is greater than 0.
+ * The function returns the old value of @v minus 1.
+ */
+static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       scd     %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       sync                                            \n"
+                "1:                                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       scd     %0, %2                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       sync                                            \n"
+                "1:                                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                spin_lock_irqsave(&atomic_lock, flags);
+                result = v->counter;
+                result -= i;
+                if (result >= 0)
+                        v->counter = result;
+                spin_unlock_irqrestore(&atomic_lock, flags);
+        }
+
+        return result;
+}
+
+#define atomic64_dec_return(v) atomic64_sub_return(1,(v))
+#define atomic64_inc_return(v) atomic64_add_return(1,(v))
+
+/*
+ * atomic64_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
+
+/*
+ * atomic64_inc_and_test - increment and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+
+/*
+ * atomic64_dec_and_test - decrement by 1 and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
+
+/*
+ * atomic64_dec_if_positive - decrement by 1 if old value positive
+ * @v: pointer of type atomic64_t
+ */
+#define atomic64_dec_if_positive(v)     atomic64_sub_if_positive(1, v)
+
+/*
+ * atomic64_inc - increment atomic variable
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic64_inc(v) atomic64_add(1,(v))
+
+/*
+ * atomic64_dec - decrement and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic64_dec(v) atomic64_sub(1,(v))
+
+/*
+ * atomic64_add_negative - add and test if negative
+ * @v: pointer of type atomic64_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
+
+#endif /* CONFIG_MIPS64 */
+
+/*
+ * atomic*_return operations are serializing but not the non-*_return
+ * versions.
+ */
+#define smp_mb__before_atomic_dec()     smp_mb()
+#define smp_mb__after_atomic_dec()      smp_mb()
+#define smp_mb__before_atomic_inc()     smp_mb()
+#define smp_mb__after_atomic_inc()      smp_mb()
+
+#endif /* _ASM_ATOMIC_H */
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
new file mode 100644
index 000000000000..446102b34f4e
--- /dev/null
+++ b/include/asm-mips/bcache.h
@@ -0,0 +1,62 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BCACHE_H
+#define _ASM_BCACHE_H
+
+#include <linux/config.h>
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
+   chipset implemented caches.  On machines with other CPUs the CPU does the
+   cache thing itself. */
+struct bcache_ops {
+        void (*bc_enable)(void);
+        void (*bc_disable)(void);
+        void (*bc_wback_inv)(unsigned long page, unsigned long size);
+        void (*bc_inv)(unsigned long page, unsigned long size);
+};
+
+extern void indy_sc_init(void);
+extern void sni_pcimt_sc_init(void);
+
+#ifdef CONFIG_BOARD_SCACHE
+
+extern struct bcache_ops *bcops;
+
+static inline void bc_enable(void)
+{
+        bcops->bc_enable();
+}
+
+static inline void bc_disable(void)
+{
+        bcops->bc_disable();
+}
+
+static inline void bc_wback_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_wback_inv(page, size);
+}
+
+static inline void bc_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_inv(page, size);
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000.  */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
+
+#endif /* _ASM_BCACHE_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
new file mode 100644
index 000000000000..779d2187a6a4
--- /dev/null
+++ b/include/asm-mips/bitops.h
@@ -0,0 +1,850 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>              /* sigh ... */
+#include <asm/cpu-features.h>
+
+#if (_MIPS_SZLONG == 32)
+#define SZLONG_LOG 5
+#define SZLONG_MASK 31UL
+#define __LL    "ll     "
+#define __SC    "sc     "
+#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 
+#elif (_MIPS_SZLONG == 64)
+#define SZLONG_LOG 6
+#define SZLONG_MASK 63UL
+#define __LL    "lld    "
+#define __SC    "scd    "
+#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 
+#endif
+
+#ifdef __KERNEL__
+
+#include <asm/interrupt.h>
+#include <asm/sgidefs.h>
+#include <asm/war.h>
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+
+/*
+ * Only disable interrupt for kernel mode stuff to keep usermode stuff
+ * that dares to use kernel include files alive.
+ */
+
+#define __bi_flags                      unsigned long flags
+#define __bi_local_irq_save(x)          local_irq_save(x)
+#define __bi_local_irq_restore(x)       local_irq_restore(x)
+#else
+#define __bi_flags
+#define __bi_local_irq_save(x)
+#define __bi_local_irq_restore(x)
+#endif /* __KERNEL__ */
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned long temp;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       or      %0, %2                                  \n"
+                "       "__SC   "%0, %1                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       or      %0, %2                                  \n"
+                "       "__SC   "%0, %1                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                *a |= mask;
+                __bi_local_irq_restore(flags);
+        }
+}
+
+/*
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(unsigned long nr, volatile unsigned long * addr)
+{
+        unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+
+        *m |= 1UL << (nr & SZLONG_MASK);
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned long temp;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       and     %0, %2                                  \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       and     %0, %2                                  \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                *a &= ~mask;
+                __bi_local_irq_restore(flags);
+        }
+}
+
+/*
+ * __clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * Unlike clear_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr)
+{
+        unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+
+        *m &= ~(1UL << (nr & SZLONG_MASK));
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1          # change_bit    \n"
+                "       xor     %0, %2                          \n"
+                "       "__SC   "%0, %1                         \n"
+                "       beqzl   %0, 1b                          \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1          # change_bit    \n"
+                "       xor     %0, %2                          \n"
+                "       "__SC   "%0, %1                         \n"
+                "       beqz    %0, 1b                          \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                *a ^= mask;
+                __bi_local_irq_restore(flags);
+        }
+}
+
+/*
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(unsigned long nr, volatile unsigned long * addr)
+{
+        unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+
+        *m ^= 1UL << (nr & SZLONG_MASK);
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "sync                                                   \n"
+#endif
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "       .set    noreorder       # test_and_set_bit      \n"
+                "1:     " __LL "%0, %1                                  \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqz    %2, 1b                                  \n"
+                "        and    %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "sync                                                   \n"
+#endif
+                ".set\treorder"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                int retval;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                retval = (mask & *a) != 0;
+                *a |= mask;
+                __bi_local_irq_restore(flags);
+
+                return retval;
+        }
+}
+
+/*
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned long mask;
+        int retval;
+
+        a += nr >> SZLONG_LOG;
+        mask = 1UL << (nr & SZLONG_MASK);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+
+        return retval;
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
+                "       or      %2, %0, %3                              \n"
+                "       xor     %2, %3                                  \n"
+                        __SC    "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "       .set    noreorder       # test_and_clear_bit    \n"
+                "1:     " __LL  "%0, %1                                 \n"
+                "       or      %2, %0, %3                              \n"
+                "       xor     %2, %3                                  \n"
+                        __SC    "%2, %1                                 \n"
+                "       beqz    %2, 1b                                  \n"
+                "        and    %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "       .set    reorder                                 \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                int retval;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                retval = (mask & *a) != 0;
+                *a &= ~mask;
+                __bi_local_irq_restore(flags);
+
+                return retval;
+        }
+}
+
+/*
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(unsigned long nr,
+        volatile unsigned long * addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned long mask;
+        int retval;
+
+        a += (nr >> SZLONG_LOG);
+        mask = 1UL << (nr & SZLONG_MASK);
+        retval = ((mask & *a) != 0);
+        *a &= ~mask;
+
+        return retval;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "1:     " __LL  " %0, %1        # test_and_change_bit   \n"
+                "       xor     %2, %0, %3                              \n"
+                "       "__SC   "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp, res;
+
+                __asm__ __volatile__(
+                "       .set    noreorder       # test_and_change_bit   \n"
+                "1:     " __LL  " %0, %1                                \n"
+                "       xor     %2, %0, %3                              \n"
+                "       "__SC   "\t%2, %1                               \n"
+                "       beqz    %2, 1b                                  \n"
+                "        and    %2, %0, %3                              \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "       .set    reorder                                 \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+                : "memory");
+
+                return res != 0;
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask, retval;
+                __bi_flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << (nr & SZLONG_MASK);
+                __bi_local_irq_save(flags);
+                retval = (mask & *a) != 0;
+                *a ^= mask;
+                __bi_local_irq_restore(flags);
+
+                return retval;
+        }
+}
+
+/*
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_change_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr;
+        unsigned long mask;
+        int retval;
+
+        a += (nr >> SZLONG_LOG);
+        mask = 1UL << (nr & SZLONG_MASK);
+        retval = ((mask & *a) != 0);
+        *a ^= mask;
+
+        return retval;
+}
+
+#undef __bi_flags
+#undef __bi_local_irq_save
+#undef __bi_local_irq_restore
+
+/*
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
+{
+        return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK));
+}
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        int b = 0, s;
+
+        word = ~word;
+#ifdef CONFIG_MIPS32
+        s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
+        s =  8; if (word << 24 != 0) s = 0; b += s; word >>= s;
+        s =  4; if (word << 28 != 0) s = 0; b += s; word >>= s;
+        s =  2; if (word << 30 != 0) s = 0; b += s; word >>= s;
+        s =  1; if (word << 31 != 0) s = 0; b += s;
+#endif
+#ifdef CONFIG_MIPS64
+        s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
+        s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s;
+        s =  8; if (word << 56 != 0) s = 0; b += s; word >>= s;
+        s =  4; if (word << 60 != 0) s = 0; b += s; word >>= s;
+        s =  2; if (word << 62 != 0) s = 0; b += s; word >>= s;
+        s =  1; if (word << 63 != 0) s = 0; b += s;
+#endif
+
+        return b;
+}
+
+/*
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        return ffz(~word);
+}
+
+/*
+ * fls: find last bit set.
+ */
+
+#define fls(x) generic_fls(x)
+
+/*
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline unsigned long find_next_zero_bit(const unsigned long *addr,
+        unsigned long size, unsigned long offset)
+{
+        const unsigned long *p = addr + (offset >> SZLONG_LOG);
+        unsigned long result = offset & ~SZLONG_MASK;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= SZLONG_MASK;
+        if (offset) {
+                tmp = *(p++);
+                tmp |= ~0UL >> (_MIPS_SZLONG-offset);
+                if (size < _MIPS_SZLONG)
+                        goto found_first;
+                if (~tmp)
+                        goto found_middle;
+                size -= _MIPS_SZLONG;
+                result += _MIPS_SZLONG;
+        }
+        while (size & ~SZLONG_MASK) {
+                if (~(tmp = *(p++)))
+                        goto found_middle;
+                result += _MIPS_SZLONG;
+                size -= _MIPS_SZLONG;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        tmp |= ~0UL << size;
+        if (tmp == ~0UL)                /* Are any bits zero? */
+                return result + size;   /* Nope. */
+found_middle:
+        return result + ffz(tmp);
+}
+
+#define find_first_zero_bit(addr, size) \
+        find_next_zero_bit((addr), (size), 0)
+
+/*
+ * find_next_bit - find the next set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline unsigned long find_next_bit(const unsigned long *addr,
+        unsigned long size, unsigned long offset)
+{
+        const unsigned long *p = addr + (offset >> SZLONG_LOG);
+        unsigned long result = offset & ~SZLONG_MASK;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= SZLONG_MASK;
+        if (offset) {
+                tmp = *(p++);
+                tmp &= ~0UL << offset;
+                if (size < _MIPS_SZLONG)
+                        goto found_first;
+                if (tmp)
+                        goto found_middle;
+                size -= _MIPS_SZLONG;
+                result += _MIPS_SZLONG;
+        }
+        while (size & ~SZLONG_MASK) {
+                if ((tmp = *(p++)))
+                        goto found_middle;
+                result += _MIPS_SZLONG;
+                size -= _MIPS_SZLONG;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        tmp &= ~0UL >> (_MIPS_SZLONG - size);
+        if (tmp == 0UL)                 /* Are any bits set? */
+                return result + size;   /* Nope. */
+found_middle:
+        return result + __ffs(tmp);
+}
+
+/*
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+#define find_first_bit(addr, size) \
+        find_next_bit((addr), (size), 0)
+
+#ifdef __KERNEL__
+
+/*
+ * Every architecture must define this function. It's the fastest
+ * way of searching a 140-bit bitmap where the first 100 bits are
+ * unlikely to be set. It's guaranteed that at least one of the 140
+ * bits is cleared.
+ */
+static inline int sched_find_first_bit(const unsigned long *b)
+{
+#ifdef CONFIG_MIPS32
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 32;
+        if (unlikely(b[2]))
+                return __ffs(b[2]) + 64;
+        if (b[3])
+                return __ffs(b[3]) + 96;
+        return __ffs(b[4]) + 128;
+#endif
+#ifdef CONFIG_MIPS64
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 64;
+        return __ffs(b[2]) + 128;
+#endif
+}
+
+/*
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight64(x)    generic_hweight64(x)
+#define hweight32(x)    generic_hweight32(x)
+#define hweight16(x)    generic_hweight16(x)
+#define hweight8(x)     generic_hweight8(x)
+
+static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr)
+{
+        unsigned char   *ADDR = (unsigned char *) addr;
+        int             mask, retval;
+
+        ADDR += nr >> 3;
+        mask = 1 << (nr & 0x07);
+        retval = (mask & *ADDR) != 0;
+        *ADDR |= mask;
+
+        return retval;
+}
+
+static inline int __test_and_clear_le_bit(unsigned long nr, unsigned long *addr)
+{
+        unsigned char   *ADDR = (unsigned char *) addr;
+        int             mask, retval;
+
+        ADDR += nr >> 3;
+        mask = 1 << (nr & 0x07);
+        retval = (mask & *ADDR) != 0;
+        *ADDR &= ~mask;
+
+        return retval;
+}
+
+static inline int test_le_bit(unsigned long nr, const unsigned long * addr)
+{
+        const unsigned char     *ADDR = (const unsigned char *) addr;
+        int                     mask;
+
+        ADDR += nr >> 3;
+        mask = 1 << (nr & 0x07);
+
+        return ((mask & *ADDR) != 0);
+}
+
+static inline unsigned long find_next_zero_le_bit(unsigned long *addr,
+        unsigned long size, unsigned long offset)
+{
+        unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG);
+        unsigned long result = offset & ~SZLONG_MASK;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= SZLONG_MASK;
+        if (offset) {
+                tmp = cpu_to_lelongp(p++);
+                tmp |= ~0UL >> (_MIPS_SZLONG-offset); /* bug or feature ? */
+                if (size < _MIPS_SZLONG)
+                        goto found_first;
+                if (~tmp)
+                        goto found_middle;
+                size -= _MIPS_SZLONG;
+                result += _MIPS_SZLONG;
+        }
+        while (size & ~SZLONG_MASK) {
+                if (~(tmp = cpu_to_lelongp(p++)))
+                        goto found_middle;
+                result += _MIPS_SZLONG;
+                size -= _MIPS_SZLONG;
+        }
+        if (!size)
+                return result;
+        tmp = cpu_to_lelongp(p);
+
+found_first:
+        tmp |= ~0UL << size;
+        if (tmp == ~0UL)                /* Are any bits zero? */
+                return result + size;   /* Nope. */
+
+found_middle:
+        return result + ffz(tmp);
+}
+
+#define find_first_zero_le_bit(addr, size) \
+        find_next_zero_le_bit((addr), (size), 0)
+
+#define ext2_set_bit(nr,addr) \
+        __test_and_set_le_bit((nr),(unsigned long*)addr)
+#define ext2_clear_bit(nr, addr) \
+        __test_and_clear_le_bit((nr),(unsigned long*)addr)
+ #define ext2_set_bit_atomic(lock, nr, addr)            \
+({                                                      \
+        int ret;                                        \
+        spin_lock(lock);                                \
+        ret = ext2_set_bit((nr), (addr));               \
+        spin_unlock(lock);                              \
+        ret;                                            \
+})
+
+#define ext2_clear_bit_atomic(lock, nr, addr)           \
+({                                                      \
+        int ret;                                        \
+        spin_lock(lock);                                \
+        ret = ext2_clear_bit((nr), (addr));             \
+        spin_unlock(lock);                              \
+        ret;                                            \
+})
+#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
+#define ext2_find_first_zero_bit(addr, size) \
+        find_first_zero_le_bit((unsigned long*)addr, size)
+#define ext2_find_next_zero_bit(addr, size, off) \
+        find_next_zero_le_bit((unsigned long*)addr, size, off)
+
+/*
+ * Bitmap functions for the minix filesystem.
+ *
+ * FIXME: These assume that Minix uses the native byte/bitorder.
+ * This limits the Minix filesystem's value for data exchange very much.
+ */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_BITOPS_H */
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
new file mode 100644
index 000000000000..b1e57d783604
--- /dev/null
+++ b/include/asm-mips/bootinfo.h
@@ -0,0 +1,256 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2003 by Ralf Baechle
+ * Copyright (C) 1995, 1996 Andreas Busse
+ * Copyright (C) 1995, 1996 Stoned Elipot
+ * Copyright (C) 1995, 1996 Paul M. Antoine.
+ */
+#ifndef _ASM_BOOTINFO_H
+#define _ASM_BOOTINFO_H
+
+#include <linux/types.h>
+#include <asm/setup.h>
+
+/*
+ * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining
+ * MACH_ values equivalent to product IDs.  As such the numbers do not
+ * necessarily reflect technical relations or similarities between systems.
+ */
+
+/*
+ * Valid machtype values for group unknown
+ */
+#define MACH_GROUP_UNKNOWN      0       /* whatever...                  */
+#define  MACH_UNKNOWN           0       /* whatever...                  */
+
+/*
+ * Valid machtype values for group JAZZ
+ */
+#define MACH_GROUP_JAZZ         1       /* Jazz                         */
+#define  MACH_ACER_PICA_61      0       /* Acer PICA-61 (PICA1)         */
+#define  MACH_MIPS_MAGNUM_4000  1       /* Mips Magnum 4000 "RC4030"    */
+#define  MACH_OLIVETTI_M700     2       /* Olivetti M700-10 (-15 ??)    */
+
+/*
+ * Valid machtype for group DEC
+ */
+#define MACH_GROUP_DEC          2       /* Digital Equipment            */
+#define  MACH_DSUNKNOWN         0
+#define  MACH_DS23100           1       /* DECstation 2100 or 3100      */
+#define  MACH_DS5100            2       /* DECsystem 5100               */
+#define  MACH_DS5000_200        3       /* DECstation 5000/200          */
+#define  MACH_DS5000_1XX        4       /* DECstation 5000/120, 125, 133, 150 */
+#define  MACH_DS5000_XX         5       /* DECstation 5000/20, 25, 33, 50 */
+#define  MACH_DS5000_2X0        6       /* DECstation 5000/240, 260     */
+#define  MACH_DS5400            7       /* DECsystem 5400               */
+#define  MACH_DS5500            8       /* DECsystem 5500               */
+#define  MACH_DS5800            9       /* DECsystem 5800               */
+#define  MACH_DS5900            10      /* DECsystem 5900               */
+
+/*
+ * Valid machtype for group ARC
+ */
+#define MACH_GROUP_ARC          3       /* Deskstation                  */
+#define MACH_DESKSTATION_RPC44  0       /* Deskstation rPC44 */
+#define MACH_DESKSTATION_TYNE   1       /* Deskstation Tyne */
+
+/*
+ * Valid machtype for group SNI_RM
+ */
+#define MACH_GROUP_SNI_RM       4       /* Siemens Nixdorf RM series    */
+#define  MACH_SNI_RM200_PCI     0       /* RM200/RM300/RM400 PCI series */
+
+/*
+ * Valid machtype for group ACN
+ */
+#define MACH_GROUP_ACN          5
+#define  MACH_ACN_MIPS_BOARD    0       /* ACN MIPS single board        */
+
+/*
+ * Valid machtype for group SGI
+ */
+#define MACH_GROUP_SGI          6       /* Silicon Graphics             */
+#define  MACH_SGI_IP22          0       /* Indy, Indigo2, Challenge S   */
+#define  MACH_SGI_IP27          1       /* Origin 200, Origin 2000, Onyx 2 */
+#define  MACH_SGI_IP28          2       /* Indigo2 Impact               */
+#define  MACH_SGI_IP32          3       /* O2                           */
+
+/*
+ * Valid machtype for group COBALT
+ */
+#define MACH_GROUP_COBALT       7       /* Cobalt servers               */
+#define  MACH_COBALT_27         0       /* Proto "27" hardware          */
+
+/*
+ * Valid machtype for group NEC DDB
+ */
+#define MACH_GROUP_NEC_DDB      8       /* NEC DDB                      */
+#define  MACH_NEC_DDB5074       0       /* NEC DDB Vrc-5074 */
+#define  MACH_NEC_DDB5476       1       /* NEC DDB Vrc-5476 */
+#define  MACH_NEC_DDB5477       2       /* NEC DDB Vrc-5477 */
+#define  MACH_NEC_ROCKHOPPER    3       /* Rockhopper base board */
+#define  MACH_NEC_ROCKHOPPERII  4       /* Rockhopper II base board */
+
+/*
+ * Valid machtype for group BAGET
+ */
+#define MACH_GROUP_BAGET        9       /* Baget                        */
+#define  MACH_BAGET201          0       /* BT23-201 */
+#define  MACH_BAGET202          1       /* BT23-202 */
+
+/*
+ * Cosine boards.
+ */
+#define MACH_GROUP_COSINE      10       /* CoSine Orion                 */
+#define  MACH_COSINE_ORION      0
+
+/*
+ * Valid machtype for group GALILEO
+ */
+#define MACH_GROUP_GALILEO     11       /* Galileo Eval Boards          */
+#define  MACH_EV96100           0       /* EV96100 */
+#define  MACH_EV64120A          1       /* EV64120A */
+
+/*
+ * Valid machtype for group MOMENCO
+ */
+#define MACH_GROUP_MOMENCO      12      /* Momentum Boards              */
+#define  MACH_MOMENCO_OCELOT    0
+#define  MACH_MOMENCO_OCELOT_G  1
+#define  MACH_MOMENCO_OCELOT_C  2
+#define  MACH_MOMENCO_JAGUAR_ATX 3
+#define  MACH_MOMENCO_OCELOT_3  4
+
+/*
+ * Valid machtype for group ITE
+ */
+#define MACH_GROUP_ITE          13      /* ITE Semi Eval Boards         */
+#define  MACH_QED_4N_S01B       0       /* ITE8172 based eval board */
+
+/*
+ * Valid machtype for group PHILIPS
+ */
+#define MACH_GROUP_PHILIPS     14
+#define  MACH_PHILIPS_NINO      0       /* Nino */
+#define  MACH_PHILIPS_VELO      1       /* Velo */
+
+/*
+ * Valid machtype for group Globespan
+ */
+#define MACH_GROUP_GLOBESPAN   15       /* Globespan */
+#define  MACH_IVR               0       /* IVR eval board */
+
+/*
+ * Valid machtype for group SIBYTE
+ */
+#define MACH_GROUP_SIBYTE       16      /* Sibyte / Broadcom */
+#define  MACH_SWARM              0
+
+/*
+ * Valid machtypes for group Toshiba
+ */
+#define MACH_GROUP_TOSHIBA      17 /* Toshiba Reference Systems TSBREF       */
+#define  MACH_PALLAS            0
+#define  MACH_TOPAS             1
+#define  MACH_JMR               2
+#define  MACH_TOSHIBA_JMR3927   3       /* JMR-TX3927 CPU/IO board */
+#define  MACH_TOSHIBA_RBTX4927  4
+#define  MACH_TOSHIBA_RBTX4937  5
+
+#define GROUP_TOSHIBA_NAMES     { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
+                                  "RBTX4927", "RBTX4937" }
+
+/*
+ * Valid machtype for group Alchemy
+ */
+#define MACH_GROUP_ALCHEMY     18       /* AMD Alchemy  */
+#define  MACH_PB1000            0       /* Au1000-based eval board */
+#define  MACH_PB1100            1       /* Au1100-based eval board */
+#define  MACH_PB1500            2       /* Au1500-based eval board */
+#define  MACH_DB1000            3       /* Au1000-based eval board */
+#define  MACH_DB1100            4       /* Au1100-based eval board */
+#define  MACH_DB1500            5       /* Au1500-based eval board */
+#define  MACH_XXS1500           6       /* Au1500-based eval board */
+#define  MACH_MTX1              7       /* 4G MTX-1 Au1500-based board */
+#define  MACH_PB1550            8       /* Au1550-based eval board */
+#define  MACH_DB1550            9       /* Au1550-based eval board */
+
+/*
+ * Valid machtype for group NEC_VR41XX
+ *
+ * Various NEC-based devices.
+ *
+ * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by
+ *        technical properties, so no new additions to this group.
+ */
+#define MACH_GROUP_NEC_VR41XX  19
+#define  MACH_NEC_OSPREY        0       /* Osprey eval board */
+#define  MACH_NEC_EAGLE         1       /* NEC Eagle/Hawk board */
+#define  MACH_ZAO_CAPCELLA      2       /* ZAO Networks Capcella */
+#define  MACH_VICTOR_MPC30X     3       /* Victor MP-C303/304 */
+#define  MACH_IBM_WORKPAD       4       /* IBM WorkPad z50 */
+#define  MACH_CASIO_E55         5       /* CASIO CASSIOPEIA E-10/15/55/65 */
+#define  MACH_TANBAC_TB0226     6       /* TANBAC TB0226 (Mbase) */
+#define  MACH_TANBAC_TB0229     7       /* TANBAC TB0229 (VR4131DIMM) */
+#define  MACH_NEC_CMBVR4133     8       /* CMB VR4133 Board */
+
+#define MACH_GROUP_HP_LJ        20      /* Hewlett Packard LaserJet     */
+#define  MACH_HP_LASERJET       1
+
+/*
+ * Valid machtype for group LASAT
+ */
+#define MACH_GROUP_LASAT       21
+#define  MACH_LASAT_100         0       /* Masquerade II/SP100/SP50/SP25 */
+#define  MACH_LASAT_200         1       /* Masquerade PRO/SP200 */
+
+/*
+ * Valid machtype for group TITAN
+ */
+#define MACH_GROUP_TITAN       22       /* PMC-Sierra Titan             */
+#define  MACH_TITAN_YOSEMITE    1       /* PMC-Sierra Yosemite          */
+
+#define CL_SIZE                 COMMAND_LINE_SIZE
+
+const char *get_system_type(void);
+
+extern unsigned long mips_machtype;
+extern unsigned long mips_machgroup;
+
+#define BOOT_MEM_MAP_MAX        32
+#define BOOT_MEM_RAM            1
+#define BOOT_MEM_ROM_DATA       2
+#define BOOT_MEM_RESERVED       3
+
+/*
+ * A memory map that's built upon what was determined
+ * or specified on the command line.
+ */
+struct boot_mem_map {
+        int nr_map;
+        struct boot_mem_map_entry {
+                phys_t addr;    /* start of memory segment */
+                phys_t size;    /* size of memory segment */
+                long type;              /* type of memory segment */
+        } map[BOOT_MEM_MAP_MAX];
+};
+
+extern struct boot_mem_map boot_mem_map;
+
+extern void add_memory_region(phys_t start, phys_t size, long type);
+
+extern void prom_init(void);
+
+/*
+ * Initial kernel command line, usually setup by prom_init()
+ */
+extern char arcs_cmdline[CL_SIZE];
+
+/*
+ * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
+ */
+extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
+#endif /* _ASM_BOOTINFO_H */
diff --git a/include/asm-mips/branch.h b/include/asm-mips/branch.h
new file mode 100644
index 000000000000..37c6857c8d4a
--- /dev/null
+++ b/include/asm-mips/branch.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
+ */
+#ifndef _ASM_BRANCH_H
+#define _ASM_BRANCH_H
+
+#include <asm/ptrace.h>
+
+static inline int delay_slot(struct pt_regs *regs)
+{
+        return regs->cp0_cause & CAUSEF_BD;
+}
+
+static inline unsigned long exception_epc(struct pt_regs *regs)
+{
+        if (!delay_slot(regs))
+                return regs->cp0_epc;
+
+        return regs->cp0_epc + 4;
+}
+
+extern int __compute_return_epc(struct pt_regs *regs);
+
+static inline int compute_return_epc(struct pt_regs *regs)
+{
+        if (!delay_slot(regs)) {
+                regs->cp0_epc += 4;
+                return 0;
+        }
+
+        return __compute_return_epc(regs);
+}
+
+#endif /* _ASM_BRANCH_H */
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
new file mode 100644
index 000000000000..2e6de788f207
--- /dev/null
+++ b/include/asm-mips/break.h
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_BREAK_H
+#define __ASM_BREAK_H
+
+/*
+ * The following break codes are or were in use for specific purposes in
+ * other MIPS operating systems.  Linux/MIPS doesn't use all of them.  The
+ * unused ones are here as placeholders; we might encounter them in
+ * non-Linux/MIPS object files or make use of them in the future.
+ */
+#define BRK_USERBP      0       /* User bp (used by debuggers) */
+#define BRK_KERNELBP    1       /* Break in the kernel */
+#define BRK_ABORT       2       /* Sometimes used by abort(3) to SIGIOT */
+#define BRK_BD_TAKEN    3       /* For bd slot emulation - not implemented */
+#define BRK_BD_NOTTAKEN 4       /* For bd slot emulation - not implemented */
+#define BRK_SSTEPBP     5       /* User bp (used by debuggers) */
+#define BRK_OVERFLOW    6       /* Overflow check */
+#define BRK_DIVZERO     7       /* Divide by zero check */
+#define BRK_RANGE       8       /* Range error check */
+#define BRK_STACKOVERFLOW 9     /* For Ada stackchecking */
+#define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
+#define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
+#define BRK_BUG         512     /* Used by BUG() */
+#define BRK_MULOVF      1023    /* Multiply overflow */
+
+#endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
new file mode 100644
index 000000000000..eb94bb96cfbc
--- /dev/null
+++ b/include/asm-mips/bug.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_BUG_H
+#define __ASM_BUG_H
+
+#include <asm/break.h>
+
+#define BUG()                                                           \
+do {                                                                    \
+        __asm__ __volatile__("break %0" : : "i" (BRK_BUG));             \
+} while (0)
+
+#define HAVE_ARCH_BUG
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
new file mode 100644
index 000000000000..18cced19cca4
--- /dev/null
+++ b/include/asm-mips/bugs.h
@@ -0,0 +1,23 @@
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+#ifndef _ASM_BUGS_H
+#define _ASM_BUGS_H
+
+#include <linux/config.h>
+
+extern void check_bugs32(void);
+extern void check_bugs64(void);
+
+static inline void check_bugs(void)
+{
+        check_bugs32();
+#ifdef CONFIG_MIPS64
+        check_bugs64();
+#endif
+}
+
+#endif /* _ASM_BUGS_H */
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
new file mode 100644
index 000000000000..d1fe9e5c62e4
--- /dev/null
+++ b/include/asm-mips/byteorder.h
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined (__MIPSEB__)
+#  include <linux/byteorder/big_endian.h>
+#elif defined (__MIPSEL__)
+#  include <linux/byteorder/little_endian.h>
+#else
+#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
new file mode 100644
index 000000000000..4517bdf20953
--- /dev/null
+++ b/include/asm-mips/cache.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <linux/config.h>
+
+#define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define L1_CACHE_SHIFT_MAX      6
+#define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
+#define SMP_CACHE_BYTES         L1_CACHE_BYTES
+
+#define ARCH_KMALLOC_MINALIGN   8
+
+#endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
new file mode 100644
index 000000000000..f3ce721861d3
--- /dev/null
+++ b/include/asm-mips/cachectl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE  (1<<0)          /* flush instruction cache        */
+#define DCACHE  (1<<1)          /* writeback and flush data cache */
+#define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE       0       /* make pages cacheable */
+#define UNCACHEABLE     1       /* make pages uncacheable */
+
+#endif  /* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
new file mode 100644
index 000000000000..635f1bfb403e
--- /dev/null
+++ b/include/asm-mips/cacheflush.h
@@ -0,0 +1,81 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHEFLUSH_H
+#define _ASM_CACHEFLUSH_H
+
+/* Keep includes the same across arches.  */
+#include <linux/mm.h>
+#include <asm/cpu-features.h>
+
+/* Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *  - flush_icache_range(start, end) flush a range of instructions
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
+ *
+ * MIPS specific flush operations:
+ *
+ *  - flush_cache_sigtramp() flush signal trampoline
+ *  - flush_icache_all() flush the entire instruction cache
+ *  - flush_data_cache_page() flushes a page from the data cache
+ */
+extern void (*flush_cache_all)(void);
+extern void (*__flush_cache_all)(void);
+extern void (*flush_cache_mm)(struct mm_struct *mm);
+extern void (*flush_cache_range)(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+extern void __flush_dcache_page(struct page *page);
+
+static inline void flush_dcache_page(struct page *page)
+{
+        if (cpu_has_dc_aliases)
+                __flush_dcache_page(page);
+
+}
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+extern void (*flush_icache_page)(struct vm_area_struct *vma,
+        struct page *page);
+extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+#define flush_cache_vmap(start, end)            flush_cache_all()
+#define flush_cache_vunmap(start, end)          flush_cache_all()
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
+do {                                                                    \
+        memcpy(dst, (void *) src, len);                                 \
+        flush_icache_page(vma, page);                                   \
+} while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
+        memcpy(dst, src, len)
+
+extern void (*flush_cache_sigtramp)(unsigned long addr);
+extern void (*flush_icache_all)(void);
+extern void (*flush_data_cache_page)(unsigned long addr);
+
+/*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty                 PG_arch_1
+
+#define Page_dcache_dirty(page)         \
+        test_bit(PG_dcache_dirty, &(page)->flags)
+#define SetPageDcacheDirty(page)        \
+        set_bit(PG_dcache_dirty, &(page)->flags)
+#define ClearPageDcacheDirty(page)      \
+        clear_bit(PG_dcache_dirty, &(page)->flags)
+
+#endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
new file mode 100644
index 000000000000..c4a1ec31ff6a
--- /dev/null
+++ b/include/asm-mips/cacheops.h
@@ -0,0 +1,81 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Load_Tag_I        0x04
+#define Index_Load_Tag_D        0x05
+#define Index_Store_Tag_I       0x08
+#define Index_Store_Tag_D       0x09
+#define Hit_Invalidate_I        0x10
+#define Hit_Invalidate_D        0x11
+#define Hit_Writeback_Inv_D     0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D     0x0d
+#define Fill                    0x14
+#define Hit_Writeback_I         0x18
+#define Hit_Writeback_D         0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_SI       0x06
+#define Index_Load_Tag_SD       0x07
+#define Index_Store_Tag_SI      0x0A
+#define Index_Store_Tag_SD      0x0B
+#define Create_Dirty_Excl_SD    0x0f
+#define Hit_Invalidate_SI       0x12
+#define Hit_Invalidate_SD       0x13
+#define Hit_Writeback_Inv_SD    0x17
+#define Hit_Writeback_SD        0x1b
+#define Hit_Set_Virtual_SI      0x1e
+#define Hit_Set_Virtual_SD      0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S   0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T       0x16
+
+/*
+ * R1000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S   0x03
+#define Index_Load_Tag_S        0x07
+#define Index_Store_Tag_S       0x0B
+#define Hit_Invalidate_S        0x13
+#define Cache_Barrier           0x14
+#define Hit_Writeback_Inv_S     0x17
+#define Index_Load_Data_I       0x18
+#define Index_Load_Data_D       0x19
+#define Index_Load_Data_S       0x1b
+#define Index_Store_Data_I      0x1c
+#define Index_Store_Data_D      0x1d
+#define Index_Store_Data_S      0x1f
+
+#endif  /* __ASM_CACHEOPS_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
new file mode 100644
index 000000000000..c25cc92b9950
--- /dev/null
+++ b/include/asm-mips/checksum.h
@@ -0,0 +1,253 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Thiemo Seufer.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef _ASM_CHECKSUM_H
+#define _ASM_CHECKSUM_H
+
+#include <linux/config.h>
+#include <linux/in6.h>
+
+#include <asm/uaccess.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
+
+/*
+ * this is a new version of the above that records errors it finds in *errp,
+ * but continues and zeros the rest of the buffer.
+ */
+unsigned int csum_partial_copy_from_user(const unsigned char *src, unsigned char *dst, int len,
+                                         unsigned int sum, int *errp);
+
+/*
+ * Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static inline unsigned int csum_and_copy_to_user (const unsigned char *src,
+                                                  unsigned char __user *dst,
+                                                  int len, int sum,
+                                                  int *err_ptr)
+{
+        might_sleep();
+        sum = csum_partial(src, len, sum);
+
+        if (copy_to_user(dst, src, len)) {
+                *err_ptr = -EFAULT;
+                return -1;
+        }
+
+        return sum;
+}
+
+/*
+ * the same as csum_partial, but copies from user space (but on MIPS
+ * we have just one address space, so this is identical to the above)
+ */
+unsigned int csum_partial_copy_nocheck(const unsigned char *src, unsigned char *dst,
+                                       int len, unsigned int sum);
+
+/*
+ *      Fold a partial checksum without adding pseudo headers
+ */
+static inline unsigned short int csum_fold(unsigned int sum)
+{
+        __asm__(
+        ".set\tnoat\t\t\t# csum_fold\n\t"
+        "sll\t$1,%0,16\n\t"
+        "addu\t%0,$1\n\t"
+        "sltu\t$1,%0,$1\n\t"
+        "srl\t%0,%0,16\n\t"
+        "addu\t%0,$1\n\t"
+        "xori\t%0,0xffff\n\t"
+        ".set\tat"
+        : "=r" (sum)
+        : "0" (sum));
+
+        return sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ *      By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
+ *      Arnt Gulbrandsen.
+ */
+static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl)
+{
+        unsigned int *word = (unsigned int *) iph;
+        unsigned int *stop = word + ihl;
+        unsigned int csum;
+        int carry;
+
+        csum = word[0];
+        csum += word[1];
+        carry = (csum < word[1]);
+        csum += carry;
+
+        csum += word[2];
+        carry = (csum < word[2]);
+        csum += carry;
+
+        csum += word[3];
+        carry = (csum < word[3]);
+        csum += carry;
+
+        word += 4;
+        do {
+                csum += *word;
+                carry = (csum < *word);
+                csum += carry;
+                word++;
+        } while (word != stop);
+
+        return csum_fold(csum);
+}
+
+static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
+        unsigned long daddr, unsigned short len, unsigned short proto,
+        unsigned int sum)
+{
+        __asm__(
+        ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
+#ifdef CONFIG_MIPS32
+        "addu\t%0, %2\n\t"
+        "sltu\t$1, %0, %2\n\t"
+        "addu\t%0, $1\n\t"
+
+        "addu\t%0, %3\n\t"
+        "sltu\t$1, %0, %3\n\t"
+        "addu\t%0, $1\n\t"
+
+        "addu\t%0, %4\n\t"
+        "sltu\t$1, %0, %4\n\t"
+        "addu\t%0, $1\n\t"
+#endif
+#ifdef CONFIG_MIPS64
+        "daddu\t%0, %2\n\t"
+        "daddu\t%0, %3\n\t"
+        "daddu\t%0, %4\n\t"
+        "dsll32\t$1, %0, 0\n\t"
+        "daddu\t%0, $1\n\t"
+        "dsrl32\t%0, %0, 0\n\t"
+#endif
+        ".set\tat"
+        : "=r" (sum)
+        : "0" (daddr), "r"(saddr),
+#ifdef __MIPSEL__
+          "r" (((unsigned long)htons(len)<<16) + proto*256),
+#else
+          "r" (((unsigned long)(proto)<<16) + len),
+#endif
+          "r" (sum));
+
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
+                                                   unsigned long daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   unsigned int sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
+                                                     struct in6_addr *daddr,
+                                                     __u32 len,
+                                                     unsigned short proto,
+                                                     unsigned int sum)
+{
+        __asm__(
+        ".set\tpush\t\t\t# csum_ipv6_magic\n\t"
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n\t"
+        "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"
+        "sltu\t$1, %0, %5\n\t"
+        "addu\t%0, $1\n\t"
+
+        "addu\t%0, %6\t\t\t# csum\n\t"
+        "sltu\t$1, %0, %6\n\t"
+        "lw\t%1, 0(%2)\t\t\t# four words source address\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 4(%2)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 8(%2)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 12(%2)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 0(%3)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 4(%3)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 8(%3)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "lw\t%1, 12(%3)\n\t"
+        "addu\t%0, $1\n\t"
+        "addu\t%0, %1\n\t"
+        "sltu\t$1, %0, %1\n\t"
+
+        "addu\t%0, $1\t\t\t# Add final carry\n\t"
+        ".set\tpop"
+        : "=r" (sum), "=r" (proto)
+        : "r" (saddr), "r" (daddr),
+          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
+
+        return csum_fold(sum);
+}
+
+#endif /* _ASM_CHECKSUM_H */
diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h
new file mode 100644
index 000000000000..ca1fbc0579fe
--- /dev/null
+++ b/include/asm-mips/cobalt/cobalt.h
@@ -0,0 +1,90 @@
+/*
+ * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
+ */
+#ifndef __ASM_COBALT_H
+#define __ASM_COBALT_H
+
+/*
+ * i8259 legacy interrupts used on Cobalt:
+ *
+ *     8  - RTC
+ *     9  - PCI
+ *    14  - IDE0
+ *    15  - IDE1
+ *
+ * CPU IRQs  are 16 ... 23
+ */
+#define COBALT_TIMER_IRQ        18
+#define COBALT_SCC_IRQ          19              /* pre-production has 85C30 */
+#define COBALT_RAQ_SCSI_IRQ     19
+#define COBALT_ETH0_IRQ         19
+#define COBALT_ETH1_IRQ         20
+#define COBALT_SERIAL_IRQ       21
+#define COBALT_SCSI_IRQ         21
+#define COBALT_VIA_IRQ          22              /* Chained to VIA ISA bridge */
+#define COBALT_QUBE_SLOT_IRQ    23
+
+/*
+ * PCI configuration space manifest constants.  These are wired into
+ * the board layout according to the PCI spec to enable the software
+ * to probe the hardware configuration space in a well defined manner.
+ *
+ * The PCI_DEVSHFT() macro transforms these values into numbers
+ * suitable for passing as the dev parameter to the various
+ * pcibios_read/write_config routines.
+ */
+#define COBALT_PCICONF_CPU      0x06
+#define COBALT_PCICONF_ETH0     0x07
+#define COBALT_PCICONF_RAQSCSI  0x08
+#define COBALT_PCICONF_VIA      0x09
+#define COBALT_PCICONF_PCISLOT  0x0A
+#define COBALT_PCICONF_ETH1     0x0C
+
+
+/*
+ * The Cobalt board id information.  The boards have an ID number wired
+ * into the VIA that is available in the high nibble of register 94.
+ * This register is available in the VIA configuration space through the
+ * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
+ */
+#define VIA_COBALT_BRD_ID_REG  0x94
+#define VIA_COBALT_BRD_REG_to_ID(reg)  ((unsigned char) (reg) >> 4)
+#define COBALT_BRD_ID_QUBE1    0x3
+#define COBALT_BRD_ID_RAQ1     0x4
+#define COBALT_BRD_ID_QUBE2    0x5
+#define COBALT_BRD_ID_RAQ2     0x6
+
+/*
+ * Galileo chipset access macros for the Cobalt. The base address for
+ * the GT64111 chip is 0x14000000
+ *
+ * Most of this really should go into a separate GT64111 header file.
+ */
+#define GT64111_IO_BASE         0x10000000UL
+#define GT64111_BASE            0x14000000UL
+#define GALILEO_REG(ofs)        (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
+
+#define GALILEO_INL(port)       (*(volatile unsigned int *) GALILEO_REG(port))
+#define GALILEO_OUTL(val, port)                                         \
+do {                                                                    \
+        *(volatile unsigned int *) GALILEO_REG(port) = (port);          \
+} while (0)
+
+#define GALILEO_T0EXP           0x0100
+#define GALILEO_ENTC0           0x01
+#define GALILEO_SELTC0          0x02
+
+#define PCI_CFG_SET(devfn,where)                                        \
+        GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |           \
+                (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
+
+
+#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
new file mode 100644
index 000000000000..dce92079e7fc
--- /dev/null
+++ b/include/asm-mips/compat.h
@@ -0,0 +1,144 @@
+#ifndef _ASM_COMPAT_H
+#define _ASM_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+#include <asm/page.h>
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_suseconds_t;
+
+typedef s32             compat_pid_t;
+typedef s32             compat_uid_t;
+typedef s32             compat_gid_t;
+typedef u32             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u32             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef u32             compat_nlink_t;
+typedef s32             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef s32             compat_caddr_t;
+typedef struct {
+        s32     val[2];
+} compat_fsid_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        s32             st_pad1[3];
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        compat_uid_t    st_uid;
+        compat_gid_t    st_gid;
+        compat_dev_t    st_rdev;
+        s32             st_pad2[2];
+        compat_off_t    st_size;
+        s32             st_pad3;
+        compat_time_t   st_atime;
+        s32             st_atime_nsec;
+        compat_time_t   st_mtime;
+        s32             st_mtime_nsec;
+        compat_time_t   st_ctime;
+        s32             st_ctime_nsec;
+        s32             st_blksize;
+        s32             st_blocks;
+        s32             st_pad4[14];
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        s32             l_sysid;
+        compat_pid_t    l_pid;
+        short           __unused;
+        s32             pad[4];
+};
+
+#define F_GETLK64       33
+#define F_SETLK64       34
+#define F_SETLKW64      35
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+};
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_frsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_files;
+        int             f_ffree;
+        int             f_bavail;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;
+        int             f_spare[6];
+};
+
+#define COMPAT_RLIM_INFINITY    0x7fffffffUL
+
+typedef u32             compat_old_sigset_t;    /* at least 32 bits */
+
+#define _COMPAT_NSIG            128             /* Don't ask !$@#% ...  */
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately comverted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void *compat_ptr(compat_uptr_t uptr)
+{
+        return (void *)(long)uptr;
+}
+
+static inline void *compat_alloc_user_space(long len)
+{
+        struct pt_regs *regs = (struct pt_regs *)
+                ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
+
+        return (void *) (regs->regs[29] - len);
+}
+#if defined (__MIPSEL__)
+#define __COMPAT_ENDIAN_SWAP__  1
+#endif
+
+#endif /* _ASM_COMPAT_H */
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
new file mode 100644
index 000000000000..169ae26105e9
--- /dev/null
+++ b/include/asm-mips/compiler.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2004  Maciej W. Rozycki
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_COMPILER_H
+#define _ASM_COMPILER_H
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+#define GCC_REG_ACCUM "$0"
+#else
+#define GCC_REG_ACCUM "accum"
+#endif
+
+#endif /* _ASM_COMPILER_H */
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
new file mode 100644
index 000000000000..1df2c299de82
--- /dev/null
+++ b/include/asm-mips/cpu-features.h
@@ -0,0 +1,159 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <linux/config.h>
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <cpu-feature-overrides.h>
+
+/*
+ * SMP assumption: Options of CPU 0 are a superset of all processors.
+ * This is true for all known MIPS systems.
+ */
+#ifndef cpu_has_tlb
+#define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
+#endif
+#ifndef cpu_has_4kex
+#define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
+#endif
+#ifndef cpu_has_4ktlb
+#define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
+#endif
+#ifndef cpu_has_fpu
+#define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
+#endif
+#ifndef cpu_has_32fpr
+#define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
+#endif
+#ifndef cpu_has_counter
+#define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
+#endif
+#ifndef cpu_has_watch
+#define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
+#endif
+#ifndef cpu_has_divec
+#define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
+#endif
+#ifndef cpu_has_vce
+#define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
+#endif
+#ifndef cpu_has_cache_cdex_p
+#define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
+#endif
+#ifndef cpu_has_cache_cdex_s
+#define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
+#endif
+#ifndef cpu_has_prefetch
+#define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
+#endif
+#ifndef cpu_has_mcheck
+#define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
+#endif
+#ifndef cpu_has_ejtag
+#define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
+#endif
+#ifndef cpu_has_llsc
+#define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
+#endif
+#ifndef cpu_has_vtag_icache
+#define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
+#endif
+#ifndef cpu_has_dc_aliases
+#define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
+#endif
+#ifndef cpu_has_ic_fills_f_dc
+#define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+
+/*
+ * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
+ * such as the R10000 have I-Caches that snoop local stores; the embedded ones
+ * don't.  For maintaining I-cache coherency this means we need to flush the
+ * D-cache all the way back to whever the I-cache does refills from, so the
+ * I-cache has a chance to see the new data at all.  Then we have to flush the
+ * I-cache also.
+ * Note we may have been rescheduled and may no longer be running on the CPU
+ * that did the store so we can't optimize this into only doing the flush on
+ * the local CPU.
+ */
+#ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
+#define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
+#else
+#define cpu_icache_snoops_remote_store  1
+#endif
+#endif
+
+/*
+ * Certain CPUs may throw bizarre exceptions if not the whole cacheline
+ * contains valid instructions.  For these we ensure proper alignment of
+ * signal trampolines and pad them to the size of a full cache lines with
+ * nops.  This is also used in structure definitions so can't be a test macro
+ * like the others.
+ */
+#ifndef PLAT_TRAMPOLINE_STUFF_LINE
+#define PLAT_TRAMPOLINE_STUFF_LINE      0UL
+#endif
+
+#ifdef CONFIG_MIPS32
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses        0
+# endif
+#endif
+
+#ifdef CONFIG_MIPS64
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex                0
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits                 1
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg         1
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses        1
+# endif
+#endif
+
+#ifndef cpu_has_subset_pcaches
+#define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
+#endif
+
+#ifndef cpu_dcache_line_size
+#define cpu_dcache_line_size()  current_cpu_data.dcache.linesz
+#endif
+#ifndef cpu_icache_line_size
+#define cpu_icache_line_size()  current_cpu_data.icache.linesz
+#endif
+#ifndef cpu_scache_line_size
+#define cpu_scache_line_size()  current_cpu_data.scache.linesz
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
new file mode 100644
index 000000000000..20a35b15a31d
--- /dev/null
+++ b/include/asm-mips/cpu-info.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+#include <linux/config.h>
+#include <asm/cache.h>
+
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/types.h>
+#endif
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+        unsigned short linesz;  /* Size of line in bytes */
+        unsigned short ways;    /* Number of ways */
+        unsigned short sets;    /* Number of lines per set */
+        unsigned int waysize;   /* Bytes per way */
+        unsigned int waybit;    /* Bits to select in a cache set */
+        unsigned int flags;     /* Flags describing cache properties */
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT  0x00000001
+#define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
+#define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
+#define MIPS_IC_SNOOPS_REMOTE   0x00000010      /* Ic snoops remote stores */
+
+struct cpuinfo_mips {
+        unsigned long           udelay_val;
+        unsigned long           asid_cache;
+#if defined(CONFIG_SGI_IP27)
+//      cpuid_t         p_cpuid;        /* PROM assigned cpuid */
+        cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
+        nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
+        unsigned char   p_slice;        /* Physical position on node board */
+#endif
+#if 0
+        unsigned long           loops_per_sec;
+        unsigned long           ipi_count;
+        unsigned long           irq_attempt[NR_IRQS];
+        unsigned long           smp_local_irq_count;
+        unsigned long           prof_multiplier;
+        unsigned long           prof_counter;
+#endif
+
+        /*
+         * Capability and feature descriptor structure for MIPS CPU
+         */
+        unsigned long           options;
+        unsigned int            processor_id;
+        unsigned int            fpu_id;
+        unsigned int            cputype;
+        int                     isa_level;
+        int                     tlbsize;
+        struct cache_desc       icache; /* Primary I-cache */
+        struct cache_desc       dcache; /* Primary D or combined I/D cache */
+        struct cache_desc       scache; /* Secondary cache */
+        struct cache_desc       tcache; /* Tertiary/split secondary cache */
+        void                    *data;  /* Additional data */
+} __attribute__((aligned(SMP_CACHE_BYTES)));
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+
+extern void cpu_probe(void);
+extern void cpu_report(void);
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
new file mode 100644
index 000000000000..dec060b49556
--- /dev/null
+++ b/include/asm-mips/cpu.h
@@ -0,0 +1,222 @@
+/*
+ * cpu.h: Values of the PRId register used to match up
+ *        various MIPS cpu types.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ */
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+/* Assigned Company values for bits 23:16 of the PRId Register
+   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
+   MTI, the PRId register is defined in this (backwards compatible)
+   way:
+
+  +----------------+----------------+----------------+----------------+
+  | Company Options| Company ID     | Processor ID   | Revision       |
+  +----------------+----------------+----------------+----------------+
+   31            24 23            16 15             8 7
+
+   I don't have docs for all the previous processors, but my impression is
+   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+   spec.
+*/
+
+#define PRID_COMP_LEGACY       0x000000
+#define PRID_COMP_MIPS         0x010000
+#define PRID_COMP_BROADCOM     0x020000
+#define PRID_COMP_ALCHEMY      0x030000
+#define PRID_COMP_SIBYTE       0x040000
+#define PRID_COMP_SANDCRAFT    0x050000
+
+/*
+ * Assigned values for the product ID register.  In order to detect a
+ * certain CPU type exactly eventually additional registers may need to
+ * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
+ */
+#define PRID_IMP_R2000          0x0100
+#define PRID_IMP_AU1_REV1       0x0100
+#define PRID_IMP_AU1_REV2       0x0200
+#define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
+#define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
+#define PRID_IMP_R4000          0x0400
+#define PRID_IMP_R6000A         0x0600
+#define PRID_IMP_R10000         0x0900
+#define PRID_IMP_R4300          0x0b00
+#define PRID_IMP_VR41XX         0x0c00
+#define PRID_IMP_R12000         0x0e00
+#define PRID_IMP_R8000          0x1000
+#define PRID_IMP_R4600          0x2000
+#define PRID_IMP_R4700          0x2100
+#define PRID_IMP_TX39           0x2200
+#define PRID_IMP_R4640          0x2200
+#define PRID_IMP_R4650          0x2200          /* Same as R4640 */
+#define PRID_IMP_R5000          0x2300
+#define PRID_IMP_TX49           0x2d00
+#define PRID_IMP_SONIC          0x2400
+#define PRID_IMP_MAGIC          0x2500
+#define PRID_IMP_RM7000         0x2700
+#define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
+#define PRID_IMP_RM9000         0x3400
+#define PRID_IMP_R5432          0x5400
+#define PRID_IMP_R5500          0x5500
+#define PRID_IMP_4KC            0x8000
+#define PRID_IMP_5KC            0x8100
+#define PRID_IMP_20KC           0x8200
+#define PRID_IMP_4KEC           0x8400
+#define PRID_IMP_4KSC           0x8600
+#define PRID_IMP_25KF           0x8800
+#define PRID_IMP_5KE            0x8900
+#define PRID_IMP_4KECR2         0x9000
+#define PRID_IMP_4KEMPR2        0x9100
+#define PRID_IMP_4KSD           0x9200
+#define PRID_IMP_24K            0x9300
+
+#define PRID_IMP_UNKNOWN        0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+
+#define PRID_IMP_SB1            0x0100
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
+ */
+
+#define PRID_IMP_SR71000        0x0400
+
+/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+
+#define PRID_REV_TX4927         0x0022
+#define PRID_REV_TX4937         0x0030
+#define PRID_REV_R4400          0x0040
+#define PRID_REV_R3000A         0x0030
+#define PRID_REV_R3000          0x0020
+#define PRID_REV_R2000A         0x0010
+#define PRID_REV_TX3912         0x0010
+#define PRID_REV_TX3922         0x0030
+#define PRID_REV_TX3927         0x0040
+#define PRID_REV_VR4111         0x0050
+#define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
+#define PRID_REV_VR4121         0x0060
+#define PRID_REV_VR4122         0x0070
+#define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
+#define PRID_REV_VR4130         0x0080
+
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0                               | Implementation | Revision       |
+ * +---------------------------------+----------------+----------------+
+ *  31                             16 15             8 7              0
+ */
+
+#define FPIR_IMP_NONE           0x0000
+
+#define CPU_UNKNOWN              0
+#define CPU_R2000                1
+#define CPU_R3000                2
+#define CPU_R3000A               3
+#define CPU_R3041                4
+#define CPU_R3051                5
+#define CPU_R3052                6
+#define CPU_R3081                7
+#define CPU_R3081E               8
+#define CPU_R4000PC              9
+#define CPU_R4000SC             10
+#define CPU_R4000MC             11
+#define CPU_R4200               12
+#define CPU_R4400PC             13
+#define CPU_R4400SC             14
+#define CPU_R4400MC             15
+#define CPU_R4600               16
+#define CPU_R6000               17
+#define CPU_R6000A              18
+#define CPU_R8000               19
+#define CPU_R10000              20
+#define CPU_R12000              21
+#define CPU_R4300               22
+#define CPU_R4650               23
+#define CPU_R4700               24
+#define CPU_R5000               25
+#define CPU_R5000A              26
+#define CPU_R4640               27
+#define CPU_NEVADA              28
+#define CPU_RM7000              29
+#define CPU_R5432               30
+#define CPU_4KC                 31
+#define CPU_5KC                 32
+#define CPU_R4310               33
+#define CPU_SB1                 34
+#define CPU_TX3912              35
+#define CPU_TX3922              36
+#define CPU_TX3927              37
+#define CPU_AU1000              38
+#define CPU_4KEC                39
+#define CPU_4KSC                40
+#define CPU_VR41XX              41
+#define CPU_R5500               42
+#define CPU_TX49XX              43
+#define CPU_AU1500              44
+#define CPU_20KC                45
+#define CPU_VR4111              46
+#define CPU_VR4121              47
+#define CPU_VR4122              48
+#define CPU_VR4131              49
+#define CPU_VR4181              50
+#define CPU_VR4181A             51
+#define CPU_AU1100              52
+#define CPU_SR71000             53
+#define CPU_RM9000              54
+#define CPU_25KF                55
+#define CPU_VR4133              56
+#define CPU_AU1550              57
+#define CPU_24K                 58
+#define CPU_LAST                58
+
+/*
+ * ISA Level encodings
+ *
+ */
+#define MIPS_CPU_ISA_I          0x00000001
+#define MIPS_CPU_ISA_II         0x00000002
+#define MIPS_CPU_ISA_III        0x00008003
+#define MIPS_CPU_ISA_IV         0x00008004
+#define MIPS_CPU_ISA_V          0x00008005
+#define MIPS_CPU_ISA_M32        0x00000020
+#define MIPS_CPU_ISA_M64        0x00008040
+
+/*
+ * Bit 15 encodes if an ISA level supports 64-bit operations.
+ */
+#define MIPS_CPU_ISA_64BIT      0x00008000
+
+/*
+ * CPU Option encodings
+ */
+#define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
+/* Leave a spare bit for variant MMU types... */
+#define MIPS_CPU_4KEX           0x00000004 /* "R4K" exception model */
+#define MIPS_CPU_4KTLB          0x00000008 /* "R4K" TLB handler */
+#define MIPS_CPU_FPU            0x00000010 /* CPU has FPU */
+#define MIPS_CPU_32FPR          0x00000020 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER        0x00000040 /* Cycle count/compare */
+#define MIPS_CPU_WATCH          0x00000080 /* watchpoint registers */
+#define MIPS_CPU_MIPS16         0x00000100 /* code compression */
+#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
+#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
+#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_SUBSET_CACHES  0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+
+#endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/cputime.h b/include/asm-mips/cputime.h
new file mode 100644
index 000000000000..c00eacbdd979
--- /dev/null
+++ b/include/asm-mips/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __MIPS_CPUTIME_H
+#define __MIPS_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __MIPS_CPUTIME_H */
diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h
new file mode 100644
index 000000000000..559db66b9790
--- /dev/null
+++ b/include/asm-mips/current.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2002 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CURRENT_H
+#define _ASM_CURRENT_H
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct * get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current         get_current()
+
+#endif /* _ASM_CURRENT_H */
diff --git a/include/asm-mips/ddb5074.h b/include/asm-mips/ddb5074.h
new file mode 100644
index 000000000000..0d09ac27f9a5
--- /dev/null
+++ b/include/asm-mips/ddb5074.h
@@ -0,0 +1,11 @@
+/*
+ *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ */
+
+extern void ddb5074_led_hex(int hex);
+extern void ddb5074_led_d2(int on);
+extern void ddb5074_led_d3(int on);
+
diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h
new file mode 100644
index 000000000000..58d88306af65
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5074.h
@@ -0,0 +1,38 @@
+/*
+ *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ */
+
+#ifndef _ASM_DDB5XXX_DDB5074_H
+#define _ASM_DDB5XXX_DDB5074_H
+
+#include <asm/nile4.h>
+
+#define DDB_SDRAM_SIZE      0x04000000      /* 64MB */
+
+#define DDB_PCI_IO_BASE     0x06000000
+#define DDB_PCI_IO_SIZE     0x02000000      /* 32 MB */
+
+#define DDB_PCI_MEM_BASE    0x08000000
+#define DDB_PCI_MEM_SIZE    0x08000000  /* 128 MB */
+
+#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
+#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
+
+#define NILE4_PCI_IO_BASE   0xa6000000
+#define NILE4_PCI_MEM_BASE  0xa8000000
+#define NILE4_PCI_CFG_BASE  NILE4_PCI_MEM_BASE
+#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
+
+#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
+#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
+#define CPU_NILE4_CASCADE 2
+
+extern void ddb5074_led_hex(int hex);
+extern void ddb5074_led_d2(int on);
+extern void ddb5074_led_d3(int on);
+
+extern void nile4_irq_setup(u32 base);
+#endif
diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h
new file mode 100644
index 000000000000..4c23390d9354
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5476.h
@@ -0,0 +1,157 @@
+/*
+ * header file specific for ddb5476
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+/*
+ *  Memory map (physical address)
+ *
+ *  Note most of the following address must be properly aligned by the
+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  PCI_IO_BASE must be aligned along 16MB boundary.
+ */
+#define DDB_SDRAM_BASE          0x00000000
+#define DDB_SDRAM_SIZE          0x04000000      /* 64MB */
+
+#define DDB_DCS3_BASE           0x04000000      /* flash 1 */
+#define DDB_DCS3_SIZE           0x01000000      /* 16MB */
+
+#define DDB_DCS2_BASE           0x05000000      /* flash 2 */
+#define DDB_DCS2_SIZE           0x01000000      /* 16MB */
+
+#define DDB_PCI_IO_BASE         0x06000000
+#define DDB_PCI_IO_SIZE         0x02000000      /* 32 MB */
+
+#define DDB_PCI_MEM_BASE        0x08000000
+#define DDB_PCI_MEM_SIZE        0x08000000      /* 128 MB */
+
+#define DDB_DCS5_BASE           0x13000000      /* DDB status regs */
+#define DDB_DCS5_SIZE           0x00200000      /* 2MB, 8-bit */
+
+#define DDB_DCS4_BASE           0x14000000      /* DDB control regs */
+#define DDB_DCS4_SIZE           0x00200000      /* 2MB, 8-bit */
+
+#define DDB_INTCS_BASE          0x1fa00000      /* VRC5476 control regs */
+#define DDB_INTCS_SIZE          0x00200000      /* 2MB */
+
+#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
+#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
+
+
+/* aliases */
+#define DDB_PCI_CONFIG_BASE     DDB_PCI_MEM_BASE
+#define DDB_PCI_CONFIG_SIZE     DDB_PCI_MEM_SIZE
+
+/* PCI intr ack share PCIW0 with PCI IO */
+#define DDB_PCI_IACK_BASE       DDB_PCI_IO_BASE
+
+/*
+ * Interrupt mapping
+ *
+ * We have three interrupt controllers:
+ *
+ *   . CPU itself - 8 sources
+ *   . i8259 - 16 sources
+ *   . vrc5476 - 16 sources
+ *
+ *  They connected as follows:
+ *    all vrc5476 interrupts are routed to cpu IP2 (by software setting)
+ *    all i2869 are routed to INTC in vrc5476 (by hardware connection)
+ *
+ *  All VRC5476 PCI interrupts are level-triggered (no ack needed).
+ *  All PCI irq but INTC are active low.
+ */
+
+/*
+ * irq number block assignment
+ */
+
+#define NUM_CPU_IRQ             8
+#define NUM_I8259_IRQ           16
+#define NUM_VRC5476_IRQ         16
+
+#define DDB_IRQ_BASE            0
+
+#define I8259_IRQ_BASE          DDB_IRQ_BASE
+#define VRC5476_IRQ_BASE        (I8259_IRQ_BASE + NUM_I8259_IRQ)
+#define CPU_IRQ_BASE            (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
+
+/*
+ * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
+ */
+
+#define VRC5476_IRQ_CPCE        0       /* cpu parity error */
+#define VRC5476_IRQ_CNTD        1       /* cpu no target */
+#define VRC5476_IRQ_MCE         2       /* memory check error */
+#define VRC5476_IRQ_DMA         3       /* DMA */
+#define VRC5476_IRQ_UART        4       /* vrc5476 builtin UART, not used */
+#define VRC5476_IRQ_WDOG        5       /* watchdog timer */
+#define VRC5476_IRQ_GPT         6       /* general purpose timer */
+#define VRC5476_IRQ_LBRT        7       /* local bus read timeout */
+#define VRC5476_IRQ_INTA        8       /* PCI INT #A */
+#define VRC5476_IRQ_INTB        9       /* PCI INT #B */
+#define VRC5476_IRQ_INTC        10      /* PCI INT #C */
+#define VRC5476_IRQ_INTD        11      /* PCI INT #D */
+#define VRC5476_IRQ_INTE        12      /* PCI INT #E */
+#define VRC5476_IRQ_RESERVED_13 13      /* reserved  */
+#define VRC5476_IRQ_PCIS        14      /* PCI SERR #  */
+#define VRC5476_IRQ_PCI         15      /* PCI internal error */
+
+/*
+ * i2859 irq assignment
+ */
+#define I8259_IRQ_RESERVED_0    0
+#define I8259_IRQ_KEYBOARD      1       /* M1543 default */
+#define I8259_IRQ_CASCADE       2
+#define I8259_IRQ_UART_B        3       /* M1543 default, may conflict with RTC according to schematic diagram  */
+#define I8259_IRQ_UART_A        4       /* M1543 default */
+#define I8259_IRQ_PARALLEL      5       /* M1543 default */
+#define I8259_IRQ_RESERVED_6    6
+#define I8259_IRQ_RESERVED_7    7
+#define I8259_IRQ_RTC           8       /* who set this? */
+#define I8259_IRQ_USB           9       /* ddb_setup */
+#define I8259_IRQ_PMU           10      /* ddb_setup */
+#define I8259_IRQ_RESERVED_11   11
+#define I8259_IRQ_RESERVED_12   12      /* m1543_irq_setup */
+#define I8259_IRQ_RESERVED_13   13
+#define I8259_IRQ_HDC1          14      /* default and ddb_setup */
+#define I8259_IRQ_HDC2          15      /* default */
+
+
+/*
+ * misc
+ */
+#define VRC5476_I8259_CASCADE   VRC5476_IRQ_INTC
+#define CPU_VRC5476_CASCADE     2
+
+#define is_i8259_irq(irq)       ((irq) < NUM_I8259_IRQ)
+#define nile4_to_irq(n)         ((n)+NUM_I8259_IRQ)
+#define irq_to_nile4(n)         ((n)-NUM_I8259_IRQ)
+
+/*
+ * low-level irq functions
+ */
+#ifndef __ASSEMBLY__
+extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+extern void nile4_map_irq_all(int cpu_irq);
+extern void nile4_enable_irq(int nile4_irq);
+extern void nile4_disable_irq(int nile4_irq);
+extern void nile4_disable_irq_all(void);
+extern u16 nile4_get_irq_stat(int cpu_irq);
+extern void nile4_enable_irq_output(int cpu_irq);
+extern void nile4_disable_irq_output(int cpu_irq);
+extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+extern void nile4_clear_irq(int nile4_irq);
+extern void nile4_clear_irq_mask(u32 mask);
+extern u8 nile4_i8259_iack(void);
+extern void nile4_dump_irq_status(void);        /* Debug */
+#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
new file mode 100644
index 000000000000..ae3e2a38fd5f
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -0,0 +1,346 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * include/asm-mips/ddb5xxx/ddb5477.h
+ *     DDB 5477 specific definitions and macros.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#ifndef __ASM_DDB5XXX_DDB5477_H
+#define __ASM_DDB5XXX_DDB5477_H
+
+#include <linux/config.h>
+
+/*
+ * This contains macros that are specific to DDB5477 or renamed from
+ * DDB5476.
+ */
+
+/*
+ * renamed PADRs
+ */
+#define DDB_LCS0        DDB_DCS2
+#define DDB_LCS1        DDB_DCS3
+#define DDB_LCS2        DDB_DCS4
+#define DDB_VRC5477     DDB_INTCS
+
+/*
+ * New CPU interface registers
+ */
+#define DDB_INTCTRL0    0x0400  /* Interrupt Control 0 */
+#define DDB_INTCTRL1    0x0404  /* Interrupt Control 1 */
+#define DDB_INTCTRL2    0x0408  /* Interrupt Control 2 */
+#define DDB_INTCTRL3    0x040c  /* Interrupt Control 3 */
+
+#define DDB_INT0STAT    0x0420  /* INT0 Status [R] */
+#define DDB_INT1STAT    0x0428  /* INT1 Status [R] */
+#define DDB_INT2STAT    0x0430  /* INT2 Status [R] */
+#define DDB_INT3STAT    0x0438  /* INT3 Status [R] */
+#define DDB_INT4STAT    0x0440  /* INT4 Status [R] */
+#define DDB_NMISTAT     0x0450  /* NMI Status [R] */
+
+#define DDB_INTCLR32    0x0468  /* Interrupt Clear */
+
+#define DDB_INTPPES0    0x0470  /* PCI0 Interrupt Control */
+#define DDB_INTPPES1    0x0478  /* PCI1 Interrupt Control */
+
+#undef  DDB_CPUSTAT             /* duplicate in Vrc-5477 */
+#define DDB_CPUSTAT     0x0480  /* CPU Status [R] */
+#define DDB_BUSCTRL     0x0488  /* Internal Bus Control */
+
+
+/*
+ * Timer registers
+ */
+#define DDB_REFCTRL_L   DDB_T0CTRL
+#define DDB_REFCTRL_H   (DDB_T0CTRL+4)
+#define DDB_REFCNTR     DDB_T0CNTR
+#define DDB_SPT0CTRL_L  DDB_T1CTRL
+#define DDB_SPT0CTRL_H  (DDB_T1CTRL+4)
+#define DDB_SPT1CTRL_L  DDB_T2CTRL
+#define DDB_SPT1CTRL_H  (DDB_T2CTRL+4)
+#define DDB_SPT1CNTR    DDB_T1CTRL
+#define DDB_WDTCTRL_L   DDB_T3CTRL
+#define DDB_WDTCTRL_H   (DDB_T3CTRL+4)
+#define DDB_WDTCNTR     DDB_T3CNTR
+
+/*
+ * DMA registers are moved.  We don't care about it for now. TODO.
+ */
+
+/*
+ * BARs for ext PCI (PCI0)
+ */
+#undef  DDB_BARC
+#undef  DDB_BARB
+
+#define DDB_BARC0       0x0210  /* PCI0 Control */
+#define DDB_BARM010     0x0218  /* PCI0 SDRAM bank01 */
+#define DDB_BARM230     0x0220  /* PCI0 SDRAM bank23 */
+#define DDB_BAR00       0x0240  /* PCI0 LDCS0 */
+#define DDB_BAR10       0x0248  /* PCI0 LDCS1 */
+#define DDB_BAR20       0x0250  /* PCI0 LDCS2 */
+#define DDB_BAR30       0x0258  /* PCI0 LDCS3 */
+#define DDB_BAR40       0x0260  /* PCI0 LDCS4 */
+#define DDB_BAR50       0x0268  /* PCI0 LDCS5 */
+#define DDB_BARB0       0x0280  /* PCI0 BOOT */
+#define DDB_BARP00      0x0290  /* PCI0 for IOPCI Window0 */
+#define DDB_BARP10      0x0298  /* PCI0 for IOPCI Window1 */
+
+/*
+ * BARs for IOPIC (PCI1)
+ */
+#define DDB_BARC1       0x0610  /* PCI1 Control */
+#define DDB_BARM011     0x0618  /* PCI1 SDRAM bank01 */
+#define DDB_BARM231     0x0620  /* PCI1 SDRAM bank23 */
+#define DDB_BAR01       0x0640  /* PCI1 LDCS0 */
+#define DDB_BAR11       0x0648  /* PCI1 LDCS1 */
+#define DDB_BAR21       0x0650  /* PCI1 LDCS2 */
+#define DDB_BAR31       0x0658  /* PCI1 LDCS3 */
+#define DDB_BAR41       0x0660  /* PCI1 LDCS4 */
+#define DDB_BAR51       0x0668  /* PCI1 LDCS5 */
+#define DDB_BARB1       0x0680  /* PCI1 BOOT */
+#define DDB_BARP01      0x0690  /* PCI1 for ext PCI Window0 */
+#define DDB_BARP11      0x0698  /* PCI1 for ext PCI Window1 */
+
+/*
+ * Other registers for ext PCI (PCI0)
+ */
+#define DDB_PCIINIT00   0x02f0  /* PCI0 Initiator 0 */
+#define DDB_PCIINIT10   0x02f8  /* PCI0 Initiator 1 */
+
+#define DDB_PCISWP0     0x02b0  /* PCI0 Swap */
+#define DDB_PCIERR0     0x02b8  /* PCI0 Error */
+
+#define DDB_PCICTL0_L   0x02e0  /* PCI0 Control-L */
+#define DDB_PCICTL0_H   0x02e4  /* PCI0 Control-H */
+#define DDB_PCIARB0_L   0x02e8  /* PCI0 Arbitration-L */
+#define DDB_PCIARB0_H   0x02ec  /* PCI0 Arbitration-H */
+
+/*
+ * Other registers for IOPCI (PCI1)
+ */
+#define DDB_IOPCIW0     0x00d0  /* PCI Address Window 0 [R/W] */
+#define DDB_IOPCIW1     0x00d8  /* PCI Address Window 1 [R/W] */
+
+#define DDB_PCIINIT01   0x06f0  /* PCI1 Initiator 0 */
+#define DDB_PCIINIT11   0x06f8  /* PCI1 Initiator 1 */
+
+#define DDB_PCISWP1     0x06b0  /* PCI1 Swap */
+#define DDB_PCIERR1     0x06b8  /* PCI1 Error */
+
+#define DDB_PCICTL1_L   0x06e0  /* PCI1 Control-L */
+#define DDB_PCICTL1_H   0x06e4  /* PCI1 Control-H */
+#define DDB_PCIARB1_L   0x06e8  /* PCI1 Arbitration-L */
+#define DDB_PCIARB1_H   0x06ec  /* PCI1 Arbitration-H */
+
+/*
+ * Local Bus
+ */
+#define DDB_LCST0       0x0110  /* LB Chip Select Timing 0 */
+#define DDB_LCST1       0x0118  /* LB Chip Select Timing 1 */
+#undef DDB_LCST2
+#define DDB_LCST2       0x0120  /* LB Chip Select Timing 2 */
+#undef DDB_LCST3
+#undef DDB_LCST4
+#undef DDB_LCST5
+#undef DDB_LCST6
+#undef DDB_LCST7
+#undef DDB_LCST8
+#define DDB_ERRADR      0x0150  /* Error Address Register */
+#define DDB_ERRCS       0x0160
+#define DDB_BTM         0x0170  /* Boot Time Mode value */
+
+/*
+ * MISC registers
+ */
+#define DDB_GIUFUNSEL   0x4040  /* select dual-func pins */
+#define DDB_PIBMISC     0x0750  /* USB buffer enable / power saving */
+
+/*
+ *  Memory map (physical address)
+ *
+ *  Note most of the following address must be properly aligned by the
+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  PCI_IO_BASE must be aligned along 16MB boundary.
+ */
+
+/* the actual ram size is detected at run-time */
+#define DDB_SDRAM_BASE          0x00000000
+#define DDB_MAX_SDRAM_SIZE      0x08000000      /* less than 128MB */
+
+#define DDB_PCI0_MEM_BASE       0x08000000
+#define DDB_PCI0_MEM_SIZE       0x08000000      /* 128 MB */
+
+#define DDB_PCI1_MEM_BASE       0x10000000
+#define DDB_PCI1_MEM_SIZE       0x08000000      /* 128 MB */
+
+#define DDB_PCI0_CONFIG_BASE    0x18000000
+#define DDB_PCI0_CONFIG_SIZE    0x01000000      /* 16 MB */
+
+#define DDB_PCI1_CONFIG_BASE    0x19000000
+#define DDB_PCI1_CONFIG_SIZE    0x01000000      /* 16 MB */
+
+#define DDB_PCI_IO_BASE         0x1a000000      /* we concatenate two IOs */
+#define DDB_PCI0_IO_BASE        0x1a000000
+#define DDB_PCI0_IO_SIZE        0x01000000      /* 16 MB */
+#define DDB_PCI1_IO_BASE        0x1b000000
+#define DDB_PCI1_IO_SIZE        0x01000000      /* 16 MB */
+
+#define DDB_LCS0_BASE           0x1c000000      /* flash memory */
+#define DDB_LCS0_SIZE           0x01000000      /* 16 MB */
+
+#define DDB_LCS1_BASE           0x1d000000      /* misc */
+#define DDB_LCS1_SIZE           0x01000000      /* 16 MB */
+
+#define DDB_LCS2_BASE           0x1e000000      /* Mezzanine */
+#define DDB_LCS2_SIZE           0x01000000      /* 16 MB */
+
+#define DDB_VRC5477_BASE        0x1fa00000      /* VRC5477 control regs */
+#define DDB_VRC5477_SIZE        0x00200000      /* 2MB */
+
+#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
+#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
+
+#define DDB_LED                 DDB_LCS1_BASE + 0x10000
+
+
+/*
+ * DDB5477 specific functions
+ */
+#ifndef __ASSEMBLY__
+extern void ddb5477_irq_setup(void);
+
+/* route irq to cpu int pin */
+extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
+
+/* low-level routine for enabling vrc5477 irq, bypassing high-level */
+extern void ll_vrc5477_irq_enable(int vrc5477_irq);
+extern void ll_vrc5477_irq_disable(int vrc5477_irq);
+#endif /* !__ASSEMBLY__ */
+
+/* PCI intr ack share PCIW0 with PCI IO */
+#define DDB_PCI_IACK_BASE       DDB_PCI_IO_BASE
+
+/*
+ * Interrupt mapping
+ *
+ * We have three interrupt controllers:
+ *
+ *   . CPU itself - 8 sources
+ *   . i8259 - 16 sources
+ *   . vrc5477 - 32 sources
+ *
+ *  They connected as follows:
+ *    all vrc5477 interrupts are routed to cpu IP2 (by software setting)
+ *    all i8359 are routed to INTC in vrc5477 (by hardware connection)
+ *
+ *  All VRC5477 PCI interrupts are level-triggered (no ack needed).
+ *  All PCI irq but INTC are active low.
+ */
+
+/* 
+ * irq number block assignment
+ */
+
+#define NUM_CPU_IRQ             8
+#define NUM_I8259_IRQ           16
+#define NUM_VRC5477_IRQ         32
+
+#define DDB_IRQ_BASE            0
+
+#define I8259_IRQ_BASE          DDB_IRQ_BASE
+#define VRC5477_IRQ_BASE        (I8259_IRQ_BASE + NUM_I8259_IRQ)
+#define CPU_IRQ_BASE            (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
+
+/*
+ * vrc5477 irq defs
+ */
+
+#define VRC5477_IRQ_CPCE        (0 + VRC5477_IRQ_BASE)  /* cpu parity error */
+#define VRC5477_IRQ_CNTD        (1 + VRC5477_IRQ_BASE)  /* cpu no target */
+#define VRC5477_IRQ_I2C         (2 + VRC5477_IRQ_BASE)  /* I2C */
+#define VRC5477_IRQ_DMA         (3 + VRC5477_IRQ_BASE)  /* DMA */
+#define VRC5477_IRQ_UART0       (4 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_WDOG        (5 + VRC5477_IRQ_BASE)  /* watchdog timer */
+#define VRC5477_IRQ_SPT1        (6 + VRC5477_IRQ_BASE)    /* special purpose timer 1 */
+#define VRC5477_IRQ_LBRT        (7 + VRC5477_IRQ_BASE)  /* local bus read timeout */
+#define VRC5477_IRQ_INTA        (8 + VRC5477_IRQ_BASE)  /* PCI INT #A */
+#define VRC5477_IRQ_INTB        (9 + VRC5477_IRQ_BASE)  /* PCI INT #B */
+#define VRC5477_IRQ_INTC        (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
+#define VRC5477_IRQ_INTD        (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
+#define VRC5477_IRQ_INTE        (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
+#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved  */
+#define VRC5477_IRQ_PCIS        (14 + VRC5477_IRQ_BASE) /* PCI SERR #  */
+#define VRC5477_IRQ_PCI         (15 + VRC5477_IRQ_BASE) /* PCI internal error */
+#define VRC5477_IRQ_IOPCI_INTA  (16 + VRC5477_IRQ_BASE)      /* USB-H */
+#define VRC5477_IRQ_IOPCI_INTB  (17 + VRC5477_IRQ_BASE)      /* USB-P */
+#define VRC5477_IRQ_IOPCI_INTC  (18 + VRC5477_IRQ_BASE)      /* AC97 */
+#define VRC5477_IRQ_IOPCI_INTD  (19 + VRC5477_IRQ_BASE)      /* Reserved */
+#define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)     
+#define VRC5477_IRQ_SPT0        (21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
+#define VRC5477_IRQ_GPT0        (22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
+#define VRC5477_IRQ_GPT1        (23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
+#define VRC5477_IRQ_GPT2        (24 + VRC5477_IRQ_BASE)      /* general purpose timer 2 */
+#define VRC5477_IRQ_GPT3        (25 + VRC5477_IRQ_BASE)      /* general purpose timer 3 */
+#define VRC5477_IRQ_GPIO        (26 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_SIO0        (27 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_SIO1        (28 + VRC5477_IRQ_BASE)
+#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE)      /* reserved */
+#define VRC5477_IRQ_IOPCISERR   (30 + VRC5477_IRQ_BASE)      /* IO PCI SERR # */
+#define VRC5477_IRQ_IOPCI       (31 + VRC5477_IRQ_BASE)
+
+/*
+ * i2859 irq assignment
+ */
+#define I8259_IRQ_RESERVED_0    (0 + I8259_IRQ_BASE)    
+#define I8259_IRQ_KEYBOARD      (1 + I8259_IRQ_BASE)    /* M1543 default */
+#define I8259_IRQ_CASCADE       (2 + I8259_IRQ_BASE)
+#define I8259_IRQ_UART_B        (3 + I8259_IRQ_BASE)    /* M1543 default, may conflict with RTC according to schematic diagram  */
+#define I8259_IRQ_UART_A        (4 + I8259_IRQ_BASE)    /* M1543 default */
+#define I8259_IRQ_PARALLEL      (5 + I8259_IRQ_BASE)    /* M1543 default */
+#define I8259_IRQ_RESERVED_6    (6 + I8259_IRQ_BASE)
+#define I8259_IRQ_RESERVED_7    (7 + I8259_IRQ_BASE)
+#define I8259_IRQ_RTC           (8 + I8259_IRQ_BASE)    /* who set this? */
+#define I8259_IRQ_USB           (9 + I8259_IRQ_BASE)    /* ddb_setup */
+#define I8259_IRQ_PMU           (10 + I8259_IRQ_BASE)   /* ddb_setup */
+#define I8259_IRQ_RESERVED_11   (11 + I8259_IRQ_BASE)
+#define I8259_IRQ_RESERVED_12   (12 + I8259_IRQ_BASE)   /* m1543_irq_setup */
+#define I8259_IRQ_RESERVED_13   (13 + I8259_IRQ_BASE)
+#define I8259_IRQ_HDC1          (14 + I8259_IRQ_BASE)   /* default and ddb_setup */
+#define I8259_IRQ_HDC2          (15 + I8259_IRQ_BASE)   /* default */
+
+
+/*
+ * misc
+ */
+#define VRC5477_I8259_CASCADE   (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
+#define CPU_VRC5477_CASCADE     2
+
+/*
+ * debug routines
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_RUNTIME_DEBUG)
+extern void vrc5477_show_pdar_regs(void);
+extern void vrc5477_show_pci_regs(void);
+extern void vrc5477_show_bar_regs(void);
+extern void vrc5477_show_int_regs(void);
+extern void vrc5477_show_all_regs(void);
+#endif
+
+/*
+ * RAM size
+ */
+extern int board_ram_size;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_DDB5XXX_DDB5477_H */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
new file mode 100644
index 000000000000..873c03f2c5fe
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5xxx.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                    Sony Software Development Center Europe (SDCE), Brussels
+ *
+ * include/asm-mips/ddb5xxx/ddb5xxx.h
+ *     Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_DDB5XXX_DDB5XXX_H
+#define __ASM_DDB5XXX_DDB5XXX_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/*
+ *  This file is based on the following documentation:
+ *
+ *      NEC Vrc 5074 System Controller Data Sheet, June 1998
+ *
+ * [jsun] It is modified so that this file only contains the macros
+ * that are true for all DDB 5xxx boards.  The modification is based on
+ *
+ *      uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
+ *      Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
+ *
+ */
+
+
+#define DDB_BASE                0xbfa00000
+#define DDB_SIZE                0x00200000              /* 2 MB */
+
+
+/*
+ *  Physical Device Address Registers (PDARs)
+ */
+
+#define DDB_SDRAM0      0x0000  /* SDRAM Bank 0 [R/W] */
+#define DDB_SDRAM1      0x0008  /* SDRAM Bank 1 [R/W] */
+#define DDB_DCS2        0x0010  /* Device Chip-Select 2 [R/W] */
+#define DDB_DCS3        0x0018  /* Device Chip-Select 3 [R/W] */
+#define DDB_DCS4        0x0020  /* Device Chip-Select 4 [R/W] */
+#define DDB_DCS5        0x0028  /* Device Chip-Select 5 [R/W] */
+#define DDB_DCS6        0x0030  /* Device Chip-Select 6 [R/W] */
+#define DDB_DCS7        0x0038  /* Device Chip-Select 7 [R/W] */
+#define DDB_DCS8        0x0040  /* Device Chip-Select 8 [R/W] */
+#define DDB_PCIW0       0x0060  /* PCI Address Window 0 [R/W] */
+#define DDB_PCIW1       0x0068  /* PCI Address Window 1 [R/W] */
+#define DDB_INTCS       0x0070  /* Controller Internal Registers and Devices */
+                                /* [R/W] */
+#define DDB_BOOTCS      0x0078  /* Boot ROM Chip-Select [R/W] */
+/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
+
+/*
+ *  CPU Interface Registers
+ */
+#define DDB_CPUSTAT     0x0080  /* CPU Status [R/W] */
+#define DDB_INTCTRL     0x0088  /* Interrupt Control [R/W] */
+#define DDB_INTSTAT0    0x0090  /* Interrupt Status 0 [R] */
+#define DDB_INTSTAT1    0x0098  /* Interrupt Status 1 and CPU Interrupt */
+                                /* Enable [R/W] */
+#define DDB_INTCLR      0x00A0  /* Interrupt Clear [R/W] */
+#define DDB_INTPPES     0x00A8  /* PCI Interrupt Control [R/W] */
+
+
+/*
+ *  Memory-Interface Registers
+ */
+#define DDB_MEMCTRL     0x00C0  /* Memory Control */
+#define DDB_ACSTIME     0x00C8  /* Memory Access Timing [R/W] */
+#define DDB_CHKERR      0x00D0  /* Memory Check Error Status [R] */
+
+
+/*
+ *  PCI-Bus Registers
+ */
+#define DDB_PCICTRL     0x00E0  /* PCI Control [R/W] */
+#define DDB_PCIARB      0x00E8  /* PCI Arbiter [R/W] */
+#define DDB_PCIINIT0    0x00F0  /* PCI Master (Initiator) 0 [R/W] */
+#define DDB_PCIINIT1    0x00F8  /* PCI Master (Initiator) 1 [R/W] */
+#define DDB_PCIERR      0x00B8  /* PCI Error [R/W] */
+
+
+/*
+ *  Local-Bus Registers
+ */
+#define DDB_LCNFG       0x0100  /* Local Bus Configuration [R/W] */
+#define DDB_LCST2       0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
+#define DDB_LCST3       0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
+#define DDB_LCST4       0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
+#define DDB_LCST5       0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
+#define DDB_LCST6       0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
+#define DDB_LCST7       0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
+#define DDB_LCST8       0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
+#define DDB_DCSFN       0x0150  /* Device Chip-Select Muxing and Output */
+                                /* Enables [R/W] */
+#define DDB_DCSIO       0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
+#define DDB_BCST        0x0178  /* Local Boot Chip-Select Timing [R/W] */
+
+
+/*
+ *  DMA Registers
+ */
+#define DDB_DMACTRL0    0x0180  /* DMA Control 0 [R/W] */
+#define DDB_DMASRCA0    0x0188  /* DMA Source Address 0 [R/W] */
+#define DDB_DMADESA0    0x0190  /* DMA Destination Address 0 [R/W] */
+#define DDB_DMACTRL1    0x0198  /* DMA Control 1 [R/W] */
+#define DDB_DMASRCA1    0x01A0  /* DMA Source Address 1 [R/W] */
+#define DDB_DMADESA1    0x01A8  /* DMA Destination Address 1 [R/W] */
+
+
+/*
+ *  Timer Registers
+ */
+#define DDB_T0CTRL      0x01C0  /* SDRAM Refresh Control [R/W] */
+#define DDB_T0CNTR      0x01C8  /* SDRAM Refresh Counter [R/W] */
+#define DDB_T1CTRL      0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
+#define DDB_T1CNTR      0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
+#define DDB_T2CTRL      0x01E0  /* General-Purpose Timer Control [R/W] */
+#define DDB_T2CNTR      0x01E8  /* General-Purpose Timer Counter [R/W] */
+#define DDB_T3CTRL      0x01F0  /* Watchdog Timer Control [R/W] */
+#define DDB_T3CNTR      0x01F8  /* Watchdog Timer Counter [R/W] */
+
+
+/*
+ *  PCI Configuration Space Registers
+ */
+#define DDB_PCI_BASE    0x0200
+
+#define DDB_VID         0x0200  /* PCI Vendor ID [R] */
+#define DDB_DID         0x0202  /* PCI Device ID [R] */
+#define DDB_PCICMD      0x0204  /* PCI Command [R/W] */
+#define DDB_PCISTS      0x0206  /* PCI Status [R/W] */
+#define DDB_REVID       0x0208  /* PCI Revision ID [R] */
+#define DDB_CLASS       0x0209  /* PCI Class Code [R] */
+#define DDB_CLSIZ       0x020C  /* PCI Cache Line Size [R/W] */
+#define DDB_MLTIM       0x020D  /* PCI Latency Timer [R/W] */
+#define DDB_HTYPE       0x020E  /* PCI Header Type [R] */
+#define DDB_BIST        0x020F  /* BIST [R] (unimplemented) */
+#define DDB_BARC        0x0210  /* PCI Base Address Register Control [R/W] */
+#define DDB_BAR0        0x0218  /* PCI Base Address Register 0 [R/W] */
+#define DDB_BAR1        0x0220  /* PCI Base Address Register 1 [R/W] */
+#define DDB_CIS         0x0228  /* PCI Cardbus CIS Pointer [R] */
+                                /* (unimplemented) */
+#define DDB_SSVID       0x022C  /* PCI Sub-System Vendor ID [R/W] */
+#define DDB_SSID        0x022E  /* PCI Sub-System ID [R/W] */
+#define DDB_ROM         0x0230  /* Expansion ROM Base Address [R] */
+                                /* (unimplemented) */
+#define DDB_INTLIN      0x023C  /* PCI Interrupt Line [R/W] */
+#define DDB_INTPIN      0x023D  /* PCI Interrupt Pin [R] */
+#define DDB_MINGNT      0x023E  /* PCI Min_Gnt [R] (unimplemented) */
+#define DDB_MAXLAT      0x023F  /* PCI Max_Lat [R] (unimplemented) */
+#define DDB_BAR2        0x0240  /* PCI Base Address Register 2 [R/W] */
+#define DDB_BAR3        0x0248  /* PCI Base Address Register 3 [R/W] */
+#define DDB_BAR4        0x0250  /* PCI Base Address Register 4 [R/W] */
+#define DDB_BAR5        0x0258  /* PCI Base Address Register 5 [R/W] */
+#define DDB_BAR6        0x0260  /* PCI Base Address Register 6 [R/W] */
+#define DDB_BAR7        0x0268  /* PCI Base Address Register 7 [R/W] */
+#define DDB_BAR8        0x0270  /* PCI Base Address Register 8 [R/W] */
+#define DDB_BARB        0x0278  /* PCI Base Address Register BOOT [R/W] */
+
+
+/*
+ *  Nile 4 Register Access
+ */
+
+static inline void ddb_sync(void)
+{
+/* The DDB5074 doesn't seem to like these accesses. They kill the board on
+ * interrupt load
+ */
+#ifndef CONFIG_DDB5074
+    volatile u32 *p = (volatile u32 *)0xbfc00000;
+    (void)(*p);
+#endif
+}
+
+static inline void ddb_out32(u32 offset, u32 val)
+{
+    *(volatile u32 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u32 ddb_in32(u32 offset)
+{
+    u32 val = *(volatile u32 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+static inline void ddb_out16(u32 offset, u16 val)
+{
+    *(volatile u16 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u16 ddb_in16(u32 offset)
+{
+    u16 val = *(volatile u16 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+static inline void ddb_out8(u32 offset, u8 val)
+{
+    *(volatile u8 *)(DDB_BASE+offset) = val;
+    ddb_sync();
+}
+
+static inline u8 ddb_in8(u32 offset)
+{
+    u8 val = *(volatile u8 *)(DDB_BASE+offset);
+    ddb_sync();
+    return val;
+}
+
+
+/*
+ *  Physical Device Address Registers
+ */
+
+extern u32
+ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
+extern void
+ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+             int on_memory_bus, int pci_visible);
+
+/*
+ *  PCI Master Registers
+ */
+
+#define DDB_PCICMD_IACK         0       /* PCI Interrupt Acknowledge */
+#define DDB_PCICMD_IO           1       /* PCI I/O Space */
+#define DDB_PCICMD_MEM          3       /* PCI Memory Space */
+#define DDB_PCICMD_CFG          5       /* PCI Configuration Space */
+
+/*
+ * additional options for pci init reg (no shifting needed)
+ */
+#define DDB_PCI_CFGTYPE1     0x200   /* for pci init0/1 regs */
+#define DDB_PCI_ACCESS_32    0x10    /* for pci init0/1 regs */
+
+
+extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
+
+/*
+ * we need to reset pci bus when we start up and shutdown
+ */
+extern void ddb_pci_reset_bus(void);
+
+
+/*
+ * include the board dependent part
+ */
+#if defined(CONFIG_DDB5074)
+#include <asm/ddb5xxx/ddb5074.h>
+#elif defined(CONFIG_DDB5476)
+#include <asm/ddb5xxx/ddb5476.h>
+#elif defined(CONFIG_DDB5477)
+#include <asm/ddb5xxx/ddb5477.h>
+#else
+#error "Unknown DDB board!"
+#endif
+
+#endif /* __ASM_DDB5XXX_DDB5XXX_H */
diff --git a/include/asm-mips/debug.h b/include/asm-mips/debug.h
new file mode 100644
index 000000000000..930f2b75e766
--- /dev/null
+++ b/include/asm-mips/debug.h
@@ -0,0 +1,49 @@
+/*
+ * Debug macros for run-time debugging.
+ * Turned on/off with CONFIG_RUNTIME_DEBUG option.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _ASM_DEBUG_H
+#define _ASM_DEBUG_H
+
+#include <linux/config.h>
+
+/*
+ * run-time macros for catching spurious errors.  Eable CONFIG_RUNTIME_DEBUG in
+ * kernel hacking config menu to use them.
+ *
+ * Use them as run-time debugging aid.  NEVER USE THEM AS ERROR HANDLING CODE!!!
+ */
+
+#ifdef CONFIG_RUNTIME_DEBUG
+
+#include <linux/kernel.h>
+
+#define db_assert(x)  if (!(x)) { \
+        panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); }
+#define db_warn(x)  if (!(x)) { \
+        printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); }
+#define db_verify(x, y) db_assert(x y)
+#define db_verify_warn(x, y) db_warn(x y)
+#define db_run(x)  do { x; } while (0)
+
+#else
+
+#define db_assert(x)
+#define db_warn(x)
+#define db_verify(x, y) x
+#define db_verify_warn(x, y) x
+#define db_run(x)
+
+#endif
+
+#endif /* _ASM_DEBUG_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
new file mode 100644
index 000000000000..724908b0bf13
--- /dev/null
+++ b/include/asm-mips/dec/ecc.h
@@ -0,0 +1,55 @@
+/*
+ *      include/asm-mips/dec/ecc.h
+ *
+ *      ECC handling logic definitions common to DECstation/DECsystem
+ *      5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
+ *      DECsystem 5900 (KN03), 5900/260 (KN05) systems.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_ECC_H
+#define __ASM_MIPS_DEC_ECC_H
+
+/*
+ * Error Address Register bits.
+ * The register is r/wc -- any write clears it.
+ */
+#define KN0X_EAR_VALID          (1<<31)         /* error data valid, bus IRQ */
+#define KN0X_EAR_CPU            (1<<30)         /* CPU/DMA transaction */
+#define KN0X_EAR_WRITE          (1<<29)         /* write/read transaction */
+#define KN0X_EAR_ECCERR         (1<<28)         /* ECC/timeout or overrun */
+#define KN0X_EAR_RES_27         (1<<27)         /* unused */
+#define KN0X_EAR_ADDRESS        (0x7ffffff<<0)  /* address involved */
+
+/*
+ * Error Syndrome Register bits.
+ * The register is frozen when EAR.VALID is set, otherwise it records bits
+ * from the last memory read.  The register is r/wc -- any write clears it.
+ */
+#define KN0X_ESR_VLDHI          (1<<31)         /* error data valid hi word */
+#define KN0X_ESR_CHKHI          (0x7f<<24)      /* check bits read from mem */
+#define KN0X_ESR_SNGHI          (1<<23)         /* single/double bit error */
+#define KN0X_ESR_SYNHI          (0x7f<<16)      /* syndrome from ECC logic */
+#define KN0X_ESR_VLDLO          (1<<15)         /* error data valid lo word */
+#define KN0X_ESR_CHKLO          (0x7f<<8)       /* check bits read from mem */
+#define KN0X_ESR_SNGLO          (1<<7)          /* single/double bit error */
+#define KN0X_ESR_SYNLO          (0x7f<<0)       /* syndrome from ECC logic */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_ecc_be_init(void);
+extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+#endif
+
+#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h
new file mode 100644
index 000000000000..273e4d65bfe6
--- /dev/null
+++ b/include/asm-mips/dec/interrupts.h
@@ -0,0 +1,125 @@
+/*
+ * Miscellaneous definitions used to initialise the interrupt vector table
+ * with the machine-specific interrupt routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 by Paul M. Antoine.
+ * reworked 1998 by Harald Koerfgen.
+ * Copyright (C) 2001, 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_INTERRUPTS_H
+#define __ASM_DEC_INTERRUPTS_H
+
+#include <asm/mipsregs.h>
+
+
+/*
+ * The list of possible system devices which provide an
+ * interrupt.  Not all devices exist on a given system.
+ */
+#define DEC_IRQ_CASCADE         0       /* cascade from CSR or I/O ASIC */
+
+/* Ordinary interrupts */
+#define DEC_IRQ_AB_RECV         1       /* ACCESS.bus receive */
+#define DEC_IRQ_AB_XMIT         2       /* ACCESS.bus transmit */
+#define DEC_IRQ_DZ11            3       /* DZ11 (DC7085) serial */
+#define DEC_IRQ_ASC             4       /* ASC (NCR53C94) SCSI */
+#define DEC_IRQ_FLOPPY          5       /* 82077 FDC */
+#define DEC_IRQ_FPU             6       /* R3k FPU */
+#define DEC_IRQ_HALT            7       /* HALT button or from ACCESS.Bus */
+#define DEC_IRQ_ISDN            8       /* Am79C30A ISDN */
+#define DEC_IRQ_LANCE           9       /* LANCE (Am7990) Ethernet */
+#define DEC_IRQ_BUS             10      /* memory, I/O bus read/write errors */
+#define DEC_IRQ_PSU             11      /* power supply unit warning */
+#define DEC_IRQ_RTC             12      /* DS1287 RTC */
+#define DEC_IRQ_SCC0            13      /* SCC (Z85C30) serial #0 */
+#define DEC_IRQ_SCC1            14      /* SCC (Z85C30) serial #1 */
+#define DEC_IRQ_SII             15      /* SII (DC7061) SCSI */
+#define DEC_IRQ_TC0             16      /* TURBOchannel slot #0 */
+#define DEC_IRQ_TC1             17      /* TURBOchannel slot #1 */
+#define DEC_IRQ_TC2             18      /* TURBOchannel slot #2 */
+#define DEC_IRQ_TIMER           19      /* ARC periodic timer */
+#define DEC_IRQ_VIDEO           20      /* framebuffer */
+
+/* I/O ASIC DMA interrupts */
+#define DEC_IRQ_ASC_MERR        21      /* ASC memory read error */
+#define DEC_IRQ_ASC_ERR         22      /* ASC page overrun */
+#define DEC_IRQ_ASC_DMA         23      /* ASC buffer pointer loaded */
+#define DEC_IRQ_FLOPPY_ERR      24      /* FDC error */
+#define DEC_IRQ_ISDN_ERR        25      /* ISDN memory read/overrun error */
+#define DEC_IRQ_ISDN_RXDMA      26      /* ISDN recv buffer pointer loaded */
+#define DEC_IRQ_ISDN_TXDMA      27      /* ISDN xmit buffer pointer loaded */
+#define DEC_IRQ_LANCE_MERR      28      /* LANCE memory read error */
+#define DEC_IRQ_SCC0A_RXERR     29      /* SCC0A (printer) receive overrun */
+#define DEC_IRQ_SCC0A_RXDMA     30      /* SCC0A receive half page */
+#define DEC_IRQ_SCC0A_TXERR     31      /* SCC0A xmit memory read/overrun */
+#define DEC_IRQ_SCC0A_TXDMA     32      /* SCC0A transmit page end */
+#define DEC_IRQ_AB_RXERR        33      /* ACCESS.bus receive overrun */
+#define DEC_IRQ_AB_RXDMA        34      /* ACCESS.bus receive half page */
+#define DEC_IRQ_AB_TXERR        35      /* ACCESS.bus xmit memory read/ovrn */
+#define DEC_IRQ_AB_TXDMA        36      /* ACCESS.bus transmit page end */
+#define DEC_IRQ_SCC1A_RXERR     37      /* SCC1A (modem) receive overrun */
+#define DEC_IRQ_SCC1A_RXDMA     38      /* SCC1A receive half page */
+#define DEC_IRQ_SCC1A_TXERR     39      /* SCC1A xmit memory read/overrun */
+#define DEC_IRQ_SCC1A_TXDMA     40      /* SCC1A transmit page end */
+
+/* TC5 & TC6 are virtual slots for KN02's onboard devices */
+#define DEC_IRQ_TC5             DEC_IRQ_ASC     /* virtual PMAZ-AA */
+#define DEC_IRQ_TC6             DEC_IRQ_LANCE   /* virtual PMAD-AA */
+
+#define DEC_NR_INTS             41
+
+
+/* Largest of cpu mask_nr tables. */
+#define DEC_MAX_CPU_INTS        6
+/* Largest of asic mask_nr tables. */
+#define DEC_MAX_ASIC_INTS       9
+
+
+/*
+ * CPU interrupt bits common to all systems.
+ */
+#define DEC_CPU_INR_FPU         7       /* R3k FPU */
+#define DEC_CPU_INR_SW1         1       /* software #1 */
+#define DEC_CPU_INR_SW0         0       /* software #0 */
+
+#define DEC_CPU_IRQ_BASE        0       /* first IRQ assigned to CPU */
+
+#define DEC_CPU_IRQ_NR(n)       ((n) + DEC_CPU_IRQ_BASE)
+#define DEC_CPU_IRQ_MASK(n)     (1 << ((n) + CAUSEB_IP))
+#define DEC_CPU_IRQ_ALL         (0xff << CAUSEB_IP)
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Interrupt table structures to hide differences between systems.
+ */
+typedef union { int i; void *p; } int_ptr;
+extern int dec_interrupt[DEC_NR_INTS];
+extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
+extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
+extern int cpu_fpu_mask;
+
+
+/*
+ * Common interrupt routine prototypes for all DECStations
+ */
+extern void kn02_io_int(void);
+extern void kn02xa_io_int(void);
+extern void kn03_io_int(void);
+extern void asic_dma_int(void);
+extern void asic_all_int(void);
+extern void kn02_all_int(void);
+extern void cpu_all_int(void);
+
+extern void dec_intr_unimplemented(void);
+extern void asic_intr_unimplemented(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h
new file mode 100644
index 000000000000..486a5b0a1302
--- /dev/null
+++ b/include/asm-mips/dec/ioasic.h
@@ -0,0 +1,36 @@
+/*
+ *      include/asm-mips/dec/ioasic.h
+ *
+ *      DEC I/O ASIC access operations.
+ *
+ *      Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_DEC_IOASIC_H
+#define __ASM_DEC_IOASIC_H
+
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+extern spinlock_t ioasic_ssr_lock;
+
+extern volatile u32 *ioasic_base;
+
+static inline void ioasic_write(unsigned int reg, u32 v)
+{
+        ioasic_base[reg / 4] = v;
+}
+
+static inline u32 ioasic_read(unsigned int reg)
+{
+        return ioasic_base[reg / 4];
+}
+
+extern void init_ioasic_irqs(int base);
+
+#endif /* __ASM_DEC_IOASIC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
new file mode 100644
index 000000000000..5e18a7510592
--- /dev/null
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the address map in the JUNKIO Asic
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
+#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
+
+#define IOASIC_SLOT_SIZE 0x00040000
+
+/*
+ * Address ranges decoded by the I/O ASIC for onboard devices.
+ */
+#define IOASIC_SYS_ROM  (0*IOASIC_SLOT_SIZE)    /* system board ROM */
+#define IOASIC_IOCTL    (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define IOASIC_ESAR     (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define IOASIC_LANCE    (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define IOASIC_SCC0     (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
+#define IOASIC_VDAC_HI  (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_SCC1     (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
+#define IOASIC_VDAC_LO  (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_TOY      (8*IOASIC_SLOT_SIZE)    /* RTC */
+#define IOASIC_ISDN     (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
+#define IOASIC_ERRADDR  (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
+#define IOASIC_CHKSYN   (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
+#define IOASIC_ACC_BUS  (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
+#define IOASIC_MCR      (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
+#define IOASIC_FLOPPY   (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
+#define IOASIC_SCSI     (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define IOASIC_FDC_DMA  (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
+#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)   /* ??? */
+#define IOASIC_RES_15   (15*IOASIC_SLOT_SIZE)   /* unused? */
+
+
+/*
+ * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
+ */
+                                        /* all systems */
+#define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
+#define IO_REG_SCSI_DMA_BP      0x10    /* SCSI DMA Buffer Pointer */
+#define IO_REG_LANCE_DMA_P      0x20    /* LANCE DMA Pointer */
+#define IO_REG_SCC0A_T_DMA_P    0x30    /* SCC0A Transmit DMA Pointer */
+#define IO_REG_SCC0A_R_DMA_P    0x40    /* SCC0A Receive DMA Pointer */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_T_DMA_P    0x50    /* SCC1A Transmit DMA Pointer */
+#define IO_REG_SCC1A_R_DMA_P    0x60    /* SCC1A Receive DMA Pointer */
+
+                                        /* Maxine */
+#define IO_REG_AB_T_DMA_P       0x50    /* ACCESS.bus Transmit DMA Pointer */
+#define IO_REG_AB_R_DMA_P       0x60    /* ACCESS.bus Receive DMA Pointer */
+#define IO_REG_FLOPPY_DMA_P     0x70    /* Floppy DMA Pointer */
+#define IO_REG_ISDN_T_DMA_P     0x80    /* ISDN Transmit DMA Pointer */
+#define IO_REG_ISDN_T_DMA_BP    0x90    /* ISDN Transmit DMA Buffer Pointer */
+#define IO_REG_ISDN_R_DMA_P     0xa0    /* ISDN Receive DMA Pointer */
+#define IO_REG_ISDN_R_DMA_BP    0xb0    /* ISDN Receive DMA Buffer Pointer */
+
+                                        /* all systems */
+#define IO_REG_DATA_0           0xc0    /* System Data Buffer 0 */
+#define IO_REG_DATA_1           0xd0    /* System Data Buffer 1 */
+#define IO_REG_DATA_2           0xe0    /* System Data Buffer 2 */
+#define IO_REG_DATA_3           0xf0    /* System Data Buffer 3 */
+
+                                        /* all systems */
+#define IO_REG_SSR              0x100   /* System Support Register */
+#define IO_REG_SIR              0x110   /* System Interrupt Register */
+#define IO_REG_SIMR             0x120   /* System Interrupt Mask Reg. */
+#define IO_REG_SAR              0x130   /* System Address Register */
+
+                                        /* Maxine */
+#define IO_REG_ISDN_T_DATA      0x140   /* ISDN Xmit Data Register */
+#define IO_REG_ISDN_R_DATA      0x150   /* ISDN Receive Data Register */
+
+                                        /* all systems */
+#define IO_REG_LANCE_SLOT       0x160   /* LANCE I/O Slot Register */
+#define IO_REG_SCSI_SLOT        0x170   /* SCSI Slot Register */
+#define IO_REG_SCC0A_SLOT       0x180   /* SCC0A DMA Slot Register */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_SLOT       0x190   /* SCC1A DMA Slot Register */
+
+                                        /* Maxine */
+#define IO_REG_AB_SLOT          0x190   /* ACCESS.bus DMA Slot Register */
+#define IO_REG_FLOPPY_SLOT      0x1a0   /* Floppy Slot Register */
+
+                                        /* all systems */
+#define IO_REG_SCSI_SCR         0x1b0   /* SCSI Partial-Word DMA Control */
+#define IO_REG_SCSI_SDR0        0x1c0   /* SCSI DMA Partial Word 0 */
+#define IO_REG_SCSI_SDR1        0x1d0   /* SCSI DMA Partial Word 1 */
+#define IO_REG_FCTR             0x1e0   /* Free-Running Counter */
+#define IO_REG_RES_31           0x1f0   /* unused */
+
+
+/*
+ * The upper 16 bits of the System Support Register are a part of the
+ * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
+ * machines.  The exception is the Maxine, which makes use of the
+ * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
+ * wiring.
+ */
+                                                /* all systems */
+#define IO_SSR_SCC0A_TX_DMA_EN  (1<<31)         /* SCC0A transmit DMA enable */
+#define IO_SSR_SCC0A_RX_DMA_EN  (1<<30)         /* SCC0A receive DMA enable */
+#define IO_SSR_RES_27           (1<<27)         /* unused */
+#define IO_SSR_RES_26           (1<<26)         /* unused */
+#define IO_SSR_RES_25           (1<<25)         /* unused */
+#define IO_SSR_RES_24           (1<<24)         /* unused */
+#define IO_SSR_RES_23           (1<<23)         /* unused */
+#define IO_SSR_SCSI_DMA_DIR     (1<<18)         /* SCSI DMA direction */
+#define IO_SSR_SCSI_DMA_EN      (1<<17)         /* SCSI DMA enable */
+#define IO_SSR_LANCE_DMA_EN     (1<<16)         /* LANCE DMA enable */
+
+                                                /* except Maxine */
+#define IO_SSR_SCC1A_TX_DMA_EN  (1<<29)         /* SCC1A transmit DMA enable */
+#define IO_SSR_SCC1A_RX_DMA_EN  (1<<28)         /* SCC1A receive DMA enable */
+#define IO_SSR_RES_22           (1<<22)         /* unused */
+#define IO_SSR_RES_21           (1<<21)         /* unused */
+#define IO_SSR_RES_20           (1<<20)         /* unused */
+#define IO_SSR_RES_19           (1<<19)         /* unused */
+
+                                                /* Maxine */
+#define IO_SSR_AB_TX_DMA_EN     (1<<29)         /* ACCESS.bus xmit DMA enable */
+#define IO_SSR_AB_RX_DMA_EN     (1<<28)         /* ACCESS.bus recv DMA enable */
+#define IO_SSR_FLOPPY_DMA_DIR   (1<<22)         /* Floppy DMA direction */
+#define IO_SSR_FLOPPY_DMA_EN    (1<<21)         /* Floppy DMA enable */
+#define IO_SSR_ISDN_TX_DMA_EN   (1<<20)         /* ISDN transmit DMA enable */
+#define IO_SSR_ISDN_RX_DMA_EN   (1<<19)         /* ISDN receive DMA enable */
+
+/*
+ * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
+ * defined here.  The rest is defined in system-specific headers.
+ */
+#define KN0X_IO_SSR_DIAGDN      (1<<15)         /* diagnostic jumper */
+#define KN0X_IO_SSR_SCC_RST     (1<<11)         /* ~SCC0,1 (Z85C30) reset */
+#define KN0X_IO_SSR_RTC_RST     (1<<10)         /* ~RTC (DS1287) reset */
+#define KN0X_IO_SSR_ASC_RST     (1<<9)          /* ~ASC (NCR53C94) reset */
+#define KN0X_IO_SSR_LANCE_RST   (1<<8)          /* ~LANCE (Am7990) reset */
+
+#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h
new file mode 100644
index 000000000000..9aaa9869615f
--- /dev/null
+++ b/include/asm-mips/dec/ioasic_ints.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the interrupt related bits in the I/O ASIC
+ * interrupt status register (and the interrupt mask register, of course)
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_IOASIC_INTS_H
+#define __ASM_DEC_IOASIC_INTS_H
+
+/*
+ * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
+ * and thus are common to all I/O ASIC machines.  The exception is
+ * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
+ * unused) and has a different SCC wiring.
+ */
+                                        /* all systems */
+#define IO_INR_SCC0A_TXDMA      31      /* SCC0A transmit page end */
+#define IO_INR_SCC0A_TXERR      30      /* SCC0A transmit memory read error */
+#define IO_INR_SCC0A_RXDMA      29      /* SCC0A receive half page */
+#define IO_INR_SCC0A_RXERR      28      /* SCC0A receive overrun */
+#define IO_INR_ASC_DMA          19      /* ASC buffer pointer loaded */
+#define IO_INR_ASC_ERR          18      /* ASC page overrun */
+#define IO_INR_ASC_MERR         17      /* ASC memory read error */
+#define IO_INR_LANCE_MERR       16      /* LANCE memory read error */
+
+                                        /* except Maxine */
+#define IO_INR_SCC1A_TXDMA      27      /* SCC1A transmit page end */
+#define IO_INR_SCC1A_TXERR      26      /* SCC1A transmit memory read error */
+#define IO_INR_SCC1A_RXDMA      25      /* SCC1A receive half page */
+#define IO_INR_SCC1A_RXERR      24      /* SCC1A receive overrun */
+#define IO_INR_RES_23           23      /* unused */
+#define IO_INR_RES_22           22      /* unused */
+#define IO_INR_RES_21           21      /* unused */
+#define IO_INR_RES_20           20      /* unused */
+
+                                        /* Maxine */
+#define IO_INR_AB_TXDMA         27      /* ACCESS.bus transmit page end */
+#define IO_INR_AB_TXERR         26      /* ACCESS.bus xmit memory read error */
+#define IO_INR_AB_RXDMA         25      /* ACCESS.bus receive half page */
+#define IO_INR_AB_RXERR         24      /* ACCESS.bus receive overrun */
+#define IO_INR_FLOPPY_ERR       23      /* FDC error */
+#define IO_INR_ISDN_TXDMA       22      /* ISDN xmit buffer pointer loaded */
+#define IO_INR_ISDN_RXDMA       21      /* ISDN recv buffer pointer loaded */
+#define IO_INR_ISDN_ERR         20      /* ISDN memory read/overrun error */
+
+#define IO_INR_DMA              16      /* first DMA IRQ */
+
+/*
+ * The lower 16 bits are system-specific and thus defined in
+ * system-specific headers.
+ */
+
+
+#define IO_IRQ_BASE             8       /* first IRQ assigned to I/O ASIC */
+#define IO_IRQ_LINES            32      /* number of I/O ASIC interrupts */
+
+#define IO_IRQ_NR(n)            ((n) + IO_IRQ_BASE)
+#define IO_IRQ_MASK(n)          (1 << (n))
+#define IO_IRQ_ALL              0x0000ffff
+#define IO_IRQ_DMA              0xffff0000
+
+#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
new file mode 100644
index 000000000000..946943502f83
--- /dev/null
+++ b/include/asm-mips/dec/kn01.h
@@ -0,0 +1,83 @@
+/*
+ * Hardware info about DECstation DS2100/3100 systems (otherwise known as
+ * pmin/pmax or KN01).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN01_H
+#define __ASM_MIPS_DEC_KN01_H
+
+#include <asm/addrspace.h>
+
+#define KN01_SLOT_BASE  KSEG1ADDR(0x10000000)
+#define KN01_SLOT_SIZE  0x01000000
+
+/*
+ * Address ranges for devices.
+ */
+#define KN01_PMASK      (0*KN01_SLOT_SIZE)      /* color plane mask */
+#define KN01_PCC        (1*KN01_SLOT_SIZE)      /* PCC (DC503) cursor */
+#define KN01_VDAC       (2*KN01_SLOT_SIZE)      /* color map */
+#define KN01_RES_3      (3*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_4      (4*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_5      (5*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_6      (6*KN01_SLOT_SIZE)      /* unused */
+#define KN01_ERRADDR    (7*KN01_SLOT_SIZE)      /* write error address */
+#define KN01_LANCE      (8*KN01_SLOT_SIZE)      /* LANCE (Am7990) Ethernet */
+#define KN01_LANCE_MEM  (9*KN01_SLOT_SIZE)      /* LANCE buffer memory */
+#define KN01_SII        (10*KN01_SLOT_SIZE)     /* SII (DC7061) SCSI */
+#define KN01_SII_MEM    (11*KN01_SLOT_SIZE)     /* SII buffer memory */
+#define KN01_DZ11       (12*KN01_SLOT_SIZE)     /* DZ11 (DC7085) serial */
+#define KN01_RTC        (13*KN01_SLOT_SIZE)     /* DS1287 RTC (bytes #0) */
+#define KN01_ESAR       (13*KN01_SLOT_SIZE)     /* MAC address (bytes #1) */
+#define KN01_CSR        (14*KN01_SLOT_SIZE)     /* system ctrl & status reg */
+#define KN01_SYS_ROM    (15*KN01_SLOT_SIZE)     /* system board ROM */
+
+
+/*
+ * Some port addresses...
+ */
+#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE)   /* 0xB8000000 */
+#define KN01_DZ11_BASE  (KN01_SLOT_BASE + KN01_DZ11)    /* 0xBC000000 */
+#define KN01_RTC_BASE   (KN01_SLOT_BASE + KN01_RTC)     /* 0xBD000000 */
+
+
+/*
+ * Frame buffer memory address.
+ */
+#define KN01_VFB_MEM    KSEG1ADDR(0x0fc00000)
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN01_CPU_INR_BUS        6       /* memory, I/O bus read/write errors */
+#define KN01_CPU_INR_VIDEO      6       /* PCC area detect #2 */
+#define KN01_CPU_INR_RTC        5       /* DS1287 RTC */
+#define KN01_CPU_INR_DZ11       4       /* DZ11 (DC7085) serial */
+#define KN01_CPU_INR_LANCE      3       /* LANCE (Am7990) Ethernet */
+#define KN01_CPU_INR_SII        2       /* SII (DC7061) SCSI */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN01_CSR_MNFMOD         (1<<15) /* MNFMOD manufacturing jumper */
+#define KN01_CSR_STATUS         (1<<14) /* self-test result status output */
+#define KN01_CSR_PARDIS         (1<<13) /* parity error disable */
+#define KN01_CSR_CRSRTST        (1<<12) /* PCC test output */
+#define KN01_CSR_MONO           (1<<11) /* mono/color fb SIMM installed */
+#define KN01_CSR_MEMERR         (1<<10) /* write timeout error status & ack*/
+#define KN01_CSR_VINT           (1<<9)  /* PCC area detect #2 status & ack */
+#define KN01_CSR_TXDIS          (1<<8)  /* DZ11 transmit disable */
+#define KN01_CSR_VBGTRG         (1<<2)  /* blue DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRG         (1<<1)  /* red DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
+#define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
+
+#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
new file mode 100644
index 000000000000..f797f7045920
--- /dev/null
+++ b/include/asm-mips/dec/kn02.h
@@ -0,0 +1,106 @@
+/*
+ * Hardware info about DECstation 5000/200 systems (otherwise known as
+ * 3max or KN02).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN02_H
+#define __ASM_MIPS_DEC_KN02_H
+
+#ifndef __ASSEMBLY__
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#endif
+
+#include <asm/addrspace.h>
+#include <asm/dec/ecc.h>
+
+
+#define KN02_SLOT_BASE  KSEG1ADDR(0x1fc00000)
+#define KN02_SLOT_SIZE  0x00080000
+
+/*
+ * Address ranges decoded by the "system slot" logic for onboard devices.
+ */
+#define KN02_SYS_ROM    (0*KN02_SLOT_SIZE)      /* system board ROM */
+#define KN02_RES_1      (1*KN02_SLOT_SIZE)      /* unused */
+#define KN02_CHKSYN     (2*KN02_SLOT_SIZE)      /* ECC syndrome */
+#define KN02_ERRADDR    (3*KN02_SLOT_SIZE)      /* bus error address */
+#define KN02_DZ11       (4*KN02_SLOT_SIZE)      /* DZ11 (DC7085) serial */
+#define KN02_RTC        (5*KN02_SLOT_SIZE)      /* DS1287 RTC */
+#define KN02_CSR        (6*KN02_SLOT_SIZE)      /* system ctrl & status reg */
+#define KN02_SYS_ROM_7  (7*KN02_SLOT_SIZE)      /* system board ROM (alias) */
+
+
+/*
+ * Some port addresses...
+ */
+#define KN02_DZ11_BASE  (KN02_SLOT_BASE + KN02_DZ11)    /* DZ11 */
+#define KN02_RTC_BASE   (KN02_SLOT_BASE + KN02_RTC)     /* RTC */
+#define KN02_CSR_BASE   (KN02_SLOT_BASE + KN02_CSR)     /* CSR */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN02_CSR_RES_28         (0xf<<28)       /* unused */
+#define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
+#define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
+#define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
+#define KN03_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN03_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN02_CSR_LEDIAG         (1<<12)         /* ECC diagn. latch strobe */
+#define KN02_CSR_TXDIS          (1<<11)         /* DZ11 transmit disable */
+#define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
+#define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
+#define KN03_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN03_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02_CPU_INR_RES_6      6       /* unused */
+#define KN02_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN02_CPU_INR_RES_4      4       /* unused */
+#define KN02_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN02_CPU_INR_CASCADE    2       /* CSR cascade */
+
+/*
+ * CSR interrupt bits.
+ */
+#define KN02_CSR_INR_DZ11       7       /* DZ11 (DC7085) serial */
+#define KN02_CSR_INR_LANCE      6       /* LANCE (Am7990) Ethernet */
+#define KN02_CSR_INR_ASC        5       /* ASC (NCR53C94) SCSI */
+#define KN02_CSR_INR_RES_4      4       /* unused */
+#define KN02_CSR_INR_RES_3      3       /* unused */
+#define KN02_CSR_INR_TC2        2       /* TURBOchannel slot #2 */
+#define KN02_CSR_INR_TC1        1       /* TURBOchannel slot #1 */
+#define KN02_CSR_INR_TC0        0       /* TURBOchannel slot #0 */
+
+
+#define KN02_IRQ_BASE           8       /* first IRQ assigned to CSR */
+#define KN02_IRQ_LINES          8       /* number of CSR interrupts */
+
+#define KN02_IRQ_NR(n)          ((n) + KN02_IRQ_BASE)
+#define KN02_IRQ_MASK(n)        (1 << (n))
+#define KN02_IRQ_ALL            0xff
+
+
+#ifndef __ASSEMBLY__
+extern u32 cached_kn02_csr;
+extern spinlock_t kn02_lock;
+extern void init_kn02_irqs(int base);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/include/asm-mips/dec/kn02ba.h b/include/asm-mips/dec/kn02ba.h
new file mode 100644
index 000000000000..c957a4f1b32d
--- /dev/null
+++ b/include/asm-mips/dec/kn02ba.h
@@ -0,0 +1,67 @@
+/*
+ *      include/asm-mips/dec/kn02ba.h
+ *
+ *      DECstation 5000/1xx (3min or KN02-BA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN02BA_H
+#define __ASM_MIPS_DEC_KN02BA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02BA_CPU_INR_HALT     6       /* HALT button */
+#define KN02BA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02BA_CPU_INR_TC2      4       /* TURBOchannel slot #2 */
+#define KN02BA_CPU_INR_TC1      3       /* TURBOchannel slot #1 */
+#define KN02BA_CPU_INR_TC0      2       /* TURBOchannel slot #0 */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02BA_IO_INR_RES_15    15      /* unused */
+#define KN02BA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02BA_IO_INR_RES_13    13      /* unused */
+#define KN02BA_IO_INR_BUS       12      /* memory, I/O bus read/write errors */
+#define KN02BA_IO_INR_RES_11    11      /* unused */
+#define KN02BA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02BA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02BA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02BA_IO_INR_SCC1      7       /* SCC (Z85C30) serial #1 */
+#define KN02BA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02BA_IO_INR_RTC       5       /* DS1287 RTC */
+#define KN02BA_IO_INR_PSU       4       /* power supply unit warning */
+#define KN02BA_IO_INR_RES_3     3       /* unused */
+#define KN02BA_IO_INR_ASC_DATA  2       /* SCSI data ready (for PIO) */
+#define KN02BA_IO_INR_PBNC      1       /* ~HALT button debouncer */
+#define KN02BA_IO_INR_PBNO      0       /* HALT button debouncer */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02BA_MER_RES_27       (1<<27)         /* unused */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02BA_MSR_RES_17       (0x3ff<<17)     /* unused */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN02BA_IO_SSR_TXDIS1    (1<<14)         /* SCC1 transmit disable */
+#define KN02BA_IO_SSR_TXDIS0    (1<<13)         /* SCC0 transmit disable */
+#define KN02BA_IO_SSR_RES_12    (1<<12)         /* unused */
+
+#define KN02BA_IO_SSR_LEDS      (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/include/asm-mips/dec/kn02ca.h b/include/asm-mips/dec/kn02ca.h
new file mode 100644
index 000000000000..92c0fe256099
--- /dev/null
+++ b/include/asm-mips/dec/kn02ca.h
@@ -0,0 +1,79 @@
+/*
+ *      include/asm-mips/dec/kn02ca.h
+ *
+ *      Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN02CA_H
+#define __ASM_MIPS_DEC_KN02CA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02CA_CPU_INR_HALT     6       /* HALT from ACCESS.Bus */
+#define KN02CA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02CA_CPU_INR_BUS      4       /* memory, I/O bus read/write errors */
+#define KN02CA_CPU_INR_RTC      3       /* DS1287 RTC */
+#define KN02CA_CPU_INR_TIMER    2       /* ARC periodic timer */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02CA_IO_INR_FLOPPY    15      /* 82077 FDC */
+#define KN02CA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02CA_IO_INR_POWERON   13      /* (*) ACCESS.Bus/power-on reset */
+#define KN02CA_IO_INR_TC0       12      /* TURBOchannel slot #0 */
+#define KN02CA_IO_INR_TIMER     12      /* ARC periodic timer (?) */
+#define KN02CA_IO_INR_ISDN      11      /* Am79C30A ISDN */
+#define KN02CA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02CA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02CA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02CA_IO_INR_HDFLOPPY  7       /* (*) HD (1.44MB) floppy status */
+#define KN02CA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02CA_IO_INR_TC1       5       /* TURBOchannel slot #1 */
+#define KN02CA_IO_INR_XDFLOPPY  4       /* (*) XD (2.88MB) floppy status */
+#define KN02CA_IO_INR_VIDEO     3       /* framebuffer */
+#define KN02CA_IO_INR_XVIDEO    2       /* ~framebuffer */
+#define KN02CA_IO_INR_AB_XMIT   1       /* ACCESS.bus transmit */
+#define KN02CA_IO_INR_AB_RECV   0       /* ACCESS.bus receive */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02CA_MER_INTR         (1<<27)         /* ARC IRQ status & ack */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02CA_MSR_INTREN       (1<<26)         /* ARC periodic IRQ enable */
+#define KN02CA_MSR_MS10EN       (1<<25)         /* 10/1ms IRQ period select */
+#define KN02CA_MSR_PFORCE       (0xf<<21)       /* byte lane error force */
+#define KN02CA_MSR_MABEN        (1<<20)         /* A side VFB address enable */
+#define KN02CA_MSR_LASTBANK     (0x7<<17)       /* onboard RAM bank # */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03CA_IO_SSR_RES_14    (1<<14)         /* unused */
+#define KN03CA_IO_SSR_RES_13    (1<<13)         /* unused */
+#define KN03CA_IO_SSR_ISDN_RST  (1<<12)         /* ~ISDN (Am79C30A) reset */
+
+#define KN03CA_IO_SSR_FLOPPY_RST (1<<7)         /* ~FDC (82077) reset */
+#define KN03CA_IO_SSR_VIDEO_RST (1<<6)          /* ~framebuffer reset */
+#define KN03CA_IO_SSR_AB_RST    (1<<5)          /* ACCESS.bus reset */
+#define KN03CA_IO_SSR_RES_4     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_3     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_2     (1<<2)          /* unused */
+#define KN03CA_IO_SSR_RES_1     (1<<1)          /* unused */
+#define KN03CA_IO_SSR_LED       (1<<0)          /* power LED */
+
+#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
new file mode 100644
index 000000000000..648c4dcbba1d
--- /dev/null
+++ b/include/asm-mips/dec/kn02xa.h
@@ -0,0 +1,75 @@
+/*
+ * Hardware info common to DECstation 5000/1xx systems (otherwise
+ * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
+ * (otherwise known as maxine or kn02ca).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ *
+ * These are addresses which have to be known early in the boot process.
+ * For other addresses refer to tc.h, ioasic_addrs.h and friends.
+ */
+#ifndef __ASM_MIPS_DEC_KN02XA_H
+#define __ASM_MIPS_DEC_KN02XA_H
+
+#include <asm/addrspace.h>
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN02XA_SLOT_BASE        KSEG1ADDR(0x1c000000)
+
+/*
+ * Some port addresses...
+ */
+#define KN02XA_IOASIC_BASE    (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
+#define KN02XA_RTC_BASE         (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
+
+
+/*
+ * Memory control ASIC registers.
+ */
+#define KN02XA_MER      KSEG1ADDR(0x0c400000)   /* memory error register */
+#define KN02XA_MSR      KSEG1ADDR(0x0c800000)   /* memory size register */
+
+/*
+ * CPU control ASIC registers.
+ */
+#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000)   /* write timeout config */
+#define KN02XA_EAR      KSEG1ADDR(0x0e000004)   /* error address register */
+#define KN02XA_BOOT0    KSEG1ADDR(0x0e000008)   /* boot 0 register */
+#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c)   /* write err IRQ stat & ack */
+
+/*
+ * Memory Error Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MER_RES_28       (0xf<<28)       /* unused */
+#define KN02XA_MER_RES_17       (0x3ff<<17)     /* unused */
+#define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
+#define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
+#define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
+#define KN02XA_MER_RES_12       (0x3<<12)       /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask */
+#define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
+
+/*
+ * Memory Size Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MSR_RES_27       (0x1f<<27)      /* unused */
+#define KN02XA_MSR_RES_14       (0x7<<14)       /* unused */
+#define KN02XA_MSR_SIZE         (1<<13)         /* 16M/4M stride */
+#define KN02XA_MSR_RES_0        (0x1fff<<0)     /* unused */
+
+/*
+ * Error Address Register bits.
+ */
+#define KN02XA_EAR_RES_29       (0x7<<29)       /* unused */
+#define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
+#define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
+
+#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
new file mode 100644
index 000000000000..676abd17c6a4
--- /dev/null
+++ b/include/asm-mips/dec/kn03.h
@@ -0,0 +1,83 @@
+/*
+ * Hardware info about DECstation 5000/2x0 systems (otherwise known as
+ * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
+ * differ mechanically but are otherwise identical (both are known as
+ * KN03).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN03_H
+#define __ASM_MIPS_DEC_KN03_H
+
+#include <asm/addrspace.h>
+#include <asm/dec/ecc.h>
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN03_SLOT_BASE  KSEG1ADDR(0x1f800000)
+
+/*
+ * Some port addresses...
+ */
+#define KN03_IOASIC_BASE        (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
+#define KN03_RTC_BASE           (KN03_SLOT_BASE + IOASIC_TOY)   /* RTC */
+#define KN03_MCR_BASE           (KN03_SLOT_BASE + IOASIC_MCR)   /* MCR */
+
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN03_CPU_INR_HALT       6       /* HALT button */
+#define KN03_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN03_CPU_INR_RES_4      4       /* unused */
+#define KN03_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN03_CPU_INR_CASCADE    2       /* I/O ASIC cascade */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN03_IO_INR_3MAXP       15      /* (*) 3max+/bigmax ID */
+#define KN03_IO_INR_NVRAM       14      /* (*) NVRAM clear jumper */
+#define KN03_IO_INR_TC2         13      /* TURBOchannel slot #2 */
+#define KN03_IO_INR_TC1         12      /* TURBOchannel slot #1 */
+#define KN03_IO_INR_TC0         11      /* TURBOchannel slot #0 */
+#define KN03_IO_INR_NRMOD       10      /* (*) NRMOD manufacturing jumper */
+#define KN03_IO_INR_ASC         9       /* ASC (NCR53C94) SCSI */
+#define KN03_IO_INR_LANCE       8       /* LANCE (Am7990) Ethernet */
+#define KN03_IO_INR_SCC1        7       /* SCC (Z85C30) serial #1 */
+#define KN03_IO_INR_SCC0        6       /* SCC (Z85C30) serial #0 */
+#define KN03_IO_INR_RTC         5       /* DS1287 RTC */
+#define KN03_IO_INR_PSU         4       /* power supply unit warning */
+#define KN03_IO_INR_RES_3       3       /* unused */
+#define KN03_IO_INR_ASC_DATA    2       /* SCSI data ready (for PIO) */
+#define KN03_IO_INR_PBNC        1       /* ~HALT button debouncer */
+#define KN03_IO_INR_PBNO        0       /* HALT button debouncer */
+
+
+/*
+ * Memory Control Register bits.
+ */
+#define KN03_MCR_RES_16         (0xffff<<16)    /* unused */
+#define KN03_MCR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN03_MCR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN03_MCR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN03_MCR_RES_11         (0x3<<12)       /* unused */
+#define KN03_MCR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN03_MCR_RES_7          (0x7<<7)        /* unused */
+#define KN03_MCR_CHECK          (0x7f<<0)       /* diagnostic check bits */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03_IO_SSR_TXDIS1      (1<<14)         /* SCC1 transmit disable */
+#define KN03_IO_SSR_TXDIS0      (1<<13)         /* SCC0 transmit disable */
+#define KN03_IO_SSR_RES_12      (1<<12)         /* unused */
+
+#define KN03_IO_SSR_LEDS        (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
new file mode 100644
index 000000000000..b120362b8f13
--- /dev/null
+++ b/include/asm-mips/dec/kn05.h
@@ -0,0 +1,71 @@
+/*
+ *      include/asm-mips/dec/kn05.h
+ *
+ *      DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
+ *      definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      WARNING!  All this information is pure guesswork based on the
+ *      ROM.  It is provided here in hope it will give someone some
+ *      food for thought.  No documentation for the KN05 module has
+ *      been located so far.
+ */
+#ifndef __ASM_MIPS_DEC_KN05_H
+#define __ASM_MIPS_DEC_KN05_H
+
+#include <asm/dec/ioasic_addrs.h>
+
+/*
+ * The oncard MB (Memory Buffer) ASIC provides an additional address
+ * decoder.  Certain address ranges within the "high" 16 slots are
+ * passed to the I/O ASIC's decoder like with the KN03.  Others are
+ * handled locally.  "Low" slots are always passed.
+ */
+#define KN05_MB_ROM     (16*IOASIC_SLOT_SIZE)   /* KN05 card ROM */
+#define KN05_IOCTL      (17*IOASIC_SLOT_SIZE)   /* I/O ASIC */
+#define KN05_ESAR       (18*IOASIC_SLOT_SIZE)   /* LANCE MAC address chip */
+#define KN05_LANCE      (19*IOASIC_SLOT_SIZE)   /* LANCE Ethernet */
+#define KN05_MB_INT     (20*IOASIC_SLOT_SIZE)   /* MB interrupt register */
+#define KN05_MB_EA      (21*IOASIC_SLOT_SIZE)   /* MB error address? */
+#define KN05_MB_EC      (22*IOASIC_SLOT_SIZE)   /* MB error ??? */
+#define KN05_MB_CSR     (23*IOASIC_SLOT_SIZE)   /* MB control & status */
+#define KN05_RES_24     (24*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_RES_25     (25*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_RES_26     (26*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_RES_27     (27*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_SCSI       (28*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN05_RES_29     (29*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_RES_30     (30*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN05_RES_31     (31*IOASIC_SLOT_SIZE)   /* unused? */
+
+/*
+ * Bits for the MB interrupt register.
+ * The register appears read-only.
+ */
+#define KN05_MB_INT_TC          (1<<0)          /* TURBOchannel? */
+#define KN05_MB_INT_RTC         (1<<1)          /* RTC? */
+#define KN05_MB_INT_MT          (1<<3)          /* ??? */
+
+/*
+ * Bits for the MB control & status register.
+ * Set to 0x00bf8001 on my system by the ROM.
+ */
+#define KN05_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN05_MB_CSR_F           (1<<1)          /* ??? */
+#define KN05_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN05_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN05_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN05_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN05_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN05_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN05_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN05_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN05_MB_CSR_FW          (1<<21)         /* ??? */
+
+#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/kn230.h b/include/asm-mips/dec/kn230.h
new file mode 100644
index 000000000000..ff1bf17de8d8
--- /dev/null
+++ b/include/asm-mips/dec/kn230.h
@@ -0,0 +1,26 @@
+/*
+ *      include/asm-mips/dec/kn230.h
+ *
+ *      DECsystem 5100 (MIPSmate or KN230) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN230_H
+#define __ASM_MIPS_DEC_KN230_H
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN230_CPU_INR_HALT      6       /* HALT button */
+#define KN230_CPU_INR_BUS       5       /* memory, I/O bus read/write errors */
+#define KN230_CPU_INR_RTC       4       /* DS1287 RTC */
+#define KN230_CPU_INR_SII       3       /* SII (DC7061) SCSI */
+#define KN230_CPU_INR_LANCE     3       /* LANCE (Am7990) Ethernet */
+#define KN230_CPU_INR_DZ11      2       /* DZ11 (DC7085) serial */
+
+#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/include/asm-mips/dec/machtype.h b/include/asm-mips/dec/machtype.h
new file mode 100644
index 000000000000..a6ecdebc430a
--- /dev/null
+++ b/include/asm-mips/dec/machtype.h
@@ -0,0 +1,27 @@
+/*
+ * Various machine type macros
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998, 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_DEC_MACHTYPE_H
+#define __ASM_DEC_MACHTYPE_H
+
+#include <asm/bootinfo.h>
+
+#define TURBOCHANNEL    (mips_machtype == MACH_DS5000_200 || \
+                         mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#define IOASIC          (mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#endif
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
new file mode 100644
index 000000000000..b63e2f2317d1
--- /dev/null
+++ b/include/asm-mips/dec/prom.h
@@ -0,0 +1,173 @@
+/*
+ *      include/asm-mips/dec/prom.h
+ *
+ *      DECstation PROM interface.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on arch/mips/dec/prom/prom.h by the Anonymous.
+ */
+#ifndef _ASM_DEC_PROM_H
+#define _ASM_DEC_PROM_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+/*
+ * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
+ * Many of these will work for MIPSen as well!
+ */
+#define VEC_RESET               (u64 *)KSEG1ADDR(0x1fc00000)
+                                                        /* Prom base address */
+
+#define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
+
+#define PMAX_PROM_HALT          PMAX_PROM_ENTRY(2)      /* valid on MIPSen */
+#define PMAX_PROM_AUTOBOOT      PMAX_PROM_ENTRY(5)      /* valid on MIPSen */
+#define PMAX_PROM_OPEN          PMAX_PROM_ENTRY(6)
+#define PMAX_PROM_READ          PMAX_PROM_ENTRY(7)
+#define PMAX_PROM_CLOSE         PMAX_PROM_ENTRY(10)
+#define PMAX_PROM_LSEEK         PMAX_PROM_ENTRY(11)
+#define PMAX_PROM_GETCHAR       PMAX_PROM_ENTRY(12)
+#define PMAX_PROM_PUTCHAR       PMAX_PROM_ENTRY(13)     /* 12 on MIPSen */
+#define PMAX_PROM_GETS          PMAX_PROM_ENTRY(15)
+#define PMAX_PROM_PRINTF        PMAX_PROM_ENTRY(17)
+#define PMAX_PROM_GETENV        PMAX_PROM_ENTRY(33)     /* valid on MIPSen */
+
+
+/*
+ * Magic number indicating REX PROM available on DECstation.  Found in
+ * register a2 on transfer of control to program from PROM.
+ */
+#define REX_PROM_MAGIC          0x30464354
+
+#ifdef CONFIG_MIPS64
+
+#define prom_is_rex(magic)      1       /* KN04 and KN05 are REX PROMs.  */
+
+#else /* !CONFIG_MIPS64 */
+
+#define prom_is_rex(magic)      ((magic) == REX_PROM_MAGIC)
+
+#endif /* !CONFIG_MIPS64 */
+
+
+/*
+ * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
+ * DS5000/2x0.
+ */
+#define REX_PROM_GETBITMAP      0x84/4  /* get mem bitmap */
+#define REX_PROM_GETCHAR        0x24/4  /* getch() */
+#define REX_PROM_GETENV         0x64/4  /* get env. variable */
+#define REX_PROM_GETSYSID       0x80/4  /* get system id */
+#define REX_PROM_GETTCINFO      0xa4/4
+#define REX_PROM_PRINTF         0x30/4  /* printf() */
+#define REX_PROM_SLOTADDR       0x6c/4  /* slotaddr */
+#define REX_PROM_BOOTINIT       0x54/4  /* open() */
+#define REX_PROM_BOOTREAD       0x58/4  /* read() */
+#define REX_PROM_CLEARCACHE     0x7c/4
+
+
+/*
+ * Used by rex_getbitmap().
+ */
+typedef struct {
+        int pagesize;
+        unsigned char bitmap[0];
+} memmap;
+
+
+/*
+ * Function pointers as read from a PROM's callback vector.
+ */
+extern int (*__rex_bootinit)(void);
+extern int (*__rex_bootread)(void);
+extern int (*__rex_getbitmap)(memmap *);
+extern unsigned long *(*__rex_slot_address)(int);
+extern void *(*__rex_gettcinfo)(void);
+extern int (*__rex_getsysid)(void);
+extern void (*__rex_clear_cache)(void);
+
+extern int (*__prom_getchar)(void);
+extern char *(*__prom_getenv)(char *);
+extern int (*__prom_printf)(char *, ...);
+
+extern int (*__pmax_open)(char*, int);
+extern int (*__pmax_lseek)(int, long, int);
+extern int (*__pmax_read)(int, void *, int);
+extern int (*__pmax_close)(int);
+
+
+#ifdef CONFIG_MIPS64
+
+/*
+ * On MIPS64 we have to call PROM functions via a helper
+ * dispatcher to accomodate ABI incompatibilities.
+ */
+#define __DEC_PROM_O32 __attribute__((alias("call_o32")))
+
+int _rex_bootinit(int (*)(void)) __DEC_PROM_O32;
+int _rex_bootread(int (*)(void)) __DEC_PROM_O32;
+int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32;
+unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32;
+void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32;
+int _rex_getsysid(int (*)(void)) __DEC_PROM_O32;
+void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32;
+
+int _prom_getchar(int (*)(void)) __DEC_PROM_O32;
+char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32;
+int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
+
+
+#define rex_bootinit()          _rex_bootinit(__rex_bootinit)
+#define rex_bootread()          _rex_bootread(__rex_bootread)
+#define rex_getbitmap(x)        _rex_getbitmap(__rex_getbitmap, x)
+#define rex_slot_address(x)     _rex_slot_address(__rex_slot_address, x)
+#define rex_gettcinfo()         _rex_gettcinfo(__rex_gettcinfo)
+#define rex_getsysid()          _rex_getsysid(__rex_getsysid)
+#define rex_clear_cache()       _rex_clear_cache(__rex_clear_cache)
+
+#define prom_getchar()          _prom_getchar(__prom_getchar)
+#define prom_getenv(x)          _prom_getenv(__prom_getenv, x)
+#define prom_printf(x...)       _prom_printf(__prom_printf, x)
+
+#else /* !CONFIG_MIPS64 */
+
+/*
+ * On plain MIPS we just call PROM functions directly.
+ */
+#define rex_bootinit            __rex_bootinit
+#define rex_bootread            __rex_bootread
+#define rex_getbitmap           __rex_getbitmap
+#define rex_slot_address        __rex_slot_address
+#define rex_gettcinfo           __rex_gettcinfo
+#define rex_getsysid            __rex_getsysid
+#define rex_clear_cache         __rex_clear_cache
+
+#define prom_getchar            __prom_getchar
+#define prom_getenv             __prom_getenv
+#define prom_printf             __prom_printf
+
+#define pmax_open               __pmax_open
+#define pmax_lseek              __pmax_lseek
+#define pmax_read               __pmax_read
+#define pmax_close              __pmax_close
+
+#endif /* !CONFIG_MIPS64 */
+
+
+extern void prom_meminit(u32);
+extern void prom_identify_arch(u32);
+extern void prom_init_cmdline(s32, s32 *, u32);
+
+extern void register_prom_console(void);
+extern void unregister_prom_console(void);
+
+#endif /* _ASM_DEC_PROM_H */
diff --git a/include/asm-mips/dec/serial.h b/include/asm-mips/dec/serial.h
new file mode 100644
index 000000000000..acad75890a05
--- /dev/null
+++ b/include/asm-mips/dec/serial.h
@@ -0,0 +1,36 @@
+/*
+ *      include/asm-mips/dec/serial.h
+ *
+ *      Definitions common to all DECstation serial devices.
+ *
+ *      Copyright (C) 2004  Maciej W. Rozycki
+ *
+ *      Based on bits extracted from drivers/tc/zs.h for which
+ *      the following copyrights apply:
+ *
+ *      Copyright (C) 1995  David S. Miller (davem@caip.rutgers.edu)
+ *      Copyright (C) 1996  Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
+ *      Copyright (C)       Harald Koerfgen
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_SERIAL_H
+#define __ASM_MIPS_DEC_SERIAL_H
+
+struct dec_serial_hook {
+        int (*init_channel)(void *handle);
+        void (*init_info)(void *handle);
+        void (*rx_char)(unsigned char ch, unsigned char fl);
+        int (*poll_rx_char)(void *handle);
+        int (*poll_tx_char)(void *handle, unsigned char ch);
+        unsigned int cflags;
+};
+
+extern int register_dec_serial_hook(unsigned int channel,
+                                    struct dec_serial_hook *hook);
+extern int unregister_dec_serial_hook(unsigned int channel);
+
+#endif /* __ASM_MIPS_DEC_SERIAL_H */
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h
new file mode 100644
index 000000000000..d7bba43f863a
--- /dev/null
+++ b/include/asm-mips/dec/tc.h
@@ -0,0 +1,43 @@
+/*
+ * Interface to the TURBOchannel related routines
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+#ifndef ASM_TC_H
+#define ASM_TC_H
+
+extern unsigned long system_base;
+
+/*
+ * Search for a TURBOchannel Option Module
+ * with a certain name. Returns slot number
+ * of the first card not in use or -ENODEV
+ * if none found.
+ */
+extern int search_tc_card(const char *);
+/*
+ * Marks the card in slot as used
+ */
+extern void claim_tc_card(int);
+/*
+ * Marks the card in slot as free
+ */
+extern void release_tc_card(int);
+/*
+ * Return base address of card in slot
+ */
+extern unsigned long get_tc_base_addr(int);
+/*
+ * Return interrupt number of slot
+ */
+extern unsigned long get_tc_irq_nr(int);
+/*
+ * Return TURBOchannel clock frequency in hz
+ */
+extern unsigned long get_tc_speed(void);
+
+#endif
diff --git a/include/asm-mips/dec/tcinfo.h b/include/asm-mips/dec/tcinfo.h
new file mode 100644
index 000000000000..cc23509ee77a
--- /dev/null
+++ b/include/asm-mips/dec/tcinfo.h
@@ -0,0 +1,47 @@
+/*
+ * Various TURBOchannel related stuff
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Information obtained through the get_tcinfo prom call
+ * created from:
+ *
+ * TURBOchannel Firmware Specification
+ *
+ * EK-TCAAD-FS-004
+ * from Digital Equipment Corporation
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+
+typedef struct {
+        int revision;
+        int clk_period;
+        int slot_size;
+        int io_timeout;
+        int dma_range;
+        int max_dma_burst;
+        int parity;
+        int reserved[4];
+} tcinfo;
+
+#define MAX_SLOT 7
+
+typedef struct {
+        unsigned long base_addr;
+        unsigned char name[9];
+        unsigned char vendor[9];
+        unsigned char firmware[9];
+        int interrupt;
+        int flags;
+} slot_info;
+
+/*
+ * Values for flags
+ */
+#define FREE    1<<0
+#define IN_USE  1<<1
+
+
diff --git a/include/asm-mips/dec/tcmodule.h b/include/asm-mips/dec/tcmodule.h
new file mode 100644
index 000000000000..6268e8915d87
--- /dev/null
+++ b/include/asm-mips/dec/tcmodule.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Offsets for the ROM header locations for
+ * TURBOchannel cards
+ *
+ * created from:
+ *
+ * TURBOchannel Firmware Specification
+ *
+ * EK-TCAAD-FS-004
+ * from Digital Equipment Corporation
+ *
+ * Jan.1998 Harald Koerfgen
+ */
+#ifndef __ASM_DEC_TCMODULE_H
+#define __ASM_DEC_TCMODULE_H
+
+#define OLDCARD 0x3c0000
+#define NEWCARD 0x000000
+
+#define TC_ROM_WIDTH    0x3e0
+#define TC_ROM_STRIDE   0x3e4
+#define TC_ROM_SIZE     0x3e8
+#define TC_SLOT_SIZE    0x3ec
+#define TC_PATTERN0     0x3f0
+#define TC_PATTERN1     0x3f4
+#define TC_PATTERN2     0x3f8
+#define TC_PATTERN3     0x3fc
+#define TC_FIRM_VER     0x400
+#define TC_VENDOR       0x420
+#define TC_MODULE       0x440
+#define TC_FIRM_TYPE    0x460
+#define TC_FLAGS        0x470
+#define TC_ROM_OBJECTS  0x480
+
+#endif /* __ASM_DEC_TCMODULE_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
new file mode 100644
index 000000000000..d0f68447e5a7
--- /dev/null
+++ b/include/asm-mips/delay.h
@@ -0,0 +1,93 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf Electronics
+ * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_DELAY_H
+#define _ASM_DELAY_H
+
+#include <linux/config.h>
+#include <linux/param.h>
+
+#include <asm/compiler.h>
+
+extern unsigned long loops_per_jiffy;
+
+static inline void __delay(unsigned long loops)
+{
+        if (sizeof(long) == 4)
+                __asm__ __volatile__ (
+                ".set\tnoreorder\n"
+                "1:\tbnez\t%0,1b\n\t"
+                "subu\t%0,1\n\t"
+                ".set\treorder"
+                : "=r" (loops)
+                : "0" (loops));
+        else if (sizeof(long) == 8)
+                __asm__ __volatile__ (
+                ".set\tnoreorder\n"
+                "1:\tbnez\t%0,1b\n\t"
+                "dsubu\t%0,1\n\t"
+                ".set\treorder"
+                :"=r" (loops)
+                :"0" (loops));
+}
+
+
+/*
+ * Division by multiplication: you don't have to worry about
+ * loss of precision.
+ *
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+        unsigned long lo;
+
+        /*
+         * The common rates of 1000 and 128 are rounded wrongly by the
+         * catchall case for 64-bit.  Excessive precission?  Probably ...
+         */
+#if defined(CONFIG_MIPS64) && (HZ == 128)
+        usecs *= 0x0008637bd05af6c7UL;          /* 2**64 / (1000000 / HZ) */
+#elif defined(CONFIG_MIPS64) && (HZ == 1000)
+        usecs *= 0x004189374BC6A7f0UL;          /* 2**64 / (1000000 / HZ) */
+#elif defined(CONFIG_MIPS64)
+        usecs *= (0x8000000000000000UL / (500000 / HZ));
+#else /* 32-bit junk follows here */
+        usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
+                                   0x80000000ULL) >> 32);
+#endif
+
+        if (sizeof(long) == 4)
+                __asm__("multu\t%2, %3"
+                : "=h" (usecs), "=l" (lo)
+                : "r" (usecs), "r" (lpj)
+                : GCC_REG_ACCUM);
+        else if (sizeof(long) == 8)
+                __asm__("dmultu\t%2, %3"
+                : "=h" (usecs), "=l" (lo)
+                : "r" (usecs), "r" (lpj)
+                : GCC_REG_ACCUM);
+
+        __delay(usecs);
+}
+
+#ifdef CONFIG_SMP
+#define __udelay_val cpu_data[smp_processor_id()].udelay_val
+#else
+#define __udelay_val loops_per_jiffy
+#endif
+
+#define udelay(usecs) __udelay((usecs),__udelay_val)
+
+#endif /* _ASM_DELAY_H */
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
new file mode 100644
index 000000000000..5f7dcf5452e7
--- /dev/null
+++ b/include/asm-mips/div64.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2000, 2004  Maciej W. Rozycki
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_DIV64_H
+#define _ASM_DIV64_H
+
+#if (_MIPS_SZLONG == 32)
+
+#include <asm/compiler.h>
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define do_div64_32(res, high, low, base) ({ \
+        unsigned long __quot, __mod; \
+        unsigned long __cf, __tmp, __tmp2, __i; \
+        \
+        __asm__(".set   push\n\t" \
+                ".set   noat\n\t" \
+                ".set   noreorder\n\t" \
+                "move   %2, $0\n\t" \
+                "move   %3, $0\n\t" \
+                "b      1f\n\t" \
+                " li    %4, 0x21\n" \
+                "0:\n\t" \
+                "sll    $1, %0, 0x1\n\t" \
+                "srl    %3, %0, 0x1f\n\t" \
+                "or     %0, $1, %5\n\t" \
+                "sll    %1, %1, 0x1\n\t" \
+                "sll    %2, %2, 0x1\n" \
+                "1:\n\t" \
+                "bnez   %3, 2f\n\t" \
+                " sltu  %5, %0, %z6\n\t" \
+                "bnez   %5, 3f\n" \
+                "2:\n\t" \
+                " addiu %4, %4, -1\n\t" \
+                "subu   %0, %0, %z6\n\t" \
+                "addiu  %2, %2, 1\n" \
+                "3:\n\t" \
+                "bnez   %4, 0b\n\t" \
+                " srl   %5, %1, 0x1f\n\t" \
+                ".set   pop" \
+                : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \
+                  "=&r" (__i), "=&r" (__tmp2) \
+                : "Jr" (base), "0" (high), "1" (low)); \
+        \
+        (res) = __quot; \
+        __mod; })
+
+#define do_div(n, base) ({ \
+        unsigned long long __quot; \
+        unsigned long __mod; \
+        unsigned long long __div; \
+        unsigned long __upper, __low, __high, __base; \
+        \
+        __div = (n); \
+        __base = (base); \
+        \
+        __high = __div >> 32; \
+        __low = __div; \
+        __upper = __high; \
+        \
+        if (__high) \
+                __asm__("divu   $0, %z2, %z3" \
+                        : "=h" (__upper), "=l" (__high) \
+                        : "Jr" (__high), "Jr" (__base) \
+                        : GCC_REG_ACCUM); \
+        \
+        __mod = do_div64_32(__low, __upper, __low, __base); \
+        \
+        __quot = __high; \
+        __quot = __quot << 32 | __low; \
+        (n) = __quot; \
+        __mod; })
+#endif /* (_MIPS_SZLONG == 32) */
+
+#if (_MIPS_SZLONG == 64)
+
+/*
+ * Don't use this one in new code
+ */
+#define do_div64_32(res, high, low, base) ({ \
+        unsigned int __quot, __mod; \
+        unsigned long __div; \
+        unsigned int __low, __high, __base; \
+        \
+        __high = (high); \
+        __low = (low); \
+        __div = __high; \
+        __div = __div << 32 | __low; \
+        __base = (base); \
+        \
+        __mod = __div % __base; \
+        __div = __div / __base; \
+        \
+        __quot = __div; \
+        (res) = __quot; \
+        __mod; })
+
+/*
+ * Hey, we're already 64-bit, no
+ * need to play games..
+ */
+#define do_div(n, base) ({ \
+        unsigned long __quot; \
+        unsigned int __mod; \
+        unsigned long __div; \
+        unsigned int __base; \
+        \
+        __div = (n); \
+        __base = (base); \
+        \
+        __mod = __div % __base; \
+        __quot = __div / __base; \
+        \
+        (n) = __quot; \
+        __mod; })
+
+#endif /* (_MIPS_SZLONG == 64) */
+
+#endif /* _ASM_DIV64_H */
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
new file mode 100644
index 000000000000..af28dc88930b
--- /dev/null
+++ b/include/asm-mips/dma-mapping.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+
+#include <asm/scatterlist.h>
+#include <asm/cache.h>
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, int flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, int flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
+extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+        enum dma_data_direction direction);
+extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction);
+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+        enum dma_data_direction direction);
+extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction);
+extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+        size_t size, enum dma_data_direction direction);
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        int nhwentries, enum dma_data_direction direction);
+extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+        size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_range_for_cpu(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_single_range_for_device(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+extern int dma_mapping_error(dma_addr_t dma_addr);
+extern int dma_supported(struct device *dev, u64 mask);
+
+static inline int
+dma_set_mask(struct device *dev, u64 mask)
+{
+        if(!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+static inline int
+dma_get_cache_alignment(void)
+{
+        /* XXX Largest on any MIPS */
+        return 128;
+}
+
+extern int dma_is_consistent(dma_addr_t dma_addr);
+
+extern void dma_cache_sync(void *vaddr, size_t size,
+               enum dma_data_direction direction);
+
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+
+extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+        dma_addr_t device_addr, size_t size, int flags);
+extern void dma_release_declared_memory(struct device *dev);
+extern void * dma_mark_declared_memory_occupied(struct device *dev,
+        dma_addr_t device_addr, size_t size);
+
+#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
new file mode 100644
index 000000000000..6aaf9939a716
--- /dev/null
+++ b/include/asm-mips/dma.h
@@ -0,0 +1,313 @@
+/*
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ *
+ * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
+ * and can only be used for expansion cards. Onboard DMA controllers, such
+ * as the R4030 on Jazz boards behave totally different!
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <linux/config.h>
+#include <asm/io.h>                     /* need byte IO */
+#include <linux/spinlock.h>             /* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb        outb_p
+#else
+#define dma_outb        outb
+#endif
+
+#define dma_inb         inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+#define MAX_DMA_CHANNELS        8
+
+/*
+ * The maximum address in KSEG0 that we can perform a DMA transfer to on this
+ * platform.  This describes only the PC style part of the DMA logic like on
+ * Deskstations or Acer PICA but not the much more versatile DMA logic used
+ * for the local devices on Acer PICA or Magnums.
+ */
+#ifdef CONFIG_SGI_IP22
+/* Horrible hack to have a correct DMA window on IP22 */
+#include <asm/sgi/mc.h>
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
+#else
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
+#endif
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            0x08    /* command register (w) */
+#define DMA1_STAT_REG           0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG           0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            0xD0    /* command register (w) */
+#define DMA2_STAT_REG           0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG           0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_PAGE_0              0x87    /* DMA page registers */
+#define DMA_PAGE_1              0x83
+#define DMA_PAGE_2              0x81
+#define DMA_PAGE_3              0x82
+#define DMA_PAGE_5              0x8B
+#define DMA_PAGE_6              0x89
+#define DMA_PAGE_7              0x8A
+
+#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT    0x10
+
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr,  DMA1_MASK_REG);
+        else
+                dma_outb(dmanr & 3,  DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr | 4,  DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(0,  DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0,  DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr<=3)
+                dma_outb(mode | dmanr,  DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+        switch(dmanr) {
+                case 0:
+                        dma_outb(pagenr, DMA_PAGE_0);
+                        break;
+                case 1:
+                        dma_outb(pagenr, DMA_PAGE_1);
+                        break;
+                case 2:
+                        dma_outb(pagenr, DMA_PAGE_2);
+                        break;
+                case 3:
+                        dma_outb(pagenr, DMA_PAGE_3);
+                        break;
+                case 5:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
+                        break;
+                case 6:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
+                        break;
+                case 7:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
+                        break;
+        }
+}
+
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+        set_dma_page(dmanr, a>>16);
+        if (dmanr <= 3)  {
+            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+        }  else  {
+            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+        }
+}
+
+
+/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3)  {
+            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+        } else {
+            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr);       /* release it again */
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* _ASM_DMA_H */
diff --git a/include/asm-mips/ds1286.h b/include/asm-mips/ds1286.h
new file mode 100644
index 000000000000..6983b6ff0af3
--- /dev/null
+++ b/include/asm-mips/ds1286.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_DS1286_H
+#define _ASM_DS1286_H
+
+#include <ds1286.h>
+
+#endif /* _ASM_DS1286_H */
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
new file mode 100644
index 000000000000..7b92c8045cc2
--- /dev/null
+++ b/include/asm-mips/elf.h
@@ -0,0 +1,282 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_ELF_H
+#define _ASM_ELF_H
+
+#include <linux/config.h>
+
+/* ELF header e_flags defines. */
+/* MIPS architecture level. */
+#define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
+#define EF_MIPS_ARCH_2          0x10000000      /* -mips2 code.  */
+#define EF_MIPS_ARCH_3          0x20000000      /* -mips3 code.  */
+#define EF_MIPS_ARCH_4          0x30000000      /* -mips4 code.  */
+#define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
+#define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
+#define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
+
+/* The ABI of a file. */
+#define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
+#define EF_MIPS_ABI_O64         0x00002000      /* O32 extended for 64 bit.  */
+
+#define PT_MIPS_REGINFO         0x70000000
+#define PT_MIPS_RTPROC          0x70000001
+#define PT_MIPS_OPTIONS         0x70000002
+
+/* Flags in the e_flags field of the header */
+#define EF_MIPS_NOREORDER       0x00000001
+#define EF_MIPS_PIC             0x00000002
+#define EF_MIPS_CPIC            0x00000004
+#define EF_MIPS_ABI2            0x00000020
+#define EF_MIPS_OPTIONS_FIRST   0x00000080
+#define EF_MIPS_32BITMODE       0x00000100
+#define EF_MIPS_ABI             0x0000f000
+#define EF_MIPS_ARCH            0xf0000000
+
+#define DT_MIPS_RLD_VERSION     0x70000001
+#define DT_MIPS_TIME_STAMP      0x70000002
+#define DT_MIPS_ICHECKSUM       0x70000003
+#define DT_MIPS_IVERSION        0x70000004
+#define DT_MIPS_FLAGS           0x70000005
+        #define RHF_NONE        0x00000000
+        #define RHF_HARDWAY     0x00000001
+        #define RHF_NOTPOT      0x00000002
+        #define RHF_SGI_ONLY    0x00000010
+#define DT_MIPS_BASE_ADDRESS    0x70000006
+#define DT_MIPS_CONFLICT        0x70000008
+#define DT_MIPS_LIBLIST         0x70000009
+#define DT_MIPS_LOCAL_GOTNO     0x7000000a
+#define DT_MIPS_CONFLICTNO      0x7000000b
+#define DT_MIPS_LIBLISTNO       0x70000010
+#define DT_MIPS_SYMTABNO        0x70000011
+#define DT_MIPS_UNREFEXTNO      0x70000012
+#define DT_MIPS_GOTSYM          0x70000013
+#define DT_MIPS_HIPAGENO        0x70000014
+#define DT_MIPS_RLD_MAP         0x70000016
+
+#define R_MIPS_NONE             0
+#define R_MIPS_16               1
+#define R_MIPS_32               2
+#define R_MIPS_REL32            3
+#define R_MIPS_26               4
+#define R_MIPS_HI16             5
+#define R_MIPS_LO16             6
+#define R_MIPS_GPREL16          7
+#define R_MIPS_LITERAL          8
+#define R_MIPS_GOT16            9
+#define R_MIPS_PC16             10
+#define R_MIPS_CALL16           11
+#define R_MIPS_GPREL32          12
+/* The remaining relocs are defined on Irix, although they are not
+   in the MIPS ELF ABI.  */
+#define R_MIPS_UNUSED1          13
+#define R_MIPS_UNUSED2          14
+#define R_MIPS_UNUSED3          15
+#define R_MIPS_SHIFT5           16
+#define R_MIPS_SHIFT6           17
+#define R_MIPS_64               18
+#define R_MIPS_GOT_DISP         19
+#define R_MIPS_GOT_PAGE         20
+#define R_MIPS_GOT_OFST         21
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_GOTHI16          22
+#define R_MIPS_GOTLO16          23
+#define R_MIPS_SUB              24
+#define R_MIPS_INSERT_A         25
+#define R_MIPS_INSERT_B         26
+#define R_MIPS_DELETE           27
+#define R_MIPS_HIGHER           28
+#define R_MIPS_HIGHEST          29
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_CALLHI16         30
+#define R_MIPS_CALLLO16         31
+/*
+ * This range is reserved for vendor specific relocations.
+ */
+#define R_MIPS_LOVENDOR         100
+#define R_MIPS_HIVENDOR         127
+
+#define SHN_MIPS_ACCOMON        0xff00
+
+#define SHT_MIPS_LIST           0x70000000
+#define SHT_MIPS_CONFLICT       0x70000002
+#define SHT_MIPS_GPTAB          0x70000003
+#define SHT_MIPS_UCODE          0x70000004
+
+#define SHF_MIPS_GPREL  0x10000000
+
+#ifndef ELF_ARCH
+/* ELF register definitions */
+#define ELF_NGREG       45
+#define ELF_NFPREG      33
+
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+#ifdef CONFIG_MIPS32
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(hdr)                                             \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (__h->e_machine != EM_MIPS)                                  \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS32)                       \
+                __res = 0;                                              \
+        if ((__h->e_flags & EF_MIPS_ABI2) != 0)                         \
+                __res = 0;                                              \
+        if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
+            ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(hdr)                                             \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (__h->e_machine != EM_MIPS)                                  \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS64
+
+#endif /* CONFIG_MIPS64 */
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#ifdef __MIPSEB__
+#define ELF_DATA        ELFDATA2MSB
+#elif __MIPSEL__
+#define ELF_DATA        ELFDATA2LSB
+#endif
+#define ELF_ARCH        EM_MIPS
+
+#endif /* !defined(ELF_ARCH) */
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_MIPS32
+
+#define SET_PERSONALITY(ex, ibcs2)                      \
+do {                                                    \
+        if (ibcs2)                                      \
+                set_personality(PER_SVR4);              \
+        set_personality(PER_LINUX);                     \
+} while (0)
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+
+#define SET_PERSONALITY(ex, ibcs2)                              \
+do {    current->thread.mflags &= ~MF_ABI_MASK;                 \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32) {             \
+                if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&     \
+                     ((ex).e_flags & EF_MIPS_ABI) == 0)         \
+                        current->thread.mflags |= MF_N32;       \
+                else                                            \
+                        current->thread.mflags |= MF_O32;       \
+        } else                                                  \
+                current->thread.mflags |= MF_N64;               \
+        if (ibcs2)                                              \
+                set_personality(PER_SVR4);                      \
+        else if (current->personality != PER_LINUX32)           \
+                set_personality(PER_LINUX);                     \
+} while (0)
+
+#endif /* CONFIG_MIPS64 */
+
+extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
+extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
+
+#define ELF_CORE_COPY_REGS(elf_regs, regs)                      \
+        dump_regs((elf_greg_t *)&(elf_regs), regs);
+#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
+        dump_task_fpu(tsk, elf_fpregs)
+
+#endif /* __KERNEL__ */
+
+/* This one accepts IRIX binaries.  */
+#define irix_elf_check_arch(hdr)        ((hdr)->e_flags & RHF_SGI_ONLY)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This could be done in userspace,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (0)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM  (NULL)
+
+/*
+ * See comments in asm-alpha/elf.h, this is the same thing
+ * on the MIPS.
+ */
+#define ELF_PLAT_INIT(_r, load_addr)    do { \
+        _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0;      \
+        _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0;      \
+        _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0;   \
+        _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0;  \
+        _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0;  \
+        _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0;  \
+        _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0;  \
+        _r->regs[30] = _r->regs[31] = 0;                                \
+} while (0)
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#ifndef ELF_ET_DYN_BASE
+#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
+#endif
+
+#endif /* _ASM_ELF_H */
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
new file mode 100644
index 000000000000..2b458f9538cd
--- /dev/null
+++ b/include/asm-mips/errno.h
@@ -0,0 +1,127 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_ERRNO_H
+#define _ASM_ERRNO_H
+
+/*
+ * These error numbers are intended to be MIPS ABI compatible
+ */
+
+#include <asm-generic/errno-base.h>
+
+#define ENOMSG          35      /* No message of desired type */
+#define EIDRM           36      /* Identifier removed */
+#define ECHRNG          37      /* Channel number out of range */
+#define EL2NSYNC        38      /* Level 2 not synchronized */
+#define EL3HLT          39      /* Level 3 halted */
+#define EL3RST          40      /* Level 3 reset */
+#define ELNRNG          41      /* Link number out of range */
+#define EUNATCH         42      /* Protocol driver not attached */
+#define ENOCSI          43      /* No CSI structure available */
+#define EL2HLT          44      /* Level 2 halted */
+#define EDEADLK         45      /* Resource deadlock would occur */
+#define ENOLCK          46      /* No record locks available */
+#define EBADE           50      /* Invalid exchange */
+#define EBADR           51      /* Invalid request descriptor */
+#define EXFULL          52      /* Exchange full */
+#define ENOANO          53      /* No anode */
+#define EBADRQC         54      /* Invalid request code */
+#define EBADSLT         55      /* Invalid slot */
+#define EDEADLOCK       56      /* File locking deadlock error */
+#define EBFONT          59      /* Bad font file format */
+#define ENOSTR          60      /* Device not a stream */
+#define ENODATA         61      /* No data available */
+#define ETIME           62      /* Timer expired */
+#define ENOSR           63      /* Out of streams resources */
+#define ENONET          64      /* Machine is not on the network */
+#define ENOPKG          65      /* Package not installed */
+#define EREMOTE         66      /* Object is remote */
+#define ENOLINK         67      /* Link has been severed */
+#define EADV            68      /* Advertise error */
+#define ESRMNT          69      /* Srmount error */
+#define ECOMM           70      /* Communication error on send */
+#define EPROTO          71      /* Protocol error */
+#define EDOTDOT         73      /* RFS specific error */
+#define EMULTIHOP       74      /* Multihop attempted */
+#define EBADMSG         77      /* Not a data message */
+#define ENAMETOOLONG    78      /* File name too long */
+#define EOVERFLOW       79      /* Value too large for defined data type */
+#define ENOTUNIQ        80      /* Name not unique on network */
+#define EBADFD          81      /* File descriptor in bad state */
+#define EREMCHG         82      /* Remote address changed */
+#define ELIBACC         83      /* Can not access a needed shared library */
+#define ELIBBAD         84      /* Accessing a corrupted shared library */
+#define ELIBSCN         85      /* .lib section in a.out corrupted */
+#define ELIBMAX         86      /* Attempting to link in too many shared libraries */
+#define ELIBEXEC        87      /* Cannot exec a shared library directly */
+#define EILSEQ          88      /* Illegal byte sequence */
+#define ENOSYS          89      /* Function not implemented */
+#define ELOOP           90      /* Too many symbolic links encountered */
+#define ERESTART        91      /* Interrupted system call should be restarted */
+#define ESTRPIPE        92      /* Streams pipe error */
+#define ENOTEMPTY       93      /* Directory not empty */
+#define EUSERS          94      /* Too many users */
+#define ENOTSOCK        95      /* Socket operation on non-socket */
+#define EDESTADDRREQ    96      /* Destination address required */
+#define EMSGSIZE        97      /* Message too long */
+#define EPROTOTYPE      98      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     99      /* Protocol not available */
+#define EPROTONOSUPPORT 120     /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121     /* Socket type not supported */
+#define EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT    123     /* Protocol family not supported */
+#define EAFNOSUPPORT    124     /* Address family not supported by protocol */
+#define EADDRINUSE      125     /* Address already in use */
+#define EADDRNOTAVAIL   126     /* Cannot assign requested address */
+#define ENETDOWN        127     /* Network is down */
+#define ENETUNREACH     128     /* Network is unreachable */
+#define ENETRESET       129     /* Network dropped connection because of reset */
+#define ECONNABORTED    130     /* Software caused connection abort */
+#define ECONNRESET      131     /* Connection reset by peer */
+#define ENOBUFS         132     /* No buffer space available */
+#define EISCONN         133     /* Transport endpoint is already connected */
+#define ENOTCONN        134     /* Transport endpoint is not connected */
+#define EUCLEAN         135     /* Structure needs cleaning */
+#define ENOTNAM         137     /* Not a XENIX named type file */
+#define ENAVAIL         138     /* No XENIX semaphores available */
+#define EISNAM          139     /* Is a named type file */
+#define EREMOTEIO       140     /* Remote I/O error */
+#define EINIT           141     /* Reserved */
+#define EREMDEV         142     /* Error 142 */
+#define ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS    144     /* Too many references: cannot splice */
+#define ETIMEDOUT       145     /* Connection timed out */
+#define ECONNREFUSED    146     /* Connection refused */
+#define EHOSTDOWN       147     /* Host is down */
+#define EHOSTUNREACH    148     /* No route to host */
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EALREADY        149     /* Operation already in progress */
+#define EINPROGRESS     150     /* Operation now in progress */
+#define ESTALE          151     /* Stale NFS file handle */
+#define ECANCELED       158     /* AIO operation canceled */
+
+/*
+ * These error are Linux extensions.
+ */
+#define ENOMEDIUM       159     /* No medium found */
+#define EMEDIUMTYPE     160     /* Wrong medium type */
+#define ENOKEY          161     /* Required key not available */
+#define EKEYEXPIRED     162     /* Key has expired */
+#define EKEYREVOKED     163     /* Key has been revoked */
+#define EKEYREJECTED    164     /* Key was rejected by service */
+
+#define EDQUOT          1133    /* Quota exceeded */
+
+#ifdef __KERNEL__
+
+/* The biggest error number defined here or in <linux/errno.h>. */
+#define EMAXERRNO       1133
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_ERRNO_H */
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
new file mode 100644
index 000000000000..2436392e7990
--- /dev/null
+++ b/include/asm-mips/fcntl.h
@@ -0,0 +1,125 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle
+ */
+#ifndef _ASM_FCNTL_H
+#define _ASM_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_ACCMODE       0x0003
+#define O_RDONLY        0x0000
+#define O_WRONLY        0x0001
+#define O_RDWR          0x0002
+#define O_APPEND        0x0008
+#define O_SYNC          0x0010
+#define O_NONBLOCK      0x0080
+#define O_CREAT         0x0100  /* not fcntl */
+#define O_TRUNC         0x0200  /* not fcntl */
+#define O_EXCL          0x0400  /* not fcntl */
+#define O_NOCTTY        0x0800  /* not fcntl */
+#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
+#define O_LARGEFILE     0x2000  /* allow large file opens */
+#define O_DIRECT        0x8000  /* direct disk access hint */
+#define O_DIRECTORY     0x10000 /* must be a directory */
+#define O_NOFOLLOW      0x20000 /* don't follow links */
+#define O_NOATIME       0x40000
+
+#define O_NDELAY        O_NONBLOCK
+
+#define F_DUPFD         0       /* dup */
+#define F_GETFD         1       /* get close_on_exec */
+#define F_SETFD         2       /* set/clear close_on_exec */
+#define F_GETFL         3       /* get file->f_flags */
+#define F_SETFL         4       /* set file->f_flags */
+#define F_GETLK         14
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        24      /*  for sockets. */
+#define F_GETOWN        23      /*  for sockets. */
+#define F_SETSIG        10      /*  for sockets. */
+#define F_GETSIG        11      /*  for sockets. */
+
+#ifndef __mips64
+#define F_GETLK64       33      /*  using 'struct flock64' */
+#define F_SETLK64       34
+#define F_SETLKW64      35
+#endif
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         0
+#define F_WRLCK         1
+#define F_UNLCK         2
+
+/* for old implementation of bsd flock () */
+#define F_EXLCK         4       /* or 3 */
+#define F_SHLCK         8       /* or 4 */
+
+/* for leases */
+#define F_INPROGRESS    16
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH         1       /* shared lock */
+#define LOCK_EX         2       /* exclusive lock */
+#define LOCK_NB         4       /* or'd with one of the above to prevent
+                                   blocking */
+#define LOCK_UN         8       /* remove lock */
+
+#define LOCK_MAND       32      /* This is a mandatory flock */
+#define LOCK_READ       64      /* ... Which allows concurrent read operations */
+#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
+#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
+
+/*
+ * The flavours of struct flock.  "struct flock" is the ABI compliant
+ * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
+ * a historic accident and inconsistence with the ABI definition it doesn't
+ * contain all the same fields as struct flock.
+ */
+
+#ifndef __mips64
+
+typedef struct flock {
+        short   l_type;
+        short   l_whence;
+        __kernel_off_t l_start;
+        __kernel_off_t l_len;
+        long    l_sysid;
+        __kernel_pid_t l_pid;
+        long    pad[4];
+} flock_t;
+
+typedef struct flock64 {
+        short   l_type;
+        short   l_whence;
+        loff_t  l_start;
+        loff_t  l_len;
+        pid_t   l_pid;
+} flock64_t;
+
+#else /* 64-bit definitions */
+
+typedef struct flock {
+        short   l_type;
+        short   l_whence;
+        __kernel_off_t l_start;
+        __kernel_off_t l_len;
+        __kernel_pid_t l_pid;
+} flock_t;
+
+#ifdef __KERNEL__
+#define flock64         flock
+#endif
+
+#endif
+
+#define F_LINUX_SPECIFIC_BASE   1024
+
+#endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
new file mode 100644
index 000000000000..26b6a90a690b
--- /dev/null
+++ b/include/asm-mips/fixmap.h
@@ -0,0 +1,110 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/config.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the end of virtual memory (0xfffff000) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanizm,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap (enum fixed_addresses idx,
+                                        unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between vmalloc'ed areas and
+ * the start of the fixmap, and leave one page empty
+ * at the top of mem..
+ */
+#define FIXADDR_TOP     (0xffffe000UL)
+#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif
diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h
new file mode 100644
index 000000000000..aa1ef8b352cc
--- /dev/null
+++ b/include/asm-mips/floppy.h
@@ -0,0 +1,56 @@
+/*
+ * Architecture specific parts of the Floppy driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 2000 Ralf Baechle
+ */
+#ifndef _ASM_FLOPPY_H
+#define _ASM_FLOPPY_H
+
+static inline void fd_cacheflush(char * addr, long size)
+{
+        dma_cache_wback_inv((unsigned long)addr,size);
+}
+
+#define MAX_BUFFER_SECTORS 24
+
+
+/*
+ * And on Mips's the CMOS info fails also ...
+ *
+ * FIXME: This information should come from the ARC configuration tree
+ *        or whereever a particular machine has stored this ...
+ */
+#define FLOPPY0_TYPE            fd_drive_type(0)
+#define FLOPPY1_TYPE            fd_drive_type(1)
+
+#define FDC1                    fd_getfdaddr1();
+
+#define N_FDC 1                 /* do you *really* want a second controller? */
+#define N_DRIVE 8
+
+#define FLOPPY_MOTOR_MASK 0xf0
+
+/*
+ * The DMA channel used by the floppy controller cannot access data at
+ * addresses >= 16MB
+ *
+ * Went back to the 1MB limit, as some people had problems with the floppy
+ * driver otherwise. It doesn't matter much for performance anyway, as most
+ * floppy accesses go through the track buffer.
+ *
+ * On MIPSes using vdma, this actually means that *all* transfers go thru
+ * the * track buffer since 0x1000000 is always smaller than KSEG0/1.
+ * Actually this needs to be a bit more complicated since the so much different
+ * hardware available with MIPS CPUs ...
+ */
+#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
+
+#define EXTRA_FLOPPY_PARAMS
+
+#include <floppy.h>
+
+#endif /* _ASM_FLOPPY_H */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
new file mode 100644
index 000000000000..1d9aa0979181
--- /dev/null
+++ b/include/asm-mips/fpregdef.h
@@ -0,0 +1,99 @@
+/*
+ * Definitions for the FPU register names
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_FPREGDEF_H
+#define _ASM_FPREGDEF_H
+
+#include <asm/sgidefs.h>
+                                                                                
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * These definitions only cover the R3000-ish 16/32 register model.
+ * But we're trying to be R3000 friendly anyway ...
+ */
+#define fv0     $f0      /* return value */
+#define fv0f    $f1
+#define fv1     $f2
+#define fv1f    $f3
+#define fa0     $f12     /* argument registers */
+#define fa0f    $f13
+#define fa1     $f14
+#define fa1f    $f15
+#define ft0     $f4      /* caller saved */
+#define ft0f    $f5
+#define ft1     $f6
+#define ft1f    $f7
+#define ft2     $f8
+#define ft2f    $f9
+#define ft3     $f10
+#define ft3f    $f11
+#define ft4     $f16
+#define ft4f    $f17
+#define ft5     $f18
+#define ft5f    $f19
+#define fs0     $f20     /* callee saved */
+#define fs0f    $f21
+#define fs1     $f22
+#define fs1f    $f23
+#define fs2     $f24
+#define fs2f    $f25
+#define fs3     $f26
+#define fs3f    $f27
+#define fs4     $f28
+#define fs4f    $f29
+#define fs5     $f30
+#define fs5f    $f31
+
+#define fcr31   $31      /* FPU status register */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+                                                                                
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define fv0     $f0     /* return value */
+#define fv1     $f2
+#define fa0     $f12    /* argument registers */
+#define fa1     $f13
+#define fa2     $f14
+#define fa3     $f15
+#define fa4     $f16
+#define fa5     $f17
+#define fa6     $f18
+#define fa7     $f19
+#define ft0     $f4     /* caller saved */
+#define ft1     $f5
+#define ft2     $f6
+#define ft3     $f7
+#define ft4     $f8
+#define ft5     $f9
+#define ft6     $f10
+#define ft7     $f11
+#define ft8     $f20
+#define ft9     $f21
+#define ft10    $f22
+#define ft11    $f23
+#define ft12    $f1
+#define ft13    $f3
+#define fs0     $f24    /* callee saved */
+#define fs1     $f25
+#define fs2     $f26
+#define fs3     $f27
+#define fs4     $f28
+#define fs5     $f29
+#define fs6     $f30
+#define fs7     $f31
+
+#define fcr31   $31
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_FPREGDEF_H */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
new file mode 100644
index 000000000000..6cb38d5c0407
--- /dev/null
+++ b/include/asm-mips/fpu.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_FPU_H
+#define _ASM_FPU_H
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/thread_info.h>
+
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/bitops.h>
+#include <asm/processor.h>
+#include <asm/current.h>
+
+struct sigcontext;
+struct sigcontext32;
+
+extern asmlinkage int (*save_fp_context)(struct sigcontext *sc);
+extern asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
+
+extern asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
+extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
+
+extern void fpu_emulator_init_fpu(void);
+extern void _init_fpu(void);
+extern void _save_fp(struct task_struct *);
+extern void _restore_fp(struct task_struct *);
+
+#if defined(CONFIG_CPU_SB1)
+#define __enable_fpu_hazard()                                           \
+do {                                                                    \
+        asm(".set       push            \n\t"                           \
+            ".set       mips64          \n\t"                           \
+            ".set       noreorder       \n\t"                           \
+            "ssnop                      \n\t"                           \
+            "bnezl      $0, .+4         \n\t"                           \
+            "ssnop                      \n\t"                           \
+            ".set pop");                                                \
+} while (0)
+#else
+#define __enable_fpu_hazard()                                           \
+do {                                                                    \
+        asm("nop;nop;nop;nop");         /* max. hazard */               \
+} while (0)
+#endif
+
+#define __enable_fpu()                                                  \
+do {                                                                    \
+        set_c0_status(ST0_CU1);                                         \
+        __enable_fpu_hazard();                                          \
+} while (0)
+
+#define __disable_fpu()                                                 \
+do {                                                                    \
+        clear_c0_status(ST0_CU1);                                       \
+        /* We don't care about the c0 hazard here  */                   \
+} while (0)
+
+#define enable_fpu()                                                    \
+do {                                                                    \
+        if (cpu_has_fpu)                                                \
+                __enable_fpu();                                         \
+} while (0)
+
+#define disable_fpu()                                                   \
+do {                                                                    \
+        if (cpu_has_fpu)                                                \
+                __disable_fpu();                                        \
+} while (0)
+
+
+#define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
+
+static inline int is_fpu_owner(void)
+{
+        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 
+}
+
+static inline void own_fpu(void)
+{
+        if (cpu_has_fpu) {
+                __enable_fpu();
+                KSTK_STATUS(current) |= ST0_CU1;
+                set_thread_flag(TIF_USEDFPU); 
+        }
+}
+
+static inline void lose_fpu(void)
+{
+        if (cpu_has_fpu) {
+                KSTK_STATUS(current) &= ~ST0_CU1;
+                clear_thread_flag(TIF_USEDFPU); 
+                __disable_fpu();
+        }
+}
+
+static inline void init_fpu(void)
+{
+        if (cpu_has_fpu) {
+                _init_fpu();
+        } else {
+                fpu_emulator_init_fpu();
+        }
+}
+
+static inline void save_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _save_fp(tsk);
+}
+
+static inline void restore_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _restore_fp(tsk);
+}
+
+static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
+{
+        if (cpu_has_fpu) {
+                if ((tsk == current) && is_fpu_owner()) 
+                        _save_fp(current);
+                return tsk->thread.fpu.hard.fpr;
+        }
+
+        return tsk->thread.fpu.soft.fpr;
+}
+
+#endif /* _ASM_FPU_H */
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
new file mode 100644
index 000000000000..46972ae2b95d
--- /dev/null
+++ b/include/asm-mips/fpu_emulator.h
@@ -0,0 +1,38 @@
+/*
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Further private data for which no space exists in mips_fpu_soft_struct.
+ * This should be subsumed into the mips_fpu_soft_struct structure as
+ * defined in processor.h as soon as the absurd wired absolute assembler
+ * offsets become dynamic at compile time.
+ *
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ */
+#ifndef _ASM_FPU_EMULATOR_H
+#define _ASM_FPU_EMULATOR_H
+
+struct mips_fpu_emulator_private {
+        unsigned int eir;
+        struct {
+                unsigned int emulated;
+                unsigned int loads;
+                unsigned int stores;
+                unsigned int cp1ops;
+                unsigned int cp1xops;
+                unsigned int errors;
+        } stats;
+};
+
+#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h
new file mode 100644
index 000000000000..070dfd84a8e8
--- /dev/null
+++ b/include/asm-mips/galileo-boards/ev96100.h
@@ -0,0 +1,55 @@
+/*
+ *
+ */
+#ifndef _MIPS_EV96100_H
+#define _MIPS_EV96100_H
+
+#include <asm/addrspace.h>
+
+/*
+ *   GT64120 config space base address
+ */
+#define GT64120_BASE    (KSEG1ADDR(0x14000000))
+#define MIPS_GT_BASE    GT64120_BASE
+
+/*
+ *   PCI Bus allocation
+ */
+#define GT_PCI_MEM_BASE    0x12000000UL
+#define GT_PCI_MEM_SIZE    0x02000000UL
+#define GT_PCI_IO_BASE     0x10000000UL
+#define GT_PCI_IO_SIZE     0x02000000UL
+#define GT_ISA_IO_BASE     PCI_IO_BASE
+
+/*
+ *   Duart I/O ports.
+ */
+#define EV96100_COM1_BASE_ADDR  (0xBD000000 + 0x20)
+#define EV96100_COM2_BASE_ADDR  (0xBD000000 + 0x00)
+
+
+/*
+ *   EV96100 interrupt controller register base.
+ */
+#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
+
+/*
+ *   EV96100 UART register base.
+ */
+#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
+#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
+#define EV96100_BASE_BAUD       ( 3686400 / 16 )
+
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.
+ */
+#define __GT_READ(ofs)                                                  \
+        (*(volatile u32 *)(GT64120_BASE+(ofs)))
+#define __GT_WRITE(ofs, data)                                           \
+        do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+#define GT_READ(ofs)            le32_to_cpu(__GT_READ(ofs))
+#define GT_WRITE(ofs, data)     __GT_WRITE(ofs, cpu_to_le32(data))
+
+#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/ev96100int.h b/include/asm-mips/galileo-boards/ev96100int.h
new file mode 100644
index 000000000000..c58b16d06d6e
--- /dev/null
+++ b/include/asm-mips/galileo-boards/ev96100int.h
@@ -0,0 +1,12 @@
+/*
+ *
+ */
+#ifndef _MIPS_EV96100INT_H
+#define _MIPS_EV96100INT_H
+
+#define EV96100INT_UART_0    6     /* IP 6 */
+#define EV96100INT_TIMER     7     /* IP 7 */
+
+extern void ev96100int_init(void);
+
+#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h
new file mode 100644
index 000000000000..aabd1b629c19
--- /dev/null
+++ b/include/asm-mips/galileo-boards/gt96100.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Register offsets of the MIPS GT96100 Advanced Communication Controller.
+ */
+#ifndef _GT96100_H
+#define _GT96100_H
+
+/*
+ * Galileo GT96100 internal register base.
+ */
+#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
+
+#define GT96100_WRITE(ofs, data) \
+    *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
+#define GT96100_READ(ofs) \
+    le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
+
+#define GT96100_ETH_IO_SIZE 0x4000
+
+/************************************************************************
+ *  Register offset addresses follow
+ ************************************************************************/
+
+/* CPU Interface Control Registers */
+#define GT96100_CPU_INTERF_CONFIG 0x000000
+
+/* Ethernet Ports */
+#define GT96100_ETH_PHY_ADDR_REG             0x080800
+#define GT96100_ETH_SMI_REG                  0x080810
+/*
+  These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
+  get offsets to port 1 registers.
+*/
+#define GT96100_ETH_PORT_CONFIG          0x084800
+#define GT96100_ETH_PORT_CONFIG_EXT      0x084808
+#define GT96100_ETH_PORT_COMM            0x084810
+#define GT96100_ETH_PORT_STATUS          0x084818
+#define GT96100_ETH_SER_PARAM            0x084820
+#define GT96100_ETH_HASH_TBL_PTR         0x084828
+#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L    0x084830
+#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H    0x084838
+#define GT96100_ETH_SDMA_CONFIG          0x084840
+#define GT96100_ETH_SDMA_COMM            0x084848
+#define GT96100_ETH_INT_CAUSE            0x084850
+#define GT96100_ETH_INT_MASK             0x084858
+#define GT96100_ETH_1ST_RX_DESC_PTR0         0x084880
+#define GT96100_ETH_1ST_RX_DESC_PTR1         0x084884
+#define GT96100_ETH_1ST_RX_DESC_PTR2         0x084888
+#define GT96100_ETH_1ST_RX_DESC_PTR3         0x08488C
+#define GT96100_ETH_CURR_RX_DESC_PTR0        0x0848A0
+#define GT96100_ETH_CURR_RX_DESC_PTR1        0x0848A4
+#define GT96100_ETH_CURR_RX_DESC_PTR2        0x0848A8
+#define GT96100_ETH_CURR_RX_DESC_PTR3        0x0848AC
+#define GT96100_ETH_CURR_TX_DESC_PTR0        0x0848E0
+#define GT96100_ETH_CURR_TX_DESC_PTR1        0x0848E4
+#define GT96100_ETH_MIB_COUNT_BASE           0x085800
+
+/* SDMAs */
+#define GT96100_SDMA_GROUP_CONFIG           0x101AF0
+/* SDMA Group 0 */
+#define GT96100_SDMA_G0_CHAN0_CONFIG        0x000900
+#define GT96100_SDMA_G0_CHAN0_COMM          0x000908
+#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE      0x008900
+#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR  0x008910
+#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE      0x00C900
+#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR  0x00C910
+#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR   0x00C914
+#define GT96100_SDMA_G0_CHAN1_CONFIG        0x010900
+#define GT96100_SDMA_G0_CHAN1_COMM          0x010908
+#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE      0x018900
+#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR  0x018910
+#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE      0x01C900
+#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR  0x01C910
+#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR   0x01C914
+#define GT96100_SDMA_G0_CHAN2_CONFIG        0x020900
+#define GT96100_SDMA_G0_CHAN2_COMM          0x020908
+#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE      0x028900
+#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR  0x028910
+#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE      0x02C900
+#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR  0x02C910
+#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR   0x02C914
+#define GT96100_SDMA_G0_CHAN3_CONFIG        0x030900
+#define GT96100_SDMA_G0_CHAN3_COMM          0x030908
+#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE      0x038900
+#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR  0x038910
+#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE      0x03C900
+#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR  0x03C910
+#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR   0x03C914
+#define GT96100_SDMA_G0_CHAN4_CONFIG        0x040900
+#define GT96100_SDMA_G0_CHAN4_COMM          0x040908
+#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE      0x048900
+#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR  0x048910
+#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE      0x04C900
+#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR  0x04C910
+#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR   0x04C914
+#define GT96100_SDMA_G0_CHAN5_CONFIG        0x050900
+#define GT96100_SDMA_G0_CHAN5_COMM          0x050908
+#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE      0x058900
+#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR  0x058910
+#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE      0x05C900
+#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR  0x05C910
+#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR   0x05C914
+#define GT96100_SDMA_G0_CHAN6_CONFIG        0x060900
+#define GT96100_SDMA_G0_CHAN6_COMM          0x060908
+#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE      0x068900
+#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR  0x068910
+#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE      0x06C900
+#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR  0x06C910
+#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR   0x06C914
+#define GT96100_SDMA_G0_CHAN7_CONFIG        0x070900
+#define GT96100_SDMA_G0_CHAN7_COMM          0x070908
+#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE      0x078900
+#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR  0x078910
+#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE      0x07C900
+#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR  0x07C910
+#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR   0x07C914
+/* SDMA Group 1 */
+#define GT96100_SDMA_G1_CHAN0_CONFIG        0x100900
+#define GT96100_SDMA_G1_CHAN0_COMM          0x100908
+#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE      0x108900
+#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR  0x108910
+#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE      0x10C900
+#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR  0x10C910
+#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR   0x10C914
+#define GT96100_SDMA_G1_CHAN1_CONFIG        0x110900
+#define GT96100_SDMA_G1_CHAN1_COMM          0x110908
+#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE      0x118900
+#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR  0x118910
+#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE      0x11C900
+#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR  0x11C910
+#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR   0x11C914
+#define GT96100_SDMA_G1_CHAN2_CONFIG        0x120900
+#define GT96100_SDMA_G1_CHAN2_COMM          0x120908
+#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE      0x128900
+#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR  0x128910
+#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE      0x12C900
+#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR  0x12C910
+#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR   0x12C914
+#define GT96100_SDMA_G1_CHAN3_CONFIG        0x130900
+#define GT96100_SDMA_G1_CHAN3_COMM          0x130908
+#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE      0x138900
+#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR  0x138910
+#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE      0x13C900
+#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR  0x13C910
+#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR   0x13C914
+#define GT96100_SDMA_G1_CHAN4_CONFIG        0x140900
+#define GT96100_SDMA_G1_CHAN4_COMM          0x140908
+#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE      0x148900
+#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR  0x148910
+#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE      0x14C900
+#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR  0x14C910
+#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR   0x14C914
+#define GT96100_SDMA_G1_CHAN5_CONFIG        0x150900
+#define GT96100_SDMA_G1_CHAN5_COMM          0x150908
+#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE      0x158900
+#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR  0x158910
+#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE      0x15C900
+#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR  0x15C910
+#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR   0x15C914
+#define GT96100_SDMA_G1_CHAN6_CONFIG        0x160900
+#define GT96100_SDMA_G1_CHAN6_COMM          0x160908
+#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE      0x168900
+#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR  0x168910
+#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE      0x16C900
+#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR  0x16C910
+#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR   0x16C914
+#define GT96100_SDMA_G1_CHAN7_CONFIG        0x170900
+#define GT96100_SDMA_G1_CHAN7_COMM          0x170908
+#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE      0x178900
+#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR  0x178910
+#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE      0x17C900
+#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR  0x17C910
+#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR   0x17C914
+/*  MPSCs  */
+#define GT96100_MPSC0_MAIN_CONFIG_LOW   0x000A00
+#define GT96100_MPSC0_MAIN_CONFIG_HIGH  0x000A04
+#define GT96100_MPSC0_PROTOCOL_CONFIG   0x000A08
+#define GT96100_MPSC_CHAN0_REG1         0x000A0C
+#define GT96100_MPSC_CHAN0_REG2         0x000A10
+#define GT96100_MPSC_CHAN0_REG3         0x000A14
+#define GT96100_MPSC_CHAN0_REG4         0x000A18
+#define GT96100_MPSC_CHAN0_REG5         0x000A1C
+#define GT96100_MPSC_CHAN0_REG6         0x000A20
+#define GT96100_MPSC_CHAN0_REG7         0x000A24
+#define GT96100_MPSC_CHAN0_REG8         0x000A28
+#define GT96100_MPSC_CHAN0_REG9         0x000A2C
+#define GT96100_MPSC_CHAN0_REG10        0x000A30
+#define GT96100_MPSC_CHAN0_REG11        0x000A34
+#define GT96100_MPSC1_MAIN_CONFIG_LOW   0x008A00
+#define GT96100_MPSC1_MAIN_CONFIG_HIGH  0x008A04
+#define GT96100_MPSC1_PROTOCOL_CONFIG   0x008A08
+#define GT96100_MPSC_CHAN1_REG1         0x008A0C
+#define GT96100_MPSC_CHAN1_REG2         0x008A10
+#define GT96100_MPSC_CHAN1_REG3         0x008A14
+#define GT96100_MPSC_CHAN1_REG4         0x008A18
+#define GT96100_MPSC_CHAN1_REG5         0x008A1C
+#define GT96100_MPSC_CHAN1_REG6         0x008A20
+#define GT96100_MPSC_CHAN1_REG7         0x008A24
+#define GT96100_MPSC_CHAN1_REG8         0x008A28
+#define GT96100_MPSC_CHAN1_REG9         0x008A2C
+#define GT96100_MPSC_CHAN1_REG10        0x008A30
+#define GT96100_MPSC_CHAN1_REG11        0x008A34
+#define GT96100_MPSC2_MAIN_CONFIG_LOW   0x010A00
+#define GT96100_MPSC2_MAIN_CONFIG_HIGH  0x010A04
+#define GT96100_MPSC2_PROTOCOL_CONFIG   0x010A08
+#define GT96100_MPSC_CHAN2_REG1         0x010A0C
+#define GT96100_MPSC_CHAN2_REG2         0x010A10
+#define GT96100_MPSC_CHAN2_REG3         0x010A14
+#define GT96100_MPSC_CHAN2_REG4         0x010A18
+#define GT96100_MPSC_CHAN2_REG5         0x010A1C
+#define GT96100_MPSC_CHAN2_REG6         0x010A20
+#define GT96100_MPSC_CHAN2_REG7         0x010A24
+#define GT96100_MPSC_CHAN2_REG8         0x010A28
+#define GT96100_MPSC_CHAN2_REG9         0x010A2C
+#define GT96100_MPSC_CHAN2_REG10        0x010A30
+#define GT96100_MPSC_CHAN2_REG11        0x010A34
+#define GT96100_MPSC3_MAIN_CONFIG_LOW   0x018A00
+#define GT96100_MPSC3_MAIN_CONFIG_HIGH  0x018A04
+#define GT96100_MPSC3_PROTOCOL_CONFIG   0x018A08
+#define GT96100_MPSC_CHAN3_REG1         0x018A0C
+#define GT96100_MPSC_CHAN3_REG2         0x018A10
+#define GT96100_MPSC_CHAN3_REG3         0x018A14
+#define GT96100_MPSC_CHAN3_REG4         0x018A18
+#define GT96100_MPSC_CHAN3_REG5         0x018A1C
+#define GT96100_MPSC_CHAN3_REG6         0x018A20
+#define GT96100_MPSC_CHAN3_REG7         0x018A24
+#define GT96100_MPSC_CHAN3_REG8         0x018A28
+#define GT96100_MPSC_CHAN3_REG9         0x018A2C
+#define GT96100_MPSC_CHAN3_REG10        0x018A30
+#define GT96100_MPSC_CHAN3_REG11        0x018A34
+#define GT96100_MPSC4_MAIN_CONFIG_LOW   0x020A00
+#define GT96100_MPSC4_MAIN_CONFIG_HIGH  0x020A04
+#define GT96100_MPSC4_PROTOCOL_CONFIG   0x020A08
+#define GT96100_MPSC_CHAN4_REG1         0x020A0C
+#define GT96100_MPSC_CHAN4_REG2         0x020A10
+#define GT96100_MPSC_CHAN4_REG3         0x020A14
+#define GT96100_MPSC_CHAN4_REG4         0x020A18
+#define GT96100_MPSC_CHAN4_REG5         0x020A1C
+#define GT96100_MPSC_CHAN4_REG6         0x020A20
+#define GT96100_MPSC_CHAN4_REG7         0x020A24
+#define GT96100_MPSC_CHAN4_REG8         0x020A28
+#define GT96100_MPSC_CHAN4_REG9         0x020A2C
+#define GT96100_MPSC_CHAN4_REG10        0x020A30
+#define GT96100_MPSC_CHAN4_REG11        0x020A34
+#define GT96100_MPSC5_MAIN_CONFIG_LOW   0x028A00
+#define GT96100_MPSC5_MAIN_CONFIG_HIGH  0x028A04
+#define GT96100_MPSC5_PROTOCOL_CONFIG   0x028A08
+#define GT96100_MPSC_CHAN5_REG1         0x028A0C
+#define GT96100_MPSC_CHAN5_REG2         0x028A10
+#define GT96100_MPSC_CHAN5_REG3         0x028A14
+#define GT96100_MPSC_CHAN5_REG4         0x028A18
+#define GT96100_MPSC_CHAN5_REG5         0x028A1C
+#define GT96100_MPSC_CHAN5_REG6         0x028A20
+#define GT96100_MPSC_CHAN5_REG7         0x028A24
+#define GT96100_MPSC_CHAN5_REG8         0x028A28
+#define GT96100_MPSC_CHAN5_REG9         0x028A2C
+#define GT96100_MPSC_CHAN5_REG10        0x028A30
+#define GT96100_MPSC_CHAN5_REG11        0x028A34
+#define GT96100_MPSC6_MAIN_CONFIG_LOW   0x030A00
+#define GT96100_MPSC6_MAIN_CONFIG_HIGH  0x030A04
+#define GT96100_MPSC6_PROTOCOL_CONFIG   0x030A08
+#define GT96100_MPSC_CHAN6_REG1         0x030A0C
+#define GT96100_MPSC_CHAN6_REG2         0x030A10
+#define GT96100_MPSC_CHAN6_REG3         0x030A14
+#define GT96100_MPSC_CHAN6_REG4         0x030A18
+#define GT96100_MPSC_CHAN6_REG5         0x030A1C
+#define GT96100_MPSC_CHAN6_REG6         0x030A20
+#define GT96100_MPSC_CHAN6_REG7         0x030A24
+#define GT96100_MPSC_CHAN6_REG8         0x030A28
+#define GT96100_MPSC_CHAN6_REG9         0x030A2C
+#define GT96100_MPSC_CHAN6_REG10        0x030A30
+#define GT96100_MPSC_CHAN6_REG11        0x030A34
+#define GT96100_MPSC7_MAIN_CONFIG_LOW   0x038A00
+#define GT96100_MPSC7_MAIN_CONFIG_HIGH  0x038A04
+#define GT96100_MPSC7_PROTOCOL_CONFIG   0x038A08
+#define GT96100_MPSC_CHAN7_REG1         0x038A0C
+#define GT96100_MPSC_CHAN7_REG2         0x038A10
+#define GT96100_MPSC_CHAN7_REG3         0x038A14
+#define GT96100_MPSC_CHAN7_REG4         0x038A18
+#define GT96100_MPSC_CHAN7_REG5         0x038A1C
+#define GT96100_MPSC_CHAN7_REG6         0x038A20
+#define GT96100_MPSC_CHAN7_REG7         0x038A24
+#define GT96100_MPSC_CHAN7_REG8         0x038A28
+#define GT96100_MPSC_CHAN7_REG9         0x038A2C
+#define GT96100_MPSC_CHAN7_REG10        0x038A30
+#define GT96100_MPSC_CHAN7_REG11        0x038A34
+/*  FlexTDMs  */
+/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
+#define GT96100_FXTDM0_TDPR0_BLK0_BASE  0x000B00
+#define GT96100_FXTDM0_TDPR0_BLK1_BASE  0x001B00
+#define GT96100_FXTDM0_TDPR0_BLK2_BASE  0x002B00
+#define GT96100_FXTDM0_TDPR0_BLK3_BASE  0x003B00
+/* RDPR0 - Receive Dual Port RAM. block size 0xff */
+#define GT96100_FXTDM0_RDPR0_BLK0_BASE  0x004B00
+#define GT96100_FXTDM0_RDPR0_BLK1_BASE  0x005B00
+#define GT96100_FXTDM0_RDPR0_BLK2_BASE  0x006B00
+#define GT96100_FXTDM0_RDPR0_BLK3_BASE  0x007B00
+#define GT96100_FXTDM0_TX_READ_PTR      0x008B00
+#define GT96100_FXTDM0_RX_READ_PTR      0x008B04
+#define GT96100_FXTDM0_CONFIG       0x008B08
+#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
+#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
+#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
+#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
+#define GT96100_FXTDM1_TDPR1_BLK0_BASE  0x010B00
+#define GT96100_FXTDM1_TDPR1_BLK1_BASE  0x011B00
+#define GT96100_FXTDM1_TDPR1_BLK2_BASE  0x012B00
+#define GT96100_FXTDM1_TDPR1_BLK3_BASE  0x013B00
+#define GT96100_FXTDM1_RDPR1_BLK0_BASE  0x014B00
+#define GT96100_FXTDM1_RDPR1_BLK1_BASE  0x015B00
+#define GT96100_FXTDM1_RDPR1_BLK2_BASE  0x016B00
+#define GT96100_FXTDM1_RDPR1_BLK3_BASE  0x017B00
+#define GT96100_FXTDM1_TX_READ_PTR      0x018B00
+#define GT96100_FXTDM1_RX_READ_PTR      0x018B04
+#define GT96100_FXTDM1_CONFIG       0x018B08
+#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
+#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
+#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
+#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
+#define GT96100_FLTDM2_TDPR2_BLK0_BASE  0x020B00
+#define GT96100_FLTDM2_TDPR2_BLK1_BASE  0x021B00
+#define GT96100_FLTDM2_TDPR2_BLK2_BASE  0x022B00
+#define GT96100_FLTDM2_TDPR2_BLK3_BASE  0x023B00
+#define GT96100_FLTDM2_RDPR2_BLK0_BASE  0x024B00
+#define GT96100_FLTDM2_RDPR2_BLK1_BASE  0x025B00
+#define GT96100_FLTDM2_RDPR2_BLK2_BASE  0x026B00
+#define GT96100_FLTDM2_RDPR2_BLK3_BASE  0x027B00
+#define GT96100_FLTDM2_TX_READ_PTR      0x028B00
+#define GT96100_FLTDM2_RX_READ_PTR      0x028B04
+#define GT96100_FLTDM2_CONFIG       0x028B08
+#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
+#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
+#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
+#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
+#define GT96100_FLTDM3_TDPR3_BLK0_BASE  0x030B00
+#define GT96100_FLTDM3_TDPR3_BLK1_BASE  0x031B00
+#define GT96100_FLTDM3_TDPR3_BLK2_BASE  0x032B00
+#define GT96100_FLTDM3_TDPR3_BLK3_BASE  0x033B00
+#define GT96100_FXTDM3_RDPR3_BLK0_BASE  0x034B00
+#define GT96100_FXTDM3_RDPR3_BLK1_BASE  0x035B00
+#define GT96100_FXTDM3_RDPR3_BLK2_BASE  0x036B00
+#define GT96100_FXTDM3_RDPR3_BLK3_BASE  0x037B00
+#define GT96100_FXTDM3_TX_READ_PTR      0x038B00
+#define GT96100_FXTDM3_RX_READ_PTR      0x038B04
+#define GT96100_FXTDM3_CONFIG       0x038B08
+#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
+#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
+#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
+#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
+/*  Baud Rate Generators  */
+#define GT96100_BRG0_CONFIG     0x102A00
+#define GT96100_BRG0_BAUD_TUNE  0x102A04
+#define GT96100_BRG1_CONFIG     0x102A08
+#define GT96100_BRG1_BAUD_TUNE  0x102A0C
+#define GT96100_BRG2_CONFIG     0x102A10
+#define GT96100_BRG2_BAUD_TUNE  0x102A14
+#define GT96100_BRG3_CONFIG     0x102A18
+#define GT96100_BRG3_BAUD_TUNE  0x102A1C
+#define GT96100_BRG4_CONFIG     0x102A20
+#define GT96100_BRG4_BAUD_TUNE  0x102A24
+#define GT96100_BRG5_CONFIG     0x102A28
+#define GT96100_BRG5_BAUD_TUNE  0x102A2C
+#define GT96100_BRG6_CONFIG     0x102A30
+#define GT96100_BRG6_BAUD_TUNE  0x102A34
+#define GT96100_BRG7_CONFIG     0x102A38
+#define GT96100_BRG7_BAUD_TUNE  0x102A3C
+/*  Routing Registers  */
+#define GT96100_ROUTE_MAIN      0x101A00
+#define GT96100_ROUTE_RX_CLOCK  0x101A10
+#define GT96100_ROUTE_TX_CLOCK  0x101A20
+/*  General Purpose Ports  */
+#define GT96100_GPP_CONFIG0     0x100A00
+#define GT96100_GPP_CONFIG1     0x100A04
+#define GT96100_GPP_CONFIG2     0x100A08
+#define GT96100_GPP_CONFIG3     0x100A0C
+#define GT96100_GPP_IO0         0x100A20
+#define GT96100_GPP_IO1         0x100A24
+#define GT96100_GPP_IO2         0x100A28
+#define GT96100_GPP_IO3         0x100A2C
+#define GT96100_GPP_DATA0       0x100A40
+#define GT96100_GPP_DATA1       0x100A44
+#define GT96100_GPP_DATA2       0x100A48
+#define GT96100_GPP_DATA3       0x100A4C
+#define GT96100_GPP_LEVEL0      0x100A60
+#define GT96100_GPP_LEVEL1      0x100A64
+#define GT96100_GPP_LEVEL2      0x100A68
+#define GT96100_GPP_LEVEL3      0x100A6C
+/*  Watchdog  */
+#define GT96100_WD_CONFIG   0x101A80
+#define GT96100_WD_VALUE    0x101A84
+/* Communication Unit Arbiter  */
+#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
+/*  PCI Arbiters  */
+#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
+#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
+/* CIU Arbiter */
+#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
+/* Interrupt Controller */
+#define GT96100_MAIN_CAUSE     0x000C18
+#define GT96100_INT0_MAIN_MASK 0x000C1C
+#define GT96100_INT1_MAIN_MASK 0x000C24
+#define GT96100_HIGH_CAUSE     0x000C98
+#define GT96100_INT0_HIGH_MASK 0x000C9C
+#define GT96100_INT1_HIGH_MASK 0x000CA4
+#define GT96100_INT0_SELECT    0x000C70
+#define GT96100_INT1_SELECT    0x000C74
+#define GT96100_SERIAL_CAUSE   0x103A00
+#define GT96100_SERINT0_MASK   0x103A80
+#define GT96100_SERINT1_MASK   0x103A88
+
+#endif /*  _GT96100_H */
diff --git a/include/asm-mips/gcc/sgidefs.h b/include/asm-mips/gcc/sgidefs.h
new file mode 100644
index 000000000000..05994371a2af
--- /dev/null
+++ b/include/asm-mips/gcc/sgidefs.h
@@ -0,0 +1,17 @@
+/*
+ * include/sgidefs.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996 by Ralf Baechle
+ *
+ * This file is here to satisfy GCC's expectations.
+ */
+#ifndef __SGIDEFS_H
+#define __SGIDEFS_H
+
+#include <asm/sgidefs.h>
+
+#endif /* __SGIDEFS_H */
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
new file mode 100644
index 000000000000..22f67d4a71ab
--- /dev/null
+++ b/include/asm-mips/gdb-stub.h
@@ -0,0 +1,215 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 Andreas Busse
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_GDB_STUB_H
+#define _ASM_GDB_STUB_H
+
+
+/*
+ * important register numbers
+ */
+
+#define REG_EPC                 37
+#define REG_FP                  72
+#define REG_SP                  29
+
+/*
+ * Stack layout for the GDB exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+ *
+ * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+ */
+#define NUMREGS                 90
+
+#define GDB_FR_REG0             (PTRSIZE*6)                     /* 0 */
+#define GDB_FR_REG1             ((GDB_FR_REG0) + LONGSIZE)      /* 1 */
+#define GDB_FR_REG2             ((GDB_FR_REG1) + LONGSIZE)      /* 2 */
+#define GDB_FR_REG3             ((GDB_FR_REG2) + LONGSIZE)      /* 3 */
+#define GDB_FR_REG4             ((GDB_FR_REG3) + LONGSIZE)      /* 4 */
+#define GDB_FR_REG5             ((GDB_FR_REG4) + LONGSIZE)      /* 5 */
+#define GDB_FR_REG6             ((GDB_FR_REG5) + LONGSIZE)      /* 6 */
+#define GDB_FR_REG7             ((GDB_FR_REG6) + LONGSIZE)      /* 7 */
+#define GDB_FR_REG8             ((GDB_FR_REG7) + LONGSIZE)      /* 8 */
+#define GDB_FR_REG9             ((GDB_FR_REG8) + LONGSIZE)      /* 9 */
+#define GDB_FR_REG10            ((GDB_FR_REG9) + LONGSIZE)      /* 10 */
+#define GDB_FR_REG11            ((GDB_FR_REG10) + LONGSIZE)     /* 11 */
+#define GDB_FR_REG12            ((GDB_FR_REG11) + LONGSIZE)     /* 12 */
+#define GDB_FR_REG13            ((GDB_FR_REG12) + LONGSIZE)     /* 13 */
+#define GDB_FR_REG14            ((GDB_FR_REG13) + LONGSIZE)     /* 14 */
+#define GDB_FR_REG15            ((GDB_FR_REG14) + LONGSIZE)     /* 15 */
+#define GDB_FR_REG16            ((GDB_FR_REG15) + LONGSIZE)     /* 16 */
+#define GDB_FR_REG17            ((GDB_FR_REG16) + LONGSIZE)     /* 17 */
+#define GDB_FR_REG18            ((GDB_FR_REG17) + LONGSIZE)     /* 18 */
+#define GDB_FR_REG19            ((GDB_FR_REG18) + LONGSIZE)     /* 19 */
+#define GDB_FR_REG20            ((GDB_FR_REG19) + LONGSIZE)     /* 20 */
+#define GDB_FR_REG21            ((GDB_FR_REG20) + LONGSIZE)     /* 21 */
+#define GDB_FR_REG22            ((GDB_FR_REG21) + LONGSIZE)     /* 22 */
+#define GDB_FR_REG23            ((GDB_FR_REG22) + LONGSIZE)     /* 23 */
+#define GDB_FR_REG24            ((GDB_FR_REG23) + LONGSIZE)     /* 24 */
+#define GDB_FR_REG25            ((GDB_FR_REG24) + LONGSIZE)     /* 25 */
+#define GDB_FR_REG26            ((GDB_FR_REG25) + LONGSIZE)     /* 26 */
+#define GDB_FR_REG27            ((GDB_FR_REG26) + LONGSIZE)     /* 27 */
+#define GDB_FR_REG28            ((GDB_FR_REG27) + LONGSIZE)     /* 28 */
+#define GDB_FR_REG29            ((GDB_FR_REG28) + LONGSIZE)     /* 29 */
+#define GDB_FR_REG30            ((GDB_FR_REG29) + LONGSIZE)     /* 30 */
+#define GDB_FR_REG31            ((GDB_FR_REG30) + LONGSIZE)     /* 31 */
+
+/*
+ * Saved special registers
+ */
+#define GDB_FR_STATUS           ((GDB_FR_REG31) + LONGSIZE)     /* 32 */
+#define GDB_FR_LO               ((GDB_FR_STATUS) + LONGSIZE)    /* 33 */
+#define GDB_FR_HI               ((GDB_FR_LO) + LONGSIZE)        /* 34 */
+#define GDB_FR_BADVADDR         ((GDB_FR_HI) + LONGSIZE)        /* 35 */
+#define GDB_FR_CAUSE            ((GDB_FR_BADVADDR) + LONGSIZE)  /* 36 */
+#define GDB_FR_EPC              ((GDB_FR_CAUSE) + LONGSIZE)     /* 37 */
+
+/*
+ * Saved floating point registers
+ */
+#define GDB_FR_FPR0             ((GDB_FR_EPC) + LONGSIZE)       /* 38 */
+#define GDB_FR_FPR1             ((GDB_FR_FPR0) + LONGSIZE)      /* 39 */
+#define GDB_FR_FPR2             ((GDB_FR_FPR1) + LONGSIZE)      /* 40 */
+#define GDB_FR_FPR3             ((GDB_FR_FPR2) + LONGSIZE)      /* 41 */
+#define GDB_FR_FPR4             ((GDB_FR_FPR3) + LONGSIZE)      /* 42 */
+#define GDB_FR_FPR5             ((GDB_FR_FPR4) + LONGSIZE)      /* 43 */
+#define GDB_FR_FPR6             ((GDB_FR_FPR5) + LONGSIZE)      /* 44 */
+#define GDB_FR_FPR7             ((GDB_FR_FPR6) + LONGSIZE)      /* 45 */
+#define GDB_FR_FPR8             ((GDB_FR_FPR7) + LONGSIZE)      /* 46 */
+#define GDB_FR_FPR9             ((GDB_FR_FPR8) + LONGSIZE)      /* 47 */
+#define GDB_FR_FPR10            ((GDB_FR_FPR9) + LONGSIZE)      /* 48 */
+#define GDB_FR_FPR11            ((GDB_FR_FPR10) + LONGSIZE)     /* 49 */
+#define GDB_FR_FPR12            ((GDB_FR_FPR11) + LONGSIZE)     /* 50 */
+#define GDB_FR_FPR13            ((GDB_FR_FPR12) + LONGSIZE)     /* 51 */
+#define GDB_FR_FPR14            ((GDB_FR_FPR13) + LONGSIZE)     /* 52 */
+#define GDB_FR_FPR15            ((GDB_FR_FPR14) + LONGSIZE)     /* 53 */
+#define GDB_FR_FPR16            ((GDB_FR_FPR15) + LONGSIZE)     /* 54 */
+#define GDB_FR_FPR17            ((GDB_FR_FPR16) + LONGSIZE)     /* 55 */
+#define GDB_FR_FPR18            ((GDB_FR_FPR17) + LONGSIZE)     /* 56 */
+#define GDB_FR_FPR19            ((GDB_FR_FPR18) + LONGSIZE)     /* 57 */
+#define GDB_FR_FPR20            ((GDB_FR_FPR19) + LONGSIZE)     /* 58 */
+#define GDB_FR_FPR21            ((GDB_FR_FPR20) + LONGSIZE)     /* 59 */
+#define GDB_FR_FPR22            ((GDB_FR_FPR21) + LONGSIZE)     /* 60 */
+#define GDB_FR_FPR23            ((GDB_FR_FPR22) + LONGSIZE)     /* 61 */
+#define GDB_FR_FPR24            ((GDB_FR_FPR23) + LONGSIZE)     /* 62 */
+#define GDB_FR_FPR25            ((GDB_FR_FPR24) + LONGSIZE)     /* 63 */
+#define GDB_FR_FPR26            ((GDB_FR_FPR25) + LONGSIZE)     /* 64 */
+#define GDB_FR_FPR27            ((GDB_FR_FPR26) + LONGSIZE)     /* 65 */
+#define GDB_FR_FPR28            ((GDB_FR_FPR27) + LONGSIZE)     /* 66 */
+#define GDB_FR_FPR29            ((GDB_FR_FPR28) + LONGSIZE)     /* 67 */
+#define GDB_FR_FPR30            ((GDB_FR_FPR29) + LONGSIZE)     /* 68 */
+#define GDB_FR_FPR31            ((GDB_FR_FPR30) + LONGSIZE)     /* 69 */
+
+#define GDB_FR_FSR              ((GDB_FR_FPR31) + LONGSIZE)     /* 70 */
+#define GDB_FR_FIR              ((GDB_FR_FSR) + LONGSIZE)       /* 71 */
+#define GDB_FR_FRP              ((GDB_FR_FIR) + LONGSIZE)       /* 72 */
+
+#define GDB_FR_DUMMY            ((GDB_FR_FRP) + LONGSIZE)       /* 73, unused ??? */
+
+/*
+ * Again, CP0 registers
+ */
+#define GDB_FR_CP0_INDEX        ((GDB_FR_DUMMY) + LONGSIZE)     /* 74 */
+#define GDB_FR_CP0_RANDOM       ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
+#define GDB_FR_CP0_ENTRYLO0     ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
+#define GDB_FR_CP0_ENTRYLO1     ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
+#define GDB_FR_CP0_CONTEXT      ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
+#define GDB_FR_CP0_PAGEMASK     ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
+#define GDB_FR_CP0_WIRED        ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
+#define GDB_FR_CP0_REG7         ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
+#define GDB_FR_CP0_REG8         ((GDB_FR_CP0_REG7) + LONGSIZE)  /* 82 */
+#define GDB_FR_CP0_REG9         ((GDB_FR_CP0_REG8) + LONGSIZE)  /* 83 */
+#define GDB_FR_CP0_ENTRYHI      ((GDB_FR_CP0_REG9) + LONGSIZE)  /* 84 */
+#define GDB_FR_CP0_REG11        ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
+#define GDB_FR_CP0_REG12        ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
+#define GDB_FR_CP0_REG13        ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
+#define GDB_FR_CP0_REG14        ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
+#define GDB_FR_CP0_PRID         ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
+
+#define GDB_FR_SIZE             ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This is the same as above, but for the high-level
+ * part of the GDB stub.
+ */
+
+struct gdb_regs {
+        /*
+         * Pad bytes for argument save space on the stack
+         * 24/48 Bytes for 32/64 bit code
+         */
+        unsigned long pad0[6];
+
+        /*
+         * saved main processor registers
+         */
+        long     reg0,  reg1,  reg2,  reg3,  reg4,  reg5,  reg6,  reg7;
+        long     reg8,  reg9, reg10, reg11, reg12, reg13, reg14, reg15;
+        long    reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+        long    reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
+
+        /*
+         * Saved special registers
+         */
+        long    cp0_status;
+        long    lo;
+        long    hi;
+        long    cp0_badvaddr;
+        long    cp0_cause;
+        long    cp0_epc;
+
+        /*
+         * Saved floating point registers
+         */
+        long    fpr0,  fpr1,  fpr2,  fpr3,  fpr4,  fpr5,  fpr6,  fpr7;
+        long    fpr8,  fpr9,  fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
+        long    fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
+        long    fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
+
+        long    cp1_fsr;
+        long    cp1_fir;
+
+        /*
+         * Frame pointer
+         */
+        long    frame_ptr;
+        long    dummy;          /* unused */
+
+        /*
+         * saved cp0 registers
+         */
+        long    cp0_index;
+        long    cp0_random;
+        long    cp0_entrylo0;
+        long    cp0_entrylo1;
+        long    cp0_context;
+        long    cp0_pagemask;
+        long    cp0_wired;
+        long    cp0_reg7;
+        long    cp0_reg8;
+        long    cp0_reg9;
+        long    cp0_entryhi;
+        long    cp0_reg11;
+        long    cp0_reg12;
+        long    cp0_reg13;
+        long    cp0_reg14;
+        long    cp0_prid;
+};
+
+/*
+ * Prototypes
+ */
+
+extern int kgdb_enabled;
+void set_debug_traps(void);
+void set_async_breakpoint(unsigned long *epc);
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_GDB_STUB_H */
diff --git a/include/asm-mips/gfx.h b/include/asm-mips/gfx.h
new file mode 100644
index 000000000000..37235e41a6fd
--- /dev/null
+++ b/include/asm-mips/gfx.h
@@ -0,0 +1,55 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This is the user-visible SGI GFX interface.
+ *
+ * This must be used verbatim into the GNU libc.  It does not include
+ * any kernel-only bits on it.
+ *
+ * miguel@nuclecu.unam.mx
+ */
+#ifndef _ASM_GFX_H
+#define _ASM_GFX_H
+
+/* The iocls, yes, they do not make sense, but such is life */
+#define GFX_BASE             100
+#define GFX_GETNUM_BOARDS    (GFX_BASE + 1)
+#define GFX_GETBOARD_INFO    (GFX_BASE + 2)
+#define GFX_ATTACH_BOARD     (GFX_BASE + 3)
+#define GFX_DETACH_BOARD     (GFX_BASE + 4)
+#define GFX_IS_MANAGED       (GFX_BASE + 5)
+
+#define GFX_MAPALL           (GFX_BASE + 10)
+#define GFX_LABEL            (GFX_BASE + 11)
+
+#define GFX_INFO_NAME_SIZE  16
+#define GFX_INFO_LABEL_SIZE 16
+
+struct gfx_info {
+        char name  [GFX_INFO_NAME_SIZE];  /* board name */
+        char label [GFX_INFO_LABEL_SIZE]; /* label name */
+        unsigned short int xpmax, ypmax;  /* screen resolution */
+        unsigned int lenght;              /* size of a complete gfx_info for this board */
+};
+
+struct gfx_getboardinfo_args {
+        unsigned int board;     /* board number.  starting from zero */
+        void *buf;              /* pointer to gfx_info */
+        unsigned int len;       /* buffer size of buf */
+};
+
+struct gfx_attach_board_args {
+        unsigned int board;     /* board number, starting from zero */
+        void        *vaddr;     /* address where the board registers should be mapped */
+};
+
+#ifdef __KERNEL__
+/* umap.c */
+extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long);
+extern void *vmalloc_uncached (unsigned long size);
+extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr);
+#endif
+
+#endif /* _ASM_GFX_H */
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
new file mode 100644
index 000000000000..2edd171bb6cd
--- /dev/null
+++ b/include/asm-mips/gt64120.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#define MSK(n)                  ((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS              0x000
+
+#define GT_MULTI_OFS            0x120
+
+/* CPU Address Decode.  */
+#define GT_SCS10LD_OFS          0x008
+#define GT_SCS10HD_OFS          0x010
+#define GT_SCS32LD_OFS          0x018
+#define GT_SCS32HD_OFS          0x020
+#define GT_CS20LD_OFS           0x028
+#define GT_CS20HD_OFS           0x030
+#define GT_CS3BOOTLD_OFS        0x038
+#define GT_CS3BOOTHD_OFS        0x040
+#define GT_PCI0IOLD_OFS         0x048
+#define GT_PCI0IOHD_OFS         0x050
+#define GT_PCI0M0LD_OFS         0x058
+#define GT_PCI0M0HD_OFS         0x060
+#define GT_ISD_OFS              0x068
+
+#define GT_PCI0M1LD_OFS         0x080
+#define GT_PCI0M1HD_OFS         0x088
+#define GT_PCI1IOLD_OFS         0x090
+#define GT_PCI1IOHD_OFS         0x098
+#define GT_PCI1M0LD_OFS         0x0a0
+#define GT_PCI1M0HD_OFS         0x0a8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+
+#define GT_SCS10AR_OFS          0x0d0
+#define GT_SCS32AR_OFS          0x0d8
+#define GT_CS20R_OFS            0x0e0
+#define GT_CS3BOOTR_OFS         0x0e8
+
+#define GT_PCI0IOREMAP_OFS      0x0f0
+#define GT_PCI0M0REMAP_OFS      0x0f8
+#define GT_PCI0M1REMAP_OFS      0x100
+#define GT_PCI1IOREMAP_OFS      0x108
+#define GT_PCI1M0REMAP_OFS      0x110
+#define GT_PCI1M1REMAP_OFS      0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS    0x070
+#define GT_CPUERR_ADDRHI_OFS    0x078
+
+#define GT_CPUERR_DATALO_OFS    0x128                   /* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS    0x130                   /* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS    0x138                   /* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS         0x0c0
+#define GT_PCI1SYNC_OFS         0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS           0x400
+#define GT_SCS0HD_OFS           0x404
+#define GT_SCS1LD_OFS           0x408
+#define GT_SCS1HD_OFS           0x40c
+#define GT_SCS2LD_OFS           0x410
+#define GT_SCS2HD_OFS           0x414
+#define GT_SCS3LD_OFS           0x418
+#define GT_SCS3HD_OFS           0x41c
+#define GT_CS0LD_OFS            0x420
+#define GT_CS0HD_OFS            0x424
+#define GT_CS1LD_OFS            0x428
+#define GT_CS1HD_OFS            0x42c
+#define GT_CS2LD_OFS            0x430
+#define GT_CS2HD_OFS            0x434
+#define GT_CS3LD_OFS            0x438
+#define GT_CS3HD_OFS            0x43c
+#define GT_BOOTLD_OFS           0x440
+#define GT_BOOTHD_OFS           0x444
+
+#define GT_ADERR_OFS            0x470
+
+/* SDRAM Configuration.  */
+#define GT_SDRAM_CFG_OFS        0x448
+
+#define GT_SDRAM_OPMODE_OFS     0x474
+#define GT_SDRAM_BM_OFS         0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS         0x44c
+#define GT_SDRAM_B1_OFS         0x450
+#define GT_SDRAM_B2_OFS         0x454
+#define GT_SDRAM_B3_OFS         0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS           0x45c
+#define GT_DEV_B1_OFS           0x460
+#define GT_DEV_B2_OFS           0x464
+#define GT_DEV_B3_OFS           0x468
+#define GT_DEV_BOOT_OFS         0x46c
+
+/* ECC.  */
+#define GT_ECC_ERRDATALO        0x480                   /* GT-64120A only  */
+#define GT_ECC_ERRDATAHI        0x484                   /* GT-64120A only  */
+#define GT_ECC_MEM              0x488                   /* GT-64120A only  */
+#define GT_ECC_CALC             0x48c                   /* GT-64120A only  */
+#define GT_ECC_ERRADDR          0x490                   /* GT-64120A only  */
+
+/* DMA Record.  */
+#define GT_DMA0_CNT_OFS         0x800
+#define GT_DMA1_CNT_OFS         0x804
+#define GT_DMA2_CNT_OFS         0x808
+#define GT_DMA3_CNT_OFS         0x80c
+#define GT_DMA0_SA_OFS          0x810
+#define GT_DMA1_SA_OFS          0x814
+#define GT_DMA2_SA_OFS          0x818
+#define GT_DMA3_SA_OFS          0x81c
+#define GT_DMA0_DA_OFS          0x820
+#define GT_DMA1_DA_OFS          0x824
+#define GT_DMA2_DA_OFS          0x828
+#define GT_DMA3_DA_OFS          0x82c
+#define GT_DMA0_NEXT_OFS        0x830
+#define GT_DMA1_NEXT_OFS        0x834
+#define GT_DMA2_NEXT_OFS        0x838
+#define GT_DMA3_NEXT_OFS        0x83c
+
+#define GT_DMA0_CUR_OFS         0x870
+#define GT_DMA1_CUR_OFS         0x874
+#define GT_DMA2_CUR_OFS         0x878
+#define GT_DMA3_CUR_OFS         0x87c
+
+/* DMA Channel Control.  */
+#define GT_DMA0_CTRL_OFS        0x840
+#define GT_DMA1_CTRL_OFS        0x844
+#define GT_DMA2_CTRL_OFS        0x848
+#define GT_DMA3_CTRL_OFS        0x84c
+
+/* DMA Arbiter.  */
+#define GT_DMA_ARB_OFS          0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS              0x850
+#define GT_TC1_OFS              0x854
+#define GT_TC2_OFS              0x858
+#define GT_TC3_OFS              0x85c
+
+#define GT_TC_CONTROL_OFS       0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS         0xc00
+#define GT_PCI0_TOR_OFS         0xc04
+#define GT_PCI0_BS_SCS10_OFS    0xc08
+#define GT_PCI0_BS_SCS32_OFS    0xc0c
+#define GT_PCI0_BS_CS20_OFS     0xc10
+#define GT_PCI0_BS_CS3BT_OFS    0xc14
+
+#define GT_PCI1_IACK_OFS        0xc30
+#define GT_PCI0_IACK_OFS        0xc34
+
+#define GT_PCI0_BARE_OFS        0xc3c
+#define GT_PCI0_PREFMBR_OFS     0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS   0xc48
+#define GT_PCI0_SCS32_BAR_OFS   0xc4c
+#define GT_PCI0_CS20_BAR_OFS    0xc50
+#define GT_PCI0_CS3BT_BAR_OFS   0xc54
+#define GT_PCI0_SSCS10_BAR_OFS  0xc58
+#define GT_PCI0_SSCS32_BAR_OFS  0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS  0xc64
+
+#define GT_PCI1_CMD_OFS         0xc80
+#define GT_PCI1_TOR_OFS         0xc84
+#define GT_PCI1_BS_SCS10_OFS    0xc88
+#define GT_PCI1_BS_SCS32_OFS    0xc8c
+#define GT_PCI1_BS_CS20_OFS     0xc90
+#define GT_PCI1_BS_CS3BT_OFS    0xc94
+
+#define GT_PCI1_BARE_OFS        0xcbc
+#define GT_PCI1_PREFMBR_OFS     0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS   0xcc8
+#define GT_PCI1_SCS32_BAR_OFS   0xccc
+#define GT_PCI1_CS20_BAR_OFS    0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS   0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS  0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS  0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS  0xce4
+
+#define GT_PCI1_CFGADDR_OFS     0xcf0
+#define GT_PCI1_CFGDATA_OFS     0xcf4
+#define GT_PCI0_CFGADDR_OFS     0xcf8
+#define GT_PCI0_CFGDATA_OFS     0xcfc
+
+/* Interrupts.  */
+#define GT_INTRCAUSE_OFS        0xc18
+#define GT_INTRMASK_OFS         0xc1c
+
+#define GT_PCI0_ICMASK_OFS      0xc24
+#define GT_PCI0_SERR0MASK_OFS   0xc28
+
+#define GT_CPU_INTSEL_OFS       0xc70
+#define GT_PCI0_INTSEL_OFS      0xc74
+
+#define GT_HINTRCAUSE_OFS       0xc98
+#define GT_HINTRMASK_OFS        0xc9c
+
+#define GT_PCI0_HICMASK_OFS     0xca4
+#define GT_PCI1_SERR1MASK_OFS   0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE              0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE              0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE             0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE             0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE              0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE       0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE        0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE             0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE      0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE       0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE    0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE                 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE            0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE     0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE     0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE     0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE     0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE    0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE    0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE    0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE    0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE              0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE              0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE             0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE             0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE              0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE       0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE        0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE             0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE      0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE       0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE    0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE                 0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE            0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF       12
+#define GT_CPU_ENDIAN_MSK       (MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT       GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF           16
+#define GT_CPU_WR_MSK           (MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT           GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX      0
+#define GT_CPU_WR_DDDD          1
+
+
+#define GT_PCI_DCRM_SHF         21
+#define GT_PCI_LD_SHF           0
+#define GT_PCI_LD_MSK           (MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF           0
+#define GT_PCI_HD_MSK           (MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF        0
+#define GT_PCI_REMAP_MSK        (MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF    31
+#define GT_CFGADDR_CFGEN_MSK    (MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT    GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF   16
+#define GT_CFGADDR_BUSNUM_MSK   (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF   11
+#define GT_CFGADDR_DEVNUM_MSK   (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF  8
+#define GT_CFGADDR_FUNCNUM_MSK  (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF   2
+#define GT_CFGADDR_REGNUM_MSK   (MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF   2
+#define GT_SDRAM_BM_ORDER_MSK   (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT   GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB   1
+#define GT_SDRAM_BM_ORDER_LIN   0
+
+#define GT_SDRAM_BM_RSVD_ALL1   0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF    0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK    (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0      0
+#define GT_SDRAM_ADDRDECODE_ADDR_1      1
+#define GT_SDRAM_ADDRDECODE_ADDR_2      2
+#define GT_SDRAM_ADDRDECODE_ADDR_3      3
+#define GT_SDRAM_ADDRDECODE_ADDR_4      4
+#define GT_SDRAM_ADDRDECODE_ADDR_5      5
+#define GT_SDRAM_ADDRDECODE_ADDR_6      6
+#define GT_SDRAM_ADDRDECODE_ADDR_7      7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF          0
+#define GT_SDRAM_B0_CASLAT_MSK          (MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2            1
+#define GT_SDRAM_B0_CASLAT_3            2
+
+#define GT_SDRAM_B0_FTDIS_SHF           2
+#define GT_SDRAM_B0_FTDIS_MSK           (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT           GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF       3
+#define GT_SDRAM_B0_SRASPRCHG_MSK       (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT       GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2         0
+#define GT_SDRAM_B0_SRASPRCHG_3         1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF        4
+#define GT_SDRAM_B0_B0COMPAB_MSK        (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT        GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF        5
+#define GT_SDRAM_B0_64BITINT_MSK        (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT        GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2          0
+#define GT_SDRAM_B0_64BITINT_4          1
+
+#define GT_SDRAM_B0_BW_SHF              6
+#define GT_SDRAM_B0_BW_MSK              (MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT              GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32               0
+#define GT_SDRAM_B0_BW_64               1
+
+#define GT_SDRAM_B0_BLODD_SHF           7
+#define GT_SDRAM_B0_BLODD_MSK           (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT           GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF             8
+#define GT_SDRAM_B0_PAR_MSK             (MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT             GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF          9
+#define GT_SDRAM_B0_BYPASS_MSK          (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT          GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF       10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK       (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT       GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2         0
+#define GT_SDRAM_B0_SRAS2SCAS_3         1
+
+#define GT_SDRAM_B0_SIZE_SHF            11
+#define GT_SDRAM_B0_SIZE_MSK            (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT            GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M            0
+#define GT_SDRAM_B0_SIZE_64M            1
+
+#define GT_SDRAM_B0_EXTPAR_SHF          12
+#define GT_SDRAM_B0_EXTPAR_MSK          (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT          GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF            13
+#define GT_SDRAM_B0_BLEN_MSK            (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT            GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8              0
+#define GT_SDRAM_B0_BLEN_4              1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF         0
+#define GT_SDRAM_CFG_REFINT_MSK         (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF    14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK    (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT    GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF            15
+#define GT_SDRAM_CFG_RMW_MSK            (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT            GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF     16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK     (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT     GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF        19
+#define GT_SDRAM_CFG_DUPCNTL_MSK        (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT        GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF          20
+#define GT_SDRAM_CFG_DUPBA_MSK          (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT          GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF        21
+#define GT_SDRAM_CFG_DUPEOT0_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT        GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF        22
+#define GT_SDRAM_CFG_DUPEOT1_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT        GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF          0
+#define GT_SDRAM_OPMODE_OP_MSK          (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL       0
+#define GT_SDRAM_OPMODE_OP_NOP          1
+#define GT_SDRAM_OPMODE_OP_PRCHG        2
+#define GT_SDRAM_OPMODE_OP_MODE         3
+#define GT_SDRAM_OPMODE_OP_CBR          4
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF  0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK  (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT  GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF     1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT     GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF     2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT     GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF       3
+#define GT_PCI0_BARE_INTIODIS_MSK       (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT       GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF      4
+#define GT_PCI0_BARE_INTMEMDIS_MSK      (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT      GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF     5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK     (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT     GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF        6
+#define GT_PCI0_BARE_CS20DIS_MSK        (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT        GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF       7
+#define GT_PCI0_BARE_SCS32DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT       GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF       8
+#define GT_PCI0_BARE_SCS10DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT       GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF      18
+#define GT_INTRCAUSE_MASABORT0_MSK      (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT      GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF      19
+#define GT_INTRCAUSE_TARABORT0_MSK      (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT      GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF      2
+#define GT_PCI0_CFGADDR_REGNUM_MSK      (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF    8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF      11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK      (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF      16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK      (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF    31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK    (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT    GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF       0
+#define GT_PCI0_CMD_MBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT       GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF       10
+#define GT_PCI0_CMD_MWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT       GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF       16
+#define GT_PCI0_CMD_SBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT       GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF       11
+#define GT_PCI0_CMD_SWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT       GT_PCI0_CMD_SWORDSWAP_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE     0x10000000UL
+#define GT_DEF_PCI0_IO_SIZE     0x02000000UL
+#define GT_DEF_PCI0_MEM0_BASE   0x12000000UL
+#define GT_DEF_PCI0_MEM0_SIZE   0x02000000UL
+#define GT_DEF_BASE             0x14000000UL
+
+#define GT_MAX_BANKSIZE         (256 * 1024 * 1024)     /* Max 256MB bank  */
+#define GT_LATTIM_MIN           6                       /* Minimum lat  */
+
+/*
+ * The gt64120_dep.h file must define the following macros
+ *
+ *   GT_READ(ofs, data_pointer)
+ *   GT_WRITE(ofs, data)           - read/write GT64120 registers in 32bit
+ *
+ *   TIMER      - gt64120 timer irq, temporary solution until
+ *                full gt64120 cascade interrupt support is in place
+ */
+
+#include <mach-gt64120.h>
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.  We also provide non-swapping versions.
+ */
+#define __GT_READ(ofs)                                                  \
+        (*(volatile u32 *)(GT64120_BASE+(ofs)))
+#define __GT_WRITE(ofs, data)                                           \
+        do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+#define GT_READ(ofs)            le32_to_cpu(__GT_READ(ofs))
+#define GT_WRITE(ofs, data)     __GT_WRITE(ofs, cpu_to_le32(data))
+
+#endif /* _ASM_GT64120_H */
diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h
new file mode 100644
index 000000000000..8f9bd341ed49
--- /dev/null
+++ b/include/asm-mips/gt64240.h
@@ -0,0 +1,1235 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright - Galileo technology.
+ * Copyright (C) 2004 by Ralf Baechle
+ */
+#ifndef __ASM_MIPS_MV64240_H
+#define __ASM_MIPS_MV64240_H
+
+#include <asm/addrspace.h>
+#include <asm/marvell.h>
+
+/*
+ * CPU Control Registers
+ */
+
+#define CPU_CONFIGURATION                                       0x000
+#define CPU_MODE                                                0x120
+#define CPU_READ_RESPONSE_CROSSBAR_LOW                          0x170
+#define CPU_READ_RESPONSE_CROSSBAR_HIGH                         0x178
+
+/*
+ * Processor Address Space
+ */
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS                                0x008
+#define SCS_0_HIGH_DECODE_ADDRESS                               0x010
+#define SCS_1_LOW_DECODE_ADDRESS                                0x208
+#define SCS_1_HIGH_DECODE_ADDRESS                               0x210
+#define SCS_2_LOW_DECODE_ADDRESS                                0x018
+#define SCS_2_HIGH_DECODE_ADDRESS                               0x020
+#define SCS_3_LOW_DECODE_ADDRESS                                0x218
+#define SCS_3_HIGH_DECODE_ADDRESS                               0x220
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS                                 0x028
+#define CS_0_HIGH_DECODE_ADDRESS                                0x030
+#define CS_1_LOW_DECODE_ADDRESS                                 0x228
+#define CS_1_HIGH_DECODE_ADDRESS                                0x230
+#define CS_2_LOW_DECODE_ADDRESS                                 0x248
+#define CS_2_HIGH_DECODE_ADDRESS                                0x250
+#define CS_3_LOW_DECODE_ADDRESS                                 0x038
+#define CS_3_HIGH_DECODE_ADDRESS                                0x040
+#define BOOTCS_LOW_DECODE_ADDRESS                               0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS                              0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS                             0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS                            0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS                         0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS                        0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS                         0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS                        0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS                         0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS                        0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS                         0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS                        0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS                             0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS                            0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS                         0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS                        0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS                         0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS                        0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS                         0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS                        0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS                         0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS                        0x2b8
+
+#define INTERNAL_SPACE_DECODE                                   0x068
+
+#define CPU_0_LOW_DECODE_ADDRESS                                0x290
+#define CPU_0_HIGH_DECODE_ADDRESS                               0x298
+#define CPU_1_LOW_DECODE_ADDRESS                                0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS                               0x2c8
+
+#define PCI_0I_O_ADDRESS_REMAP                                  0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP                              0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP                         0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP                              0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP                         0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP                              0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP                         0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP                              0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP                         0x338
+
+#define PCI_1I_O_ADDRESS_REMAP                                  0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP                              0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP                         0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP                              0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP                         0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP                              0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP                         0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP                              0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP                         0x358
+
+/*
+ * CPU Sync Barrier
+ */
+
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER                       0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER                       0x0c8
+
+
+/*
+ * CPU Access Protect
+ */
+
+#define CPU_LOW_PROTECT_ADDRESS_0                               0X180
+#define CPU_HIGH_PROTECT_ADDRESS_0                              0X188
+#define CPU_LOW_PROTECT_ADDRESS_1                               0X190
+#define CPU_HIGH_PROTECT_ADDRESS_1                              0X198
+#define CPU_LOW_PROTECT_ADDRESS_2                               0X1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2                              0X1a8
+#define CPU_LOW_PROTECT_ADDRESS_3                               0X1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3                              0X1b8
+#define CPU_LOW_PROTECT_ADDRESS_4                               0X1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4                              0X1c8
+#define CPU_LOW_PROTECT_ADDRESS_5                               0X1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5                              0X1d8
+#define CPU_LOW_PROTECT_ADDRESS_6                               0X1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6                              0X1e8
+#define CPU_LOW_PROTECT_ADDRESS_7                               0X1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7                              0X1f8
+
+
+/*
+ * Snoop Control
+ */
+
+#define SNOOP_BASE_ADDRESS_0                                    0x380
+#define SNOOP_TOP_ADDRESS_0                                     0x388
+#define SNOOP_BASE_ADDRESS_1                                    0x390
+#define SNOOP_TOP_ADDRESS_1                                     0x398
+#define SNOOP_BASE_ADDRESS_2                                    0x3a0
+#define SNOOP_TOP_ADDRESS_2                                     0x3a8
+#define SNOOP_BASE_ADDRESS_3                                    0x3b0
+#define SNOOP_TOP_ADDRESS_3                                     0x3b8
+
+/*
+ * CPU Error Report
+ */
+
+#define CPU_ERROR_ADDRESS_LOW                                   0x070
+#define CPU_ERROR_ADDRESS_HIGH                                  0x078
+#define CPU_ERROR_DATA_LOW                                      0x128
+#define CPU_ERROR_DATA_HIGH                                     0x130
+#define CPU_ERROR_PARITY                                        0x138
+#define CPU_ERROR_CAUSE                                         0x140
+#define CPU_ERROR_MASK                                          0x148
+
+/*
+ * Pslave Debug
+ */
+
+#define X_0_ADDRESS                                             0x360
+#define X_0_COMMAND_ID                                          0x368
+#define X_1_ADDRESS                                             0x370
+#define X_1_COMMAND_ID                                          0x378
+#define WRITE_DATA_LOW                                          0x3c0
+#define WRITE_DATA_HIGH                                         0x3c8
+#define WRITE_BYTE_ENABLE                                       0X3e0
+#define READ_DATA_LOW                                           0x3d0
+#define READ_DATA_HIGH                                          0x3d8
+#define READ_ID                                                 0x3e8
+
+
+/*
+ * SDRAM and Device Address Space
+ */
+
+
+/*
+ * SDRAM Configuration
+ */
+
+#define SDRAM_CONFIGURATION                                     0x448
+#define SDRAM_OPERATION_MODE                                    0x474
+#define SDRAM_ADDRESS_DECODE                                    0x47C
+#define SDRAM_TIMING_PARAMETERS                                 0x4b4
+#define SDRAM_UMA_CONTROL                                       0x4a4
+#define SDRAM_CROSS_BAR_CONTROL_LOW                             0x4a8
+#define SDRAM_CROSS_BAR_CONTROL_HIGH                            0x4ac
+#define SDRAM_CROSS_BAR_TIMEOUT                                 0x4b0
+
+
+/*
+ * SDRAM Parameters
+ */
+
+#define SDRAM_BANK0PARAMETERS                                   0x44C
+#define SDRAM_BANK1PARAMETERS                                   0x450
+#define SDRAM_BANK2PARAMETERS                                   0x454
+#define SDRAM_BANK3PARAMETERS                                   0x458
+
+
+/*
+ * SDRAM Error Report
+ */
+
+#define SDRAM_ERROR_DATA_LOW                                    0x484
+#define SDRAM_ERROR_DATA_HIGH                                   0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS                          0x490
+#define SDRAM_RECEIVED_ECC                                      0x488
+#define SDRAM_CALCULATED_ECC                                    0x48c
+#define SDRAM_ECC_CONTROL                                       0x494
+#define SDRAM_ECC_ERROR_COUNTER                                 0x498
+
+
+/*
+ * SDunit Debug (for internal use)
+ */
+
+#define X0_ADDRESS                                              0x500
+#define X0_COMMAND_AND_ID                                       0x504
+#define X0_WRITE_DATA_LOW                                       0x508
+#define X0_WRITE_DATA_HIGH                                      0x50c
+#define X0_WRITE_BYTE_ENABLE                                    0x518
+#define X0_READ_DATA_LOW                                        0x510
+#define X0_READ_DATA_HIGH                                       0x514
+#define X0_READ_ID                                              0x51c
+#define X1_ADDRESS                                              0x520
+#define X1_COMMAND_AND_ID                                       0x524
+#define X1_WRITE_DATA_LOW                                       0x528
+#define X1_WRITE_DATA_HIGH                                      0x52c
+#define X1_WRITE_BYTE_ENABLE                                    0x538
+#define X1_READ_DATA_LOW                                        0x530
+#define X1_READ_DATA_HIGH                                       0x534
+#define X1_READ_ID                                              0x53c
+#define X0_SNOOP_ADDRESS                                        0x540
+#define X0_SNOOP_COMMAND                                        0x544
+#define X1_SNOOP_ADDRESS                                        0x548
+#define X1_SNOOP_COMMAND                                        0x54c
+
+
+/*
+ * Device Parameters
+ */
+
+#define DEVICE_BANK0PARAMETERS                                  0x45c
+#define DEVICE_BANK1PARAMETERS                                  0x460
+#define DEVICE_BANK2PARAMETERS                                  0x464
+#define DEVICE_BANK3PARAMETERS                                  0x468
+#define DEVICE_BOOT_BANK_PARAMETERS                             0x46c
+#define DEVICE_CONTROL                                          0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW                            0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH                           0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT                                0x4c4
+
+
+/*
+ * Device Interrupt
+ */
+
+#define DEVICE_INTERRUPT_CAUSE                                  0x4d0
+#define DEVICE_INTERRUPT_MASK                                   0x4d4
+#define DEVICE_ERROR_ADDRESS                                    0x4d8
+
+/*
+ * DMA Record
+ */
+
+#define CHANNEL0_DMA_BYTE_COUNT                                 0x800
+#define CHANNEL1_DMA_BYTE_COUNT                                 0x804
+#define CHANNEL2_DMA_BYTE_COUNT                                 0x808
+#define CHANNEL3_DMA_BYTE_COUNT                                 0x80C
+#define CHANNEL4_DMA_BYTE_COUNT                                 0x900
+#define CHANNEL5_DMA_BYTE_COUNT                                 0x904
+#define CHANNEL6_DMA_BYTE_COUNT                                 0x908
+#define CHANNEL7_DMA_BYTE_COUNT                                 0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS                             0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS                             0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS                             0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS                             0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS                             0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS                             0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS                             0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS                             0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS                        0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS                        0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS                        0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS                        0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS                        0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS                        0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS                        0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS                        0x92C
+#define CHANNEL0NEXT_RECORD_POINTER                             0x830
+#define CHANNEL1NEXT_RECORD_POINTER                             0x834
+#define CHANNEL2NEXT_RECORD_POINTER                             0x838
+#define CHANNEL3NEXT_RECORD_POINTER                             0x83C
+#define CHANNEL4NEXT_RECORD_POINTER                             0x930
+#define CHANNEL5NEXT_RECORD_POINTER                             0x934
+#define CHANNEL6NEXT_RECORD_POINTER                             0x938
+#define CHANNEL7NEXT_RECORD_POINTER                             0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER                      0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER                      0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER                      0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER                      0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER                      0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER                      0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER                      0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER                      0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS                    0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS               0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS       0x9bc
+
+/*
+ * DMA Channel Control
+ */
+
+#define CHANNEL0CONTROL                                         0x840
+#define CHANNEL0CONTROL_HIGH                                    0x880
+
+#define CHANNEL1CONTROL                                         0x844
+#define CHANNEL1CONTROL_HIGH                                    0x884
+
+#define CHANNEL2CONTROL                                         0x848
+#define CHANNEL2CONTROL_HIGH                                    0x888
+
+#define CHANNEL3CONTROL                                         0x84C
+#define CHANNEL3CONTROL_HIGH                                    0x88C
+
+#define CHANNEL4CONTROL                                         0x940
+#define CHANNEL4CONTROL_HIGH                                    0x980
+
+#define CHANNEL5CONTROL                                         0x944
+#define CHANNEL5CONTROL_HIGH                                    0x984
+
+#define CHANNEL6CONTROL                                         0x948
+#define CHANNEL6CONTROL_HIGH                                    0x988
+
+#define CHANNEL7CONTROL                                         0x94C
+#define CHANNEL7CONTROL_HIGH                                    0x98C
+
+
+/*
+ * DMA Arbiter
+ */
+
+#define ARBITER_CONTROL_0_3                                     0x860
+#define ARBITER_CONTROL_4_7                                     0x960
+
+
+/*
+ * DMA Interrupt
+ */
+
+#define CHANELS0_3_INTERRUPT_CAUSE                              0x8c0
+#define CHANELS0_3_INTERRUPT_MASK                               0x8c4
+#define CHANELS0_3_ERROR_ADDRESS                                0x8c8
+#define CHANELS0_3_ERROR_SELECT                                 0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE                              0x9c0
+#define CHANELS4_7_INTERRUPT_MASK                               0x9c4
+#define CHANELS4_7_ERROR_ADDRESS                                0x9c8
+#define CHANELS4_7_ERROR_SELECT                                 0x9cc
+
+
+/*
+ * DMA Debug (for internal use)
+ */
+
+#define DMA_X0_ADDRESS                                          0x8e0
+#define DMA_X0_COMMAND_AND_ID                                   0x8e4
+#define DMA_X0_WRITE_DATA_LOW                                   0x8e8
+#define DMA_X0_WRITE_DATA_HIGH                                  0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE                                0x8f8
+#define DMA_X0_READ_DATA_LOW                                    0x8f0
+#define DMA_X0_READ_DATA_HIGH                                   0x8f4
+#define DMA_X0_READ_ID                                          0x8fc
+#define DMA_X1_ADDRESS                                          0x9e0
+#define DMA_X1_COMMAND_AND_ID                                   0x9e4
+#define DMA_X1_WRITE_DATA_LOW                                   0x9e8
+#define DMA_X1_WRITE_DATA_HIGH                                  0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE                                0x9f8
+#define DMA_X1_READ_DATA_LOW                                    0x9f0
+#define DMA_X1_READ_DATA_HIGH                                   0x9f4
+#define DMA_X1_READ_ID                                          0x9fc
+
+/*
+ * Timer_Counter
+ */
+
+#define TIMER_COUNTER0                                          0x850
+#define TIMER_COUNTER1                                          0x854
+#define TIMER_COUNTER2                                          0x858
+#define TIMER_COUNTER3                                          0x85C
+#define TIMER_COUNTER_0_3_CONTROL                               0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE                       0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK                        0x86c
+#define TIMER_COUNTER4                                          0x950
+#define TIMER_COUNTER5                                          0x954
+#define TIMER_COUNTER6                                          0x958
+#define TIMER_COUNTER7                                          0x95C
+#define TIMER_COUNTER_4_7_CONTROL                               0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE                       0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK                        0x96c
+
+/*
+ * PCI Slave Address Decoding
+ */
+
+#define PCI_0SCS_0_BANK_SIZE                                    0xc08
+#define PCI_1SCS_0_BANK_SIZE                                    0xc88
+#define PCI_0SCS_1_BANK_SIZE                                    0xd08
+#define PCI_1SCS_1_BANK_SIZE                                    0xd88
+#define PCI_0SCS_2_BANK_SIZE                                    0xc0c
+#define PCI_1SCS_2_BANK_SIZE                                    0xc8c
+#define PCI_0SCS_3_BANK_SIZE                                    0xd0c
+#define PCI_1SCS_3_BANK_SIZE                                    0xd8c
+#define PCI_0CS_0_BANK_SIZE                                     0xc10
+#define PCI_1CS_0_BANK_SIZE                                     0xc90
+#define PCI_0CS_1_BANK_SIZE                                     0xd10
+#define PCI_1CS_1_BANK_SIZE                                     0xd90
+#define PCI_0CS_2_BANK_SIZE                                     0xd18
+#define PCI_1CS_2_BANK_SIZE                                     0xd98
+#define PCI_0CS_3_BANK_SIZE                                     0xc14
+#define PCI_1CS_3_BANK_SIZE                                     0xc94
+#define PCI_0CS_BOOT_BANK_SIZE                                  0xd14
+#define PCI_1CS_BOOT_BANK_SIZE                                  0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE                                  0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE                                  0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE                                  0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE                                  0xda0
+#define PCI_0P2P_I_O_BAR_SIZE                                   0xd24
+#define PCI_1P2P_I_O_BAR_SIZE                                   0xda4
+#define PCI_0CPU_BAR_SIZE                                       0xd28
+#define PCI_1CPU_BAR_SIZE                                       0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE                                0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE                                0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE                                0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE                                0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE                                0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE                                0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE                                0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE                                0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE                                 0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE                                 0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE                                 0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE                                 0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE                                 0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE                                 0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE                                 0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE                                 0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE                               0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE                               0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE                              0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE                              0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE                              0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE                              0xea8
+#define PCI_0DAC_CPU_BAR_SIZE                                   0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE                                   0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE                             0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE                             0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE                      0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE                      0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP                           0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP                           0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP                           0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP                           0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP                           0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP                           0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP                           0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP                           0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP                            0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP                            0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP                            0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP                            0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP                            0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP                            0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP                            0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP                            0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP                       0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP                       0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW                    0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW                    0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH                   0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH                   0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW                    0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW                    0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH                   0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH                   0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                         0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                         0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP                             0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP                             0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP                       0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP                       0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP                       0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP                       0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP                       0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP                       0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP                       0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP                       0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP                        0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP                        0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP                        0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP                        0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP                        0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP                        0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP                        0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP                        0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP                      0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP                      0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP                         0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP                         0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP                   0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP                   0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL                             0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL                             0xdbc
+
+/*
+ * PCI Control
+ */
+
+#define PCI_0COMMAND                                            0xc00
+#define PCI_1COMMAND                                            0xc80
+#define PCI_0MODE                                               0xd00
+#define PCI_1MODE                                               0xd80
+#define PCI_0TIMEOUT_RETRY                                      0xc04
+#define PCI_1TIMEOUT_RETRY                                      0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER                          0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER                          0xd84
+#define MSI_0TRIGGER_TIMER                                      0xc38
+#define MSI_1TRIGGER_TIMER                                      0xcb8
+#define PCI_0ARBITER_CONTROL                                    0x1d00
+#define PCI_1ARBITER_CONTROL                                    0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW                               0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH                              0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT                                   0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW                 0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH                0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                       0x1d10
+#define PCI_0P2P_CONFIGURATION                                   0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW                           0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                          0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0                                0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW                           0c1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                          0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1                                0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW                           0c1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                          0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2                                0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW                           0c1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                          0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3                                0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW                           0c1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                          0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4                                0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW                           0c1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                          0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5                                0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW                           0c1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                          0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6                                0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW                           0c1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                          0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7                                0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW                               0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH                              0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT                                   0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW                 0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH                0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                       0x1d90
+#define PCI_1P2P_CONFIGURATION                                   0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW                           0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                          0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0                                0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW                           0c1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                          0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1                                0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW                           0c1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                          0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2                                0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW                           0c1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                          0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3                                0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW                           0c1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                          0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4                                0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW                           0c1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                          0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5                                0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW                           0c1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                          0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6                                0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW                           0c1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                          0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7                                0x1ef8
+
+/*
+ * PCI Snoop Control
+ */
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW                            0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                           0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0                                 0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                          0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                         0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1                                 0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                          0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                         0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2                                 0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                          0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                         0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3                                 0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW                            0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                           0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0                                 0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                          0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                         0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1                                 0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                          0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                         0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2                                 0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                          0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                         0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3                                 0x1fb8
+
+/*
+ * PCI Configuration Address
+ */
+
+#define PCI_0CONFIGURATION_ADDRESS                              0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER                0xcfc
+#define PCI_1CONFIGURATION_ADDRESS                              0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER                0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER             0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER             0xcb4
+
+/*
+ * PCI Error Report
+ */
+
+#define PCI_0SERR_MASK                                           0xc28
+#define PCI_0ERROR_ADDRESS_LOW                                   0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH                                  0x1d44
+#define PCI_0ERROR_DATA_LOW                                      0x1d48
+#define PCI_0ERROR_DATA_HIGH                                     0x1d4c
+#define PCI_0ERROR_COMMAND                                       0x1d50
+#define PCI_0ERROR_CAUSE                                         0x1d58
+#define PCI_0ERROR_MASK                                          0x1d5c
+
+#define PCI_1SERR_MASK                                           0xca8
+#define PCI_1ERROR_ADDRESS_LOW                                   0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH                                  0x1dc4
+#define PCI_1ERROR_DATA_LOW                                      0x1dc8
+#define PCI_1ERROR_DATA_HIGH                                     0x1dcc
+#define PCI_1ERROR_COMMAND                                       0x1dd0
+#define PCI_1ERROR_CAUSE                                         0x1dd8
+#define PCI_1ERROR_MASK                                          0x1ddc
+
+
+/*
+ * Lslave Debug  (for internal use)
+ */
+
+#define L_SLAVE_X0_ADDRESS                                      0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID                               0x1d24
+#define L_SLAVE_X1_ADDRESS                                      0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID                               0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW                                  0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH                                 0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE                               0x1d60
+#define L_SLAVE_READ_DATA_LOW                                   0x1d38
+#define L_SLAVE_READ_DATA_HIGH                                  0x1d3c
+#define L_SLAVE_READ_ID                                         0x1d64
+
+#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */
+
+/*
+ * PCI Configuration Function 0
+ */
+
+#define PCI_DEVICE_AND_VENDOR_ID                                0x000
+#define PCI_STATUS_AND_COMMAND                                  0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID                          0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE           0x00C
+#define PCI_SCS_0_BASE_ADDRESS                                  0x010
+#define PCI_SCS_1_BASE_ADDRESS                                  0x014
+#define PCI_SCS_2_BASE_ADDRESS                                  0x018
+#define PCI_SCS_3_BASE_ADDRESS                                  0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS       0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS           0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID                0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER                 0x030
+#define PCI_CAPABILTY_LIST_POINTER                              0x034
+#define PCI_INTERRUPT_PIN_AND_LINE                              0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY                         0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL                 0x044
+#define PCI_VPD_ADDRESS                                         0x048
+#define PCI_VPD_DATA                                            0X04c
+#define PCI_MSI_MESSAGE_CONTROL                                 0x050
+#define PCI_MSI_MESSAGE_ADDRESS                                 0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS                           0x058
+#define PCI_MSI_MESSAGE_DATA                                    0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                     0x058
+
+/*
+ * PCI Configuration Function 1
+ */
+
+#define PCI_CS_0_BASE_ADDRESS                                   0x110
+#define PCI_CS_1_BASE_ADDRESS                                   0x114
+#define PCI_CS_2_BASE_ADDRESS                                   0x118
+#define PCI_CS_3_BASE_ADDRESS                                   0x11c
+#define PCI_BOOTCS_BASE_ADDRESS                                 0x120
+
+/*
+ * PCI Configuration Function 2
+ */
+
+#define PCI_P2P_MEM0_BASE_ADDRESS                               0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS                               0x214
+#define PCI_P2P_I_O_BASE_ADDRESS                                0x218
+#define PCI_CPU_BASE_ADDRESS                                    0x21c
+
+/*
+ * PCI Configuration Function 4
+ */
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW                          0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH                         0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW                          0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH                         0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW                       0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH                      0x424
+
+
+/*
+ * PCI Configuration Function 5
+ */
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW                          0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH                         0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW                          0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH                         0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW                       0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH                      0x524
+
+
+/*
+ * PCI Configuration Function 6
+ */
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW                           0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH                          0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW                           0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH                          0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW                           0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH                          0x624
+
+/*
+ * PCI Configuration Function 7
+ */
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW                           0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH                          0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW                         0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH                        0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW                            0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH                           0x724
+#endif
+
+/*
+ * Interrupts
+ */
+
+#define LOW_INTERRUPT_CAUSE_REGISTER                            0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER                           0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW                         0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH                        0xc6c
+#define CPU_SELECT_CAUSE_REGISTER                               0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW                  0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH                 0xc64
+#define PCI_0SELECT_CAUSE                                       0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW                  0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH                 0xce4
+#define PCI_1SELECT_CAUSE                                       0xcf4
+#define CPU_INT_0_MASK                                          0xe60
+#define CPU_INT_1_MASK                                          0xe64
+#define CPU_INT_2_MASK                                          0xe68
+#define CPU_INT_3_MASK                                          0xe6c
+
+/*
+ * I20 Support registers
+ */
+
+#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE                     0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE                     0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE                    0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE                    0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE                     0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE              0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE               0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE                    0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE             0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE              0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE           0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE          0x044
+#define QUEUE_CONTROL_REGISTER_PCI0_SIDE                        0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE                   0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE            0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE            0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE            0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE            0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE           0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE           0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE           0x0F8
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE           0x0FC
+
+#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE                     0x090
+#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE                     0x094
+#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE                    0x098
+#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE                    0x09C
+#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE                     0x0A0
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE              0x0A4
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE               0x0A8
+#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE                    0x0AC
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE             0x0B0
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE              0x0B4
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE           0x0C0
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE          0x0C4
+#define QUEUE_CONTROL_REGISTER_PCI1_SIDE                        0x0D0
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE                   0x0D4
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE            0x0E0
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE            0x0E4
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE            0x0E8
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE            0x0EC
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE           0x0F0
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE           0x0F4
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE           0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE           0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE                     0X1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE                     0X1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE                    0X1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE                    0X1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE                     0X1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE              0X1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE               0X1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE                    0X1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE             0X1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE              0X1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE           0X1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE          0X1C44
+#define QUEUE_CONTROL_REGISTER_CPU0_SIDE                        0X1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE                   0X1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE            0X1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE            0X1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE            0X1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE            0X1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE           0X1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE           0X1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE           0X1CF8
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE           0X1CFC
+
+#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE                     0X1C90
+#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE                     0X1C94
+#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE                    0X1C98
+#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE                    0X1C9C
+#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE                     0X1CA0
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE              0X1CA4
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE               0X1CA8
+#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE                    0X1CAC
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE             0X1CB0
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE              0X1CB4
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE           0X1CC0
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE          0X1CC4
+#define QUEUE_CONTROL_REGISTER_CPU1_SIDE                        0X1CD0
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE                   0X1CD4
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE            0X1CE0
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE            0X1CE4
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE            0X1CE8
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE            0X1CEC
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE           0X1CF0
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE           0X1CF4
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE           0X1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE           0X1C7C
+
+/*
+ * Communication Unit Registers
+ */
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH                         0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS                  0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW                          0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH                         0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS                  0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW                          0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH                         0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS                  0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW                              0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH                             0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS                  0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS                 0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS              0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS             0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW                              0xf2a0
+#define MPSC_1_ADDRESS_CONTROL_HIGH                             0xf2a4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS                  0xf2a8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS                 0xf2ac
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS              0xf2b0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS             0xf2b4
+#define MPSC_2_ADDRESS_CONTROL_LOW                              0xf2c0
+#define MPSC_2_ADDRESS_CONTROL_HIGH                             0xf2c4
+#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS                  0xf2c8
+#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS                 0xf2cc
+#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS              0xf2d0
+#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS             0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS                            0xf320
+#define SERIAL_INIT_LAST_DATA                                   0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL                          0xf328
+#define COMM_UNIT_ARBITER_CONTROL                               0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT                             0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE                               0xf310
+#define COMM_UNIT_INTERRUPT_MASK                                0xf314
+#define COMM_UNIT_ERROR_ADDRESS                                 0xf314
+
+/*
+ * Cunit Debug  (for internal use)
+ */
+
+#define CUNIT_ADDRESS                                           0xf340
+#define CUNIT_COMMAND_AND_ID                                    0xf344
+#define CUNIT_WRITE_DATA_LOW                                    0xf348
+#define CUNIT_WRITE_DATA_HIGH                                   0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE                                 0xf358
+#define CUNIT_READ_DATA_LOW                                     0xf350
+#define CUNIT_READ_DATA_HIGH                                    0xf354
+#define CUNIT_READ_ID                                           0xf35c
+
+/*
+ * Fast Ethernet Unit Registers
+ */
+
+/* Ethernet */
+
+#define ETHERNET_PHY_ADDRESS_REGISTER                           0x2000
+#define ETHERNET_SMI_REGISTER                                   0x2010
+
+/* Ethernet 0 */
+
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER                   0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER            0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER                         0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER                          0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER                     0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER                   0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER                   0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER                         0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER                      0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER                       0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0                  0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1                  0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2                  0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3                  0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0                0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1                0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2                0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3                0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0                0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1                0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE                              0x2500
+
+/* Ethernet 1 */
+
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER                   0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER            0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER                         0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER                          0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER                     0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER                   0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER                   0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER                         0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER                      0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER                       0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0                  0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1                  0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2                  0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3                  0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0                0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1                0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2                0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3                0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0                0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1                0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE                              0x2900
+
+/* Ethernet 2 */
+
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER                   0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER            0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER                         0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER                          0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER                     0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER                   0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW               0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH              0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER                   0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER                         0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER                      0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER                       0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0                  0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1                  0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2                  0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3                  0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0                0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1                0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2                0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3                0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0                0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1                0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE                              0x2d00
+
+/*
+ * SDMA Registers
+ */
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER                       0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER                         0x4000
+#define CHANNEL0_COMMAND_REGISTER                               0x4008
+#define CHANNEL0_RX_CMD_STATUS                                  0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES                     0x4804
+#define CHANNEL0_RX_BUFFER_POINTER                              0x4808
+#define CHANNEL0_RX_NEXT_POINTER                                0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER                  0x4810
+#define CHANNEL0_TX_CMD_STATUS                                  0x4C00
+#define CHANNEL0_TX_PACKET_SIZE                                 0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER                              0x4C08
+#define CHANNEL0_TX_NEXT_POINTER                                0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER                  0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER                    0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER                         0x6000
+#define CHANNEL1_COMMAND_REGISTER                               0x6008
+#define CHANNEL1_RX_CMD_STATUS                                  0x6800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES                     0x6804
+#define CHANNEL1_RX_BUFFER_POINTER                              0x6808
+#define CHANNEL1_RX_NEXT_POINTER                                0x680c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER                  0x6810
+#define CHANNEL1_TX_CMD_STATUS                                  0x6C00
+#define CHANNEL1_TX_PACKET_SIZE                                 0x6C04
+#define CHANNEL1_TX_BUFFER_POINTER                              0x6C08
+#define CHANNEL1_TX_NEXT_POINTER                                0x6C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER                  0x6810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER                  0x6c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER                    0x6c14
+
+/* SDMA Interrupt */
+
+#define SDMA_CAUSE                                              0xb820
+#define SDMA_MASK                                               0xb8a0
+
+
+/*
+ * Baude Rate Generators Registers
+ */
+
+/* BRG 0 */
+
+#define BRG0_CONFIGURATION_REGISTER                             0xb200
+#define BRG0_BAUDE_TUNING_REGISTER                              0xb204
+
+/* BRG 1 */
+
+#define BRG1_CONFIGURATION_REGISTER                             0xb208
+#define BRG1_BAUDE_TUNING_REGISTER                              0xb20c
+
+/* BRG 2 */
+
+#define BRG2_CONFIGURATION_REGISTER                             0xb210
+#define BRG2_BAUDE_TUNING_REGISTER                              0xb214
+
+/* BRG Interrupts */
+
+#define BRG_CAUSE_REGISTER                                      0xb834
+#define BRG_MASK_REGISTER                                       0xb8b4
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER                                   0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER                          0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER                         0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER                0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER                         0xb410
+#define WATCHDOG_VALUE_REGISTER                                 0xb414
+
+
+/*
+ * Flex TDM Registers
+ */
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER                           0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER                            0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER                          0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER                        0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER                        0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER                        0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER                        0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER                                     0xb830
+#define FTDM_MASK_REGISTER                                      0xb8b0
+
+
+/*
+ * GPP Interface Registers
+ */
+
+#define GPP_IO_CONTROL                                          0xf100
+#define GPP_LEVEL_CONTROL                                       0xf110
+#define GPP_VALUE                                               0xf104
+#define GPP_INTERRUPT_CAUSE                                     0xf108
+#define GPP_INTERRUPT_MASK                                      0xf10c
+
+#define MPP_CONTROL0                                            0xf000
+#define MPP_CONTROL1                                            0xf004
+#define MPP_CONTROL2                                            0xf008
+#define MPP_CONTROL3                                            0xf00c
+#define DEBUG_PORT_MULTIPLEX                                    0xf014
+#define SERIAL_PORT_MULTIPLEX                                   0xf010
+
+/*
+ * I2C Registers
+ */
+
+#define I2C_SLAVE_ADDRESS                                       0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS                              0xc040
+#define I2C_DATA                                                0xc004
+#define I2C_CONTROL                                             0xc008
+#define I2C_STATUS_BAUDE_RATE                                   0xc00C
+#define I2C_SOFT_RESET                                          0xc01c
+
+/*
+ * MPSC Registers
+ */
+
+/*
+ * MPSC0
+ */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW                            0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH                           0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION                            0x8008
+#define CHANNEL0_REGISTER1                                      0x800c
+#define CHANNEL0_REGISTER2                                      0x8010
+#define CHANNEL0_REGISTER3                                      0x8014
+#define CHANNEL0_REGISTER4                                      0x8018
+#define CHANNEL0_REGISTER5                                      0x801c
+#define CHANNEL0_REGISTER6                                      0x8020
+#define CHANNEL0_REGISTER7                                      0x8024
+#define CHANNEL0_REGISTER8                                      0x8028
+#define CHANNEL0_REGISTER9                                      0x802c
+#define CHANNEL0_REGISTER10                                     0x8030
+#define CHANNEL0_REGISTER11                                     0x8034
+
+/*
+ * MPSC1
+ */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW                            0x9000
+#define MPSC1_MAIN_CONFIGURATION_HIGH                           0x9004
+#define MPSC1_PROTOCOL_CONFIGURATION                            0x9008
+#define CHANNEL1_REGISTER1                                      0x900c
+#define CHANNEL1_REGISTER2                                      0x9010
+#define CHANNEL1_REGISTER3                                      0x9014
+#define CHANNEL1_REGISTER4                                      0x9018
+#define CHANNEL1_REGISTER5                                      0x901c
+#define CHANNEL1_REGISTER6                                      0x9020
+#define CHANNEL1_REGISTER7                                      0x9024
+#define CHANNEL1_REGISTER8                                      0x9028
+#define CHANNEL1_REGISTER9                                      0x902c
+#define CHANNEL1_REGISTER10                                     0x9030
+#define CHANNEL1_REGISTER11                                     0x9034
+
+/*
+ * MPSCs Interupts
+ */
+
+#define MPSC0_CAUSE                                             0xb804
+#define MPSC0_MASK                                              0xb884
+#define MPSC1_CAUSE                                             0xb80c
+#define MPSC1_MASK                                              0xb88c
+
+#endif  /* __ASM_MIPS_MV64240_H */
diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h
new file mode 100644
index 000000000000..90bf399e6dd9
--- /dev/null
+++ b/include/asm-mips/hardirq.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_HARDIRQ_H
+#define _ASM_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+extern void ack_bad_irq(unsigned int irq);
+
+#endif /* _ASM_HARDIRQ_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
new file mode 100644
index 000000000000..f524eaccd5f1
--- /dev/null
+++ b/include/asm-mips/hazards.h
@@ -0,0 +1,217 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef _ASM_HAZARDS_H
+#define _ASM_HAZARDS_H
+
+#include <linux/config.h>
+
+#ifdef __ASSEMBLY__
+
+        .macro  _ssnop
+        sll     $0, $0, 1
+        .endm
+
+        .macro  _ehb
+        sll     $0, $0, 3
+        .endm
+
+/*
+ * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
+ */
+#ifdef CONFIG_CPU_RM9000
+
+        .macro  mtc0_tlbw_hazard
+        .set    push
+        .set    mips32
+        _ssnop; _ssnop; _ssnop; _ssnop
+        .set    pop
+        .endm
+
+        .macro  tlbw_eret_hazard
+        .set    push
+        .set    mips32
+        _ssnop; _ssnop; _ssnop; _ssnop
+        .set    pop
+        .endm
+
+#else
+
+/*
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400.  Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.
+ */
+        .macro  mtc0_tlbw_hazard
+        b       . + 8
+        .endm
+
+        .macro  tlbw_eret_hazard
+        .endm
+#endif
+
+/*
+ * mtc0->mfc0 hazard
+ * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
+ * It is a MIPS32R2 processor so ehb will clear the hazard.
+ */
+
+#ifdef CONFIG_CPU_MIPSR2
+/*
+ * Use a macro for ehb unless explicit support for MIPSR2 is enabled
+ */
+
+#define irq_enable_hazard
+        _ehb
+
+#define irq_disable_hazard
+        _ehb
+
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+#define irq_enable_hazard
+
+#define irq_disable_hazard
+
+#else
+
+/*
+ * Classic MIPS needs 1 - 3 nops or ssnops
+ */
+#define irq_enable_hazard
+#define irq_disable_hazard                                              \
+        _ssnop; _ssnop; _ssnop
+
+#endif
+
+#else /* __ASSEMBLY__ */
+
+__asm__(
+        "       .macro  _ssnop                                  \n\t"
+        "       sll     $0, $2, 1                               \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro  _ehb                                    \n\t"
+        "       sll     $0, $0, 3                               \n\t"
+        "       .endm                                           \n\t");
+
+#ifdef CONFIG_CPU_RM9000
+/*
+ * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
+ */
+
+#define mtc0_tlbw_hazard()                                              \
+        __asm__ __volatile__(                                           \
+                ".set\tmips32\n\t"                                      \
+                "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
+                ".set\tmips0")
+
+#define tlbw_use_hazard()                                               \
+        __asm__ __volatile__(                                           \
+                ".set\tmips32\n\t"                                      \
+                "_ssnop; _ssnop; _ssnop; _ssnop\n\t"                    \
+                ".set\tmips0")
+#else
+
+/*
+ * Overkill warning ...
+ */
+#define mtc0_tlbw_hazard()                                              \
+        __asm__ __volatile__(                                           \
+                ".set noreorder\n\t"                                    \
+                "nop; nop; nop; nop; nop; nop;\n\t"                     \
+                ".set reorder\n\t")
+
+#define tlbw_use_hazard()                                               \
+        __asm__ __volatile__(                                           \
+                ".set noreorder\n\t"                                    \
+                "nop; nop; nop; nop; nop; nop;\n\t"                     \
+                ".set reorder\n\t")
+
+#endif
+
+/*
+ * mtc0->mfc0 hazard
+ * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
+ * It is a MIPS32R2 processor so ehb will clear the hazard.
+ */
+
+#ifdef CONFIG_CPU_MIPSR2
+/*
+ * Use a macro for ehb unless explicit support for MIPSR2 is enabled
+ */
+__asm__(
+        "       .macro\tirq_enable_hazard                       \n\t"
+        "       _ehb                                            \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tirq_disable_hazard                      \n\t"
+        "       _ehb                                            \n\t"
+        "       .endm");
+
+#define irq_enable_hazard()                                             \
+        __asm__ __volatile__(                                           \
+        "_ehb\t\t\t\t# irq_enable_hazard")
+
+#define irq_disable_hazard()                                            \
+        __asm__ __volatile__(                                           \
+        "_ehb\t\t\t\t# irq_disable_hazard")
+
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+__asm__(
+        "       .macro\tirq_enable_hazard                       \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tirq_disable_hazard                      \n\t"
+        "       .endm");
+
+#define irq_enable_hazard()     do { } while (0)
+#define irq_disable_hazard()    do { } while (0)
+
+#else
+
+/*
+ * Default for classic MIPS processors.  Assume worst case hazards but don't
+ * care about the irq_enable_hazard - sooner or later the hardware will
+ * enable it and we don't care when exactly.
+ */
+
+__asm__(
+        "       #                                               \n\t"
+        "       # There is a hazard but we do not care          \n\t"
+        "       #                                               \n\t"
+        "       .macro\tirq_enable_hazard                       \n\t"
+        "       .endm                                           \n\t"
+        "                                                       \n\t"
+        "       .macro\tirq_disable_hazard                      \n\t"
+        "       _ssnop; _ssnop; _ssnop                          \n\t"
+        "       .endm");
+
+#define irq_enable_hazard()     do { } while (0)
+#define irq_disable_hazard()                                            \
+        __asm__ __volatile__(                                           \
+        "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/hdreg.h b/include/asm-mips/hdreg.h
new file mode 100644
index 000000000000..5989bbc97cbf
--- /dev/null
+++ b/include/asm-mips/hdreg.h
@@ -0,0 +1 @@
+#warning this file is obsolete, please do not use it
diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h
new file mode 100644
index 000000000000..f49930d947d4
--- /dev/null
+++ b/include/asm-mips/highmem.h
@@ -0,0 +1,103 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/kmap_types.h>
+
+/* undef for production */
+#define HIGHMEM_DEBUG 1
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define PKMAP_BASE (0xfe000000UL)
+#define LAST_PKMAP 1024
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+extern void * kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+/*
+ * CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's
+ * Jaguar ATX.  This option exploits the highmem code in the kernel so is
+ * always enabled together with CONFIG_HIGHMEM but at this time doesn't
+ * actually add highmem functionality.
+ */
+
+#ifdef CONFIG_LIMITED_DMA
+
+/*
+ * These are the default functions for the no-highmem case from
+ * <linux/highmem.h>
+ */
+static inline void *kmap(struct page *page)
+{
+        might_sleep();
+        return page_address(page);
+}
+
+#define kunmap(page) do { (void) (page); } while (0)
+
+static inline void *kmap_atomic(struct page *page, enum km_type type)
+{
+        return page_address(page);
+}
+
+static inline void kunmap_atomic(void *kvaddr, enum km_type type) { }
+
+#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
+
+#define flush_cache_kmaps()     do { } while (0)
+
+#else /* LIMITED_DMA */
+
+extern void *__kmap(struct page *page);
+extern void __kunmap(struct page *page);
+extern void *__kmap_atomic(struct page *page, enum km_type type);
+extern void __kunmap_atomic(void *kvaddr, enum km_type type);
+extern struct page *__kmap_atomic_to_page(void *ptr);
+
+#define kmap                    __kmap
+#define kunmap                  __kunmap
+#define kmap_atomic             __kmap_atomic
+#define kunmap_atomic           __kunmap_atomic
+#define kmap_atomic_to_page     __kmap_atomic_to_page
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+#endif /* LIMITED_DMA */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-mips/hp-lj/asic.h b/include/asm-mips/hp-lj/asic.h
new file mode 100644
index 000000000000..fc2ca656da00
--- /dev/null
+++ b/include/asm-mips/hp-lj/asic.h
@@ -0,0 +1,7 @@
+
+typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId;
+
+AsicId GetAsicId(void);
+
+const char* const GetAsicName(void);
+
diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h
new file mode 100644
index 000000000000..c854d017c0e5
--- /dev/null
+++ b/include/asm-mips/hw_irq.h
@@ -0,0 +1,27 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2001, 2002 by Ralf Baechle
+ */
+#ifndef __ASM_HW_IRQ_H
+#define __ASM_HW_IRQ_H
+
+#include <linux/profile.h>
+#include <asm/atomic.h>
+
+extern void disable_8259A_irq(unsigned int irq);
+extern void enable_8259A_irq(unsigned int irq);
+extern int i8259A_irq_pending(unsigned int irq);
+extern void make_8259A_irq(unsigned int irq);
+extern void init_8259A(int aeoi);
+
+extern atomic_t irq_err_count;
+
+/* This may not be apropriate for all machines, we'll see ...  */
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
+{
+}
+
+#endif /* __ASM_HW_IRQ_H */
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
new file mode 100644
index 000000000000..0214abe3f0af
--- /dev/null
+++ b/include/asm-mips/i8259.h
@@ -0,0 +1,67 @@
+/*
+ *      include/asm-mips/i8259.h
+ *
+ *      i8259A interrupt definitions.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ *      Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_I8259_H
+#define _ASM_I8259_H
+
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+
+extern spinlock_t i8259A_lock;
+
+extern void init_i8259_irqs(void);
+
+/*
+ * Do the traditional i8259 interrupt polling thing.  This is for the few
+ * cases where no better interrupt acknowledge method is available and we
+ * absolutely must touch the i8259.
+ */
+static inline int i8259_irq(void)
+{
+        int irq;
+
+        spin_lock(&i8259A_lock);
+
+        /* Perform an interrupt acknowledge cycle on controller 1. */
+        outb(0x0C, 0x20);               /* prepare for poll */
+        irq = inb(0x20) & 7;
+        if (irq == 2) {
+                /*
+                 * Interrupt is cascaded so perform interrupt
+                 * acknowledge on controller 2.
+                 */
+                outb(0x0C, 0xA0);               /* prepare for poll */
+                irq = (inb(0xA0) & 7) + 8;
+        }
+
+        if (unlikely(irq == 7)) {
+                /*
+                 * This may be a spurious interrupt.
+                 *
+                 * Read the interrupt status register (ISR). If the most
+                 * significant bit is not set then there is no valid
+                 * interrupt.
+                 */
+                outb(0x0B, 0x20);               /* ISR register */
+                if(~inb(0x20) & 0x80)
+                        irq = -1;
+        }
+
+        spin_unlock(&i8259A_lock);
+
+        return irq;
+}
+
+#endif /* _ASM_I8259_H */
diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h
new file mode 100644
index 000000000000..bb674c3b0303
--- /dev/null
+++ b/include/asm-mips/ide.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file contains the MIPS architecture specific IDE code.
+ */
+#ifndef __ASM_IDE_H
+#define __ASM_IDE_H
+
+#include <ide.h>
+
+#endif /* __ASM_IDE_H */
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
new file mode 100644
index 000000000000..6ad517241768
--- /dev/null
+++ b/include/asm-mips/inst.h
@@ -0,0 +1,371 @@
+/*
+ * Format of an instruction in memory.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_INST_H
+#define _ASM_INST_H
+
+/*
+ * Major opcodes; before MIPS IV cop1x was called cop3.
+ */
+enum major_op {
+        spec_op, bcond_op, j_op, jal_op,
+        beq_op, bne_op, blez_op, bgtz_op,
+        addi_op, addiu_op, slti_op, sltiu_op,
+        andi_op, ori_op, xori_op, lui_op,
+        cop0_op, cop1_op, cop2_op, cop1x_op,
+        beql_op, bnel_op, blezl_op, bgtzl_op,
+        daddi_op, daddiu_op, ldl_op, ldr_op,
+        major_1c_op, jalx_op, major_1e_op, major_1f_op,
+        lb_op, lh_op, lwl_op, lw_op,
+        lbu_op, lhu_op, lwr_op, lwu_op,
+        sb_op, sh_op, swl_op, sw_op,
+        sdl_op, sdr_op, swr_op, cache_op,
+        ll_op, lwc1_op, lwc2_op, pref_op,
+        lld_op, ldc1_op, ldc2_op, ld_op,
+        sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
+        scd_op, sdc1_op, sdc2_op, sd_op
+};
+
+/*
+ * func field of spec opcode.
+ */
+enum spec_op {
+        sll_op, movc_op, srl_op, sra_op,
+        sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
+        jr_op, jalr_op, movz_op, movn_op,
+        syscall_op, break_op, spim_op, sync_op,
+        mfhi_op, mthi_op, mflo_op, mtlo_op,
+        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
+        mult_op, multu_op, div_op, divu_op,
+        dmult_op, dmultu_op, ddiv_op, ddivu_op,
+        add_op, addu_op, sub_op, subu_op,
+        and_op, or_op, xor_op, nor_op,
+        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
+        dadd_op, daddu_op, dsub_op, dsubu_op,
+        tge_op, tgeu_op, tlt_op, tltu_op,
+        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
+        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
+        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
+};
+
+/*
+ * rt field of bcond opcodes.
+ */
+enum rt_op {
+        bltz_op, bgez_op, bltzl_op, bgezl_op,
+        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
+        tgei_op, tgeiu_op, tlti_op, tltiu_op,
+        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
+        bltzal_op, bgezal_op, bltzall_op, bgezall_op
+        /*
+         * The others (0x14 - 0x1f) are unused.
+         */
+};
+
+/*
+ * rs field of cop opcodes.
+ */
+enum cop_op {
+        mfc_op        = 0x00, dmfc_op       = 0x01,
+        cfc_op        = 0x02, mtc_op        = 0x04,
+        dmtc_op       = 0x05, ctc_op        = 0x06,
+        bc_op         = 0x08, cop_op        = 0x10,
+        copm_op       = 0x18
+};
+
+/*
+ * rt field of cop.bc_op opcodes
+ */
+enum bcop_op {
+        bcf_op, bct_op, bcfl_op, bctl_op
+};
+
+/*
+ * func field of cop0 coi opcodes.
+ */
+enum cop0_coi_func {
+        tlbr_op       = 0x01, tlbwi_op      = 0x02,
+        tlbwr_op      = 0x06, tlbp_op       = 0x08,
+        rfe_op        = 0x10, eret_op       = 0x18
+};
+
+/*
+ * func field of cop0 com opcodes.
+ */
+enum cop0_com_func {
+        tlbr1_op      = 0x01, tlbw_op       = 0x02,
+        tlbp1_op      = 0x08, dctr_op       = 0x09,
+        dctw_op       = 0x0a
+};
+
+/*
+ * fmt field of cop1 opcodes.
+ */
+enum cop1_fmt {
+        s_fmt, d_fmt, e_fmt, q_fmt,
+        w_fmt, l_fmt
+};
+
+/*
+ * func field of cop1 instructions using d, s or w format.
+ */
+enum cop1_sdw_func {
+        fadd_op      =  0x00, fsub_op      =  0x01,
+        fmul_op      =  0x02, fdiv_op      =  0x03,
+        fsqrt_op     =  0x04, fabs_op      =  0x05,
+        fmov_op      =  0x06, fneg_op      =  0x07,
+        froundl_op   =  0x08, ftruncl_op   =  0x09,
+        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
+        fround_op    =  0x0c, ftrunc_op    =  0x0d,
+        fceil_op     =  0x0e, ffloor_op    =  0x0f,
+        fmovc_op     =  0x11, fmovz_op     =  0x12,
+        fmovn_op     =  0x13, frecip_op    =  0x15,
+        frsqrt_op    =  0x16, fcvts_op     =  0x20,
+        fcvtd_op     =  0x21, fcvte_op     =  0x22,
+        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
+        fcmp_op      =  0x30
+};
+
+/*
+ * func field of cop1x opcodes (MIPS IV).
+ */
+enum cop1x_func {
+        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
+        pfetch_op    =  0x07, swxc1_op     =  0x08,
+        sdxc1_op     =  0x09, madd_s_op    =  0x20,
+        madd_d_op    =  0x21, madd_e_op    =  0x22,
+        msub_s_op    =  0x28, msub_d_op    =  0x29,
+        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
+        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
+        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
+        nmsub_e_op   =  0x3a
+};
+
+/*
+ * func field for mad opcodes (MIPS IV).
+ */
+enum mad_func {
+        madd_op      = 0x08, msub_op      = 0x0a,
+        nmadd_op     = 0x0c, nmsub_op     = 0x0e
+};
+
+/*
+ * Damn ...  bitfields depend from byteorder :-(
+ */
+#ifdef __MIPSEB__
+struct j_format {       /* Jump format */
+        unsigned int opcode : 6;
+        unsigned int target : 26;
+};
+
+struct i_format {       /* Immediate format (addi, lw, ...) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        signed int simmediate : 16;
+};
+
+struct u_format {       /* Unsigned immediate format (ori, xori, ...) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int uimmediate : 16;
+};
+
+struct c_format {       /* Cache (>= R6000) format */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int c_op : 3;
+        unsigned int cache : 2;
+        unsigned int simmediate : 16;
+};
+
+struct r_format {       /* Register format */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct p_format {       /* Performance counter format (R10000) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct f_format {       /* FPU register format */
+        unsigned int opcode : 6;
+        unsigned int : 1;
+        unsigned int fmt : 4;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+        unsigned int opcode : 6;
+        unsigned int fr : 5;
+        unsigned int ft : 5;
+        unsigned int fs : 5;
+        unsigned int fd : 5;
+        unsigned int func : 4;
+        unsigned int fmt : 2;
+};
+
+#elif defined(__MIPSEL__)
+
+struct j_format {       /* Jump format */
+        unsigned int target : 26;
+        unsigned int opcode : 6;
+};
+
+struct i_format {       /* Immediate format */
+        signed int simmediate : 16;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct u_format {       /* Unsigned immediate format */
+        unsigned int uimmediate : 16;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct c_format {       /* Cache (>= R6000) format */
+        unsigned int simmediate : 16;
+        unsigned int cache : 2;
+        unsigned int c_op : 3;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct r_format {       /* Register format */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct p_format {       /* Performance counter format (R10000) */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct f_format {       /* FPU register format */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int fmt : 4;
+        unsigned int : 1;
+        unsigned int opcode : 6;
+};
+
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+        unsigned int fmt : 2;
+        unsigned int func : 4;
+        unsigned int fd : 5;
+        unsigned int fs : 5;
+        unsigned int ft : 5;
+        unsigned int fr : 5;
+        unsigned int opcode : 6;
+};
+
+#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
+#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
+#endif
+
+union mips_instruction {
+        unsigned int word;
+        unsigned short halfword[2];
+        unsigned char byte[4];
+        struct j_format j_format;
+        struct i_format i_format;
+        struct u_format u_format;
+        struct c_format c_format;
+        struct r_format r_format;
+        struct f_format f_format;
+        struct ma_format ma_format;
+};
+
+/* HACHACHAHCAHC ...  */
+
+/* In case some other massaging is needed, keep MIPSInst as wrapper */
+
+#define MIPSInst(x) x
+
+#define I_OPCODE_SFT    26
+#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
+
+#define I_JTARGET_SFT   0
+#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
+
+#define I_RS_SFT        21
+#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
+
+#define I_RT_SFT        16
+#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
+
+#define I_IMM_SFT       0
+#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
+#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
+
+#define I_CACHEOP_SFT   18
+#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
+
+#define I_CACHESEL_SFT  16
+#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
+
+#define I_RD_SFT        11
+#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
+
+#define I_RE_SFT        6
+#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
+
+#define I_FUNC_SFT      0
+#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
+
+#define I_FFMT_SFT      21
+#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
+
+#define I_FT_SFT        16
+#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
+
+#define I_FS_SFT        11
+#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
+
+#define I_FD_SFT        6
+#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
+
+#define I_FR_SFT        21
+#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
+
+#define I_FMA_FUNC_SFT  2
+#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
+
+#define I_FMA_FFMT_SFT  0
+#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
+
+typedef unsigned int mips_instruction;
+
+#endif /* _ASM_INST_H */
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
new file mode 100644
index 000000000000..e8357f5379fa
--- /dev/null
+++ b/include/asm-mips/interrupt.h
@@ -0,0 +1,134 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_INTERRUPT_H
+#define _ASM_INTERRUPT_H
+
+#include <asm/hazards.h>
+
+__asm__ (
+        ".macro\tlocal_irq_enable\n\t"
+        ".set\tpush\n\t"
+        ".set\treorder\n\t"
+        ".set\tnoat\n\t"
+        "mfc0\t$1,$12\n\t"
+        "ori\t$1,0x1f\n\t"
+        "xori\t$1,0x1e\n\t"
+        "mtc0\t$1,$12\n\t"
+        "irq_enable_hazard\n\t"
+        ".set\tpop\n\t"
+        ".endm");
+
+static inline void local_irq_enable(void)
+{
+        __asm__ __volatile__(
+                "local_irq_enable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+__asm__ (
+        ".macro\tlocal_irq_disable\n\t"
+        ".set\tpush\n\t"
+        ".set\tnoat\n\t"
+        "mfc0\t$1,$12\n\t"
+        "ori\t$1,1\n\t"
+        "xori\t$1,1\n\t"
+        ".set\tnoreorder\n\t"
+        "mtc0\t$1,$12\n\t"
+        "irq_disable_hazard\n\t"
+        ".set\tpop\n\t"
+        ".endm");
+
+static inline void local_irq_disable(void)
+{
+        __asm__ __volatile__(
+                "local_irq_disable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+__asm__ (
+        ".macro\tlocal_save_flags flags\n\t"
+        ".set\tpush\n\t"
+        ".set\treorder\n\t"
+        "mfc0\t\\flags, $12\n\t"
+        ".set\tpop\n\t"
+        ".endm");
+
+#define local_save_flags(x)                                             \
+__asm__ __volatile__(                                                   \
+        "local_save_flags %0"                                           \
+        : "=r" (x))
+
+__asm__ (
+        ".macro\tlocal_irq_save result\n\t"
+        ".set\tpush\n\t"
+        ".set\treorder\n\t"
+        ".set\tnoat\n\t"
+        "mfc0\t\\result, $12\n\t"
+        "ori\t$1, \\result, 1\n\t"
+        "xori\t$1, 1\n\t"
+        ".set\tnoreorder\n\t"
+        "mtc0\t$1, $12\n\t"
+        "irq_disable_hazard\n\t"
+        ".set\tpop\n\t"
+        ".endm");
+
+#define local_irq_save(x)                                               \
+__asm__ __volatile__(                                                   \
+        "local_irq_save\t%0"                                            \
+        : "=r" (x)                                                      \
+        : /* no inputs */                                               \
+        : "memory")
+
+__asm__ (
+        ".macro\tlocal_irq_restore flags\n\t"
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n\t"
+        "mfc0\t$1, $12\n\t"
+        "andi\t\\flags, 1\n\t"
+        "ori\t$1, 1\n\t"
+        "xori\t$1, 1\n\t"
+        "or\t\\flags, $1\n\t"
+        "mtc0\t\\flags, $12\n\t"
+        "irq_disable_hazard\n\t"
+        ".set\tat\n\t"
+        ".set\treorder\n\t"
+        ".endm");
+
+#define local_irq_restore(flags)                                        \
+do {                                                                    \
+        unsigned long __tmp1;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+                "local_irq_restore\t%0"                                 \
+                : "=r" (__tmp1)                                         \
+                : "0" (flags)                                           \
+                : "memory");                                            \
+} while(0)
+
+#define irqs_disabled()                                                 \
+({                                                                      \
+        unsigned long flags;                                            \
+        local_save_flags(flags);                                        \
+        !(flags & 1);                                                   \
+})
+
+#endif /* _ASM_INTERRUPT_H */
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
new file mode 100644
index 000000000000..4cd36fe98173
--- /dev/null
+++ b/include/asm-mips/inventory.h
@@ -0,0 +1,20 @@
+/*
+ * Miguel de Icaza
+ */
+#ifndef __ASM_INVENTORY_H
+#define __ASM_INVENTORY_H
+
+typedef struct inventory_s {
+        struct inventory_s *inv_next;
+        int    inv_class;
+        int    inv_type;
+        int    inv_controller;
+        int    inv_unit;
+        int    inv_state;
+} inventory_t;
+
+extern int inventory_items;
+void add_to_inventory (int class, int type, int controller, int unit, int state);
+int dump_inventory_to_user (void *userbuf, int size);
+
+#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
new file mode 100644
index 000000000000..039845f2e6b0
--- /dev/null
+++ b/include/asm-mips/io.h
@@ -0,0 +1,630 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf GmbH
+ * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Author: Maciej W. Rozycki <macro@mips.com>
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/bug.h>
+#include <asm/byteorder.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/page.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+
+#include <mangle-port.h>
+
+/*
+ * Slowdown I/O port space accesses for antique hardware.
+ */
+#undef CONF_SLOWDOWN_IO
+
+/*
+ * Raw operations are never swapped in software.  Otoh values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware.  An example use would be for flash memory that's used for
+ * execute in place.
+ */
+# define __raw_ioswabb(x)       (x)
+# define __raw_ioswabw(x)       (x)
+# define __raw_ioswabl(x)       (x)
+# define __raw_ioswabq(x)       (x)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(x)             (x)
+# ifdef CONFIG_SGI_IP22
+/*
+ * IP22 seems braindead enough to swap 16bits values in hardware, but
+ * not 32bits.  Go figure... Can't tell without documentation.
+ */
+#  define ioswabw(x)            (x)
+# else
+#  define ioswabw(x)            le16_to_cpu(x)
+# endif
+# define ioswabl(x)             le32_to_cpu(x)
+# define ioswabq(x)             le64_to_cpu(x)
+
+#else
+
+# define ioswabb(x)             (x)
+# define ioswabw(x)             (x)
+# define ioswabl(x)             (x)
+# define ioswabq(x)             (x)
+
+#endif
+
+/*
+ * Native bus accesses never swapped.
+ */
+#define bus_ioswabb(x)          (x)
+#define bus_ioswabw(x)          (x)
+#define bus_ioswabl(x)          (x)
+#define bus_ioswabq(x)          (x)
+
+#define __bus_ioswabq           bus_ioswabq
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. mips_io_port_base is the virtual address to
+ * which all ports are being mapped.  For sake of efficiency some code
+ * assumes that this is an address that can be loaded with a single lui
+ * instruction, so the lower 16 bits must be zero.  Should be true on
+ * on any sane architecture; generic code does not use this assumption.
+ */
+extern const unsigned long mips_io_port_base;
+
+#define set_io_port_base(base)  \
+        do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *              Linus
+ *
+ */
+
+#define __SLOW_DOWN_IO \
+        __asm__ __volatile__( \
+                "sb\t$0,0x80(%0)" \
+                : : "r" (mips_io_port_base));
+
+#ifdef CONF_SLOWDOWN_IO
+#ifdef REALLY_SLOW_IO
+#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
+#else
+#define SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+#else
+#define SLOW_DOWN_IO
+#endif
+
+/*
+ *     virt_to_phys    -       map virtual addresses to physical
+ *     @address: address to remap
+ *
+ *     The returned physical address is the physical (CPU) mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses directly mapped or allocated via kmalloc.
+ *
+ *     This function does not give bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+        return (unsigned long)address - PAGE_OFFSET;
+}
+
+/*
+ *     phys_to_virt    -       map physical address to virtual
+ *     @address: address to remap
+ *
+ *     The returned virtual address is a current CPU mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses that have a kernel mapping
+ *
+ *     This function does not handle bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void *)(address + PAGE_OFFSET);
+}
+
+/*
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
+ */
+static inline unsigned long isa_virt_to_bus(volatile void * address)
+{
+        return (unsigned long)address - PAGE_OFFSET;
+}
+
+static inline void * isa_bus_to_virt(unsigned long address)
+{
+        return (void *)(address + PAGE_OFFSET);
+}
+
+#define isa_page_to_bus page_to_phys
+
+/*
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
+ */
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+/*
+ * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
+ * for the processor.  This implies the assumption that there is only
+ * one of these busses.
+ */
+extern unsigned long isa_slot_offset;
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
+
+extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
+extern void __iounmap(volatile void __iomem *addr);
+
+static inline void * __ioremap_mode(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        if (cpu_has_64bit_addresses) {
+                u64 base = UNCAC_BASE;
+
+                /*
+                 * R10000 supports a 2 bit uncached attribute therefore
+                 * UNCAC_BASE may not equal IO_BASE.
+                 */
+                if (flags == _CACHE_UNCACHED)
+                        base = (u64) IO_BASE;
+                return (void *) (unsigned long) (base + offset);
+        }
+
+        return __ioremap(offset, size, flags);
+}
+
+/*
+ * ioremap     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ */
+#define ioremap(offset, size)                                           \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+
+/*
+ * ioremap_nocache     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In paticular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
+ */
+#define ioremap_nocache(offset, size)                                   \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+
+/*
+ * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
+ */
+#define ioremap_cacheable_cow(offset, size)                             \
+        __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size)                      \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
+
+static inline void iounmap(volatile void __iomem *addr)
+{
+        if (cpu_has_64bit_addresses)
+                return;
+
+        __iounmap(addr);
+}
+
+
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
+                                                                        \
+static inline void pfx##write##bwlq(type val,                           \
+                                    volatile void __iomem *mem)         \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        __val = pfx##ioswab##bwlq(val);                                 \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                *__mem = __val;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                type __tmp;                                             \
+                                                                        \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
+                __asm__ __volatile__(                                   \
+                        ".set   mips3"          "\t\t# __writeq""\n\t"  \
+                        "dsll32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsrl32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsll32 %M0, %M0, 0"                    "\n\t"  \
+                        "or     %L0, %L0, %M0"                  "\n\t"  \
+                        "sd     %L0, %2"                        "\n\t"  \
+                        ".set   mips0"                          "\n"    \
+                        : "=r" (__tmp)                                  \
+                        : "0" (__val), "m" (*__mem));                   \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
+        } else                                                          \
+                BUG();                                                  \
+}                                                                       \
+                                                                        \
+static inline type pfx##read##bwlq(volatile void __iomem *mem)          \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                __val = *__mem;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                                                                        \
+                local_irq_save(__flags);                                \
+                __asm__ __volatile__(                                   \
+                        ".set   mips3"          "\t\t# __readq" "\n\t"  \
+                        "ld     %L0, %1"                        "\n\t"  \
+                        "dsra32 %M0, %L0, 0"                    "\n\t"  \
+                        "sll    %L0, %L0, 0"                    "\n\t"  \
+                        ".set   mips0"                          "\n"    \
+                        : "=r" (__val)                                  \
+                        : "m" (*__mem));                                \
+                local_irq_restore(__flags);                             \
+        } else {                                                        \
+                __val = 0;                                              \
+                BUG();                                                  \
+        }                                                               \
+                                                                        \
+        return pfx##ioswab##bwlq(__val);                                \
+}
+
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
+                                                                        \
+static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        port = __swizzle_addr_##bwlq(port);                             \
+        __addr = (void *)(mips_io_port_base + port);                    \
+                                                                        \
+        __val = pfx##ioswab##bwlq(val);                                 \
+                                                                        \
+        if (sizeof(type) != sizeof(u64)) {                              \
+                *__addr = __val;                                        \
+                slow;                                                   \
+        } else                                                          \
+                BUILD_BUG();                                            \
+}                                                                       \
+                                                                        \
+static inline type pfx##in##bwlq##p(unsigned long port)                 \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        port = __swizzle_addr_##bwlq(port);                             \
+        __addr = (void *)(mips_io_port_base + port);                    \
+                                                                        \
+        if (sizeof(type) != sizeof(u64)) {                              \
+                __val = *__addr;                                        \
+                slow;                                                   \
+        } else {                                                        \
+                __val = 0;                                              \
+                BUILD_BUG();                                            \
+        }                                                               \
+                                                                        \
+        return pfx##ioswab##bwlq(__val);                                \
+}
+
+#define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
+                                                                        \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+                                                                        \
+__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                               \
+__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO(bwlq, type)                                             \
+                                                                        \
+__BUILD_MEMORY_PFX(, bwlq, type)                                        \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
+__BUILD_MEMORY_PFX(bus_, bwlq, type)                                    \
+__BUILD_IOPORT_PFX(, bwlq, type)                                        \
+__BUILD_IOPORT_PFX(__raw_, bwlq, type)
+
+#define __BUILDIO(bwlq, type)                                           \
+                                                                        \
+__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
+
+BUILDIO(b, u8)
+BUILDIO(w, u16)
+BUILDIO(l, u32)
+BUILDIO(q, u64)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed                   readb
+#define readw_relaxed                   readw
+#define readl_relaxed                   readl
+#define readq_relaxed                   readq
+
+/*
+ * Some code tests for these symbols
+ */
+#define readq                           readq
+#define writeq                          writeq
+
+#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+                                                                        \
+static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \
+                                unsigned int count)                     \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                __raw_write##bwlq(*__addr, mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
+                               unsigned int count)                      \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __raw_read##bwlq(mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define __BUILD_IOPORT_STRING(bwlq, type)                               \
+                                                                        \
+static inline void outs##bwlq(unsigned long port, void *addr,           \
+                              unsigned int count)                       \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                __raw_out##bwlq(*__addr, port);                         \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void ins##bwlq(unsigned long port, void *addr,            \
+                             unsigned int count)                        \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __raw_in##bwlq(port);                         \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define BUILDSTRING(bwlq, type)                                         \
+                                                                        \
+__BUILD_MEMORY_STRING(bwlq, type)                                       \
+__BUILD_IOPORT_STRING(bwlq, type)
+
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+BUILDSTRING(q, u64)
+
+
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+
+#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+
+/*
+ * Memory Mapped I/O
+ */
+#define ioread8(addr)           readb(addr)
+#define ioread16(addr)          readw(addr)
+#define ioread32(addr)          readl(addr)
+
+#define iowrite8(b,addr)        writeb(b,addr)
+#define iowrite16(w,addr)       writew(w,addr)
+#define iowrite32(l,addr)       writel(l,addr)
+
+#define ioread8_rep(a,b,c)      readsb(a,b,c)
+#define ioread16_rep(a,b,c)     readsw(a,b,c)
+#define ioread32_rep(a,b,c)     readsl(a,b,c)
+
+#define iowrite8_rep(a,b,c)     writesb(a,b,c)
+#define iowrite16_rep(a,b,c)    writesw(a,b,c)
+#define iowrite32_rep(a,b,c)    writesl(a,b,c)
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/*
+ * ISA space is 'always mapped' on currently supported MIPS systems, no need
+ * to explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+ * are physical addresses. The following constant pointer can be
+ * used as the IO-area pointer (it can be iounmapped as well, so the
+ * analogy with PCI is quite large):
+ */
+#define __ISA_IO_base ((char *)(isa_slot_offset))
+
+#define isa_readb(a)            readb(__ISA_IO_base + (a))
+#define isa_readw(a)            readw(__ISA_IO_base + (a))
+#define isa_readl(a)            readl(__ISA_IO_base + (a))
+#define isa_readq(a)            readq(__ISA_IO_base + (a))
+#define isa_writeb(b,a)         writeb(b,__ISA_IO_base + (a))
+#define isa_writew(w,a)         writew(w,__ISA_IO_base + (a))
+#define isa_writel(l,a)         writel(l,__ISA_IO_base + (a))
+#define isa_writeq(q,a)         writeq(q,__ISA_IO_base + (a))
+#define isa_memset_io(a,b,c)    memset_io(__ISA_IO_base + (a),(b),(c))
+#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
+#define isa_memcpy_toio(a,b,c)  memcpy_toio(__ISA_IO_base + (a),(b),(c))
+
+/*
+ * We don't have csum_partial_copy_fromio() yet, so we cheat here and
+ * just copy it. The net code will then do the checksum later.
+ */
+#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
+#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
+
+/*
+ *     check_signature         -       find BIOS signatures
+ *     @io_addr: mmio address to check
+ *     @signature:  signature block
+ *     @length: length of signature
+ *
+ *     Perform a signature comparison with the mmio address io_addr. This
+ *     address should have been obtained by ioremap.
+ *     Returns 1 on a match.
+ */
+static inline int check_signature(char __iomem *io_addr,
+        const unsigned char *signature, int length)
+{
+        int retval = 0;
+        do {
+                if (readb(io_addr) != *signature)
+                        goto out;
+                io_addr++;
+                signature++;
+                length--;
+        } while (length);
+        retval = 1;
+out:
+        return retval;
+}
+
+/*
+ * The caches on some architectures aren't dma-coherent and have need to
+ * handle this in software.  There are three types of operations that
+ * can be applied to dma buffers.
+ *
+ *  - dma_cache_wback_inv(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_wback(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_inv(start, size) invalidates the affected parts of the
+ *    caches.  Dirty lines of the caches may be written back or simply
+ *    be discarded.  This operation is necessary before dma operations
+ *    to the memory.
+ */
+#ifdef CONFIG_DMA_NONCOHERENT
+
+extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+#define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start,size)
+#define dma_cache_wback(start, size)            _dma_cache_wback(start,size)
+#define dma_cache_inv(start, size)              _dma_cache_inv(start,size)
+
+#else /* Sane hardware */
+
+#define dma_cache_wback_inv(start,size) \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size)     \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size)       \
+        do { (void) (start); (void) (size); } while (0)
+
+#endif /* CONFIG_DMA_NONCOHERENT */
+
+/*
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
+ */
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* _ASM_IO_H */
diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h
new file mode 100644
index 000000000000..cba641a6ce09
--- /dev/null
+++ b/include/asm-mips/ioctl.h
@@ -0,0 +1,99 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle
+ */
+#ifndef _ASM_IOCTL_H
+#define _ASM_IOCTL_H
+
+/*
+ * The original linux ioctl numbering scheme was just a general
+ * "anything goes" setup, where more or less random numbers were
+ * assigned.  Sorry, I was clueless when I started out on this.
+ *
+ * On the alpha, we'll try to clean it up a bit, using a more sane
+ * ioctl numbering, and also trying to be compatible with OSF/1 in
+ * the process. I'd like to clean it up for the i386 as well, but
+ * it's so painful recognizing both the new and the old numbers..
+ *
+ * The same applies for for the MIPS ABI; in fact even the macros
+ * from Linux/Alpha fit almost perfectly.
+ */
+
+#define _IOC_NRBITS     8
+#define _IOC_TYPEBITS   8
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT    0
+#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * We to additionally limit parameters to a maximum 255 bytes.
+ */
+#define _IOC_SLMASK     0xff
+
+/*
+ * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
+ * And this turns out useful to catch old ioctl numbers in header
+ * files for us.
+ */
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+/*
+ * The following are included for compatibility
+ */
+#define _IOC_VOID       0x20000000
+#define _IOC_OUT        0x40000000
+#define _IOC_IN         0x80000000
+#define _IOC_INOUT      (IOC_IN|IOC_OUT)
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+        ((sizeof(t) == sizeof(t[1]) && \
+          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+          sizeof(t) : __invalid_size_argument_for_IOC)
+
+/* used to create numbers */
+#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW_BAD(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+
+/* used to decode them.. */
+#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif /* _ASM_IOCTL_H */
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
new file mode 100644
index 000000000000..92f6c36aac4d
--- /dev/null
+++ b/include/asm-mips/ioctls.h
@@ -0,0 +1,105 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_IOCTLS_H
+#define __ASM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define TCGETA          0x5401
+#define TCSETA          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETAW         0x5403
+#define TCSETAF         0x5404
+
+#define TCSBRK          0x5405
+#define TCXONC          0x5406
+#define TCFLSH          0x5407
+
+#define TCGETS          0x540d
+#define TCSETS          0x540e
+#define TCSETSW         0x540f
+#define TCSETSF         0x5410
+
+#define TIOCEXCL        0x740d          /* set exclusive use of tty */
+#define TIOCNXCL        0x740e          /* reset exclusive use of tty */
+#define TIOCOUTQ        0x7472          /* output queue size */
+#define TIOCSTI         0x5472          /* simulate terminal input */
+#define TIOCMGET        0x741d          /* get all modem bits */
+#define TIOCMBIS        0x741b          /* bis modem bits */
+#define TIOCMBIC        0x741c          /* bic modem bits */
+#define TIOCMSET        0x741a          /* set all modem bits */
+#define TIOCPKT         0x5470          /* pty: set/clear packet mode */
+#define  TIOCPKT_DATA           0x00    /* data packet */
+#define  TIOCPKT_FLUSHREAD      0x01    /* flush packet */
+#define  TIOCPKT_FLUSHWRITE     0x02    /* flush packet */
+#define  TIOCPKT_STOP           0x04    /* stop output */
+#define  TIOCPKT_START          0x08    /* start output */
+#define  TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
+#define  TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
+/* #define  TIOCPKT_IOCTL               0x40    state change of pty driver */
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */
+#define TIOCNOTTY       0x5471          /* void tty association */
+#define TIOCSETD        0x7401
+#define TIOCGETD        0x7400
+
+#define FIOCLEX         0x6601
+#define FIONCLEX        0x6602
+#define FIOASYNC        0x667d
+#define FIONBIO         0x667e
+#define FIOQSIZE        0x667f
+
+#define TIOCGLTC        0x7474                  /* get special local chars */
+#define TIOCSLTC        0x7475                  /* set special local chars */
+#define TIOCSPGRP       _IOW('t', 118, int)     /* set pgrp of tty */
+#define TIOCGPGRP       _IOR('t', 119, int)     /* get pgrp of tty */
+#define TIOCCONS        _IOW('t', 120, int)     /* become virtual console */
+
+#define FIONREAD        0x467f
+#define TIOCINQ         FIONREAD
+
+#define TIOCGETP        0x7408
+#define TIOCSETP        0x7409
+#define TIOCSETN        0x740a                  /* TIOCSETP wo flush */
+
+/* #define TIOCSETA     _IOW('t', 20, struct termios) set termios struct */
+/* #define TIOCSETAW    _IOW('t', 21, struct termios) drain output, set */
+/* #define TIOCSETAF    _IOW('t', 22, struct termios) drn out, fls in, set */
+/* #define TIOCGETD     _IOR('t', 26, int)      get line discipline */
+/* #define TIOCSETD     _IOW('t', 27, int)      set line discipline */
+                                                /* 127-124 compat */
+
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x7416  /* Return the session ID of FD */
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+/* I hope the range from 0x5480 on is free ... */
+#define TIOCSCTTY       0x5480          /* become controlling tty */
+#define TIOCGSOFTCAR    0x5481
+#define TIOCSSOFTCAR    0x5482
+#define TIOCLINUX       0x5483
+#define TIOCGSERIAL     0x5484
+#define TIOCSSERIAL     0x5485
+#define TCSBRKP         0x5486  /* Needed for POSIX tcsendbreak() */
+#define TIOCSERCONFIG   0x5488
+#define TIOCSERGWILD    0x5489
+#define TIOCSERSWILD    0x548a
+#define TIOCGLCKTRMIOS  0x548b
+#define TIOCSLCKTRMIOS  0x548c
+#define TIOCSERGSTRUCT  0x548d /* For debugging only */
+#define TIOCSERGETLSR   0x548e /* Get line status register */
+#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
+#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
+#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP   0x5493 /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP   0x5494 /* Set Hayes ESP configuration */
+
+#endif /* __ASM_IOCTLS_H */
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h
new file mode 100644
index 000000000000..152879bae20f
--- /dev/null
+++ b/include/asm-mips/ip32/crime.h
@@ -0,0 +1,161 @@
+/*
+ * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
+ * Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_CRIME_H__
+#define __ASM_CRIME_H__
+
+/*
+ * Address map
+ */
+#define CRIME_BASE      0x14000000      /* physical */
+
+#undef BIT
+#define BIT(x)  (1UL << (x))
+
+struct sgi_crime {
+        volatile unsigned long id;
+#define CRIME_ID_MASK                   0xff
+#define CRIME_ID_IDBITS                 0xf0
+#define CRIME_ID_IDVALUE                0xa0
+#define CRIME_ID_REV                    0x0f
+#define CRIME_REV_PETTY                 0x00
+#define CRIME_REV_11                    0x11
+#define CRIME_REV_13                    0x13
+#define CRIME_REV_14                    0x14
+
+        volatile unsigned long control;
+#define CRIME_CONTROL_MASK              0x3fff
+#define CRIME_CONTROL_TRITON_SYSADC     0x2000
+#define CRIME_CONTROL_CRIME_SYSADC      0x1000
+#define CRIME_CONTROL_HARD_RESET        0x0800
+#define CRIME_CONTROL_SOFT_RESET        0x0400
+#define CRIME_CONTROL_DOG_ENA           0x0200
+#define CRIME_CONTROL_ENDIANESS         0x0100
+#define CRIME_CONTROL_ENDIAN_BIG        0x0100
+#define CRIME_CONTROL_ENDIAN_LITTLE     0x0000
+#define CRIME_CONTROL_CQUEUE_HWM        0x000f
+#define CRIME_CONTROL_CQUEUE_SHFT       0
+#define CRIME_CONTROL_WBUF_HWM          0x00f0
+#define CRIME_CONTROL_WBUF_SHFT         8
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+        volatile unsigned long soft_int;
+        volatile unsigned long hard_int;
+#define MACE_VID_IN1_INT                BIT(0)
+#define MACE_VID_IN2_INT                BIT(1)
+#define MACE_VID_OUT_INT                BIT(2)
+#define MACE_ETHERNET_INT               BIT(3)
+#define MACE_SUPERIO_INT                BIT(4)
+#define MACE_MISC_INT                   BIT(5)
+#define MACE_AUDIO_INT                  BIT(6)
+#define MACE_PCI_BRIDGE_INT             BIT(7)
+#define MACEPCI_SCSI0_INT               BIT(8)
+#define MACEPCI_SCSI1_INT               BIT(9)
+#define MACEPCI_SLOT0_INT               BIT(10)
+#define MACEPCI_SLOT1_INT               BIT(11)
+#define MACEPCI_SLOT2_INT               BIT(12)
+#define MACEPCI_SHARED0_INT             BIT(13)
+#define MACEPCI_SHARED1_INT             BIT(14)
+#define MACEPCI_SHARED2_INT             BIT(15)
+#define CRIME_GBE0_INT                  BIT(16)
+#define CRIME_GBE1_INT                  BIT(17)
+#define CRIME_GBE2_INT                  BIT(18)
+#define CRIME_GBE3_INT                  BIT(19)
+#define CRIME_CPUERR_INT                BIT(20)
+#define CRIME_MEMERR_INT                BIT(21)
+#define CRIME_RE_EMPTY_E_INT            BIT(22)
+#define CRIME_RE_FULL_E_INT             BIT(23)
+#define CRIME_RE_IDLE_E_INT             BIT(24)
+#define CRIME_RE_EMPTY_L_INT            BIT(25)
+#define CRIME_RE_FULL_L_INT             BIT(26)
+#define CRIME_RE_IDLE_L_INT             BIT(27)
+#define CRIME_SOFT0_INT                 BIT(28)
+#define CRIME_SOFT1_INT                 BIT(29)
+#define CRIME_SOFT2_INT                 BIT(30)
+#define CRIME_SYSCORERR_INT             CRIME_SOFT2_INT
+#define CRIME_VICE_INT                  BIT(31)
+/* Masks for deciding who handles the interrupt */
+#define CRIME_MACE_INT_MASK             0x8f
+#define CRIME_MACEISA_INT_MASK          0x70
+#define CRIME_MACEPCI_INT_MASK          0xff00
+#define CRIME_CRIME_INT_MASK            0xffff0000
+
+        volatile unsigned long watchdog;
+#define CRIME_DOG_POWER_ON_RESET        0x00010000
+#define CRIME_DOG_WARM_RESET            0x00080000
+#define CRIME_DOG_TIMEOUT               (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
+#define CRIME_DOG_VALUE                 0x00007fff
+
+        volatile unsigned long timer;
+#define CRIME_MASTER_FREQ               66666500        /* Crime upcounter frequency */
+#define CRIME_NS_PER_TICK               15              /* for delay_calibrate */
+
+        volatile unsigned long cpu_error_addr;
+#define CRIME_CPU_ERROR_ADDR_MASK       0x3ffffffff
+
+        volatile unsigned long cpu_error_stat;
+#define CRIME_CPU_ERROR_MASK            0x7             /* cpu error stat is 3 bits */
+#define CRIME_CPU_ERROR_CPU_ILL_ADDR    0x4
+#define CRIME_CPU_ERROR_VICE_WRT_PRTY   0x2
+#define CRIME_CPU_ERROR_CPU_WRT_PRTY    0x1
+
+        unsigned long _pad0[54];
+
+        volatile unsigned long mc_ctrl;
+        volatile unsigned long bank_ctrl[8];
+#define CRIME_MEM_BANK_CONTROL_MASK             0x11f   /* 9 bits 7:5 reserved */
+#define CRIME_MEM_BANK_CONTROL_ADDR             0x01f
+#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE       0x100
+#define CRIME_MAXBANKS                          8
+
+        volatile unsigned long mem_ref_counter;
+#define CRIME_MEM_REF_COUNTER_MASK      0x3ff           /* 10bit */
+
+        volatile unsigned long mem_error_stat;
+#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff      /* 28-bit register */
+#define CRIME_MEM_ERROR_MACE_ID         0x0000007f
+#define CRIME_MEM_ERROR_MACE_ACCESS     0x00000080
+#define CRIME_MEM_ERROR_RE_ID           0x00007f00
+#define CRIME_MEM_ERROR_RE_ACCESS       0x00008000
+#define CRIME_MEM_ERROR_GBE_ACCESS      0x00010000
+#define CRIME_MEM_ERROR_VICE_ACCESS     0x00020000
+#define CRIME_MEM_ERROR_CPU_ACCESS      0x00040000
+#define CRIME_MEM_ERROR_RESERVED        0x00080000
+#define CRIME_MEM_ERROR_SOFT_ERR        0x00100000
+#define CRIME_MEM_ERROR_HARD_ERR        0x00200000
+#define CRIME_MEM_ERROR_MULTIPLE        0x00400000
+#define CRIME_MEM_ERROR_ECC             0x01800000
+#define CRIME_MEM_ERROR_MEM_ECC_RD      0x00800000
+#define CRIME_MEM_ERROR_MEM_ECC_RMW     0x01000000
+#define CRIME_MEM_ERROR_INV             0x0e000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
+
+        volatile unsigned long mem_error_addr;
+#define CRIME_MEM_ERROR_ADDR_MASK       0x3fffffff
+
+        volatile unsigned long mem_ecc_syn;
+#define CRIME_MEM_ERROR_ECC_SYN_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_chk;
+#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_repl;
+#define CRIME_MEM_ERROR_ECC_REPL_MASK   0xffffffff
+};
+
+extern struct sgi_crime *crime;
+
+#define CRIME_HI_MEM_BASE       0x40000000      /* this is where whole 1G of RAM is mapped */
+
+#endif /* __ASM_CRIME_H__ */
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
new file mode 100644
index 000000000000..c3c280e3d591
--- /dev/null
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -0,0 +1,94 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_IP32_INTS_H
+#define __ASM_IP32_INTS_H
+
+/*
+ * This list reflects the assignment of interrupt numbers to
+ * interrupting events.  Order is fairly irrelevant to handling
+ * priority.  This differs from irix.
+ */
+
+/* CPU */
+#define IP32_R4K_TIMER_IRQ              0
+
+/* MACE */
+#define MACE_VID_IN1_IRQ                1
+#define MACE_VID_IN2_IRQ                2
+#define MACE_VID_OUT_IRQ                3
+#define MACE_ETHERNET_IRQ               4
+/* SUPERIO, MISC, and AUDIO are MACEISA */
+#define MACE_PCI_BRIDGE_IRQ             8
+
+/* MACEPCI */
+#define MACEPCI_SCSI0_IRQ               9
+#define MACEPCI_SCSI1_IRQ               10
+#define MACEPCI_SLOT0_IRQ               11
+#define MACEPCI_SLOT1_IRQ               12
+#define MACEPCI_SLOT2_IRQ               13
+#define MACEPCI_SHARED0_IRQ             14
+#define MACEPCI_SHARED1_IRQ             15
+#define MACEPCI_SHARED2_IRQ             16
+
+/* CRIME */
+#define CRIME_GBE0_IRQ                  17
+#define CRIME_GBE1_IRQ                  18
+#define CRIME_GBE2_IRQ                  19
+#define CRIME_GBE3_IRQ                  20
+#define CRIME_CPUERR_IRQ                21
+#define CRIME_MEMERR_IRQ                22
+#define CRIME_RE_EMPTY_E_IRQ            23
+#define CRIME_RE_FULL_E_IRQ             24
+#define CRIME_RE_IDLE_E_IRQ             25
+#define CRIME_RE_EMPTY_L_IRQ            26
+#define CRIME_RE_FULL_L_IRQ             27
+#define CRIME_RE_IDLE_L_IRQ             28
+#define CRIME_SOFT0_IRQ                 29
+#define CRIME_SOFT1_IRQ                 30
+#define CRIME_SOFT2_IRQ                 31
+#define CRIME_SYSCORERR_IRQ             CRIME_SOFT2_IRQ
+#define CRIME_VICE_IRQ                  32
+
+/* MACEISA */
+#define MACEISA_AUDIO_SW_IRQ            33
+#define MACEISA_AUDIO_SC_IRQ            34
+#define MACEISA_AUDIO1_DMAT_IRQ         35
+#define MACEISA_AUDIO1_OF_IRQ           36
+#define MACEISA_AUDIO2_DMAT_IRQ         37
+#define MACEISA_AUDIO2_MERR_IRQ         38
+#define MACEISA_AUDIO3_DMAT_IRQ         39
+#define MACEISA_AUDIO3_MERR_IRQ         40
+#define MACEISA_RTC_IRQ                 41
+#define MACEISA_KEYB_IRQ                42
+/* MACEISA_KEYB_POLL is not an IRQ */
+#define MACEISA_MOUSE_IRQ               44
+/* MACEISA_MOUSE_POLL is not an IRQ */
+#define MACEISA_TIMER0_IRQ              46
+#define MACEISA_TIMER1_IRQ              47
+#define MACEISA_TIMER2_IRQ              48
+#define MACEISA_PARALLEL_IRQ            49
+#define MACEISA_PAR_CTXA_IRQ            50
+#define MACEISA_PAR_CTXB_IRQ            51
+#define MACEISA_PAR_MERR_IRQ            52
+#define MACEISA_SERIAL1_IRQ             53
+#define MACEISA_SERIAL1_TDMAT_IRQ       54
+#define MACEISA_SERIAL1_TDMAPR_IRQ      55
+#define MACEISA_SERIAL1_TDMAME_IRQ      56
+#define MACEISA_SERIAL1_RDMAT_IRQ       57
+#define MACEISA_SERIAL1_RDMAOR_IRQ      58
+#define MACEISA_SERIAL2_IRQ             59
+#define MACEISA_SERIAL2_TDMAT_IRQ       60
+#define MACEISA_SERIAL2_TDMAPR_IRQ      61
+#define MACEISA_SERIAL2_TDMAME_IRQ      62
+#define MACEISA_SERIAL2_RDMAT_IRQ       63
+#define MACEISA_SERIAL2_RDMAOR_IRQ      64
+
+#define IP32_IRQ_MAX                    MACEISA_SERIAL2_RDMAOR_IRQ
+
+#endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
new file mode 100644
index 000000000000..2b7b0fdeac19
--- /dev/null
+++ b/include/asm-mips/ip32/mace.h
@@ -0,0 +1,334 @@
+/*
+ * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ * Copyright (C) 2004 Ladislav Michl
+ */
+
+#ifndef __ASM_MACE_H__
+#define __ASM_MACE_H__
+
+/*
+ * Address map
+ */
+#define MACE_BASE       0x1f000000      /* physical */
+
+#undef BIT
+#define BIT(x) (1UL << (x))
+
+/*
+ * PCI interface
+ */
+struct mace_pci {
+        volatile unsigned int error_addr;
+        volatile unsigned int error;
+#define MACEPCI_ERROR_MASTER_ABORT              BIT(31)
+#define MACEPCI_ERROR_TARGET_ABORT              BIT(30)
+#define MACEPCI_ERROR_DATA_PARITY_ERR           BIT(29)
+#define MACEPCI_ERROR_RETRY_ERR                 BIT(28)
+#define MACEPCI_ERROR_ILLEGAL_CMD               BIT(27)
+#define MACEPCI_ERROR_SYSTEM_ERR                BIT(26)
+#define MACEPCI_ERROR_INTERRUPT_TEST            BIT(25)
+#define MACEPCI_ERROR_PARITY_ERR                BIT(24)
+#define MACEPCI_ERROR_OVERRUN                   BIT(23)
+#define MACEPCI_ERROR_RSVD                      BIT(22)
+#define MACEPCI_ERROR_MEMORY_ADDR               BIT(21)
+#define MACEPCI_ERROR_CONFIG_ADDR               BIT(20)
+#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
+#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
+#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
+#define MACEPCI_ERROR_RETRY_ADDR_VALID          BIT(16)
+#define MACEPCI_ERROR_SIG_TABORT                BIT(4)
+#define MACEPCI_ERROR_DEVSEL_MASK               0xc0
+#define MACEPCI_ERROR_DEVSEL_FAST               0
+#define MACEPCI_ERROR_DEVSEL_MED                0x40
+#define MACEPCI_ERROR_DEVSEL_SLOW               0x80
+#define MACEPCI_ERROR_FBB                       BIT(1)
+#define MACEPCI_ERROR_66MHZ                     BIT(0)
+        volatile unsigned int control;
+#define MACEPCI_CONTROL_INT(x)                  BIT(x)
+#define MACEPCI_CONTROL_INT_MASK                0xff
+#define MACEPCI_CONTROL_SERR_ENA                BIT(8)
+#define MACEPCI_CONTROL_ARB_N6                  BIT(9)
+#define MACEPCI_CONTROL_PARITY_ERR              BIT(10)
+#define MACEPCI_CONTROL_MRMRA_ENA               BIT(11)
+#define MACEPCI_CONTROL_ARB_N3                  BIT(12)
+#define MACEPCI_CONTROL_ARB_N4                  BIT(13)
+#define MACEPCI_CONTROL_ARB_N5                  BIT(14)
+#define MACEPCI_CONTROL_PARK_LIU                BIT(15)
+#define MACEPCI_CONTROL_INV_INT(x)              BIT(16+x)
+#define MACEPCI_CONTROL_INV_INT_MASK            0x00ff0000
+#define MACEPCI_CONTROL_OVERRUN_INT             BIT(24)
+#define MACEPCI_CONTROL_PARITY_INT              BIT(25)
+#define MACEPCI_CONTROL_SERR_INT                BIT(26)
+#define MACEPCI_CONTROL_IT_INT                  BIT(27)
+#define MACEPCI_CONTROL_RE_INT                  BIT(28)
+#define MACEPCI_CONTROL_DPED_INT                BIT(29)
+#define MACEPCI_CONTROL_TAR_INT                 BIT(30)
+#define MACEPCI_CONTROL_MAR_INT                 BIT(31)
+        volatile unsigned int rev;
+        unsigned int _pad[0xcf8/4 - 4];
+        volatile unsigned int config_addr;
+        union {
+                volatile unsigned char b[4];
+                volatile unsigned short w[2];
+                volatile unsigned int l;
+        } config_data;
+};
+#define MACEPCI_LOW_MEMORY              0x1a000000
+#define MACEPCI_LOW_IO                  0x18000000
+#define MACEPCI_SWAPPED_VIEW            0
+#define MACEPCI_NATIVE_VIEW             0x40000000
+#define MACEPCI_IO                      0x80000000
+#define MACEPCI_HI_MEMORY               0x280000000
+#define MACEPCI_HI_IO                   0x100000000
+
+/*
+ * Video interface
+ */
+struct mace_video {
+        unsigned long xxx;      /* later... */
+};
+
+/* 
+ * Ethernet interface
+ */
+struct mace_ethernet {
+        volatile unsigned long mac_ctrl;
+        volatile unsigned long int_stat;
+        volatile unsigned long dma_ctrl;
+        volatile unsigned long timer;
+        volatile unsigned long tx_int_al;
+        volatile unsigned long rx_int_al;
+        volatile unsigned long tx_info;
+        volatile unsigned long tx_info_al;
+        volatile unsigned long rx_buff;
+        volatile unsigned long rx_buff_al1;
+        volatile unsigned long rx_buff_al2;
+        volatile unsigned long diag;
+        volatile unsigned long phy_data;
+        volatile unsigned long phy_regs;
+        volatile unsigned long phy_trans_go;
+        volatile unsigned long backoff_seed;
+        /*===================================*/
+        volatile unsigned long imq_reserved[4];
+        volatile unsigned long mac_addr;
+        volatile unsigned long mac_addr2;
+        volatile unsigned long mcast_filter;
+        volatile unsigned long tx_ring_base;
+        /* Following are read-only registers for debugging */
+        volatile unsigned long tx_pkt1_hdr;
+        volatile unsigned long tx_pkt1_ptr[3];
+        volatile unsigned long tx_pkt2_hdr;
+        volatile unsigned long tx_pkt2_ptr[3];
+        /*===================================*/
+        volatile unsigned long rx_fifo;
+};
+
+/* 
+ * Peripherals
+ */
+
+/* Audio registers */
+struct mace_audio {
+        volatile unsigned long control;
+        volatile unsigned long codec_control;           /* codec status control */
+        volatile unsigned long codec_mask;              /* codec status input mask */
+        volatile unsigned long codec_read;              /* codec status read data */
+        struct {
+                volatile unsigned long control;         /* channel control */
+                volatile unsigned long read_ptr;        /* channel read pointer */
+                volatile unsigned long write_ptr;       /* channel write pointer */
+                volatile unsigned long depth;           /* channel depth */
+        } chan[3];
+};
+
+/* ISA Control and DMA registers */
+struct mace_isactrl {
+        volatile unsigned long ringbase;
+#define MACEISA_RINGBUFFERS_SIZE        (8 * 4096)
+
+        volatile unsigned long misc;
+#define MACEISA_FLASH_WE                BIT(0)  /* 1=> Enable FLASH writes */
+#define MACEISA_PWD_CLEAR               BIT(1)  /* 1=> PWD CLEAR jumper detected */
+#define MACEISA_NIC_DEASSERT            BIT(2)
+#define MACEISA_NIC_DATA                BIT(3)
+#define MACEISA_LED_RED                 BIT(4)  /* 0=> Illuminate red LED */
+#define MACEISA_LED_GREEN               BIT(5)  /* 0=> Illuminate green LED */
+#define MACEISA_DP_RAM_ENABLE           BIT(6)
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+#define MACEISA_AUDIO_SW_INT            BIT(0)
+#define MACEISA_AUDIO_SC_INT            BIT(1)
+#define MACEISA_AUDIO1_DMAT_INT         BIT(2)
+#define MACEISA_AUDIO1_OF_INT           BIT(3)
+#define MACEISA_AUDIO2_DMAT_INT         BIT(4)
+#define MACEISA_AUDIO2_MERR_INT         BIT(5)
+#define MACEISA_AUDIO3_DMAT_INT         BIT(6)
+#define MACEISA_AUDIO3_MERR_INT         BIT(7)
+#define MACEISA_RTC_INT                 BIT(8)
+#define MACEISA_KEYB_INT                BIT(9)
+#define MACEISA_KEYB_POLL_INT           BIT(10)
+#define MACEISA_MOUSE_INT               BIT(11)
+#define MACEISA_MOUSE_POLL_INT          BIT(12)
+#define MACEISA_TIMER0_INT              BIT(13)
+#define MACEISA_TIMER1_INT              BIT(14)
+#define MACEISA_TIMER2_INT              BIT(15)
+#define MACEISA_PARALLEL_INT            BIT(16)
+#define MACEISA_PAR_CTXA_INT            BIT(17)
+#define MACEISA_PAR_CTXB_INT            BIT(18)
+#define MACEISA_PAR_MERR_INT            BIT(19)
+#define MACEISA_SERIAL1_INT             BIT(20)
+#define MACEISA_SERIAL1_TDMAT_INT       BIT(21)
+#define MACEISA_SERIAL1_TDMAPR_INT      BIT(22)
+#define MACEISA_SERIAL1_TDMAME_INT      BIT(23)
+#define MACEISA_SERIAL1_RDMAT_INT       BIT(24)
+#define MACEISA_SERIAL1_RDMAOR_INT      BIT(25)
+#define MACEISA_SERIAL2_INT             BIT(26)
+#define MACEISA_SERIAL2_TDMAT_INT       BIT(27)
+#define MACEISA_SERIAL2_TDMAPR_INT      BIT(28)
+#define MACEISA_SERIAL2_TDMAME_INT      BIT(29)
+#define MACEISA_SERIAL2_RDMAT_INT       BIT(30)
+#define MACEISA_SERIAL2_RDMAOR_INT      BIT(31)
+
+        volatile unsigned long _pad[0x2000/8 - 4];
+
+        volatile unsigned long dp_ram[0x400];
+};
+
+/* Keyboard & Mouse registers
+ * -> drivers/input/serio/maceps2.c */
+struct mace_ps2port {
+        volatile unsigned long tx;
+        volatile unsigned long rx;
+        volatile unsigned long control;
+        volatile unsigned long status;
+};
+
+struct mace_ps2 {
+        struct mace_ps2port keyb;
+        struct mace_ps2port mouse;
+};
+
+/* I2C registers
+ * -> drivers/i2c/algos/i2c-algo-sgi.c */
+struct mace_i2c {
+        volatile unsigned long config;
+#define MACEI2C_RESET           BIT(0)
+#define MACEI2C_FAST            BIT(1)
+#define MACEI2C_DATA_OVERRIDE   BIT(2)
+#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
+#define MACEI2C_DATA_STATUS     BIT(4)
+#define MACEI2C_CLOCK_STATUS    BIT(5)
+        volatile unsigned long control;
+        volatile unsigned long data;
+};
+
+/* Timer registers */
+typedef union {
+        volatile unsigned long ust_msc;
+        struct reg {
+                volatile unsigned int ust;
+                volatile unsigned int msc;
+        } reg;
+} timer_reg;
+
+struct mace_timers {
+        volatile unsigned long ust;
+#define MACE_UST_PERIOD_NS      960
+
+        volatile unsigned long compare1;
+        volatile unsigned long compare2;
+        volatile unsigned long compare3;
+
+        timer_reg audio_in;
+        timer_reg audio_out1;
+        timer_reg audio_out2;
+        timer_reg video_in1;
+        timer_reg video_in2;
+        timer_reg video_out;    
+};
+
+struct mace_perif {
+        struct mace_audio audio;
+        char _pad0[0x10000 - sizeof(struct mace_audio)];
+
+        struct mace_isactrl ctrl;
+        char _pad1[0x10000 - sizeof(struct mace_isactrl)];
+
+        struct mace_ps2 ps2;
+        char _pad2[0x10000 - sizeof(struct mace_ps2)];
+
+        struct mace_i2c i2c;
+        char _pad3[0x10000 - sizeof(struct mace_i2c)];
+
+        struct mace_timers timers;
+        char _pad4[0x10000 - sizeof(struct mace_timers)];
+};
+
+
+/* 
+ * ISA peripherals
+ */
+
+/* Parallel port */
+struct mace_parallel {  /* later... */
+};
+
+struct mace_ecp1284 {   /* later... */
+};
+
+/* Serial port */
+struct mace_serial {
+        volatile unsigned long xxx;     /* later... */
+};
+
+struct mace_isa {
+        struct mace_parallel parallel;
+        char _pad1[0x8000 - sizeof(struct mace_parallel)];
+
+        struct mace_ecp1284 ecp1284;
+        char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
+
+        struct mace_serial serial1;
+        char _pad3[0x8000 - sizeof(struct mace_serial)];
+
+        struct mace_serial serial2;
+        char _pad4[0x8000 - sizeof(struct mace_serial)];
+
+        volatile unsigned char rtc[0x10000];
+};
+
+struct sgi_mace {
+        char _reserved[0x80000];
+
+        struct mace_pci pci;
+        char _pad0[0x80000 - sizeof(struct mace_pci)];
+
+        struct mace_video video_in1;
+        char _pad1[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_in2;
+        char _pad2[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_out;
+        char _pad3[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_ethernet eth;
+        char _pad4[0x80000 - sizeof(struct mace_ethernet)];
+
+        struct mace_perif perif;
+        char _pad5[0x80000 - sizeof(struct mace_perif)];
+
+        struct mace_isa isa;
+        char _pad6[0x80000 - sizeof(struct mace_isa)];
+};
+
+extern struct sgi_mace *mace;
+
+#endif /* __ASM_MACE_H__ */
diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h
new file mode 100644
index 000000000000..e440fdf4b232
--- /dev/null
+++ b/include/asm-mips/ip32/machine.h
@@ -0,0 +1,21 @@
+/*
+ * machine.h -- Machine/group probing for ip32
+ *
+ * Copyright (C) 2001 Keith M Wesolowski
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_IP32_MACHINE_H
+#define _ASM_IP32_MACHINE_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SGI_IP32
+
+#define SGI_MACH_O2             0x3201
+
+#endif /* CONFIG_SGI_IP32 */
+
+#endif /* _ASM_SGI_MACHINE_H */
diff --git a/include/asm-mips/ipc.h b/include/asm-mips/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-mips/ipc.h
@@ -0,0 +1 @@
+#include <asm-generic/ipc.h>
diff --git a/include/asm-mips/ipcbuf.h b/include/asm-mips/ipcbuf.h
new file mode 100644
index 000000000000..d47d08f264e7
--- /dev/null
+++ b/include/asm-mips/ipcbuf.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_IPCBUF_H
+#define _ASM_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for alpha architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned short  seq;
+        unsigned short  __pad1;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_IPCBUF_H */
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
new file mode 100644
index 000000000000..b90b11d0b886
--- /dev/null
+++ b/include/asm-mips/irq.h
@@ -0,0 +1,55 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ */
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <irq.h>
+
+#ifdef CONFIG_I8259
+static inline int irq_canonicalize(int irq)
+{
+        return ((irq == 2) ? 9 : irq);
+}
+#else
+#define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
+#endif
+
+struct pt_regs;
+
+#ifdef CONFIG_PREEMPT
+
+extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
+
+#else
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ *
+ * Ideally there should be away to get this into kernel/irq/handle.c to
+ * avoid the overhead of a call for just a tiny function ...
+ */
+#define do_IRQ(irq, regs)                                               \
+do {                                                                    \
+        irq_enter();                                                    \
+        __do_IRQ((irq), (regs));                                        \
+        irq_exit();                                                     \
+} while (0)
+
+#endif
+
+extern void arch_init_irq(void);
+
+struct irqaction;
+int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+
+#endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h
new file mode 100644
index 000000000000..ed3d1e3d09ec
--- /dev/null
+++ b/include/asm-mips/irq_cpu.h
@@ -0,0 +1,20 @@
+/*
+ *      include/asm-mips/irq_cpu.h
+ *
+ *      MIPS CPU interrupt definitions.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_IRQ_CPU_H
+#define _ASM_IRQ_CPU_H
+
+extern void mips_cpu_irq_init(int irq_base);
+extern void rm7k_cpu_irq_init(int irq_base);
+extern void rm9k_cpu_irq_init(int irq_base);
+
+#endif /* _ASM_IRQ_CPU_H */
diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h
new file mode 100644
index 000000000000..7bb003511d9e
--- /dev/null
+++ b/include/asm-mips/isadep.h
@@ -0,0 +1,35 @@
+/*
+ * Various ISA level dependent constants.
+ * Most of the following constants reflect the different layout
+ * of Coprocessor 0 registers.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+#include <linux/config.h>
+
+#ifndef __ASM_ISADEP_H
+#define __ASM_ISADEP_H
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+/*
+ * R2000 or R3000
+ */
+
+/*
+ * kernel or user mode? (CP0_STATUS)
+ */
+#define KU_MASK 0x08
+#define KU_USER 0x08
+#define KU_KERN 0x00
+
+#else
+/*
+ * kernel or user mode?
+ */
+#define KU_MASK 0x18
+#define KU_USER 0x10
+#define KU_KERN 0x00
+
+#endif
+
+#endif /* __ASM_ISADEP_H */
diff --git a/include/asm-mips/it8172/it8172.h b/include/asm-mips/it8172/it8172.h
new file mode 100644
index 000000000000..8f23af0a1ee8
--- /dev/null
+++ b/include/asm-mips/it8172/it8172.h
@@ -0,0 +1,348 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      IT8172 system controller defines.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __IT8172__H__
+#define __IT8172__H__
+
+#include <asm/addrspace.h>
+
+#define IT8172_BASE                     0x18000000
+#define IT8172_PCI_IO_BASE              0x14000000
+#define IT8172_PCI_MEM_BASE             0x10000000
+
+// System registers offsets from IT8172_BASE
+#define IT_CMFPCR                       0x0
+#define IT_DSRR                         0x2
+#define IT_PCDCR                        0x4
+#define IT_SPLLCR                       0x6
+#define IT_CIDR                         0x10
+#define IT_CRNR                         0x12
+#define IT_CPUTR                        0x14
+#define IT_CTCR                         0x16
+#define IT_SDPR                         0xF0
+
+// Power management register offset from IT8172_PCI_IO_BASE
+// Power Management Device Standby Register
+#define IT_PM_DSR               0x15800
+
+#define IT_PM_DSR_TMR0SB        0x0001
+#define IT_PM_DSR_TMR1SB        0x0002
+#define IT_PM_DSR_CIR0SB        0x0004
+#define IT_PM_DSR_CIR1SB        0x0008
+#define IT_PM_DSR_SCR0SB        0x0010
+#define IT_PM_DSR_SCR1SB        0x0020
+#define IT_PM_DSR_PPSB          0x0040
+#define IT_PM_DSR_I2CSB         0x0080
+#define IT_PM_DSR_UARTSB        0x0100
+#define IT_PM_DSR_IDESB         0x0200
+#define IT_PM_DSR_ACSB          0x0400
+#define IT_PM_DSR_M68KSB        0x0800
+
+// Power Management PCI Device Software Reset Register
+#define IT_PM_PCISR             0x15802
+
+#define IT_PM_PCISR_IDESR       0x0001
+#define IT_PM_PCISR_CDMASR      0x0002
+#define IT_PM_PCISR_USBSR       0x0004
+#define IT_PM_PCISR_DMASR       0x0008
+#define IT_PM_PCISR_ACSR        0x0010
+#define IT_PM_PCISR_MEMSR       0x0020
+#define IT_PM_PCISR_68KSR       0x0040
+
+
+// PCI Configuration address and data register offsets
+// from IT8172_BASE
+#define IT_CONFADDR                     0x4000
+#define IT_BUSNUM_SHF                   16
+#define IT_DEVNUM_SHF                   11
+#define IT_FUNCNUM_SHF                  8
+#define IT_REGNUM_SHF                   2
+
+#define IT_CONFDATA                     0x4004
+
+// PCI configuration header common register offsets
+#define IT_VID                          0x00
+#define IT_DID                          0x02
+#define IT_PCICMD                       0x04
+#define IT_PCISTS                       0x06
+#define IT_RID                          0x08
+#define IT_CLASSC                       0x09
+#define IT_HEADT                        0x0E
+#define IT_SERIRQC                      0x49
+
+// PCI to Internal/LPC Bus Bridge configuration header register offset
+#define IT_P2I_BCR                              0x4C
+#define IT_P2I_D0IOSC                           0x50
+#define IT_P2I_D1IOSC                           0x54
+#define IT_P2I_D2IOSC                           0x58
+#define IT_P2I_D3IOSC                           0x5C
+#define IT_P2I_D4IOSC                           0x60
+#define IT_P2I_D5IOSC                           0x64
+#define IT_P2I_D6IOSC                           0x68
+#define IT_P2I_D7IOSC                           0x6C
+#define IT_P2I_D8IOSC                           0x70
+#define IT_P2I_D9IOSC                           0x74
+#define IT_P2I_D10IOSC                          0x78
+#define IT_P2I_D11IOSC                          0x7C
+
+// Memory controller register offsets from IT8172_BASE
+#define IT_MC_SDRMR                                     0x1000
+#define IT_MC_SDRTR                                     0x1004
+#define IT_MC_MCR                                       0x1008
+#define IT_MC_SDTYPE                                    0x100C
+#define IT_MC_WPBA                                      0x1010
+#define IT_MC_WPTA                                      0x1014
+#define IT_MC_HATR                                      0x1018
+#define IT_MC_PCICR                                     0x101C
+
+// Flash/ROM control register offsets from IT8172_BASE
+#define IT_FC_BRCR                                      0x2000
+#define IT_FC_FCR                                       0x2004
+#define IT_FC_DCR                                       0x2008
+
+// M68K interface bridge configuration header register offset
+#define IT_M68K_MBCSR                                   0x54
+#define IT_M68K_TMR                                     0x58
+#define IT_M68K_BCR                                     0x5C
+#define IT_M68K_BSR                                     0x5D
+#define IT_M68K_DTR                                     0x5F
+
+// Register offset from IT8172_PCI_IO_BASE
+// These registers are accessible through 8172 PCI IO window.
+
+// INTC
+#define IT_INTC_BASE                            0x10000
+#define IT_INTC_LBDNIRR                         0x10000
+#define IT_INTC_LBDNIMR                         0x10002
+#define IT_INTC_LBDNITR                         0x10004
+#define IT_INTC_LBDNIAR                         0x10006
+#define IT_INTC_LPCNIRR                         0x10010
+#define IT_INTC_LPCNIMR                         0x10012
+#define IT_INTC_LPCNITR                         0x10014
+#define IT_INTC_LPCNIAR                         0x10016
+#define IT_INTC_PDNIRR                          0x10020
+#define IT_INTC_PDNIMR                          0x10022
+#define IT_INTC_PDNITR                          0x10024
+#define IT_INTC_PDNIAR                          0x10026
+#define IT_INTC_UMNIRR                          0x10030
+#define IT_INTC_UMNITR                          0x10034
+#define IT_INTC_UMNIAR                          0x10036
+#define IT_INTC_TYPER                           0x107FE
+
+// IT8172 PCI device number
+#define IT_C2P_DEVICE                           0
+#define IT_AUDIO_DEVICE                         1
+#define IT_DMAC_DEVICE                          1
+#define IT_CDMAC_DEVICE                         1
+#define IT_USB_DEVICE                           1
+#define IT_P2I_DEVICE                           1
+#define IT_IDE_DEVICE                           1
+#define IT_M68K_DEVICE                          1
+
+// IT8172 PCI function number
+#define IT_C2P_FUNCION                          0
+#define IT_AUDIO_FUNCTION                       0
+#define IT_DMAC_FUNCTION                        1
+#define IT_CDMAC_FUNCTION                       2
+#define IT_USB_FUNCTION                         3
+#define IT_P2I_FUNCTION                         4
+#define IT_IDE_FUNCTION                         5
+#define IT_M68K_FUNCTION                        6
+
+// IT8172 GPIO
+#define IT_GPADR                                0x13800
+#define IT_GPBDR                                0x13808
+#define IT_GPCDR                                0x13810
+#define IT_GPACR                                0x13802
+#define IT_GPBCR                                0x1380A
+#define IT_GPCCR                                0x13812
+#define IT_GPAICR                               0x13804
+#define IT_GPBICR                               0x1380C
+#define IT_GPCICR                               0x13814
+#define IT_GPAISR                               0x13806
+#define IT_GPBISR                               0x1380E
+#define IT_GPCISR                               0x13816
+#define IT_GCR                                  0x13818
+
+// IT8172 RTC
+#define IT_RTC_BASE                             0x14800
+#define IT_RTC_CENTURY                          0x14808
+
+#define IT_RTC_RIR0                             0x00
+#define IT_RTC_RTR0                             0x01
+#define IT_RTC_RIR1                             0x02
+#define IT_RTC_RTR1                             0x03
+#define IT_RTC_RIR2                             0x04
+#define IT_RTC_RTR2                             0x05
+#define IT_RTC_RCTR                             0x08
+#define IT_RTC_RA                               0x0A
+#define IT_RTC_RB                               0x0B
+#define IT_RTC_RC                               0x0C
+#define IT_RTC_RD                               0x0D
+
+#define RTC_SEC_INDEX                           0x00
+#define RTC_MIN_INDEX                           0x02
+#define RTC_HOUR_INDEX                          0x04
+#define RTC_DAY_INDEX                           0x06
+#define RTC_DATE_INDEX                          0x07
+#define RTC_MONTH_INDEX                         0x08
+#define RTC_YEAR_INDEX                          0x09
+
+// IT8172 internal device registers
+#define IT_TIMER_BASE                           0x10800
+#define IT_CIR0_BASE                            0x11000
+#define IT_UART_BASE                            0x11800
+#define IT_SCR0_BASE                            0x12000
+#define IT_SCR1_BASE                            0x12800
+#define IT_PP_BASE                              0x13000
+#define IT_I2C_BASE                             0x14000
+#define IT_CIR1_BASE                            0x15000
+
+// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
+#define IT_SCR_SFR                              0x08
+#define IT_SCR_SCDR                             0x09
+
+// IT8172 IT_SCR_SFR bit definition & mask
+#define IT_SCR_SFR_GATE_UART                    0x40
+#define IT_SCR_SFR_GATE_UART_BIT                6
+#define IT_SCR_SFR_GATE_UART_OFF                0
+#define IT_SCR_SFR_GATE_UART_ON                 1
+#define IT_SCR_SFR_FET_CHARGE                   0x30
+#define IT_SCR_SFR_FET_CHARGE_BIT               4
+#define IT_SCR_SFR_FET_CHARGE_3_3_US            3
+#define IT_SCR_SFR_FET_CHARGE_13_US             2
+#define IT_SCR_SFR_FET_CHARGE_53_US             1
+#define IT_SCR_SFR_FET_CHARGE_213_US            0
+#define IT_SCR_SFR_CARD_FREQ                    0x0C
+#define IT_SCR_SFR_CARD_FREQ_BIT                2
+#define IT_SCR_SFR_CARD_FREQ_STOP               3
+#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ            0
+#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ            2
+#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ         1
+#define IT_SCR_SFR_FET_ACTIVE                   0x02
+#define IT_SCR_SFR_FET_ACTIVE_BIT               1
+#define IT_SCR_SFR_FET_ACTIVE_INVERT            0
+#define IT_SCR_SFR_FET_ACTIVE_NONINVERT         1
+#define IT_SCR_SFR_ENABLE                       0x01
+#define IT_SCR_SFR_ENABLE_BIT                   0
+#define IT_SCR_SFR_ENABLE_OFF                   0
+#define IT_SCR_SFR_ENABLE_ON                    1
+
+// IT8172 IT_SCR_SCDR bit definition & mask
+#define IT_SCR_SCDR_RESET_MODE                  0x80
+#define IT_SCR_SCDR_RESET_MODE_BIT              7
+#define IT_SCR_SCDR_RESET_MODE_ASYNC            0
+#define IT_SCR_SCDR_RESET_MODE_SYNC             1
+#define IT_SCR_SCDR_DIVISOR                     0x7F
+#define IT_SCR_SCDR_DIVISOR_BIT                 0
+#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1          0x00
+#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2          0x01
+#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3          0x7F
+
+// IT8172 DMA
+#define IT_DMAC_BASE                            0x16000
+#define IT_DMAC_BCAR0                           0x00
+#define IT_DMAC_BCAR1                           0x04
+#define IT_DMAC_BCAR2                           0x08
+#define IT_DMAC_BCAR3                           0x0C
+#define IT_DMAC_BCCR0                           0x02
+#define IT_DMAC_BCCR1                           0x06
+#define IT_DMAC_BCCR2                           0x0a
+#define IT_DMAC_BCCR3                           0x0e
+#define IT_DMAC_CR                              0x10
+#define IT_DMAC_SR                              0x12
+#define IT_DMAC_ESR                             0x13
+#define IT_DMAC_RQR                             0x14
+#define IT_DMAC_MR                              0x16
+#define IT_DMAC_EMR                             0x17
+#define IT_DMAC_MKR                             0x18
+#define IT_DMAC_PAR0                            0x20
+#define IT_DMAC_PAR1                            0x22
+#define IT_DMAC_PAR2                            0x24
+#define IT_DMAC_PAR3                            0x26
+
+// IT8172 IDE
+#define IT_IDE_BASE                             0x17800
+#define IT_IDE_STATUS                           0x1F7
+
+// IT8172 Audio Controller
+#define IT_AC_BASE                              0x17000
+#define IT_AC_PCMOV                             0x00
+#define IT_AC_FMOV                              0x02
+#define IT_AC_I2SV                              0x04
+#define IT_AC_DRSS                              0x06
+#define IT_AC_PCC                               0x08
+#define IT_AC_PCDL                              0x0A
+#define IT_AC_PCB1STA                           0x0C
+#define IT_AC_PCB2STA                           0x10
+#define IT_AC_CAPCC                             0x14
+#define IT_AC_CAPCDL                            0x16
+#define IT_AC_CAPB1STA                          0x18
+#define IT_AC_CAPB2STA                          0x1C
+#define IT_AC_CODECC                            0x22
+#define IT_AC_I2SMC                             0x24
+#define IT_AC_VS                                0x26
+#define IT_AC_SRCS                              0x28
+#define IT_AC_CIRCP                             0x2A
+#define IT_AC_CIRDP                             0x2C
+#define IT_AC_TM                                0x4A
+#define IT_AC_PFDP                              0x4C
+#define IT_AC_GC                                0x54
+#define IT_AC_IMC                               0x56
+#define IT_AC_ISC                               0x5B
+#define IT_AC_OPL3SR                            0x68
+#define IT_AC_OPL3DWDR                          0x69
+#define IT_AC_OPL3AB1W                          0x6A
+#define IT_AC_OPL3DW                            0x6B
+#define IT_AC_BPDC                              0x70
+
+
+// IT8172 Timer
+#define IT_TIMER_BASE                           0x10800
+#define TIMER_TCVR0                             0x00
+#define TIMER_TRVR0                             0x02
+#define TIMER_TCR0                              0x04
+#define TIMER_TIRR                              0x06
+#define TIMER_TCVR1                             0x08
+#define TIMER_TRVR1                             0x0A
+#define TIMER_TCR1                              0x0C
+#define TIMER_TIDR                              0x0E
+
+
+#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
+#define IT_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
+
+#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
+#define IT_IO_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
+
+#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
+#define IT_IO_READ16(ofs, data)  data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
+
+#endif
diff --git a/include/asm-mips/it8172/it8172_cir.h b/include/asm-mips/it8172/it8172_cir.h
new file mode 100644
index 000000000000..6a1dbd29f6d1
--- /dev/null
+++ b/include/asm-mips/it8172/it8172_cir.h
@@ -0,0 +1,140 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      IT8172 Consumer IR port defines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define NUM_CIR_PORTS 2
+
+/* Master Control Register */
+#define CIR_RESET              0x1
+#define CIR_FIFO_CLEAR         0x2
+#define CIR_SET_FIFO_TL(x)     (((x)&0x3)<<2)
+#define CIR_ILE                0x10
+#define CIR_ILSEL              0x20
+
+/* Interrupt Enable Register */
+#define CIR_TLDLIE             0x1
+#define CIR_RDAIE              0x2
+#define CIR_RFOIE              0x4
+#define CIR_IEC                0x80
+
+/* Interrupt Identification Register */
+#define CIR_TLDLI              0x1
+#define CIR_RDAI               0x2
+#define CIR_RFOI               0x4
+#define CIR_NIP                0x80
+
+/* Carrier Frequency Register */
+#define CIR_SET_CF(x)          ((x)&0x1f)
+  #define CFQ_38_480           0xB       /* 38 KHz low, 480 KHz high */
+#define CIR_HCFS               0x20
+  #define CIR_SET_HS(x)        (((x)&0x1)<<5)
+
+
+/* Receiver Control Register */
+#define CIR_SET_RXDCR(x)       ((x)&0x7)
+#define CIR_RXACT              0x8
+#define CIR_RXEND              0x10
+#define CIR_RDWOS              0x20
+  #define CIR_SET_RDWOS(x)     (((x)&0x1)<<5)
+#define CIR_RXEN               0x80
+
+/* Transmitter Control Register */
+#define CIR_SET_TXMPW(x)       ((x)&0x7)
+#define CIR_SET_TXMPM(x)       (((x)&0x3)<<3)
+#define CIR_TXENDF             0x20
+#define CIR_TXRLE              0x40
+
+/* Receiver FIFO Status Register */
+#define CIR_RXFBC_MASK         0x3f
+#define CIR_RXFTO              0x80
+
+/* Wakeup Code Length Register */
+#define CIR_SET_WCL            ((x)&0x3f)
+#define CIR_WCL_MASK(x)        ((x)&0x3f)
+
+/* Wakeup Power Control/Status Register */
+#define CIR_BTMON              0x2
+#define CIR_CIRON              0x4
+#define CIR_RCRST              0x10
+#define CIR_WCRST              0x20
+
+struct cir_port {
+        int port;
+        unsigned short baud_rate;
+        unsigned char fifo_tl;
+        unsigned char cfq;
+        unsigned char hcfs;
+        unsigned char rdwos;
+        unsigned char rxdcr;
+};
+
+struct it8172_cir_regs {
+        unsigned char dr;       /* data                        */
+        char pad;
+        unsigned char mstcr;    /* master control              */
+        char pad1;
+        unsigned char ier;      /* interrupt enable            */
+        char pad2;
+        unsigned char iir;      /* interrupt identification    */
+        char pad3;
+        unsigned char cfr;      /* carrier frequency           */
+        char pad4;
+        unsigned char rcr;      /* receiver control            */
+        char pad5;
+        unsigned char tcr;      /* transmitter control         */
+        char pad6;
+        char pad7;
+        char pad8;
+        unsigned char bdlr;     /* baud rate divisor low byte  */
+        char pad9;
+        unsigned char bdhr;     /* baud rate divisor high byte */
+        char pad10;
+        unsigned char tfsr;     /* tx fifo byte count          */
+        char pad11;
+        unsigned char rfsr;     /* rx fifo status              */
+        char pad12;
+        unsigned char wcl;      /* wakeup code length          */
+        char pad13;
+        unsigned char wcr;      /* wakeup code read/write      */
+        char pad14;
+        unsigned char wps;      /* wakeup power control/status */
+};
+
+int cir_port_init(struct cir_port *cir);
+extern void clear_fifo(struct cir_port *cir);
+extern void enable_receiver(struct cir_port *cir);
+extern void disable_receiver(struct cir_port *cir);
+extern void enable_rx_demodulation(struct cir_port *cir);
+extern void disable_rx_demodulation(struct cir_port *cir);
+extern void set_rx_active(struct cir_port *cir);
+extern void int_enable(struct cir_port *cir);
+extern void rx_int_enable(struct cir_port *cir);
+extern char get_int_status(struct cir_port *cir);
+extern int cir_get_rx_count(struct cir_port *cir);
+extern char cir_read_data(struct cir_port *cir);
diff --git a/include/asm-mips/it8172/it8172_dbg.h b/include/asm-mips/it8172/it8172_dbg.h
new file mode 100644
index 000000000000..f404ec7c03ac
--- /dev/null
+++ b/include/asm-mips/it8172/it8172_dbg.h
@@ -0,0 +1,38 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Function prototypes for low level uart routines to
+ *      directly access a 16550 uart.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+
+extern void putch(const unsigned char c);
+extern void puts(unsigned char *cp);
+extern void fputs(unsigned char *cp);
+extern void put64(uint64_t ul);
+extern void put32(unsigned u);
diff --git a/include/asm-mips/it8172/it8172_int.h b/include/asm-mips/it8172/it8172_int.h
new file mode 100644
index 000000000000..837e83ac25f5
--- /dev/null
+++ b/include/asm-mips/it8172/it8172_int.h
@@ -0,0 +1,144 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      ITE 8172 Interrupt Numbering
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _MIPS_ITEINT_H
+#define _MIPS_ITEINT_H
+
+/*
+ * Here's the "strategy":
+ * We number the LPC serial irqs from 0 to 15,
+ * the local bus irqs from 16 to 31,
+ * the pci dev register interrupts from 32 to 47,
+ * and the non-maskable ints from 48 to 53.
+ */
+
+#define IT8172_LPC_IRQ_BASE  0    /* first LPC int number */
+#define IT8172_SERIRQ_0      (IT8172_LPC_IRQ_BASE + 0)
+#define IT8172_SERIRQ_1      (IT8172_LPC_IRQ_BASE + 1)
+#define IT8172_SERIRQ_2      (IT8172_LPC_IRQ_BASE + 2)
+#define IT8172_SERIRQ_3      (IT8172_LPC_IRQ_BASE + 3)
+#define IT8172_SERIRQ_4      (IT8172_LPC_IRQ_BASE + 4)
+#define IT8172_SERIRQ_5      (IT8172_LPC_IRQ_BASE + 5)
+#define IT8172_SERIRQ_6      (IT8172_LPC_IRQ_BASE + 6)
+#define IT8172_SERIRQ_7      (IT8172_LPC_IRQ_BASE + 7)
+#define IT8172_SERIRQ_8      (IT8172_LPC_IRQ_BASE + 8)
+#define IT8172_SERIRQ_9      (IT8172_LPC_IRQ_BASE + 9)
+#define IT8172_SERIRQ_10     (IT8172_LPC_IRQ_BASE + 10)
+#define IT8172_SERIRQ_11     (IT8172_LPC_IRQ_BASE + 11)
+#define IT8172_SERIRQ_12     (IT8172_LPC_IRQ_BASE + 12)
+#define IT8172_SERIRQ_13     (IT8172_LPC_IRQ_BASE + 13)
+#define IT8172_SERIRQ_14     (IT8172_LPC_IRQ_BASE + 14)
+#define IT8172_SERIRQ_15     (IT8172_LPC_IRQ_BASE + 15)
+
+#define IT8172_LB_IRQ_BASE  16   /* first local bus int number */
+#define IT8172_PPR_IRQ          (IT8172_LB_IRQ_BASE + 0) /* parallel port */
+#define IT8172_TIMER0_IRQ       (IT8172_LB_IRQ_BASE + 1)
+#define IT8172_TIMER1_IRQ       (IT8172_LB_IRQ_BASE + 2)
+#define IT8172_I2C_IRQ          (IT8172_LB_IRQ_BASE + 3)
+#define IT8172_GPIO_IRQ         (IT8172_LB_IRQ_BASE + 4)
+#define IT8172_CIR0_IRQ         (IT8172_LB_IRQ_BASE + 5)
+#define IT8172_CIR1_IRQ         (IT8172_LB_IRQ_BASE + 6)
+#define IT8172_UART_IRQ         (IT8172_LB_IRQ_BASE + 7)
+#define IT8172_SCR0_IRQ         (IT8172_LB_IRQ_BASE + 8)
+#define IT8172_SCR1_IRQ         (IT8172_LB_IRQ_BASE + 9)
+#define IT8172_RTC_IRQ          (IT8172_LB_IRQ_BASE + 10)
+#define IT8172_IOCHK_IRQ        (IT8172_LB_IRQ_BASE + 11)
+/* 12 - 15 reserved */
+
+/*
+ * Note here that the pci dev registers includes bits for more than
+ * just the pci devices.
+ */
+#define IT8172_PCI_DEV_IRQ_BASE  32   /* first pci dev irq */
+#define IT8172_AC97_IRQ          (IT8172_PCI_DEV_IRQ_BASE + 0)
+#define IT8172_MC68K_IRQ         (IT8172_PCI_DEV_IRQ_BASE + 1)
+#define IT8172_IDE_IRQ           (IT8172_PCI_DEV_IRQ_BASE + 2)
+#define IT8172_USB_IRQ           (IT8172_PCI_DEV_IRQ_BASE + 3)
+#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
+#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
+#define IT8172_PCI_INTA_IRQ      (IT8172_PCI_DEV_IRQ_BASE + 6)
+#define IT8172_PCI_INTB_IRQ      (IT8172_PCI_DEV_IRQ_BASE + 7)
+#define IT8172_PCI_INTC_IRQ      (IT8172_PCI_DEV_IRQ_BASE + 8)
+#define IT8172_PCI_INTD_IRQ      (IT8172_PCI_DEV_IRQ_BASE + 9)
+#define IT8172_S_INTA_IRQ        (IT8172_PCI_DEV_IRQ_BASE + 10)
+#define IT8172_S_INTB_IRQ        (IT8172_PCI_DEV_IRQ_BASE + 11)
+#define IT8172_S_INTC_IRQ        (IT8172_PCI_DEV_IRQ_BASE + 12)
+#define IT8172_S_INTD_IRQ        (IT8172_PCI_DEV_IRQ_BASE + 13)
+#define IT8172_CDMA_IRQ          (IT8172_PCI_DEV_IRQ_BASE + 14)
+#define IT8172_DMA_IRQ           (IT8172_PCI_DEV_IRQ_BASE + 15)
+
+#define IT8172_NMI_IRQ_BASE      48
+#define IT8172_SER_NMI_IRQ       (IT8172_NMI_IRQ_BASE + 0)
+#define IT8172_PCI_NMI_IRQ       (IT8172_NMI_IRQ_BASE + 1)
+#define IT8172_RTC_NMI_IRQ       (IT8172_NMI_IRQ_BASE + 2)
+#define IT8172_CPUIF_NMI_IRQ     (IT8172_NMI_IRQ_BASE + 3)
+#define IT8172_PMER_NMI_IRQ      (IT8172_NMI_IRQ_BASE + 4)
+#define IT8172_POWER_NMI_IRQ     (IT8172_NMI_IRQ_BASE + 5)
+
+#define IT8172_LAST_IRQ          (IT8172_POWER_NMI_IRQ)
+/* Finally, let's move over here the mips cpu timer interrupt.
+ */
+#define MIPS_CPU_TIMER_IRQ       (NR_IRQS-1)
+
+/*
+ * IT8172 Interrupt Controller Registers
+ */
+struct it8172_intc_regs {
+        volatile unsigned short lb_req;      /* offset 0 */
+        volatile unsigned short lb_mask;
+        volatile unsigned short lb_trigger;
+        volatile unsigned short lb_level;
+        unsigned char pad0[8];
+
+        volatile unsigned short lpc_req;     /* offset 0x10 */
+        volatile unsigned short lpc_mask;
+        volatile unsigned short lpc_trigger;
+        volatile unsigned short lpc_level;
+        unsigned char pad1[8];
+
+        volatile unsigned short pci_req;     /* offset 0x20 */
+        volatile unsigned short pci_mask;
+        volatile unsigned short pci_trigger;
+        volatile unsigned short pci_level;
+        unsigned char pad2[8];
+
+        volatile unsigned short nmi_req;     /* offset 0x30 */
+        volatile unsigned short nmi_mask;
+        volatile unsigned short nmi_trigger;
+        volatile unsigned short nmi_level;
+        unsigned char pad3[6];
+
+        volatile unsigned short nmi_redir;   /* offset 0x3E */
+        unsigned char pad4[0xBE];
+
+        volatile unsigned short intstatus;    /* offset 0xFE */
+};
+
+#endif /* _MIPS_ITEINT_H */
diff --git a/include/asm-mips/it8172/it8172_pci.h b/include/asm-mips/it8172/it8172_pci.h
new file mode 100644
index 000000000000..42c61f56eeba
--- /dev/null
+++ b/include/asm-mips/it8172/it8172_pci.h
@@ -0,0 +1,108 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      IT8172 system controller specific pci defines.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _8172PCI_H_
+#define _8172PCI_H_
+
+// PCI configuration space Type0
+#define PCI_IDREG       0x00
+#define PCI_CMDSTSREG   0x04
+#define PCI_CLASSREG    0x08
+#define PCI_BHLCREG     0x0C
+#define PCI_BASE1REG    0x10
+#define PCI_BASE2REG    0x14
+#define PCI_BASE3REG    0x18
+#define PCI_BASE4REG    0x1C
+#define PCI_BASE5REG    0x20
+#define PCI_BASE6REG    0x24
+#define PCI_ROMBASEREG  0x30
+#define PCI_INTRREG     0x3C
+
+// PCI configuration space Type1
+#define PCI_BUSNOREG    0x18
+
+#define IT_PCI_VENDORID(x)      ((x) & 0xFFFF)
+#define IT_PCI_DEVICEID(x)      (((x)>>16) & 0xFFFF)
+
+// Command register
+#define PCI_CMD_IOEN            0x00000001
+#define PCI_CMD_MEMEN           0x00000002
+#define PCI_CMD_BUSMASTER       0x00000004
+#define PCI_CMD_SPCYCLE         0x00000008
+#define PCI_CMD_WRINV           0x00000010
+#define PCI_CMD_VGASNOOP        0x00000020
+#define PCI_CMD_PERR            0x00000040
+#define PCI_CMD_WAITCTRL        0x00000080
+#define PCI_CMD_SERR            0x00000100
+#define PCI_CMD_FAST_BACKTOBACK 0x00000200
+
+// Status register
+#define PCI_STS_66MHZ           0x00200000
+#define PCI_STS_SUPPORT_UDF     0x00400000
+#define PCI_STS_FAST_BACKTOBACK 0x00800000
+#define PCI_STS_DATA_PERR       0x01000000
+#define PCI_STS_DEVSEL0         0x02000000
+#define PCI_STS_DEVSEL1         0x04000000
+#define PCI_STS_SIG_TGTABORT    0x08000000
+#define PCI_STS_RCV_TGTABORT    0x10000000
+#define PCI_STS_RCV_MSTABORT    0x20000000
+#define PCI_STS_SYSERR          0x40000000
+#define PCI_STS_DETCT_PERR      0x80000000
+
+#define IT_PCI_CLASS(x)         (((x)>>24) & 0xFF)
+#define IT_PCI_SUBCLASS(x)              (((x)>>16) & 0xFF)
+#define IT_PCI_INTERFACE(x)     (((x)>>8) & 0xFF)
+#define IT_PCI_REVISION(x)              ((x) & 0xFF)
+
+// PCI class code
+#define PCI_CLASS_BRIDGE                        0x06
+
+// bridge subclass
+#define PCI_SUBCLASS_BRIDGE_HOST                0x00
+#define PCI_SUBCLASS_BRIDGE_PCI                 0x04
+
+// BHLCREG
+#define IT_PCI_BIST(x)          (((x)>>24) & 0xFF)
+#define IT_PCI_HEADERTYPE(x)    (((x)>>16) & 0xFF)
+#define IT_PCI_LATENCYTIMER(x)  (((x)>>8) & 0xFF)
+#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
+
+#define PCI_MULTIFUNC   0x80
+
+// INTRREG
+#define IT_PCI_MAXLAT(x)                (((x)>>24) & 0xFF)
+#define IT_PCI_MINGNT(x)                (((x)>>16) & 0xFF)
+#define IT_PCI_INTRPIN(x)               (((x)>>8) & 0xFF)
+#define IT_PCI_INTRLINE(x)              ((x) & 0xFF)
+
+#define PCI_VENDOR_NEC  0x1033
+#define PCI_VENDOR_DEC  0x1101
+
+#endif // _8172PCI_H_
diff --git a/include/asm-mips/it8712.h b/include/asm-mips/it8712.h
new file mode 100644
index 000000000000..ca2dee02a011
--- /dev/null
+++ b/include/asm-mips/it8712.h
@@ -0,0 +1,28 @@
+
+#ifndef __IT8712_H__
+#define __IT8712_H__
+
+#define LPC_BASE_ADDR   0x14000000
+
+// MB PnP configuration register
+#define LPC_KEY_ADDR    0x1400002E
+#define LPC_DATA_ADDR   0x1400002F
+
+// Device LDN
+#define LDN_SERIAL1     0x01
+#define LDN_SERIAL2     0x02
+#define LDN_PARALLEL    0x03
+#define LDN_KEYBOARD    0x05
+#define LDN_MOUSE       0x06
+
+#define IT8712_UART1_PORT      0x3F8
+#define IT8712_UART2_PORT      0x2F8
+
+#ifndef ASM_ONLY
+
+void LPCSetConfig(char LdnNumber, char Index, char data);
+char LPCGetConfig(char LdnNumber, char Index);
+
+#endif
+
+#endif
diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h
new file mode 100644
index 000000000000..81cbf004fd13
--- /dev/null
+++ b/include/asm-mips/jazz.h
@@ -0,0 +1,322 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
+ */
+#ifndef __ASM_JAZZ_H
+#define __ASM_JAZZ_H
+
+/*
+ * The addresses below are virtual address. The mappings are
+ * created on startup via wired entries in the tlb. The Mips
+ * Magnum R3000 and R4000 machines are similar in many aspects,
+ * but many hardware register are accessible at 0xb9000000 in
+ * instead of 0xe0000000.
+ */
+
+#define JAZZ_LOCAL_IO_SPACE     0xe0000000
+
+/*
+ * Revision numbers in PICA_ASIC_REVISION
+ *
+ * 0xf0000000 - Rev1
+ * 0xf0000001 - Rev2
+ * 0xf0000002 - Rev3
+ */
+#define PICA_ASIC_REVISION      0xe0000008
+
+/*
+ * The segments of the seven segment LED are mapped
+ * to the control bits as follows:
+ *
+ *         (7)
+ *      ---------
+ *      |       |
+ *  (2) |       | (6)
+ *      |  (1)  |
+ *      ---------
+ *      |       |
+ *  (3) |       | (5)
+ *      |  (4)  |
+ *      --------- . (0)
+ */
+#define PICA_LED                0xe000f000
+
+/*
+ * Some characters for the LED control registers
+ * The original Mips machines seem to have a LED display
+ * with integrated decoder while the Acer machines can
+ * control each of the seven segments and the dot independently.
+ * It's only a toy, anyway...
+ */
+#define LED_DOT                 0x01
+#define LED_SPACE               0x00
+#define LED_0                   0xfc
+#define LED_1                   0x60
+#define LED_2                   0xda
+#define LED_3                   0xf2
+#define LED_4                   0x66
+#define LED_5                   0xb6
+#define LED_6                   0xbe
+#define LED_7                   0xe0
+#define LED_8                   0xfe
+#define LED_9                   0xf6
+#define LED_A                   0xee
+#define LED_b                   0x3e
+#define LED_C                   0x9c
+#define LED_d                   0x7a
+#define LED_E                   0x9e
+#define LED_F                   0x8e
+
+#ifndef __ASSEMBLY__
+
+static __inline__ void pica_set_led(unsigned int bits)
+{
+        volatile unsigned int *led_register = (unsigned int *) PICA_LED;
+
+        *led_register = bits;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Base address of the Sonic Ethernet adapter in Jazz machines.
+ */
+#define JAZZ_ETHERNET_BASE  0xe0001000
+
+/*
+ * Base address of the 53C94 SCSI hostadapter in Jazz machines.
+ */
+#define JAZZ_SCSI_BASE          0xe0002000
+
+/*
+ * i8042 keyboard controller for JAZZ and PICA chipsets.
+ * This address is just a guess and seems to differ from
+ * other mips machines such as RC3xxx...
+ */
+#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
+#define JAZZ_KEYBOARD_DATA      0xe0005000
+#define JAZZ_KEYBOARD_COMMAND   0xe0005001
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned char data;
+        unsigned char command;
+} jazz_keyboard_hardware;
+
+#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
+
+typedef struct {
+        unsigned char pad0[3];
+        unsigned char data;
+        unsigned char pad1[3];
+        unsigned char command;
+} mips_keyboard_hardware;
+
+/*
+ * For now. Needs to be changed for RC3xxx support. See below.
+ */
+#define keyboard_hardware       jazz_keyboard_hardware
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * i8042 keyboard controller for most other Mips machines.
+ */
+#define MIPS_KEYBOARD_ADDRESS   0xb9005000
+#define MIPS_KEYBOARD_DATA      0xb9005003
+#define MIPS_KEYBOARD_COMMAND   0xb9005007
+
+/*
+ * Serial and parallel ports (WD 16C552) on the Mips JAZZ
+ */
+#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
+#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
+#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
+
+/*
+ * Dummy Device Address. Used in jazzdma.c
+ */
+#define JAZZ_DUMMY_DEVICE       0xe000d000
+
+/*
+ * JAZZ timer registers and interrupt no.
+ * Note that the hardware timer interrupt is actually on
+ * cpu level 6, but to keep compatibility with PC stuff
+ * it is remapped to vector 0. See arch/mips/kernel/entry.S.
+ */
+#define JAZZ_TIMER_INTERVAL     0xe0000228
+#define JAZZ_TIMER_REGISTER     0xe0000230
+
+/*
+ * DRAM configuration register
+ */
+#ifndef __ASSEMBLY__
+#ifdef __MIPSEL__
+typedef struct {
+        unsigned int bank2 : 3;
+        unsigned int bank1 : 3;
+        unsigned int mem_bus_width : 1;
+        unsigned int reserved2 : 1;
+        unsigned int page_mode : 1;
+        unsigned int reserved1 : 23;
+} dram_configuration;
+#else /* defined (__MIPSEB__) */
+typedef struct {
+        unsigned int reserved1 : 23;
+        unsigned int page_mode : 1;
+        unsigned int reserved2 : 1;
+        unsigned int mem_bus_width : 1;
+        unsigned int bank1 : 3;
+        unsigned int bank2 : 3;
+} dram_configuration;
+#endif
+#endif /* !__ASSEMBLY__ */
+
+#define PICA_DRAM_CONFIG        0xe00fffe0
+
+/*
+ * JAZZ interrupt control registers
+ */
+#define JAZZ_IO_IRQ_SOURCE      0xe0010000
+#define JAZZ_IO_IRQ_ENABLE      0xe0010002
+
+/*
+ * JAZZ interrupt enable bits
+ */
+#define JAZZ_IE_PARALLEL            (1 << 0)
+#define JAZZ_IE_FLOPPY              (1 << 1)
+#define JAZZ_IE_SOUND               (1 << 2)
+#define JAZZ_IE_VIDEO               (1 << 3)
+#define JAZZ_IE_ETHERNET            (1 << 4)
+#define JAZZ_IE_SCSI                (1 << 5)
+#define JAZZ_IE_KEYBOARD            (1 << 6)
+#define JAZZ_IE_MOUSE               (1 << 7)
+#define JAZZ_IE_SERIAL1             (1 << 8)
+#define JAZZ_IE_SERIAL2             (1 << 9)
+
+/*
+ * JAZZ Interrupt Level definitions
+ *
+ * This is somewhat broken.  For reasons which nobody can remember anymore
+ * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
+ */
+#define JAZZ_PARALLEL_IRQ       16
+#define JAZZ_FLOPPY_IRQ         17
+#define JAZZ_SOUND_IRQ          18
+#define JAZZ_VIDEO_IRQ          19
+#define JAZZ_ETHERNET_IRQ       20
+#define JAZZ_SCSI_IRQ           21
+#define JAZZ_KEYBOARD_IRQ       22
+#define JAZZ_MOUSE_IRQ          23
+#define JAZZ_SERIAL1_IRQ        24
+#define JAZZ_SERIAL2_IRQ        25
+
+#define JAZZ_TIMER_IRQ          31
+
+
+/*
+ * JAZZ DMA Channels
+ * Note: Channels 4...7 are not used with respect to the Acer PICA-61
+ * chipset which does not provide these DMA channels.
+ */
+#define JAZZ_SCSI_DMA           0              /* SCSI */
+#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
+#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
+#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
+
+/*
+ * JAZZ R4030 MCT_ADR chip (DMA controller)
+ * Note: Virtual Addresses !
+ */
+#define JAZZ_R4030_CONFIG       0xE0000000      /* R4030 config register */
+#define JAZZ_R4030_REVISION     0xE0000008      /* same as PICA_ASIC_REVISION */
+#define JAZZ_R4030_INV_ADDR     0xE0000010      /* Invalid Address register */
+
+#define JAZZ_R4030_TRSTBL_BASE  0xE0000018      /* Translation Table Base */
+#define JAZZ_R4030_TRSTBL_LIM   0xE0000020      /* Translation Table Limit */
+#define JAZZ_R4030_TRSTBL_INV   0xE0000028      /* Translation Table Invalidate */
+
+#define JAZZ_R4030_CACHE_MTNC   0xE0000030      /* Cache Maintenance */
+#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038      /* Remote Failed Address */
+#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040      /* Memory Failed Address */
+
+#define JAZZ_R4030_CACHE_PTAG   0xE0000048      /* I/O Cache Physical Tag */
+#define JAZZ_R4030_CACHE_LTAG   0xE0000050      /* I/O Cache Logical Tag */
+#define JAZZ_R4030_CACHE_BMASK  0xE0000058      /* I/O Cache Byte Mask */
+#define JAZZ_R4030_CACHE_BWIN   0xE0000060      /* I/O Cache Buffer Window */
+
+/*
+ * Remote Speed Registers.
+ *
+ *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
+ *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
+ *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
+ * 12: reserved, 13: free,     14: 7seg LED, 15: ???
+ */
+#define JAZZ_R4030_REM_SPEED    0xE0000070      /* 16 Remote Speed Registers */
+                                                /* 0xE0000070,78,80... 0xE00000E8 */
+#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8      /* Internal Interrupt Enable */
+#define JAZZ_R4030_INVAL_ADDR   0xE0000010      /* Invalid address Register */
+#define JAZZ_R4030_IRQ_SOURCE   0xE0000200      /* Interrupt Source Register */
+#define JAZZ_R4030_I386_ERROR   0xE0000208      /* i386/EISA Bus Error */
+
+/*
+ * Virtual (E)ISA controller address
+ */
+#define JAZZ_EISA_IRQ_ACK       0xE0000238      /* EISA interrupt acknowledge */
+
+/*
+ * Access the R4030 DMA and I/O Controller
+ */
+#ifndef __ASSEMBLY__
+
+static inline void r4030_delay(void)
+{
+__asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".set\treorder");
+}
+
+static inline unsigned short r4030_read_reg16(unsigned long addr)
+{
+        unsigned short ret = *((volatile unsigned short *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline unsigned int r4030_read_reg32(unsigned long addr)
+{
+        unsigned int ret = *((volatile unsigned int *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline void r4030_write_reg16(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned short *)addr) = val;
+        r4030_delay();
+}
+
+static inline void r4030_write_reg32(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned int *)addr) = val;
+        r4030_delay();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#define JAZZ_FDC_BASE   0xe0003000
+#define JAZZ_RTC_BASE   0xe0004000
+#define JAZZ_PORT_BASE  0xe2000000
+
+#define JAZZ_EISA_BASE  0xe3000000
+
+#endif /* __ASM_JAZZ_H */
diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h
new file mode 100644
index 000000000000..0a205b77e505
--- /dev/null
+++ b/include/asm-mips/jazzdma.h
@@ -0,0 +1,96 @@
+/*
+ * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
+ */
+#ifndef _ASM_JAZZDMA_H
+#define _ASM_JAZZDMA_H
+
+/*
+ * Prototypes and macros
+ */
+extern void vdma_init(void);
+extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
+extern int vdma_free(unsigned long laddr);
+extern int vdma_remap(unsigned long laddr, unsigned long paddr,
+                      unsigned long size);
+extern unsigned long vdma_phys2log(unsigned long paddr);
+extern unsigned long vdma_log2phys(unsigned long laddr);
+extern void vdma_stats(void);           /* for debugging only */
+
+extern void vdma_enable(int channel);
+extern void vdma_disable(int channel);
+extern void vdma_set_mode(int channel, int mode);
+extern void vdma_set_addr(int channel, long addr);
+extern void vdma_set_count(int channel, int count);
+extern int vdma_get_residue(int channel);
+extern int vdma_get_enable(int channel);
+
+/*
+ * some definitions used by the driver functions
+ */
+#define VDMA_PAGESIZE           4096
+#define VDMA_PGTBL_ENTRIES      4096
+#define VDMA_PGTBL_SIZE         (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
+#define VDMA_PAGE_EMPTY         0xff000000
+
+/*
+ * Macros to get page no. and offset of a given address
+ * Note that VDMA_PAGE() works for physical addresses only
+ */
+#define VDMA_PAGE(a)            ((unsigned int)(a) >> 12)
+#define VDMA_OFFSET(a)          ((unsigned int)(a) & (VDMA_PAGESIZE-1))
+
+/*
+ * error code returned by vdma_alloc()
+ * (See also arch/mips/kernel/jazzdma.c)
+ */
+#define VDMA_ERROR              0xffffffff
+
+/*
+ * VDMA pagetable entry description
+ */
+typedef volatile struct VDMA_PGTBL_ENTRY {
+        unsigned int frame;             /* physical frame no. */
+        unsigned int owner;             /* owner of this entry (0=free) */
+} VDMA_PGTBL_ENTRY;
+
+
+/*
+ * DMA channel control registers
+ * in the R4030 MCT_ADR chip
+ */
+#define JAZZ_R4030_CHNL_MODE    0xE0000100      /* 8 DMA Channel Mode Registers, */
+                                                /* 0xE0000100,120,140... */
+#define JAZZ_R4030_CHNL_ENABLE  0xE0000108      /* 8 DMA Channel Enable Regs, */
+                                                /* 0xE0000108,128,148... */
+#define JAZZ_R4030_CHNL_COUNT   0xE0000110      /* 8 DMA Channel Byte Cnt Regs, */
+                                                /* 0xE0000110,130,150... */
+#define JAZZ_R4030_CHNL_ADDR    0xE0000118      /* 8 DMA Channel Address Regs, */
+                                                /* 0xE0000118,138,158... */
+
+/* channel enable register bits */
+
+#define R4030_CHNL_ENABLE        (1<<0)
+#define R4030_CHNL_WRITE         (1<<1)
+#define R4030_TC_INTR            (1<<8)
+#define R4030_MEM_INTR           (1<<9)
+#define R4030_ADDR_INTR          (1<<10)
+
+/*
+ * Channel mode register bits
+ */
+#define R4030_MODE_ATIME_40      (0) /* device access time on remote bus */
+#define R4030_MODE_ATIME_80      (1)
+#define R4030_MODE_ATIME_120     (2)
+#define R4030_MODE_ATIME_160     (3)
+#define R4030_MODE_ATIME_200     (4)
+#define R4030_MODE_ATIME_240     (5)
+#define R4030_MODE_ATIME_280     (6)
+#define R4030_MODE_ATIME_320     (7)
+#define R4030_MODE_WIDTH_8       (1<<3) /* device data bus width */
+#define R4030_MODE_WIDTH_16      (2<<3)
+#define R4030_MODE_WIDTH_32      (3<<3)
+#define R4030_MODE_INTR_EN       (1<<5)
+#define R4030_MODE_BURST         (1<<6) /* Rev. 2 only */
+#define R4030_MODE_FAST_ACK      (1<<7) /* Rev. 2 only */
+
+#endif /* _ASM_JAZZDMA_H */
diff --git a/include/asm-mips/jmr3927/irq.h b/include/asm-mips/jmr3927/irq.h
new file mode 100644
index 000000000000..b0c325a22343
--- /dev/null
+++ b/include/asm-mips/jmr3927/irq.h
@@ -0,0 +1,62 @@
+/*
+ *  linux/include/asm-mips/tx3927/irq.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Toshiba Corporation
+ */
+#ifndef __ASM_TX3927_IRQ_H
+#define __ASM_TX3927_IRQ_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+#include <asm/irq.h>
+
+struct tb_irq_space {
+        struct tb_irq_space* next;
+        int start_irqno;
+        int nr_irqs;
+        void (*mask_func)(int irq_nr, int space_id);
+        void (*unmask_func)(int irq_no, int space_id);
+        const char *name;
+        int space_id;
+        int can_share;
+};
+extern struct tb_irq_space* tb_irq_spaces;
+
+static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
+{
+        sp->next = tb_irq_spaces;
+        tb_irq_spaces = sp;
+}
+
+
+struct pt_regs;
+extern void
+toshibaboards_spurious(struct pt_regs *regs, int irq);
+extern void
+toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
+
+extern struct irqaction *
+toshibaboards_get_irq_action(int irq);
+extern int
+toshibaboards_setup_irq(int irq, struct irqaction * new);
+
+
+#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
+extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
+#endif
+
+extern int (*toshibaboards_gen_iack)(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#define NR_ISA_IRQS 16
+#define TB_IRQ_IS_ISA(irq)      \
+        (0 <= (irq) && (irq) < NR_ISA_IRQS)
+#define TB_IRQ_TO_ISA_IRQ(irq)  (irq)
+
+#endif /* __ASM_TX3927_IRQ_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
new file mode 100644
index 000000000000..86df317b4078
--- /dev/null
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -0,0 +1,325 @@
+/*
+ * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ */
+#ifndef __ASM_TX3927_JMR3927_H
+#define __ASM_TX3927_JMR3927_H
+
+#include <asm/jmr3927/tx3927.h>
+#include <asm/addrspace.h>
+#include <asm/jmr3927/irq.h>
+#ifndef __ASSEMBLY__
+#include <asm/system.h>
+#endif
+
+/* CS */
+#define JMR3927_ROMCE0  0x1fc00000      /* 4M */
+#define JMR3927_ROMCE1  0x1e000000      /* 4M */
+#define JMR3927_ROMCE2  0x14000000      /* 16M */
+#define JMR3927_ROMCE3  0x10000000      /* 64M */
+#define JMR3927_ROMCE5  0x1d000000      /* 4M */
+#define JMR3927_SDCS0   0x00000000      /* 32M */
+#define JMR3927_SDCS1   0x02000000      /* 32M */
+/* PCI Direct Mappings */
+
+#define JMR3927_PCIMEM  0x08000000
+#define JMR3927_PCIMEM_SIZE     0x08000000      /* 128M */
+#define JMR3927_PCIIO   0x15000000
+#define JMR3927_PCIIO_SIZE      0x01000000      /* 16M */
+
+#define JMR3927_SDRAM_SIZE      0x02000000      /* 32M */
+#define JMR3927_PORT_BASE       KSEG1
+
+/* select indirect initiator access per errata */
+#define JMR3927_INIT_INDIRECT_PCI
+#define PCI_ISTAT_IDICC           0x1000
+#define PCI_IPCIBE_IBE_LONG       0
+#define PCI_IPCIBE_ICMD_IOREAD    2
+#define PCI_IPCIBE_ICMD_IOWRITE   3
+#define PCI_IPCIBE_ICMD_MEMREAD   6
+#define PCI_IPCIBE_ICMD_MEMWRITE  7
+#define PCI_IPCIBE_ICMD_SHIFT     4
+
+/* Address map (virtual address) */
+#define JMR3927_ROM0_BASE       (KSEG1 + JMR3927_ROMCE0)
+#define JMR3927_ROM1_BASE       (KSEG1 + JMR3927_ROMCE1)
+#define JMR3927_IOC_BASE        (KSEG1 + JMR3927_ROMCE2)
+#define JMR3927_IOB_BASE        (KSEG1 + JMR3927_ROMCE3)
+#define JMR3927_ISAMEM_BASE     (JMR3927_IOB_BASE)
+#define JMR3927_ISAIO_BASE      (JMR3927_IOB_BASE + 0x01000000)
+#define JMR3927_ISAC_BASE       (JMR3927_IOB_BASE + 0x02000000)
+#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
+#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
+#define JMR3927_JMY1394_BASE    (KSEG1 + JMR3927_ROMCE5)
+#define JMR3927_PREMIER3_BASE   (JMR3927_JMY1394_BASE + 0x00100000)
+#define JMR3927_PCIMEM_BASE     (KSEG1 + JMR3927_PCIMEM)
+#define JMR3927_PCIIO_BASE      (KSEG1 + JMR3927_PCIIO)
+
+#define JMR3927_IOC_REV_ADDR    (JMR3927_IOC_BASE + 0x00000000)
+#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
+#define JMR3927_IOC_LED_ADDR    (JMR3927_IOC_BASE + 0x00020000)
+#define JMR3927_IOC_DIPSW_ADDR  (JMR3927_IOC_BASE + 0x00030000)
+#define JMR3927_IOC_BREV_ADDR   (JMR3927_IOC_BASE + 0x00040000)
+#define JMR3927_IOC_DTR_ADDR    (JMR3927_IOC_BASE + 0x00050000)
+#define JMR3927_IOC_INTS1_ADDR  (JMR3927_IOC_BASE + 0x00080000)
+#define JMR3927_IOC_INTS2_ADDR  (JMR3927_IOC_BASE + 0x00090000)
+#define JMR3927_IOC_INTM_ADDR   (JMR3927_IOC_BASE + 0x000a0000)
+#define JMR3927_IOC_INTP_ADDR   (JMR3927_IOC_BASE + 0x000b0000)
+#define JMR3927_IOC_RESET_ADDR  (JMR3927_IOC_BASE + 0x000f0000)
+
+#define JMR3927_ISAC_REV_ADDR   (JMR3927_ISAC_BASE + 0x00000000)
+#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
+#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
+#define JMR3927_ISAC_NMI_ADDR   (JMR3927_ISAC_BASE + 0x00400000)
+#define JMR3927_ISAC_LED_ADDR   (JMR3927_ISAC_BASE + 0x00500000)
+#define JMR3927_ISAC_INTP_ADDR  (JMR3927_ISAC_BASE + 0x00800000)
+#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
+#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
+#define JMR3927_ISAC_INTM_ADDR  (JMR3927_ISAC_BASE + 0x00b00000)
+
+/* Flash ROM */
+#define JMR3927_FLASH_BASE      (JMR3927_ROM0_BASE)
+#define JMR3927_FLASH_SIZE      0x00400000
+
+/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
+#define JMR3927_IDT_MASK        0xfc
+#define JMR3927_REV_MASK        0x03
+#define JMR3927_IOC_IDT         0xe0
+#define JMR3927_ISAC_IDT        0x20
+
+/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
+#define JMR3927_IOC_INTB_PCIA   0
+#define JMR3927_IOC_INTB_PCIB   1
+#define JMR3927_IOC_INTB_PCIC   2
+#define JMR3927_IOC_INTB_PCID   3
+#define JMR3927_IOC_INTB_MODEM  4
+#define JMR3927_IOC_INTB_INT6   5
+#define JMR3927_IOC_INTB_INT7   6
+#define JMR3927_IOC_INTB_SOFT   7
+#define JMR3927_IOC_INTF_PCIA   (1 << JMR3927_IOC_INTF_PCIA)
+#define JMR3927_IOC_INTF_PCIB   (1 << JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IOC_INTF_PCIC   (1 << JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IOC_INTF_PCID   (1 << JMR3927_IOC_INTB_PCID)
+#define JMR3927_IOC_INTF_MODEM  (1 << JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IOC_INTF_INT6   (1 << JMR3927_IOC_INTB_INT6)
+#define JMR3927_IOC_INTF_INT7   (1 << JMR3927_IOC_INTB_INT7)
+#define JMR3927_IOC_INTF_SOFT   (1 << JMR3927_IOC_INTB_SOFT)
+
+/* bits for IOC_RESET (high byte) */
+#define JMR3927_IOC_RESET_CPU   1
+#define JMR3927_IOC_RESET_PCI   2
+
+/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
+#define JMR3927_ISAC_EINTB_IOCHK        2
+#define JMR3927_ISAC_EINTB_BWTH 4
+#define JMR3927_ISAC_EINTF_IOCHK        (1 << JMR3927_ISAC_EINTB_IOCHK)
+#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
+
+/* bits for ISAC_LED (high byte) */
+#define JMR3927_ISAC_LED_ISALED 0x01
+#define JMR3927_ISAC_LED_USRLED 0x02
+
+/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
+#define JMR3927_ISAC_INTB_IRQ5  0
+#define JMR3927_ISAC_INTB_IRQKB 1
+#define JMR3927_ISAC_INTB_IRQMOUSE      2
+#define JMR3927_ISAC_INTB_IRQ4  3
+#define JMR3927_ISAC_INTB_IRQ12 4
+#define JMR3927_ISAC_INTB_IRQ3  5
+#define JMR3927_ISAC_INTB_IRQ10 6
+#define JMR3927_ISAC_INTB_ISAER 7
+#define JMR3927_ISAC_INTF_IRQ5  (1 << JMR3927_ISAC_INTB_IRQ5)
+#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
+#define JMR3927_ISAC_INTF_IRQMOUSE      (1 << JMR3927_ISAC_INTB_IRQMOUSE)
+#define JMR3927_ISAC_INTF_IRQ4  (1 << JMR3927_ISAC_INTB_IRQ4)
+#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
+#define JMR3927_ISAC_INTF_IRQ3  (1 << JMR3927_ISAC_INTB_IRQ3)
+#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
+#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
+
+#ifndef __ASSEMBLY__
+
+#if 0
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned short *)(a)) = (d) << 8)
+#define jmr3927_ioc_reg_in(a)           (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
+#else
+#if defined(__BIG_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)(a)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)(a))
+#elif defined(__LITTLE_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)((a)^1)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)((a)^1))
+#else
+#error "No Endian"
+#endif
+#endif
+#define jmr3927_isac_reg_out(d, a)      ((*(volatile unsigned char *)(a)) = (d))
+#define jmr3927_isac_reg_in(a)          (*(volatile unsigned char *)(a))
+
+static inline int jmr3927_have_isac(void)
+{
+        unsigned char idt;
+        unsigned long flags;
+        unsigned long romcr3;
+
+        local_irq_save(flags);
+        romcr3 = tx3927_romcptr->cr[3];
+        tx3927_romcptr->cr[3] &= 0xffffefff;    /* do not wait infinitely */
+        idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
+        tx3927_romcptr->cr[3] = romcr3;
+        local_irq_restore(flags);
+
+        return idt == JMR3927_ISAC_IDT;
+}
+#define jmr3927_have_nvram() \
+        ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
+
+/* NVRAM macro */
+#define jmr3927_nvram_in(ofs) \
+        jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
+#define jmr3927_nvram_out(d, ofs) \
+        jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
+
+/* LED macro */
+#define jmr3927_led_set(n/*0-16*/)      jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
+#define jmr3927_io_led_set(n/*0-3*/)    jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
+
+#define jmr3927_led_and_set(n/*0-16*/)  jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
+
+/* DIPSW4 macro */
+#define jmr3927_dipsw1()        ((tx3927_pioptr->din & (1 << 11)) == 0)
+#define jmr3927_dipsw2()        ((tx3927_pioptr->din & (1 << 10)) == 0)
+#define jmr3927_dipsw3()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
+#define jmr3927_dipsw4()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
+#define jmr3927_io_dipsw()      (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
+
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * UART defines for serial.h
+ */
+
+/* use Pre-scaler T0 (1/2) */
+#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
+
+#define UART0_ADDR   0xfffef300
+#define UART1_ADDR   0xfffef400
+#define UART0_INT    JMR3927_IRQ_IRC_SIO0
+#define UART1_INT    JMR3927_IRQ_IRC_SIO1
+#define UART0_FLAGS  ASYNC_BOOT_AUTOCONF
+#define UART1_FLAGS  0
+
+/*
+ * IRQ mappings
+ */
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an JMR machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
+#define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
+#define JMR3927_NR_IRQ_ISAC     8       /* ISA */
+
+
+#define JMR3927_IRQ_IRC NR_ISA_IRQS
+#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
+#define JMR3927_IRQ_ISAC        (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
+#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
+#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
+#define JMR3927_IRQ_IS_IOC(irq)         (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
+#define JMR3927_IRQ_IS_ISAC(irq)        (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
+
+#define JMR3927_IRQ_IRC_INT0    (JMR3927_IRQ_IRC + TX3927_IR_INT0)
+#define JMR3927_IRQ_IRC_INT1    (JMR3927_IRQ_IRC + TX3927_IR_INT1)
+#define JMR3927_IRQ_IRC_INT2    (JMR3927_IRQ_IRC + TX3927_IR_INT2)
+#define JMR3927_IRQ_IRC_INT3    (JMR3927_IRQ_IRC + TX3927_IR_INT3)
+#define JMR3927_IRQ_IRC_INT4    (JMR3927_IRQ_IRC + TX3927_IR_INT4)
+#define JMR3927_IRQ_IRC_INT5    (JMR3927_IRQ_IRC + TX3927_IR_INT5)
+#define JMR3927_IRQ_IRC_SIO0    (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
+#define JMR3927_IRQ_IRC_SIO1    (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
+#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
+#define JMR3927_IRQ_IRC_DMA     (JMR3927_IRQ_IRC + TX3927_IR_DMA)
+#define JMR3927_IRQ_IRC_PIO     (JMR3927_IRQ_IRC + TX3927_IR_PIO)
+#define JMR3927_IRQ_IRC_PCI     (JMR3927_IRQ_IRC + TX3927_IR_PCI)
+#define JMR3927_IRQ_IRC_TMR0    (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
+#define JMR3927_IRQ_IRC_TMR1    (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
+#define JMR3927_IRQ_IRC_TMR2    (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
+#define JMR3927_IRQ_IOC_PCIA    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
+#define JMR3927_IRQ_IOC_PCIB    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IRQ_IOC_PCIC    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IRQ_IOC_PCID    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
+#define JMR3927_IRQ_IOC_MODEM   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IRQ_IOC_INT6    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
+#define JMR3927_IRQ_IOC_INT7    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
+#define JMR3927_IRQ_IOC_SOFT    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
+#define JMR3927_IRQ_ISAC_IRQ5   (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
+#define JMR3927_IRQ_ISAC_IRQKB  (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
+#define JMR3927_IRQ_ISAC_IRQMOUSE       (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
+#define JMR3927_IRQ_ISAC_IRQ4   (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
+#define JMR3927_IRQ_ISAC_IRQ12  (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
+#define JMR3927_IRQ_ISAC_IRQ3   (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
+#define JMR3927_IRQ_ISAC_IRQ10  (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
+#define JMR3927_IRQ_ISAC_ISAER  (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
+
+#if 0   /* auto detect */
+/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
+#define JMR3927_IRQ_ETHER1      JMR3927_IRQ_IRC_INT0
+#endif
+/* IOC (PCI, MODEM) */
+#define JMR3927_IRQ_IOCINT      JMR3927_IRQ_IRC_INT1
+/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
+#define JMR3927_IRQ_ISACINT     JMR3927_IRQ_IRC_INT2
+/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
+#define JMR3927_IRQ_ETHER0      JMR3927_IRQ_IRC_INT3
+/* Clock Tick (10ms) */
+#define JMR3927_IRQ_TICK        JMR3927_IRQ_IRC_TMR0
+#define JMR3927_IRQ_IDE         JMR3927_IRQ_ISAC_IRQ12
+
+/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
+#define JMR3927_IRQ_PREMIER3    JMR3927_IRQ_IRC_INT0
+
+/* I/O Ports */
+/* RTL8019AS 10M Ether */
+#define JMR3927_ETHER1_PORT     (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
+#define JMR3927_KBD_PORT        (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
+#define JMR3927_IDE_PORT        (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
+
+/* Clocks */
+#define JMR3927_CORECLK 132710400       /* 132.7MHz */
+#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2)   /* 66.35MHz */
+#define JMR3927_IMCLK   (JMR3927_CORECLK / 4)   /* 33.17MHz */
+
+#define jmr3927_tmrptr          tx3927_tmrptr(0)        /* TMR0 */
+
+
+/*
+ * TX3927 Pin Configuration:
+ *
+ *      PCFG bits               Avail                   Dead
+ *      SELSIO[1:0]:11          RXD[1:0], TXD[1:0]      PIO[6:3]
+ *      SELSIOC[0]:1            CTS[0], RTS[0]          INT[5:4]
+ *      SELSIOC[1]:0,SELDSF:0,  GSDAO[0],GPCST[3]       CTS[1], RTS[1],DSF,
+ *        GDBGE*                                          PIO[2:1]
+ *      SELDMA[2]:1             DMAREQ[2],DMAACK[2]     PIO[13:12]
+ *      SELTMR[2:0]:000                                 TIMER[1:0]
+ *      SELCS:0,SELDMA[1]:0     PIO[11;10]              SDCS_CE[7:6],
+ *                                                        DMAREQ[1],DMAACK[1]
+ *      SELDMA[0]:1             DMAREQ[0],DMAACK[0]     PIO[9:8]
+ *      SELDMA[3]:1             DMAREQ[3],DMAACK[3]     PIO[15:14]
+ *      SELDONE:1               DMADONE                 PIO[7]
+ *
+ * Usable pins are:
+ *      RXD[1;0],TXD[1:0],CTS[0],RTS[0],
+ *      DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
+ *      INT[3:0]
+ */
+
+#endif /* __ASM_TX3927_JMR3927_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
new file mode 100644
index 000000000000..b3d67c75d9ac
--- /dev/null
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -0,0 +1,365 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Toshiba Corporation
+ */
+#ifndef __ASM_TX3927_H
+#define __ASM_TX3927_H
+
+#include <asm/jmr3927/txx927.h>
+
+#define TX3927_SDRAMC_REG       0xfffe8000
+#define TX3927_ROMC_REG         0xfffe9000
+#define TX3927_DMA_REG          0xfffeb000
+#define TX3927_IRC_REG          0xfffec000
+#define TX3927_PCIC_REG         0xfffed000
+#define TX3927_CCFG_REG         0xfffee000
+#define TX3927_NR_TMR   3
+#define TX3927_TMR_REG(ch)      (0xfffef000 + (ch) * 0x100)
+#define TX3927_NR_SIO   2
+#define TX3927_SIO_REG(ch)      (0xfffef300 + (ch) * 0x100)
+#define TX3927_PIO_REG          0xfffef500
+
+#ifndef __ASSEMBLY__
+
+struct tx3927_sdramc_reg {
+        volatile unsigned long cr[8];
+        volatile unsigned long tr[3];
+        volatile unsigned long cmd;
+        volatile unsigned long smrs[2];
+};
+
+struct tx3927_romc_reg {
+        volatile unsigned long cr[8];
+};
+
+struct tx3927_dma_reg {
+        struct tx3927_dma_ch_reg {
+                volatile unsigned long cha;
+                volatile unsigned long sar;
+                volatile unsigned long dar;
+                volatile unsigned long cntr;
+                volatile unsigned long sair;
+                volatile unsigned long dair;
+                volatile unsigned long ccr;
+                volatile unsigned long csr;
+        } ch[4];
+        volatile unsigned long dbr[8];
+        volatile unsigned long tdhr;
+        volatile unsigned long mcr;
+        volatile unsigned long unused0;
+};
+
+struct tx3927_irc_reg {
+        volatile unsigned long cer;
+        volatile unsigned long cr[2];
+        volatile unsigned long unused0;
+        volatile unsigned long ilr[8];
+        volatile unsigned long unused1[4];
+        volatile unsigned long imr;
+        volatile unsigned long unused2[7];
+        volatile unsigned long scr;
+        volatile unsigned long unused3[7];
+        volatile unsigned long ssr;
+        volatile unsigned long unused4[7];
+        volatile unsigned long csr;
+};
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e1,e2
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned short e1;volatile unsigned char e2,e3
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned char e1,e2;volatile unsigned short e3
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e1,e2,e3,e4
+#else
+#define endian_def_s2(e1,e2)    \
+        volatile unsigned short e2,e1
+#define endian_def_sb2(e1,e2,e3)        \
+        volatile unsigned char e3,e2;volatile unsigned short e1
+#define endian_def_b2s(e1,e2,e3)        \
+        volatile unsigned short e3;volatile unsigned char e2,e1
+#define endian_def_b4(e1,e2,e3,e4)      \
+        volatile unsigned char e4,e3,e2,e1
+#endif
+
+struct tx3927_pcic_reg {
+        endian_def_s2(did, vid);
+        endian_def_s2(pcistat, pcicmd);
+        endian_def_b4(cc, scc, rpli, rid);
+        endian_def_b4(unused0, ht, mlt, cls);
+        volatile unsigned long ioba;            /* +10 */
+        volatile unsigned long mba;
+        volatile unsigned long unused1[5];
+        endian_def_s2(svid, ssvid);
+        volatile unsigned long unused2;         /* +30 */
+        endian_def_sb2(unused3, unused4, capptr);
+        volatile unsigned long unused5;
+        endian_def_b4(ml, mg, ip, il);
+        volatile unsigned long unused6;         /* +40 */
+        volatile unsigned long istat;
+        volatile unsigned long iim;
+        volatile unsigned long rrt;
+        volatile unsigned long unused7[3];              /* +50 */
+        volatile unsigned long ipbmma;
+        volatile unsigned long ipbioma;         /* +60 */
+        volatile unsigned long ilbmma;
+        volatile unsigned long ilbioma;
+        volatile unsigned long unused8[9];
+        volatile unsigned long tc;              /* +90 */
+        volatile unsigned long tstat;
+        volatile unsigned long tim;
+        volatile unsigned long tccmd;
+        volatile unsigned long pcirrt;          /* +a0 */
+        volatile unsigned long pcirrt_cmd;
+        volatile unsigned long pcirrdt;
+        volatile unsigned long unused9[3];
+        volatile unsigned long tlboap;
+        volatile unsigned long tlbiap;
+        volatile unsigned long tlbmma;          /* +c0 */
+        volatile unsigned long tlbioma;
+        volatile unsigned long sc_msg;
+        volatile unsigned long sc_be;
+        volatile unsigned long tbl;             /* +d0 */
+        volatile unsigned long unused10[3];
+        volatile unsigned long pwmng;           /* +e0 */
+        volatile unsigned long pwmngs;
+        volatile unsigned long unused11[6];
+        volatile unsigned long req_trace;               /* +100 */
+        volatile unsigned long pbapmc;
+        volatile unsigned long pbapms;
+        volatile unsigned long pbapmim;
+        volatile unsigned long bm;              /* +110 */
+        volatile unsigned long cpcibrs;
+        volatile unsigned long cpcibgs;
+        volatile unsigned long pbacs;
+        volatile unsigned long iobas;           /* +120 */
+        volatile unsigned long mbas;
+        volatile unsigned long lbc;
+        volatile unsigned long lbstat;
+        volatile unsigned long lbim;            /* +130 */
+        volatile unsigned long pcistatim;
+        volatile unsigned long ica;
+        volatile unsigned long icd;
+        volatile unsigned long iiadp;           /* +140 */
+        volatile unsigned long iscdp;
+        volatile unsigned long mmas;
+        volatile unsigned long iomas;
+        volatile unsigned long ipciaddr;                /* +150 */
+        volatile unsigned long ipcidata;
+        volatile unsigned long ipcibe;
+};
+
+struct tx3927_ccfg_reg {
+        volatile unsigned long ccfg;
+        volatile unsigned long crir;
+        volatile unsigned long pcfg;
+        volatile unsigned long tear;
+        volatile unsigned long pdcr;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * SDRAMC
+ */
+
+/*
+ * ROMC
+ */
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX3927_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX3927_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX3927_DMA_MCR_RSFIF    0x00000080
+#define TX3927_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX3927_DMA_MCR_LE       0x00000004
+#define TX3927_DMA_MCR_RPRT     0x00000002
+#define TX3927_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX3927_DMA_CCR_DBINH    0x04000000
+#define TX3927_DMA_CCR_SBINH    0x02000000
+#define TX3927_DMA_CCR_CHRST    0x01000000
+#define TX3927_DMA_CCR_RVBYTE   0x00800000
+#define TX3927_DMA_CCR_ACKPOL   0x00400000
+#define TX3927_DMA_CCR_REQPL    0x00200000
+#define TX3927_DMA_CCR_EGREQ    0x00100000
+#define TX3927_DMA_CCR_CHDN     0x00080000
+#define TX3927_DMA_CCR_DNCTL    0x00060000
+#define TX3927_DMA_CCR_EXTRQ    0x00010000
+#define TX3927_DMA_CCR_INTRQD   0x0000e000
+#define TX3927_DMA_CCR_INTENE   0x00001000
+#define TX3927_DMA_CCR_INTENC   0x00000800
+#define TX3927_DMA_CCR_INTENT   0x00000400
+#define TX3927_DMA_CCR_CHNEN    0x00000200
+#define TX3927_DMA_CCR_XFACT    0x00000100
+#define TX3927_DMA_CCR_SNOP     0x00000080
+#define TX3927_DMA_CCR_DSTINC   0x00000040
+#define TX3927_DMA_CCR_SRCINC   0x00000020
+#define TX3927_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX3927_DMA_CCR_XFSZ_1W  TX3927_DMA_CCR_XFSZ(2)
+#define TX3927_DMA_CCR_XFSZ_4W  TX3927_DMA_CCR_XFSZ(4)
+#define TX3927_DMA_CCR_XFSZ_8W  TX3927_DMA_CCR_XFSZ(5)
+#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
+#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
+#define TX3927_DMA_CCR_MEMIO    0x00000002
+#define TX3927_DMA_CCR_ONEAD    0x00000001
+
+/* bits for CSRn */
+#define TX3927_DMA_CSR_CHNACT   0x00000100
+#define TX3927_DMA_CSR_ABCHC    0x00000080
+#define TX3927_DMA_CSR_NCHNC    0x00000040
+#define TX3927_DMA_CSR_NTRNFC   0x00000020
+#define TX3927_DMA_CSR_EXTDN    0x00000010
+#define TX3927_DMA_CSR_CFERR    0x00000008
+#define TX3927_DMA_CSR_CHERR    0x00000004
+#define TX3927_DMA_CSR_DESERR   0x00000002
+#define TX3927_DMA_CSR_SORERR   0x00000001
+
+/*
+ * IRC
+ */
+#define TX3927_IR_MAX_LEVEL     7
+
+/* IRCER : Int. Control Enable */
+#define TX3927_IRCER_ICE        0x00000001
+
+/* IRCR : Int. Control */
+#define TX3927_IRCR_LOW 0x00000000
+#define TX3927_IRCR_HIGH        0x00000001
+#define TX3927_IRCR_DOWN        0x00000002
+#define TX3927_IRCR_UP  0x00000003
+
+/* IRSCR : Int. Status Control */
+#define TX3927_IRSCR_EIClrE     0x00000100
+#define TX3927_IRSCR_EIClr_MASK 0x0000000f
+
+/* IRCSR : Int. Current Status */
+#define TX3927_IRCSR_IF 0x00010000
+#define TX3927_IRCSR_ILV_MASK   0x00000700
+#define TX3927_IRCSR_IVL_MASK   0x0000001f
+
+#define TX3927_IR_INT0  0
+#define TX3927_IR_INT1  1
+#define TX3927_IR_INT2  2
+#define TX3927_IR_INT3  3
+#define TX3927_IR_INT4  4
+#define TX3927_IR_INT5  5
+#define TX3927_IR_SIO0  6
+#define TX3927_IR_SIO1  7
+#define TX3927_IR_SIO(ch)       (6 + (ch))
+#define TX3927_IR_DMA   8
+#define TX3927_IR_PIO   9
+#define TX3927_IR_PCI   10
+#define TX3927_IR_TMR0  13
+#define TX3927_IR_TMR1  14
+#define TX3927_IR_TMR2  15
+#define TX3927_NUM_IR   16
+
+/*
+ * PCIC
+ */
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci.h */
+#define PCI_STATUS_NEW_CAP      0x0010
+
+/* bits for TC */
+#define TX3927_PCIC_TC_OF16E    0x00000020
+#define TX3927_PCIC_TC_IF8E     0x00000010
+#define TX3927_PCIC_TC_OF8E     0x00000008
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
+
+/* bits for PBAPMC */
+#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
+#define TX3927_PCIC_PBAPMC_PBAEN        0x00000002
+#define TX3927_PCIC_PBAPMC_BMCEN        0x00000001
+
+/* bits for LBSTAT/LBIM */
+#define TX3927_PCIC_LBIM_ALL    0x0000003e
+
+/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX3927_PCIC_PCISTATIM_ALL       0x0000f900
+
+/* bits for LBC */
+#define TX3927_PCIC_LBC_IBSE    0x00004000
+#define TX3927_PCIC_LBC_TIBSE   0x00002000
+#define TX3927_PCIC_LBC_TMFBSE  0x00001000
+#define TX3927_PCIC_LBC_HRST    0x00000800
+#define TX3927_PCIC_LBC_SRST    0x00000400
+#define TX3927_PCIC_LBC_EPCAD   0x00000200
+#define TX3927_PCIC_LBC_MSDSE   0x00000100
+#define TX3927_PCIC_LBC_CRR     0x00000080
+#define TX3927_PCIC_LBC_ILMDE   0x00000040
+#define TX3927_PCIC_LBC_ILIDE   0x00000020
+
+#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX3927_PCIC_MAX_DEVNU   TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX3927_CCFG_TLBOFF      0x00020000
+#define TX3927_CCFG_BEOW        0x00010000
+#define TX3927_CCFG_WR  0x00008000
+#define TX3927_CCFG_TOE 0x00004000
+#define TX3927_CCFG_PCIXARB     0x00002000
+#define TX3927_CCFG_PCI3        0x00001000
+#define TX3927_CCFG_PSNP        0x00000800
+#define TX3927_CCFG_PPRI        0x00000400
+#define TX3927_CCFG_PLLM        0x00000030
+#define TX3927_CCFG_ENDIAN      0x00000004
+#define TX3927_CCFG_HALT        0x00000002
+#define TX3927_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX3927_PCFG_SYSCLKEN    0x08000000
+#define TX3927_PCFG_SDRCLKEN_ALL        0x07c00000
+#define TX3927_PCFG_SDRCLKEN(ch)        (0x00400000<<(ch))
+#define TX3927_PCFG_PCICLKEN_ALL        0x003c0000
+#define TX3927_PCFG_PCICLKEN(ch)        (0x00040000<<(ch))
+#define TX3927_PCFG_SELALL      0x0003ffff
+#define TX3927_PCFG_SELCS       0x00020000
+#define TX3927_PCFG_SELDSF      0x00010000
+#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
+#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
+#define TX3927_PCFG_SELSIO_ALL  0x00003000
+#define TX3927_PCFG_SELSIO(ch)  (0x00001000<<(ch))
+#define TX3927_PCFG_SELTMR_ALL  0x00000e00
+#define TX3927_PCFG_SELTMR(ch)  (0x00000200<<(ch))
+#define TX3927_PCFG_SELDONE     0x00000100
+#define TX3927_PCFG_INTDMA_ALL  0x000000f0
+#define TX3927_PCFG_INTDMA(ch)  (0x00000010<<(ch))
+#define TX3927_PCFG_SELDMA_ALL  0x0000000f
+#define TX3927_PCFG_SELDMA(ch)  (0x00000001<<(ch))
+
+#ifndef __ASSEMBLY__
+
+#define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
+#define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
+#define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
+#define tx3927_ircptr           ((struct tx3927_irc_reg *)TX3927_IRC_REG)
+#define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
+#define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
+#define tx3927_tmrptr(ch)       ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
+#define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
+#define tx3927_pioptr           ((struct txx927_pio_reg *)TX3927_PIO_REG)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
new file mode 100644
index 000000000000..9d5792eab452
--- /dev/null
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -0,0 +1,175 @@
+/*
+ * Common definitions for TX3927/TX4927
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Toshiba Corporation
+ */
+#ifndef __ASM_TXX927_H
+#define __ASM_TXX927_H
+
+#ifndef __ASSEMBLY__
+
+struct txx927_tmr_reg {
+        volatile unsigned long tcr;
+        volatile unsigned long tisr;
+        volatile unsigned long cpra;
+        volatile unsigned long cprb;
+        volatile unsigned long itmr;
+        volatile unsigned long unused0[3];
+        volatile unsigned long ccdr;
+        volatile unsigned long unused1[3];
+        volatile unsigned long pgmr;
+        volatile unsigned long unused2[3];
+        volatile unsigned long wtmr;
+        volatile unsigned long unused3[43];
+        volatile unsigned long trr;
+};
+
+struct txx927_sio_reg {
+        volatile unsigned long lcr;
+        volatile unsigned long dicr;
+        volatile unsigned long disr;
+        volatile unsigned long cisr;
+        volatile unsigned long fcr;
+        volatile unsigned long flcr;
+        volatile unsigned long bgr;
+        volatile unsigned long tfifo;
+        volatile unsigned long rfifo;
+};
+
+struct txx927_pio_reg {
+        volatile unsigned long dout;
+        volatile unsigned long din;
+        volatile unsigned long dir;
+        volatile unsigned long od;
+        volatile unsigned long flag[2];
+        volatile unsigned long pol;
+        volatile unsigned long intc;
+        volatile unsigned long maskcpu;
+        volatile unsigned long maskext;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+
+/*
+ * TMR
+ */
+/* TMTCR : Timer Control */
+#define TXx927_TMTCR_TCE        0x00000080
+#define TXx927_TMTCR_CCDE       0x00000040
+#define TXx927_TMTCR_CRE        0x00000020
+#define TXx927_TMTCR_ECES       0x00000008
+#define TXx927_TMTCR_CCS        0x00000004
+#define TXx927_TMTCR_TMODE_MASK 0x00000003
+#define TXx927_TMTCR_TMODE_ITVL 0x00000000
+
+/* TMTISR : Timer Int. Status */
+#define TXx927_TMTISR_TPIBS     0x00000004
+#define TXx927_TMTISR_TPIAS     0x00000002
+#define TXx927_TMTISR_TIIS      0x00000001
+
+/* TMTITMR : Interval Timer Mode */
+#define TXx927_TMTITMR_TIIE     0x00008000
+#define TXx927_TMTITMR_TZCE     0x00000001
+
+/*
+ * SIO
+ */
+/* SILCR : Line Control */
+#define TXx927_SILCR_SCS_MASK   0x00000060
+#define TXx927_SILCR_SCS_IMCLK  0x00000000
+#define TXx927_SILCR_SCS_IMCLK_BG       0x00000020
+#define TXx927_SILCR_SCS_SCLK   0x00000040
+#define TXx927_SILCR_SCS_SCLK_BG        0x00000060
+#define TXx927_SILCR_UEPS       0x00000010
+#define TXx927_SILCR_UPEN       0x00000008
+#define TXx927_SILCR_USBL_MASK  0x00000004
+#define TXx927_SILCR_USBL_1BIT  0x00000004
+#define TXx927_SILCR_USBL_2BIT  0x00000000
+#define TXx927_SILCR_UMODE_MASK 0x00000003
+#define TXx927_SILCR_UMODE_8BIT 0x00000000
+#define TXx927_SILCR_UMODE_7BIT 0x00000001
+
+/* SIDICR : DMA/Int. Control */
+#define TXx927_SIDICR_TDE       0x00008000
+#define TXx927_SIDICR_RDE       0x00004000
+#define TXx927_SIDICR_TIE       0x00002000
+#define TXx927_SIDICR_RIE       0x00001000
+#define TXx927_SIDICR_SPIE      0x00000800
+#define TXx927_SIDICR_CTSAC     0x00000600
+#define TXx927_SIDICR_STIE_MASK 0x0000003f
+#define TXx927_SIDICR_STIE_OERS         0x00000020
+#define TXx927_SIDICR_STIE_CTSS         0x00000010
+#define TXx927_SIDICR_STIE_RBRKD        0x00000008
+#define TXx927_SIDICR_STIE_TRDY         0x00000004
+#define TXx927_SIDICR_STIE_TXALS        0x00000002
+#define TXx927_SIDICR_STIE_UBRKD        0x00000001
+
+/* SIDISR : DMA/Int. Status */
+#define TXx927_SIDISR_UBRK      0x00008000
+#define TXx927_SIDISR_UVALID    0x00004000
+#define TXx927_SIDISR_UFER      0x00002000
+#define TXx927_SIDISR_UPER      0x00001000
+#define TXx927_SIDISR_UOER      0x00000800
+#define TXx927_SIDISR_ERI       0x00000400
+#define TXx927_SIDISR_TOUT      0x00000200
+#define TXx927_SIDISR_TDIS      0x00000100
+#define TXx927_SIDISR_RDIS      0x00000080
+#define TXx927_SIDISR_STIS      0x00000040
+#define TXx927_SIDISR_RFDN_MASK 0x0000001f
+
+/* SICISR : Change Int. Status */
+#define TXx927_SICISR_OERS      0x00000020
+#define TXx927_SICISR_CTSS      0x00000010
+#define TXx927_SICISR_RBRKD     0x00000008
+#define TXx927_SICISR_TRDY      0x00000004
+#define TXx927_SICISR_TXALS     0x00000002
+#define TXx927_SICISR_UBRKD     0x00000001
+
+/* SIFCR : FIFO Control */
+#define TXx927_SIFCR_SWRST      0x00008000
+#define TXx927_SIFCR_RDIL_MASK  0x00000180
+#define TXx927_SIFCR_RDIL_1     0x00000000
+#define TXx927_SIFCR_RDIL_4     0x00000080
+#define TXx927_SIFCR_RDIL_8     0x00000100
+#define TXx927_SIFCR_RDIL_12    0x00000180
+#define TXx927_SIFCR_RDIL_MAX   0x00000180
+#define TXx927_SIFCR_TDIL_MASK  0x00000018
+#define TXx927_SIFCR_TDIL_MASK  0x00000018
+#define TXx927_SIFCR_TDIL_1     0x00000000
+#define TXx927_SIFCR_TDIL_4     0x00000001
+#define TXx927_SIFCR_TDIL_8     0x00000010
+#define TXx927_SIFCR_TDIL_MAX   0x00000010
+#define TXx927_SIFCR_TFRST      0x00000004
+#define TXx927_SIFCR_RFRST      0x00000002
+#define TXx927_SIFCR_FRSTE      0x00000001
+#define TXx927_SIO_TX_FIFO      8
+#define TXx927_SIO_RX_FIFO      16
+
+/* SIFLCR : Flow Control */
+#define TXx927_SIFLCR_RCS       0x00001000
+#define TXx927_SIFLCR_TES       0x00000800
+#define TXx927_SIFLCR_RTSSC     0x00000200
+#define TXx927_SIFLCR_RSDE      0x00000100
+#define TXx927_SIFLCR_TSDE      0x00000080
+#define TXx927_SIFLCR_RTSTL_MASK        0x0000001e
+#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
+#define TXx927_SIFLCR_TBRK      0x00000001
+
+/* SIBGR : Baudrate Control */
+#define TXx927_SIBGR_BCLK_MASK  0x00000300
+#define TXx927_SIBGR_BCLK_T0    0x00000000
+#define TXx927_SIBGR_BCLK_T2    0x00000100
+#define TXx927_SIBGR_BCLK_T4    0x00000200
+#define TXx927_SIBGR_BCLK_T6    0x00000300
+#define TXx927_SIBGR_BRD_MASK   0x000000ff
+
+/*
+ * PIO
+ */
+
+#endif /* __ASM_TXX927_H */
diff --git a/include/asm-mips/kmap_types.h b/include/asm-mips/kmap_types.h
new file mode 100644
index 000000000000..6886a0c3fedf
--- /dev/null
+++ b/include/asm-mips/kmap_types.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0)    KM_BOUNCE_READ,
+D(1)    KM_SKB_SUNRPC_DATA,
+D(2)    KM_SKB_DATA_SOFTIRQ,
+D(3)    KM_USER0,
+D(4)    KM_USER1,
+D(5)    KM_BIO_SRC_IRQ,
+D(6)    KM_BIO_DST_IRQ,
+D(7)    KM_PTE0,
+D(8)    KM_PTE1,
+D(9)    KM_IRQ0,
+D(10)   KM_IRQ1,
+D(11)   KM_SOFTIRQ0,
+D(12)   KM_SOFTIRQ1,
+D(13)   KM_TYPE_NR
+};
+
+#undef D
+
+#endif
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
new file mode 100644
index 000000000000..edcd7544b358
--- /dev/null
+++ b/include/asm-mips/lasat/ds1603.h
@@ -0,0 +1,18 @@
+#include <asm/addrspace.h>
+
+/* Lasat 100    */
+#define DS1603_REG_100          (KSEG1ADDR(0x1c810000))
+#define DS1603_RST_100          (1 << 2)
+#define DS1603_CLK_100          (1 << 0)
+#define DS1603_DATA_SHIFT_100   1
+#define DS1603_DATA_100         (1 << DS1603_DATA_SHIFT_100)
+
+/* Lasat 200    */
+#define DS1603_REG_200          (KSEG1ADDR(0x11000000))
+#define DS1603_RST_200          (1 << 3)
+#define DS1603_CLK_200          (1 << 4)
+#define DS1603_DATA_200         (1 << 5)
+
+#define DS1603_DATA_REG_200             (DS1603_REG_200 + 0x10000)
+#define DS1603_DATA_READ_SHIFT_200      9
+#define DS1603_DATA_READ_200    (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
new file mode 100644
index 000000000000..7b53edd5cd5f
--- /dev/null
+++ b/include/asm-mips/lasat/eeprom.h
@@ -0,0 +1,17 @@
+#include <asm/addrspace.h>
+
+/* lasat 100 */
+#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
+#define AT93C_RDATA_REG_100         AT93C_REG_100
+#define AT93C_RDATA_SHIFT_100       4
+#define AT93C_WDATA_SHIFT_100       4
+#define AT93C_CS_M_100              ( 1 << 5 )
+#define AT93C_CLK_M_100             ( 1 << 3 )
+
+/* lasat 200 */
+#define AT93C_REG_200           KSEG1ADDR(0x11000000)
+#define AT93C_RDATA_REG_200     (AT93C_REG_200+0x10000)
+#define AT93C_RDATA_SHIFT_200   8
+#define AT93C_WDATA_SHIFT_200   2
+#define AT93C_CS_M_200          ( 1 << 0 )
+#define AT93C_CLK_M_200         ( 1 << 1 )
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
new file mode 100644
index 000000000000..f5589f31a197
--- /dev/null
+++ b/include/asm-mips/lasat/head.h
@@ -0,0 +1,22 @@
+/*
+ * Image header stuff
+ */
+#ifndef _HEAD_H
+#define _HEAD_H
+
+#define LASAT_K_MAGIC0_VAL      0xfedeabba
+#define LASAT_K_MAGIC1_VAL      0x00bedead
+
+#ifndef _LANGUAGE_ASSEMBLY
+#include <linux/types.h>
+struct bootloader_header {
+        u32 magic[2];
+        u32 version;
+        u32 image_start;
+        u32 image_size;
+        u32 kernel_start;
+        u32 kernel_entry;
+};
+#endif
+
+#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
new file mode 100644
index 000000000000..181afc5c0f1d
--- /dev/null
+++ b/include/asm-mips/lasat/lasat.h
@@ -0,0 +1,255 @@
+/*
+ * lasat.h
+ *
+ * Thomas Horsten <thh@lasat.com>
+ * Copyright (C) 2000 LASAT Networks A/S.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Configuration for LASAT boards, loads the appropriate include files.
+ */
+#ifndef _LASAT_H
+#define _LASAT_H
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+extern struct lasat_misc {
+        volatile u32 *reset_reg;
+        volatile u32 *flash_wp_reg;
+        u32 flash_wp_bit;
+} *lasat_misc;
+
+enum lasat_mtdparts {
+        LASAT_MTD_BOOTLOADER,
+        LASAT_MTD_SERVICE,
+        LASAT_MTD_NORMAL,
+        LASAT_MTD_CONFIG,
+        LASAT_MTD_FS,
+        LASAT_MTD_LAST
+};
+
+/*
+ * The format of the data record in the EEPROM.
+ * See Documentation/LASAT/eeprom.txt for a detailed description
+ * of the fields in this struct, and the LASAT Hardware Configuration
+ * field specification for a detailed description of the config
+ * field.
+ */
+#include <linux/types.h>
+
+#define LASAT_EEPROM_VERSION 7
+struct lasat_eeprom_struct {
+        unsigned int  version;
+        unsigned int  cfg[3];
+        unsigned char hwaddr[6];
+        unsigned char print_partno[12];
+        unsigned char term0;
+        unsigned char print_serial[14];
+        unsigned char term1;
+        unsigned char prod_partno[12];
+        unsigned char term2;
+        unsigned char prod_serial[14];
+        unsigned char term3;
+        unsigned char passwd_hash[16];
+        unsigned char pwdnull;
+        unsigned char vendid;
+        unsigned char ts_ref;
+        unsigned char ts_signoff;
+        unsigned char reserved[11];
+        unsigned char debugaccess;
+        unsigned short prid;
+        unsigned int  serviceflag;
+        unsigned int  ipaddr;
+        unsigned int  netmask;
+        unsigned int  crc32;
+};
+
+struct lasat_eeprom_struct_pre7 {
+        unsigned int  version;
+        unsigned int  flags[3];
+        unsigned char hwaddr0[6];
+        unsigned char hwaddr1[6];
+        unsigned char print_partno[9];
+        unsigned char term0;
+        unsigned char print_serial[14];
+        unsigned char term1;
+        unsigned char prod_partno[9];
+        unsigned char term2;
+        unsigned char prod_serial[14];
+        unsigned char term3;
+        unsigned char passwd_hash[24];
+        unsigned char pwdnull;
+        unsigned char vendor;
+        unsigned char ts_ref;
+        unsigned char ts_signoff;
+        unsigned char reserved[6];
+        unsigned int  writecount;
+        unsigned int  ipaddr;
+        unsigned int  netmask;
+        unsigned int  crc32;
+};
+
+/* Configuration descriptor encoding - see the doc for details */
+
+#define LASAT_W0_DSCTYPE(v)             ( ( (v)         ) & 0xf )
+#define LASAT_W0_BMID(v)                ( ( (v) >> 0x04 ) & 0xf )
+#define LASAT_W0_CPUTYPE(v)             ( ( (v) >> 0x08 ) & 0xf )
+#define LASAT_W0_BUSSPEED(v)            ( ( (v) >> 0x0c ) & 0xf )
+#define LASAT_W0_CPUCLK(v)              ( ( (v) >> 0x10 ) & 0xf )
+#define LASAT_W0_SDRAMBANKSZ(v)         ( ( (v) >> 0x14 ) & 0xf )
+#define LASAT_W0_SDRAMBANKS(v)          ( ( (v) >> 0x18 ) & 0xf )
+#define LASAT_W0_L2CACHE(v)             ( ( (v) >> 0x1c ) & 0xf )
+
+#define LASAT_W1_EDHAC(v)               ( ( (v)         ) & 0xf )
+#define LASAT_W1_HIFN(v)                ( ( (v) >> 0x04 ) & 0x1 )
+#define LASAT_W1_ISDN(v)                ( ( (v) >> 0x05 ) & 0x1 )
+#define LASAT_W1_IDE(v)                 ( ( (v) >> 0x06 ) & 0x1 )
+#define LASAT_W1_HDLC(v)                ( ( (v) >> 0x07 ) & 0x1 )
+#define LASAT_W1_USVERSION(v)           ( ( (v) >> 0x08 ) & 0x1 )
+#define LASAT_W1_4MACS(v)               ( ( (v) >> 0x09 ) & 0x1 )
+#define LASAT_W1_EXTSERIAL(v)           ( ( (v) >> 0x0a ) & 0x1 )
+#define LASAT_W1_FLASHSIZE(v)           ( ( (v) >> 0x0c ) & 0xf )
+#define LASAT_W1_PCISLOTS(v)            ( ( (v) >> 0x10 ) & 0xf )
+#define LASAT_W1_PCI1OPT(v)             ( ( (v) >> 0x14 ) & 0xf )
+#define LASAT_W1_PCI2OPT(v)             ( ( (v) >> 0x18 ) & 0xf )
+#define LASAT_W1_PCI3OPT(v)             ( ( (v) >> 0x1c ) & 0xf )
+
+/* Routines specific to LASAT boards */
+
+#define LASAT_BMID_MASQUERADE2          0
+#define LASAT_BMID_MASQUERADEPRO        1
+#define LASAT_BMID_SAFEPIPE25                   2
+#define LASAT_BMID_SAFEPIPE50                   3
+#define LASAT_BMID_SAFEPIPE100          4
+#define LASAT_BMID_SAFEPIPE5000         5
+#define LASAT_BMID_SAFEPIPE7000         6
+#define LASAT_BMID_SAFEPIPE1000         7
+//#define LASAT_BMID_SAFEPIPE30         7
+//#define LASAT_BMID_SAFEPIPE5100       8
+//#define LASAT_BMID_SAFEPIPE7100       9
+#define LASAT_BMID_UNKNOWN                              0xf
+#define LASAT_MAX_BMID_NAMES                    9   // no larger than 15!
+
+#define LASAT_HAS_EDHAC                 ( 1 << 0 )
+#define LASAT_EDHAC_FAST                ( 1 << 1 )
+#define LASAT_HAS_EADI                  ( 1 << 2 )
+#define LASAT_HAS_HIFN                  ( 1 << 3 )
+#define LASAT_HAS_ISDN                  ( 1 << 4 )
+#define LASAT_HAS_LEASEDLINE_IF         ( 1 << 5 )
+#define LASAT_HAS_HDC                   ( 1 << 6 )
+
+#define LASAT_PRID_MASQUERADE2          0
+#define LASAT_PRID_MASQUERADEPRO        1
+#define LASAT_PRID_SAFEPIPE25                   2
+#define LASAT_PRID_SAFEPIPE50                   3
+#define LASAT_PRID_SAFEPIPE100          4
+#define LASAT_PRID_SAFEPIPE5000         5
+#define LASAT_PRID_SAFEPIPE7000         6
+#define LASAT_PRID_SAFEPIPE30                   7
+#define LASAT_PRID_SAFEPIPE5100         8
+#define LASAT_PRID_SAFEPIPE7100         9
+
+#define LASAT_PRID_SAFEPIPE1110         10
+#define LASAT_PRID_SAFEPIPE3020         11
+#define LASAT_PRID_SAFEPIPE3030         12
+#define LASAT_PRID_SAFEPIPE5020         13
+#define LASAT_PRID_SAFEPIPE5030         14
+#define LASAT_PRID_SAFEPIPE1120         15
+#define LASAT_PRID_SAFEPIPE1130         16
+#define LASAT_PRID_SAFEPIPE6010         17
+#define LASAT_PRID_SAFEPIPE6110         18
+#define LASAT_PRID_SAFEPIPE6210         19
+#define LASAT_PRID_SAFEPIPE1020         20
+#define LASAT_PRID_SAFEPIPE1040         21
+#define LASAT_PRID_SAFEPIPE1060         22
+
+struct lasat_info {
+        unsigned int  li_cpu_hz;
+        unsigned int  li_bus_hz;
+        unsigned int  li_bmid;
+        unsigned int  li_memsize;
+        unsigned int  li_flash_size;
+        unsigned int  li_prid;
+        unsigned char li_bmstr[16];
+        unsigned char li_namestr[32];
+        unsigned char li_typestr[16];
+        /* Info on the Flash layout */
+        unsigned int  li_flash_base;
+        unsigned long li_flashpart_base[LASAT_MTD_LAST];
+        unsigned long li_flashpart_size[LASAT_MTD_LAST];
+        struct lasat_eeprom_struct li_eeprom_info;
+        unsigned int  li_eeprom_upgrade_version;
+        unsigned int  li_debugaccess;
+};
+
+extern struct lasat_info lasat_board_info;
+
+static inline unsigned long lasat_flash_partition_start(int partno)
+{
+        if (partno < 0 || partno >= LASAT_MTD_LAST)
+                return 0;
+
+        return lasat_board_info.li_flashpart_base[partno];
+}
+
+static inline unsigned long lasat_flash_partition_size(int partno)
+{
+        if (partno < 0 || partno >= LASAT_MTD_LAST)
+                return 0;
+
+        return lasat_board_info.li_flashpart_size[partno];
+}
+
+/* Called from setup() to initialize the global board_info struct */
+extern int lasat_init_board_info(void);
+
+/* Write the modified EEPROM info struct */
+extern void lasat_write_eeprom_info(void);
+
+#define N_MACHTYPES             2
+/* for calibration of delays */
+
+/* the lasat_ndelay function is necessary because it is used at an
+ * early stage of the boot process where ndelay is not calibrated.
+ * It is used for the bit-banging rtc and eeprom drivers */
+
+#include <asm/delay.h>
+/* calculating with the slowest board with 100 MHz clock */
+#define LASAT_100_DIVIDER 20
+/* All 200's run at 250 MHz clock */
+#define LASAT_200_DIVIDER 8
+
+extern unsigned int lasat_ndelay_divider;
+
+static inline void lasat_ndelay(unsigned int ns)
+{
+            __delay(ns / lasat_ndelay_divider);
+}
+
+extern void (* prom_printf)(const char *fmt, ...);
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
+#define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
+
+/* Lasat 100 boards */
+#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
+
+/* Lasat 200 boards */
+#define Vrc5074_PHYS_BASE       0x1fa00000
+#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
+#define PCI_WINDOW1             0x1a000000
+
+#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
new file mode 100644
index 000000000000..065474feeccc
--- /dev/null
+++ b/include/asm-mips/lasat/lasatint.h
@@ -0,0 +1,12 @@
+#define LASATINT_END 16
+
+/* lasat 100 */
+#define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
+#define LASAT_INT_MASK_REG_100          (KSEG1ADDR(0x1c890000))
+#define LASATINT_MASK_SHIFT_100         0
+
+/* lasat 200 */
+#define LASAT_INT_STATUS_REG_200        (KSEG1ADDR(0x1104003c))
+#define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
+#define LASATINT_MASK_SHIFT_200         16
+
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
new file mode 100644
index 000000000000..42a492edc40e
--- /dev/null
+++ b/include/asm-mips/lasat/picvue.h
@@ -0,0 +1,15 @@
+/* Lasat 100 */
+#define PVC_REG_100             KSEG1ADDR(0x1c820000)
+#define PVC_DATA_SHIFT_100      0
+#define PVC_DATA_M_100          0xFF
+#define PVC_E_100               (1 << 8)
+#define PVC_RW_100              (1 << 9)
+#define PVC_RS_100              (1 << 10)
+
+/* Lasat 200 */
+#define PVC_REG_200             KSEG1ADDR(0x11000000)
+#define PVC_DATA_SHIFT_200      24
+#define PVC_DATA_M_200          (0xFF << PVC_DATA_SHIFT_200)
+#define PVC_E_200               (1 << 16)
+#define PVC_RW_200              (1 << 17)
+#define PVC_RS_200              (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
new file mode 100644
index 000000000000..21d0fb7cee64
--- /dev/null
+++ b/include/asm-mips/lasat/serial.h
@@ -0,0 +1,13 @@
+#include <asm/lasat/lasat.h>
+
+/* Lasat 100 boards serial configuration */
+#define LASAT_BASE_BAUD_100             ( 7372800 / 16 ) 
+#define LASAT_UART_REGS_BASE_100        0x1c8b0000
+#define LASAT_UART_REGS_SHIFT_100       2
+#define LASATINT_UART_100               8
+
+/* * LASAT 200 boards serial configuration */
+#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12) 
+#define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
+#define LASAT_UART_REGS_SHIFT_200       3
+#define LASATINT_UART_200               13
diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
new file mode 100644
index 000000000000..291c2d01c44f
--- /dev/null
+++ b/include/asm-mips/linkage.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
new file mode 100644
index 000000000000..7eb6bf661b80
--- /dev/null
+++ b/include/asm-mips/local.h
@@ -0,0 +1,61 @@
+#ifndef _ASM_LOCAL_H
+#define _ASM_LOCAL_H
+
+#include <linux/config.h>
+#include <linux/percpu.h>
+#include <asm/atomic.h>
+
+#ifdef CONFIG_MIPS32
+
+typedef atomic_t local_t;
+
+#define LOCAL_INIT(i)   ATOMIC_INIT(i)
+#define local_read(v)   atomic_read(v)
+#define local_set(v,i)  atomic_set(v,i)
+
+#define local_inc(v)    atomic_inc(v)
+#define local_dec(v)    atomic_dec(v)
+#define local_add(i, v) atomic_add(i, v)
+#define local_sub(i, v) atomic_sub(i, v)
+
+#endif
+
+#ifdef CONFIG_MIPS64
+
+typedef atomic64_t local_t;
+
+#define LOCAL_INIT(i)   ATOMIC64_INIT(i)
+#define local_read(v)   atomic64_read(v)
+#define local_set(v,i)  atomic64_set(v,i)
+
+#define local_inc(v)    atomic64_inc(v)
+#define local_dec(v)    atomic64_dec(v)
+#define local_add(i, v) atomic64_add(i, v)
+#define local_sub(i, v) atomic64_sub(i, v)
+
+#endif
+
+#define __local_inc(v)          ((v)->counter++)
+#define __local_dec(v)          ((v)->counter--)
+#define __local_add(i,v)        ((v)->counter+=(i))
+#define __local_sub(i,v)        ((v)->counter-=(i))
+
+/*
+ * Use these for per-cpu local_t variables: on some archs they are
+ * much more efficient than these naive implementations.  Note they take
+ * a variable, not an address.
+ */
+#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
+#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
+
+#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
+#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
+#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
+#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
+
+#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
+#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
+#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
+#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
+
+#endif /* _ASM_LOCAL_H */
diff --git a/include/asm-mips/m48t35.h b/include/asm-mips/m48t35.h
new file mode 100644
index 000000000000..f44852e9a96d
--- /dev/null
+++ b/include/asm-mips/m48t35.h
@@ -0,0 +1,27 @@
+/*
+ *  Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
+ */
+#ifndef _ASM_M48T35_H
+#define _ASM_M48T35_H
+
+#include <linux/spinlock.h>
+
+extern spinlock_t rtc_lock;
+
+struct m48t35_rtc {
+        volatile u8     pad[0x7ff8];    /* starts at 0x7ff8 */
+        volatile u8     control;
+        volatile u8     sec;
+        volatile u8     min;
+        volatile u8     hour;
+        volatile u8     day;
+        volatile u8     date;
+        volatile u8     month;
+        volatile u8     year;
+};
+
+#define M48T35_RTC_SET          0x80
+#define M48T35_RTC_STOPPED      0x80
+#define M48T35_RTC_READ         0x40
+
+#endif /* _ASM_M48T35_H */
diff --git a/include/asm-mips/m48t37.h b/include/asm-mips/m48t37.h
new file mode 100644
index 000000000000..cabf86264f36
--- /dev/null
+++ b/include/asm-mips/m48t37.h
@@ -0,0 +1,35 @@
+/*
+ *  Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
+ */
+#ifndef _ASM_M48T37_H
+#define _ASM_M48T37_H
+
+#include <linux/spinlock.h>
+
+extern spinlock_t rtc_lock;
+
+struct m48t37_rtc {
+        volatile u8     pad[0x7ff0];    /* NVRAM */
+        volatile u8     flags;
+        volatile u8     century;
+        volatile u8     alarm_sec;
+        volatile u8     alarm_min;
+        volatile u8     alarm_hour;
+        volatile u8     alarm_data;
+        volatile u8     interrupts;
+        volatile u8     watchdog;
+        volatile u8     control;
+        volatile u8     sec;
+        volatile u8     min;
+        volatile u8     hour;
+        volatile u8     day;
+        volatile u8     date;
+        volatile u8     month;
+        volatile u8     year;
+};
+
+#define M48T37_RTC_SET          0x80
+#define M48T37_RTC_STOPPED      0x80
+#define M48T37_RTC_READ         0x40
+
+#endif /* _ASM_M48T37_H */
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
new file mode 100644
index 000000000000..397522ea5565
--- /dev/null
+++ b/include/asm-mips/mach-atlas/mc146818rtc.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 1999, 2000, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef __ASM_MACH_ATLAS_MC146818RTC_H
+#define __ASM_MACH_ATLAS_MC146818RTC_H
+
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+#include <asm/mips-boards/atlas.h>
+#include <asm/mips-boards/atlasint.h>
+
+#define RTC_PORT(x)     (ATLAS_RTC_ADR_REG + (x) * 8)
+#define RTC_IO_EXTENT   0x100
+#define RTC_IOMAPPED    0
+#define RTC_IRQ         ATLASINT_RTC
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
+        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
+
+        *ireg = addr;
+        return *dreg;
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
+        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
+
+        *ireg = addr;
+        *dreg = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+
+#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
new file mode 100644
index 000000000000..2b36ea346910
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -0,0 +1,1408 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2000,2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+ /*
+  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
+  */
+
+#ifndef _AU1000_H_
+#define _AU1000_H_
+
+#include <linux/config.h>
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#include <linux/delay.h>
+#include <asm/io.h>
+
+/* cpu pipeline flush */
+void static inline au_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+void static inline au_sync_udelay(int us)
+{
+        __asm__ volatile ("sync");
+        udelay(us);
+}
+
+void static inline au_sync_delay(int ms)
+{
+        __asm__ volatile ("sync");
+        mdelay(ms);
+}
+
+void static inline au_writeb(u8 val, int reg)
+{
+        *(volatile u8 *)(reg) = val;
+}
+
+void static inline au_writew(u16 val, int reg)
+{
+        *(volatile u16 *)(reg) = val;
+}
+
+void static inline au_writel(u32 val, int reg)
+{
+        *(volatile u32 *)(reg) = val;
+}
+
+static inline u8 au_readb(unsigned long port)
+{
+        return (*(volatile u8 *)port);
+}
+
+static inline u16 au_readw(unsigned long port)
+{
+        return (*(volatile u16 *)port);
+}
+
+static inline u32 au_readl(unsigned long port)
+{
+        return (*(volatile u32 *)port);
+}
+
+/* These next three functions should be a generic part of the MIPS
+ * kernel (with the 'au_' removed from the name) and selected for
+ * processors that support the instructions.
+ * Taken from PPC tree.  -- Dan
+ */
+/* Return the bit position of the most significant 1 bit in a word */
+static __inline__ int __ilog2(unsigned int x)
+{
+        int lz;
+
+        asm volatile (
+                ".set\tnoreorder\n\t"
+                ".set\tnoat\n\t"
+                ".set\tmips32\n\t"
+                "clz\t%0,%1\n\t"
+                ".set\tmips0\n\t"
+                ".set\tat\n\t"
+                ".set\treorder"
+                : "=r" (lz)
+                : "r" (x));
+
+        return 31 - lz;
+}
+
+static __inline__ int au_ffz(unsigned int x)
+{
+        if ((x = ~x) == 0)
+                return 32;
+        return __ilog2(x & -x);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int au_ffs(int x)
+{
+        return __ilog2(x & -x) + 1;
+}
+
+/* arch/mips/au1000/common/clocks.c */
+extern void set_au1x00_speed(unsigned int new_freq);
+extern unsigned int get_au1x00_speed(void);
+extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
+extern unsigned long get_au1x00_uart_baud_base(void);
+extern void set_au1x00_lcd_clock(void);
+extern unsigned int get_au1x00_lcd_clock(void);
+
+/*
+ * Every board describes its IRQ mapping with this table.
+ */
+typedef struct au1xxx_irqmap {
+        int     im_irq;
+        int     im_type;
+        int     im_request;
+} au1xxx_irq_map_t;
+
+/*
+ * init_IRQ looks for a table with this name.
+ */
+extern au1xxx_irq_map_t au1xxx_irq_map[];
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#ifdef CONFIG_PM
+/* no CP0 timer irq */
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
+#else
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+#endif
+
+/* SDRAM Controller */
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
+#define MEM_SDMODE0                0xB4000000
+#define MEM_SDMODE1                0xB4000004
+#define MEM_SDMODE2                0xB4000008
+
+#define MEM_SDADDR0                0xB400000C
+#define MEM_SDADDR1                0xB4000010
+#define MEM_SDADDR2                0xB4000014
+
+#define MEM_SDREFCFG               0xB4000018
+#define MEM_SDPRECMD               0xB400001C
+#define MEM_SDAUTOREF              0xB4000020
+
+#define MEM_SDWRMD0                0xB4000024
+#define MEM_SDWRMD1                0xB4000028
+#define MEM_SDWRMD2                0xB400002C
+
+#define MEM_SDSLEEP                0xB4000030
+#define MEM_SDSMCKE                0xB4000034
+#endif
+
+/* Static Bus Controller */
+#define MEM_STCFG0                 0xB4001000
+#define MEM_STTIME0                0xB4001004
+#define MEM_STADDR0                0xB4001008
+
+#define MEM_STCFG1                 0xB4001010
+#define MEM_STTIME1                0xB4001014
+#define MEM_STADDR1                0xB4001018
+
+#define MEM_STCFG2                 0xB4001020
+#define MEM_STTIME2                0xB4001024
+#define MEM_STADDR2                0xB4001028
+
+#define MEM_STCFG3                 0xB4001030
+#define MEM_STTIME3                0xB4001034
+#define MEM_STADDR3                0xB4001038
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_STNDCTL                0xB4001100
+#define MEM_STSTAT                 0xB4001104
+
+#define MEM_STNAND_CMD                  (0x0)
+#define MEM_STNAND_ADDR                 (0x4)
+#define MEM_STNAND_DATA                (0x20)
+#endif
+
+/* Interrupt Controller 0 */
+#define IC0_CFG0RD                 0xB0400040
+#define IC0_CFG0SET                0xB0400040
+#define IC0_CFG0CLR                0xB0400044
+
+#define IC0_CFG1RD                 0xB0400048
+#define IC0_CFG1SET                0xB0400048
+#define IC0_CFG1CLR                0xB040004C
+
+#define IC0_CFG2RD                 0xB0400050
+#define IC0_CFG2SET                0xB0400050
+#define IC0_CFG2CLR                0xB0400054
+
+#define IC0_REQ0INT                0xB0400054
+#define IC0_SRCRD                  0xB0400058
+#define IC0_SRCSET                 0xB0400058
+#define IC0_SRCCLR                 0xB040005C
+#define IC0_REQ1INT                0xB040005C
+
+#define IC0_ASSIGNRD               0xB0400060
+#define IC0_ASSIGNSET              0xB0400060
+#define IC0_ASSIGNCLR              0xB0400064
+
+#define IC0_WAKERD                 0xB0400068
+#define IC0_WAKESET                0xB0400068
+#define IC0_WAKECLR                0xB040006C
+
+#define IC0_MASKRD                 0xB0400070
+#define IC0_MASKSET                0xB0400070
+#define IC0_MASKCLR                0xB0400074
+
+#define IC0_RISINGRD               0xB0400078
+#define IC0_RISINGCLR              0xB0400078
+#define IC0_FALLINGRD              0xB040007C
+#define IC0_FALLINGCLR             0xB040007C
+
+#define IC0_TESTBIT                0xB0400080
+
+/* Interrupt Controller 1 */
+#define IC1_CFG0RD                 0xB1800040
+#define IC1_CFG0SET                0xB1800040
+#define IC1_CFG0CLR                0xB1800044
+
+#define IC1_CFG1RD                 0xB1800048
+#define IC1_CFG1SET                0xB1800048
+#define IC1_CFG1CLR                0xB180004C
+
+#define IC1_CFG2RD                 0xB1800050
+#define IC1_CFG2SET                0xB1800050
+#define IC1_CFG2CLR                0xB1800054
+
+#define IC1_REQ0INT                0xB1800054
+#define IC1_SRCRD                  0xB1800058
+#define IC1_SRCSET                 0xB1800058
+#define IC1_SRCCLR                 0xB180005C
+#define IC1_REQ1INT                0xB180005C
+
+#define IC1_ASSIGNRD               0xB1800060
+#define IC1_ASSIGNSET              0xB1800060
+#define IC1_ASSIGNCLR              0xB1800064
+
+#define IC1_WAKERD                 0xB1800068
+#define IC1_WAKESET                0xB1800068
+#define IC1_WAKECLR                0xB180006C
+
+#define IC1_MASKRD                 0xB1800070
+#define IC1_MASKSET                0xB1800070
+#define IC1_MASKCLR                0xB1800074
+
+#define IC1_RISINGRD               0xB1800078
+#define IC1_RISINGCLR              0xB1800078
+#define IC1_FALLINGRD              0xB180007C
+#define IC1_FALLINGCLR             0xB180007C
+
+#define IC1_TESTBIT                0xB1800080
+
+/* Interrupt Configuration Modes */
+#define INTC_INT_DISABLED                0
+#define INTC_INT_RISE_EDGE             0x1
+#define INTC_INT_FALL_EDGE             0x2
+#define INTC_INT_RISE_AND_FALL_EDGE    0x3
+#define INTC_INT_HIGH_LEVEL            0x5
+#define INTC_INT_LOW_LEVEL             0x6
+#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7
+
+/* Interrupt Numbers */
+/* Au1000 */
+#ifdef CONFIG_SOC_AU1000
+#define AU1000_UART0_INT          0
+#define AU1000_UART1_INT          1 /* au1000 */
+#define AU1000_UART2_INT          2 /* au1000 */
+#define AU1000_UART3_INT          3
+#define AU1000_SSI0_INT           4 /* au1000 */
+#define AU1000_SSI1_INT           5 /* au1000 */
+#define AU1000_DMA_INT_BASE       6
+#define AU1000_TOY_INT            14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
+#define AU1000_IRDA_TX_INT        22 /* au1000 */
+#define AU1000_IRDA_RX_INT        23 /* au1000 */
+#define AU1000_USB_DEV_REQ_INT    24
+#define AU1000_USB_DEV_SUS_INT    25
+#define AU1000_USB_HOST_INT       26
+#define AU1000_ACSYNC_INT         27
+#define AU1000_MAC0_DMA_INT       28
+#define AU1000_MAC1_DMA_INT       29
+#define AU1000_I2S_UO_INT         30 /* au1000 */
+#define AU1000_AC97C_INT          31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART2_ADDR                0xB1300000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1000_ETH0_BASE      0xB0500000
+#define AU1000_ETH1_BASE      0xB0510000
+#define AU1000_MAC0_ENABLE       0xB0520000
+#define AU1000_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1000
+
+/* Au1500 */
+#ifdef CONFIG_SOC_AU1500
+#define AU1500_UART0_INT          0
+#define AU1000_PCI_INTA           1 /* au1500 */
+#define AU1000_PCI_INTB           2 /* au1500 */
+#define AU1500_UART3_INT          3
+#define AU1000_PCI_INTC           4 /* au1500 */
+#define AU1000_PCI_INTD           5 /* au1500 */
+#define AU1000_DMA_INT_BASE       6
+#define AU1000_TOY_INT            14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
+#define AU1500_PCI_ERR_INT        22
+#define AU1000_USB_DEV_REQ_INT    24
+#define AU1000_USB_DEV_SUS_INT    25
+#define AU1000_USB_HOST_INT       26
+#define AU1000_ACSYNC_INT         27
+#define AU1500_MAC0_DMA_INT       28
+#define AU1500_MAC1_DMA_INT       29
+#define AU1000_AC97C_INT          31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+#define AU1500_GPIO_200           48
+#define AU1500_GPIO_201           49
+#define AU1500_GPIO_202           50
+#define AU1500_GPIO_203           51
+#define AU1500_GPIO_20            52
+#define AU1500_GPIO_204           53
+#define AU1500_GPIO_205           54
+#define AU1500_GPIO_23            55
+#define AU1500_GPIO_24            56
+#define AU1500_GPIO_25            57
+#define AU1500_GPIO_26            58
+#define AU1500_GPIO_27            59
+#define AU1500_GPIO_28            60
+#define AU1500_GPIO_206           61
+#define AU1500_GPIO_207           62
+#define AU1500_GPIO_208_215       63
+
+#define UART0_ADDR                0xB1100000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1500_ETH0_BASE          0xB1500000
+#define AU1500_ETH1_BASE          0xB1510000
+#define AU1500_MAC0_ENABLE       0xB1520000
+#define AU1500_MAC1_ENABLE       0xB1520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1500
+
+/* Au1100 */
+#ifdef CONFIG_SOC_AU1100
+#define AU1100_UART0_INT          0
+#define AU1100_UART1_INT          1
+#define AU1100_SD_INT             2
+#define AU1100_UART3_INT          3
+#define AU1000_SSI0_INT           4
+#define AU1000_SSI1_INT           5
+#define AU1000_DMA_INT_BASE       6
+#define AU1000_TOY_INT            14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
+#define AU1000_IRDA_TX_INT        22
+#define AU1000_IRDA_RX_INT        23
+#define AU1000_USB_DEV_REQ_INT    24
+#define AU1000_USB_DEV_SUS_INT    25
+#define AU1000_USB_HOST_INT       26
+#define AU1000_ACSYNC_INT         27
+#define AU1100_MAC0_DMA_INT       28
+#define AU1100_GPIO_208_215     29
+#define AU1100_LCD_INT            30
+#define AU1000_AC97C_INT          31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1100_ETH0_BASE          0xB0500000
+#define AU1100_MAC0_ENABLE       0xB0520000
+#define NUM_ETH_INTERFACES 1
+#endif // CONFIG_SOC_AU1100
+
+#ifdef CONFIG_SOC_AU1550
+#define AU1550_UART0_INT          0
+#define AU1550_PCI_INTA           1
+#define AU1550_PCI_INTB           2
+#define AU1550_DDMA_INT           3
+#define AU1550_CRYPTO_INT         4
+#define AU1550_PCI_INTC           5
+#define AU1550_PCI_INTD           6
+#define AU1550_PCI_RST_INT        7
+#define AU1550_UART1_INT          8
+#define AU1550_UART3_INT          9
+#define AU1550_PSC0_INT           10
+#define AU1550_PSC1_INT           11
+#define AU1550_PSC2_INT           12
+#define AU1550_PSC3_INT           13
+#define AU1550_TOY_INT                    14
+#define AU1550_TOY_MATCH0_INT     15
+#define AU1550_TOY_MATCH1_INT     16
+#define AU1550_TOY_MATCH2_INT     17
+#define AU1550_RTC_INT            18
+#define AU1550_RTC_MATCH0_INT     19
+#define AU1550_RTC_MATCH1_INT     20
+#define AU1550_RTC_MATCH2_INT     21
+#define AU1550_NAND_INT           23
+#define AU1550_USB_DEV_REQ_INT    24
+#define AU1550_USB_DEV_SUS_INT    25
+#define AU1550_USB_HOST_INT       26
+#define AU1000_USB_DEV_REQ_INT    AU1550_USB_DEV_REQ_INT
+#define AU1000_USB_DEV_SUS_INT    AU1550_USB_DEV_SUS_INT
+#define AU1000_USB_HOST_INT       AU1550_USB_HOST_INT
+#define AU1550_MAC0_DMA_INT       27
+#define AU1550_MAC1_DMA_INT       28
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+#define AU1550_GPIO_200           48
+#define AU1500_GPIO_201_205       49    // Logical or of GPIO201:205
+#define AU1500_GPIO_16            50
+#define AU1500_GPIO_17            51
+#define AU1500_GPIO_20            52
+#define AU1500_GPIO_21            53
+#define AU1500_GPIO_22            54
+#define AU1500_GPIO_23            55
+#define AU1500_GPIO_24            56
+#define AU1500_GPIO_25            57
+#define AU1500_GPIO_26            58
+#define AU1500_GPIO_27            59
+#define AU1500_GPIO_28            60
+#define AU1500_GPIO_206           61
+#define AU1500_GPIO_207           62
+#define AU1500_GPIO_208_218       63    // Logical or of GPIO208:218
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB4027ffc
+
+#define AU1550_ETH0_BASE      0xB0500000
+#define AU1550_ETH1_BASE      0xB0510000
+#define AU1550_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1550
+
+#ifdef CONFIG_SOC_AU1200
+#define AU1200_UART0_INT          0
+#define AU1200_SWT_INT            1
+#define AU1200_SD_INT             2
+#define AU1200_DDMA_INT           3
+#define AU1200_MAE_BE_INT         4
+#define AU1200_GPIO_200           5
+#define AU1200_GPIO_201           6
+#define AU1200_GPIO_202           7
+#define AU1200_UART1_INT          8
+#define AU1200_MAE_FE_INT         9
+#define AU1200_PSC0_INT           10
+#define AU1200_PSC1_INT           11
+#define AU1200_AES_INT            12
+#define AU1200_CAMERA_INT         13
+#define AU1200_TOY_INT                    14
+#define AU1200_TOY_MATCH0_INT     15
+#define AU1200_TOY_MATCH1_INT     16
+#define AU1200_TOY_MATCH2_INT     17
+#define AU1200_RTC_INT            18
+#define AU1200_RTC_MATCH0_INT     19
+#define AU1200_RTC_MATCH1_INT     20
+#define AU1200_RTC_MATCH2_INT     21
+#define AU1200_NAND_INT           23
+#define AU1200_GPIO_204           24
+#define AU1200_GPIO_205           25
+#define AU1200_GPIO_206           26
+#define AU1200_GPIO_207           27
+#define AU1200_GPIO_208_215       28 // Logical OR of 208:215
+#define AU1200_USB_INT            29
+#define AU1200_LCD_INT            30
+#define AU1200_MAE_BOTH_INT       31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+
+#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB4027ffc
+
+// these are here for prototyping on au1550 (do not exist on au1200)
+#define AU1200_ETH0_BASE      0xB0500000
+#define AU1200_ETH1_BASE      0xB0510000
+#define AU1200_MAC0_ENABLE       0xB0520000
+#define AU1200_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1200
+
+#define AU1000_LAST_INTC0_INT     31
+#define AU1000_MAX_INTR           63
+
+
+/* Programmable Counters 0 and 1 */
+#define SYS_BASE                   0xB1900000
+#define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
+  #define SYS_CNTRL_E1S            (1<<23)
+  #define SYS_CNTRL_T1S            (1<<20)
+  #define SYS_CNTRL_M21            (1<<19)
+  #define SYS_CNTRL_M11            (1<<18)
+  #define SYS_CNTRL_M01            (1<<17)
+  #define SYS_CNTRL_C1S            (1<<16)
+  #define SYS_CNTRL_BP             (1<<14)
+  #define SYS_CNTRL_EN1            (1<<13)
+  #define SYS_CNTRL_BT1            (1<<12)
+  #define SYS_CNTRL_EN0            (1<<11)
+  #define SYS_CNTRL_BT0            (1<<10)
+  #define SYS_CNTRL_E0             (1<<8)
+  #define SYS_CNTRL_E0S            (1<<7)
+  #define SYS_CNTRL_32S            (1<<5)
+  #define SYS_CNTRL_T0S            (1<<4)
+  #define SYS_CNTRL_M20            (1<<3)
+  #define SYS_CNTRL_M10            (1<<2)
+  #define SYS_CNTRL_M00            (1<<1)
+  #define SYS_CNTRL_C0S            (1<<0)
+
+/* Programmable Counter 0 Registers */
+#define SYS_TOYTRIM                 (SYS_BASE + 0)
+#define SYS_TOYWRITE                (SYS_BASE + 4)
+#define SYS_TOYMATCH0               (SYS_BASE + 8)
+#define SYS_TOYMATCH1               (SYS_BASE + 0xC)
+#define SYS_TOYMATCH2               (SYS_BASE + 0x10)
+#define SYS_TOYREAD                 (SYS_BASE + 0x40)
+
+/* Programmable Counter 1 Registers */
+#define SYS_RTCTRIM                 (SYS_BASE + 0x44)
+#define SYS_RTCWRITE                (SYS_BASE + 0x48)
+#define SYS_RTCMATCH0               (SYS_BASE + 0x4C)
+#define SYS_RTCMATCH1               (SYS_BASE + 0x50)
+#define SYS_RTCMATCH2               (SYS_BASE + 0x54)
+#define SYS_RTCREAD                 (SYS_BASE + 0x58)
+
+/* I2S Controller */
+#define I2S_DATA                    0xB1000000
+  #define I2S_DATA_MASK        (0xffffff)
+#define I2S_CONFIG                0xB1000004
+  #define I2S_CONFIG_XU        (1<<25)
+  #define I2S_CONFIG_XO        (1<<24)
+  #define I2S_CONFIG_RU        (1<<23)
+  #define I2S_CONFIG_RO        (1<<22)
+  #define I2S_CONFIG_TR        (1<<21)
+  #define I2S_CONFIG_TE        (1<<20)
+  #define I2S_CONFIG_TF        (1<<19)
+  #define I2S_CONFIG_RR        (1<<18)
+  #define I2S_CONFIG_RE        (1<<17)
+  #define I2S_CONFIG_RF        (1<<16)
+  #define I2S_CONFIG_PD        (1<<11)
+  #define I2S_CONFIG_LB        (1<<10)
+  #define I2S_CONFIG_IC        (1<<9)
+  #define I2S_CONFIG_FM_BIT    7
+  #define I2S_CONFIG_FM_MASK     (0x3 << I2S_CONFIG_FM_BIT)
+    #define I2S_CONFIG_FM_I2S    (0x0 << I2S_CONFIG_FM_BIT)
+    #define I2S_CONFIG_FM_LJ     (0x1 << I2S_CONFIG_FM_BIT)
+    #define I2S_CONFIG_FM_RJ     (0x2 << I2S_CONFIG_FM_BIT)
+  #define I2S_CONFIG_TN        (1<<6)
+  #define I2S_CONFIG_RN        (1<<5)
+  #define I2S_CONFIG_SZ_BIT    0
+  #define I2S_CONFIG_SZ_MASK     (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL                0xB1000008
+  #define I2S_CONTROL_D         (1<<1)
+  #define I2S_CONTROL_CE        (1<<0)
+
+/* USB Host Controller */
+#define USB_OHCI_LEN              0x00100000
+
+/* USB Device Controller */
+#define USBD_EP0RD                0xB0200000
+#define USBD_EP0WR                0xB0200004
+#define USBD_EP2WR                0xB0200008
+#define USBD_EP3WR                0xB020000C
+#define USBD_EP4RD                0xB0200010
+#define USBD_EP5RD                0xB0200014
+#define USBD_INTEN                0xB0200018
+#define USBD_INTSTAT              0xB020001C
+  #define USBDEV_INT_SOF       (1<<12)
+  #define USBDEV_INT_HF_BIT    6
+  #define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)
+  #define USBDEV_INT_CMPLT_BIT  0
+  #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
+#define USBD_CONFIG               0xB0200020
+#define USBD_EP0CS                0xB0200024
+#define USBD_EP2CS                0xB0200028
+#define USBD_EP3CS                0xB020002C
+#define USBD_EP4CS                0xB0200030
+#define USBD_EP5CS                0xB0200034
+  #define USBDEV_CS_SU         (1<<14)
+  #define USBDEV_CS_NAK        (1<<13)
+  #define USBDEV_CS_ACK        (1<<12)
+  #define USBDEV_CS_BUSY       (1<<11)
+  #define USBDEV_CS_TSIZE_BIT  1
+  #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
+  #define USBDEV_CS_STALL      (1<<0)
+#define USBD_EP0RDSTAT            0xB0200040
+#define USBD_EP0WRSTAT            0xB0200044
+#define USBD_EP2WRSTAT            0xB0200048
+#define USBD_EP3WRSTAT            0xB020004C
+#define USBD_EP4RDSTAT            0xB0200050
+#define USBD_EP5RDSTAT            0xB0200054
+  #define USBDEV_FSTAT_FLUSH     (1<<6)
+  #define USBDEV_FSTAT_UF        (1<<5)
+  #define USBDEV_FSTAT_OF        (1<<4)
+  #define USBDEV_FSTAT_FCNT_BIT  0
+  #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
+#define USBD_ENABLE               0xB0200058
+  #define USBDEV_ENABLE (1<<1)
+  #define USBDEV_CE     (1<<0)
+
+/* Ethernet Controllers  */
+
+/* 4 byte offsets from AU1000_ETH_BASE */
+#define MAC_CONTROL                     0x0
+  #define MAC_RX_ENABLE               (1<<2)
+  #define MAC_TX_ENABLE               (1<<3)
+  #define MAC_DEF_CHECK               (1<<5)
+  #define MAC_SET_BL(X)       (((X)&0x3)<<6)
+  #define MAC_AUTO_PAD                (1<<8)
+  #define MAC_DISABLE_RETRY          (1<<10)
+  #define MAC_DISABLE_BCAST          (1<<11)
+  #define MAC_LATE_COL               (1<<12)
+  #define MAC_HASH_MODE              (1<<13)
+  #define MAC_HASH_ONLY              (1<<15)
+  #define MAC_PASS_ALL               (1<<16)
+  #define MAC_INVERSE_FILTER         (1<<17)
+  #define MAC_PROMISCUOUS            (1<<18)
+  #define MAC_PASS_ALL_MULTI         (1<<19)
+  #define MAC_FULL_DUPLEX            (1<<20)
+  #define MAC_NORMAL_MODE                 0
+  #define MAC_INT_LOOPBACK           (1<<21)
+  #define MAC_EXT_LOOPBACK           (1<<22)
+  #define MAC_DISABLE_RX_OWN         (1<<23)
+  #define MAC_BIG_ENDIAN             (1<<30)
+  #define MAC_RX_ALL                 (1<<31)
+#define MAC_ADDRESS_HIGH                0x4
+#define MAC_ADDRESS_LOW                 0x8
+#define MAC_MCAST_HIGH                  0xC
+#define MAC_MCAST_LOW                  0x10
+#define MAC_MII_CNTRL                  0x14
+  #define MAC_MII_BUSY                (1<<0)
+  #define MAC_MII_READ                     0
+  #define MAC_MII_WRITE               (1<<1)
+  #define MAC_SET_MII_SELECT_REG(X)   (((X)&0x1f)<<6)
+  #define MAC_SET_MII_SELECT_PHY(X)   (((X)&0x1f)<<11)
+#define MAC_MII_DATA                   0x18
+#define MAC_FLOW_CNTRL                 0x1C
+  #define MAC_FLOW_CNTRL_BUSY         (1<<0)
+  #define MAC_FLOW_CNTRL_ENABLE       (1<<1)
+  #define MAC_PASS_CONTROL            (1<<2)
+  #define MAC_SET_PAUSE(X)        (((X)&0xffff)<<16)
+#define MAC_VLAN1_TAG                  0x20
+#define MAC_VLAN2_TAG                  0x24
+
+/* Ethernet Controller Enable */
+
+  #define MAC_EN_CLOCK_ENABLE         (1<<0)
+  #define MAC_EN_RESET0               (1<<1)
+  #define MAC_EN_TOSS                 (0<<2)
+  #define MAC_EN_CACHEABLE            (1<<3)
+  #define MAC_EN_RESET1               (1<<4)
+  #define MAC_EN_RESET2               (1<<5)
+  #define MAC_DMA_RESET               (1<<6)
+
+/* Ethernet Controller DMA Channels */
+
+#define MAC0_TX_DMA_ADDR         0xB4004000
+#define MAC1_TX_DMA_ADDR         0xB4004200
+/* offsets from MAC_TX_RING_ADDR address */
+#define MAC_TX_BUFF0_STATUS             0x0
+  #define TX_FRAME_ABORTED            (1<<0)
+  #define TX_JAB_TIMEOUT              (1<<1)
+  #define TX_NO_CARRIER               (1<<2)
+  #define TX_LOSS_CARRIER             (1<<3)
+  #define TX_EXC_DEF                  (1<<4)
+  #define TX_LATE_COLL_ABORT          (1<<5)
+  #define TX_EXC_COLL                 (1<<6)
+  #define TX_UNDERRUN                 (1<<7)
+  #define TX_DEFERRED                 (1<<8)
+  #define TX_LATE_COLL                (1<<9)
+  #define TX_COLL_CNT_MASK         (0xF<<10)
+  #define TX_PKT_RETRY               (1<<31)
+#define MAC_TX_BUFF0_ADDR                0x4
+  #define TX_DMA_ENABLE               (1<<0)
+  #define TX_T_DONE                   (1<<1)
+  #define TX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
+#define MAC_TX_BUFF0_LEN                 0x8
+#define MAC_TX_BUFF1_STATUS             0x10
+#define MAC_TX_BUFF1_ADDR               0x14
+#define MAC_TX_BUFF1_LEN                0x18
+#define MAC_TX_BUFF2_STATUS             0x20
+#define MAC_TX_BUFF2_ADDR               0x24
+#define MAC_TX_BUFF2_LEN                0x28
+#define MAC_TX_BUFF3_STATUS             0x30
+#define MAC_TX_BUFF3_ADDR               0x34
+#define MAC_TX_BUFF3_LEN                0x38
+
+#define MAC0_RX_DMA_ADDR         0xB4004100
+#define MAC1_RX_DMA_ADDR         0xB4004300
+/* offsets from MAC_RX_RING_ADDR */
+#define MAC_RX_BUFF0_STATUS              0x0
+  #define RX_FRAME_LEN_MASK           0x3fff
+  #define RX_WDOG_TIMER              (1<<14)
+  #define RX_RUNT                    (1<<15)
+  #define RX_OVERLEN                 (1<<16)
+  #define RX_COLL                    (1<<17)
+  #define RX_ETHER                   (1<<18)
+  #define RX_MII_ERROR               (1<<19)
+  #define RX_DRIBBLING               (1<<20)
+  #define RX_CRC_ERROR               (1<<21)
+  #define RX_VLAN1                   (1<<22)
+  #define RX_VLAN2                   (1<<23)
+  #define RX_LEN_ERROR               (1<<24)
+  #define RX_CNTRL_FRAME             (1<<25)
+  #define RX_U_CNTRL_FRAME           (1<<26)
+  #define RX_MCAST_FRAME             (1<<27)
+  #define RX_BCAST_FRAME             (1<<28)
+  #define RX_FILTER_FAIL             (1<<29)
+  #define RX_PACKET_FILTER           (1<<30)
+  #define RX_MISSED_FRAME            (1<<31)
+
+  #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
+                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+#define MAC_RX_BUFF0_ADDR                0x4
+  #define RX_DMA_ENABLE               (1<<0)
+  #define RX_T_DONE                   (1<<1)
+  #define RX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
+  #define RX_SET_BUFF_ADDR(X)     ((X)&0xffffffc0)
+#define MAC_RX_BUFF1_STATUS              0x10
+#define MAC_RX_BUFF1_ADDR                0x14
+#define MAC_RX_BUFF2_STATUS              0x20
+#define MAC_RX_BUFF2_ADDR                0x24
+#define MAC_RX_BUFF3_STATUS              0x30
+#define MAC_RX_BUFF3_ADDR                0x34
+
+
+/* UARTS 0-3 */
+#define UART_BASE                 UART0_ADDR
+#define UART_DEBUG_BASE           UART3_ADDR
+
+#define UART_RX         0       /* Receive buffer */
+#define UART_TX         4       /* Transmit buffer */
+#define UART_IER        8       /* Interrupt Enable Register */
+#define UART_IIR        0xC     /* Interrupt ID Register */
+#define UART_FCR        0x10    /* FIFO Control Register */
+#define UART_LCR        0x14    /* Line Control Register */
+#define UART_MCR        0x18    /* Modem Control Register */
+#define UART_LSR        0x1C    /* Line Status Register */
+#define UART_MSR        0x20    /* Modem Status Register */
+#define UART_CLK        0x28    /* Baud Rate Clock Divider */
+#define UART_MOD_CNTRL  0x100   /* Module Control */
+
+#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK   0xF0 /* Mask for the FIFO trigger range */
+#define UART_FCR_R_TRIGGER_1    0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR_R_TRIGGER_4    0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR_R_TRIGGER_8    0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
+#define UART_FCR_T_TRIGGER_0    0x00 /* Mask for transmit trigger set at 0 */
+#define UART_FCR_T_TRIGGER_4    0x10 /* Mask for transmit trigger set at 4 */
+#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
+#define UART_FCR_T_TRIGGER_12   0x30 /* Mask for transmit trigger set at 12 */
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_SBC    0x40    /* Set break control */
+#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
+#define UART_LCR_EPAR   0x10    /* Even parity select */
+#define UART_LCR_PARITY 0x08    /* Parity Enable */
+#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT   0x40    /* Transmitter empty */
+#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
+#define UART_LSR_BI     0x10    /* Break interrupt indicator */
+#define UART_LSR_FE     0x08    /* Frame error indicator */
+#define UART_LSR_PE     0x04    /* Parity error indicator */
+#define UART_LSR_OE     0x02    /* Overrun error indicator */
+#define UART_LSR_DR     0x01    /* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
+#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
+#define UART_IIR_MSI    0x00    /* Modem status interrupt */
+#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
+#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
+#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
+#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
+#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
+#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
+#define UART_MCR_OUT2   0x08    /* Out2 complement */
+#define UART_MCR_OUT1   0x04    /* Out1 complement */
+#define UART_MCR_RTS    0x02    /* RTS complement */
+#define UART_MCR_DTR    0x01    /* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
+#define UART_MSR_RI     0x40    /* Ring Indicator */
+#define UART_MSR_DSR    0x20    /* Data Set Ready */
+#define UART_MSR_CTS    0x10    /* Clear to Send */
+#define UART_MSR_DDCD   0x08    /* Delta DCD */
+#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
+#define UART_MSR_DDSR   0x02    /* Delta DSR */
+#define UART_MSR_DCTS   0x01    /* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+
+
+
+/* SSIO */
+#define SSI0_STATUS                0xB1600000
+  #define SSI_STATUS_BF              (1<<4)
+  #define SSI_STATUS_OF              (1<<3)
+  #define SSI_STATUS_UF              (1<<2)
+  #define SSI_STATUS_D               (1<<1)
+  #define SSI_STATUS_B               (1<<0)
+#define SSI0_INT                   0xB1600004
+  #define SSI_INT_OI                 (1<<3)
+  #define SSI_INT_UI                 (1<<2)
+  #define SSI_INT_DI                 (1<<1)
+#define SSI0_INT_ENABLE            0xB1600008
+  #define SSI_INTE_OIE               (1<<3)
+  #define SSI_INTE_UIE               (1<<2)
+  #define SSI_INTE_DIE               (1<<1)
+#define SSI0_CONFIG                0xB1600020
+  #define SSI_CONFIG_AO              (1<<24)
+  #define SSI_CONFIG_DO              (1<<23)
+  #define SSI_CONFIG_ALEN_BIT        20
+    #define SSI_CONFIG_ALEN_MASK       (0x7<<20)
+  #define SSI_CONFIG_DLEN_BIT        16
+    #define SSI_CONFIG_DLEN_MASK       (0x7<<16)
+  #define SSI_CONFIG_DD              (1<<11)
+  #define SSI_CONFIG_AD              (1<<10)
+  #define SSI_CONFIG_BM_BIT          8
+    #define SSI_CONFIG_BM_MASK         (0x3<<8)
+  #define SSI_CONFIG_CE              (1<<7)
+  #define SSI_CONFIG_DP              (1<<6)
+  #define SSI_CONFIG_DL              (1<<5)
+  #define SSI_CONFIG_EP              (1<<4)
+#define SSI0_ADATA                 0xB1600024
+  #define SSI_AD_D                   (1<<24)
+  #define SSI_AD_ADDR_BIT            16
+    #define SSI_AD_ADDR_MASK           (0xff<<16)
+  #define SSI_AD_DATA_BIT            0
+    #define SSI_AD_DATA_MASK           (0xfff<<0)
+#define SSI0_CLKDIV                0xB1600028
+#define SSI0_CONTROL               0xB1600100
+  #define SSI_CONTROL_CD             (1<<1)
+  #define SSI_CONTROL_E              (1<<0)
+
+/* SSI1 */
+#define SSI1_STATUS                0xB1680000
+#define SSI1_INT                   0xB1680004
+#define SSI1_INT_ENABLE            0xB1680008
+#define SSI1_CONFIG                0xB1680020
+#define SSI1_ADATA                 0xB1680024
+#define SSI1_CLKDIV                0xB1680028
+#define SSI1_ENABLE                0xB1680100
+
+/*
+ * Register content definitions
+ */
+#define SSI_STATUS_BF                           (1<<4)
+#define SSI_STATUS_OF                           (1<<3)
+#define SSI_STATUS_UF                           (1<<2)
+#define SSI_STATUS_D                            (1<<1)
+#define SSI_STATUS_B                            (1<<0)
+
+/* SSI_INT */
+#define SSI_INT_OI                                      (1<<3)
+#define SSI_INT_UI                                      (1<<2)
+#define SSI_INT_DI                                      (1<<1)
+
+/* SSI_INTEN */
+#define SSI_INTEN_OIE                           (1<<3)
+#define SSI_INTEN_UIE                           (1<<2)
+#define SSI_INTEN_DIE                           (1<<1)
+
+#define SSI_CONFIG_AO                           (1<<24)
+#define SSI_CONFIG_DO                           (1<<23)
+#define SSI_CONFIG_ALEN                         (7<<20)
+#define SSI_CONFIG_DLEN                         (15<<16)
+#define SSI_CONFIG_DD                           (1<<11)
+#define SSI_CONFIG_AD                           (1<<10)
+#define SSI_CONFIG_BM                           (3<<8)
+#define SSI_CONFIG_CE                           (1<<7)
+#define SSI_CONFIG_DP                           (1<<6)
+#define SSI_CONFIG_DL                           (1<<5)
+#define SSI_CONFIG_EP                           (1<<4)
+#define SSI_CONFIG_ALEN_N(N)            ((N-1)<<20)
+#define SSI_CONFIG_DLEN_N(N)            ((N-1)<<16)
+#define SSI_CONFIG_BM_HI                        (0<<8)
+#define SSI_CONFIG_BM_LO                        (1<<8)
+#define SSI_CONFIG_BM_CY                        (2<<8)
+
+#define SSI_ADATA_D                                     (1<<24)
+#define SSI_ADATA_ADDR                          (0xFF<<16)
+#define SSI_ADATA_DATA                          (0x0FFF)
+#define SSI_ADATA_ADDR_N(N)                     (N<<16)
+
+#define SSI_ENABLE_CD                           (1<<1)
+#define SSI_ENABLE_E                            (1<<0)
+
+
+/* IrDA Controller */
+#define IRDA_BASE                 0xB0300000
+#define IR_RING_PTR_STATUS        (IRDA_BASE+0x00)
+#define IR_RING_BASE_ADDR_H       (IRDA_BASE+0x04)
+#define IR_RING_BASE_ADDR_L       (IRDA_BASE+0x08)
+#define IR_RING_SIZE              (IRDA_BASE+0x0C)
+#define IR_RING_PROMPT            (IRDA_BASE+0x10)
+#define IR_RING_ADDR_CMPR         (IRDA_BASE+0x14)
+#define IR_INT_CLEAR              (IRDA_BASE+0x18)
+#define IR_CONFIG_1               (IRDA_BASE+0x20)
+  #define IR_RX_INVERT_LED        (1<<0)
+  #define IR_TX_INVERT_LED        (1<<1)
+  #define IR_ST                   (1<<2)
+  #define IR_SF                   (1<<3)
+  #define IR_SIR                  (1<<4)
+  #define IR_MIR                  (1<<5)
+  #define IR_FIR                  (1<<6)
+  #define IR_16CRC                (1<<7)
+  #define IR_TD                   (1<<8)
+  #define IR_RX_ALL               (1<<9)
+  #define IR_DMA_ENABLE           (1<<10)
+  #define IR_RX_ENABLE            (1<<11)
+  #define IR_TX_ENABLE            (1<<12)
+  #define IR_LOOPBACK             (1<<14)
+  #define IR_SIR_MODE             (IR_SIR | IR_DMA_ENABLE | \
+                                   IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS              (IRDA_BASE+0x24)
+#define IR_ENABLE                 (IRDA_BASE+0x28)
+  #define IR_RX_STATUS            (1<<9)
+  #define IR_TX_STATUS            (1<<10)
+#define IR_READ_PHY_CONFIG        (IRDA_BASE+0x2C)
+#define IR_WRITE_PHY_CONFIG       (IRDA_BASE+0x30)
+#define IR_MAX_PKT_LEN            (IRDA_BASE+0x34)
+#define IR_RX_BYTE_CNT            (IRDA_BASE+0x38)
+#define IR_CONFIG_2               (IRDA_BASE+0x3C)
+  #define IR_MODE_INV             (1<<0)
+  #define IR_ONE_PIN              (1<<1)
+#define IR_INTERFACE_CONFIG       (IRDA_BASE+0x40)
+
+/* GPIO */
+#define SYS_PINFUNC               0xB190002C
+  #define SYS_PF_USB                    (1<<15) /* 2nd USB device/host */
+  #define SYS_PF_U3                     (1<<14) /* GPIO23/U3TXD */
+  #define SYS_PF_U2                     (1<<13) /* GPIO22/U2TXD */
+  #define SYS_PF_U1                     (1<<12) /* GPIO21/U1TXD */
+  #define SYS_PF_SRC                    (1<<11) /* GPIO6/SROMCKE */
+  #define SYS_PF_CK5                    (1<<10) /* GPIO3/CLK5 */
+  #define SYS_PF_CK4                    (1<<9)  /* GPIO2/CLK4 */
+  #define SYS_PF_IRF                    (1<<8)  /* GPIO15/IRFIRSEL */
+  #define SYS_PF_UR3                    (1<<7)  /* GPIO[14:9]/UART3 */
+  #define SYS_PF_I2D                    (1<<6)  /* GPIO8/I2SDI */
+  #define SYS_PF_I2S                    (1<<5)  /* I2S/GPIO[29:31] */
+  #define SYS_PF_NI2                    (1<<4)  /* NI2/GPIO[24:28] */
+  #define SYS_PF_U0                     (1<<3)  /* U0TXD/GPIO20 */
+  #define SYS_PF_RD                     (1<<2)  /* IRTXD/GPIO19 */
+  #define SYS_PF_A97                    (1<<1)  /* AC97/SSL1 */
+  #define SYS_PF_S0                     (1<<0)  /* SSI_0/GPIO[16:18] */
+
+/* Au1100 Only */
+  #define SYS_PF_PC                     (1<<18) /* PCMCIA/GPIO[207:204] */
+  #define SYS_PF_LCD                    (1<<17) /* extern lcd/GPIO[203:200] */
+  #define SYS_PF_CS                     (1<<16) /* EXTCLK0/32khz to gpio2 */
+  #define SYS_PF_EX0                    (1<<9)  /* gpio2/clock */
+
+/* Au1550 Only.  Redefines lots of pins */
+  #define SYS_PF_PSC2_MASK              (7 << 17)
+  #define SYS_PF_PSC2_AC97              (0)
+  #define SYS_PF_PSC2_SPI               (0)
+  #define SYS_PF_PSC2_I2S               (1 << 17)
+  #define SYS_PF_PSC2_SMBUS             (3 << 17)
+  #define SYS_PF_PSC2_GPIO              (7 << 17)
+  #define SYS_PF_PSC3_MASK              (7 << 20)
+  #define SYS_PF_PSC3_AC97              (0)
+  #define SYS_PF_PSC3_SPI               (0)
+  #define SYS_PF_PSC3_I2S               (1 << 20)
+  #define SYS_PF_PSC3_SMBUS             (3 << 20)
+  #define SYS_PF_PSC3_GPIO              (7 << 20)
+  #define SYS_PF_PSC1_S1                (1 << 1)
+  #define SYS_PF_MUST_BE_SET            ((1 << 5) | (1 << 2))
+
+#define SYS_TRIOUTRD              0xB1900100
+#define SYS_TRIOUTCLR             0xB1900100
+#define SYS_OUTPUTRD              0xB1900108
+#define SYS_OUTPUTSET             0xB1900108
+#define SYS_OUTPUTCLR             0xB190010C
+#define SYS_PINSTATERD            0xB1900110
+#define SYS_PININPUTEN            0xB1900110
+
+/* GPIO2, Au1500, Au1550 only */
+#define GPIO2_BASE                0xB1700000
+#define GPIO2_DIR                 (GPIO2_BASE + 0)
+#define GPIO2_OUTPUT              (GPIO2_BASE + 8)
+#define GPIO2_PINSTATE            (GPIO2_BASE + 0xC)
+#define GPIO2_INTENABLE           (GPIO2_BASE + 0x10)
+#define GPIO2_ENABLE              (GPIO2_BASE + 0x14)
+
+/* Power Management */
+#define SYS_SCRATCH0              0xB1900018
+#define SYS_SCRATCH1              0xB190001C
+#define SYS_WAKEMSK               0xB1900034
+#define SYS_ENDIAN                0xB1900038
+#define SYS_POWERCTRL             0xB190003C
+#define SYS_WAKESRC               0xB190005C
+#define SYS_SLPPWR                0xB1900078
+#define SYS_SLEEP                 0xB190007C
+
+/* Clock Controller */
+#define SYS_FREQCTRL0             0xB1900020
+  #define SYS_FC_FRDIV2_BIT         22
+  #define SYS_FC_FRDIV2_MASK        (0xff << SYS_FC_FRDIV2_BIT)
+  #define SYS_FC_FE2                (1<<21)
+  #define SYS_FC_FS2                (1<<20)
+  #define SYS_FC_FRDIV1_BIT         12
+  #define SYS_FC_FRDIV1_MASK        (0xff << SYS_FC_FRDIV1_BIT)
+  #define SYS_FC_FE1                (1<<11)
+  #define SYS_FC_FS1                (1<<10)
+  #define SYS_FC_FRDIV0_BIT         2
+  #define SYS_FC_FRDIV0_MASK        (0xff << SYS_FC_FRDIV0_BIT)
+  #define SYS_FC_FE0                (1<<1)
+  #define SYS_FC_FS0                (1<<0)
+#define SYS_FREQCTRL1             0xB1900024
+  #define SYS_FC_FRDIV5_BIT         22
+  #define SYS_FC_FRDIV5_MASK        (0xff << SYS_FC_FRDIV5_BIT)
+  #define SYS_FC_FE5                (1<<21)
+  #define SYS_FC_FS5                (1<<20)
+  #define SYS_FC_FRDIV4_BIT         12
+  #define SYS_FC_FRDIV4_MASK        (0xff << SYS_FC_FRDIV4_BIT)
+  #define SYS_FC_FE4                (1<<11)
+  #define SYS_FC_FS4                (1<<10)
+  #define SYS_FC_FRDIV3_BIT         2
+  #define SYS_FC_FRDIV3_MASK        (0xff << SYS_FC_FRDIV3_BIT)
+  #define SYS_FC_FE3                (1<<1)
+  #define SYS_FC_FS3                (1<<0)
+#define SYS_CLKSRC                0xB1900028
+  #define SYS_CS_ME1_BIT            27
+  #define SYS_CS_ME1_MASK           (0x7<<SYS_CS_ME1_BIT)
+  #define SYS_CS_DE1                (1<<26)
+  #define SYS_CS_CE1                (1<<25)
+  #define SYS_CS_ME0_BIT            22
+  #define SYS_CS_ME0_MASK           (0x7<<SYS_CS_ME0_BIT)
+  #define SYS_CS_DE0                (1<<21)
+  #define SYS_CS_CE0                (1<<20)
+  #define SYS_CS_MI2_BIT            17
+  #define SYS_CS_MI2_MASK           (0x7<<SYS_CS_MI2_BIT)
+  #define SYS_CS_DI2                (1<<16)
+  #define SYS_CS_CI2                (1<<15)
+  #define SYS_CS_MUH_BIT            12
+  #define SYS_CS_MUH_MASK           (0x7<<SYS_CS_MUH_BIT)
+  #define SYS_CS_DUH                (1<<11)
+  #define SYS_CS_CUH                (1<<10)
+  #define SYS_CS_MUD_BIT            7
+  #define SYS_CS_MUD_MASK           (0x7<<SYS_CS_MUD_BIT)
+  #define SYS_CS_DUD                (1<<6)
+  #define SYS_CS_CUD                (1<<5)
+  #define SYS_CS_MIR_BIT            2
+  #define SYS_CS_MIR_MASK           (0x7<<SYS_CS_MIR_BIT)
+  #define SYS_CS_DIR                (1<<1)
+  #define SYS_CS_CIR                (1<<0)
+
+  #define SYS_CS_MUX_AUX            0x1
+  #define SYS_CS_MUX_FQ0            0x2
+  #define SYS_CS_MUX_FQ1            0x3
+  #define SYS_CS_MUX_FQ2            0x4
+  #define SYS_CS_MUX_FQ3            0x5
+  #define SYS_CS_MUX_FQ4            0x6
+  #define SYS_CS_MUX_FQ5            0x7
+#define SYS_CPUPLL                0xB1900060
+#define SYS_AUXPLL                0xB1900064
+
+/* AC97 Controller */
+#define AC97C_CONFIG              0xB0000000
+  #define AC97C_RECV_SLOTS_BIT  13
+  #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
+  #define AC97C_XMIT_SLOTS_BIT  3
+  #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
+  #define AC97C_SG              (1<<2)
+  #define AC97C_SYNC            (1<<1)
+  #define AC97C_RESET           (1<<0)
+#define AC97C_STATUS              0xB0000004
+  #define AC97C_XU              (1<<11)
+  #define AC97C_XO              (1<<10)
+  #define AC97C_RU              (1<<9)
+  #define AC97C_RO              (1<<8)
+  #define AC97C_READY           (1<<7)
+  #define AC97C_CP              (1<<6)
+  #define AC97C_TR              (1<<5)
+  #define AC97C_TE              (1<<4)
+  #define AC97C_TF              (1<<3)
+  #define AC97C_RR              (1<<2)
+  #define AC97C_RE              (1<<1)
+  #define AC97C_RF              (1<<0)
+#define AC97C_DATA                0xB0000008
+#define AC97C_CMD                 0xB000000C
+  #define AC97C_WD_BIT          16
+  #define AC97C_READ            (1<<7)
+  #define AC97C_INDEX_MASK      0x7f
+#define AC97C_CNTRL               0xB0000010
+  #define AC97C_RS              (1<<1)
+  #define AC97C_CE              (1<<0)
+
+
+/* Secure Digital (SD) Controller */
+#define SD0_XMIT_FIFO   0xB0600000
+#define SD0_RECV_FIFO   0xB0600004
+#define SD1_XMIT_FIFO   0xB0680000
+#define SD1_RECV_FIFO   0xB0680004
+
+
+#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+/* Au1500 PCI Controller */
+#define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
+#define Au1500_PCI_CMEM           (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG            (Au1500_CFG_BASE + 4)
+  #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
+#define Au1500_PCI_B2BMASK_CCH    (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID       (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID        (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV     (Au1500_CFG_BASE + 0x14)
+#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
+#define Au1500_PCI_ERR_ADDR       (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK    (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID             (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD        (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV       (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE        (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR           (Au1500_CFG_BASE + 0x110)
+
+#define Au1500_PCI_HDR            0xB4005100 // virtual, kseg0 addr
+
+/* All of our structures, like pci resource, have 32 bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32 bit type.  We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
+ * addresses.  For PCI IO, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
+ */
+#define Au1500_EXT_CFG            0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1      0x680000000ULL
+#define Au1500_PCI_IO_START       0x500000000ULL
+#define Au1500_PCI_IO_END         0x5000FFFFFULL
+#define Au1500_PCI_MEM_START      0x440000000ULL
+#define Au1500_PCI_MEM_END        0x44FFFFFFFULL
+
+#define PCI_IO_START    (Au1500_PCI_IO_START + 0x1000)
+#define PCI_IO_END      (Au1500_PCI_IO_END)
+#define PCI_MEM_START   (Au1500_PCI_MEM_START)
+#define PCI_MEM_END     (Au1500_PCI_MEM_END)
+#define PCI_FIRST_DEVFN (0<<3)
+#define PCI_LAST_DEVFN  (19<<3)
+
+#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
+#define IOPORT_RESOURCE_END   0xffffffff
+#define IOMEM_RESOURCE_START  0x10000000
+#define IOMEM_RESOURCE_END    0xffffffff
+
+  /*
+   * Borrowed from the PPC arch:
+   * The following macro is used to lookup irqs in a standard table
+   * format for those PPC systems that do not already have PCI
+   * interrupts properly routed.
+   */
+  /* FIXME - double check this from asm-ppc/pci-bridge.h */
+#define PCI_IRQ_TABLE_LOOKUP                            \
+  ({ long _ctl_ = -1;                                 \
+      if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
+               _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];               \
+                      _ctl_; })
+
+
+#else /* Au1000 and Au1100 */
+
+/* don't allow any legacy ports probing */
+#define IOPORT_RESOURCE_START 0x10000000;
+#define IOPORT_RESOURCE_END   0xffffffff
+#define IOMEM_RESOURCE_START  0x10000000
+#define IOMEM_RESOURCE_END    0xffffffff
+
+#ifdef CONFIG_MIPS_PB1000
+#define PCI_IO_START      0x10000000
+#define PCI_IO_END        0x1000ffff
+#define PCI_MEM_START     0x18000000
+#define PCI_MEM_END       0x18ffffff
+#define PCI_FIRST_DEVFN   0
+#define PCI_LAST_DEVFN    1
+#else
+/* no PCI bus controller */
+#define PCI_IO_START    0
+#define PCI_IO_END      0
+#define PCI_MEM_START   0
+#define PCI_MEM_END     0 
+#define PCI_FIRST_DEVFN 0
+#define PCI_LAST_DEVFN  0
+#endif
+
+#endif
+
+/* Processor information base on prid.
+ * Copied from PowerPC.
+ */
+struct cpu_spec {
+        /* CPU is matched via (PRID & prid_mask) == prid_value */
+        unsigned int    prid_mask;
+        unsigned int    prid_value;
+
+        char            *cpu_name;
+        unsigned char   cpu_od;         /* Set Config[OD] */
+        unsigned char   cpu_bclk;       /* Enable BCLK switching */
+};
+
+extern struct cpu_spec          cpu_specs[];
+extern struct cpu_spec          *cur_cpu_spec[];
+#endif
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
new file mode 100644
index 000000000000..810f2fa33444
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1000_dma.h
@@ -0,0 +1,446 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using and allocating dma channels on the Alchemy
+ *      Au1000 mips processor.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_AU1000_DMA_H
+#define __ASM_AU1000_DMA_H
+
+#include <asm/io.h>             /* need byte IO */
+#include <linux/spinlock.h>     /* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+#define NUM_AU1000_DMA_CHANNELS 8
+
+/* DMA Channel Base Addresses */
+#define DMA_CHANNEL_BASE        0xB4002000
+#define DMA_CHANNEL_LEN         0x00000100
+
+/* DMA Channel Register Offsets */
+#define DMA_MODE_SET            0x00000000
+#define DMA_MODE_READ           DMA_MODE_SET
+#define DMA_MODE_CLEAR          0x00000004
+/* DMA Mode register bits follow */
+#define DMA_DAH_MASK            (0x0f << 20)
+#define DMA_DID_BIT             16
+#define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
+#define DMA_DS                  (1<<15)
+#define DMA_BE                  (1<<13)
+#define DMA_DR                  (1<<12)
+#define DMA_TS8                 (1<<11)
+#define DMA_DW_BIT              9
+#define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
+#define DMA_DW8                 (0 << DMA_DW_BIT)
+#define DMA_DW16                (1 << DMA_DW_BIT)
+#define DMA_DW32                (2 << DMA_DW_BIT)
+#define DMA_NC                  (1<<8)
+#define DMA_IE                  (1<<7)
+#define DMA_HALT                (1<<6)
+#define DMA_GO                  (1<<5)
+#define DMA_AB                  (1<<4)
+#define DMA_D1                  (1<<3)
+#define DMA_BE1                 (1<<2)
+#define DMA_D0                  (1<<1)
+#define DMA_BE0                 (1<<0)
+
+#define DMA_PERIPHERAL_ADDR       0x00000008
+#define DMA_BUFFER0_START         0x0000000C
+#define DMA_BUFFER1_START         0x00000014
+#define DMA_BUFFER0_COUNT         0x00000010
+#define DMA_BUFFER1_COUNT         0x00000018
+#define DMA_BAH_BIT 16
+#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
+#define DMA_COUNT_BIT 0
+#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
+
+/* DMA Device ID's follow */
+enum {
+        DMA_ID_UART0_TX = 0,
+        DMA_ID_UART0_RX,
+        DMA_ID_GP04,
+        DMA_ID_GP05,
+        DMA_ID_AC97C_TX,
+        DMA_ID_AC97C_RX,
+        DMA_ID_UART3_TX,
+        DMA_ID_UART3_RX,
+        DMA_ID_USBDEV_EP0_RX,
+        DMA_ID_USBDEV_EP0_TX,
+        DMA_ID_USBDEV_EP2_TX,
+        DMA_ID_USBDEV_EP3_TX,
+        DMA_ID_USBDEV_EP4_RX,
+        DMA_ID_USBDEV_EP5_RX,
+        DMA_ID_I2S_TX,
+        DMA_ID_I2S_RX,
+        DMA_NUM_DEV
+};
+
+/* DMA Device ID's for 2nd bank (AU1100) follow */
+enum {
+        DMA_ID_SD0_TX = 0,
+        DMA_ID_SD0_RX,
+        DMA_ID_SD1_TX,
+        DMA_ID_SD1_RX,
+        DMA_NUM_DEV_BANK2
+};
+
+struct dma_chan {
+        int dev_id;             // this channel is allocated if >=0, free otherwise
+        unsigned int io;
+        const char *dev_str;
+        int irq;
+        void *irq_dev;
+        unsigned int fifo_addr;
+        unsigned int mode;
+};
+
+/* These are in arch/mips/au1000/common/dma.c */
+extern struct dma_chan au1000_dma_table[];
+extern int request_au1000_dma(int dev_id,
+                              const char *dev_str,
+                              irqreturn_t (*irqhandler)(int, void *,
+                                                 struct pt_regs *),
+                              unsigned long irqflags,
+                              void *irq_dev_id);
+extern void free_au1000_dma(unsigned int dmanr);
+extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
+                                int length, int *eof, void *data);
+extern void dump_au1000_dma_channel(unsigned int dmanr);
+extern spinlock_t au1000_dma_spin_lock;
+
+
+static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
+{
+        if (dmanr >= NUM_AU1000_DMA_CHANNELS
+            || au1000_dma_table[dmanr].dev_id < 0)
+                return NULL;
+        return &au1000_dma_table[dmanr];
+}
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&au1000_dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
+}
+
+/*
+ * Set the DMA buffer enable bits in the mode register.
+ */
+static __inline__ void enable_dma_buffer0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
+}
+static __inline__ void enable_dma_buffer1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
+}
+static __inline__ void enable_dma_buffers(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
+}
+
+static __inline__ void start_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+
+        au_writel(DMA_GO, chan->io + DMA_MODE_SET);
+}
+
+#define DMA_HALT_POLL 0x5000
+
+static __inline__ void halt_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        int i;
+        if (!chan)
+                return;
+
+        au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
+        // poll the halt bit
+        for (i = 0; i < DMA_HALT_POLL; i++)
+                if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
+                        break;
+        if (i == DMA_HALT_POLL)
+                printk(KERN_INFO "halt_dma: HALT poll expired!\n");
+}
+
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+
+        halt_dma(dmanr);
+
+        // now we can disable the buffers
+        au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
+}
+
+static __inline__ int dma_halted(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return 1;
+        return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
+}
+
+/* initialize a DMA channel */
+static __inline__ void init_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        u32 mode;
+        if (!chan)
+                return;
+
+        disable_dma(dmanr);
+
+        // set device FIFO address
+        au_writel(CPHYSADDR(chan->fifo_addr),
+                  chan->io + DMA_PERIPHERAL_ADDR);
+
+        mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
+        if (chan->irq)
+                mode |= DMA_IE;
+
+        au_writel(~mode, chan->io + DMA_MODE_CLEAR);
+        au_writel(mode, chan->io + DMA_MODE_SET);
+}
+
+/*
+ * set mode for a specific DMA channel
+ */
+static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        /*
+         * set_dma_mode is only allowed to change endianess, direction,
+         * transfer size, device FIFO width, and coherency settings.
+         * Make sure anything else is masked off.
+         */
+        mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode |= mode;
+}
+
+static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return 0;
+        return chan->mode;
+}
+
+static __inline__ int get_dma_active_buffer(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return -1;
+        return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
+}
+
+
+/*
+ * set the device FIFO address for a specific DMA channel - only
+ * applicable to GPO4 and GPO5. All the other devices have fixed
+ * FIFO addresses.
+ */
+static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
+                                         unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+
+        if (chan->mode & DMA_DS)        /* second bank of device ids */
+                return;
+
+        if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
+                return;
+
+        au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
+}
+
+/*
+ * Clear the DMA buffer done bits in the mode register.
+ */
+static __inline__ void clear_dma_done0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
+}
+static __inline__ void clear_dma_done1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
+}
+
+/*
+ * This does nothing - not applicable to Au1000 DMA.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+/*
+ * Set Buffer 0 transfer address for specific DMA channel.
+ */
+static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(a, chan->io + DMA_BUFFER0_START);
+}
+
+/*
+ * Set Buffer 1 transfer address for specific DMA channel.
+ */
+static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        au_writel(a, chan->io + DMA_BUFFER1_START);
+}
+
+
+/*
+ * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
+ */
+static __inline__ void set_dma_count0(unsigned int dmanr,
+                                      unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+}
+
+/*
+ * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
+ */
+static __inline__ void set_dma_count1(unsigned int dmanr,
+                                      unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr,
+                                     unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Returns which buffer has its done bit set in the mode register.
+ * Returns -1 if neither or both done bits set.
+ */
+static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return 0;
+
+    return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
+}
+
+
+/*
+ * Returns the DMA channel's Buffer Done IRQ number.
+ */
+static __inline__ int get_dma_done_irq(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return -1;
+
+        return chan->irq;
+}
+
+/*
+ * Get DMA residue count. Returns the number of _bytes_ left to transfer.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        int curBufCntReg, count;
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        if (!chan)
+                return 0;
+
+        curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
+            DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
+
+        count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
+
+        if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
+                count <<= 1;
+        else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
+                count <<= 2;
+
+        return count;
+}
+
+#endif /* __ASM_AU1000_DMA_H */
+
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
new file mode 100644
index 000000000000..298f92012e8e
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1000_gpio.h
@@ -0,0 +1,56 @@
+/*
+ * FILE NAME au1000_gpio.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      API to Alchemy Au1000 GPIO device.
+ *
+ *  Author: MontaVista Software, Inc.  <source@mvista.com>
+ *          Steve Longerbeam <stevel@mvista.com>
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AU1000_GPIO_H
+#define __AU1000_GPIO_H
+
+#include <linux/ioctl.h>
+
+#define AU1000GPIO_IOC_MAGIC 'A'
+
+#define AU1000GPIO_IN           _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
+#define AU1000GPIO_SET          _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
+#define AU1000GPIO_CLEAR        _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
+#define AU1000GPIO_OUT          _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
+#define AU1000GPIO_TRISTATE     _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
+#define AU1000GPIO_AVAIL_MASK   _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
+
+#ifdef __KERNEL__
+extern u32 get_au1000_avail_gpio_mask(void);
+extern int au1000gpio_tristate(u32 data);
+extern int au1000gpio_in(u32 *data);
+extern int au1000gpio_set(u32 data);
+extern int au1000gpio_clear(u32 data);
+extern int au1000gpio_out(u32 data);
+#endif
+
+#endif
diff --git a/include/asm-mips/mach-au1x00/au1000_usbdev.h b/include/asm-mips/mach-au1x00/au1000_usbdev.h
new file mode 100644
index 000000000000..05bc74bed0b1
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1000_usbdev.h
@@ -0,0 +1,73 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Au1000 USB Device-Side Driver
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              stevel@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define USBDEV_REV 0x0110 // BCD
+#define USBDEV_EP0_MAX_PACKET_SIZE 64
+
+typedef enum {
+        ATTACHED = 0,
+        POWERED,
+        DEFAULT,
+        ADDRESS,
+        CONFIGURED
+} usbdev_state_t;
+
+typedef enum {
+        CB_NEW_STATE = 0,
+        CB_PKT_COMPLETE
+} usbdev_cb_type_t;
+
+
+typedef struct usbdev_pkt {
+        int                ep_addr;    // ep addr this packet routed to
+        int                size;       // size of payload in bytes
+        unsigned           status;     // packet status
+        struct usbdev_pkt* next;       // function layer can't touch this
+        u8                 payload[0]; // the payload
+} usbdev_pkt_t;
+
+#define PKT_STATUS_ACK  (1<<0)
+#define PKT_STATUS_NAK  (1<<1)
+#define PKT_STATUS_SU   (1<<2)
+
+extern int usbdev_init(struct usb_device_descriptor* dev_desc,
+                       struct usb_config_descriptor* config_desc,
+                       struct usb_interface_descriptor* if_desc,
+                       struct usb_endpoint_descriptor* ep_desc,
+                       struct usb_string_descriptor* str_desc[],
+                       void (*cb)(usbdev_cb_type_t, unsigned long, void *),
+                       void* cb_data);
+
+extern void usbdev_exit(void);
+
+extern int usbdev_alloc_packet  (int ep_addr, int data_size,
+                                 usbdev_pkt_t** pkt);
+extern int usbdev_send_packet   (int ep_addr, usbdev_pkt_t* pkt);
+extern int usbdev_receive_packet(int ep_addr, usbdev_pkt_t** pkt);
+extern int usbdev_get_byte_count(int ep_addr);
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
new file mode 100644
index 000000000000..9e7d1ba21b55
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -0,0 +1,205 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using the MMC/SD controllers on the
+ *      Alchemy Au1100 mips processor.
+ *
+ * Copyright (c) 2003 Embedded Edge, LLC.
+ * Author: Embedded Edge, LLC.
+ *              dan@embeddededge.com or tim@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+/*
+ * AU1100 MMC/SD definitions.
+ *
+ * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
+ *    June, 2003
+ */
+
+#ifndef __ASM_AU1100_MMC_H
+#define __ASM_AU1100_MMC_H
+
+
+#define NUM_AU1100_MMC_CONTROLLERS      2
+
+
+#define AU1100_SD_IRQ   2
+
+
+#define SD0_BASE        0xB0600000
+#define SD1_BASE        0xB0680000
+
+
+/*
+ *  Register offsets.
+ */
+#define SD_TXPORT       (0x0000)
+#define SD_RXPORT       (0x0004)
+#define SD_CONFIG       (0x0008)
+#define SD_ENABLE       (0x000C)
+#define SD_CONFIG2      (0x0010)
+#define SD_BLKSIZE      (0x0014)
+#define SD_STATUS       (0x0018)
+#define SD_DEBUG        (0x001C)
+#define SD_CMD          (0x0020)
+#define SD_CMDARG       (0x0024)
+#define SD_RESP3        (0x0028)
+#define SD_RESP2        (0x002C)
+#define SD_RESP1        (0x0030)
+#define SD_RESP0        (0x0034)
+#define SD_TIMEOUT      (0x0038)
+
+
+/*
+ *  SD_TXPORT bit definitions.
+ */
+#define SD_TXPORT_TXD   (0x000000ff)
+
+
+/*
+ *  SD_RXPORT bit definitions.
+ */
+#define SD_RXPORT_RXD   (0x000000ff)
+
+
+/*
+ *  SD_CONFIG bit definitions.
+ */
+#define SD_CONFIG_DIV   (0x000001ff)
+#define SD_CONFIG_DE    (0x00000200)
+#define SD_CONFIG_NE    (0x00000400)
+#define SD_CONFIG_TU    (0x00000800)
+#define SD_CONFIG_TO    (0x00001000)
+#define SD_CONFIG_RU    (0x00002000)
+#define SD_CONFIG_RO    (0x00004000)
+#define SD_CONFIG_I     (0x00008000)
+#define SD_CONFIG_CR    (0x00010000)
+#define SD_CONFIG_RAT   (0x00020000)
+#define SD_CONFIG_DD    (0x00040000)
+#define SD_CONFIG_DT    (0x00080000)
+#define SD_CONFIG_SC    (0x00100000)
+#define SD_CONFIG_RC    (0x00200000)
+#define SD_CONFIG_WC    (0x00400000)
+#define SD_CONFIG_xxx   (0x00800000)
+#define SD_CONFIG_TH    (0x01000000)
+#define SD_CONFIG_TE    (0x02000000)
+#define SD_CONFIG_TA    (0x04000000)
+#define SD_CONFIG_RH    (0x08000000)
+#define SD_CONFIG_RA    (0x10000000)
+#define SD_CONFIG_RF    (0x20000000)
+#define SD_CONFIG_CD    (0x40000000)
+#define SD_CONFIG_SI    (0x80000000)
+
+
+/*
+ *  SD_ENABLE bit definitions.
+ */
+#define SD_ENABLE_CE    (0x00000001)
+#define SD_ENABLE_R     (0x00000002)
+
+
+/*
+ *  SD_CONFIG2 bit definitions.
+ */
+#define SD_CONFIG2_EN   (0x00000001)
+#define SD_CONFIG2_FF   (0x00000002)
+#define SD_CONFIG2_xx1  (0x00000004)
+#define SD_CONFIG2_DF   (0x00000008)
+#define SD_CONFIG2_DC   (0x00000010)
+#define SD_CONFIG2_xx2  (0x000000e0)
+#define SD_CONFIG2_WB   (0x00000100)
+#define SD_CONFIG2_RW   (0x00000200)
+
+
+/*
+ *  SD_BLKSIZE bit definitions.
+ */
+#define SD_BLKSIZE_BS   (0x000007ff)
+#define SD_BLKSIZE_BS_SHIFT      (0)
+#define SD_BLKSIZE_BC   (0x01ff0000)
+#define SD_BLKSIZE_BC_SHIFT     (16)
+
+
+/*
+ *  SD_STATUS bit definitions.
+ */
+#define SD_STATUS_DCRCW (0x00000007)
+#define SD_STATUS_xx1   (0x00000008)
+#define SD_STATUS_CB    (0x00000010)
+#define SD_STATUS_DB    (0x00000020)
+#define SD_STATUS_CF    (0x00000040)
+#define SD_STATUS_D3    (0x00000080)
+#define SD_STATUS_xx2   (0x00000300)
+#define SD_STATUS_NE    (0x00000400)
+#define SD_STATUS_TU    (0x00000800)
+#define SD_STATUS_TO    (0x00001000)
+#define SD_STATUS_RU    (0x00002000)
+#define SD_STATUS_RO    (0x00004000)
+#define SD_STATUS_I     (0x00008000)
+#define SD_STATUS_CR    (0x00010000)
+#define SD_STATUS_RAT   (0x00020000)
+#define SD_STATUS_DD    (0x00040000)
+#define SD_STATUS_DT    (0x00080000)
+#define SD_STATUS_SC    (0x00100000)
+#define SD_STATUS_RC    (0x00200000)
+#define SD_STATUS_WC    (0x00400000)
+#define SD_STATUS_xx3   (0x00800000)
+#define SD_STATUS_TH    (0x01000000)
+#define SD_STATUS_TE    (0x02000000)
+#define SD_STATUS_TA    (0x04000000)
+#define SD_STATUS_RH    (0x08000000)
+#define SD_STATUS_RA    (0x10000000)
+#define SD_STATUS_RF    (0x20000000)
+#define SD_STATUS_CD    (0x40000000)
+#define SD_STATUS_SI    (0x80000000)
+
+
+/*
+ *  SD_CMD bit definitions.
+ */
+#define SD_CMD_GO       (0x00000001)
+#define SD_CMD_RY       (0x00000002)
+#define SD_CMD_xx1      (0x0000000c)
+#define SD_CMD_CT_MASK  (0x000000f0)
+#define SD_CMD_CT_0     (0x00000000)
+#define SD_CMD_CT_1     (0x00000010)
+#define SD_CMD_CT_2     (0x00000020)
+#define SD_CMD_CT_3     (0x00000030)
+#define SD_CMD_CT_4     (0x00000040)
+#define SD_CMD_CT_5     (0x00000050)
+#define SD_CMD_CT_6     (0x00000060)
+#define SD_CMD_CT_7     (0x00000070)
+#define SD_CMD_CI       (0x0000ff00)
+#define SD_CMD_CI_SHIFT         (8)
+#define SD_CMD_RT_MASK  (0x00ff0000)
+#define SD_CMD_RT_0     (0x00000000)
+#define SD_CMD_RT_1     (0x00010000)
+#define SD_CMD_RT_2     (0x00020000)
+#define SD_CMD_RT_3     (0x00030000)
+#define SD_CMD_RT_4     (0x00040000)
+#define SD_CMD_RT_5     (0x00050000)
+#define SD_CMD_RT_6     (0x00060000)
+#define SD_CMD_RT_1B    (0x00810000)
+
+
+#endif /* __ASM_AU1100_MMC_H */
+
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
new file mode 100644
index 000000000000..d5eb88cd7d51
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -0,0 +1,299 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1550 Descriptor
+ *      Based DMA Controller.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
+ * seen in the AU1550 part.
+ */
+#ifndef _AU1000_DBDMA_H_
+#define _AU1000_DBDMA_H_
+
+#include <linux/config.h>
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/* The DMA base addresses.
+ * The Channels are every 256 bytes (0x0100) from the channel 0 base.
+ * Interrupt status/enable is bits 15:0 for channels 15 to zero.
+ */
+#define DDMA_GLOBAL_BASE        0xb4003000
+#define DDMA_CHANNEL_BASE       0xb4002000
+
+typedef struct dbdma_global {
+        u32     ddma_config;
+        u32     ddma_intstat;
+        u32     ddma_throttle;
+        u32     ddma_inten;
+} dbdma_global_t;
+
+/* General Configuration.
+*/
+#define DDMA_CONFIG_AF          (1 << 2)
+#define DDMA_CONFIG_AH          (1 << 1)
+#define DDMA_CONFIG_AL          (1 << 0)
+
+#define DDMA_THROTTLE_EN        (1 << 31)
+
+/* The structure of a DMA Channel.
+*/
+typedef struct au1xxx_dma_channel {
+        u32     ddma_cfg;       /* See below */
+        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
+        u32     ddma_statptr;   /* word aligned pointer to status word */
+        u32     ddma_dbell;     /* A write activates channel operation */
+        u32     ddma_irq;       /* If bit 0 set, interrupt pending */
+        u32     ddma_stat;      /* See below */
+        u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
+        /* Remainder, up to the 256 byte boundary, is reserved.
+        */
+} au1x_dma_chan_t;
+
+#define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
+#define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
+#define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
+#define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
+#define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
+#define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
+#define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
+#define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
+#define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
+#define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
+
+/* Always set when descriptor processing done, regardless of
+ * interrupt enable state.  Reflected in global intstat, don't
+ * clear this until global intstat is read/used.
+ */
+#define DDMA_IRQ_IN     (1 << 0)
+
+#define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
+#define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
+#define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
+
+/* "Standard" DDMA Descriptor.
+ * Must be 32-byte aligned.
+ */
+typedef struct au1xxx_ddma_desc {
+        u32     dscr_cmd0;              /* See below */
+        u32     dscr_cmd1;              /* See below */
+        u32     dscr_source0;           /* source phys address */
+        u32     dscr_source1;           /* See below */
+        u32     dscr_dest0;             /* Destination address */
+        u32     dscr_dest1;             /* See below */
+        u32     dscr_stat;              /* completion status */
+        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+} au1x_ddma_desc_t;
+
+#define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
+#define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
+#define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
+#define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
+#define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
+#define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
+#define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
+#define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
+#define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
+#define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
+#define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
+#define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
+#define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
+#define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
+#define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
+
+/* Command 0 device IDs.
+*/
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART3_TX      2
+#define DSCR_CMD0_UART3_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_DMA_REQ2      6
+#define DSCR_CMD0_DMA_REQ3      7
+#define DSCR_CMD0_USBDEV_RX0    8
+#define DSCR_CMD0_USBDEV_TX0    9
+#define DSCR_CMD0_USBDEV_TX1    10
+#define DSCR_CMD0_USBDEV_TX2    11
+#define DSCR_CMD0_USBDEV_RX3    12
+#define DSCR_CMD0_USBDEV_RX4    13
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_PSC2_TX       18
+#define DSCR_CMD0_PSC2_RX       19
+#define DSCR_CMD0_PSC3_TX       20
+#define DSCR_CMD0_PSC3_RX       21
+#define DSCR_CMD0_PCI_WRITE     22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_MAC0_RX       24
+#define DSCR_CMD0_MAC0_TX       25
+#define DSCR_CMD0_MAC1_RX       26
+#define DSCR_CMD0_MAC1_TX       27
+#define DSCR_CMD0_THROTTLE      30
+#define DSCR_CMD0_ALWAYS        31
+#define DSCR_NDEV_IDS           32
+
+#define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
+#define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
+
+/* Source/Destination transfer width.
+*/
+#define DSCR_CMD0_BYTE          0
+#define DSCR_CMD0_HALFWORD      1
+#define DSCR_CMD0_WORD          2
+
+#define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
+#define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
+
+/* DDMA Descriptor Type.
+*/
+#define DSCR_CMD0_STANDARD      0
+#define DSCR_CMD0_LITERAL       1
+#define DSCR_CMD0_CMP_BRANCH    2
+
+#define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
+
+/* Status Instruction.
+*/
+#define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
+#define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
+#define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
+#define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
+
+#define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
+
+/* Descriptor Command 1
+*/
+#define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
+#define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
+#define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
+#define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
+
+/* Flag description.
+*/
+#define DSCR_CMD1_FL_MEM_STRIDE0        0
+#define DSCR_CMD1_FL_MEM_STRIDE1        1
+#define DSCR_CMD1_FL_MEM_STRIDE2        2
+
+#define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
+
+/* Source1, 1-dimensional stride.
+*/
+#define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
+#define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
+#define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
+#define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
+#define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
+#define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
+
+/* Dest1, 1-dimensional stride.
+*/
+#define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
+#define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
+#define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
+#define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
+#define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
+#define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
+
+#define DSCR_xTS_SIZE1          0
+#define DSCR_xTS_SIZE2          1
+#define DSCR_xTS_SIZE4          2
+#define DSCR_xTS_SIZE8          3
+#define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
+#define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
+
+#define DSCR_xAM_INCREMENT      0
+#define DSCR_xAM_DECREMENT      1
+#define DSCR_xAM_STATIC         2
+#define DSCR_xAM_BURST          3
+#define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
+#define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
+
+/* The next descriptor pointer.
+*/
+#define DSCR_NXTPTR_MASK        (0x07ffffff)
+#define DSCR_NXTPTR(x)          ((x) >> 5)
+#define DSCR_GET_NXTPTR(x)      ((x) << 5)
+#define DSCR_NXTPTR_MS          (1 << 27)
+
+/* The number of DBDMA channels.
+*/
+#define NUM_DBDMA_CHANS 16
+
+/* External functions for drivers to use.
+*/
+/* Use this to allocate a dbdma channel.  The device ids are one of the
+ * DSCR_CMD0 devices IDs, which is usually redefined to a more
+ * meaningful name.  The 'callback' is called during dma completion
+ * interrupt.
+ */
+u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
+       void (*callback)(int, void *, struct pt_regs *), void *callparam);
+
+#define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
+
+/* ACK!  These should be in a board specific description file.
+*/
+#ifdef CONFIG_MIPS_PB1550
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#endif
+#ifdef CONFIG_MIPS_DB1550
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#endif
+
+
+/* Set the device width of a in/out fifo.
+*/
+u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
+
+/* Allocate a ring of descriptors for dbdma.
+*/
+u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
+
+/* Put buffers on source/destination descriptors.
+*/
+u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
+u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
+
+/* Get a buffer from the destination descriptor.
+*/
+u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
+
+void au1xxx_dbdma_stop(u32 chanid);
+void au1xxx_dbdma_start(u32 chanid);
+void au1xxx_dbdma_reset(u32 chanid);
+u32 au1xxx_get_dma_residue(u32 chanid);
+
+void au1xxx_dbdma_chan_free(u32 chanid);
+void au1xxx_dbdma_dump(u32 chanid);
+
+#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
new file mode 100644
index 000000000000..283519dfdec4
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -0,0 +1,522 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Specifics for the Au1xxx Programmable Serial Controllers, first
+ * seen in the AU1550 part.
+ */
+#ifndef _AU1000_PSC_H_
+#define _AU1000_PSC_H_
+
+/* The PSC base addresses.  */
+#ifdef CONFIG_SOC_AU1550
+#define PSC0_BASE_ADDR          0xb1a00000
+#define PSC1_BASE_ADDR          0xb1b00000
+#define PSC2_BASE_ADDR          0xb0a00000
+#define PSC3_BASE_ADDR          0xb0d00000
+#endif
+
+/* The PSC select and control registers are common to
+ * all protocols.
+ */
+#define PSC_SEL_OFFSET          0x00000000
+#define PSC_CTRL_OFFSET         0x00000004
+
+#define PSC_SEL_CLK_MASK        (3 << 4)
+#define PSC_SEL_CLK_INTCLK      (0 << 4)
+#define PSC_SEL_CLK_EXTCLK      (1 << 4)
+#define PSC_SEL_CLK_SERCLK      (2 << 4)
+
+#define PSC_SEL_PS_MASK         0x00000007
+#define PSC_SEL_PS_DISABLED     (0)
+#define PSC_SEL_PS_SPIMODE      (2)
+#define PSC_SEL_PS_I2SMODE      (3)
+#define PSC_SEL_PS_AC97MODE     (4)
+#define PSC_SEL_PS_SMBUSMODE    (5)
+
+#define PSC_CTRL_DISABLE        (0)
+#define PSC_CTRL_SUSPEND        (2)
+#define PSC_CTRL_ENABLE         (3)
+
+/* AC97 Registers.
+*/
+#define PSC_AC97CFG_OFFSET      0x00000008
+#define PSC_AC97MSK_OFFSET      0x0000000c
+#define PSC_AC97PCR_OFFSET      0x00000010
+#define PSC_AC97STAT_OFFSET     0x00000014
+#define PSC_AC97EVNT_OFFSET     0x00000018
+#define PSC_AC97TXRX_OFFSET     0x0000001c
+#define PSC_AC97CDC_OFFSET      0x00000020
+#define PSC_AC97RST_OFFSET      0x00000024
+#define PSC_AC97GPO_OFFSET      0x00000028
+#define PSC_AC97GPI_OFFSET      0x0000002c
+
+#define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
+#define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
+#define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
+#define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
+#define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
+#define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
+#define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
+#define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
+#define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
+#define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
+#define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
+#define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
+
+/* AC97 Config Register.
+*/
+#define PSC_AC97CFG_RT_MASK     (3 << 30)
+#define PSC_AC97CFG_RT_FIFO1    (0 << 30)
+#define PSC_AC97CFG_RT_FIFO2    (1 << 30)
+#define PSC_AC97CFG_RT_FIFO4    (2 << 30)
+#define PSC_AC97CFG_RT_FIFO8    (3 << 30)
+
+#define PSC_AC97CFG_TT_MASK     (3 << 28)
+#define PSC_AC97CFG_TT_FIFO1    (0 << 28)
+#define PSC_AC97CFG_TT_FIFO2    (1 << 28)
+#define PSC_AC97CFG_TT_FIFO4    (2 << 28)
+#define PSC_AC97CFG_TT_FIFO8    (3 << 28)
+
+#define PSC_AC97CFG_DD_DISABLE  (1 << 27)
+#define PSC_AC97CFG_DE_ENABLE   (1 << 26)
+#define PSC_AC97CFG_SE_ENABLE   (1 << 25)
+
+#define PSC_AC97CFG_LEN_MASK    (0xf << 21)
+#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
+#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
+#define PSC_AC97CFG_GE_ENABLE   (1)
+
+/* Enable slots 3-12.
+*/
+#define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
+#define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
+
+/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
+ * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
+ * arithmetic in the macro.
+ */
+#define PSC_AC97CFG_SET_LEN(x)  (((((x)-2)/2) & 0xf) << 21)
+#define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
+
+/* AC97 Mask Register.
+*/
+#define PSC_AC97MSK_GR          (1 << 25)
+#define PSC_AC97MSK_CD          (1 << 24)
+#define PSC_AC97MSK_RR          (1 << 13)
+#define PSC_AC97MSK_RO          (1 << 12)
+#define PSC_AC97MSK_RU          (1 << 11)
+#define PSC_AC97MSK_TR          (1 << 10)
+#define PSC_AC97MSK_TO          (1 << 9)
+#define PSC_AC97MSK_TU          (1 << 8)
+#define PSC_AC97MSK_RD          (1 << 5)
+#define PSC_AC97MSK_TD          (1 << 4)
+#define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
+                                 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
+                                 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
+                                 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
+                                 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
+
+/* AC97 Protocol Control Register.
+*/
+#define PSC_AC97PCR_RC          (1 << 6)
+#define PSC_AC97PCR_RP          (1 << 5)
+#define PSC_AC97PCR_RS          (1 << 4)
+#define PSC_AC97PCR_TC          (1 << 2)
+#define PSC_AC97PCR_TP          (1 << 1)
+#define PSC_AC97PCR_TS          (1 << 0)
+
+/* AC97 Status register (read only).
+*/
+#define PSC_AC97STAT_CB         (1 << 26)
+#define PSC_AC97STAT_CP         (1 << 25)
+#define PSC_AC97STAT_CR         (1 << 24)
+#define PSC_AC97STAT_RF         (1 << 13)
+#define PSC_AC97STAT_RE         (1 << 12)
+#define PSC_AC97STAT_RR         (1 << 11)
+#define PSC_AC97STAT_TF         (1 << 10)
+#define PSC_AC97STAT_TE         (1 << 9)
+#define PSC_AC97STAT_TR         (1 << 8)
+#define PSC_AC97STAT_RB         (1 << 5)
+#define PSC_AC97STAT_TB         (1 << 4)
+#define PSC_AC97STAT_DI         (1 << 2)
+#define PSC_AC97STAT_DR         (1 << 1)
+#define PSC_AC97STAT_SR         (1 << 0)
+
+/* AC97 Event Register.
+*/
+#define PSC_AC97EVNT_GR         (1 << 25)
+#define PSC_AC97EVNT_CD         (1 << 24)
+#define PSC_AC97EVNT_RR         (1 << 13)
+#define PSC_AC97EVNT_RO         (1 << 12)
+#define PSC_AC97EVNT_RU         (1 << 11)
+#define PSC_AC97EVNT_TR         (1 << 10)
+#define PSC_AC97EVNT_TO         (1 << 9)
+#define PSC_AC97EVNT_TU         (1 << 8)
+#define PSC_AC97EVNT_RD         (1 << 5)
+#define PSC_AC97EVNT_TD         (1 << 4)
+
+/* CODEC Command Register.
+*/
+#define PSC_AC97CDC_RD          (1 << 25)
+#define PSC_AC97CDC_ID_MASK     (3 << 23)
+#define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
+#define PSC_AC97CDC_ID(x)       (((x) & 0x3) << 23)
+#define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
+
+/* AC97 Reset Control Register.
+*/
+#define PSC_AC97RST_RST         (1 << 1)
+#define PSC_AC97RST_SNC         (1 << 0)
+
+
+/* PSC in I2S Mode.
+*/
+typedef struct  psc_i2s {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_i2scfg;
+        u32     psc_i2smsk;
+        u32     psc_i2spcr;
+        u32     psc_i2sstat;
+        u32     psc_i2sevent;
+        u32     psc_i2stxrx;
+        u32     psc_i2sudf;
+} psc_i2s_t;
+
+/* I2S Config Register.
+*/
+#define PSC_I2SCFG_RT_MASK      (3 << 30)
+#define PSC_I2SCFG_RT_FIFO1     (0 << 30)
+#define PSC_I2SCFG_RT_FIFO2     (1 << 30)
+#define PSC_I2SCFG_RT_FIFO4     (2 << 30)
+#define PSC_I2SCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_I2SCFG_TT_MASK      (3 << 28)
+#define PSC_I2SCFG_TT_FIFO1     (0 << 28)
+#define PSC_I2SCFG_TT_FIFO2     (1 << 28)
+#define PSC_I2SCFG_TT_FIFO4     (2 << 28)
+#define PSC_I2SCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_I2SCFG_DD_DISABLE   (1 << 27)
+#define PSC_I2SCFG_DE_ENABLE    (1 << 26)
+#define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
+#define PSC_I2SCFG_WI           (1 << 15)
+
+#define PSC_I2SCFG_DIV_MASK     (3 << 13)
+#define PSC_I2SCFG_DIV2         (0 << 13)
+#define PSC_I2SCFG_DIV4         (1 << 13)
+#define PSC_I2SCFG_DIV8         (2 << 13)
+#define PSC_I2SCFG_DIV16        (3 << 13)
+
+#define PSC_I2SCFG_BI           (1 << 12)
+#define PSC_I2SCFG_BUF          (1 << 11)
+#define PSC_I2SCFG_MLJ          (1 << 10)
+#define PSC_I2SCFG_XM           (1 << 9)
+
+/* The word length equation is simply LEN+1.
+ */
+#define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
+#define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
+
+#define PSC_I2SCFG_LB           (1 << 2)
+#define PSC_I2SCFG_MLF          (1 << 1)
+#define PSC_I2SCFG_MS           (1 << 0)
+
+/* I2S Mask Register.
+*/
+#define PSC_I2SMSK_RR           (1 << 13)
+#define PSC_I2SMSK_RO           (1 << 12)
+#define PSC_I2SMSK_RU           (1 << 11)
+#define PSC_I2SMSK_TR           (1 << 10)
+#define PSC_I2SMSK_TO           (1 << 9)
+#define PSC_I2SMSK_TU           (1 << 8)
+#define PSC_I2SMSK_RD           (1 << 5)
+#define PSC_I2SMSK_TD           (1 << 4)
+#define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
+                                 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
+                                 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
+                                 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
+
+/* I2S Protocol Control Register.
+*/
+#define PSC_I2SPCR_RC           (1 << 6)
+#define PSC_I2SPCR_RP           (1 << 5)
+#define PSC_I2SPCR_RS           (1 << 4)
+#define PSC_I2SPCR_TC           (1 << 2)
+#define PSC_I2SPCR_TP           (1 << 1)
+#define PSC_I2SPCR_TS           (1 << 0)
+
+/* I2S Status register (read only).
+*/
+#define PSC_I2SSTAT_RF          (1 << 13)
+#define PSC_I2SSTAT_RE          (1 << 12)
+#define PSC_I2SSTAT_RR          (1 << 11)
+#define PSC_I2SSTAT_TF          (1 << 10)
+#define PSC_I2SSTAT_TE          (1 << 9)
+#define PSC_I2SSTAT_TR          (1 << 8)
+#define PSC_I2SSTAT_RB          (1 << 5)
+#define PSC_I2SSTAT_TB          (1 << 4)
+#define PSC_I2SSTAT_DI          (1 << 2)
+#define PSC_I2SSTAT_DR          (1 << 1)
+#define PSC_I2SSTAT_SR          (1 << 0)
+
+/* I2S Event Register.
+*/
+#define PSC_I2SEVNT_RR          (1 << 13)
+#define PSC_I2SEVNT_RO          (1 << 12)
+#define PSC_I2SEVNT_RU          (1 << 11)
+#define PSC_I2SEVNT_TR          (1 << 10)
+#define PSC_I2SEVNT_TO          (1 << 9)
+#define PSC_I2SEVNT_TU          (1 << 8)
+#define PSC_I2SEVNT_RD          (1 << 5)
+#define PSC_I2SEVNT_TD          (1 << 4)
+
+/* PSC in SPI Mode.
+*/
+typedef struct  psc_spi {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_spicfg;
+        u32     psc_spimsk;
+        u32     psc_spipcr;
+        u32     psc_spistat;
+        u32     psc_spievent;
+        u32     psc_spitxrx;
+} psc_spi_t;
+
+/* SPI Config Register.
+*/
+#define PSC_SPICFG_RT_MASK      (3 << 30)
+#define PSC_SPICFG_RT_FIFO1     (0 << 30)
+#define PSC_SPICFG_RT_FIFO2     (1 << 30)
+#define PSC_SPICFG_RT_FIFO4     (2 << 30)
+#define PSC_SPICFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SPICFG_TT_MASK      (3 << 28)
+#define PSC_SPICFG_TT_FIFO1     (0 << 28)
+#define PSC_SPICFG_TT_FIFO2     (1 << 28)
+#define PSC_SPICFG_TT_FIFO4     (2 << 28)
+#define PSC_SPICFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SPICFG_DD_DISABLE   (1 << 27)
+#define PSC_SPICFG_DE_ENABLE    (1 << 26)
+#define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
+#define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
+
+#define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SPICFG_DIV2         0
+#define PSC_SPICFG_DIV4         1
+#define PSC_SPICFG_DIV8         2
+#define PSC_SPICFG_DIV16        3
+
+#define PSC_SPICFG_BI           (1 << 12)
+#define PSC_SPICFG_PSE          (1 << 11)
+#define PSC_SPICFG_CGE          (1 << 10)
+#define PSC_SPICFG_CDE          (1 << 9)
+
+#define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
+#define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
+
+#define PSC_SPICFG_LB           (1 << 3)
+#define PSC_SPICFG_MLF          (1 << 1)
+#define PSC_SPICFG_MO           (1 << 0)
+
+/* SPI Mask Register.
+*/
+#define PSC_SPIMSK_MM           (1 << 16)
+#define PSC_SPIMSK_RR           (1 << 13)
+#define PSC_SPIMSK_RO           (1 << 12)
+#define PSC_SPIMSK_RU           (1 << 11)
+#define PSC_SPIMSK_TR           (1 << 10)
+#define PSC_SPIMSK_TO           (1 << 9)
+#define PSC_SPIMSK_TU           (1 << 8)
+#define PSC_SPIMSK_SD           (1 << 5)
+#define PSC_SPIMSK_MD           (1 << 4)
+#define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
+                                 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
+                                 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
+                                 PSC_SPIMSK_MD)
+
+/* SPI Protocol Control Register.
+*/
+#define PSC_SPIPCR_RC           (1 << 6)
+#define PSC_SPIPCR_SP           (1 << 5)
+#define PSC_SPIPCR_SS           (1 << 4)
+#define PSC_SPIPCR_TC           (1 << 2)
+#define PSC_SPIPCR_MS           (1 << 0)
+
+/* SPI Status register (read only).
+*/
+#define PSC_SPISTAT_RF          (1 << 13)
+#define PSC_SPISTAT_RE          (1 << 12)
+#define PSC_SPISTAT_RR          (1 << 11)
+#define PSC_SPISTAT_TF          (1 << 10)
+#define PSC_SPISTAT_TE          (1 << 9)
+#define PSC_SPISTAT_TR          (1 << 8)
+#define PSC_SPISTAT_SB          (1 << 5)
+#define PSC_SPISTAT_MB          (1 << 4)
+#define PSC_SPISTAT_DI          (1 << 2)
+#define PSC_SPISTAT_DR          (1 << 1)
+#define PSC_SPISTAT_SR          (1 << 0)
+
+/* SPI Event Register.
+*/
+#define PSC_SPIEVNT_MM          (1 << 16)
+#define PSC_SPIEVNT_RR          (1 << 13)
+#define PSC_SPIEVNT_RO          (1 << 12)
+#define PSC_SPIEVNT_RU          (1 << 11)
+#define PSC_SPIEVNT_TR          (1 << 10)
+#define PSC_SPIEVNT_TO          (1 << 9)
+#define PSC_SPIEVNT_TU          (1 << 8)
+#define PSC_SPIEVNT_SD          (1 << 5)
+#define PSC_SPIEVNT_MD          (1 << 4)
+
+/* Transmit register control.
+*/
+#define PSC_SPITXRX_LC          (1 << 29)
+#define PSC_SPITXRX_SR          (1 << 28)
+
+/* PSC in SMBus (I2C) Mode.
+*/
+typedef struct  psc_smb {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_smbcfg;
+        u32     psc_smbmsk;
+        u32     psc_smbpcr;
+        u32     psc_smbstat;
+        u32     psc_smbevnt;
+        u32     psc_smbtxrx;
+        u32     psc_smbtmr;
+} psc_smb_t;
+
+/* SMBus Config Register.
+*/
+#define PSC_SMBCFG_RT_MASK      (3 << 30)
+#define PSC_SMBCFG_RT_FIFO1     (0 << 30)
+#define PSC_SMBCFG_RT_FIFO2     (1 << 30)
+#define PSC_SMBCFG_RT_FIFO4     (2 << 30)
+#define PSC_SMBCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SMBCFG_TT_MASK      (3 << 28)
+#define PSC_SMBCFG_TT_FIFO1     (0 << 28)
+#define PSC_SMBCFG_TT_FIFO2     (1 << 28)
+#define PSC_SMBCFG_TT_FIFO4     (2 << 28)
+#define PSC_SMBCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SMBCFG_DD_DISABLE   (1 << 27)
+#define PSC_SMBCFG_DE_ENABLE    (1 << 26)
+
+#define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SMBCFG_DIV2         0
+#define PSC_SMBCFG_DIV4         1
+#define PSC_SMBCFG_DIV8         2
+#define PSC_SMBCFG_DIV16        3
+
+#define PSC_SMBCFG_GCE          (1 << 9)
+#define PSC_SMBCFG_SFM          (1 << 8)
+
+#define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
+
+/* SMBus Mask Register.
+*/
+#define PSC_SMBMSK_DN           (1 << 30)
+#define PSC_SMBMSK_AN           (1 << 29)
+#define PSC_SMBMSK_AL           (1 << 28)
+#define PSC_SMBMSK_RR           (1 << 13)
+#define PSC_SMBMSK_RO           (1 << 12)
+#define PSC_SMBMSK_RU           (1 << 11)
+#define PSC_SMBMSK_TR           (1 << 10)
+#define PSC_SMBMSK_TO           (1 << 9)
+#define PSC_SMBMSK_TU           (1 << 8)
+#define PSC_SMBMSK_SD           (1 << 5)
+#define PSC_SMBMSK_MD           (1 << 4)
+#define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
+                                 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
+                                 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
+                                 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
+                                 PSC_SMBMSK_MD)
+
+/* SMBus Protocol Control Register.
+*/
+#define PSC_SMBPCR_DC           (1 << 2)
+#define PSC_SMBPCR_MS           (1 << 0)
+
+/* SMBus Status register (read only).
+*/
+#define PSC_SMBSTAT_BB          (1 << 28)
+#define PSC_SMBSTAT_RF          (1 << 13)
+#define PSC_SMBSTAT_RE          (1 << 12)
+#define PSC_SMBSTAT_RR          (1 << 11)
+#define PSC_SMBSTAT_TF          (1 << 10)
+#define PSC_SMBSTAT_TE          (1 << 9)
+#define PSC_SMBSTAT_TR          (1 << 8)
+#define PSC_SMBSTAT_SB          (1 << 5)
+#define PSC_SMBSTAT_MB          (1 << 4)
+#define PSC_SMBSTAT_DI          (1 << 2)
+#define PSC_SMBSTAT_DR          (1 << 1)
+#define PSC_SMBSTAT_SR          (1 << 0)
+
+/* SMBus Event Register.
+*/
+#define PSC_SMBEVNT_DN          (1 << 30)
+#define PSC_SMBEVNT_AN          (1 << 29)
+#define PSC_SMBEVNT_AL          (1 << 28)
+#define PSC_SMBEVNT_RR          (1 << 13)
+#define PSC_SMBEVNT_RO          (1 << 12)
+#define PSC_SMBEVNT_RU          (1 << 11)
+#define PSC_SMBEVNT_TR          (1 << 10)
+#define PSC_SMBEVNT_TO          (1 << 9)
+#define PSC_SMBEVNT_TU          (1 << 8)
+#define PSC_SMBEVNT_SD          (1 << 5)
+#define PSC_SMBEVNT_MD          (1 << 4)
+#define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
+                                 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
+                                 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
+                                 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
+                                 PSC_SMBEVNT_MD)
+
+/* Transmit register control.
+*/
+#define PSC_SMBTXRX_RSR         (1 << 30)
+#define PSC_SMBTXRX_STP         (1 << 29)
+#define PSC_SMBTXRX_DATAMASK    (0xff)
+
+/* SMBus protocol timers register.
+*/
+#define PSC_SMBTMR_SET_TH(x)    (((x) & 0x3) << 30)
+#define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
+#define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
+#define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
+#define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
+#define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
+#define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
+
+
+#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-au1x00/timex.h b/include/asm-mips/mach-au1x00/timex.h
new file mode 100644
index 000000000000..e3ada66cb636
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/timex.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_AU1X00_TIMEX_H
+#define __ASM_MACH_AU1X00_TIMEX_H
+
+#define CLOCK_TICK_RATE         ((HZ * 100000UL) / 2)
+
+#endif /* __ASM_MACH_AU1X00_TIMEX_H */
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
new file mode 100644
index 000000000000..4691398a414f
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -0,0 +1,205 @@
+/*
+ * AMD Alchemy DB1x00 Reference Boards
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * 
+ */
+#ifndef __ASM_DB1X00_H
+#define __ASM_DB1X00_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_MIPS_DB1550
+#define BCSR_KSEG1_ADDR 0xAF000000
+#define NAND_PHYS_ADDR  0x20000000
+#else
+#define BCSR_KSEG1_ADDR 0xAE000000
+#endif
+
+/*
+ * Overlay data structure of the Db1x00 board registers.
+ * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
+ */
+typedef volatile struct
+{
+        /*00*/  unsigned short whoami;
+        unsigned short reserved0;
+        /*04*/  unsigned short status;
+        unsigned short reserved1;
+        /*08*/  unsigned short switches;
+        unsigned short reserved2;
+        /*0C*/  unsigned short resets;
+        unsigned short reserved3;
+        /*10*/  unsigned short pcmcia;
+        unsigned short reserved4;
+        /*14*/  unsigned short specific;
+        unsigned short reserved5;
+        /*18*/  unsigned short leds;
+        unsigned short reserved6;
+        /*1C*/  unsigned short swreset;
+        unsigned short reserved7;
+
+} BCSR;
+
+
+/*
+ * Register/mask bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID                0x000F
+#define BCSR_WHOAMI_CPLD                0x00F0
+#define BCSR_WHOAMI_BOARD               0x0F00
+
+#define BCSR_STATUS_PC0VS               0x0003
+#define BCSR_STATUS_PC1VS               0x000C
+#define BCSR_STATUS_PC0FI               0x0010
+#define BCSR_STATUS_PC1FI               0x0020
+#define BCSR_STATUS_FLASHBUSY           0x0100
+#define BCSR_STATUS_ROMBUSY             0x0400
+#define BCSR_STATUS_SWAPBOOT            0x2000
+#define BCSR_STATUS_FLASHDEN            0xC000
+
+#define BCSR_SWITCHES_DIP               0x00FF
+#define BCSR_SWITCHES_DIP_1             0x0080
+#define BCSR_SWITCHES_DIP_2             0x0040
+#define BCSR_SWITCHES_DIP_3             0x0020
+#define BCSR_SWITCHES_DIP_4             0x0010
+#define BCSR_SWITCHES_DIP_5             0x0008
+#define BCSR_SWITCHES_DIP_6             0x0004
+#define BCSR_SWITCHES_DIP_7             0x0002
+#define BCSR_SWITCHES_DIP_8             0x0001
+#define BCSR_SWITCHES_ROTARY            0x0F00
+
+#define BCSR_RESETS_PHY0                0x0001
+#define BCSR_RESETS_PHY1                0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_FIR_SEL             0x2000
+#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
+#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
+#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
+#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
+#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
+
+#define BCSR_PCMCIA_PC0VPP              0x0003
+#define BCSR_PCMCIA_PC0VCC              0x000C
+#define BCSR_PCMCIA_PC0DRVEN            0x0010
+#define BCSR_PCMCIA_PC0RST              0x0080
+#define BCSR_PCMCIA_PC1VPP              0x0300
+#define BCSR_PCMCIA_PC1VCC              0x0C00
+#define BCSR_PCMCIA_PC1DRVEN            0x1000
+#define BCSR_PCMCIA_PC1RST              0x8000
+
+#define BCSR_BOARD_PCIM66EN             0x0001
+#define BCSR_BOARD_SD0_PWR              0x0040
+#define BCSR_BOARD_SD1_PWR              0x0080
+#define BCSR_BOARD_PCIM33               0x0100
+#define BCSR_BOARD_GPIO200RST           0x0400
+#define BCSR_BOARD_PCICFG               0x1000
+#define BCSR_BOARD_SD0_WP               0x4000
+#define BCSR_BOARD_SD1_WP               0x8000
+
+#define BCSR_LEDS_DECIMALS              0x0003
+#define BCSR_LEDS_LED0                  0x0100
+#define BCSR_LEDS_LED1                  0x0200
+#define BCSR_LEDS_LED2                  0x0400
+#define BCSR_LEDS_LED3                  0x0800
+
+#define BCSR_SWRESET_RESET              0x0080
+
+/* PCMCIA Db1x00 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+/* SD controller macros */
+/*
+ * Detect card.
+ */
+#define mmc_card_inserted(_n_, _res_) \
+        do { \
+                BCSR * const bcsr = (BCSR *)0xAE000000; \
+                unsigned long mmc_wp, board_specific; \
+                if ((_n_)) { \
+                        mmc_wp = BCSR_BOARD_SD1_WP; \
+                } else { \
+                        mmc_wp = BCSR_BOARD_SD0_WP; \
+                } \
+                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
+                if (!(board_specific & mmc_wp)) {/* low means card present */ \
+                        *(int *)(_res_) = 1; \
+                } else { \
+                        *(int *)(_res_) = 0; \
+                } \
+        } while (0)
+
+/*
+ * Apply power to card slot(s).
+ */
+#define mmc_power_on(_n_) \
+        do { \
+                BCSR * const bcsr = (BCSR *)0xAE000000; \
+                unsigned long mmc_pwr, mmc_wp, board_specific; \
+                if ((_n_)) { \
+                        mmc_pwr = BCSR_BOARD_SD1_PWR; \
+                        mmc_wp = BCSR_BOARD_SD1_WP; \
+                } else { \
+                        mmc_pwr = BCSR_BOARD_SD0_PWR; \
+                        mmc_wp = BCSR_BOARD_SD0_WP; \
+                } \
+                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
+                if (!(board_specific & mmc_wp)) {/* low means card present */ \
+                        board_specific |= mmc_pwr; \
+                        au_writel(board_specific, (int)(&bcsr->specific)); \
+                        au_sync(); \
+                } \
+        } while (0)
+
+
+/* NAND defines */
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                        (18 >> 2)
+#define NAND_T_PUL                      (30 >> 2)
+#define NAND_T_SU                       (30 >> 2)
+#define NAND_T_WH                       (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+
+#endif /* __ASM_DB1X00_H */
+
diff --git a/include/asm-mips/mach-ddb5074/mc146818rtc.h b/include/asm-mips/mach-ddb5074/mc146818rtc.h
new file mode 100644
index 000000000000..2eb9acb10a5a
--- /dev/null
+++ b/include/asm-mips/mach-ddb5074/mc146818rtc.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
+#define __ASM_MACH_DDB5074_MC146818RTC_H
+
+#include <asm/ddb5xxx/ddb5074.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
new file mode 100644
index 000000000000..a326f451253b
--- /dev/null
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -0,0 +1,46 @@
+/*
+ * RTC definitions for DECstation style attached Dallas DS1287 chip.
+ *
+ * Copyright (C) 1998, 2001 by Ralf Baechle
+ * Copyright (C) 1998 by Harald Koerfgen
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_RTC_DEC_H
+#define __ASM_MIPS_DEC_RTC_DEC_H
+
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+extern volatile u8 *dec_rtc_base;
+extern unsigned long dec_kn_slot_size;
+
+#define RTC_PORT(x)     CPHYSADDR(dec_rtc_base)
+#define RTC_IO_EXTENT   dec_kn_slot_size
+#define RTC_IOMAPPED    0
+#undef RTC_IRQ
+
+#define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
+
+#include <linux/mc146818rtc.h>
+#include <linux/module.h>
+#include <linux/types.h>
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        return dec_rtc_base[addr * 4];
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        dec_rtc_base[addr * 4] = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MIPS_DEC_RTC_DEC_H */
diff --git a/include/asm-mips/mach-dec/param.h b/include/asm-mips/mach-dec/param.h
new file mode 100644
index 000000000000..3e4f0e390847
--- /dev/null
+++ b/include/asm-mips/mach-dec/param.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_DEC_PARAM_H
+#define __ASM_MACH_DEC_PARAM_H
+
+/*
+ * log2(HZ), change this here if you want another HZ value. This is also
+ * used in dec_time_init.  Minimum is 1, Maximum is 15.
+ */
+#define LOG_2_HZ 7
+#define HZ (1 << LOG_2_HZ)
+
+#endif /* __ASM_MACH_DEC_PARAM_H */
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
new file mode 100644
index 000000000000..13b1443a7a65
--- /dev/null
+++ b/include/asm-mips/mach-ev64120/mach-gt64120.h
@@ -0,0 +1,61 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H
+#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H
+
+/*
+ *   GT64120 config space base address
+ */
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE    (gt64120_base)
+
+/*
+ *   PCI Bus allocation
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x10000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+#define GT_ISA_IO_BASE  PCI_IO_BASE
+
+/*
+ *   Duart I/O ports.
+ */
+#define EV64120_COM1_BASE_ADDR  (0x1d000000 + 0x20)
+#define EV64120_COM2_BASE_ADDR  (0x1d000000 + 0x00)
+
+
+/*
+ *   EV64120 interrupt controller register base.
+ */
+#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
+
+/*
+ *   EV64120 UART register base.
+ */
+#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
+#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
+#define EV64120_BASE_BAUD ( 3686400 / 16 )
+
+/*
+ * PCI interrupts will come in on either the INTA or INTD interrups lines,
+ * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
+ * boards, they all either come in on IntD or they all come in on IntA, they
+ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
+ * "requested" interrupt numbers and go through the list whenever we get an
+ * IntA/D.
+ *
+ * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
+ * INTD is 11.
+ */
+#define GT_TIMER        4
+#define GT_INTA         2
+#define GT_INTD         5
+
+#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */
diff --git a/include/asm-mips/mach-ev96100/mach-gt64120.h b/include/asm-mips/mach-ev96100/mach-gt64120.h
new file mode 100644
index 000000000000..0ef1e6c25acf
--- /dev/null
+++ b/include/asm-mips/mach-ev96100/mach-gt64120.h
@@ -0,0 +1,46 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H
+#define _ASM_GT64120_EV96100_GT64120_DEP_H
+
+/*
+ *   GT96100 config space base address
+ */
+#define GT64120_BASE    (KSEG1ADDR(0x14000000))
+
+/*
+ *   PCI Bus allocation
+ *
+ *   (Guessing ...)
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x10000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+#define GT_ISA_IO_BASE  PCI_IO_BASE
+
+/*
+ *   Duart I/O ports.
+ */
+#define EV96100_COM1_BASE_ADDR  (0xBD000000 + 0x20)
+#define EV96100_COM2_BASE_ADDR  (0xBD000000 + 0x00)
+
+
+/*
+ *   EV96100 interrupt controller register base.
+ */
+#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
+
+/*
+ *   EV96100 UART register base.
+ */
+#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
+#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
+#define EV96100_BASE_BAUD       ( 3686400 / 16 )
+
+#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 000000000000..0aecfd08e39a
--- /dev/null
+++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intensionally empty file ...  */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-generic/floppy.h b/include/asm-mips/mach-generic/floppy.h
new file mode 100644
index 000000000000..682a5858f8d7
--- /dev/null
+++ b/include/asm-mips/mach-generic/floppy.h
@@ -0,0 +1,139 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_FLOPPY_H
+#define __ASM_MACH_GENERIC_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+
+#include <asm/bootinfo.h>
+#include <asm/cachectl.h>
+#include <asm/dma.h>
+#include <asm/floppy.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+
+/*
+ * How to access the FDC's registers.
+ */
+static inline unsigned char fd_inb(unsigned int port)
+{
+        return inb_p(port);
+}
+
+static inline void fd_outb(unsigned char value, unsigned int port)
+{
+        outb_p(value, port);
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        enable_dma(FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        disable_dma(FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return request_dma(FLOPPY_DMA, "floppy");
+}
+
+static inline void fd_free_dma(void)
+{
+        free_dma(FLOPPY_DMA);
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+        clear_dma_ff(FLOPPY_DMA);
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        set_dma_mode(FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *addr)
+{
+        set_dma_addr(FLOPPY_DMA, (unsigned long) addr);
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        set_dma_count(FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return get_dma_residue(FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+        enable_irq(FLOPPY_IRQ);
+}
+
+static inline void fd_disable_irq(void)
+{
+        disable_irq(FLOPPY_IRQ);
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
+}
+
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return 0x3f0;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        unsigned long mem;
+
+        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
+
+        return mem;
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_FLOPPY_H */
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
new file mode 100644
index 000000000000..cb2edd018ad6
--- /dev/null
+++ b/include/asm-mips/mach-generic/ide.h
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994-1996  Linus Torvalds & authors
+ *
+ * Copied from i386; many of the especially older MIPS or ISA-based platforms
+ * are basically identical.  Using this file probably implies i8259 PIC
+ * support in a system but the very least interrupt numbers 0 - 15 need to
+ * be put aside for legacy devices.
+ */
+#ifndef __ASM_MACH_GENERIC_IDE_H
+#define __ASM_MACH_GENERIC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/stddef.h>
+
+#ifndef MAX_HWIFS
+# ifdef CONFIG_BLK_DEV_IDEPCI
+#define MAX_HWIFS       10
+# else
+#define MAX_HWIFS       6
+# endif
+#endif
+
+#define IDE_ARCH_OBSOLETE_DEFAULTS
+
+static __inline__ int ide_probe_legacy(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_dev *dev;
+        if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
+            (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
+                pci_dev_put(dev);
+
+                return 1;
+        }
+        return 0;
+#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+static __inline__ int ide_default_irq(unsigned long base)
+{
+        if (ide_probe_legacy())
+                switch (base) {
+                case 0x1f0:
+                        return 14;
+                case 0x170:
+                        return 15;
+                case 0x1e8:
+                        return 11;
+                case 0x168:
+                        return 10;
+                case 0x1e0:
+                        return 8;
+                case 0x160:
+                        return 12;
+                default:
+                        return 0;
+                }
+        else
+                return 0;
+}
+
+static __inline__ unsigned long ide_default_io_base(int index)
+{
+        if (ide_probe_legacy())
+                switch (index) {
+                case 0:
+                        return 0x1f0;
+                case 1:
+                        return 0x170;
+                case 2:
+                        return 0x1e8;
+                case 3:
+                        return 0x168;
+                case 4:
+                        return 0x1e0;
+                case 5:
+                        return 0x160;
+                default:
+                        return 0;
+                }
+        else
+                return 0;
+}
+
+#define IDE_ARCH_OBSOLETE_INIT
+#define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
+
+#ifdef CONFIG_BLK_DEV_IDEPCI
+#define ide_init_default_irq(base)      (0)
+#else
+#define ide_init_default_irq(base)      ide_default_irq(base)
+#endif
+
+/* MIPS port and memory-mapped I/O string operations.  */
+
+#define __ide_insw      insw
+#define __ide_insl      insl
+#define __ide_outsw     outsw
+#define __ide_outsl     outsl
+
+#define __ide_mm_insw   readsw
+#define __ide_mm_insl   readsl
+#define __ide_mm_outsw  writesw
+#define __ide_mm_outsl  writesl
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_MACH_GENERIC_IDE_H */
diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h
new file mode 100644
index 000000000000..500e10ff24de
--- /dev/null
+++ b/include/asm-mips/mach-generic/irq.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+#define NR_IRQS 128
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h
new file mode 100644
index 000000000000..4a98d83b8ec7
--- /dev/null
+++ b/include/asm-mips/mach-generic/mangle-port.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-generic/mc146818rtc.h b/include/asm-mips/mach-generic/mc146818rtc.h
new file mode 100644
index 000000000000..90c2e6f77faa
--- /dev/null
+++ b/include/asm-mips/mach-generic/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_GENERIC_MC146818RTC_H
+#define __ASM_MACH_GENERIC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
diff --git a/include/asm-mips/mach-generic/param.h b/include/asm-mips/mach-generic/param.h
new file mode 100644
index 000000000000..a0d12f964e4f
--- /dev/null
+++ b/include/asm-mips/mach-generic/param.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_PARAM_H
+#define __ASM_MACH_GENERIC_PARAM_H
+
+#define HZ              1000            /* Internal kernel timer frequency */
+
+#endif /* __ASM_MACH_GENERIC_PARAM_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
new file mode 100644
index 000000000000..63c0a81c7832
--- /dev/null
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_MIPS32
+
+#define CAC_BASE                0x80000000
+#define IO_BASE                 0xa0000000
+#define UNCAC_BASE              0xa0000000
+#define MAP_BASE                0xc0000000
+
+/*
+ * This handles the memory map.
+ * We handle pages at KSEG0 for kernels with 32 bit address space.
+ */
+#define PAGE_OFFSET             0x80000000UL
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           0x20000000UL
+#endif
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+
+/*
+ * This handles the memory map.
+ */
+#ifdef CONFIG_DMA_NONCOHERENT
+#define PAGE_OFFSET     0x9800000000000000UL
+#else
+#define PAGE_OFFSET     0xa800000000000000UL
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           (1UL << 59UL)
+#endif
+
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE                0x9800000000000000
+#else
+#define CAC_BASE                0xa800000000000000
+#endif
+#define IO_BASE                 0x9000000000000000
+#define UNCAC_BASE              0x9000000000000000
+#define MAP_BASE                0xc000000000000000
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_MIPS64 */
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-generic/timex.h b/include/asm-mips/mach-generic/timex.h
new file mode 100644
index 000000000000..c6a2e5f0574a
--- /dev/null
+++ b/include/asm-mips/mach-generic/timex.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_TIMEX_H
+#define __ASM_MACH_GENERIC_TIMEX_H
+
+#include <linux/config.h>
+
+/*
+ * Last remaining user of the i8254 PIC, will be converted, too ...
+ */
+#ifdef CONFIG_SNI_RM200_PCI
+#define CLOCK_TICK_RATE         1193182
+#else
+#define CLOCK_TICK_RATE         500000
+#endif
+
+#endif /* __ASM_MACH_GENERIC_TIMEX_H */
diff --git a/include/asm-mips/mach-generic/topology.h b/include/asm-mips/mach-generic/topology.h
new file mode 100644
index 000000000000..5428f333a02c
--- /dev/null
+++ b/include/asm-mips/mach-generic/topology.h
@@ -0,0 +1 @@
+#include <asm-generic/topology.h>
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
new file mode 100644
index 000000000000..3c8896d9b133
--- /dev/null
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP22 with a variety of processors so we can't use defaults for everything.
+ */
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0               /* Needs to change for R8000 */
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h
new file mode 100644
index 000000000000..f19f1eafbc71
--- /dev/null
+++ b/include/asm-mips/mach-ip22/ds1286.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_IP22_DS1286_H
+#define __ASM_MACH_IP22_DS1286_H
+
+#include <asm/sgi/hpc3.h>
+
+#define rtc_read(reg)           (hpc3c0->rtcregs[(reg)] & 0xff)
+#define rtc_write(data, reg)    do { hpc3c0->rtcregs[(reg)] = (data); } while(0)
+
+#endif /* __ASM_MACH_IP22_DS1286_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
new file mode 100644
index 000000000000..30d42fcafe3d
--- /dev/null
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -0,0 +1,55 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP22_SPACES_H
+#define _ASM_MACH_IP22_SPACES_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_MIPS32
+
+#define CAC_BASE                0x80000000
+#define IO_BASE                 0xa0000000
+#define UNCAC_BASE              0xa0000000
+#define MAP_BASE                0xc0000000
+
+/*
+ * This handles the memory map.
+ * We handle pages at KSEG0 for kernels with 32 bit address space.
+ */
+#define PAGE_OFFSET             0x80000000UL
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           0x20000000UL
+#endif
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+#define PAGE_OFFSET             0xffffffff80000000UL
+
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           (1UL << 59UL)
+#endif
+
+#define CAC_BASE                0xffffffff80000000
+#define IO_BASE                 0xffffffffa0000000
+#define UNCAC_BASE              0xffffffffa0000000
+#define MAP_BASE                0xffffffffc0000000
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_MIPS64 */
+
+#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
new file mode 100644
index 000000000000..fe96d7358517
--- /dev/null
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP27 only comes with R10000 family processors all using the same config
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  1
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  1
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  64
+#define cpu_scache_line_size()  128
+
+#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h
new file mode 100644
index 000000000000..806213ce31b6
--- /dev/null
+++ b/include/asm-mips/mach-ip27/irq.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Kanoj Sarcar
+ */
+#ifndef __ASM_MACH_IP27_IRQ_H
+#define __ASM_MACH_IP27_IRQ_H
+
+#include <asm/sn/arch.h>
+
+/*
+ * A hardwired interrupt number is completly stupid for this system - a
+ * large configuration might have thousands if not tenthousands of
+ * interrupts.
+ */
+#define NR_IRQS 256
+
+#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h
new file mode 100644
index 000000000000..f76c44880451
--- /dev/null
+++ b/include/asm-mips/mach-ip27/mangle-port.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
+#define __ASM_MACH_IP27_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
new file mode 100644
index 000000000000..d3f566362e9d
--- /dev/null
+++ b/include/asm-mips/mach-ip27/mmzone.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_MACH_MMZONE_H
+#define _ASM_MACH_MMZONE_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/hub.h>
+
+#define pa_to_nid(addr)         NASID_TO_COMPACT_NODEID(NASID_GET(addr))
+
+#define LEVELS_PER_SLICE        128
+
+struct slice_data {
+        unsigned long irq_alloc_mask[2];
+        unsigned long irq_enable_mask[2];
+        int level_to_irq[LEVELS_PER_SLICE];
+};
+
+struct hub_data {
+        kern_vars_t     kern_vars;
+        DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
+        cpumask_t       h_cpus;
+        unsigned long slice_map;
+        struct slice_data slice[2];
+};
+
+struct node_data {
+        struct pglist_data pglist;
+        struct hub_data hub;
+};
+
+extern struct node_data *__node_data[];
+
+#define NODE_DATA(n)            (&__node_data[(n)]->pglist)
+#define hub_data(n)             (&__node_data[(n)]->hub)
+
+#endif /* _ASM_MACH_MMZONE_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
new file mode 100644
index 000000000000..e3b3fe32eeb1
--- /dev/null
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP27_SPACES_H
+#define _ASM_MACH_IP27_SPACES_H
+
+/*
+ * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
+ * uncached memory addressing.
+ */
+#define CAC_BASE                0xa800000000000000
+
+#define HSPEC_BASE              0x9000000000000000
+#define IO_BASE                 0x9200000000000000
+#define MSPEC_BASE              0x9400000000000000
+#define UNCAC_BASE              0x9600000000000000
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
+
+#define PAGE_OFFSET             CAC_BASE
+
+#define HIGHMEM_START           (~0UL)
+
+#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
new file mode 100644
index 000000000000..a70a81257c3d
--- /dev/null
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_MACH_TOPOLOGY_H
+#define _ASM_MACH_TOPOLOGY_H    1
+
+#include <asm/sn/arch.h>
+#include <asm/sn/hub.h>
+#include <asm/mmzone.h>
+
+#define cpu_to_node(cpu)        (cpu_data[(cpu)].p_nodeid)
+#define parent_node(node)       (node)
+#define node_to_cpumask(node)   (hub_data(node)->h_cpus)
+#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
+#define pcibus_to_cpumask(bus)  (cpu_online_map)
+
+extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
+
+#define node_distance(from, to) (__node_distances[(from)][(to)])
+
+/* sched_domains SD_NODE_INIT for SGI IP27 machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_hot_time         = (10*1000),            \
+        .cache_nice_tries       = 1,                    \
+        .per_cpu_gain           = 100,                  \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
new file mode 100644
index 000000000000..b932237f2193
--- /dev/null
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -0,0 +1,41 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/config.h>
+
+/*
+ * R5000 has an interesting "restriction":  ll(d)/sc(d)
+ * instructions to XKPHYS region simply do uncached bus
+ * requests. This breaks all the atomic bitops functions.
+ * so, for 64bit IP32 kernel we just don't use ll/sc.
+ * This does not affect luserland.
+ */
+#if defined(CONFIG_CPU_R5000) && defined(CONFIG_MIPS64)
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+/* Settings which are common for all ip32 CPUs */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_mips16          0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+
+#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
new file mode 100644
index 000000000000..6e25b52ed8f2
--- /dev/null
+++ b/include/asm-mips/mach-ip32/mangle-port.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ladislav Michl
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
+#define __ASM_MACH_IP32_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  ((port) ^ 3)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h
new file mode 100644
index 000000000000..f5d780ff843f
--- /dev/null
+++ b/include/asm-mips/mach-ip32/mc146818rtc.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ * Copyright (C) 2000 Harald Koerfgen
+ *
+ * RTC routines for IP32 style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_IP32_MC146818RTC_H
+#define __ASM_MACH_IP32_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/ip32/mace.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+
+static unsigned char CMOS_READ(unsigned long addr)
+{
+        return mace->isa.rtc[addr << 8];
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        mace->isa.rtc[addr << 8] = data;
+}
+
+/* FIXME: Do it right. For now just assume that noone lives in 20th century
+ * and no O2 user in 22th century ;-) */
+#define mc146818_decode_year(year) ((year) + 2000)
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MACH_IP32_MC146818RTC_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
new file mode 100644
index 000000000000..c7839f85c68d
--- /dev/null
+++ b/include/asm-mips/mach-ip32/spaces.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP32_SPACES_H
+#define _ASM_MACH_IP32_SPACES_H
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           (1UL << 59UL)
+#endif
+
+#define CAC_BASE                0x9800000000000000
+#define IO_BASE                 0x9000000000000000
+#define UNCAC_BASE              0x9000000000000000
+#define MAP_BASE                0xc000000000000000
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+/*
+ * This handles the memory map.
+ */
+#define PAGE_OFFSET             CAC_BASE
+
+#endif /* __ASM_MACH_IP32_SPACES_H */
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
new file mode 100644
index 000000000000..ca57e7db98bb
--- /dev/null
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Jaguar ATX always has the RM9000 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
+
+#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ja/spaces.h b/include/asm-mips/mach-ja/spaces.h
new file mode 100644
index 000000000000..8466a0e69c79
--- /dev/null
+++ b/include/asm-mips/mach-ja/spaces.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_MACH_JA_SPACES_H
+#define __ASM_MACH_JA_SPACES_H
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#define HIGHMEM_START           0x08000000UL
+
+#include_next <spaces.h>
+
+#endif /* __ASM_MACH_JA_SPACES_H */
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
new file mode 100644
index 000000000000..8cf0d042c864
--- /dev/null
+++ b/include/asm-mips/mach-jazz/floppy.h
@@ -0,0 +1,135 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JAZZ_FLOPPY_H
+#define __ASM_MACH_JAZZ_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <asm/addrspace.h>
+#include <asm/jazz.h>
+#include <asm/jazzdma.h>
+#include <asm/pgtable.h>
+
+static inline unsigned char fd_inb(unsigned int port)
+{
+        unsigned char c;
+
+        c = *(volatile unsigned char *) port;
+        udelay(1);
+
+        return c;
+}
+
+static inline void fd_outb(unsigned char value, unsigned int port)
+{
+        *(volatile unsigned char *) port = value;
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        vdma_enable(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        vdma_disable(JAZZ_FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return 0;
+}
+
+static inline void fd_free_dma(void)
+{
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        vdma_set_mode(JAZZ_FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *a)
+{
+        vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a)));
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        vdma_set_count(JAZZ_FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return vdma_get_residue(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+}
+
+static inline void fd_disable_irq(void)
+{
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
+}
+                                                                                
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return JAZZ_FDC_BASE;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        unsigned long mem;
+
+        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
+        if(!mem)
+                return 0;
+        vdma_alloc(CPHYSADDR(mem), size);       /* XXX error checking */
+
+        return mem;
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        vdma_free(vdma_phys2log(CPHYSADDR(addr)));
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        /* XXX This is wrong for machines with ED 2.88mb disk drives like the
+           Olivetti M700.  Anyway, we should suck this from the ARC
+           firmware.  */
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_JAZZ_FLOPPY_H */
diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h
new file mode 100644
index 000000000000..f44fdba1998b
--- /dev/null
+++ b/include/asm-mips/mach-jazz/mc146818rtc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for Jazz style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_JAZZ_MC146818RTC_H
+#define __ASM_MACH_JAZZ_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/jazz.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+
+        return *(char *)JAZZ_RTC_BASE;
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        *(char *)JAZZ_RTC_BASE = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */
diff --git a/include/asm-mips/mach-jazz/param.h b/include/asm-mips/mach-jazz/param.h
new file mode 100644
index 000000000000..639763a517bc
--- /dev/null
+++ b/include/asm-mips/mach-jazz/param.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JAZZ_PARAM_H
+#define __ASM_MACH_JAZZ_PARAM_H
+
+/*
+ * Jazz is currently using the internal 100Hz timer of the R4030
+ */
+#define HZ              100             /* Internal kernel timer frequency */
+
+#endif /* __ASM_MACH_JAZZ_PARAM_H */
diff --git a/include/asm-mips/mach-jazz/timex.h b/include/asm-mips/mach-jazz/timex.h
new file mode 100644
index 000000000000..93affa33dfa8
--- /dev/null
+++ b/include/asm-mips/mach-jazz/timex.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JAZZ_TIMEX_H
+#define __ASM_MACH_JAZZ_TIMEX_H
+
+/*
+ * Jazz is still using the R4030 100Hz counter
+ */
+#define CLOCK_TICK_RATE         100
+
+#endif /* __ASM_MACH_JAZZ_TIMEX_H */
diff --git a/include/asm-mips/mach-jmr3927/asm/ds1742.h b/include/asm-mips/mach-jmr3927/asm/ds1742.h
new file mode 100644
index 000000000000..134a4b6c334a
--- /dev/null
+++ b/include/asm-mips/mach-jmr3927/asm/ds1742.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JMR3927_ASM_DS1742_H
+#define __ASM_MACH_JMR3927_ASM_DS1742_H
+
+#include <asm/jmr3927/jmr3927.h>
+
+#define rtc_read(reg)           (jmr3927_nvram_in(addr))
+#define rtc_write(data, reg)    (jmr3927_nvram_out((data),(reg)))
+
+#endif /* __ASM_MACH_JMR3927_ASM_DS1742_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
new file mode 100644
index 000000000000..1a9ad45cc135
--- /dev/null
+++ b/include/asm-mips/mach-lasat/mach-gt64120.h
@@ -0,0 +1,27 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
+#define _ASM_GT64120_LASAT_GT64120_DEP_H
+
+/*
+ *   GT64120 config space base address on Lasat 100
+ */
+#define GT64120_BASE    (KSEG1ADDR(0x14000000))
+
+/*
+ *   PCI Bus allocation
+ *
+ *   (Guessing ...)
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x10000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+#define GT_ISA_IO_BASE  PCI_IO_BASE
+
+#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
new file mode 100644
index 000000000000..6f51be571bf0
--- /dev/null
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -0,0 +1,67 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/config.h>
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4ktlb           1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4ktlb           1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h
new file mode 100644
index 000000000000..511f7cf3a6be
--- /dev/null
+++ b/include/asm-mips/mach-mips/mach-gt64120.h
@@ -0,0 +1,28 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+
+#define MIPS_GT_BASE    0x1be00000
+
+extern unsigned long _pcictrl_gt64120;
+/*
+ *   GT64120 config space base address
+ */
+#define GT64120_BASE    _pcictrl_gt64120
+
+/*
+ *   PCI Bus allocation
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x10000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+#define GT_ISA_IO_BASE  PCI_IO_BASE
+
+#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-mips/mc146818rtc.h
new file mode 100644
index 000000000000..6730ba066576
--- /dev/null
+++ b/include/asm-mips/mach-mips/mc146818rtc.h
@@ -0,0 +1,48 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2003 by Ralf Baechle
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * RTC routines for Malta style attached PIIX4 device, which contains a
+ * Motorola MC146818A-compatible Real Time Clock.
+ */
+#ifndef __ASM_MACH_MALTA_MC146818RTC_H
+#define __ASM_MACH_MALTA_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/malta.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        return inb(MALTA_RTC_DAT_REG);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        outb(data, MALTA_RTC_DAT_REG);
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+
+#endif /* __ASM_MACH_MALTA_MC146818RTC_H */
diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h
new file mode 100644
index 000000000000..a62ecb53c751
--- /dev/null
+++ b/include/asm-mips/mach-ocelot/mach-gt64120.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
+#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
+
+/*
+ * PCI address allocation
+ */
+#define GT_PCI_MEM_BASE (0x22000000UL)
+#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE
+#define GT_PCI_IO_BASE  (0x20000000UL)
+#define GT_PCI_IO_SIZE  GT_DEF_PCI0_IO_SIZE
+
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE    (gt64120_base)
+
+/*
+ * GT timer irq
+ */
+#define GT_TIMER                6
+
+#endif  /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7473512384bc
--- /dev/null
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -0,0 +1,48 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Author: Manish Lachwani, mlachwani@mvista.com
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Ocelot-3 is based on Rm7900 processor which
+ * is based on the E9000 core.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
+
+#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/include/asm-mips/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 000000000000..622c58710e5b
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
+#define __ASM_MACH_AU1XX_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define RTC_PORT(x)     (0x0c000000 + (x))
+#define RTC_IRQ         8
+#define PB1500_RTC_ADDR 0x0c000000
+
+static inline unsigned char CMOS_READ(unsigned long offset)
+{
+        offset <<= 2;
+        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
+{
+        offset <<= 2;
+        au_writel(data, offset + PB1500_RTC_ADDR);
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
new file mode 100644
index 000000000000..50c1e413a688
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -0,0 +1,172 @@
+/*
+ * Alchemy Semi PB1000 Referrence Board
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1000_H
+#define __ASM_PB1000_H
+
+/* PCMCIA PB1000 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+#define PB1000_PCR     0xBE000000
+  #define PCR_SLOT_0_VPP0  (1<<0)
+  #define PCR_SLOT_0_VPP1  (1<<1)
+  #define PCR_SLOT_0_VCC0  (1<<2)
+  #define PCR_SLOT_0_VCC1  (1<<3)
+  #define PCR_SLOT_0_RST   (1<<4)
+
+  #define PCR_SLOT_1_VPP0  (1<<8)
+  #define PCR_SLOT_1_VPP1  (1<<9)
+  #define PCR_SLOT_1_VCC0  (1<<10)
+  #define PCR_SLOT_1_VCC1  (1<<11)
+  #define PCR_SLOT_1_RST   (1<<12)
+
+#define PB1000_MDR     0xBE000004
+  #define MDR_PI        (1<<5)  /* pcmcia int latch  */
+  #define MDR_EPI      (1<<14)  /* enable pcmcia int */
+  #define MDR_CPI      (1<<15)  /* clear pcmcia int  */
+
+#define PB1000_ACR1    0xBE000008
+  #define ACR1_SLOT_0_CD1    (1<<0)  /* card detect 1     */
+  #define ACR1_SLOT_0_CD2    (1<<1)  /* card detect 2     */
+  #define ACR1_SLOT_0_READY  (1<<2)  /* ready             */
+  #define ACR1_SLOT_0_STATUS (1<<3)  /* status change     */
+  #define ACR1_SLOT_0_VS1    (1<<4)  /* voltage sense 1   */
+  #define ACR1_SLOT_0_VS2    (1<<5)  /* voltage sense 2   */
+  #define ACR1_SLOT_0_INPACK (1<<6)  /* inpack pin status */
+  #define ACR1_SLOT_1_CD1    (1<<8)  /* card detect 1     */
+  #define ACR1_SLOT_1_CD2    (1<<9)  /* card detect 2     */
+  #define ACR1_SLOT_1_READY  (1<<10) /* ready             */
+  #define ACR1_SLOT_1_STATUS (1<<11) /* status change     */
+  #define ACR1_SLOT_1_VS1    (1<<12) /* voltage sense 1   */
+  #define ACR1_SLOT_1_VS2    (1<<13) /* voltage sense 2   */
+  #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
+
+#define CPLD_AUX0      0xBE00000C
+#define CPLD_AUX1      0xBE000010
+#define CPLD_AUX2      0xBE000014
+
+/* Voltage levels */
+
+/* VPPEN1 - VPPEN0 */
+#define VPP_GND ((0<<1) | (0<<0))
+#define VPP_5V  ((1<<1) | (0<<0))
+#define VPP_3V  ((0<<1) | (1<<0))
+#define VPP_12V ((0<<1) | (1<<0))
+#define VPP_HIZ ((1<<1) | (1<<0))
+
+/* VCCEN1 - VCCEN0 */
+#define VCC_3V  ((0<<1) | (1<<0))
+#define VCC_5V  ((1<<1) | (0<<0))
+#define VCC_HIZ ((0<<1) | (0<<0))
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+
+/* PCI PB1000 specific defines */
+/* The reason these defines are here instead of au1000.h is because
+ * the Au1000 does not have a PCI bus controller so the PCI implementation
+ * on the some of the older Pb1000 boards was very board specific.
+ */
+#define PCI_CONFIG_BASE   0xBA020000 /* the only external slot */
+
+#define SDRAM_DEVID       0xBA010000
+#define SDRAM_CMD         0xBA010004
+#define SDRAM_CLASS       0xBA010008
+#define SDRAM_MISC        0xBA01000C
+#define SDRAM_MBAR        0xBA010010
+
+#define PCI_IO_DATA_PORT  0xBA800000
+
+#define PCI_IO_ADDR       0xBE00001C
+#define PCI_INT_ACK       0xBBC00000
+#define PCI_IO_READ       0xBBC00020
+#define PCI_IO_WRITE      0xBBC00030
+
+#define PCI_BRIDGE_CONFIG 0xBE000018
+
+#define PCI_IO_START      0x10000000
+#define PCI_IO_END        0x1000ffff
+#define PCI_MEM_START     0x18000000
+#define PCI_MEM_END       0x18ffffff
+
+#define PCI_FIRST_DEVFN   0
+#define PCI_LAST_DEVFN    1
+
+static inline u8 au_pci_io_readb(u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
+        return (readl(PCI_IO_DATA_PORT) & 0xff);
+}
+
+static inline u16 au_pci_io_readw(u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
+        return (readl(PCI_IO_DATA_PORT) & 0xffff);
+}
+
+static inline u32 au_pci_io_readl(u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
+        return readl(PCI_IO_DATA_PORT);
+}
+
+static inline void au_pci_io_writeb(u8 val, u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
+        writel(val, PCI_IO_DATA_PORT);
+}
+
+static inline void au_pci_io_writew(u16 val, u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
+        writel(val, PCI_IO_DATA_PORT);
+}
+
+static inline void au_pci_io_writel(u32 val, u32 addr)
+{
+        writel(addr, PCI_IO_ADDR);
+        writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
+        writel(val, PCI_IO_DATA_PORT);
+}
+
+static inline void set_sdram_extbyte(void)
+{
+        writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
+}
+
+static inline void set_slot_extbyte(void)
+{
+        writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
+}
+#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
new file mode 100644
index 000000000000..4c5a1cd01841
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -0,0 +1,85 @@
+/*
+ * Alchemy Semi PB1100 Referrence Board
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1100_H
+#define __ASM_PB1100_H
+
+#define PB1100_IDENT          0xAE000000
+#define BOARD_STATUS_REG      0xAE000004
+  #define PB1100_ROM_SEL         (1<<15)
+  #define PB1100_ROM_SIZ         (1<<14)
+  #define PB1100_SWAP_BOOT       (1<<13)
+  #define PB1100_FLASH_WP        (1<<12)
+  #define PB1100_ROM_H_STS       (1<<11)
+  #define PB1100_ROM_L_STS       (1<<10)
+  #define PB1100_FLASH_H_STS      (1<<9)
+  #define PB1100_FLASH_L_STS      (1<<8)
+  #define PB1100_SRAM_SIZ         (1<<7)
+  #define PB1100_TSC_BUSY         (1<<6)
+  #define PB1100_PCMCIA_VS_MASK   (3<<4)
+  #define PB1100_RS232_CD         (1<<3)
+  #define PB1100_RS232_CTS        (1<<2)
+  #define PB1100_RS232_DSR        (1<<1)
+  #define PB1100_RS232_RI         (1<<0)
+
+#define PB1100_IRDA_RS232     0xAE00000C
+  #define PB1100_IRDA_FULL       (0<<14) /* full power */
+  #define PB1100_IRDA_SHUTDOWN   (1<<14)
+  #define PB1100_IRDA_TT         (2<<14) /* 2/3 power */
+  #define PB1100_IRDA_OT         (3<<14) /* 1/3 power */
+  #define PB1100_IRDA_FIR        (1<<13)
+
+#define PCMCIA_BOARD_REG     0xAE000010
+  #define PB1100_SD_WP1_RO       (1<<15) /* read only */
+  #define PB1100_SD_WP0_RO       (1<<14) /* read only */
+  #define PB1100_SD_PWR1         (1<<11) /* applies power to SD1 */
+  #define PB1100_SD_PWR0         (1<<10) /* applies power to SD0 */
+  #define PB1100_SEL_SD_CONN1     (1<<9)
+  #define PB1100_SEL_SD_CONN0     (1<<8)
+  #define PC_DEASSERT_RST         (1<<7)
+  #define PC_DRV_EN               (1<<4)
+
+#define PB1100_G_CONTROL      0xAE000014 /* graphics control */
+
+#define PB1100_RST_VDDI       0xAE00001C
+  #define PB1100_SOFT_RESET      (1<<15) /* clear to reset the board */
+  #define PB1100_VDDI_MASK        (0x1F)
+
+#define PB1100_LEDS           0xAE000018
+
+/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
+ * 7:0 is the LED Display's decimal points.
+ */
+#define PB1100_HEX_LED        0xAE000018
+
+/* PCMCIA PB1100 specific defines */
+#define PCMCIA_MAX_SOCK 0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
+
+#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
new file mode 100644
index 000000000000..d6c779747b3c
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -0,0 +1,51 @@
+/*
+ * Alchemy Semi PB1500 Referrence Board
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1500_H
+#define __ASM_PB1500_H
+
+
+#define IDENT_BOARD_REG           0xAE000000
+#define BOARD_STATUS_REG          0xAE000004
+#define PCI_BOARD_REG             0xAE000010
+#define PCMCIA_BOARD_REG          0xAE000010
+  #define PC_DEASSERT_RST               0x80
+  #define PC_DRV_EN                     0x10 
+#define PB1500_G_CONTROL          0xAE000014
+#define PB1500_RST_VDDI           0xAE00001C
+#define PB1500_LEDS               0xAE000018
+  
+#define PB1500_HEX_LED            0xAF000004
+#define PB1500_HEX_LED_BLANK      0xAF000008
+
+/* PCMCIA PB1500 specific defines */
+#define PCMCIA_MAX_SOCK 0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
+
+#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
new file mode 100644
index 000000000000..431d6088ea96
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -0,0 +1,169 @@
+/*
+ * AMD Alchemy Semi PB1550 Referrence Board
+ * Board Registers defines.
+ *
+ * Copyright 2004 Embedded Edge LLC.
+ * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1550_H
+#define __ASM_PB1550_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC2_BASE_ADDR
+#define I2S_PSC_BASE        PSC3_BASE_ADDR
+
+#define BCSR_PHYS_ADDR 0xAF000000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 pci;
+                u16 reserved5;
+        /*18*/  u16 leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_PCMCIA0FI   0x0010
+#define BCSR_STATUS_PCMCIA1FI   0x0020
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_SRAMWIDTH   0x0080
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_ROMBUSY     0x0200
+#define BCSR_STATUS_USBOTGID    0x0800
+#define BCSR_STATUS_U0RXD       0x1000
+#define BCSR_STATUS_U1RXD       0x2000
+#define BCSR_STATUS_U3RXD       0x8000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_PHY0        0x0001
+#define BCSR_RESETS_PHY1        0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_WSC         0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_RESETS_DMAREQ      0x8000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_PCI_M66EN          0x0001
+#define BCSR_PCI_M33            0x0100
+#define BCSR_PCI_EXTERNARB      0x0200
+#define BCSR_PCI_GPIO200RST     0x0400
+#define BCSR_PCI_CLKOUT         0x0800
+#define BCSR_PCI_CFGHOST        0x1000
+
+#define BCSR_LEDS_DECIMALS      0x00FF
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_BOTH_BANKS
+#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_BOOT_ONLY
+#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_USER_ONLY
+#endif
+
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                        (18 >> 2)
+#define NAND_T_PUL                      (30 >> 2)
+#define NAND_T_SU                       (30 >> 2)
+#define NAND_T_WH                       (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+
+#endif /* __ASM_PB1550_H */
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f48736032b2a
--- /dev/null
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
+ */
+#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+
+#include <cpu-feature-overrides.h>
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4ktlb           1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_watch           0
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  0       /* No S-cache on R5000 I think ...  */
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  0       /* No S-cache on R5000 I think ...  */
+
+#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rm200/mc146818rtc.h b/include/asm-mips/mach-rm200/mc146818rtc.h
new file mode 100644
index 000000000000..d37ae68dc6a3
--- /dev/null
+++ b/include/asm-mips/mach-rm200/mc146818rtc.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip with ARC epoch.
+ */
+#ifndef __ASM_MACH_RM200_MC146818RTC_H
+#define __ASM_MACH_RM200_MC146818RTC_H
+
+#define mc146818_decode_year(year) ((year) + 1980)
+
+#include_next <mc146818rtc.h>
+
+#endif /* __ASM_MACH_RM200_MC146818RTC_H */
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
new file mode 100644
index 000000000000..a3a2cc6014b2
--- /dev/null
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Sibyte are MIPS64 processors weired to a specific configuration
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          1
+#define cpu_has_ejtag           1
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-vr41xx/timex.h b/include/asm-mips/mach-vr41xx/timex.h
new file mode 100644
index 000000000000..8d71485d003a
--- /dev/null
+++ b/include/asm-mips/mach-vr41xx/timex.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+/*
+ * Changes:
+ *  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *  - CLOCK_TICK_RATE is changed into 32768 from 6144000.
+ */
+#ifndef __ASM_MACH_VR41XX_TIMEX_H
+#define __ASM_MACH_VR41XX_TIMEX_H
+
+#define CLOCK_TICK_RATE         32768
+
+#endif /* __ASM_MACH_VR41XX_TIMEX_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
new file mode 100644
index 000000000000..58603e3daca6
--- /dev/null
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Jaguar ATX always has the RM9000 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_subset_pcaches  0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE      32UL
+
+#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
new file mode 100644
index 000000000000..9225b3397a4f
--- /dev/null
+++ b/include/asm-mips/marvell.h
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ */
+#ifndef __ASM_MIPS_MARVELL_H
+#define __ASM_MIPS_MARVELL_H
+
+#include <linux/pci.h>
+
+#include <asm/byteorder.h>
+
+extern unsigned long marvell_base;
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.
+ */
+#define __MV_READ(ofs)                                                  \
+        (*(volatile u32 *)(marvell_base+(ofs)))
+#define __MV_WRITE(ofs, data)                                           \
+        do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0)
+
+#define MV_READ(ofs)            le32_to_cpu(__MV_READ(ofs))
+#define MV_WRITE(ofs, data)     __MV_WRITE(ofs, cpu_to_le32(data))
+
+#define MV_READ_16(ofs)                                                 \
+        le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs)))
+#define MV_WRITE_16(ofs, data)  \
+        *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data)
+
+#define MV_READ_8(ofs)                                                  \
+        *(volatile u8 *)(marvell_base+(ofs))
+#define MV_WRITE_8(ofs, data)                                           \
+        *(volatile u8 *)(marvell_base+(ofs)) = data
+
+#define MV_SET_REG_BITS(ofs, bits)                                      \
+        (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits))
+#define MV_RESET_REG_BITS(ofs, bits)                                    \
+        (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits))
+
+extern struct pci_ops mv_pci_ops;
+
+struct mv_pci_controller {
+        struct pci_controller   pcic;
+
+        /*
+         * GT-64240/MV-64340 specific, per host bus information
+         */
+        unsigned long   config_addr;
+        unsigned long   config_vreg;
+};
+
+#endif  /* __ASM_MIPS_MARVELL_H */
diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h
new file mode 100644
index 000000000000..a2c2d2c24303
--- /dev/null
+++ b/include/asm-mips/mc146818-time.h
@@ -0,0 +1,128 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_MC146818_TIME_H
+#define __ASM_MC146818_TIME_H
+
+#include <linux/bcd.h>
+#include <linux/mc146818rtc.h>
+#include <linux/time.h>
+
+/*
+ * For check timing call set_rtc_mmss() 500ms; used in timer interrupt.
+ */
+#define USEC_AFTER      500000
+#define USEC_BEFORE     500000
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ *      sets the minutes. Usually you'll only notice that after reboot!
+ */
+static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
+{
+        int real_seconds, real_minutes, cmos_minutes;
+        unsigned char save_control, save_freq_select;
+        int retval = 0;
+
+        save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
+        CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+
+        save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
+        CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+
+        cmos_minutes = CMOS_READ(RTC_MINUTES);
+        if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
+                BCD_TO_BIN(cmos_minutes);
+
+        /*
+         * since we're only adjusting minutes and seconds,
+         * don't interfere with hour overflow. This avoids
+         * messing with unknown time zones but requires your
+         * RTC not to be off by more than 15 minutes
+         */
+        real_seconds = nowtime % 60;
+        real_minutes = nowtime / 60;
+        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
+                real_minutes += 30;             /* correct for half hour time zone */
+        real_minutes %= 60;
+
+        if (abs(real_minutes - cmos_minutes) < 30) {
+                if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                        BIN_TO_BCD(real_seconds);
+                        BIN_TO_BCD(real_minutes);
+                }
+                CMOS_WRITE(real_seconds,RTC_SECONDS);
+                CMOS_WRITE(real_minutes,RTC_MINUTES);
+        } else {
+                printk(KERN_WARNING
+                       "set_rtc_mmss: can't update from %d to %d\n",
+                       cmos_minutes, real_minutes);
+                retval = -1;
+        }
+
+        /* The following flags have to be released exactly in this order,
+         * otherwise the DS12887 (popular MC146818A clone with integrated
+         * battery and quartz) will not reset the oscillator and will not
+         * update precisely 500 ms later. You won't find this mentioned in
+         * the Dallas Semiconductor data sheets, but who believes data
+         * sheets anyway ...                           -- Markus Kuhn
+         */
+        CMOS_WRITE(save_control, RTC_CONTROL);
+        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+
+        return retval;
+}
+
+static inline unsigned long mc146818_get_cmos_time(void)
+{
+        unsigned int year, mon, day, hour, min, sec;
+        int i;
+
+        /*
+         * The Linux interpretation of the CMOS clock register contents:
+         * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
+         * RTC registers show the second which has precisely just started.
+         * Let's hope other operating systems interpret the RTC the same way.
+         */
+
+        /* read RTC exactly on falling edge of update flag */
+        for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
+                if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
+                        break;
+        for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
+                if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
+                        break;
+
+        do { /* Isn't this overkill ? UIP above should guarantee consistency */
+                sec = CMOS_READ(RTC_SECONDS);
+                min = CMOS_READ(RTC_MINUTES);
+                hour = CMOS_READ(RTC_HOURS);
+                day = CMOS_READ(RTC_DAY_OF_MONTH);
+                mon = CMOS_READ(RTC_MONTH);
+                year = CMOS_READ(RTC_YEAR);
+        } while (sec != CMOS_READ(RTC_SECONDS));
+
+        if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                BCD_TO_BIN(sec);
+                BCD_TO_BIN(min);
+                BCD_TO_BIN(hour);
+                BCD_TO_BIN(day);
+                BCD_TO_BIN(mon);
+                BCD_TO_BIN(year);
+        }
+        year = mc146818_decode_year(year);
+
+        return mktime(year, mon, day, hour, min, sec);
+}
+
+#endif /* __ASM_MC146818_TIME_H */
diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h
new file mode 100644
index 000000000000..68b4da6d520b
--- /dev/null
+++ b/include/asm-mips/mc146818rtc.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2000 Ralf Baechle
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <mc146818rtc.h>
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h
new file mode 100644
index 000000000000..0998151fb3a1
--- /dev/null
+++ b/include/asm-mips/mips-boards/atlas.h
@@ -0,0 +1,64 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the Atlas board specific address-MAP, registers, etc.
+ *
+ */
+#ifndef _MIPS_ATLAS_H
+#define _MIPS_ATLAS_H
+
+#include <asm/addrspace.h>
+
+/*
+ * Atlas RTC-device indirect register access.
+ */
+#define ATLAS_RTC_ADR_REG       0x1f000800
+#define ATLAS_RTC_DAT_REG       0x1f000808
+
+
+/*
+ * Atlas interrupt controller register base.
+ */
+#define ATLAS_ICTRL_REGS_BASE   0x1f000000
+
+/*
+ * Atlas UART register base.
+ */
+#define ATLAS_UART_REGS_BASE    0x1f000900
+#define ATLAS_BASE_BAUD ( 3686400 / 16 )
+
+/*
+ * Atlas PSU standby register.
+ */
+#define ATLAS_PSUSTBY_REG       0x1f000600
+#define ATLAS_GOSTBY            0x4d
+
+/*
+ * We make a universal assumption about the way the bootloader (YAMON)
+ * have located the Philips SAA9730 chip.
+ * This is not ideal, but is needed for setting up remote debugging as
+ * soon as possible.
+ */
+#define ATLAS_SAA9730_REG       0x10800000
+
+#define ATLAS_SAA9730_BAUDCLOCK 3692300
+
+#endif /* !(_MIPS_ATLAS_H) */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
new file mode 100644
index 000000000000..bba35c183d08
--- /dev/null
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -0,0 +1,84 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Atlas interrupt controller.
+ *
+ */
+#ifndef _MIPS_ATLASINT_H
+#define _MIPS_ATLASINT_H
+
+#define ATLASINT_BASE           1
+#define ATLASINT_UART           (ATLASINT_BASE+0)
+#define ATLASINT_TIM0           (ATLASINT_BASE+1)
+#define ATLASINT_RES2           (ATLASINT_BASE+2)
+#define ATLASINT_RES3           (ATLASINT_BASE+3)
+#define ATLASINT_RTC            (ATLASINT_BASE+4)
+#define ATLASINT_COREHI         (ATLASINT_BASE+5)
+#define ATLASINT_CORELO         (ATLASINT_BASE+6)
+#define ATLASINT_RES7           (ATLASINT_BASE+7)
+#define ATLASINT_PCIA           (ATLASINT_BASE+8)
+#define ATLASINT_PCIB           (ATLASINT_BASE+9)
+#define ATLASINT_PCIC           (ATLASINT_BASE+10)
+#define ATLASINT_PCID           (ATLASINT_BASE+11)
+#define ATLASINT_ENUM           (ATLASINT_BASE+12)
+#define ATLASINT_DEG            (ATLASINT_BASE+13)
+#define ATLASINT_ATXFAIL        (ATLASINT_BASE+14)
+#define ATLASINT_INTA           (ATLASINT_BASE+15)
+#define ATLASINT_INTB           (ATLASINT_BASE+16)
+#define ATLASINT_ETH            ATLASINT_INTB
+#define ATLASINT_INTC           (ATLASINT_BASE+17)
+#define ATLASINT_SCSI           ATLASINT_INTC
+#define ATLASINT_INTD           (ATLASINT_BASE+18)
+#define ATLASINT_SERR           (ATLASINT_BASE+19)
+#define ATLASINT_RES20          (ATLASINT_BASE+20)
+#define ATLASINT_RES21          (ATLASINT_BASE+21)
+#define ATLASINT_RES22          (ATLASINT_BASE+22)
+#define ATLASINT_RES23          (ATLASINT_BASE+23)
+#define ATLASINT_RES24          (ATLASINT_BASE+24)
+#define ATLASINT_RES25          (ATLASINT_BASE+25)
+#define ATLASINT_RES26          (ATLASINT_BASE+26)
+#define ATLASINT_RES27          (ATLASINT_BASE+27)
+#define ATLASINT_RES28          (ATLASINT_BASE+28)
+#define ATLASINT_RES29          (ATLASINT_BASE+29)
+#define ATLASINT_RES30          (ATLASINT_BASE+30)
+#define ATLASINT_RES31          (ATLASINT_BASE+31)
+#define ATLASINT_END            (ATLASINT_BASE+31)
+
+/*
+ * Atlas registers are memory mapped on 64-bit aligned boundaries and
+ * only word access are allowed.
+ */
+struct atlas_ictrl_regs {
+        volatile unsigned int intraw;
+        int dummy1;
+        volatile unsigned int intseten;
+        int dummy2;
+        volatile unsigned int intrsten;
+        int dummy3;
+        volatile unsigned int intenable;
+        int dummy4;
+        volatile unsigned int intstatus;
+        int dummy5;
+};
+
+extern void atlasint_init(void);
+
+#endif /* !(_MIPS_ATLASINT_H) */
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
new file mode 100644
index 000000000000..cd7125610100
--- /dev/null
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -0,0 +1,431 @@
+/*
+ * Bonito Register Map
+ *
+ * This file is the original bonito.h from Algorithmics with minor changes
+ * to fit into linux.
+ *
+ * Copyright (c) 1999 Algorithmics Ltd
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2001 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * Algorithmics gives permission for anyone to use and modify this file
+ * without any obligation or license condition except that you retain
+ * this copyright message in any source redistribution in whole or part.
+ *
+ */
+
+/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
+/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
+
+#ifndef _ASM_MIPS_BOARDS_BONITO64_H
+#define _ASM_MIPS_BOARDS_BONITO64_H
+
+#ifdef __ASSEMBLY__
+
+/* offsets from base register */
+#define BONITO(x)       (x)
+
+#else /* !__ASSEMBLY__ */
+
+/*
+ * Algorithmics Bonito64 system controller register base.
+ */
+extern unsigned long _pcictrl_bonito;
+extern unsigned long _pcictrl_bonito_pcicfg;
+
+#define BONITO(x)               *(volatile u32 *)(_pcictrl_bonito + (x))
+
+#endif /* __ASSEMBLY__ */
+
+
+#define BONITO_BOOT_BASE                0x1fc00000
+#define BONITO_BOOT_SIZE                0x00100000
+#define BONITO_BOOT_TOP                 (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
+#define BONITO_FLASH_BASE               0x1c000000
+#define BONITO_FLASH_SIZE               0x03000000
+#define BONITO_FLASH_TOP                (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
+#define BONITO_SOCKET_BASE              0x1f800000
+#define BONITO_SOCKET_SIZE              0x00400000
+#define BONITO_SOCKET_TOP               (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
+#define BONITO_REG_BASE                 0x1fe00000
+#define BONITO_REG_SIZE                 0x00040000
+#define BONITO_REG_TOP                  (BONITO_REG_BASE+BONITO_REG_SIZE-1)
+#define BONITO_DEV_BASE                 0x1ff00000
+#define BONITO_DEV_SIZE                 0x00100000
+#define BONITO_DEV_TOP                  (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
+#define BONITO_PCILO_BASE               0x10000000
+#define BONITO_PCILO_SIZE               0x0c000000
+#define BONITO_PCILO_TOP                (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
+#define BONITO_PCILO0_BASE              0x10000000
+#define BONITO_PCILO1_BASE              0x14000000
+#define BONITO_PCILO2_BASE              0x18000000
+#define BONITO_PCIHI_BASE               0x20000000
+#define BONITO_PCIHI_SIZE               0x20000000
+#define BONITO_PCIHI_TOP                (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
+#define BONITO_PCIIO_BASE               0x1fd00000
+#define BONITO_PCIIO_SIZE               0x00100000
+#define BONITO_PCIIO_TOP                (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
+#define BONITO_PCICFG_BASE              0x1fe80000
+#define BONITO_PCICFG_SIZE              0x00080000
+#define BONITO_PCICFG_TOP               (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
+
+
+/* Bonito Register Bases */
+
+#define BONITO_PCICONFIGBASE            0x00
+#define BONITO_REGBASE                  0x100
+
+
+/* PCI Configuration  Registers */
+
+#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
+#define BONITO_PCIDID                   BONITO_PCI_REG(0x00)
+#define BONITO_PCICMD                   BONITO_PCI_REG(0x04)
+#define BONITO_PCICLASS                 BONITO_PCI_REG(0x08)
+#define BONITO_PCILTIMER                BONITO_PCI_REG(0x0c)
+#define BONITO_PCIBASE0                 BONITO_PCI_REG(0x10)
+#define BONITO_PCIBASE1                 BONITO_PCI_REG(0x14)
+#define BONITO_PCIBASE2                 BONITO_PCI_REG(0x18)
+#define BONITO_PCIEXPRBASE              BONITO_PCI_REG(0x30)
+#define BONITO_PCIINT                   BONITO_PCI_REG(0x3c)
+
+#define BONITO_PCICMD_PERR_CLR          0x80000000
+#define BONITO_PCICMD_SERR_CLR          0x40000000
+#define BONITO_PCICMD_MABORT_CLR        0x20000000
+#define BONITO_PCICMD_MTABORT_CLR       0x10000000
+#define BONITO_PCICMD_TABORT_CLR        0x08000000
+#define BONITO_PCICMD_MPERR_CLR         0x01000000
+#define BONITO_PCICMD_PERRRESPEN        0x00000040
+#define BONITO_PCICMD_ASTEPEN           0x00000080
+#define BONITO_PCICMD_SERREN            0x00000100
+#define BONITO_PCILTIMER_BUSLATENCY     0x0000ff00
+#define BONITO_PCILTIMER_BUSLATENCY_SHIFT       8
+
+
+
+
+/* 1. Bonito h/w Configuration */
+/* Power on register */
+
+#define BONITO_BONPONCFG                BONITO(BONITO_REGBASE + 0x00)
+
+#define BONITO_BONPONCFG_SYSCONTROLLERRD        0x00040000
+#define BONITO_BONPONCFG_ROMCS1SAMP     0x00020000
+#define BONITO_BONPONCFG_ROMCS0SAMP     0x00010000
+#define BONITO_BONPONCFG_CPUBIGEND      0x00004000
+/* Added by RPF 11-9-00 */
+#define BONITO_BONPONCFG_BURSTORDER     0x00001000
+/* --- */
+#define BONITO_BONPONCFG_CPUPARITY      0x00002000
+#define BONITO_BONPONCFG_CPUTYPE        0x00000007
+#define BONITO_BONPONCFG_CPUTYPE_SHIFT  0
+#define BONITO_BONPONCFG_PCIRESET_OUT   0x00000008
+#define BONITO_BONPONCFG_IS_ARBITER     0x00000010
+#define BONITO_BONPONCFG_ROMBOOT        0x000000c0
+#define BONITO_BONPONCFG_ROMBOOT_SHIFT  6
+
+#define BONITO_BONPONCFG_ROMBOOT_FLASH  (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SDRAM  (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_CPURESET       (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+
+#define BONITO_BONPONCFG_ROMCS0WIDTH    0x00000100
+#define BONITO_BONPONCFG_ROMCS1WIDTH    0x00000200
+#define BONITO_BONPONCFG_ROMCS0FAST     0x00000400
+#define BONITO_BONPONCFG_ROMCS1FAST     0x00000800
+#define BONITO_BONPONCFG_CONFIG_DIS     0x00000020
+
+
+/* Other Bonito configuration */
+
+#define BONITO_BONGENCFG_OFFSET         0x4
+#define BONITO_BONGENCFG                BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
+
+#define BONITO_BONGENCFG_DEBUGMODE      0x00000001
+#define BONITO_BONGENCFG_SNOOPEN        0x00000002
+#define BONITO_BONGENCFG_CPUSELFRESET   0x00000004
+
+#define BONITO_BONGENCFG_FORCE_IRQA     0x00000008
+#define BONITO_BONGENCFG_IRQA_ISOUT     0x00000010
+#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
+#define BONITO_BONGENCFG_BYTESWAP       0x00000040
+
+#define BONITO_BONGENCFG_UNCACHED       0x00000080
+#define BONITO_BONGENCFG_PREFETCHEN     0x00000100
+#define BONITO_BONGENCFG_WBEHINDEN      0x00000200
+#define BONITO_BONGENCFG_CACHEALG       0x00000c00
+#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
+#define BONITO_BONGENCFG_PCIQUEUE       0x00001000
+#define BONITO_BONGENCFG_CACHESTOP      0x00002000
+#define BONITO_BONGENCFG_MSTRBYTESWAP   0x00004000
+#define BONITO_BONGENCFG_BUSERREN       0x00008000
+#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
+#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT       0x00020000
+
+/* 2. IO & IDE configuration */
+
+#define BONITO_IODEVCFG                 BONITO(BONITO_REGBASE + 0x08)
+
+/* 3. IO & IDE configuration */
+
+#define BONITO_SDCFG                    BONITO(BONITO_REGBASE + 0x0c)
+
+/* 4. PCI address map control */
+
+#define BONITO_PCIMAP                   BONITO(BONITO_REGBASE + 0x10)
+#define BONITO_PCIMEMBASECFG            BONITO(BONITO_REGBASE + 0x14)
+#define BONITO_PCIMAP_CFG               BONITO(BONITO_REGBASE + 0x18)
+
+/* 5. ICU & GPIO regs */
+
+/* GPIO Regs - r/w */
+
+#define BONITO_GPIODATA_OFFSET          0x1c
+#define BONITO_GPIODATA                 BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
+#define BONITO_GPIOIE                   BONITO(BONITO_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define BONITO_INTEDGE                  BONITO(BONITO_REGBASE + 0x24)
+#define BONITO_INTSTEER                 BONITO(BONITO_REGBASE + 0x28)
+#define BONITO_INTPOL                   BONITO(BONITO_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define BONITO_INTENSET                 BONITO(BONITO_REGBASE + 0x30)
+#define BONITO_INTENCLR                 BONITO(BONITO_REGBASE + 0x34)
+#define BONITO_INTEN                    BONITO(BONITO_REGBASE + 0x38)
+#define BONITO_INTISR                   BONITO(BONITO_REGBASE + 0x3c)
+
+/* PCI mail boxes */
+
+#define BONITO_PCIMAIL0_OFFSET          0x40
+#define BONITO_PCIMAIL1_OFFSET          0x44
+#define BONITO_PCIMAIL2_OFFSET          0x48
+#define BONITO_PCIMAIL3_OFFSET          0x4c
+#define BONITO_PCIMAIL0                 BONITO(BONITO_REGBASE + 0x40)
+#define BONITO_PCIMAIL1                 BONITO(BONITO_REGBASE + 0x44)
+#define BONITO_PCIMAIL2                 BONITO(BONITO_REGBASE + 0x48)
+#define BONITO_PCIMAIL3                 BONITO(BONITO_REGBASE + 0x4c)
+
+
+/* 6. PCI cache */
+
+#define BONITO_PCICACHECTRL             BONITO(BONITO_REGBASE + 0x50)
+#define BONITO_PCICACHETAG              BONITO(BONITO_REGBASE + 0x54)
+
+#define BONITO_PCIBADADDR               BONITO(BONITO_REGBASE + 0x58)
+#define BONITO_PCIMSTAT                 BONITO(BONITO_REGBASE + 0x5c)
+
+
+/*
+#define BONITO_PCIRDPOST                BONITO(BONITO_REGBASE + 0x60)
+#define BONITO_PCIDATA                  BONITO(BONITO_REGBASE + 0x64)
+*/
+
+/* 7. IDE DMA & Copier */
+
+#define BONITO_CONFIGBASE               0x000
+#define BONITO_BONITOBASE               0x100
+#define BONITO_LDMABASE                 0x200
+#define BONITO_COPBASE                  0x300
+#define BONITO_REG_BLOCKMASK            0x300
+
+#define BONITO_LDMACTRL                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMASTAT                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMAADDR                 BONITO(BONITO_LDMABASE + 0x4)
+#define BONITO_LDMAGO                   BONITO(BONITO_LDMABASE + 0x8)
+#define BONITO_LDMADATA                 BONITO(BONITO_LDMABASE + 0xc)
+
+#define BONITO_COPCTRL                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPSTAT                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPPADDR                 BONITO(BONITO_COPBASE + 0x4)
+#define BONITO_COPDADDR                 BONITO(BONITO_COPBASE + 0x8)
+#define BONITO_COPGO                    BONITO(BONITO_COPBASE + 0xc)
+
+
+/* ###### Bit Definitions for individual Registers #### */
+
+/* Gen DMA. */
+
+#define BONITO_IDECOPDADDR_DMA_DADDR    0x0ffffffc
+#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT      2
+#define BONITO_IDECOPPADDR_DMA_PADDR    0xfffffffc
+#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT      2
+#define BONITO_IDECOPGO_DMA_SIZE        0x0000fffe
+#define BONITO_IDECOPGO_DMA_SIZE_SHIFT  0
+#define BONITO_IDECOPGO_DMA_WRITE       0x00010000
+#define BONITO_IDECOPGO_DMAWCOUNT       0x000f0000
+#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
+
+#define BONITO_IDECOPCTRL_DMA_STARTBIT  0x80000000
+#define BONITO_IDECOPCTRL_DMA_RSTBIT    0x40000000
+
+/* DRAM - sdCfg */
+
+#define BONITO_SDCFG_AROWBITS           0x00000003
+#define BONITO_SDCFG_AROWBITS_SHIFT     0
+#define BONITO_SDCFG_ACOLBITS           0x0000000c
+#define BONITO_SDCFG_ACOLBITS_SHIFT     2
+#define BONITO_SDCFG_ABANKBIT           0x00000010
+#define BONITO_SDCFG_ASIDES             0x00000020
+#define BONITO_SDCFG_AABSENT            0x00000040
+#define BONITO_SDCFG_AWIDTH64           0x00000080
+
+#define BONITO_SDCFG_BROWBITS           0x00000300
+#define BONITO_SDCFG_BROWBITS_SHIFT     8
+#define BONITO_SDCFG_BCOLBITS           0x00000c00
+#define BONITO_SDCFG_BCOLBITS_SHIFT     10
+#define BONITO_SDCFG_BBANKBIT           0x00001000
+#define BONITO_SDCFG_BSIDES             0x00002000
+#define BONITO_SDCFG_BABSENT            0x00004000
+#define BONITO_SDCFG_BWIDTH64           0x00008000
+
+#define BONITO_SDCFG_EXTRDDATA          0x00010000
+#define BONITO_SDCFG_EXTRASCAS          0x00020000
+#define BONITO_SDCFG_EXTPRECH           0x00040000
+#define BONITO_SDCFG_EXTRASWIDTH        0x00180000
+#define BONITO_SDCFG_EXTRASWIDTH_SHIFT  19
+/* Changed by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMMODESET        0x00200000
+/* --- */
+#define BONITO_SDCFG_DRAMEXTREGS        0x00400000
+#define BONITO_SDCFG_DRAMPARITY         0x00800000
+/* Added by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMBURSTLEN       0x03000000
+#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
+#define BONITO_SDCFG_DRAMMODESET_DONE   0x80000000
+/* --- */
+
+/* PCI Cache - pciCacheCtrl */
+
+#define BONITO_PCICACHECTRL_CACHECMD    0x00000007
+#define BONITO_PCICACHECTRL_CACHECMD_SHIFT      0
+#define BONITO_PCICACHECTRL_CACHECMDLINE        0x00000018
+#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT  3
+#define BONITO_PCICACHECTRL_CMDEXEC     0x00000020
+
+#define BONITO_PCICACHECTRL_IOBCCOH_PRES        0x00000100
+#define BONITO_PCICACHECTRL_IOBCCOH_EN  0x00000200
+#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
+#define BONITO_PCICACHECTRL_CPUCOH_EN   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_CS0     0x00000001
+#define BONITO_IODEVCFG_SPEEDBIT_CS0    0x00000002
+#define BONITO_IODEVCFG_MOREABITS_CS0   0x00000004
+
+#define BONITO_IODEVCFG_BUFFBIT_CS1     0x00000008
+#define BONITO_IODEVCFG_SPEEDBIT_CS1    0x00000010
+#define BONITO_IODEVCFG_MOREABITS_CS1   0x00000020
+
+#define BONITO_IODEVCFG_BUFFBIT_CS2     0x00000040
+#define BONITO_IODEVCFG_SPEEDBIT_CS2    0x00000080
+#define BONITO_IODEVCFG_MOREABITS_CS2   0x00000100
+
+#define BONITO_IODEVCFG_BUFFBIT_CS3     0x00000200
+#define BONITO_IODEVCFG_SPEEDBIT_CS3    0x00000400
+#define BONITO_IODEVCFG_MOREABITS_CS3   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_IDE     0x00001000
+#define BONITO_IODEVCFG_SPEEDBIT_IDE    0x00002000
+#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
+#define BONITO_IODEVCFG_MODEBIT_IDE     0x00008000
+#define BONITO_IODEVCFG_DMAON_IDE       0x001f0000
+#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
+#define BONITO_IODEVCFG_DMAOFF_IDE      0x01e00000
+#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT        21
+#define BONITO_IODEVCFG_EPROMSPLIT      0x02000000
+/* Added by RPF 11-9-00 */
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD  0xfc000000
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
+/* --- */
+
+/* gpio */
+#define BONITO_GPIO_GPIOW               0x000003ff
+#define BONITO_GPIO_GPIOW_SHIFT         0
+#define BONITO_GPIO_GPIOR               0x01ff0000
+#define BONITO_GPIO_GPIOR_SHIFT         16
+#define BONITO_GPIO_GPINR               0xfe000000
+#define BONITO_GPIO_GPINR_SHIFT         25
+#define BONITO_GPIO_IOW(N)              (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
+#define BONITO_GPIO_IOR(N)              (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
+#define BONITO_GPIO_INR(N)              (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
+
+/* ICU */
+#define BONITO_ICU_MBOXES               0x0000000f
+#define BONITO_ICU_MBOXES_SHIFT         0
+#define BONITO_ICU_DMARDY               0x00000010
+#define BONITO_ICU_DMAEMPTY             0x00000020
+#define BONITO_ICU_COPYRDY              0x00000040
+#define BONITO_ICU_COPYEMPTY            0x00000080
+#define BONITO_ICU_COPYERR              0x00000100
+#define BONITO_ICU_PCIIRQ               0x00000200
+#define BONITO_ICU_MASTERERR            0x00000400
+#define BONITO_ICU_SYSTEMERR            0x00000800
+#define BONITO_ICU_DRAMPERR             0x00001000
+#define BONITO_ICU_RETRYERR             0x00002000
+#define BONITO_ICU_GPIOS                0x01ff0000
+#define BONITO_ICU_GPIOS_SHIFT          16
+#define BONITO_ICU_GPINS                0x7e000000
+#define BONITO_ICU_GPINS_SHIFT          25
+#define BONITO_ICU_MBOX(N)              (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
+#define BONITO_ICU_GPIO(N)              (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
+#define BONITO_ICU_GPIN(N)              (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
+
+/* pcimap */
+
+#define BONITO_PCIMAP_PCIMAP_LO0        0x0000003f
+#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT  0
+#define BONITO_PCIMAP_PCIMAP_LO1        0x00000fc0
+#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT  6
+#define BONITO_PCIMAP_PCIMAP_LO2        0x0003f000
+#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT  12
+#define BONITO_PCIMAP_PCIMAP_2          0x00040000
+#define BONITO_PCIMAP_WIN(WIN,ADDR)     ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#define BONITO_PCIMAP_WINSIZE           (1<<26)
+#define BONITO_PCIMAP_WINOFFSET(ADDR)   ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
+#define BONITO_PCIMAP_WINBASE(ADDR)     ((ADDR) << 26)
+
+/* pcimembaseCfg */
+
+#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK      0x0000001f
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT        0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS     0x000003e0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT       5
+#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED    0x00000400
+#define BONITO_PCIMEMBASECFG_MEMBASE0_IO        0x00000800
+
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK      0x0001f000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT        12
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS     0x003e0000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT       17
+#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED    0x00400000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_IO        0x00800000
+
+#define BONITO_PCIMEMBASECFG_ASHIFT     23
+#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
+#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE)      (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
+#define BONITO_PCIMEMBASECFGBASE(WIN,BASE)      (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
+
+#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
+
+
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+
+#define BONITO_PCITOPHYS(WIN,ADDR,CFG)          ( \
+                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \
+                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \
+                                                )
+
+/* PCICmd */
+
+#define BONITO_PCICMD_MEMEN             0x00000002
+#define BONITO_PCICMD_MSTREN            0x00000004
+
+
+#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
new file mode 100644
index 000000000000..65d1d16eab16
--- /dev/null
+++ b/include/asm-mips/mips-boards/generic.h
@@ -0,0 +1,82 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Defines of the MIPS boards specific address-MAP, registers, etc.
+ */
+#ifndef __ASM_MIPS_BOARDS_GENERIC_H
+#define __ASM_MIPS_BOARDS_GENERIC_H
+
+#include <linux/config.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+#include <asm/mips-boards/bonito64.h>
+
+/*
+ * Display register base.
+ */
+#ifdef CONFIG_MIPS_SEAD
+#define ASCII_DISPLAY_POS_BASE     0x1f0005c0
+#else
+#define ASCII_DISPLAY_WORD_BASE    0x1f000410
+#define ASCII_DISPLAY_POS_BASE     0x1f000418
+#endif
+
+
+/*
+ * Yamon Prom print address.
+ */
+#define YAMON_PROM_PRINT_ADDR      0x1fc00504
+
+
+/*
+ * Reset register.
+ */
+#ifdef CONFIG_MIPS_SEAD
+#define SOFTRES_REG       0x1e800050
+#define GORESET           0x4d
+#else
+#define SOFTRES_REG       0x1f000500
+#define GORESET           0x42
+#endif
+
+/*
+ * Revision register.
+ */
+#define MIPS_REVISION_REG                  0x1fc00010
+#define MIPS_REVISION_CORID_QED_RM5261     0
+#define MIPS_REVISION_CORID_CORE_LV        1
+#define MIPS_REVISION_CORID_BONITO64       2
+#define MIPS_REVISION_CORID_CORE_20K       3
+#define MIPS_REVISION_CORID_CORE_FPGA      4
+#define MIPS_REVISION_CORID_CORE_MSC       5
+#define MIPS_REVISION_CORID_CORE_EMUL      6
+#define MIPS_REVISION_CORID_CORE_FPGA2     7
+#define MIPS_REVISION_CORID_CORE_FPGAR2    8
+
+/**** Artificial corid defines ****/
+/*
+ *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
+ *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
+ */
+#define MIPS_REVISION_CORID_CORE_EMUL_BON  0x63
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC  0x65
+
+#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
+
+extern unsigned int mips_revision_corid;
+
+#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
new file mode 100644
index 000000000000..b0ba3c5a921e
--- /dev/null
+++ b/include/asm-mips/mips-boards/malta.h
@@ -0,0 +1,75 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Defines of the Malta board specific address-MAP, registers, etc.
+ */
+#ifndef __ASM_MIPS_BOARDS_MALTA_H
+#define __ASM_MIPS_BOARDS_MALTA_H
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mips-boards/msc01_pci.h>
+#include <asm/gt64120.h>
+
+/*
+ * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
+ * Bonito system controllers.
+ */
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
+#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        addr = GT_READ(reg);
+        return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        MSC_READ(reg, addr);
+        return (unsigned long) ioremap(addr, 0x10000);
+}
+
+/*
+ * Malta RTC-device indirect register access.
+ */
+#define MALTA_RTC_ADR_REG       0x70
+#define MALTA_RTC_DAT_REG       0x71
+
+/*
+ * Malta SMSC FDC37M817 Super I/O Controller register.
+ */
+#define SMSC_CONFIG_REG         0x3f0
+#define SMSC_DATA_REG           0x3f1
+
+#define SMSC_CONFIG_DEVNUM      0x7
+#define SMSC_CONFIG_ACTIVATE    0x30
+#define SMSC_CONFIG_ENTER       0x55
+#define SMSC_CONFIG_EXIT        0xaa
+
+#define SMSC_CONFIG_DEVNUM_FLOPPY     0
+
+#define SMSC_CONFIG_ACTIVATE_ENABLE   1
+
+#define SMSC_WRITE(x,a)     outb(x,a)
+
+#define MALTA_JMPRS_REG         0x1f000210
+
+#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
new file mode 100644
index 000000000000..376181882e81
--- /dev/null
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -0,0 +1,33 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Malta interrupt controller.
+ *
+ */
+#ifndef _MIPS_MALTAINT_H
+#define _MIPS_MALTAINT_H
+
+/* Number of IRQ supported on hw interrupt 0. */
+#define MALTAINT_END      16
+
+extern void maltaint_init(void);
+
+#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
new file mode 100644
index 000000000000..6b2a87a38f4b
--- /dev/null
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -0,0 +1,256 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
+#define __ASM_MIPS_BOARDS_MSC01_PCI_H
+
+/*
+ * Register offset addresses
+ */
+
+#define MSC01_PCI_ID_OFS                0x0000
+#define MSC01_PCI_SC2PMBASL_OFS         0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS         0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS         0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS        0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS        0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS        0x0268
+#define MSC01_PCI_P2SCMSKL_OFS          0x0308
+#define MSC01_PCI_P2SCMAPL_OFS          0x0318
+#define MSC01_PCI_INTCFG_OFS            0x0600
+#define MSC01_PCI_INTSTAT_OFS           0x0608
+#define MSC01_PCI_CFGADDR_OFS           0x0610
+#define MSC01_PCI_CFGDATA_OFS           0x0618
+#define MSC01_PCI_IACK_OFS              0x0620
+#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
+#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_BAR0_OFS              0x2220
+#define MSC01_PCI_CFG_OFS               0x2380
+#define MSC01_PCI_SWAP_OFS              0x2388
+
+
+/*****************************************************************************
+ * Register encodings
+ ****************************************************************************/
+
+#define MSC01_PCI_ID_ID_SHF             16
+#define MSC01_PCI_ID_ID_MSK             0x00ff0000
+#define MSC01_PCI_ID_ID_HOSTBRIDGE      82
+#define MSC01_PCI_ID_MAR_SHF            8
+#define MSC01_PCI_ID_MAR_MSK            0x0000ff00
+#define MSC01_PCI_ID_MIR_SHF            0
+#define MSC01_PCI_ID_MIR_MSK            0x000000ff
+
+#define MSC01_PCI_SC2PMBASL_BAS_SHF     24
+#define MSC01_PCI_SC2PMBASL_BAS_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMSKL_MSK_SHF     24
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMAPL_MAP_SHF     24
+#define MSC01_PCI_SC2PMMAPL_MAP_MSK     0xff000000
+
+#define MSC01_PCI_SC2PIOBASL_BAS_SHF    24
+#define MSC01_PCI_SC2PIOBASL_BAS_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMSKL_MSK_SHF    24
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMAPL_MAP_SHF    24
+#define MSC01_PCI_SC2PIOMAPL_MAP_MSK    0xff000000
+
+#define MSC01_PCI_P2SCMSKL_MSK_SHF      24
+#define MSC01_PCI_P2SCMSKL_MSK_MSK      0xff000000
+
+#define MSC01_PCI_P2SCMAPL_MAP_SHF      24
+#define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
+
+#define MSC01_PCI_INTCFG_RST_SHF        10
+#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
+#define MSC01_PCI_INTCFG_MWE_SHF        9
+#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
+#define MSC01_PCI_INTCFG_DTO_SHF        8
+#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
+#define MSC01_PCI_INTCFG_MA_SHF         7
+#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
+#define MSC01_PCI_INTCFG_TA_SHF         6
+#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
+#define MSC01_PCI_INTCFG_RTY_SHF        5
+#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
+#define MSC01_PCI_INTCFG_MWP_SHF        4
+#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
+#define MSC01_PCI_INTCFG_MRP_SHF        3
+#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
+#define MSC01_PCI_INTCFG_SWP_SHF        2
+#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
+#define MSC01_PCI_INTCFG_SRP_SHF        1
+#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
+#define MSC01_PCI_INTCFG_SE_SHF         0
+#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
+
+#define MSC01_PCI_INTSTAT_RST_SHF       10
+#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
+#define MSC01_PCI_INTSTAT_MWE_SHF       9
+#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
+#define MSC01_PCI_INTSTAT_DTO_SHF       8
+#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
+#define MSC01_PCI_INTSTAT_MA_SHF        7
+#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
+#define MSC01_PCI_INTSTAT_TA_SHF        6
+#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
+#define MSC01_PCI_INTSTAT_RTY_SHF       5
+#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
+#define MSC01_PCI_INTSTAT_MWP_SHF       4
+#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
+#define MSC01_PCI_INTSTAT_MRP_SHF       3
+#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
+#define MSC01_PCI_INTSTAT_SWP_SHF       2
+#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
+#define MSC01_PCI_INTSTAT_SRP_SHF       1
+#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
+#define MSC01_PCI_INTSTAT_SE_SHF        0
+#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF      16
+#define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
+#define MSC01_PCI_CFGADDR_DNUM_SHF      11
+#define MSC01_PCI_CFGADDR_DNUM_MSK      0x0000f800
+#define MSC01_PCI_CFGADDR_FNUM_SHF      8
+#define MSC01_PCI_CFGADDR_FNUM_MSK      0x00000700
+#define MSC01_PCI_CFGADDR_RNUM_SHF      2
+#define MSC01_PCI_CFGADDR_RNUM_MSK      0x000000fc
+
+#define MSC01_PCI_CFGDATA_DATA_SHF      0
+#define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
+
+/* The defines below are ONLY valid for a MEM bar! */
+#define MSC01_PCI_BAR0_SIZE_SHF         4
+#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
+#define MSC01_PCI_BAR0_P_SHF            3
+#define MSC01_PCI_BAR0_P_MSK            0x00000008
+#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_D_SHF            1
+#define MSC01_PCI_BAR0_D_MSK            0x00000006
+#define MSC01_PCI_BAR0_T_SHF            0
+#define MSC01_PCI_BAR0_T_MSK            0x00000001
+#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
+
+
+#define MSC01_PCI_CFG_RA_SHF            17
+#define MSC01_PCI_CFG_RA_MSK            0x00020000
+#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_G_SHF             16
+#define MSC01_PCI_CFG_G_MSK             0x00010000
+#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_EN_SHF            15
+#define MSC01_PCI_CFG_EN_MSK            0x00008000
+#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_MAXRTRY_SHF       0
+#define MSC01_PCI_CFG_MAXRTRY_MSK       0x000000ff
+
+#define MSC01_PCI_SWAP_IO_SHF           18
+#define MSC01_PCI_SWAP_IO_MSK           0x000c0000
+#define MSC01_PCI_SWAP_MEM_SHF          16
+#define MSC01_PCI_SWAP_MEM_MSK          0x00030000
+#define MSC01_PCI_SWAP_BAR0_SHF         0
+#define MSC01_PCI_SWAP_BAR0_MSK         0x00000003
+#define MSC01_PCI_SWAP_NOSWAP           0
+#define MSC01_PCI_SWAP_BYTESWAP         1
+
+/*
+ * MIPS System controller PCI register base.
+ *
+ * FIXME - are these macros specific to Malta and co or to the MSC?  If the
+ * latter, they should be moved elsewhere.
+ */
+#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
+
+extern unsigned long _pcictrl_msc;
+
+#define MSC01_PCI_REG_BASE      _pcictrl_msc
+
+#define MSC_WRITE(reg, data)    do { *(volatile u32 *)(reg) = data; } while (0)
+#define MSC_READ(reg, data)     do { data = *(volatile u32 *)(reg); } while (0)
+
+/*
+ * Registers absolute addresses
+ */
+
+#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
+#define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
+#define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
+#define MSC01_PCI_HEAD2         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
+#define MSC01_PCI_HEAD3         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
+#define MSC01_PCI_HEAD4         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
+#define MSC01_PCI_HEAD5         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
+#define MSC01_PCI_HEAD6         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
+#define MSC01_PCI_HEAD7         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
+#define MSC01_PCI_HEAD8         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
+#define MSC01_PCI_HEAD9         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
+#define MSC01_PCI_HEAD10        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
+#define MSC01_PCI_HEAD11        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
+#define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
+#define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h
new file mode 100644
index 000000000000..2971d60f2e95
--- /dev/null
+++ b/include/asm-mips/mips-boards/piix4.h
@@ -0,0 +1,80 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Register definitions for Intel PIIX4 South Bridge Device.
+ */
+#ifndef __ASM_MIPS_BOARDS_PIIX4_H
+#define __ASM_MIPS_BOARDS_PIIX4_H
+
+/************************************************************************
+ *  IO register offsets
+ ************************************************************************/
+#define PIIX4_ICTLR1_ICW1       0x20
+#define PIIX4_ICTLR1_ICW2       0x21
+#define PIIX4_ICTLR1_ICW3       0x21
+#define PIIX4_ICTLR1_ICW4       0x21
+#define PIIX4_ICTLR2_ICW1       0xa0
+#define PIIX4_ICTLR2_ICW2       0xa1
+#define PIIX4_ICTLR2_ICW3       0xa1
+#define PIIX4_ICTLR2_ICW4       0xa1
+#define PIIX4_ICTLR1_OCW1       0x21
+#define PIIX4_ICTLR1_OCW2       0x20
+#define PIIX4_ICTLR1_OCW3       0x20
+#define PIIX4_ICTLR1_OCW4       0x20
+#define PIIX4_ICTLR2_OCW1       0xa1
+#define PIIX4_ICTLR2_OCW2       0xa0
+#define PIIX4_ICTLR2_OCW3       0xa0
+#define PIIX4_ICTLR2_OCW4       0xa0
+
+
+/************************************************************************
+ *  Register encodings.
+ ************************************************************************/
+#define PIIX4_OCW2_NSEOI        (0x1 << 5)
+#define PIIX4_OCW2_SEOI         (0x3 << 5)
+#define PIIX4_OCW2_RNSEOI       (0x5 << 5)
+#define PIIX4_OCW2_RAEOIS       (0x4 << 5)
+#define PIIX4_OCW2_RAEOIC       (0x0 << 5)
+#define PIIX4_OCW2_RSEOI        (0x7 << 5)
+#define PIIX4_OCW2_SP           (0x6 << 5)
+#define PIIX4_OCW2_NOP          (0x2 << 5)
+
+#define PIIX4_OCW2_SEL          (0x0 << 3)
+
+#define PIIX4_OCW2_ILS_0        0
+#define PIIX4_OCW2_ILS_1        1
+#define PIIX4_OCW2_ILS_2        2
+#define PIIX4_OCW2_ILS_3        3
+#define PIIX4_OCW2_ILS_4        4
+#define PIIX4_OCW2_ILS_5        5
+#define PIIX4_OCW2_ILS_6        6
+#define PIIX4_OCW2_ILS_7        7
+#define PIIX4_OCW2_ILS_8        0
+#define PIIX4_OCW2_ILS_9        1
+#define PIIX4_OCW2_ILS_10       2
+#define PIIX4_OCW2_ILS_11       3
+#define PIIX4_OCW2_ILS_12       4
+#define PIIX4_OCW2_ILS_13       5
+#define PIIX4_OCW2_ILS_14       6
+#define PIIX4_OCW2_ILS_15       7
+
+#define PIIX4_OCW3_SEL          (0x1 << 3)
+
+#define PIIX4_OCW3_IRR          0x2
+#define PIIX4_OCW3_ISR          0x3
+
+#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h
new file mode 100644
index 000000000000..4168c7fcd43e
--- /dev/null
+++ b/include/asm-mips/mips-boards/prom.h
@@ -0,0 +1,49 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ */
+
+#ifndef _MIPS_PROM_H
+#define _MIPS_PROM_H
+
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void setup_prom_printf(int tty_no);
+extern void prom_printf(char *fmt, ...);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+extern unsigned long prom_free_prom_memory (void);
+extern void mips_display_message(const char *str);
+extern void mips_display_word(unsigned int num);
+extern int get_ethernet_addr(char *ethernet_addr);
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    32
+struct prom_pmemblock {
+        unsigned long base; /* Within KSEG0. */
+        unsigned int size;  /* In bytes. */
+        unsigned int type;  /* free or prom memory */
+};
+
+#endif /* !(_MIPS_PROM_H) */
diff --git a/include/asm-mips/mips-boards/saa9730_uart.h b/include/asm-mips/mips-boards/saa9730_uart.h
new file mode 100644
index 000000000000..c913143d58ec
--- /dev/null
+++ b/include/asm-mips/mips-boards/saa9730_uart.h
@@ -0,0 +1,69 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for the UART part of the Philips SAA9730 chip.
+ *
+ */
+
+#ifndef SAA9730_UART_H
+#define SAA9730_UART_H
+
+/* The SAA9730 UART register map, as seen via the PCI bus */
+
+#define SAA9730_UART_REGS_ADDR  0x21800
+
+struct uart_saa9730_regmap {
+        volatile unsigned char Thr_Rbr;
+        volatile unsigned char Ier;
+        volatile unsigned char Iir_Fcr;
+        volatile unsigned char Lcr;
+        volatile unsigned char Mcr;
+        volatile unsigned char Lsr;
+        volatile unsigned char Msr;
+        volatile unsigned char Scr;
+        volatile unsigned char BaudDivLsb;
+        volatile unsigned char BaudDivMsb;
+        volatile unsigned char Junk0;
+        volatile unsigned char Junk1;
+        volatile unsigned int Config;           /* 0x2180c */
+        volatile unsigned int TxStart;          /* 0x21810 */
+        volatile unsigned int TxLength;         /* 0x21814 */
+        volatile unsigned int TxCounter;        /* 0x21818 */
+        volatile unsigned int RxStart;          /* 0x2181c */
+        volatile unsigned int RxLength;         /* 0x21820 */
+        volatile unsigned int RxCounter;        /* 0x21824 */
+};
+typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
+
+/*
+ * Only a subset of the UART control bits are defined here,
+ * enough to make the serial debug port work.
+ */
+
+#define SAA9730_LCR_DATA8       0x03
+
+#define SAA9730_MCR_DTR         0x01
+#define SAA9730_MCR_RTS         0x02
+
+#define SAA9730_LSR_DR          0x01
+#define SAA9730_LSR_THRE        0x20
+
+#endif /* !(SAA9730_UART_H) */
diff --git a/include/asm-mips/mips-boards/sead.h b/include/asm-mips/mips-boards/sead.h
new file mode 100644
index 000000000000..68c69de0b66f
--- /dev/null
+++ b/include/asm-mips/mips-boards/sead.h
@@ -0,0 +1,36 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the SEAD board specific address-MAP, registers, etc.
+ *
+ */
+#ifndef _MIPS_SEAD_H
+#define _MIPS_SEAD_H
+
+#include <asm/addrspace.h>
+
+/*
+ * SEAD UART register base.
+ */
+#define SEAD_UART0_REGS_BASE    (0x1f000800)
+#define SEAD_BASE_BAUD ( 3686400 / 16 )
+
+#endif /* !(_MIPS_SEAD_H) */
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
new file mode 100644
index 000000000000..c3dcfcb928b6
--- /dev/null
+++ b/include/asm-mips/mips-boards/seadint.h
@@ -0,0 +1,28 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Defines for the SEAD interrupt controller.
+ */
+#ifndef _MIPS_SEADINT_H
+#define _MIPS_SEADINT_H
+
+#define SEADINT_UART0     2
+#define SEADINT_UART1     3
+
+extern void seadint_init(void);
+
+#endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
new file mode 100644
index 000000000000..ce7cff7f1e8e
--- /dev/null
+++ b/include/asm-mips/mipsprom.h
@@ -0,0 +1,74 @@
+#ifndef __ASM_MIPS_PROM_H
+#define __ASM_MIPS_PROM_H
+
+#define PROM_RESET              0
+#define PROM_EXEC               1
+#define PROM_RESTART            2
+#define PROM_REINIT             3
+#define PROM_REBOOT             4
+#define PROM_AUTOBOOT           5
+#define PROM_OPEN               6
+#define PROM_READ               7
+#define PROM_WRITE              8
+#define PROM_IOCTL              9
+#define PROM_CLOSE              10
+#define PROM_GETCHAR            11
+#define PROM_PUTCHAR            12
+#define PROM_SHOWCHAR           13      /* XXX */
+#define PROM_GETS               14      /* XXX */
+#define PROM_PUTS               15      /* XXX */
+#define PROM_PRINTF             16      /* XXX */
+
+/* What are these for? */
+#define PROM_INITPROTO          17      /* XXX */
+#define PROM_PROTOENABLE        18      /* XXX */
+#define PROM_PROTODISABLE       19      /* XXX */
+#define PROM_GETPKT             20      /* XXX */
+#define PROM_PUTPKT             21      /* XXX */
+
+/* More PROM shit.  Probably has to do with VME RMW cycles??? */
+#define PROM_ORW_RMW            22      /* XXX */
+#define PROM_ORH_RMW            23      /* XXX */
+#define PROM_ORB_RMW            24      /* XXX */
+#define PROM_ANDW_RMW           25      /* XXX */
+#define PROM_ANDH_RMW           26      /* XXX */
+#define PROM_ANDB_RMW           27      /* XXX */
+
+/* Cache handling stuff */
+#define PROM_FLUSHCACHE         28      /* XXX */
+#define PROM_CLEARCACHE         29      /* XXX */
+
+/* Libc alike stuff */
+#define PROM_SETJMP             30      /* XXX */
+#define PROM_LONGJMP            31      /* XXX */
+#define PROM_BEVUTLB            32      /* XXX */
+#define PROM_GETENV             33      /* XXX */
+#define PROM_SETENV             34      /* XXX */
+#define PROM_ATOB               35      /* XXX */
+#define PROM_STRCMP             36      /* XXX */
+#define PROM_STRLEN             37      /* XXX */
+#define PROM_STRCPY             38      /* XXX */
+#define PROM_STRCAT             39      /* XXX */
+
+/* Misc stuff */
+#define PROM_PARSER             40      /* XXX */
+#define PROM_RANGE              41      /* XXX */
+#define PROM_ARGVIZE            42      /* XXX */
+#define PROM_HELP               43      /* XXX */
+
+/* Entry points for some PROM commands */
+#define PROM_DUMPCMD            44      /* XXX */
+#define PROM_SETENVCMD          45      /* XXX */
+#define PROM_UNSETENVCMD        46      /* XXX */
+#define PROM_PRINTENVCMD        47      /* XXX */
+#define PROM_BEVEXCEPT          48      /* XXX */
+#define PROM_ENABLECMD          49      /* XXX */
+#define PROM_DISABLECMD         50      /* XXX */
+
+#define PROM_CLEARNOFAULT       51      /* XXX */
+#define PROM_NOTIMPLEMENT       52      /* XXX */
+
+#define PROM_NV_GET             53      /* XXX */
+#define PROM_NV_SET             54      /* XXX */
+
+#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
new file mode 100644
index 000000000000..2197aa4ce456
--- /dev/null
+++ b/include/asm-mips/mipsregs.h
@@ -0,0 +1,1018 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2003  Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/hazards.h>
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE  $7
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   $0
+#define CP1_STATUS     $31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K           0x00000000
+#define PM_4K           0x00001800
+#define PM_16K          0x00007800
+#define PM_64K          0x0001f800
+#define PM_256K         0x0007f800
+
+#else
+
+#define PM_4K           0x00000000
+#define PM_16K          0x00006000
+#define PM_64K          0x0001e000
+#define PM_256K         0x0007e000
+#define PM_1M           0x001fe000
+#define PM_4M           0x007fe000
+#define PM_16M          0x01ffe000
+#define PM_64M          0x07ffe000
+#define PM_256M         0x1fffe000
+
+#endif
+
+/*
+ * Default page size for a given kernel configuration
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PM_DEFAULT_MASK PM_4K
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define PM_DEFAULT_MASK PM_16K
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define PM_DEFAULT_MASK PM_64K
+#else
+#error Bad page size configuration!
+#endif
+
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K           12
+#define PL_16K          14
+#define PL_64K          16
+#define PL_256K         18
+#define PL_1M           20
+#define PL_4M           22
+#define PL_16M          24
+#define PL_64M          26
+#define PL_256M         28
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (_ULCAST_(1) <<  8)
+#define IE_SW1          (_ULCAST_(1) <<  9)
+#define IE_IRQ0         (_ULCAST_(1) << 10)
+#define IE_IRQ1         (_ULCAST_(1) << 11)
+#define IE_IRQ2         (_ULCAST_(1) << 12)
+#define IE_IRQ3         (_ULCAST_(1) << 13)
+#define IE_IRQ4         (_ULCAST_(1) << 14)
+#define IE_IRQ5         (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (_ULCAST_(1) <<  8)
+#define C_SW1           (_ULCAST_(1) <<  9)
+#define C_IRQ0          (_ULCAST_(1) << 10)
+#define C_IRQ1          (_ULCAST_(1) << 11)
+#define C_IRQ2          (_ULCAST_(1) << 12)
+#define C_IRQ3          (_ULCAST_(1) << 13)
+#define C_IRQ4          (_ULCAST_(1) << 14)
+#define C_IRQ5          (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE                  0x00000001
+#define ST0_EXL                 0x00000002
+#define ST0_ERL                 0x00000004
+#define ST0_KSU                 0x00000018
+#  define KSU_USER              0x00000010
+#  define KSU_SUPERVISOR        0x00000008
+#  define KSU_KERNEL            0x00000000
+#define ST0_UX                  0x00000020
+#define ST0_SX                  0x00000040
+#define ST0_KX                  0x00000080
+#define ST0_DE                  0x00010000
+#define ST0_CE                  0x00020000
+
+/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO                  0x08000000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC                 0x00000002
+#define ST0_IEP                 0x00000004
+#define ST0_KUP                 0x00000008
+#define ST0_IEO                 0x00000010
+#define ST0_KUO                 0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC                 0x00010000
+#define ST0_SWC                 0x00020000
+#define ST0_CM                  0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM                  (_ULCAST_(1) <<  4)
+#define ST0_IL                  (_ULCAST_(1) << 23)
+#define ST0_DL                  (_ULCAST_(1) << 24)
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT     19
+#define TX39_CONF_ICS_MASK      0x00380000
+#define TX39_CONF_ICS_1KB       0x00000000
+#define TX39_CONF_ICS_2KB       0x00080000
+#define TX39_CONF_ICS_4KB       0x00100000
+#define TX39_CONF_ICS_8KB       0x00180000
+#define TX39_CONF_ICS_16KB      0x00200000
+
+#define TX39_CONF_DCS_SHIFT     16
+#define TX39_CONF_DCS_MASK      0x00070000
+#define TX39_CONF_DCS_1KB       0x00000000
+#define TX39_CONF_DCS_2KB       0x00010000
+#define TX39_CONF_DCS_4KB       0x00020000
+#define TX39_CONF_DCS_8KB       0x00030000
+#define TX39_CONF_DCS_16KB      0x00040000
+
+#define TX39_CONF_CWFON         0x00004000
+#define TX39_CONF_WBON          0x00002000
+#define TX39_CONF_RF_SHIFT      10
+#define TX39_CONF_RF_MASK       0x00000c00
+#define TX39_CONF_DOZE          0x00000200
+#define TX39_CONF_HALT          0x00000100
+#define TX39_CONF_LOCK          0x00000080
+#define TX39_CONF_ICE           0x00000020
+#define TX39_CONF_DCE           0x00000010
+#define TX39_CONF_IRSIZE_SHIFT  2
+#define TX39_CONF_IRSIZE_MASK   0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT  0
+#define TX39_CONF_DRSIZE_MASK   0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM                  0x0000ff00
+#define  STATUSB_IP0            8
+#define  STATUSF_IP0            (_ULCAST_(1) <<  8)
+#define  STATUSB_IP1            9
+#define  STATUSF_IP1            (_ULCAST_(1) <<  9)
+#define  STATUSB_IP2            10
+#define  STATUSF_IP2            (_ULCAST_(1) << 10)
+#define  STATUSB_IP3            11
+#define  STATUSF_IP3            (_ULCAST_(1) << 11)
+#define  STATUSB_IP4            12
+#define  STATUSF_IP4            (_ULCAST_(1) << 12)
+#define  STATUSB_IP5            13
+#define  STATUSF_IP5            (_ULCAST_(1) << 13)
+#define  STATUSB_IP6            14
+#define  STATUSF_IP6            (_ULCAST_(1) << 14)
+#define  STATUSB_IP7            15
+#define  STATUSF_IP7            (_ULCAST_(1) << 15)
+#define  STATUSB_IP8            0
+#define  STATUSF_IP8            (_ULCAST_(1) <<  0)
+#define  STATUSB_IP9            1
+#define  STATUSF_IP9            (_ULCAST_(1) <<  1)
+#define  STATUSB_IP10           2
+#define  STATUSF_IP10           (_ULCAST_(1) <<  2)
+#define  STATUSB_IP11           3
+#define  STATUSF_IP11           (_ULCAST_(1) <<  3)
+#define  STATUSB_IP12           4
+#define  STATUSF_IP12           (_ULCAST_(1) <<  4)
+#define  STATUSB_IP13           5
+#define  STATUSF_IP13           (_ULCAST_(1) <<  5)
+#define  STATUSB_IP14           6
+#define  STATUSF_IP14           (_ULCAST_(1) <<  6)
+#define  STATUSB_IP15           7
+#define  STATUSF_IP15           (_ULCAST_(1) <<  7)
+#define ST0_CH                  0x00040000
+#define ST0_SR                  0x00100000
+#define ST0_TS                  0x00200000
+#define ST0_BEV                 0x00400000
+#define ST0_RE                  0x02000000
+#define ST0_FR                  0x04000000
+#define ST0_CU                  0xf0000000
+#define ST0_CU0                 0x10000000
+#define ST0_CU1                 0x20000000
+#define ST0_CU2                 0x40000000
+#define ST0_CU3                 0x80000000
+#define ST0_XX                  0x80000000      /* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define  CAUSEB_EXCCODE         2
+#define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
+#define  CAUSEB_IP              8
+#define  CAUSEF_IP              (_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0             8
+#define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1             9
+#define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2             10
+#define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3             11
+#define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4             12
+#define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5             13
+#define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6             14
+#define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7             15
+#define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
+#define  CAUSEB_IV              23
+#define  CAUSEF_IV              (_ULCAST_(1)   << 23)
+#define  CAUSEB_CE              28
+#define  CAUSEF_CE              (_ULCAST_(3)   << 28)
+#define  CAUSEB_BD              31
+#define  CAUSEF_BD              (_ULCAST_(1)   << 31)
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA          0
+#define CONF_CM_CACHABLE_WA             1
+#define CONF_CM_UNCACHED                2
+#define CONF_CM_CACHABLE_NONCOHERENT    3
+#define CONF_CM_CACHABLE_CE             4
+#define CONF_CM_CACHABLE_COW            5
+#define CONF_CM_CACHABLE_CUW            6
+#define CONF_CM_CACHABLE_ACCELERATED    7
+#define CONF_CM_CMASK                   7
+#define CONF_BE                 (_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU                 (_ULCAST_(1) <<  3)
+#define CONF_DB                 (_ULCAST_(1) <<  4)
+#define CONF_IB                 (_ULCAST_(1) <<  5)
+#define CONF_DC                 (_ULCAST_(7) <<  6)
+#define CONF_IC                 (_ULCAST_(7) <<  9)
+#define CONF_EB                 (_ULCAST_(1) << 13)
+#define CONF_EM                 (_ULCAST_(1) << 14)
+#define CONF_SM                 (_ULCAST_(1) << 16)
+#define CONF_SC                 (_ULCAST_(1) << 17)
+#define CONF_EW                 (_ULCAST_(3) << 18)
+#define CONF_EP                 (_ULCAST_(15)<< 24)
+#define CONF_EC                 (_ULCAST_(7) << 28)
+#define CONF_CM                 (_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.  */
+#define R4K_CONF_SW             (_ULCAST_(1) << 20)
+#define R4K_CONF_SS             (_ULCAST_(1) << 21)
+#define R4K_CONF_SB             (_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.  */
+#define R5K_CONF_SE             (_ULCAST_(1) << 12)
+#define R5K_CONF_SS             (_ULCAST_(3) << 20)
+
+/* Bits specific to the R10000.  */
+#define R10K_CONF_DN            (_ULCAST_(3) <<  3)
+#define R10K_CONF_CT            (_ULCAST_(1) <<  5)
+#define R10K_CONF_PE            (_ULCAST_(1) <<  6)
+#define R10K_CONF_PM            (_ULCAST_(3) <<  7)
+#define R10K_CONF_EC            (_ULCAST_(15)<<  9)
+#define R10K_CONF_SB            (_ULCAST_(1) << 13)
+#define R10K_CONF_SK            (_ULCAST_(1) << 14)
+#define R10K_CONF_SS            (_ULCAST_(7) << 16)
+#define R10K_CONF_SC            (_ULCAST_(7) << 19)
+#define R10K_CONF_DC            (_ULCAST_(7) << 26)
+#define R10K_CONF_IC            (_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.  */
+#define VR41_CONF_CS            (_ULCAST_(1) << 12)
+#define VR41_CONF_M16           (_ULCAST_(1) << 20)
+#define VR41_CONF_AD            (_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.  */
+#define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV          (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC           (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF           (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB           (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC            (_ULCAST_(1) << 16)
+#define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT          (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.  */
+#define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
+#define MIPS_CONF_AR            (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT            (_ULCAST_(3) << 13)
+#define MIPS_CONF_M             (_ULCAST_(1) << 31)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ *        time accounting with a precission of one cycle.  I don't have
+ *        R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES                      0
+#define CE0_INSN_ISSUED                 1
+#define CE0_LPSC_ISSUED                 2
+#define CE0_S_ISSUED                    3
+#define CE0_SC_ISSUED                   4
+#define CE0_SC_FAILED                   5
+#define CE0_BRANCH_DECODED              6
+#define CE0_QW_WB_SECONDARY             7
+#define CE0_CORRECTED_ECC_ERRORS        8
+#define CE0_ICACHE_MISSES               9
+#define CE0_SCACHE_I_MISSES             10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED  11
+#define CE0_EXT_INTERVENTIONS_REQ       12
+#define CE0_EXT_INVALIDATE_REQ          13
+#define CE0_VIRTUAL_COHERENCY_COND      14
+#define CE0_INSN_GRADUATED              15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES                      0
+#define CE1_INSN_GRADUATED              1
+#define CE1_LPSC_GRADUATED              2
+#define CE1_S_GRADUATED                 3
+#define CE1_SC_GRADUATED                4
+#define CE1_FP_INSN_GRADUATED           5
+#define CE1_QW_WB_PRIMARY               6
+#define CE1_TLB_REFILL                  7
+#define CE1_BRANCH_MISSPREDICTED        8
+#define CE1_DCACHE_MISS                 9
+#define CE1_SCACHE_D_MISSES             10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED  11
+#define CE1_EXT_INTERVENTION_HITS       12
+#define CE1_EXT_INVALIDATE_REQ          13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
+
+/*
+ * These flags define in which privilege mode the counters count events
+ */
+#define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Functions to access the R10000 performance counters.  These are basically
+ * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
+ * performance counter number encoded into bits 1 ... 5 of the instruction.
+ * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
+ * disassembler these will look like an access to sel 0 or 1.
+ */
+#define read_r10k_perf_cntr(counter)                            \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfpc\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntr(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtpc\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+#define read_r10k_perf_event(counter)                           \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfps\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntl(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtps\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel)                           \
+({ int __res;                                                           \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        "mfc0\t%0, " #source "\n\t"                     \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mfc0\t%0, " #source ", " #sel "\n\t"           \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __read_64bit_c0_register(source, sel)                           \
+({ unsigned long long __res;                                            \
+        if (sizeof(unsigned long) == 4)                                 \
+                __res = __read_64bit_c0_split(source, sel);             \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips3\n\t"                               \
+                        "dmfc0\t%0, " #source "\n\t"                    \
+                        ".set\tmips0"                                   \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%0, " #source ", " #sel "\n\t"          \
+                        ".set\tmips0"                                   \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __write_32bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        "mtc0\t%z0, " #register "\n\t"                  \
+                        : : "Jr" ((unsigned int)value));                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
+                        ".set\tmips0"                                   \
+                        : : "Jr" ((unsigned int)value));                \
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_64bit_c0_split(register, sel, value);           \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips3\n\t"                               \
+                        "dmtc0\t%z0, " #register "\n\t"                 \
+                        ".set\tmips0"                                   \
+                        : : "Jr" (value));                              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
+                        ".set\tmips0"                                   \
+                        : : "Jr" (value));                              \
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)                              \
+        ((sizeof(unsigned long) == 4) ?                                 \
+        (unsigned long) __read_32bit_c0_register(reg, sel) :            \
+        (unsigned long) __read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val)                        \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_32bit_c0_register(reg, sel, val);               \
+        else                                                            \
+                __write_64bit_c0_register(reg, sel, val);               \
+} while (0)
+
+/*
+ * On RM7000/RM9000 these are uses to access cop0 set 1 registers
+ */
+#define __read_32bit_c0_ctrl_register(source)                           \
+({ int __res;                                                           \
+        __asm__ __volatile__(                                           \
+                "cfc0\t%0, " #source "\n\t"                             \
+                : "=r" (__res));                                        \
+        __res;                                                          \
+})
+
+#define __write_32bit_c0_ctrl_register(register, value)                 \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+                "ctc0\t%z0, " #register "\n\t"                          \
+                : : "Jr" ((unsigned int)value));                        \
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel.  That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel)                              \
+({                                                                      \
+        unsigned long long val;                                         \
+        unsigned long flags;                                            \
+                                                                        \
+        local_irq_save(flags);                                          \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%M0, " #source "\n\t"                   \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsrl\t%M0, %M0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0"                                   \
+                        : "=r" (val));                                  \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsrl\t%M0, %M0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0"                                   \
+                        : "=r" (val));                                  \
+        local_irq_restore(flags);                                       \
+                                                                        \
+        val;                                                            \
+})
+
+#define __write_64bit_c0_split(source, sel, val)                        \
+do {                                                                    \
+        unsigned long flags;                                            \
+                                                                        \
+        local_irq_save(flags);                                          \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source "\n\t"                   \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+        local_irq_restore(flags);                                       \
+} while (0)
+
+#define read_c0_index()         __read_32bit_c0_register($0, 0)
+#define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
+
+#define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf()          __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()       __read_ulong_c0_register($4, 0)
+#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
+
+#define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired()         __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()          __read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_count()         __read_32bit_c0_register($9, 0)
+#define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
+
+#define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare()       __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
+
+#define read_c0_status()        __read_32bit_c0_register($12, 0)
+#define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause()         __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()           __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid()          __read_32bit_c0_register($15, 0)
+
+#define read_c0_config()        __read_32bit_c0_register($16, 0)
+#define read_c0_config1()       __read_32bit_c0_register($16, 1)
+#define read_c0_config2()       __read_32bit_c0_register($16, 2)
+#define read_c0_config3()       __read_32bit_c0_register($16, 3)
+#define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
+
+/*
+ * The WatchLo register.  There may be upto 8 of them.
+ */
+#define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register.  There may be upto 8 of them.
+ */
+#define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask()     __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+/* RM9000 PerfControl performance counter control register */
+#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
+#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag()          __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag1()         __read_32bit_c0_register($22, 1)
+#define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_diag2()         __read_32bit_c0_register($22, 2)
+#define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_diag3()         __read_32bit_c0_register($22, 3)
+#define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_diag4()         __read_32bit_c0_register($22, 4)
+#define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_diag5()         __read_32bit_c0_register($22, 5)
+#define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_debug()         __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc()          __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+
+/* RM9000 PerfCount performance counter register */
+#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
+#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+
+#define read_c0_ecc()           __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo()         __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
+
+#define read_c0_taghi()         __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set\treorder\n\t"                                     \
+        "cfc1\t%0,"STR(source)"\n\t"                            \
+        ".set\tpop"                                             \
+        : "=r" (__res));                                        \
+        __res;})
+
+/*
+ * TLB operations.
+ *
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void tlb_probe(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbp\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbr\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_write_indexed(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwi\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwr\n\t"
+                ".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name)                                    \
+static inline unsigned int                                      \
+set_c0_##name(unsigned int set)                                 \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res |= set;                                             \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+clear_c0_##name(unsigned int clear)                             \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res &= ~clear;                                          \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+change_c0_##name(unsigned int change, unsigned int new)         \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res &= ~change;                                         \
+        res |= (new & change);                                  \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}
+
+__BUILD_SET_C0(status)
+__BUILD_SET_C0(cause)
+__BUILD_SET_C0(config)
+__BUILD_SET_C0(intcontrol)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/include/asm-mips/mman.h b/include/asm-mips/mman.h
new file mode 100644
index 000000000000..62060957ba93
--- /dev/null
+++ b/include/asm-mips/mman.h
@@ -0,0 +1,73 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+#define PROT_NONE       0x00            /* page can not be accessed */
+#define PROT_READ       0x01            /* page can be read */
+#define PROT_WRITE      0x02            /* page can be written */
+#define PROT_EXEC       0x04            /* page can be executed */
+/*                      0x08               reserved for PROT_EXEC_NOFLUSH */
+#define PROT_SEM        0x10            /* page may be used for atomic ops */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+/*
+ * Flags for mmap
+ */
+#define MAP_SHARED      0x001           /* Share changes */
+#define MAP_PRIVATE     0x002           /* Changes are private */
+#define MAP_TYPE        0x00f           /* Mask for type of mapping */
+#define MAP_FIXED       0x010           /* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME      0x020           /* Assign page to file */
+#define MAP_AUTOGROW    0x040           /* File may grow by writing */
+#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
+#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE   0x0400          /* don't check for reservations */
+#define MAP_ANONYMOUS   0x0800          /* don't use a file */
+#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
+#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
+#define MAP_LOCKED      0x8000          /* pages are locked */
+#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x20000         /* do not block on IO */
+
+/*
+ * Flags for msync
+ */
+#define MS_ASYNC        0x0001          /* sync memory asynchronously */
+#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
+#define MS_SYNC         0x0004          /* synchronous memory sync */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#define MADV_NORMAL     0x0             /* default page-in behavior */
+#define MADV_RANDOM     0x1             /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2             /* read-ahead aggressively */
+#define MADV_WILLNEED   0x3             /* pre-fault pages */
+#define MADV_DONTNEED   0x4             /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON       MAP_ANONYMOUS
+#define MAP_FILE       0
+
+#endif /* _ASM_MMAN_H */
diff --git a/include/asm-mips/mmu.h b/include/asm-mips/mmu.h
new file mode 100644
index 000000000000..4063edd79623
--- /dev/null
+++ b/include/asm-mips/mmu.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+typedef unsigned long mm_context_t[NR_CPUS];
+
+#endif /* __ASM_MMU_H */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
new file mode 100644
index 000000000000..48b77c9fb4f2
--- /dev/null
+++ b/include/asm-mips/mmu_context.h
@@ -0,0 +1,196 @@
+/*
+ * Switch a MMU context.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MMU_CONTEXT_H
+#define _ASM_MMU_CONTEXT_H
+
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+/*
+ * For the fast tlb miss handlers, we keep a per cpu array of pointers
+ * to the current pgd for each processor. Also, the proc. id is stuffed
+ * into the context register.
+ */
+extern unsigned long pgd_current[];
+
+#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
+        pgd_current[smp_processor_id()] = (unsigned long)(pgd)
+
+#ifdef CONFIG_MIPS32
+#define TLBMISS_HANDLER_SETUP()                                         \
+        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif
+#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#define TLBMISS_HANDLER_SETUP()                                         \
+        write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif
+#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#define TLBMISS_HANDLER_SETUP()                                         \
+        write_c0_context((unsigned long) smp_processor_id() << 23);     \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define ASID_INC        0x40
+#define ASID_MASK       0xfc0
+
+#elif defined(CONFIG_CPU_R8000)
+
+#define ASID_INC        0x10
+#define ASID_MASK       0xff0
+
+#elif defined(CONFIG_CPU_RM9000)
+
+#define ASID_INC        0x1
+#define ASID_MASK       0xfff
+
+#else /* FIXME: not correct for R6000 */
+
+#define ASID_INC        0x1
+#define ASID_MASK       0xff
+
+#endif
+
+#define cpu_context(cpu, mm)    ((mm)->context[cpu])
+#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
+#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ *  All unused by hardware upper bits will be considered
+ *  as a software asid extension.
+ */
+#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
+#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
+
+static inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
+{
+        unsigned long asid = asid_cache(cpu);
+
+        if (! ((asid += ASID_INC) & ASID_MASK) ) {
+                if (cpu_has_vtag_icache)
+                        flush_icache_all();
+                local_flush_tlb_all();  /* start new asid cycle */
+                if (!asid)              /* fix version if needed */
+                        asid = ASID_FIRST_VERSION;
+        }
+        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        int i;
+
+        for (i = 0; i < num_online_cpus(); i++)
+                cpu_context(i, mm) = 0;
+
+        return 0;
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        /* Check if our ASID is of an older version and thus invalid */
+        if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
+                get_new_mmu_context(next, cpu);
+
+        write_c0_entryhi(cpu_context(cpu, next));
+        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
+
+        /*
+         * Mark current->active_mm as not "active" anymore.
+         * We don't want to mislead possible IPI tlb flush routines.
+         */
+        cpu_clear(cpu, prev->cpu_vm_mask);
+        cpu_set(cpu, next->cpu_vm_mask);
+
+        local_irq_restore(flags);
+}
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void
+activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        unsigned long flags;
+        unsigned int cpu = smp_processor_id();
+
+        local_irq_save(flags);
+
+        /* Unconditionally get a new ASID.  */
+        get_new_mmu_context(next, cpu);
+
+        write_c0_entryhi(cpu_context(cpu, next));
+        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
+
+        /* mark mmu ownership change */
+        cpu_clear(cpu, prev->cpu_vm_mask);
+        cpu_set(cpu, next->cpu_vm_mask);
+
+        local_irq_restore(flags);
+}
+
+/*
+ * If mm is currently active_mm, we can't really drop it.  Instead,
+ * we will get a new one for it.
+ */
+static inline void
+drop_mmu_context(struct mm_struct *mm, unsigned cpu)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        if (cpu_isset(cpu, mm->cpu_vm_mask))  {
+                get_new_mmu_context(mm, cpu);
+                write_c0_entryhi(cpu_asid(cpu, mm));
+        } else {
+                /* will get a new context next time */
+                cpu_context(cpu, mm) = 0;
+        }
+
+        local_irq_restore(flags);
+}
+
+#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
new file mode 100644
index 000000000000..29ee13be0b2a
--- /dev/null
+++ b/include/asm-mips/mmzone.h
@@ -0,0 +1,39 @@
+/*
+ * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
+ * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004
+ */
+#ifndef _ASM_MMZONE_H_
+#define _ASM_MMZONE_H_
+
+#include <asm/page.h>
+#include <mmzone.h>
+
+#define kvaddr_to_nid(kvaddr)   pa_to_nid(__pa(kvaddr))
+#define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
+
+#define pfn_valid(pfn)                                          \
+({                                                              \
+        unsigned long __pfn = (pfn);                            \
+        int __n = pfn_to_nid(__pfn);                            \
+        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
+                       NODE_DATA(__n)->node_spanned_pages) : 0);\
+})
+
+#define pfn_to_page(pfn)                                        \
+({                                                              \
+        unsigned long __pfn = (pfn);                            \
+        pg_data_t *__pg = NODE_DATA(pfn_to_nid(__pfn));         \
+        __pg->node_mem_map + (__pfn - __pg->node_start_pfn);    \
+})
+
+#define page_to_pfn(p)                                          \
+({                                                              \
+        struct page *__p = (p);                                 \
+        struct zone *__z = page_zone(__p);                      \
+        ((__p - __z->zone_mem_map) + __z->zone_start_pfn);      \
+})
+
+/* XXX: FIXME -- wli */
+#define kern_addr_valid(addr)   (0)
+
+#endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
new file mode 100644
index 000000000000..90ee24aad955
--- /dev/null
+++ b/include/asm-mips/module.h
@@ -0,0 +1,56 @@
+#ifndef _ASM_MODULE_H
+#define _ASM_MODULE_H
+
+#include <linux/config.h>
+#include <linux/list.h>
+#include <asm/uaccess.h>
+
+struct mod_arch_specific {
+        /* Data Bus Error exception tables */
+        struct list_head dbe_list;
+        const struct exception_table_entry *dbe_start;
+        const struct exception_table_entry *dbe_end;
+};
+
+typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
+
+typedef struct
+{
+  Elf64_Addr r_offset;                  /* Address of relocation.  */
+  Elf64_Word r_sym;                     /* Symbol index.  */
+  Elf64_Byte r_ssym;                    /* Special symbol.  */
+  Elf64_Byte r_type3;                   /* Third relocation.  */
+  Elf64_Byte r_type2;                   /* Second relocation.  */
+  Elf64_Byte r_type;                    /* First relocation.  */
+  Elf64_Sxword r_addend;                /* Addend.  */
+} Elf64_Mips_Rela;
+
+#ifdef CONFIG_MIPS32
+
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+
+#endif
+
+#ifdef CONFIG_MIPS64
+
+#define Elf_Shdr        Elf64_Shdr
+#define Elf_Sym         Elf64_Sym
+#define Elf_Ehdr        Elf64_Ehdr
+
+#endif
+
+#ifdef CONFIG_MODULES
+/* Given an address, look for it in the exception tables. */
+const struct exception_table_entry*search_module_dbetables(unsigned long addr);
+#else
+/* Given an address, look for it in the exception tables. */
+static inline const struct exception_table_entry *
+search_module_dbetables(unsigned long addr)
+{
+        return NULL;
+}
+#endif
+
+#endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h
new file mode 100644
index 000000000000..64f17208d602
--- /dev/null
+++ b/include/asm-mips/msc01_ic.h
@@ -0,0 +1,151 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
+#define __ASM_MIPS_BOARDS_MSC01_IC_H
+
+/*****************************************************************************
+ * Register offset addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
+#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
+#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
+#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
+#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
+#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
+#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
+#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
+#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
+#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
+#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)         */
+#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
+#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
+#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
+#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
+#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
+#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
+#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
+#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
+#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
+#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
+#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
+#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
+#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
+#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
+#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
+
+/*****************************************************************************
+ * Register field encodings
+ *****************************************************************************/
+
+#define MSC01_IC_RST_RST_SHF      0
+#define MSC01_IC_RST_RST_MSK      0x00000001
+#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
+#define MSC01_IC_LVL_LVL_SHF      0
+#define MSC01_IC_LVL_LVL_MSK      0x000000ff
+#define MSC01_IC_LVL_SPUR_SHF     16
+#define MSC01_IC_LVL_SPUR_MSK     0x00010000
+#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
+#define MSC01_IC_RAMW_RIPL_SHF    0
+#define MSC01_IC_RAMW_RIPL_MSK    0x0000003f
+#define MSC01_IC_RAMW_DATA_SHF    6
+#define MSC01_IC_RAMW_DATA_MSK    0x00000fc0
+#define MSC01_IC_RAMW_ADDR_SHF    25
+#define MSC01_IC_RAMW_ADDR_MSK    0x7e000000
+#define MSC01_IC_RAMW_READ_SHF    31
+#define MSC01_IC_RAMW_READ_MSK    0x80000000
+#define MSC01_IC_RAMW_READ_BIT    MSC01_IC_RAMW_READ_MSK
+#define MSC01_IC_OSB_OSB_SHF      0
+#define MSC01_IC_OSB_OSB_MSK      0x000000ff
+#define MSC01_IC_OSA_OSA_SHF      0
+#define MSC01_IC_OSA_OSA_MSK      0x000000ff
+#define MSC01_IC_GENA_GENA_SHF    0
+#define MSC01_IC_GENA_GENA_MSK    0x00000001
+#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
+#define MSC01_IC_CFG_DIS_SHF      0
+#define MSC01_IC_CFG_DIS_MSK      0x00000001
+#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
+#define MSC01_IC_CFG_SHFT_SHF     8
+#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
+#define MSC01_IC_TCFG_ENA_SHF     0
+#define MSC01_IC_TCFG_ENA_MSK     0x00000001
+#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
+#define MSC01_IC_TCFG_INT_SHF     8
+#define MSC01_IC_TCFG_INT_MSK     0x00000100
+#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
+#define MSC01_IC_TCFG_EDGE_SHF    16
+#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
+#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
+#define MSC01_IC_SUP_PRI_SHF      0
+#define MSC01_IC_SUP_PRI_MSK      0x00000007
+#define MSC01_IC_SUP_EDGE_SHF     8
+#define MSC01_IC_SUP_EDGE_MSK     0x00000100
+#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
+#define MSC01_IC_SUP_STEP         8
+
+/*
+ * MIPS System controller interrupt register base.
+ *
+ * FIXME - are these macros specific to Malta and co or to the MSC?  If the
+ * latter, they should be moved elsewhere.
+ */
+#define MIPS_MSC01_IC_REG_BASE  0x1bc40000
+
+/*****************************************************************************
+ * Absolute register addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
+#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
+#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
+#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
+#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
+#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
+#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
+#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
+#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
+#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
+#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
+#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
+#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
+#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
+#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
+#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
+#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
+#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
+#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
+#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
+#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
+#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
+#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
+#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
+#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
+#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
+
+/*
+ * Soc-it interrupts are configurable.
+ * Every board describes its IRQ mapping with this table.
+ */
+typedef struct msc_irqmap {
+        int     im_irq;
+        int     im_type;
+        int     im_lvl;
+} msc_irqmap_t;
+
+/* im_type */
+#define MSC01_IRQ_LEVEL         0
+#define MSC01_IRQ_EDGE          1
+
+extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
+extern void ll_msc_irq(struct pt_regs *regs);
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
+
diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h
new file mode 100644
index 000000000000..513b2824838b
--- /dev/null
+++ b/include/asm-mips/msgbuf.h
@@ -0,0 +1,48 @@
+#ifndef _ASM_MSGBUF_H
+#define _ASM_MSGBUF_H
+
+#include <linux/config.h>
+
+/*
+ * The msqid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem
+ * - 2 miscellaneous unsigned long values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        __kernel_time_t msg_ctime;      /* last change time */
+#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _ASM_MSGBUF_H */
diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h
new file mode 100644
index 000000000000..c94d12d1f868
--- /dev/null
+++ b/include/asm-mips/namei.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_NAMEI_H
+#define _ASM_NAMEI_H
+
+#include <linux/personality.h>
+#include <linux/stddef.h>
+
+#define IRIX_EMUL       "/usr/gnemul/irix/"
+#define RISCOS_EMUL     "/usr/gnemul/riscos/"
+
+static inline char *__emul_prefix(void)
+{
+        switch (current->personality) {
+        case PER_IRIX32:
+        case PER_IRIXN32:
+        case PER_IRIX64:
+                return IRIX_EMUL;
+
+        case PER_RISCOS:
+                return RISCOS_EMUL;
+
+        default:
+                return NULL;
+        }
+}
+
+#endif /* _ASM_NAMEI_H */
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
new file mode 100644
index 000000000000..c3ca959aa4d9
--- /dev/null
+++ b/include/asm-mips/nile4.h
@@ -0,0 +1,310 @@
+/*
+ *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ *
+ *  This file is based on the following documentation:
+ *
+ *      NEC Vrc 5074 System Controller Data Sheet, June 1998
+ */
+
+#ifndef _ASM_NILE4_H
+#define _ASM_NILE4_H
+
+#define NILE4_BASE              0xbfa00000
+#define NILE4_SIZE              0x00200000              /* 2 MB */
+
+
+    /*
+     *  Physical Device Address Registers (PDARs)
+     */
+
+#define NILE4_SDRAM0    0x0000  /* SDRAM Bank 0 [R/W] */
+#define NILE4_SDRAM1    0x0008  /* SDRAM Bank 1 [R/W] */
+#define NILE4_DCS2      0x0010  /* Device Chip-Select 2 [R/W] */
+#define NILE4_DCS3      0x0018  /* Device Chip-Select 3 [R/W] */
+#define NILE4_DCS4      0x0020  /* Device Chip-Select 4 [R/W] */
+#define NILE4_DCS5      0x0028  /* Device Chip-Select 5 [R/W] */
+#define NILE4_DCS6      0x0030  /* Device Chip-Select 6 [R/W] */
+#define NILE4_DCS7      0x0038  /* Device Chip-Select 7 [R/W] */
+#define NILE4_DCS8      0x0040  /* Device Chip-Select 8 [R/W] */
+#define NILE4_PCIW0     0x0060  /* PCI Address Window 0 [R/W] */
+#define NILE4_PCIW1     0x0068  /* PCI Address Window 1 [R/W] */
+#define NILE4_INTCS     0x0070  /* Controller Internal Registers and Devices */
+                                /* [R/W] */
+#define NILE4_BOOTCS    0x0078  /* Boot ROM Chip-Select [R/W] */
+
+
+    /*
+     *  CPU Interface Registers
+     */
+
+#define NILE4_CPUSTAT   0x0080  /* CPU Status [R/W] */
+#define NILE4_INTCTRL   0x0088  /* Interrupt Control [R/W] */
+#define NILE4_INTSTAT0  0x0090  /* Interrupt Status 0 [R] */
+#define NILE4_INTSTAT1  0x0098  /* Interrupt Status 1 and CPU Interrupt */
+                                /* Enable [R/W] */
+#define NILE4_INTCLR    0x00A0  /* Interrupt Clear [R/W] */
+#define NILE4_INTPPES   0x00A8  /* PCI Interrupt Control [R/W] */
+
+
+    /*
+     *  Memory-Interface Registers
+     */
+
+#define NILE4_MEMCTRL   0x00C0  /* Memory Control */
+#define NILE4_ACSTIME   0x00C8  /* Memory Access Timing [R/W] */
+#define NILE4_CHKERR    0x00D0  /* Memory Check Error Status [R] */
+
+
+    /*
+     *  PCI-Bus Registers
+     */
+
+#define NILE4_PCICTRL   0x00E0  /* PCI Control [R/W] */
+#define NILE4_PCIARB    0x00E8  /* PCI Arbiter [R/W] */
+#define NILE4_PCIINIT0  0x00F0  /* PCI Master (Initiator) 0 [R/W] */
+#define NILE4_PCIINIT1  0x00F8  /* PCI Master (Initiator) 1 [R/W] */
+#define NILE4_PCIERR    0x00B8  /* PCI Error [R/W] */
+
+
+    /*
+     *  Local-Bus Registers
+     */
+
+#define NILE4_LCNFG     0x0100  /* Local Bus Configuration [R/W] */
+#define NILE4_LCST2     0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
+#define NILE4_LCST3     0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
+#define NILE4_LCST4     0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
+#define NILE4_LCST5     0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
+#define NILE4_LCST6     0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
+#define NILE4_LCST7     0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
+#define NILE4_LCST8     0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
+#define NILE4_DCSFN     0x0150  /* Device Chip-Select Muxing and Output */
+                                /* Enables [R/W] */
+#define NILE4_DCSIO     0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
+#define NILE4_BCST      0x0178  /* Local Boot Chip-Select Timing [R/W] */
+
+
+    /*
+     *  DMA Registers
+     */
+
+#define NILE4_DMACTRL0  0x0180  /* DMA Control 0 [R/W] */
+#define NILE4_DMASRCA0  0x0188  /* DMA Source Address 0 [R/W] */
+#define NILE4_DMADESA0  0x0190  /* DMA Destination Address 0 [R/W] */
+#define NILE4_DMACTRL1  0x0198  /* DMA Control 1 [R/W] */
+#define NILE4_DMASRCA1  0x01A0  /* DMA Source Address 1 [R/W] */
+#define NILE4_DMADESA1  0x01A8  /* DMA Destination Address 1 [R/W] */
+
+
+    /*
+     *  Timer Registers
+     */
+
+#define NILE4_T0CTRL    0x01C0  /* SDRAM Refresh Control [R/W] */
+#define NILE4_T0CNTR    0x01C8  /* SDRAM Refresh Counter [R/W] */
+#define NILE4_T1CTRL    0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
+#define NILE4_T1CNTR    0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
+#define NILE4_T2CTRL    0x01E0  /* General-Purpose Timer Control [R/W] */
+#define NILE4_T2CNTR    0x01E8  /* General-Purpose Timer Counter [R/W] */
+#define NILE4_T3CTRL    0x01F0  /* Watchdog Timer Control [R/W] */
+#define NILE4_T3CNTR    0x01F8  /* Watchdog Timer Counter [R/W] */
+
+
+    /*
+     *  PCI Configuration Space Registers
+     */
+
+#define NILE4_PCI_BASE  0x0200
+
+#define NILE4_VID       0x0200  /* PCI Vendor ID [R] */
+#define NILE4_DID       0x0202  /* PCI Device ID [R] */
+#define NILE4_PCICMD    0x0204  /* PCI Command [R/W] */
+#define NILE4_PCISTS    0x0206  /* PCI Status [R/W] */
+#define NILE4_REVID     0x0208  /* PCI Revision ID [R] */
+#define NILE4_CLASS     0x0209  /* PCI Class Code [R] */
+#define NILE4_CLSIZ     0x020C  /* PCI Cache Line Size [R/W] */
+#define NILE4_MLTIM     0x020D  /* PCI Latency Timer [R/W] */
+#define NILE4_HTYPE     0x020E  /* PCI Header Type [R] */
+#define NILE4_BIST      0x020F  /* BIST [R] (unimplemented) */
+#define NILE4_BARC      0x0210  /* PCI Base Address Register Control [R/W] */
+#define NILE4_BAR0      0x0218  /* PCI Base Address Register 0 [R/W] */
+#define NILE4_BAR1      0x0220  /* PCI Base Address Register 1 [R/W] */
+#define NILE4_CIS       0x0228  /* PCI Cardbus CIS Pointer [R] */
+                                /* (unimplemented) */
+#define NILE4_SSVID     0x022C  /* PCI Sub-System Vendor ID [R/W] */
+#define NILE4_SSID      0x022E  /* PCI Sub-System ID [R/W] */
+#define NILE4_ROM       0x0230  /* Expansion ROM Base Address [R] */
+                                /* (unimplemented) */
+#define NILE4_INTLIN    0x023C  /* PCI Interrupt Line [R/W] */
+#define NILE4_INTPIN    0x023D  /* PCI Interrupt Pin [R] */
+#define NILE4_MINGNT    0x023E  /* PCI Min_Gnt [R] (unimplemented) */
+#define NILE4_MAXLAT    0x023F  /* PCI Max_Lat [R] (unimplemented) */
+#define NILE4_BAR2      0x0240  /* PCI Base Address Register 2 [R/W] */
+#define NILE4_BAR3      0x0248  /* PCI Base Address Register 3 [R/W] */
+#define NILE4_BAR4      0x0250  /* PCI Base Address Register 4 [R/W] */
+#define NILE4_BAR5      0x0258  /* PCI Base Address Register 5 [R/W] */
+#define NILE4_BAR6      0x0260  /* PCI Base Address Register 6 [R/W] */
+#define NILE4_BAR7      0x0268  /* PCI Base Address Register 7 [R/W] */
+#define NILE4_BAR8      0x0270  /* PCI Base Address Register 8 [R/W] */
+#define NILE4_BARB      0x0278  /* PCI Base Address Register BOOT [R/W] */
+
+
+    /*
+     *  Serial-Port Registers
+     */
+
+#define NILE4_UART_BASE 0x0300
+
+#define NILE4_UARTRBR   0x0300  /* UART Receiver Data Buffer [R] */
+#define NILE4_UARTTHR   0x0300  /* UART Transmitter Data Holding [W] */
+#define NILE4_UARTIER   0x0308  /* UART Interrupt Enable [R/W] */
+#define NILE4_UARTDLL   0x0300  /* UART Divisor Latch LSB [R/W] */
+#define NILE4_UARTDLM   0x0308  /* UART Divisor Latch MSB [R/W] */
+#define NILE4_UARTIIR   0x0310  /* UART Interrupt ID [R] */
+#define NILE4_UARTFCR   0x0310  /* UART FIFO Control [W] */
+#define NILE4_UARTLCR   0x0318  /* UART Line Control [R/W] */
+#define NILE4_UARTMCR   0x0320  /* UART Modem Control [R/W] */
+#define NILE4_UARTLSR   0x0328  /* UART Line Status [R/W] */
+#define NILE4_UARTMSR   0x0330  /* UART Modem Status [R/W] */
+#define NILE4_UARTSCR   0x0338  /* UART Scratch [R/W] */
+
+#define NILE4_UART_BASE_BAUD    520833  /* 100 MHz / 12 / 16 */
+
+
+    /*
+     *  Interrupt Lines
+     */
+
+#define NILE4_INT_CPCE  0       /* CPU-Interface Parity-Error Interrupt */
+#define NILE4_INT_CNTD  1       /* CPU No-Target Decode Interrupt */
+#define NILE4_INT_MCE   2       /* Memory-Check Error Interrupt */
+#define NILE4_INT_DMA   3       /* DMA Controller Interrupt */
+#define NILE4_INT_UART  4       /* UART Interrupt */
+#define NILE4_INT_WDOG  5       /* Watchdog Timer Interrupt */
+#define NILE4_INT_GPT   6       /* General-Purpose Timer Interrupt */
+#define NILE4_INT_LBRTD 7       /* Local-Bus Ready Timer Interrupt */
+#define NILE4_INT_INTA  8       /* PCI Interrupt Signal INTA# */
+#define NILE4_INT_INTB  9       /* PCI Interrupt Signal INTB# */
+#define NILE4_INT_INTC  10      /* PCI Interrupt Signal INTC# */
+#define NILE4_INT_INTD  11      /* PCI Interrupt Signal INTD# */
+#define NILE4_INT_INTE  12      /* PCI Interrupt Signal INTE# (ISA cascade) */
+#define NILE4_INT_RESV  13      /* Reserved */
+#define NILE4_INT_PCIS  14      /* PCI SERR# Interrupt */
+#define NILE4_INT_PCIE  15      /* PCI Internal Error Interrupt */
+
+
+    /*
+     *  Nile 4 Register Access
+     */
+
+static inline void nile4_sync(void)
+{
+    volatile u32 *p = (volatile u32 *)0xbfc00000;
+    (void)(*p);
+}
+
+static inline void nile4_out32(u32 offset, u32 val)
+{
+    *(volatile u32 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u32 nile4_in32(u32 offset)
+{
+    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+static inline void nile4_out16(u32 offset, u16 val)
+{
+    *(volatile u16 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u16 nile4_in16(u32 offset)
+{
+    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+static inline void nile4_out8(u32 offset, u8 val)
+{
+    *(volatile u8 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u8 nile4_in8(u32 offset)
+{
+    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+
+    /*
+     *  Physical Device Address Registers
+     */
+
+extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+                           int on_memory_bus, int visible);
+
+
+    /*
+     *  PCI Master Registers
+     */
+
+#define NILE4_PCICMD_IACK       0       /* PCI Interrupt Acknowledge */
+#define NILE4_PCICMD_IO         1       /* PCI I/O Space */
+#define NILE4_PCICMD_MEM        3       /* PCI Memory Space */
+#define NILE4_PCICMD_CFG        5       /* PCI Configuration Space */
+
+
+    /*
+     *  PCI Address Spaces
+     *
+     *  Note that these are multiplexed using PCIINIT[01]!
+     */
+
+#define NILE4_PCI_IO_BASE       0xa6000000
+#define NILE4_PCI_MEM_BASE      0xa8000000
+#define NILE4_PCI_CFG_BASE      NILE4_PCI_MEM_BASE
+#define NILE4_PCI_IACK_BASE     NILE4_PCI_IO_BASE
+
+
+extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
+
+
+    /*
+     *  Interrupt Programming
+     */
+
+#define NUM_I8259_INTERRUPTS    16
+#define NUM_NILE4_INTERRUPTS    16
+
+#define IRQ_I8259_CASCADE       NILE4_INT_INTE
+#define is_i8259_irq(irq)       ((irq) < NUM_I8259_INTERRUPTS)
+#define nile4_to_irq(n)         ((n)+NUM_I8259_INTERRUPTS)
+#define irq_to_nile4(n)         ((n)-NUM_I8259_INTERRUPTS)
+
+extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+extern void nile4_map_irq_all(int cpu_irq);
+extern void nile4_enable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq_all(void);
+extern u16 nile4_get_irq_stat(int cpu_irq);
+extern void nile4_enable_irq_output(int cpu_irq);
+extern void nile4_disable_irq_output(int cpu_irq);
+extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+extern void nile4_clear_irq(int nile4_irq);
+extern void nile4_clear_irq_mask(u32 mask);
+extern u8 nile4_i8259_iack(void);
+extern void nile4_dump_irq_status(void);        /* Debug */
+
+#endif
+
diff --git a/include/asm-mips/numnodes.h b/include/asm-mips/numnodes.h
new file mode 100644
index 000000000000..4f00c16ceeb0
--- /dev/null
+++ b/include/asm-mips/numnodes.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_MAX_NUMNODES_H
+#define _ASM_MAX_NUMNODES_H
+
+/* Max 128 Nodes */
+#define NODES_SHIFT     6
+
+#endif /* _ASM_MAX_NUMNODES_H */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
new file mode 100644
index 000000000000..36cec9e31696
--- /dev/null
+++ b/include/asm-mips/paccess.h
@@ -0,0 +1,113 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Protected memory access.  Used for everything that might take revenge
+ * by sending a DBE error like accessing possibly non-existant memory or
+ * devices.
+ */
+#ifndef _ASM_PACCESS_H
+#define _ASM_PACCESS_H
+
+#include <linux/config.h>
+#include <linux/errno.h>
+
+#ifdef CONFIG_MIPS32
+#define __PA_ADDR       ".word"
+#endif
+#ifdef CONFIG_MIPS64
+#define __PA_ADDR       ".dword"
+#endif
+
+extern asmlinkage void handle_ibe(void);
+extern asmlinkage void handle_dbe(void);
+
+#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr)))
+#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr)))
+
+struct __large_pstruct { unsigned long buf[100]; };
+#define __mp(x) (*(struct __large_pstruct *)(x))
+
+#define __get_dbe(x,ptr,size)                                           \
+({                                                                      \
+        long __gu_err;                                                  \
+        __typeof(*(ptr)) __gu_val;                                      \
+        unsigned long __gu_addr;                                        \
+        __asm__("":"=r" (__gu_val));                                    \
+        __gu_addr = (unsigned long) (ptr);                              \
+        __asm__("":"=r" (__gu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __get_dbe_asm("lb"); break;                             \
+        case 2: __get_dbe_asm("lh"); break;                             \
+        case 4: __get_dbe_asm("lw"); break;                             \
+        case 8:  __get_dbe_asm("ld"); break;                            \
+        default: __get_dbe_unknown(); break;                            \
+        }                                                               \
+        x = (__typeof__(*(ptr))) __gu_val;                              \
+        __gu_err;                                                       \
+})
+
+#define __get_dbe_asm(insn)                                             \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "move\t%1,$0\n\t"                                               \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        :"=r" (__gu_err), "=r" (__gu_val)                               \
+        :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
+})
+
+extern void __get_dbe_unknown(void);
+
+#define __put_dbe(x,ptr,size)                                           \
+({                                                                      \
+        long __pu_err;                                                  \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        long __pu_addr;                                                 \
+        __pu_val = (x);                                                 \
+        __pu_addr = (long) (ptr);                                       \
+        __asm__("":"=r" (__pu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __put_dbe_asm("sb"); break;                             \
+        case 2: __put_dbe_asm("sh"); break;                             \
+        case 4: __put_dbe_asm("sw"); break;                             \
+        case 8: __put_dbe_asm("sd"); break;                             \
+        default: __put_dbe_unknown(); break;                            \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_dbe_asm(insn)                                             \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        : "=r" (__pu_err)                                               \
+        : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
+})
+
+extern void __put_dbe_unknown(void);
+
+extern unsigned long search_dbe_table(unsigned long addr);
+
+#endif /* _ASM_PACCESS_H */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
new file mode 100644
index 000000000000..d1bf8240e73b
--- /dev/null
+++ b/include/asm-mips/page.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PAGE_H
+#define _ASM_PAGE_H
+
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+
+#include <spaces.h>
+
+#endif
+
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT      12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT      13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT      14
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT      16
+#endif
+#define PAGE_SIZE       (1UL << PAGE_SHIFT)
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+extern void clear_page(void * page);
+extern void copy_page(void * to, void * from);
+
+extern unsigned long shm_align_mask;
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+        unsigned long addr2)
+{
+        return (addr1 ^ addr2) & shm_align_mask;
+}
+
+struct page;
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
+        struct page *page)
+{
+        extern void (*flush_data_cache_page)(unsigned long addr);
+
+        clear_page(addr);
+        if (pages_do_alias((unsigned long) addr, vaddr))
+                flush_data_cache_page((unsigned long)addr);
+}
+
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+        struct page *to)
+{
+        extern void (*flush_data_cache_page)(unsigned long addr);
+
+        copy_page(vto, vfrom);
+        if (pages_do_alias((unsigned long)vto, vaddr))
+                flush_data_cache_page((unsigned long)vto);
+}
+
+/*
+ * These are used to make use of C type-checking..
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+  #ifdef CONFIG_CPU_MIPS32
+    typedef struct { unsigned long pte_low, pte_high; } pte_t;
+    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+  #else
+     typedef struct { unsigned long long pte; } pte_t;
+     #define pte_val(x) ((x).pte)
+  #endif
+#else
+typedef struct { unsigned long pte; } pte_t;
+#define pte_val(x)      ((x).pte)
+#endif
+
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+/* Pure 2^n version of get_order */
+static __inline__ int get_order(unsigned long size)
+{
+        int order;
+
+        size = (size-1) >> (PAGE_SHIFT-1);
+        order = -1;
+        do {
+                size >>= 1;
+                order++;
+        } while (size);
+        return order;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
+
+#define __pa(x)                 ((unsigned long) (x) - PAGE_OFFSET)
+#define __va(x)                 ((void *)((unsigned long) (x) + PAGE_OFFSET))
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+
+#ifndef CONFIG_DISCONTIGMEM
+#define pfn_to_page(pfn)        (mem_map + (pfn))
+#define page_to_pfn(page)       ((unsigned long)((page) - mem_map))
+#define pfn_valid(pfn)          ((pfn) < max_mapnr)
+#endif
+
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + UNCAC_BASE)
+#define CAC_ADDR(addr)          ((addr) - UNCAC_BASE + PAGE_OFFSET)
+
+#endif /* defined (__KERNEL__) */
+
+#ifdef CONFIG_LIMITED_DMA
+#define WANT_PAGE_VIRTUAL
+#endif
+
+#endif /* _ASM_PAGE_H */
diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h
new file mode 100644
index 000000000000..2bead8273ced
--- /dev/null
+++ b/include/asm-mips/param.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PARAM_H
+#define _ASM_PARAM_H
+
+#ifdef __KERNEL__
+
+# include <param.h>                     /* Internal kernel timer frequency */
+# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   65536
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif /* _ASM_PARAM_H */
diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h
new file mode 100644
index 000000000000..a742e04e82de
--- /dev/null
+++ b/include/asm-mips/parport.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+#ifndef _ASM_PARPORT_H
+#define _ASM_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
+static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports (autoirq, autodma);
+}
+
+#endif /* _ASM_PARPORT_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
new file mode 100644
index 000000000000..c9c576b48556
--- /dev/null
+++ b/include/asm-mips/pci.h
@@ -0,0 +1,160 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_PCI_H
+#define _ASM_PCI_H
+
+#include <linux/config.h>
+#include <linux/mm.h>
+
+#ifdef __KERNEL__
+
+/*
+ * This file essentially defines the interface between board
+ * specific PCI code and MIPS common PCI code.  Should potentially put
+ * into include/asm/pci.h file.
+ */
+
+#include <linux/ioport.h>
+
+/*
+ * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
+ * multiple PCI channels may have multiple PCI host controllers or a
+ * single controller supporting multiple channels.
+ */
+struct pci_controller {
+        struct pci_controller *next;
+        struct pci_bus *bus;
+
+        struct pci_ops *pci_ops;
+        struct resource *mem_resource;
+        unsigned long mem_offset;
+        struct resource *io_resource;
+        unsigned long io_offset;
+
+        unsigned int index;
+        /* For compatibility with current (as of July 2003) pciutils
+           and XFree86. Eventually will be removed. */
+        unsigned int need_domain_info;
+
+        int iommu;
+};
+
+/*
+ * Used by boards to register their PCI busses before the actual scanning.
+ */
+extern struct pci_controller * alloc_pci_controller(void);
+extern void register_pci_controller(struct pci_controller *hose);
+
+/*
+ * board supplied pci irq fixup routine
+ */
+extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+extern unsigned int pcibios_assign_all_busses(void);
+
+#define pcibios_scan_all_fns(a, b)      0
+
+extern unsigned long PCIBIOS_MIN_IO;
+extern unsigned long PCIBIOS_MIN_MEM;
+
+#define PCIBIOS_MIN_CARDBUS_IO  0x4000
+
+extern void pcibios_set_master(struct pci_dev *dev);
+
+static inline void pcibios_penalize_isa_irq(int irq)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/*
+ * Dynamic DMA mapping stuff.
+ * MIPS has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+struct pci_dev;
+
+/*
+ * The PCI address space does equal the physical memory address space.  The
+ * networking and block device layers use this boolean for bounce buffer
+ * decisions.  This is set if any hose does not have an IOMMU.
+ */
+extern unsigned int PCI_DMA_BUS_IS_PHYS;
+
+#ifdef CONFIG_MAPPED_DMA_IO
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)          ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
+
+#else /* CONFIG_MAPPED_DMA_IO  */
+
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+#endif /* CONFIG_MAPPED_DMA_IO  */
+
+/* This is always fine. */
+#define pci_dac_dma_supported(pci_dev, mask)    (1)
+
+extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev,
+        struct page *page, unsigned long offset, int direction);
+extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev,
+        dma64_addr_t dma_addr);
+extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev,
+        dma64_addr_t dma_addr);
+extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev,
+        dma64_addr_t dma_addr, size_t len, int direction);
+extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
+        dma64_addr_t dma_addr, size_t len, int direction);
+
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+        struct pci_bus_region *region, struct resource *res);
+
+#ifdef CONFIG_PCI_DOMAINS
+
+#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+        return hose->need_domain_info;
+}
+
+#endif /* CONFIG_PCI_DOMAINS */
+
+#endif /* __KERNEL__ */
+
+/* implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+extern int pcibios_plat_dev_init(struct pci_dev *dev);
+
+#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
new file mode 100644
index 000000000000..b4ee995c56e6
--- /dev/null
+++ b/include/asm-mips/pci/bridge.h
@@ -0,0 +1,851 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
+ * revision 1.76.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_PCI_BRIDGE_H
+#define _ASM_PCI_BRIDGE_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <asm/xtalk/xwidget.h>          /* generic widget header */
+
+/* I/O page size */
+
+#define IOPFNSHIFT              12      /* 4K per mapped page */
+
+#define IOPGSIZE                (1 << IOPFNSHIFT)
+#define IOPG(x)                 ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
+
+/* Bridge RAM sizes */
+
+#define BRIDGE_ATE_RAM_SIZE     0x00000400      /* 1kB ATE RAM */
+
+#define BRIDGE_CONFIG_BASE      0x20000
+#define BRIDGE_CONFIG1_BASE     0x28000
+#define BRIDGE_CONFIG_END       0x30000
+#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
+
+#define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
+#define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
+#define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
+#define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
+
+/* ========================================================================
+ *    Bridge address map
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All accesses to bridge hardware registers must be done
+ * using 32-bit loads and stores.
+ */
+typedef u32     bridgereg_t;
+
+typedef u64     bridge_ate_t;
+
+/* pointers to bridge ATEs
+ * are always "pointer to volatile"
+ */
+typedef volatile bridge_ate_t  *bridge_ate_p;
+
+/*
+ * It is generally preferred that hardware registers on the bridge
+ * are located from C code via this structure.
+ *
+ * Generated from Bridge spec dated 04oct95
+ */
+
+typedef volatile struct bridge_s {
+        /* Local Registers                             0x000000-0x00FFFF */
+
+        /* standard widget configuration               0x000000-0x000057 */
+        widget_cfg_t        b_widget;                   /* 0x000000 */
+
+        /* helper fieldnames for accessing bridge widget */
+
+#define b_wid_id                        b_widget.w_id
+#define b_wid_stat                      b_widget.w_status
+#define b_wid_err_upper                 b_widget.w_err_upper_addr
+#define b_wid_err_lower                 b_widget.w_err_lower_addr
+#define b_wid_control                   b_widget.w_control
+#define b_wid_req_timeout               b_widget.w_req_timeout
+#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
+#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
+#define b_wid_err_cmdword               b_widget.w_err_cmd_word
+#define b_wid_llp                       b_widget.w_llp_cfg
+#define b_wid_tflush                    b_widget.w_tflush
+
+        /* bridge-specific widget configuration 0x000058-0x00007F */
+        bridgereg_t         _pad_000058;
+        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
+        bridgereg_t         _pad_000060;
+        bridgereg_t         b_wid_resp_upper;           /* 0x000064 */
+        bridgereg_t         _pad_000068;
+        bridgereg_t         b_wid_resp_lower;           /* 0x00006C */
+        bridgereg_t         _pad_000070;
+        bridgereg_t         b_wid_tst_pin_ctrl;         /* 0x000074 */
+        bridgereg_t     _pad_000078[2];
+
+        /* PMU & Map 0x000080-0x00008F */
+        bridgereg_t     _pad_000080;
+        bridgereg_t     b_dir_map;                      /* 0x000084 */
+        bridgereg_t     _pad_000088[2];
+
+        /* SSRAM 0x000090-0x00009F */
+        bridgereg_t     _pad_000090;
+        bridgereg_t     b_ram_perr;                     /* 0x000094 */
+        bridgereg_t     _pad_000098[2];
+
+        /* Arbitration 0x0000A0-0x0000AF */
+        bridgereg_t     _pad_0000A0;
+        bridgereg_t     b_arb;                          /* 0x0000A4 */
+        bridgereg_t     _pad_0000A8[2];
+
+        /* Number In A Can 0x0000B0-0x0000BF */
+        bridgereg_t     _pad_0000B0;
+        bridgereg_t     b_nic;                          /* 0x0000B4 */
+        bridgereg_t     _pad_0000B8[2];
+
+        /* PCI/GIO 0x0000C0-0x0000FF */
+        bridgereg_t     _pad_0000C0;
+        bridgereg_t     b_bus_timeout;                  /* 0x0000C4 */
+#define b_pci_bus_timeout b_bus_timeout
+
+        bridgereg_t     _pad_0000C8;
+        bridgereg_t     b_pci_cfg;                      /* 0x0000CC */
+        bridgereg_t     _pad_0000D0;
+        bridgereg_t     b_pci_err_upper;                /* 0x0000D4 */
+        bridgereg_t     _pad_0000D8;
+        bridgereg_t     b_pci_err_lower;                /* 0x0000DC */
+        bridgereg_t     _pad_0000E0[8];
+#define b_gio_err_lower b_pci_err_lower
+#define b_gio_err_upper b_pci_err_upper
+
+        /* Interrupt 0x000100-0x0001FF */
+        bridgereg_t     _pad_000100;
+        bridgereg_t     b_int_status;                   /* 0x000104 */
+        bridgereg_t     _pad_000108;
+        bridgereg_t     b_int_enable;                   /* 0x00010C */
+        bridgereg_t     _pad_000110;
+        bridgereg_t     b_int_rst_stat;                 /* 0x000114 */
+        bridgereg_t     _pad_000118;
+        bridgereg_t     b_int_mode;                     /* 0x00011C */
+        bridgereg_t     _pad_000120;
+        bridgereg_t     b_int_device;                   /* 0x000124 */
+        bridgereg_t     _pad_000128;
+        bridgereg_t     b_int_host_err;                 /* 0x00012C */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0001{30,,,68} */
+                bridgereg_t     addr;                   /* 0x0001{34,,,6C} */
+        } b_int_addr[8];                                /* 0x000130 */
+
+        bridgereg_t     _pad_000170[36];
+
+        /* Device 0x000200-0x0003FF */
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{00,,,38} */
+                bridgereg_t     reg;                    /* 0x0002{04,,,3C} */
+        } b_device[8];                                  /* 0x000200 */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{40,,,78} */
+                bridgereg_t     reg;                    /* 0x0002{44,,,7C} */
+        } b_wr_req_buf[8];                              /* 0x000240 */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
+                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
+        } b_rrb_map[2];                                 /* 0x000280 */
+#define b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
+#define b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
+
+        bridgereg_t     _pad_000290;
+        bridgereg_t     b_resp_status;                  /* 0x000294 */
+        bridgereg_t     _pad_000298;
+        bridgereg_t     b_resp_clear;                   /* 0x00029C */
+
+        bridgereg_t     _pad_0002A0[24];
+
+        char            _pad_000300[0x10000 - 0x000300];
+
+        /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
+        union {
+                bridge_ate_t    wr;                     /* write-only */
+                struct {
+                        bridgereg_t     _p_pad;
+                        bridgereg_t     rd;             /* read-only */
+                }                       hi;
+        }                           b_int_ate_ram[128];
+
+        char    _pad_010400[0x11000 - 0x010400];
+
+        /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
+        struct {
+                bridgereg_t     _p_pad;
+                bridgereg_t     rd;             /* read-only */
+        } b_int_ate_ram_lo[128];
+
+        char    _pad_011400[0x20000 - 0x011400];
+
+        /* PCI Device Configuration Spaces 0x020000-0x027FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+                union {
+                        u8      c[0x100 / 1];
+                        u16     s[0x100 / 2];
+                        u32     l[0x100 / 4];
+                        u64     d[0x100 / 8];
+                } f[8];
+        } b_type0_cfg_dev[8];                                   /* 0x020000 */
+
+    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+        } b_type1_cfg;                                  /* 0x028000-0x029000 */
+
+        char    _pad_029000[0x007000];                  /* 0x029000-0x030000 */
+
+        /* PCI Interrupt Acknowledge Cycle 0x030000 */
+        union {
+                u8      c[8 / 1];
+                u16     s[8 / 2];
+                u32     l[8 / 4];
+                u64     d[8 / 8];
+        } b_pci_iack;                                           /* 0x030000 */
+
+        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
+
+        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
+        bridge_ate_t    b_ext_ate_ram[0x10000];
+
+        /* Reserved 0x100000-0x1FFFFF */
+        char    _pad_100000[0x200000-0x100000];
+
+        /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x100000 / 1];
+                u16     s[0x100000 / 2];
+                u32     l[0x100000 / 4];
+                u64     d[0x100000 / 8];
+        } b_devio_raw[10];                              /* 0x200000 */
+
+        /* b_devio macro is a bit strange; it reflects the
+         * fact that the Bridge ASIC provides 2M for the
+         * first two DevIO windows and 1M for the other six.
+         */
+#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+        /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
+        union {         /* make all access sizes available. */
+                u8      c[0x400000 / 1];        /* read-only */
+                u16     s[0x400000 / 2];        /* read-write */
+                u32     l[0x400000 / 4];        /* read-only */
+                u64     d[0x400000 / 8];        /* read-only */
+        } b_external_flash;                     /* 0xC00000 */
+} bridge_t;
+
+/*
+ * Field formats for Error Command Word and Auxillary Error Command Word
+ * of bridge.
+ */
+typedef struct bridge_err_cmdword_s {
+        union {
+                u32             cmd_word;
+                struct {
+                        u32     didn:4,         /* Destination ID */
+                                sidn:4,         /* Source ID      */
+                                pactyp:4,       /* Packet type    */
+                                tnum:5,         /* Trans Number   */
+                                coh:1,          /* Coh Transacti  */
+                                ds:2,           /* Data size      */
+                                gbr:1,          /* GBR enable     */
+                                vbpm:1,         /* VBPM message   */
+                                error:1,        /* Error occurred  */
+                                barr:1,         /* Barrier op     */
+                                rsvd:8;
+                } berr_st;
+        } berr_un;
+} bridge_err_cmdword_t;
+
+#define berr_field      berr_un.berr_st
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The values of these macros can and should be crosschecked
+ * regularly against the offsets of the like-named fields
+ * within the "bridge_t" structure above.
+ */
+
+/* Byte offset macros for Bridge internal registers */
+
+#define BRIDGE_WID_ID           WIDGET_ID
+#define BRIDGE_WID_STAT         WIDGET_STATUS
+#define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
+#define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
+#define BRIDGE_WID_CONTROL      WIDGET_CONTROL
+#define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
+#define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
+#define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
+#define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
+#define BRIDGE_WID_LLP          WIDGET_LLP_CFG
+#define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
+
+#define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
+#define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
+#define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
+#define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
+
+#define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
+
+#define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
+
+#define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
+
+#define BRIDGE_NIC              0x0000B4        /* Number In A Can */
+
+#define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
+#define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
+#define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
+#define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
+#define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
+
+#define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
+#define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
+#define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
+#define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
+#define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
+#define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
+
+#define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
+#define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
+#define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
+
+#define BRIDGE_DEVICE0          0x000204        /* Device 0 */
+#define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
+#define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
+
+#define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
+#define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
+#define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
+
+#define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
+#define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
+
+#define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
+#define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
+
+/* Byte offset macros for Bridge I/O space */
+
+#define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
+
+#define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
+#define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
+#define BRIDGE_TYPE0_CFG_DEVF(s,f)      (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
+                                         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
+
+#define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
+
+#define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
+#define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
+
+/* Byte offset macros for Bridge device IO spaces */
+
+#define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
+#define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
+#define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
+#define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
+#define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
+
+#define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
+#define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
+
+#define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
+
+#define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
+
+/* ========================================================================
+ *    Bridge register bit field definitions
+ */
+
+/* Widget part number of bridge */
+#define BRIDGE_WIDGET_PART_NUM          0xc002
+#define XBRIDGE_WIDGET_PART_NUM         0xd002
+
+/* Manufacturer of bridge */
+#define BRIDGE_WIDGET_MFGR_NUM          0x036
+#define XBRIDGE_WIDGET_MFGR_NUM         0x024
+
+/* Revision numbers for known Bridge revisions */
+#define BRIDGE_REV_A                    0x1
+#define BRIDGE_REV_B                    0x2
+#define BRIDGE_REV_C                    0x3
+#define BRIDGE_REV_D                    0x4
+
+/* Bridge widget status register bits definition */
+
+#define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
+#define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
+#define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
+#define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
+#define BRIDGE_STAT_PENDING             (0x1F << 0)
+
+/* Bridge widget control register bits definition */
+#define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)
+#define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
+#define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
+#define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
+#define BRIDGE_CTRL_RST(n)              ((n) << 24)
+#define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
+#define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
+#define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
+#define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
+#define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
+#define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
+#define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
+#define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
+#define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
+#define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
+#define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
+#define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
+#define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
+#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
+#define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
+#define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
+#define BRIDGE_CTRL_SYS_END             (0x1 << 9)
+#define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
+#define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
+#define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
+#define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
+
+/* Bridge Response buffer Error Upper Register bit fields definition */
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+#define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
+
+#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
+                        (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
+                                BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+
+#define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
+                        (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
+                                 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+
+/* Bridge direct mapping register bits definition */
+#define BRIDGE_DIRMAP_W_ID_SHFT         20
+#define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
+#define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
+#define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
+#define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
+#define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
+
+/* Bridge Arbitration register bits definition */
+#define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
+#define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
+#define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
+#define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
+#define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
+#define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
+#define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
+#define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
+#define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
+#define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
+#define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
+
+/* Bridge Bus time-out register bits definition */
+#define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
+#define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
+#define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
+#define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
+#define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
+
+/* Bridge interrupt status register bits definition */
+#define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)
+#define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)
+#define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
+#define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
+#define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
+#define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
+#define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
+#define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
+#define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
+#define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
+#define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
+#define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
+#define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
+#define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
+#define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
+#define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
+#define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
+#define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
+#define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
+#define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
+#define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
+#define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
+#define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
+#define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
+#define BRIDGE_ISR_INT_MSK              (0xff << 0)
+#define BRIDGE_ISR_INT(x)               (0x1 << (x))
+
+#define BRIDGE_ISR_LINK_ERROR           \
+                (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
+                 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
+                 BRIDGE_ISR_LLP_TCTY)
+
+#define BRIDGE_ISR_PCIBUS_PIOERR        \
+                (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+
+#define BRIDGE_ISR_PCIBUS_ERROR         \
+                (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
+                 BRIDGE_ISR_PCI_PARITY)
+
+#define BRIDGE_ISR_XTALK_ERROR          \
+                (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
+                 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
+                 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
+                 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
+                 BRIDGE_ISR_UNEXP_RESP)
+
+#define BRIDGE_ISR_ERRORS               \
+                (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
+                 BRIDGE_ISR_PMU_ESIZE_FAULT)
+
+/*
+ * List of Errors which are fatal and kill the sytem
+ */
+#define BRIDGE_ISR_ERROR_FATAL          \
+                ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+
+#define BRIDGE_ISR_ERROR_DUMP           \
+                (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+
+/* Bridge interrupt enable register bits definition */
+#define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
+#define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
+#define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
+#define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
+#define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
+#define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
+#define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
+#define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
+#define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
+#define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
+#define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
+#define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
+#define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
+#define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
+#define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
+#define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
+#define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
+#define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
+#define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
+#define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
+#define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
+#define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
+#define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
+#define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
+#define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
+
+/* Bridge interrupt reset register bits definition */
+#define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
+#define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
+#define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
+#define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
+#define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
+#define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
+#define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_ALL_CLR              0x7f
+
+#define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
+                                         BRIDGE_ISR_XREQ_FIFO_OFLOW)
+#define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
+                                         BRIDGE_ISR_RESP_XTLK_ERR | \
+                                         BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+#define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
+                                         BRIDGE_ISR_BAD_XREQ_PKT | \
+                                         BRIDGE_ISR_REQ_XTLK_ERR | \
+                                         BRIDGE_ISR_INVLD_ADDR)
+#define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
+                                         BRIDGE_ISR_LLP_REC_CBERR | \
+                                         BRIDGE_ISR_LLP_RCTY | \
+                                         BRIDGE_ISR_LLP_TX_RETRY | \
+                                         BRIDGE_ISR_LLP_TCTY)
+#define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
+                                         BRIDGE_ISR_PMU_ESIZE_FAULT)
+#define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
+                                         BRIDGE_ISR_PCI_PARITY | \
+                                         BRIDGE_ISR_PCI_SERR | \
+                                         BRIDGE_ISR_PCI_PERR | \
+                                         BRIDGE_ISR_PCI_MST_TIMEOUT | \
+                                         BRIDGE_ISR_PCI_RETRY_CNT)
+
+#define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
+                                         BRIDGE_ISR_GIO_MST_TIMEOUT)
+
+/* Bridge INT_DEV register bits definition */
+#define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
+#define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
+#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
+
+/* Bridge interrupt(x) register bits definition */
+#define BRIDGE_INT_ADDR_HOST            0x0003FF00
+#define BRIDGE_INT_ADDR_FLD             0x000000FF
+
+#define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
+#define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
+#define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
+
+#define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
+
+/*
+ * The NASID should be shifted by this amount and stored into the
+ * interrupt(x) register.
+ */
+#define BRIDGE_INT_ADDR_NASID_SHFT      8
+
+/*
+ * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
+ * memory.
+ */
+#define BRIDGE_INT_ADDR_DEST_IO         (1 << 17)
+#define BRIDGE_INT_ADDR_DEST_MEM        0
+#define BRIDGE_INT_ADDR_MASK            (1 << 17)
+
+/* Bridge device(x) register bits definition */
+#define BRIDGE_DEV_ERR_LOCK_EN          0x10000000
+#define BRIDGE_DEV_PAGE_CHK_DIS         0x08000000
+#define BRIDGE_DEV_FORCE_PCI_PAR        0x04000000
+#define BRIDGE_DEV_VIRTUAL_EN           0x02000000
+#define BRIDGE_DEV_PMU_WRGA_EN          0x01000000
+#define BRIDGE_DEV_DIR_WRGA_EN          0x00800000
+#define BRIDGE_DEV_DEV_SIZE             0x00400000
+#define BRIDGE_DEV_RT                   0x00200000
+#define BRIDGE_DEV_SWAP_PMU             0x00100000
+#define BRIDGE_DEV_SWAP_DIR             0x00080000
+#define BRIDGE_DEV_PREF                 0x00040000
+#define BRIDGE_DEV_PRECISE              0x00020000
+#define BRIDGE_DEV_COH                  0x00010000
+#define BRIDGE_DEV_BARRIER              0x00008000
+#define BRIDGE_DEV_GBR                  0x00004000
+#define BRIDGE_DEV_DEV_SWAP             0x00002000
+#define BRIDGE_DEV_DEV_IO_MEM           0x00001000
+#define BRIDGE_DEV_OFF_MASK             0x00000fff
+#define BRIDGE_DEV_OFF_ADDR_SHFT        20
+
+#define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_PMU)
+#define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_PREF                | \
+                                         BRIDGE_DEV_PRECISE             | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+#define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+
+/* Bridge Error Upper register bit field definition */
+#define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
+#define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
+#define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
+#define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
+#define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
+
+/* Bridge interrupt mode register bits definition */
+#define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
+
+/* this should be written to the xbow's link_control(x) register */
+#define BRIDGE_CREDIT   3
+
+/* RRB assignment register */
+#define BRIDGE_RRB_EN   0x8     /* after shifting down */
+#define BRIDGE_RRB_DEV  0x7     /* after shifting down */
+#define BRIDGE_RRB_VDEV 0x4     /* after shifting down */
+#define BRIDGE_RRB_PDEV 0x3     /* after shifting down */
+
+/* RRB status register */
+#define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
+#define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
+
+/* RRB clear register */
+#define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
+
+/* xbox system controller declarations */
+#define XBOX_BRIDGE_WID         8
+#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
+#define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
+#define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
+
+/* ========================================================================
+ */
+/*
+ * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
+ * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
+ */
+/* XTALK addresses that map into Bridge Bus addr space */
+#define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
+#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
+#define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
+#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
+#define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
+#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
+
+/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
+#define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
+#define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
+#define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
+#define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
+
+/* XTALK addresses that map into PCI addresses */
+#define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
+
+/*
+ * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
+ */
+/* Bridge Bus DMA addresses */
+#define BRIDGE_LOCAL_BASE               0
+#define BRIDGE_DMA_MAPPED_BASE          0x40000000
+#define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
+#define BRIDGE_DMA_DIRECT_BASE          0x80000000
+#define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
+
+#define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
+
+/* PCI addresses of regions decoded by Bridge for DMA */
+#define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
+#define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
+
+#define IS_PCI32_LOCAL(x)       ((ulong_t)(x) < PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)      ((ulong_t)(x) < PCI32_DIRECT_BASE && \
+                                        (ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)      ((ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI64(x)             ((ulong_t)(x) >= PCI64_BASE)
+
+/*
+ * The GIO address space.
+ */
+/* Xtalk to GIO PIO */
+#define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+
+#define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
+
+/* GIO addresses of regions decoded by Bridge for DMA */
+#define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
+#define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
+
+#define IS_GIO_LOCAL(x)         ((ulong_t)(x) < GIO_MAPPED_BASE)
+#define IS_GIO_MAPPED(x)        ((ulong_t)(x) < GIO_DIRECT_BASE && \
+                                        (ulong_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_DIRECT(x)        ((ulong_t)(x) >= GIO_MAPPED_BASE)
+
+/* PCI to xtalk mapping */
+
+/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
+ * which xtalk address is accessed
+ */
+#define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
+#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
+        ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
+                ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
+
+/* 64-bit address attribute masks */
+#define PCI64_ATTR_TARG_MASK    0xf000000000000000
+#define PCI64_ATTR_TARG_SHFT    60
+#define PCI64_ATTR_PREF         0x0800000000000000
+#define PCI64_ATTR_PREC         0x0400000000000000
+#define PCI64_ATTR_VIRTUAL      0x0200000000000000
+#define PCI64_ATTR_BAR          0x0100000000000000
+#define PCI64_ATTR_RMF_MASK     0x00ff000000000000
+#define PCI64_ATTR_RMF_SHFT     48
+
+#ifndef __ASSEMBLY__
+/* Address translation entry for mapped pci32 accesses */
+typedef union ate_u {
+        u64     ent;
+        struct ate_s {
+                u64     rmf:16;
+                u64     addr:36;
+                u64     targ:4;
+                u64     reserved:3;
+                u64     barrier:1;
+                u64     prefetch:1;
+                u64     precise:1;
+                u64     coherent:1;
+                u64     valid:1;
+        } field;
+} ate_t;
+#endif /* !__ASSEMBLY__ */
+
+#define ATE_V           0x01
+#define ATE_CO          0x02
+#define ATE_PREC        0x04
+#define ATE_PREF        0x08
+#define ATE_BAR         0x10
+
+#define ATE_PFNSHIFT            12
+#define ATE_TIDSHIFT            8
+#define ATE_RMFSHIFT            48
+
+#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
+                                ((xid)<<ATE_TIDSHIFT) | \
+                                (attr)
+
+#define BRIDGE_INTERNAL_ATES    128
+
+struct bridge_controller {
+        struct pci_controller   pc;
+        struct resource         mem;
+        struct resource         io;
+        bridge_t                *base;
+        nasid_t                 nasid;
+        unsigned int            widget_id;
+        unsigned int            irq_cpu;
+        dma64_addr_t            baddr;
+        unsigned int            pci_int[8];
+};
+
+#define BRIDGE_CONTROLLER(bus) \
+        ((struct bridge_controller *)((bus)->sysdata))
+
+extern void register_bridge_irq(unsigned int irq);
+extern int request_bridge_irq(struct bridge_controller *bc);
+
+#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/include/asm-mips/percpu.h b/include/asm-mips/percpu.h
new file mode 100644
index 000000000000..844e763e9332
--- /dev/null
+++ b/include/asm-mips/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_PERCPU_H
+#define __ASM_PERCPU_H
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ASM_PERCPU_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
new file mode 100644
index 000000000000..2d63f5ba403f
--- /dev/null
+++ b/include/asm-mips/pgalloc.h
@@ -0,0 +1,125 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGALLOC_H
+#define _ASM_PGALLOC_H
+
+#include <linux/config.h>
+#include <linux/highmem.h>
+#include <linux/mm.h>
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+        pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+        struct page *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        pgd_t *ret, *init;
+
+        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
+        if (ret) {
+                init = pgd_offset(&init_mm, 0);
+                pgd_init((unsigned long)ret);
+                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+        }
+
+        return ret;
+}
+
+static inline void pgd_free(pgd_t *pgd)
+{
+        free_pages((unsigned long)pgd, PGD_ORDER);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+        unsigned long address)
+{
+        pte_t *pte;
+
+        pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, PTE_ORDER);
+
+        return pte;
+}
+
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
+        unsigned long address)
+{
+        struct page *pte;
+
+        pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
+        if (pte)
+                clear_highpage(pte);
+
+        return pte;
+}
+
+static inline void pte_free_kernel(pte_t *pte)
+{
+        free_pages((unsigned long)pte, PTE_ORDER);
+}
+
+static inline void pte_free(struct page *pte)
+{
+        __free_pages(pte, PTE_ORDER);
+}
+
+#define __pte_free_tlb(tlb,pte)         tlb_remove_page((tlb),(pte))
+
+#ifdef CONFIG_MIPS32
+#define pgd_populate(mm, pmd, pte)      BUG()
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+#define pmd_alloc_one(mm, addr)         ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(x)                     do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS64
+
+#define pgd_populate(mm, pgd, pmd)      set_pgd(pgd, __pgd(pmd))
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        pmd_t *pmd;
+
+        pmd = (pmd_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PMD_ORDER);
+        if (pmd)
+                pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table);
+        return pmd;
+}
+
+static inline void pmd_free(pmd_t *pmd)
+{
+        free_pages((unsigned long)pmd, PMD_ORDER);
+}
+
+#define __pmd_free_tlb(tlb,x)   pmd_free(x)
+
+#endif
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _ASM_PGALLOC_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
new file mode 100644
index 000000000000..41a0df7d7768
--- /dev/null
+++ b/include/asm-mips/pgtable-32.h
@@ -0,0 +1,243 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_32_H
+#define _ASM_PGTABLE_32_H
+
+#include <linux/config.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+
+#include <linux/linkage.h>
+#include <asm/cachectl.h>
+#include <asm/fixmap.h>
+
+/*
+ * - add_wired_entry() add a fixed TLB entry, and move wired register
+ */
+extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *      starting at the top and working down. This is for populating the
+ *      TLB before trap_init() puts the TLB miss handler in place. It
+ *      should be used only for entries matching the actual page tables,
+ *      to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+
+/* Basically we have the same two-level (which is the logical three level
+ * Linux page table layout folded) page tables as the i386.  Some day
+ * when we have proper page coloring support we can have a 1% quicker
+ * tlb refill handling mechanism, but for now it is a bit slower but
+ * works even with the cache aliasing problem the R4k and above have.
+ */
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+#define PMD_SHIFT       21
+#else
+#define PMD_SHIFT       22
+#endif
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     PMD_SHIFT
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * Entries per page directory level: we use two-level, so
+ * we don't really have any PMD directory physically.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+#define PGD_ORDER       1
+#define PMD_ORDER       0
+#define PTE_ORDER       0
+#else
+#define PGD_ORDER       0
+#define PMD_ORDER       0
+#define PTE_ORDER       0
+#endif
+
+#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#define PTRS_PER_PMD    1
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+#define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
+#define FIRST_USER_PGD_NR       0
+
+#define VMALLOC_START     KSEG2
+
+#ifdef CONFIG_HIGHMEM
+# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
+#else
+# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
+#endif
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#else
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern void load_pgd(unsigned long pg_dir);
+
+extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+static inline int pgd_none(pgd_t pgd)           { return 0; }
+static inline int pgd_bad(pgd_t pgd)            { return 0; }
+static inline int pgd_present(pgd_t pgd)        { return 1; }
+static inline void pgd_clear(pgd_t *pgdp)       { }
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
+static inline pte_t
+pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+        pte_t pte;
+        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
+        pte.pte_low = pgprot_val(prot);
+        return pte;
+}
+
+#else
+
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#endif
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+
+#define __pgd_offset(address)   pgd_index(address)
+#define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
+{
+        return (pmd_t *) dir;
+}
+
+/* Find an entry in the third-level page table.. */
+#define __pte_offset(address)                                           \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset(dir, address)                                        \
+        ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address))
+#define pte_offset_kernel(dir, address) \
+        ((pte_t *) pmd_page_kernel(*(dir)) +  __pte_offset(address))
+
+#define pte_offset_map(dir, address)                                    \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_offset_map_nested(dir, address)                             \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_unmap(pte) ((void)(pte))
+#define pte_unmap_nested(pte) ((void)(pte))
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/* Swap entries must have VALID bit cleared. */
+#define __swp_type(x)           (((x).val >> 10) & 0x1f)
+#define __swp_offset(x)         ((x).val >> 15)
+#define __swp_entry(type,offset)        \
+        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
+
+/*
+ * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
+ * into this range:
+ */
+#define PTE_FILE_MAX_BITS       27
+
+#define pte_to_pgoff(_pte) \
+        ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
+
+#define pgoff_to_pte(off) \
+        ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
+
+#else
+
+/* Swap entries must have VALID and GLOBAL bits cleared. */
+#define __swp_type(x)           (((x).val >> 8) & 0x1f)
+#define __swp_offset(x)         ((x).val >> 13)
+#define __swp_entry(type,offset)        \
+                ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+
+/*
+ * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
+ * into this range:
+ */
+#define PTE_FILE_MAX_BITS       27
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+        /* fixme */
+#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
+#define pgoff_to_pte(off) \
+        ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
+
+#else
+#define pte_to_pgoff(_pte) \
+        ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
+
+#define pgoff_to_pte(off) \
+        ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
+#endif
+
+#endif
+
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+#endif /* _ASM_PGTABLE_32_H */
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
new file mode 100644
index 000000000000..704b551f59e9
--- /dev/null
+++ b/include/asm-mips/pgtable-64.h
@@ -0,0 +1,227 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_64_H
+#define _ASM_PGTABLE_64_H
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cachectl.h>
+
+/*
+ * Each address space has 2 4K pages as its page directory, giving 1024
+ * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
+ * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to
+ * page tables. Each page table is a single 4K page, giving 512 (==
+ * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to
+ * invalid_pmd_table, each pmde is initialized to point to
+ * invalid_pte_table, each pte is initialized to 0. When memory is low,
+ * and a pmd table or a page table allocation fails, empty_bad_pmd_table
+ * and empty_bad_page_table is returned back to higher layer code, so
+ * that the failure is recognized later on. Linux does not seem to
+ * handle these failures very well though. The empty_bad_page_table has
+ * invalid pte entries in it, to force page faults.
+ *
+ * Kernel mappings: kernel mappings are held in the swapper_pg_table.
+ * The layout is identical to userspace except it's indexed with the
+ * fault address - VMALLOC_START.
+ */
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT - 3))
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + 1 - 3))
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which
+ * permits us mapping 40 bits of virtual address space.
+ *
+ * We used to implement 41 bits by having an order 1 pmd level but that seemed
+ * rather pointless.
+ *
+ * For 8kB page size we use a 3 level page tree which permits a total of
+ * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
+ * two levels would be easy to implement.
+ *
+ * For 16kB page size we use a 2 level page tree which permits a total of
+ * 36 bits of virtual address space.  We could add a third leve. but it seems
+ * like at the moment there's no need for this.
+ *
+ * For 64kB page size we use a 2 level page table tree for a total of 42 bits
+ * of virtual address space.
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PGD_ORDER               1
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PGD_ORDER               0
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PGD_ORDER               0
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PGD_ORDER               0
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+
+#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_PGD_NR       0
+
+#define VMALLOC_START           XKSEG
+#define VMALLOC_END     \
+        (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
+extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
+extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
+
+/*
+ * Empty pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+/*
+ * Empty pgd entries point to the invalid_pmd_table.
+ */
+static inline int pgd_none(pgd_t pgd)
+{
+        return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
+}
+
+#define pgd_bad(pgd)            (pgd_val(pgd) &~ PAGE_MASK)
+
+static inline int pgd_present(pgd_t pgd)
+{
+        return pgd_val(pgd) != (unsigned long) invalid_pmd_table;
+}
+
+static inline void pgd_clear(pgd_t *pgdp)
+{
+        pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
+}
+
+#define pte_page(x)             pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT)))
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#endif
+
+#define __pgd_offset(address)   pgd_index(address)
+#define page_pte(page) page_pte_prot(page, __pgprot(0))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, 0)
+
+#define pgd_index(address)              ((address) >> PGDIR_SHIFT)
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm,addr)     ((mm)->pgd + pgd_index(addr))
+
+static inline unsigned long pgd_page(pgd_t pgd)
+{
+        return pgd_val(pgd);
+}
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
+{
+        return (pmd_t *) pgd_page(*dir) +
+               ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
+}
+
+/* Find an entry in the third-level page table.. */
+#define __pte_offset(address)                                           \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset(dir, address)                                        \
+        ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address))
+#define pte_offset_kernel(dir, address)                                 \
+        ((pte_t *) pmd_page_kernel(*(dir)) +  __pte_offset(address))
+#define pte_offset_map(dir, address)                                    \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_offset_map_nested(dir, address)                             \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_unmap(pte) ((void)(pte))
+#define pte_unmap_nested(pte) ((void)(pte))
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+/*
+ * Non-present pages:  high 24 bits are offset, next 8 bits type,
+ * low 32 bits zero.
+ */
+static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
+{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
+
+#define __swp_type(x)           (((x).val >> 32) & 0xff)
+#define __swp_offset(x)         ((x).val >> 40)
+#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+/*
+ * Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset
+ * into this range:
+ */
+#define PTE_FILE_MAX_BITS       32
+
+#define pte_to_pgoff(_pte) \
+        ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
+
+#define pgoff_to_pte(off) \
+        ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
+
+#endif /* _ASM_PGTABLE_64_H */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
new file mode 100644
index 000000000000..3aad751ccd5f
--- /dev/null
+++ b/include/asm-mips/pgtable-bits.h
@@ -0,0 +1,149 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+#include <linux/config.h>
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software.  We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.  On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things.  The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+
+#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
+#define _PAGE_READ                  (1<<7)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
+#define _PAGE_FILE                  (1<<10)  /* set:pagecache unset:swap */
+
+#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<0)
+#define _PAGE_VALID                 (1<<1)
+#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<2)
+#define _CACHE_MASK                 (7<<3)
+
+/* MIPS32 defines only values 2 and 3. The rest are implementation
+ * dependent.
+ */
+#define _CACHE_UNCACHED             (2<<3)
+#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
+#define _CACHE_CACHABLE_COW         (3<<3)  /* Au1x                    */
+
+#else
+
+#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
+#define _PAGE_READ                  (1<<1)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
+#define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _PAGE_GLOBAL                (1<<8)
+#define _PAGE_VALID                 (1<<9)
+#define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<10) /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<10)
+#define _CACHE_UNCACHED             (1<<11)
+#define _CACHE_MASK                 (1<<11)
+#define _CACHE_CACHABLE_NONCOHERENT 0
+
+#else
+#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<6)
+#define _PAGE_VALID                 (1<<7)
+#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<8)
+#define _CACHE_MASK                 (7<<9)
+
+#ifdef CONFIG_CPU_SB1
+
+/* No penalty for being coherent on the SB1, so just
+   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
+
+#define _CACHE_UNCACHED             (2<<9)
+#define _CACHE_CACHABLE_COW         (5<<9)
+#define _CACHE_CACHABLE_NONCOHERENT (5<<9)
+#define _CACHE_UNCACHED_ACCELERATED (7<<9)
+
+#elif defined(CONFIG_CPU_RM9000)
+
+#define _CACHE_WT                       (0 << 9)
+#define _CACHE_WTWA                     (1 << 9)
+#define _CACHE_UC_B                     (2 << 9)
+#define _CACHE_WB                       (3 << 9)
+#define _CACHE_CWBEA                    (4 << 9)
+#define _CACHE_CWB                      (5 << 9)
+#define _CACHE_UCNB                     (6 << 9)
+#define _CACHE_FPC                      (7 << 9)
+
+#define _CACHE_UNCACHED                 _CACHE_UC_B
+#define _CACHE_CACHABLE_NONCOHERENT     _CACHE_WB
+
+#else
+
+#define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
+#define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
+#define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
+#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00MC only         */
+#define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
+
+#endif
+#endif
+#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
+
+#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+
+#ifdef CONFIG_MIPS_UNCACHED
+#define PAGE_CACHABLE_DEFAULT   _CACHE_UNCACHED
+#elif defined(CONFIG_DMA_NONCOHERENT)
+#define PAGE_CACHABLE_DEFAULT   _CACHE_CACHABLE_NONCOHERENT
+#elif defined(CONFIG_CPU_RM9000)
+#define PAGE_CACHABLE_DEFAULT   _CACHE_CWB
+#else
+#define PAGE_CACHABLE_DEFAULT   _CACHE_CACHABLE_COW
+#endif
+
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 3)
+#else
+#define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT >> 9)
+#endif
+
+#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
new file mode 100644
index 000000000000..878843203d67
--- /dev/null
+++ b/include/asm-mips/pgtable.h
@@ -0,0 +1,404 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_PGTABLE_H
+#define _ASM_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <linux/config.h>
+#ifdef CONFIG_MIPS32
+#include <asm/pgtable-32.h>
+#endif
+#ifdef CONFIG_MIPS64
+#include <asm/pgtable-64.h>
+#endif
+
+#include <asm/pgtable-bits.h>
+
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                        PAGE_CACHABLE_DEFAULT)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+                        PAGE_CACHABLE_DEFAULT)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+                        PAGE_CACHABLE_DEFAULT)
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+                        _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                        PAGE_CACHABLE_DEFAULT)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+                        __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
+
+/*
+ * MIPS can't do page protection for execute, and considers that the same like
+ * read. Also, write permissions imply read permissions. This is the closest
+ * we can get by reasonable means..
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY
+#define __P101  PAGE_READONLY
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY
+#define __S101  PAGE_READONLY
+#define __S110  PAGE_SHARED
+#define __S111  PAGE_SHARED
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero; used
+ * for zero-mapped memory areas etc..
+ */
+
+extern unsigned long empty_zero_page;
+extern unsigned long zero_page_mask;
+
+#define ZERO_PAGE(vaddr) \
+        (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
+
+extern void paging_init(void);
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define page_pte(page)          page_pte_prot(page, __pgprot(0))
+#define pmd_phys(pmd)           (pmd_val(pmd) - PAGE_OFFSET)
+#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+#define pmd_page_kernel(pmd)    pmd_val(pmd)
+
+#define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+        //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
+
+        if (pte_val(pte) & _PAGE_GLOBAL) {
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+                if (pte_none(*buddy))
+                        buddy->pte_low |= _PAGE_GLOBAL;
+        }
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        /* Preserve global status for the pair */
+        if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
+                set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
+        else
+                set_pte_at(mm, addr, ptep, __pte(0));
+}
+#else
+/*
+ * Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        *ptep = pteval;
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+        if (pte_val(pteval) & _PAGE_GLOBAL) {
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+                if (pte_none(*buddy))
+                        pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
+        }
+#endif
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+        /* Preserve global status for the pair */
+        if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
+                set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
+        else
+#endif
+                set_pte_at(mm, addr, ptep, __pte(0));
+}
+#endif
+
+/*
+ * (pmds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
+#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0)
+
+#define PGD_T_LOG2      ffz(~sizeof(pgd_t))
+#define PMD_T_LOG2      ffz(~sizeof(pmd_t))
+#define PTE_T_LOG2      ffz(~sizeof(pte_t))
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_user(pte_t pte)   { BUG(); return 0; }
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline int pte_read(pte_t pte)   { return (pte).pte_low & _PAGE_READ; }
+static inline int pte_write(pte_t pte)  { return (pte).pte_low & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return (pte).pte_low & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return (pte).pte_low & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return (pte).pte_low & _PAGE_FILE; }
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        (pte).pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_rdprotect(pte_t pte)
+{
+        (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
+        (pte).pte_high &= ~_PAGE_SILENT_READ;
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
+        (pte).pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+        (pte).pte_high &= ~_PAGE_SILENT_READ;
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        (pte).pte_low |= _PAGE_WRITE;
+        if ((pte).pte_low & _PAGE_MODIFIED) {
+                (pte).pte_low |= _PAGE_SILENT_WRITE;
+                (pte).pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkread(pte_t pte)
+{
+        (pte).pte_low |= _PAGE_READ;
+        if ((pte).pte_low & _PAGE_ACCESSED) {
+                (pte).pte_low |= _PAGE_SILENT_READ;
+                (pte).pte_high |= _PAGE_SILENT_READ;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        (pte).pte_low |= _PAGE_MODIFIED;
+        if ((pte).pte_low & _PAGE_WRITE) {
+                (pte).pte_low |= _PAGE_SILENT_WRITE;
+                (pte).pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        (pte).pte_low |= _PAGE_ACCESSED;
+        if ((pte).pte_low & _PAGE_READ)
+                (pte).pte_low |= _PAGE_SILENT_READ;
+                (pte).pte_high |= _PAGE_SILENT_READ;
+        return pte;
+}
+#else
+static inline int pte_read(pte_t pte)   { return pte_val(pte) & _PAGE_READ; }
+static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_rdprotect(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_WRITE;
+        if (pte_val(pte) & _PAGE_MODIFIED)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkread(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_READ;
+        if (pte_val(pte) & _PAGE_ACCESSED)
+                pte_val(pte) |= _PAGE_SILENT_READ;
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_MODIFIED;
+        if (pte_val(pte) & _PAGE_WRITE)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_ACCESSED;
+        if (pte_val(pte) & _PAGE_READ)
+                pte_val(pte) |= _PAGE_SILENT_READ;
+        return pte;
+}
+#endif
+
+/*
+ * Macro to make mark a page protection value as "uncacheable".  Note
+ * that "protection" is really a misnomer here as the protection value
+ * contains the memory attribute bits, dirty bits, and various other
+ * bits as well.
+ */
+#define pgprot_noncached pgprot_noncached
+
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+        unsigned long prot = pgprot_val(_prot);
+
+        prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
+
+        return __pgprot(prot);
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low &= _PAGE_CHG_MASK;
+        pte.pte_low |= pgprot_val(newprot);
+        pte.pte_high |= pgprot_val(newprot) & 0x3f;
+        return pte;
+}
+#else
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+}
+#endif
+
+
+extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
+extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
+
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+        unsigned long address, pte_t pte)
+{
+        __update_tlb(vma, address, pte);
+        __update_cache(vma, address, pte);
+}
+
+#ifndef CONFIG_DISCONTIGMEM
+#define kern_addr_valid(addr)   (1)
+#endif
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
+
+static inline int io_remap_page_range(struct vm_area_struct *vma,
+                unsigned long vaddr,
+                unsigned long paddr,
+                unsigned long size,
+                pgprot_t prot)
+{
+        phys_t phys_addr_high = fixup_bigphys_addr(paddr, size);
+        return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
+}
+
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+                unsigned long vaddr,
+                unsigned long pfn,
+                unsigned long size,
+                pgprot_t prot)
+{
+        phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+        return remap_pfn_range(vma, vaddr, pfn, size, prot);
+}
+#else
+#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
+                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#endif
+
+#define MK_IOSPACE_PFN(space, pfn)      (pfn)
+#define GET_IOSPACE(pfn)                0
+#define GET_PFN(pfn)                    (pfn)
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own get_unmapped area to cope with the virtual aliasing
+ * constraints placed on us by the cache architecture.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#endif /* _ASM_PGTABLE_H */
diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h
new file mode 100644
index 000000000000..260f3448ccf1
--- /dev/null
+++ b/include/asm-mips/pmon.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ *
+ * The cpustart method is a PMC-Sierra's function to start the secondary CPU.
+ * Stock PMON 2000 has the smpfork, semlock and semunlock methods instead.
+ */
+#ifndef _ASM_PMON_H
+#define _ASM_PMON_H
+
+struct callvectors {
+        int     (*open) (char*, int, int);
+        int     (*close) (int);
+        int     (*read) (int, void*, int);
+        int     (*write) (int, void*, int);
+        off_t   (*lseek) (int, off_t, int);
+        int     (*printf) (const char*, ...);
+        void    (*cacheflush) (void);
+        char*   (*gets) (char*);
+        union {
+                int     (*smpfork) (unsigned long cp, char *sp);
+                int     (*cpustart) (long, long, long, long);
+        } _s;
+        int     (*semlock) (int sem);
+        void    (*semunlock) (int sem);
+};
+
+extern struct callvectors *debug_vectors;
+
+#define pmon_open(name, flags, mode)    debug_vectors->open(name, flage, mode)
+#define pmon_close(fd)                  debug_vectors->close(fd)
+#define pmon_read(fd, buf, count)       debug_vectors->read(fd, buf, count)
+#define pmon_write(fd, buf, count)      debug_vectors->write(fd, buf, count)
+#define pmon_lseek(fd, off, whence)     debug_vectors->lseek(fd, off, whence)
+#define pmon_printf(fmt...)             debug_vectors->printf(fmt)
+#define pmon_cacheflush()               debug_vectors->cacheflush()
+#define pmon_gets(s)                    debug_vectors->gets(s)
+#define pmon_cpustart(n, f, sp, gp)     debug_vectors->_s.cpustart(n, f, sp, gp)
+#define pmon_smpfork(cp, sp)            debug_vectors->_s.smpfork(cp, sp)
+#define pmon_semlock(sem)               debug_vectors->semlock(sem)
+#define pmon_semunlock(sem)             debug_vectors->semunlock(sem)
+
+#endif /* _ASM_PMON_H */
diff --git a/include/asm-mips/poll.h b/include/asm-mips/poll.h
new file mode 100644
index 000000000000..a000f1f789e3
--- /dev/null
+++ b/include/asm-mips/poll.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_POLL_H
+#define __ASM_POLL_H
+
+#define POLLIN          0x0001
+#define POLLPRI         0x0002
+#define POLLOUT         0x0004
+
+#define POLLERR         0x0008
+#define POLLHUP         0x0010
+#define POLLNVAL        0x0020
+
+#define POLLRDNORM      0x0040
+#define POLLRDBAND      0x0080
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      0x0100
+
+/* These seem to be more or less nonstandard ...  */
+#define POLLMSG         0x0400
+#define POLLREMOVE      0x1000
+
+struct pollfd {
+        int fd;
+        short events;
+        short revents;
+};
+
+#endif /* __ASM_POLL_H */
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h
new file mode 100644
index 000000000000..c2e8a0070daf
--- /dev/null
+++ b/include/asm-mips/posix_types.h
@@ -0,0 +1,144 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+#include <asm/sgidefs.h>
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned long   __kernel_nlink_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned int    __kernel_nlink_t;
+#endif
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+#endif
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef long            __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+typedef __kernel_uid_t  __kernel_old_uid_t;
+typedef __kernel_gid_t  __kernel_old_gid_t;
+typedef unsigned int    __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long      __kernel_loff_t;
+#endif
+
+typedef struct {
+#if (_MIPS_SZLONG == 32)
+        long    val[2];
+#endif
+#if (_MIPS_SZLONG == 64)
+        int     val[2];
+#endif
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
new file mode 100644
index 000000000000..4aaaff670361
--- /dev/null
+++ b/include/asm-mips/prctl.h
@@ -0,0 +1,41 @@
+/*
+ * IRIX prctl interface
+ *
+ * The IRIX kernel maps a page at PRDA_ADDRESS with the
+ * contents of prda and fills it the bits on prda_sys.
+ */
+
+#ifndef __PRCTL_H__
+#define __PRCTL_H__
+
+#define PRDA_ADDRESS 0x200000L
+#define PRDA ((struct prda *) PRDA_ADDRESS)
+
+struct prda_sys {
+        pid_t t_pid;
+        u32   t_hint;
+        u32   t_dlactseq;
+        u32   t_fpflags;
+        u32   t_prid;           /* processor type, $prid CP0 register */
+        u32   t_dlendseq;
+        u64   t_unused1[5];
+        pid_t t_rpid;
+        s32   t_resched;
+        u32   t_unused[8];
+        u32   t_cpu;            /* current/last cpu */
+
+        /* FIXME: The signal information, not supported by Linux now */
+        u32   t_flags;          /* if true, then the sigprocmask is in userspace */
+        u32   t_sigprocmask [1]; /* the sigprocmask */
+};
+
+struct prda {
+        char fill [0xe00];
+        struct prda_sys prda_sys;
+};
+
+#define t_sys           prda_sys
+
+ptrdiff_t prctl (int op, int v1, int v2);
+
+#endif
diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h
new file mode 100644
index 000000000000..71293ec1657c
--- /dev/null
+++ b/include/asm-mips/prefetch.h
@@ -0,0 +1,88 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_PREFETCH_H
+#define __ASM_PREFETCH_H
+
+#include <linux/config.h>
+
+/*
+ * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
+ * rather than wasting time we pretend these processors don't support
+ * prefetching at all.
+ *
+ * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
+ * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
+ *
+ * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
+ *
+ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
+ * Pref_PrepareForStore also.
+ *
+ * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
+ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
+ * current versions due to erratum G105.
+ *
+ * VR7701 only implements the Load prefetch.
+ *
+ * Finally MIPS32 and MIPS64 implement all of the following hints.
+ */
+
+#define Pref_Load                       0
+#define Pref_Store                      1
+                                                /* 2 and 3 are reserved */
+#define Pref_LoadStreamed               4
+#define Pref_StoreStreamed              5
+#define Pref_LoadRetained               6
+#define Pref_StoreRetained              7
+                                                /* 8 ... 24 are reserved */
+#define Pref_WriteBackInvalidate        25
+#define Pref_PrepareForStore            30
+
+#ifdef __ASSEMBLY__
+
+        .macro  __pref hint addr
+#ifdef CONFIG_CPU_HAS_PREFETCH
+        pref    \hint, \addr
+#endif
+        .endm
+
+        .macro  pref_load addr
+        __pref  Pref_Load, \addr
+        .endm
+
+        .macro  pref_store addr
+        __pref  Pref_Store, \addr
+        .endm
+
+        .macro  pref_load_streamed addr
+        __pref  Pref_LoadStreamed, \addr
+        .endm
+
+        .macro  pref_store_streamed addr
+        __pref  Pref_StoreStreamed, \addr
+        .endm
+
+        .macro  pref_load_retained addr
+        __pref  Pref_LoadRetained, \addr
+        .endm
+
+        .macro  pref_store_retained addr
+        __pref  Pref_StoreRetained, \addr
+        .endm
+
+        .macro  pref_wback_inv addr
+        __pref  Pref_WriteBackInvalidate, \addr
+        .endm
+
+        .macro  pref_prepare_for_store addr
+        __pref  Pref_PrepareForStore, \addr
+        .endm
+
+#endif
+
+#endif /* __ASM_PREFETCH_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
new file mode 100644
index 000000000000..13c54d5b3b48
--- /dev/null
+++ b/include/asm-mips/processor.h
@@ -0,0 +1,220 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/cachectl.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
+#include <asm/prefetch.h>
+#include <asm/system.h>
+
+/*
+ * Return current * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+/*
+ * System setup and hardware flags..
+ */
+extern void (*cpu_wait)(void);
+
+extern unsigned int vced_count, vcei_count;
+
+#ifdef CONFIG_MIPS32
+/*
+ * User space process size: 2GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE       0x7fff8000UL
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
+#endif
+
+#ifdef CONFIG_MIPS64
+/*
+ * User space process size: 1TB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.  TASK_SIZE
+ * is limited to 1TB by the R4000 architecture; R10000 and better can
+ * support 16TB; the architectural reserve for future expansion is
+ * 8192EB ...
+ */
+#define TASK_SIZE32     0x7fff8000UL
+#define TASK_SIZE       0x10000000000UL
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      ((current->thread.mflags & MF_32BIT_ADDR) ? \
+        PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
+#endif
+
+#define NUM_FPU_REGS    32
+
+typedef __u64 fpureg_t;
+
+struct mips_fpu_hard_struct {
+        fpureg_t        fpr[NUM_FPU_REGS];
+        unsigned int    fcr31;
+};
+
+/*
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand.  So the additional information will be private to
+ * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
+ */
+
+struct mips_fpu_soft_struct {
+        fpureg_t        fpr[NUM_FPU_REGS];
+        unsigned int    fcr31;
+};
+
+union mips_fpu_union {
+        struct mips_fpu_hard_struct hard;
+        struct mips_fpu_soft_struct soft;
+};
+
+#define INIT_FPU { \
+        {{0,},} \
+}
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define ARCH_MIN_TASKALIGN      8
+
+/*
+ * If you change thread_struct remember to change the #defines below too!
+ */
+struct thread_struct {
+        /* Saved main processor registers. */
+        unsigned long reg16;
+        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+        unsigned long reg29, reg30, reg31;
+
+        /* Saved cp0 stuff. */
+        unsigned long cp0_status;
+
+        /* Saved fpu/fpu emulator stuff. */
+        union mips_fpu_union fpu;
+
+        /* Other stuff associated with the thread. */
+        unsigned long cp0_badvaddr;     /* Last user fault */
+        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
+        unsigned long error_code;
+        unsigned long trap_no;
+#define MF_FIXADE       1               /* Fix address errors in software */
+#define MF_LOGADE       2               /* Log address errors to syslog */
+#define MF_32BIT_REGS   4               /* also implies 16/32 fprs */
+#define MF_32BIT_ADDR   8               /* 32-bit address space (o32/n32) */
+        unsigned long mflags;
+        unsigned long irix_trampoline;  /* Wheee... */
+        unsigned long irix_oldctx;
+};
+
+#define MF_ABI_MASK     (MF_32BIT_REGS | MF_32BIT_ADDR)
+#define MF_O32          (MF_32BIT_REGS | MF_32BIT_ADDR)
+#define MF_N32          MF_32BIT_ADDR
+#define MF_N64          0
+
+#define INIT_THREAD  { \
+        /* \
+         * saved main processor registers \
+         */ \
+        0, 0, 0, 0, 0, 0, 0, 0, \
+                       0, 0, 0, \
+        /* \
+         * saved cp0 stuff \
+         */ \
+        0, \
+        /* \
+         * saved fpu/fpu emulator stuff \
+         */ \
+        INIT_FPU, \
+        /* \
+         * Other stuff associated with the process \
+         */ \
+        0, 0, 0, 0, \
+        /* \
+         * For now the default is to fix address errors \
+         */ \
+        MF_FIXADE, 0, 0 \
+}
+
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+extern unsigned long thread_saved_pc(struct task_struct *tsk);
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
+#define __KSTK_TOS(tsk) ((unsigned long)(tsk->thread_info) + THREAD_SIZE - 32)
+#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
+#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
+#define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
+
+#define cpu_relax()     barrier()
+
+/*
+ * Return_address is a replacement for __builtin_return_address(count)
+ * which on certain architectures cannot reasonably be implemented in GCC
+ * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
+ * aborts compilation on some CPUs.  It's simply not possible to unwind
+ * some CPU's stackframes.
+ *
+ * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * overhead of a function call by forcing the compiler to save the return
+ * address register on the stack.
+ */
+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
+
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+
+extern inline void prefetch(const void *addr)
+{
+        __asm__ __volatile__(
+        "       .set    mips4           \n"
+        "       pref    %0, (%1)        \n"
+        "       .set    mips0           \n"
+        :
+        : "i" (Pref_Load), "r" (addr));
+}
+
+#endif
+
+#endif /* _ASM_PROCESSOR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
new file mode 100644
index 000000000000..d3c46d633826
--- /dev/null
+++ b/include/asm-mips/ptrace.h
@@ -0,0 +1,79 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+#include <linux/config.h>
+
+#include <asm/isadep.h>
+
+/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
+#define FPR_BASE        32
+#define PC              64
+#define CAUSE           65
+#define BADVADDR        66
+#define MMHI            67
+#define MMLO            68
+#define FPC_CSR         69
+#define FPC_EIR         70
+
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_MIPS32
+        /* Pad bytes for argument save space on the stack. */
+        unsigned long pad0[6];
+#endif
+
+        /* Saved main processor registers. */
+        unsigned long regs[32];
+
+        /* Saved special registers. */
+        unsigned long cp0_status;
+        unsigned long lo;
+        unsigned long hi;
+        unsigned long cp0_badvaddr;
+        unsigned long cp0_cause;
+        unsigned long cp0_epc;
+};
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+/* #define PTRACE_GETREGS               12 */
+/* #define PTRACE_SETREGS               13 */
+/* #define PTRACE_GETFPREGS             14 */
+/* #define PTRACE_SETFPREGS             15 */
+/* #define PTRACE_GETFPXREGS            18 */
+/* #define PTRACE_SETFPXREGS            19 */
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#define PTRACE_GET_THREAD_AREA  25
+#define PTRACE_SET_THREAD_AREA  26
+
+#ifdef __KERNEL__
+
+#include <linux/linkage.h>
+
+/*
+ * Does the process account for user or for system time?
+ */
+#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
+
+#define instruction_pointer(regs) ((regs)->cp0_epc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+extern void show_regs(struct pt_regs *);
+
+extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
+
+#endif
+
+#endif /* _ASM_PTRACE_H */
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
new file mode 100644
index 000000000000..da03a32c1ca7
--- /dev/null
+++ b/include/asm-mips/r4kcache.h
@@ -0,0 +1,598 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Inline assembly cache operations.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_R4KCACHE_H
+#define _ASM_R4KCACHE_H
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+
+/*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations.  Two issues here:
+ *
+ *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
+ *    the index bits from the virtual address.  This breaks with tradition
+ *    set by the R4000.  To keep unpleassant surprises from happening we pick
+ *    an address in KSEG0 / CKSEG0.
+ *  - We need a properly sign extended address for 64-bit code.  To get away
+ *    without ifdefs we let the compiler do it by a type cast.
+ */
+#define INDEX_BASE      CKSEG0
+
+#define cache_op(op,addr)                                               \
+        __asm__ __volatile__(                                           \
+        "       .set    noreorder                               \n"     \
+        "       .set    mips3\n\t                               \n"     \
+        "       cache   %0, %1                                  \n"     \
+        "       .set    mips0                                   \n"     \
+        "       .set    reorder"                                        \
+        :                                                               \
+        : "i" (op), "m" (*(unsigned char *)(addr)))
+
+static inline void flush_icache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Invalidate_I, addr);
+}
+
+static inline void flush_dcache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Writeback_Inv_D, addr);
+}
+
+static inline void flush_scache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Writeback_Inv_SD, addr);
+}
+
+static inline void flush_icache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_I, addr);
+}
+
+static inline void flush_dcache_line(unsigned long addr)
+{
+        cache_op(Hit_Writeback_Inv_D, addr);
+}
+
+static inline void invalidate_dcache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_D, addr);
+}
+
+static inline void invalidate_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_SD, addr);
+}
+
+static inline void flush_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Writeback_Inv_SD, addr);
+}
+
+/*
+ * The next two are for badland addresses like signal trampolines.
+ */
+static inline void protected_flush_icache_line(unsigned long addr)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                ".set mips3\n"
+                "1:\tcache %0,(%1)\n"
+                "2:\t.set mips0\n\t"
+                ".set reorder\n\t"
+                ".section\t__ex_table,\"a\"\n\t"
+                STR(PTR)"\t1b,2b\n\t"
+                ".previous"
+                :
+                : "i" (Hit_Invalidate_I), "r" (addr));
+}
+
+/*
+ * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
+ * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
+ * caches.  We're talking about one cacheline unnecessarily getting invalidated
+ * here so the penaltiy isn't overly hard.
+ */
+static inline void protected_writeback_dcache_line(unsigned long addr)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                ".set mips3\n"
+                "1:\tcache %0,(%1)\n"
+                "2:\t.set mips0\n\t"
+                ".set reorder\n\t"
+                ".section\t__ex_table,\"a\"\n\t"
+                STR(PTR)"\t1b,2b\n\t"
+                ".previous"
+                :
+                : "i" (Hit_Writeback_Inv_D), "r" (addr));
+}
+
+static inline void protected_writeback_scache_line(unsigned long addr)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                ".set mips3\n"
+                "1:\tcache %0,(%1)\n"
+                "2:\t.set mips0\n\t"
+                ".set reorder\n\t"
+                ".section\t__ex_table,\"a\"\n\t"
+                STR(PTR)"\t1b,2b\n\t"
+                ".previous"
+                :
+                : "i" (Hit_Writeback_Inv_SD), "r" (addr));
+}
+
+/*
+ * This one is RM7000-specific
+ */
+static inline void invalidate_tcache_page(unsigned long addr)
+{
+        cache_op(Page_Invalidate_T, addr);
+}
+
+#define cache16_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x010(%0)        \n"     \
+        "       cache %1, 0x020(%0); cache %1, 0x030(%0)        \n"     \
+        "       cache %1, 0x040(%0); cache %1, 0x050(%0)        \n"     \
+        "       cache %1, 0x060(%0); cache %1, 0x070(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x090(%0)        \n"     \
+        "       cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)        \n"     \
+        "       cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)        \n"     \
+        "       cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x110(%0)        \n"     \
+        "       cache %1, 0x120(%0); cache %1, 0x130(%0)        \n"     \
+        "       cache %1, 0x140(%0); cache %1, 0x150(%0)        \n"     \
+        "       cache %1, 0x160(%0); cache %1, 0x170(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x190(%0)        \n"     \
+        "       cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)        \n"     \
+        "       cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)        \n"     \
+        "       cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)        \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set reorder                                    \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+static inline void blast_dcache16(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.dcache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+        unsigned long ws_end = current_cpu_data.dcache.ways << 
+                               current_cpu_data.dcache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200)
+                        cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
+}
+
+static inline void blast_dcache16_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+
+        do {
+                cache16_unroll32(start,Hit_Writeback_Inv_D);
+                start += 0x200;
+        } while (start < end);
+}
+
+static inline void blast_dcache16_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+        unsigned long ws_end = current_cpu_data.dcache.ways <<
+                               current_cpu_data.dcache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200) 
+                        cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
+}
+
+static inline void blast_icache16(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.icache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200) 
+                        cache16_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_icache16_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+
+        do {
+                cache16_unroll32(start,Hit_Invalidate_I);
+                start += 0x200;
+        } while (start < end);
+}
+
+static inline void blast_icache16_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200) 
+                        cache16_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_scache16(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.scache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways << 
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200)
+                        cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+static inline void blast_scache16_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = page + PAGE_SIZE;
+
+        do {
+                cache16_unroll32(start,Hit_Writeback_Inv_SD);
+                start += 0x200;
+        } while (start < end);
+}
+
+static inline void blast_scache16_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways <<
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x200) 
+                        cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+#define cache32_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x020(%0)        \n"     \
+        "       cache %1, 0x040(%0); cache %1, 0x060(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x0a0(%0)        \n"     \
+        "       cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x120(%0)        \n"     \
+        "       cache %1, 0x140(%0); cache %1, 0x160(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x1a0(%0)        \n"     \
+        "       cache %1, 0x1c0(%0); cache %1, 0x1e0(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x220(%0)        \n"     \
+        "       cache %1, 0x240(%0); cache %1, 0x260(%0)        \n"     \
+        "       cache %1, 0x280(%0); cache %1, 0x2a0(%0)        \n"     \
+        "       cache %1, 0x2c0(%0); cache %1, 0x2e0(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x320(%0)        \n"     \
+        "       cache %1, 0x340(%0); cache %1, 0x360(%0)        \n"     \
+        "       cache %1, 0x380(%0); cache %1, 0x3a0(%0)        \n"     \
+        "       cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)        \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set reorder                                    \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+static inline void blast_dcache32(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.dcache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+        unsigned long ws_end = current_cpu_data.dcache.ways <<
+                               current_cpu_data.dcache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x400) 
+                        cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
+}
+
+static inline void blast_dcache32_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+
+        do {
+                cache32_unroll32(start,Hit_Writeback_Inv_D);
+                start += 0x400;
+        } while (start < end);
+}
+
+static inline void blast_dcache32_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+        unsigned long ws_end = current_cpu_data.dcache.ways <<
+                               current_cpu_data.dcache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x400) 
+                        cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
+}
+
+static inline void blast_icache32(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.icache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x400) 
+                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_icache32_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+
+        do {
+                cache32_unroll32(start,Hit_Invalidate_I);
+                start += 0x400;
+        } while (start < end);
+}
+
+static inline void blast_icache32_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400) 
+                        cache32_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_scache32(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.scache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways << 
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x400)
+                        cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+static inline void blast_scache32_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = page + PAGE_SIZE;
+
+        do {
+                cache32_unroll32(start,Hit_Writeback_Inv_SD);
+                start += 0x400;
+        } while (start < end);
+}
+
+static inline void blast_scache32_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways <<
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x400) 
+                        cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+#define cache64_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x040(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x0c0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x140(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x1c0(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x240(%0)        \n"     \
+        "       cache %1, 0x280(%0); cache %1, 0x2c0(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x340(%0)        \n"     \
+        "       cache %1, 0x380(%0); cache %1, 0x3c0(%0)        \n"     \
+        "       cache %1, 0x400(%0); cache %1, 0x440(%0)        \n"     \
+        "       cache %1, 0x480(%0); cache %1, 0x4c0(%0)        \n"     \
+        "       cache %1, 0x500(%0); cache %1, 0x540(%0)        \n"     \
+        "       cache %1, 0x580(%0); cache %1, 0x5c0(%0)        \n"     \
+        "       cache %1, 0x600(%0); cache %1, 0x640(%0)        \n"     \
+        "       cache %1, 0x680(%0); cache %1, 0x6c0(%0)        \n"     \
+        "       cache %1, 0x700(%0); cache %1, 0x740(%0)        \n"     \
+        "       cache %1, 0x780(%0); cache %1, 0x7c0(%0)        \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set reorder                                    \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+static inline void blast_icache64(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.icache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x800) 
+                        cache64_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_icache64_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+
+        do {
+                cache64_unroll32(start,Hit_Invalidate_I);
+                start += 0x800;
+        } while (start < end);
+}
+
+static inline void blast_icache64_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
+        unsigned long ws_end = current_cpu_data.icache.ways <<
+                               current_cpu_data.icache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x800) 
+                        cache64_unroll32(addr|ws,Index_Invalidate_I);
+}
+
+static inline void blast_scache64(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.scache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways << 
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x800)
+                        cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+static inline void blast_scache64_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = page + PAGE_SIZE;
+
+        do {
+                cache64_unroll32(start,Hit_Writeback_Inv_SD);
+                start += 0x800;
+        } while (start < end);
+}
+
+static inline void blast_scache64_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways <<
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x800) 
+                        cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+#define cache128_unroll32(base,op)                                      \
+        __asm__ __volatile__(                                           \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x080(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x180(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x280(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x380(%0)        \n"     \
+        "       cache %1, 0x400(%0); cache %1, 0x480(%0)        \n"     \
+        "       cache %1, 0x500(%0); cache %1, 0x580(%0)        \n"     \
+        "       cache %1, 0x600(%0); cache %1, 0x680(%0)        \n"     \
+        "       cache %1, 0x700(%0); cache %1, 0x780(%0)        \n"     \
+        "       cache %1, 0x800(%0); cache %1, 0x880(%0)        \n"     \
+        "       cache %1, 0x900(%0); cache %1, 0x980(%0)        \n"     \
+        "       cache %1, 0xa00(%0); cache %1, 0xa80(%0)        \n"     \
+        "       cache %1, 0xb00(%0); cache %1, 0xb80(%0)        \n"     \
+        "       cache %1, 0xc00(%0); cache %1, 0xc80(%0)        \n"     \
+        "       cache %1, 0xd00(%0); cache %1, 0xd80(%0)        \n"     \
+        "       cache %1, 0xe00(%0); cache %1, 0xe80(%0)        \n"     \
+        "       cache %1, 0xf00(%0); cache %1, 0xf80(%0)        \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set reorder                                    \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+static inline void blast_scache128(void)
+{
+        unsigned long start = INDEX_BASE;
+        unsigned long end = start + current_cpu_data.scache.waysize;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways << 
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x1000)
+                        cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+static inline void blast_scache128_page(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = page + PAGE_SIZE;
+
+        do {
+                cache128_unroll32(start,Hit_Writeback_Inv_SD);
+                start += 0x1000;
+        } while (start < end);
+}
+
+static inline void blast_scache128_page_indexed(unsigned long page)
+{
+        unsigned long start = page;
+        unsigned long end = start + PAGE_SIZE;
+        unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
+        unsigned long ws_end = current_cpu_data.scache.ways <<
+                               current_cpu_data.scache.waybit;
+        unsigned long ws, addr;
+
+        for (ws = 0; ws < ws_end; ws += ws_inc) 
+                for (addr = start; addr < end; addr += 0x1000) 
+                        cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
+}
+
+#endif /* _ASM_R4KCACHE_H */
diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h
new file mode 100644
index 000000000000..2f10ebcbe141
--- /dev/null
+++ b/include/asm-mips/reboot.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void (*_machine_restart)(char *command);
+extern void (*_machine_halt)(void);
+extern void (*_machine_power_off)(void);
+
+#endif /* _ASM_REBOOT_H */
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
new file mode 100644
index 000000000000..7b33bbca9585
--- /dev/null
+++ b/include/asm-mips/reg.h
@@ -0,0 +1,129 @@
+/*
+ * Various register offset definitions for debuggers, core file
+ * examiners and whatnot.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1995, 1999 Silicon Graphics
+ */
+#ifndef __ASM_MIPS_REG_H
+#define __ASM_MIPS_REG_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_MIPS32) || defined(WANT_COMPAT_REG_H)
+
+#define EF_R0                   6
+#define EF_R1                   7
+#define EF_R2                   8
+#define EF_R3                   9
+#define EF_R4                   10
+#define EF_R5                   11
+#define EF_R6                   12
+#define EF_R7                   13
+#define EF_R8                   14
+#define EF_R9                   15
+#define EF_R10                  16
+#define EF_R11                  17
+#define EF_R12                  18
+#define EF_R13                  19
+#define EF_R14                  20
+#define EF_R15                  21
+#define EF_R16                  22
+#define EF_R17                  23
+#define EF_R18                  24
+#define EF_R19                  25
+#define EF_R20                  26
+#define EF_R21                  27
+#define EF_R22                  28
+#define EF_R23                  29
+#define EF_R24                  30
+#define EF_R25                  31
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26                  32
+#define EF_R27                  33
+
+#define EF_R28                  34
+#define EF_R29                  35
+#define EF_R30                  36
+#define EF_R31                  37
+
+/*
+ * Saved special registers
+ */
+#define EF_LO                   38
+#define EF_HI                   39
+
+#define EF_CP0_EPC              40
+#define EF_CP0_BADVADDR         41
+#define EF_CP0_STATUS           42
+#define EF_CP0_CAUSE            43
+#define EF_UNUSED0              44
+
+#define EF_SIZE                 180
+
+#endif
+
+#if CONFIG_MIPS64
+
+#define EF_R0                    0
+#define EF_R1                    1
+#define EF_R2                    2
+#define EF_R3                    3
+#define EF_R4                    4
+#define EF_R5                    5
+#define EF_R6                    6
+#define EF_R7                    7
+#define EF_R8                    8
+#define EF_R9                    9
+#define EF_R10                  10
+#define EF_R11                  11
+#define EF_R12                  12
+#define EF_R13                  13
+#define EF_R14                  14
+#define EF_R15                  15
+#define EF_R16                  16
+#define EF_R17                  17
+#define EF_R18                  18
+#define EF_R19                  19
+#define EF_R20                  20
+#define EF_R21                  21
+#define EF_R22                  22
+#define EF_R23                  23
+#define EF_R24                  24
+#define EF_R25                  25
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26                  26
+#define EF_R27                  27
+
+
+#define EF_R28                  28
+#define EF_R29                  29
+#define EF_R30                  30
+#define EF_R31                  31
+
+/*
+ * Saved special registers
+ */
+#define EF_LO                   32
+#define EF_HI                   33
+
+#define EF_CP0_EPC              34
+#define EF_CP0_BADVADDR         35
+#define EF_CP0_STATUS           36
+#define EF_CP0_CAUSE            37
+
+#define EF_SIZE                 304     /* size in bytes */
+
+#endif /* CONFIG_MIPS64 */
+
+#endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h
new file mode 100644
index 000000000000..7c8ecb6b9c40
--- /dev/null
+++ b/include/asm-mips/regdef.h
@@ -0,0 +1,100 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+#define zero    $0      /* wired zero */
+#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
+#define v0      $2      /* return value */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8      /* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define zero    $0      /* wired zero */
+#define AT      $at     /* assembler temp - uppercase because of ".set at" */
+#define v0      $2      /* return value - caller saved */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define a4      $8      /* arg reg 64 bit; caller saved in 32 bit */
+#define ta0     $8
+#define a5      $9
+#define ta1     $9
+#define a6      $10
+#define ta2     $10
+#define a7      $11
+#define ta3     $11
+#define t0      $12     /* caller saved */
+#define t1      $13
+#define t2      $14
+#define t3      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25     /* callee address for PIC/temp */
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel temporary */
+#define k1      $27
+#define gp      $28     /* global pointer - caller saved for PIC */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* callee saved */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_REGDEF_H */
diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h
new file mode 100644
index 000000000000..fd3c6d17a5f6
--- /dev/null
+++ b/include/asm-mips/resource.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_RESOURCE_H
+#define _ASM_RESOURCE_H
+
+#include <linux/config.h>
+
+/*
+ * These five resource limit IDs have a MIPS/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           5       /* max number of open files */
+#define RLIMIT_AS               6       /* address space limit */
+#define RLIMIT_RSS              7       /* max resident set size */
+#define RLIMIT_NPROC            8       /* max number of processes */
+#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
+
+/*
+ * SuS says limits have to be unsigned.
+ * Which makes a ton more sense anyway,
+ * but we keep the old value on MIPS32,
+ * for compatibility:
+ */
+#ifdef CONFIG_MIPS32
+# define RLIM_INFINITY          0x7fffffffUL
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* _ASM_RESOURCE_H */
diff --git a/include/asm-mips/riscos-syscall.h b/include/asm-mips/riscos-syscall.h
new file mode 100644
index 000000000000..4d8eb15461eb
--- /dev/null
+++ b/include/asm-mips/riscos-syscall.h
@@ -0,0 +1,979 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_RISCOS_SYSCALL_H
+#define _ASM_RISCOS_SYSCALL_H
+
+/*
+ * The syscalls 0 - 3999 are reserved for a down to the root syscall
+ * compatibility with RISC/os and IRIX.  We'll see how to deal with the
+ * various "real" BSD variants like Ultrix, NetBSD ...
+ */
+
+/*
+ * SVR4 syscalls are in the range from 1 to 999
+ */
+#define __NR_SVR4                       0
+#define __NR_SVR4_syscall               (__NR_SVR4 +   0)
+#define __NR_SVR4_exit                  (__NR_SVR4 +   1)
+#define __NR_SVR4_fork                  (__NR_SVR4 +   2)
+#define __NR_SVR4_read                  (__NR_SVR4 +   3)
+#define __NR_SVR4_write                 (__NR_SVR4 +   4)
+#define __NR_SVR4_open                  (__NR_SVR4 +   5)
+#define __NR_SVR4_close                 (__NR_SVR4 +   6)
+#define __NR_SVR4_wait                  (__NR_SVR4 +   7)
+#define __NR_SVR4_creat                 (__NR_SVR4 +   8)
+#define __NR_SVR4_link                  (__NR_SVR4 +   9)
+#define __NR_SVR4_unlink                (__NR_SVR4 +  10)
+#define __NR_SVR4_exec                  (__NR_SVR4 +  11)
+#define __NR_SVR4_chdir                 (__NR_SVR4 +  12)
+#define __NR_SVR4_gtime                 (__NR_SVR4 +  13)
+#define __NR_SVR4_mknod                 (__NR_SVR4 +  14)
+#define __NR_SVR4_chmod                 (__NR_SVR4 +  15)
+#define __NR_SVR4_chown                 (__NR_SVR4 +  16)
+#define __NR_SVR4_sbreak                (__NR_SVR4 +  17)
+#define __NR_SVR4_stat                  (__NR_SVR4 +  18)
+#define __NR_SVR4_lseek                 (__NR_SVR4 +  19)
+#define __NR_SVR4_getpid                (__NR_SVR4 +  20)
+#define __NR_SVR4_mount                 (__NR_SVR4 +  21)
+#define __NR_SVR4_umount                (__NR_SVR4 +  22)
+#define __NR_SVR4_setuid                (__NR_SVR4 +  23)
+#define __NR_SVR4_getuid                (__NR_SVR4 +  24)
+#define __NR_SVR4_stime                 (__NR_SVR4 +  25)
+#define __NR_SVR4_ptrace                (__NR_SVR4 +  26)
+#define __NR_SVR4_alarm                 (__NR_SVR4 +  27)
+#define __NR_SVR4_fstat                 (__NR_SVR4 +  28)
+#define __NR_SVR4_pause                 (__NR_SVR4 +  29)
+#define __NR_SVR4_utime                 (__NR_SVR4 +  30)
+#define __NR_SVR4_stty                  (__NR_SVR4 +  31)
+#define __NR_SVR4_gtty                  (__NR_SVR4 +  32)
+#define __NR_SVR4_access                (__NR_SVR4 +  33)
+#define __NR_SVR4_nice                  (__NR_SVR4 +  34)
+#define __NR_SVR4_statfs                (__NR_SVR4 +  35)
+#define __NR_SVR4_sync                  (__NR_SVR4 +  36)
+#define __NR_SVR4_kill                  (__NR_SVR4 +  37)
+#define __NR_SVR4_fstatfs               (__NR_SVR4 +  38)
+#define __NR_SVR4_setpgrp               (__NR_SVR4 +  39)
+#define __NR_SVR4_cxenix                (__NR_SVR4 +  40)
+#define __NR_SVR4_dup                   (__NR_SVR4 +  41)
+#define __NR_SVR4_pipe                  (__NR_SVR4 +  42)
+#define __NR_SVR4_times                 (__NR_SVR4 +  43)
+#define __NR_SVR4_profil                (__NR_SVR4 +  44)
+#define __NR_SVR4_plock                 (__NR_SVR4 +  45)
+#define __NR_SVR4_setgid                (__NR_SVR4 +  46)
+#define __NR_SVR4_getgid                (__NR_SVR4 +  47)
+#define __NR_SVR4_sig                   (__NR_SVR4 +  48)
+#define __NR_SVR4_msgsys                (__NR_SVR4 +  49)
+#define __NR_SVR4_sysmips               (__NR_SVR4 +  50)
+#define __NR_SVR4_sysacct               (__NR_SVR4 +  51)
+#define __NR_SVR4_shmsys                (__NR_SVR4 +  52)
+#define __NR_SVR4_semsys                (__NR_SVR4 +  53)
+#define __NR_SVR4_ioctl                 (__NR_SVR4 +  54)
+#define __NR_SVR4_uadmin                (__NR_SVR4 +  55)
+#define __NR_SVR4_exch                  (__NR_SVR4 +  56)
+#define __NR_SVR4_utssys                (__NR_SVR4 +  57)
+#define __NR_SVR4_fsync                 (__NR_SVR4 +  58)
+#define __NR_SVR4_exece                 (__NR_SVR4 +  59)
+#define __NR_SVR4_umask                 (__NR_SVR4 +  60)
+#define __NR_SVR4_chroot                (__NR_SVR4 +  61)
+#define __NR_SVR4_fcntl                 (__NR_SVR4 +  62)
+#define __NR_SVR4_ulimit                (__NR_SVR4 +  63)
+#define __NR_SVR4_reserved1             (__NR_SVR4 +  64)
+#define __NR_SVR4_reserved2             (__NR_SVR4 +  65)
+#define __NR_SVR4_reserved3             (__NR_SVR4 +  66)
+#define __NR_SVR4_reserved4             (__NR_SVR4 +  67)
+#define __NR_SVR4_reserved5             (__NR_SVR4 +  68)
+#define __NR_SVR4_reserved6             (__NR_SVR4 +  69)
+#define __NR_SVR4_advfs                 (__NR_SVR4 +  70)
+#define __NR_SVR4_unadvfs               (__NR_SVR4 +  71)
+#define __NR_SVR4_unused1               (__NR_SVR4 +  72)
+#define __NR_SVR4_unused2               (__NR_SVR4 +  73)
+#define __NR_SVR4_rfstart               (__NR_SVR4 +  74)
+#define __NR_SVR4_unused3               (__NR_SVR4 +  75)
+#define __NR_SVR4_rdebug                (__NR_SVR4 +  76)
+#define __NR_SVR4_rfstop                (__NR_SVR4 +  77)
+#define __NR_SVR4_rfsys                 (__NR_SVR4 +  78)
+#define __NR_SVR4_rmdir                 (__NR_SVR4 +  79)
+#define __NR_SVR4_mkdir                 (__NR_SVR4 +  80)
+#define __NR_SVR4_getdents              (__NR_SVR4 +  81)
+#define __NR_SVR4_libattach             (__NR_SVR4 +  82)
+#define __NR_SVR4_libdetach             (__NR_SVR4 +  83)
+#define __NR_SVR4_sysfs                 (__NR_SVR4 +  84)
+#define __NR_SVR4_getmsg                (__NR_SVR4 +  85)
+#define __NR_SVR4_putmsg                (__NR_SVR4 +  86)
+#define __NR_SVR4_poll                  (__NR_SVR4 +  87)
+#define __NR_SVR4_lstat                 (__NR_SVR4 +  88)
+#define __NR_SVR4_symlink               (__NR_SVR4 +  89)
+#define __NR_SVR4_readlink              (__NR_SVR4 +  90)
+#define __NR_SVR4_setgroups             (__NR_SVR4 +  91)
+#define __NR_SVR4_getgroups             (__NR_SVR4 +  92)
+#define __NR_SVR4_fchmod                (__NR_SVR4 +  93)
+#define __NR_SVR4_fchown                (__NR_SVR4 +  94)
+#define __NR_SVR4_sigprocmask           (__NR_SVR4 +  95)
+#define __NR_SVR4_sigsuspend            (__NR_SVR4 +  96)
+#define __NR_SVR4_sigaltstack           (__NR_SVR4 +  97)
+#define __NR_SVR4_sigaction             (__NR_SVR4 +  98)
+#define __NR_SVR4_sigpending            (__NR_SVR4 +  99)
+#define __NR_SVR4_setcontext            (__NR_SVR4 + 100)
+#define __NR_SVR4_evsys                 (__NR_SVR4 + 101)
+#define __NR_SVR4_evtrapret             (__NR_SVR4 + 102)
+#define __NR_SVR4_statvfs               (__NR_SVR4 + 103)
+#define __NR_SVR4_fstatvfs              (__NR_SVR4 + 104)
+#define __NR_SVR4_reserved7             (__NR_SVR4 + 105)
+#define __NR_SVR4_nfssys                (__NR_SVR4 + 106)
+#define __NR_SVR4_waitid                (__NR_SVR4 + 107)
+#define __NR_SVR4_sigsendset            (__NR_SVR4 + 108)
+#define __NR_SVR4_hrtsys                (__NR_SVR4 + 109)
+#define __NR_SVR4_acancel               (__NR_SVR4 + 110)
+#define __NR_SVR4_async                 (__NR_SVR4 + 111)
+#define __NR_SVR4_priocntlset           (__NR_SVR4 + 112)
+#define __NR_SVR4_pathconf              (__NR_SVR4 + 113)
+#define __NR_SVR4_mincore               (__NR_SVR4 + 114)
+#define __NR_SVR4_mmap                  (__NR_SVR4 + 115)
+#define __NR_SVR4_mprotect              (__NR_SVR4 + 116)
+#define __NR_SVR4_munmap                (__NR_SVR4 + 117)
+#define __NR_SVR4_fpathconf             (__NR_SVR4 + 118)
+#define __NR_SVR4_vfork                 (__NR_SVR4 + 119)
+#define __NR_SVR4_fchdir                (__NR_SVR4 + 120)
+#define __NR_SVR4_readv                 (__NR_SVR4 + 121)
+#define __NR_SVR4_writev                (__NR_SVR4 + 122)
+#define __NR_SVR4_xstat                 (__NR_SVR4 + 123)
+#define __NR_SVR4_lxstat                (__NR_SVR4 + 124)
+#define __NR_SVR4_fxstat                (__NR_SVR4 + 125)
+#define __NR_SVR4_xmknod                (__NR_SVR4 + 126)
+#define __NR_SVR4_clocal                (__NR_SVR4 + 127)
+#define __NR_SVR4_setrlimit             (__NR_SVR4 + 128)
+#define __NR_SVR4_getrlimit             (__NR_SVR4 + 129)
+#define __NR_SVR4_lchown                (__NR_SVR4 + 130)
+#define __NR_SVR4_memcntl               (__NR_SVR4 + 131)
+#define __NR_SVR4_getpmsg               (__NR_SVR4 + 132)
+#define __NR_SVR4_putpmsg               (__NR_SVR4 + 133)
+#define __NR_SVR4_rename                (__NR_SVR4 + 134)
+#define __NR_SVR4_nuname                (__NR_SVR4 + 135)
+#define __NR_SVR4_setegid               (__NR_SVR4 + 136)
+#define __NR_SVR4_sysconf               (__NR_SVR4 + 137)
+#define __NR_SVR4_adjtime               (__NR_SVR4 + 138)
+#define __NR_SVR4_sysinfo               (__NR_SVR4 + 139)
+#define __NR_SVR4_reserved8             (__NR_SVR4 + 140)
+#define __NR_SVR4_seteuid               (__NR_SVR4 + 141)
+#define __NR_SVR4_PYRAMID_statis        (__NR_SVR4 + 142)
+#define __NR_SVR4_PYRAMID_tuning        (__NR_SVR4 + 143)
+#define __NR_SVR4_PYRAMID_forcerr       (__NR_SVR4 + 144)
+#define __NR_SVR4_PYRAMID_mpcntl        (__NR_SVR4 + 145)
+#define __NR_SVR4_reserved9             (__NR_SVR4 + 146)
+#define __NR_SVR4_reserved10            (__NR_SVR4 + 147)
+#define __NR_SVR4_reserved11            (__NR_SVR4 + 148)
+#define __NR_SVR4_reserved12            (__NR_SVR4 + 149)
+#define __NR_SVR4_reserved13            (__NR_SVR4 + 150)
+#define __NR_SVR4_reserved14            (__NR_SVR4 + 151)
+#define __NR_SVR4_reserved15            (__NR_SVR4 + 152)
+#define __NR_SVR4_reserved16            (__NR_SVR4 + 153)
+#define __NR_SVR4_reserved17            (__NR_SVR4 + 154)
+#define __NR_SVR4_reserved18            (__NR_SVR4 + 155)
+#define __NR_SVR4_reserved19            (__NR_SVR4 + 156)
+#define __NR_SVR4_reserved20            (__NR_SVR4 + 157)
+#define __NR_SVR4_reserved21            (__NR_SVR4 + 158)
+#define __NR_SVR4_reserved22            (__NR_SVR4 + 159)
+#define __NR_SVR4_reserved23            (__NR_SVR4 + 160)
+#define __NR_SVR4_reserved24            (__NR_SVR4 + 161)
+#define __NR_SVR4_reserved25            (__NR_SVR4 + 162)
+#define __NR_SVR4_reserved26            (__NR_SVR4 + 163)
+#define __NR_SVR4_reserved27            (__NR_SVR4 + 164)
+#define __NR_SVR4_reserved28            (__NR_SVR4 + 165)
+#define __NR_SVR4_reserved29            (__NR_SVR4 + 166)
+#define __NR_SVR4_reserved30            (__NR_SVR4 + 167)
+#define __NR_SVR4_reserved31            (__NR_SVR4 + 168)
+#define __NR_SVR4_reserved32            (__NR_SVR4 + 169)
+#define __NR_SVR4_reserved33            (__NR_SVR4 + 170)
+#define __NR_SVR4_reserved34            (__NR_SVR4 + 171)
+#define __NR_SVR4_reserved35            (__NR_SVR4 + 172)
+#define __NR_SVR4_reserved36            (__NR_SVR4 + 173)
+#define __NR_SVR4_reserved37            (__NR_SVR4 + 174)
+#define __NR_SVR4_reserved38            (__NR_SVR4 + 175)
+#define __NR_SVR4_reserved39            (__NR_SVR4 + 176)
+#define __NR_SVR4_reserved40            (__NR_SVR4 + 177)
+#define __NR_SVR4_reserved41            (__NR_SVR4 + 178)
+#define __NR_SVR4_reserved42            (__NR_SVR4 + 179)
+#define __NR_SVR4_reserved43            (__NR_SVR4 + 180)
+#define __NR_SVR4_reserved44            (__NR_SVR4 + 181)
+#define __NR_SVR4_reserved45            (__NR_SVR4 + 182)
+#define __NR_SVR4_reserved46            (__NR_SVR4 + 183)
+#define __NR_SVR4_reserved47            (__NR_SVR4 + 184)
+#define __NR_SVR4_reserved48            (__NR_SVR4 + 185)
+#define __NR_SVR4_reserved49            (__NR_SVR4 + 186)
+#define __NR_SVR4_reserved50            (__NR_SVR4 + 187)
+#define __NR_SVR4_reserved51            (__NR_SVR4 + 188)
+#define __NR_SVR4_reserved52            (__NR_SVR4 + 189)
+#define __NR_SVR4_reserved53            (__NR_SVR4 + 190)
+#define __NR_SVR4_reserved54            (__NR_SVR4 + 191)
+#define __NR_SVR4_reserved55            (__NR_SVR4 + 192)
+#define __NR_SVR4_reserved56            (__NR_SVR4 + 193)
+#define __NR_SVR4_reserved57            (__NR_SVR4 + 194)
+#define __NR_SVR4_reserved58            (__NR_SVR4 + 195)
+#define __NR_SVR4_reserved59            (__NR_SVR4 + 196)
+#define __NR_SVR4_reserved60            (__NR_SVR4 + 197)
+#define __NR_SVR4_reserved61            (__NR_SVR4 + 198)
+#define __NR_SVR4_reserved62            (__NR_SVR4 + 199)
+#define __NR_SVR4_reserved63            (__NR_SVR4 + 200)
+#define __NR_SVR4_aread                 (__NR_SVR4 + 201)
+#define __NR_SVR4_awrite                (__NR_SVR4 + 202)
+#define __NR_SVR4_listio                (__NR_SVR4 + 203)
+#define __NR_SVR4_mips_acancel          (__NR_SVR4 + 204)
+#define __NR_SVR4_astatus               (__NR_SVR4 + 205)
+#define __NR_SVR4_await                 (__NR_SVR4 + 206)
+#define __NR_SVR4_areadv                (__NR_SVR4 + 207)
+#define __NR_SVR4_awritev               (__NR_SVR4 + 208)
+#define __NR_SVR4_MIPS_reserved1        (__NR_SVR4 + 209)
+#define __NR_SVR4_MIPS_reserved2        (__NR_SVR4 + 210)
+#define __NR_SVR4_MIPS_reserved3        (__NR_SVR4 + 211)
+#define __NR_SVR4_MIPS_reserved4        (__NR_SVR4 + 212)
+#define __NR_SVR4_MIPS_reserved5        (__NR_SVR4 + 213)
+#define __NR_SVR4_MIPS_reserved6        (__NR_SVR4 + 214)
+#define __NR_SVR4_MIPS_reserved7        (__NR_SVR4 + 215)
+#define __NR_SVR4_MIPS_reserved8        (__NR_SVR4 + 216)
+#define __NR_SVR4_MIPS_reserved9        (__NR_SVR4 + 217)
+#define __NR_SVR4_MIPS_reserved10       (__NR_SVR4 + 218)
+#define __NR_SVR4_MIPS_reserved11       (__NR_SVR4 + 219)
+#define __NR_SVR4_MIPS_reserved12       (__NR_SVR4 + 220)
+#define __NR_SVR4_CDC_reserved1         (__NR_SVR4 + 221)
+#define __NR_SVR4_CDC_reserved2         (__NR_SVR4 + 222)
+#define __NR_SVR4_CDC_reserved3         (__NR_SVR4 + 223)
+#define __NR_SVR4_CDC_reserved4         (__NR_SVR4 + 224)
+#define __NR_SVR4_CDC_reserved5         (__NR_SVR4 + 225)
+#define __NR_SVR4_CDC_reserved6         (__NR_SVR4 + 226)
+#define __NR_SVR4_CDC_reserved7         (__NR_SVR4 + 227)
+#define __NR_SVR4_CDC_reserved8         (__NR_SVR4 + 228)
+#define __NR_SVR4_CDC_reserved9         (__NR_SVR4 + 229)
+#define __NR_SVR4_CDC_reserved10        (__NR_SVR4 + 230)
+#define __NR_SVR4_CDC_reserved11        (__NR_SVR4 + 231)
+#define __NR_SVR4_CDC_reserved12        (__NR_SVR4 + 232)
+#define __NR_SVR4_CDC_reserved13        (__NR_SVR4 + 233)
+#define __NR_SVR4_CDC_reserved14        (__NR_SVR4 + 234)
+#define __NR_SVR4_CDC_reserved15        (__NR_SVR4 + 235)
+#define __NR_SVR4_CDC_reserved16        (__NR_SVR4 + 236)
+#define __NR_SVR4_CDC_reserved17        (__NR_SVR4 + 237)
+#define __NR_SVR4_CDC_reserved18        (__NR_SVR4 + 238)
+#define __NR_SVR4_CDC_reserved19        (__NR_SVR4 + 239)
+#define __NR_SVR4_CDC_reserved20        (__NR_SVR4 + 240)
+
+/*
+ * SYS V syscalls are in the range from 1000 to 1999
+ */
+#define __NR_SYSV                       1000
+#define __NR_SYSV_syscall               (__NR_SYSV +   0)
+#define __NR_SYSV_exit                  (__NR_SYSV +   1)
+#define __NR_SYSV_fork                  (__NR_SYSV +   2)
+#define __NR_SYSV_read                  (__NR_SYSV +   3)
+#define __NR_SYSV_write                 (__NR_SYSV +   4)
+#define __NR_SYSV_open                  (__NR_SYSV +   5)
+#define __NR_SYSV_close                 (__NR_SYSV +   6)
+#define __NR_SYSV_wait                  (__NR_SYSV +   7)
+#define __NR_SYSV_creat                 (__NR_SYSV +   8)
+#define __NR_SYSV_link                  (__NR_SYSV +   9)
+#define __NR_SYSV_unlink                (__NR_SYSV +  10)
+#define __NR_SYSV_execv                 (__NR_SYSV +  11)
+#define __NR_SYSV_chdir                 (__NR_SYSV +  12)
+#define __NR_SYSV_time                  (__NR_SYSV +  13)
+#define __NR_SYSV_mknod                 (__NR_SYSV +  14)
+#define __NR_SYSV_chmod                 (__NR_SYSV +  15)
+#define __NR_SYSV_chown                 (__NR_SYSV +  16)
+#define __NR_SYSV_brk                   (__NR_SYSV +  17)
+#define __NR_SYSV_stat                  (__NR_SYSV +  18)
+#define __NR_SYSV_lseek                 (__NR_SYSV +  19)
+#define __NR_SYSV_getpid                (__NR_SYSV +  20)
+#define __NR_SYSV_mount                 (__NR_SYSV +  21)
+#define __NR_SYSV_umount                (__NR_SYSV +  22)
+#define __NR_SYSV_setuid                (__NR_SYSV +  23)
+#define __NR_SYSV_getuid                (__NR_SYSV +  24)
+#define __NR_SYSV_stime                 (__NR_SYSV +  25)
+#define __NR_SYSV_ptrace                (__NR_SYSV +  26)
+#define __NR_SYSV_alarm                 (__NR_SYSV +  27)
+#define __NR_SYSV_fstat                 (__NR_SYSV +  28)
+#define __NR_SYSV_pause                 (__NR_SYSV +  29)
+#define __NR_SYSV_utime                 (__NR_SYSV +  30)
+#define __NR_SYSV_stty                  (__NR_SYSV +  31)
+#define __NR_SYSV_gtty                  (__NR_SYSV +  32)
+#define __NR_SYSV_access                (__NR_SYSV +  33)
+#define __NR_SYSV_nice                  (__NR_SYSV +  34)
+#define __NR_SYSV_statfs                (__NR_SYSV +  35)
+#define __NR_SYSV_sync                  (__NR_SYSV +  36)
+#define __NR_SYSV_kill                  (__NR_SYSV +  37)
+#define __NR_SYSV_fstatfs               (__NR_SYSV +  38)
+#define __NR_SYSV_setpgrp               (__NR_SYSV +  39)
+#define __NR_SYSV_syssgi                (__NR_SYSV +  40)
+#define __NR_SYSV_dup                   (__NR_SYSV +  41)
+#define __NR_SYSV_pipe                  (__NR_SYSV +  42)
+#define __NR_SYSV_times                 (__NR_SYSV +  43)
+#define __NR_SYSV_profil                (__NR_SYSV +  44)
+#define __NR_SYSV_plock                 (__NR_SYSV +  45)
+#define __NR_SYSV_setgid                (__NR_SYSV +  46)
+#define __NR_SYSV_getgid                (__NR_SYSV +  47)
+#define __NR_SYSV_sig                   (__NR_SYSV +  48)
+#define __NR_SYSV_msgsys                (__NR_SYSV +  49)
+#define __NR_SYSV_sysmips               (__NR_SYSV +  50)
+#define __NR_SYSV_acct                  (__NR_SYSV +  51)
+#define __NR_SYSV_shmsys                (__NR_SYSV +  52)
+#define __NR_SYSV_semsys                (__NR_SYSV +  53)
+#define __NR_SYSV_ioctl                 (__NR_SYSV +  54)
+#define __NR_SYSV_uadmin                (__NR_SYSV +  55)
+#define __NR_SYSV_sysmp                 (__NR_SYSV +  56)
+#define __NR_SYSV_utssys                (__NR_SYSV +  57)
+#define __NR_SYSV_USG_reserved1         (__NR_SYSV +  58)
+#define __NR_SYSV_execve                (__NR_SYSV +  59)
+#define __NR_SYSV_umask                 (__NR_SYSV +  60)
+#define __NR_SYSV_chroot                (__NR_SYSV +  61)
+#define __NR_SYSV_fcntl                 (__NR_SYSV +  62)
+#define __NR_SYSV_ulimit                (__NR_SYSV +  63)
+#define __NR_SYSV_SAFARI4_reserved1     (__NR_SYSV +  64)
+#define __NR_SYSV_SAFARI4_reserved2     (__NR_SYSV +  65)
+#define __NR_SYSV_SAFARI4_reserved3     (__NR_SYSV +  66)
+#define __NR_SYSV_SAFARI4_reserved4     (__NR_SYSV +  67)
+#define __NR_SYSV_SAFARI4_reserved5     (__NR_SYSV +  68)
+#define __NR_SYSV_SAFARI4_reserved6     (__NR_SYSV +  69)
+#define __NR_SYSV_advfs                 (__NR_SYSV +  70)
+#define __NR_SYSV_unadvfs               (__NR_SYSV +  71)
+#define __NR_SYSV_rmount                (__NR_SYSV +  72)
+#define __NR_SYSV_rumount               (__NR_SYSV +  73)
+#define __NR_SYSV_rfstart               (__NR_SYSV +  74)
+#define __NR_SYSV_getrlimit64           (__NR_SYSV +  75)
+#define __NR_SYSV_setrlimit64           (__NR_SYSV +  76)
+#define __NR_SYSV_nanosleep             (__NR_SYSV +  77)
+#define __NR_SYSV_lseek64               (__NR_SYSV +  78)
+#define __NR_SYSV_rmdir                 (__NR_SYSV +  79)
+#define __NR_SYSV_mkdir                 (__NR_SYSV +  80)
+#define __NR_SYSV_getdents              (__NR_SYSV +  81)
+#define __NR_SYSV_sginap                (__NR_SYSV +  82)
+#define __NR_SYSV_sgikopt               (__NR_SYSV +  83)
+#define __NR_SYSV_sysfs                 (__NR_SYSV +  84)
+#define __NR_SYSV_getmsg                (__NR_SYSV +  85)
+#define __NR_SYSV_putmsg                (__NR_SYSV +  86)
+#define __NR_SYSV_poll                  (__NR_SYSV +  87)
+#define __NR_SYSV_sigreturn             (__NR_SYSV +  88)
+#define __NR_SYSV_accept                (__NR_SYSV +  89)
+#define __NR_SYSV_bind                  (__NR_SYSV +  90)
+#define __NR_SYSV_connect               (__NR_SYSV +  91)
+#define __NR_SYSV_gethostid             (__NR_SYSV +  92)
+#define __NR_SYSV_getpeername           (__NR_SYSV +  93)
+#define __NR_SYSV_getsockname           (__NR_SYSV +  94)
+#define __NR_SYSV_getsockopt            (__NR_SYSV +  95)
+#define __NR_SYSV_listen                (__NR_SYSV +  96)
+#define __NR_SYSV_recv                  (__NR_SYSV +  97)
+#define __NR_SYSV_recvfrom              (__NR_SYSV +  98)
+#define __NR_SYSV_recvmsg               (__NR_SYSV +  99)
+#define __NR_SYSV_select                (__NR_SYSV + 100)
+#define __NR_SYSV_send                  (__NR_SYSV + 101)
+#define __NR_SYSV_sendmsg               (__NR_SYSV + 102)
+#define __NR_SYSV_sendto                (__NR_SYSV + 103)
+#define __NR_SYSV_sethostid             (__NR_SYSV + 104)
+#define __NR_SYSV_setsockopt            (__NR_SYSV + 105)
+#define __NR_SYSV_shutdown              (__NR_SYSV + 106)
+#define __NR_SYSV_socket                (__NR_SYSV + 107)
+#define __NR_SYSV_gethostname           (__NR_SYSV + 108)
+#define __NR_SYSV_sethostname           (__NR_SYSV + 109)
+#define __NR_SYSV_getdomainname         (__NR_SYSV + 110)
+#define __NR_SYSV_setdomainname         (__NR_SYSV + 111)
+#define __NR_SYSV_truncate              (__NR_SYSV + 112)
+#define __NR_SYSV_ftruncate             (__NR_SYSV + 113)
+#define __NR_SYSV_rename                (__NR_SYSV + 114)
+#define __NR_SYSV_symlink               (__NR_SYSV + 115)
+#define __NR_SYSV_readlink              (__NR_SYSV + 116)
+#define __NR_SYSV_lstat                 (__NR_SYSV + 117)
+#define __NR_SYSV_nfsmount              (__NR_SYSV + 118)
+#define __NR_SYSV_nfssvc                (__NR_SYSV + 119)
+#define __NR_SYSV_getfh                 (__NR_SYSV + 120)
+#define __NR_SYSV_async_daemon          (__NR_SYSV + 121)
+#define __NR_SYSV_exportfs              (__NR_SYSV + 122)
+#define __NR_SYSV_setregid              (__NR_SYSV + 123)
+#define __NR_SYSV_setreuid              (__NR_SYSV + 124)
+#define __NR_SYSV_getitimer             (__NR_SYSV + 125)
+#define __NR_SYSV_setitimer             (__NR_SYSV + 126)
+#define __NR_SYSV_adjtime               (__NR_SYSV + 127)
+#define __NR_SYSV_BSD_getime            (__NR_SYSV + 128)
+#define __NR_SYSV_sproc                 (__NR_SYSV + 129)
+#define __NR_SYSV_prctl                 (__NR_SYSV + 130)
+#define __NR_SYSV_procblk               (__NR_SYSV + 131)
+#define __NR_SYSV_sprocsp               (__NR_SYSV + 132)
+#define __NR_SYSV_sgigsc                (__NR_SYSV + 133)
+#define __NR_SYSV_mmap                  (__NR_SYSV + 134)
+#define __NR_SYSV_munmap                (__NR_SYSV + 135)
+#define __NR_SYSV_mprotect              (__NR_SYSV + 136)
+#define __NR_SYSV_msync                 (__NR_SYSV + 137)
+#define __NR_SYSV_madvise               (__NR_SYSV + 138)
+#define __NR_SYSV_pagelock              (__NR_SYSV + 139)
+#define __NR_SYSV_getpagesize           (__NR_SYSV + 140)
+#define __NR_SYSV_quotactl              (__NR_SYSV + 141)
+#define __NR_SYSV_libdetach             (__NR_SYSV + 142)
+#define __NR_SYSV_BSDgetpgrp            (__NR_SYSV + 143)
+#define __NR_SYSV_BSDsetpgrp            (__NR_SYSV + 144)
+#define __NR_SYSV_vhangup               (__NR_SYSV + 145)
+#define __NR_SYSV_fsync                 (__NR_SYSV + 146)
+#define __NR_SYSV_fchdir                (__NR_SYSV + 147)
+#define __NR_SYSV_getrlimit             (__NR_SYSV + 148)
+#define __NR_SYSV_setrlimit             (__NR_SYSV + 149)
+#define __NR_SYSV_cacheflush            (__NR_SYSV + 150)
+#define __NR_SYSV_cachectl              (__NR_SYSV + 151)
+#define __NR_SYSV_fchown                (__NR_SYSV + 152)
+#define __NR_SYSV_fchmod                (__NR_SYSV + 153)
+#define __NR_SYSV_wait3                 (__NR_SYSV + 154)
+#define __NR_SYSV_socketpair            (__NR_SYSV + 155)
+#define __NR_SYSV_sysinfo               (__NR_SYSV + 156)
+#define __NR_SYSV_nuname                (__NR_SYSV + 157)
+#define __NR_SYSV_xstat                 (__NR_SYSV + 158)
+#define __NR_SYSV_lxstat                (__NR_SYSV + 159)
+#define __NR_SYSV_fxstat                (__NR_SYSV + 160)
+#define __NR_SYSV_xmknod                (__NR_SYSV + 161)
+#define __NR_SYSV_ksigaction            (__NR_SYSV + 162)
+#define __NR_SYSV_sigpending            (__NR_SYSV + 163)
+#define __NR_SYSV_sigprocmask           (__NR_SYSV + 164)
+#define __NR_SYSV_sigsuspend            (__NR_SYSV + 165)
+#define __NR_SYSV_sigpoll               (__NR_SYSV + 166)
+#define __NR_SYSV_swapctl               (__NR_SYSV + 167)
+#define __NR_SYSV_getcontext            (__NR_SYSV + 168)
+#define __NR_SYSV_setcontext            (__NR_SYSV + 169)
+#define __NR_SYSV_waitsys               (__NR_SYSV + 170)
+#define __NR_SYSV_sigstack              (__NR_SYSV + 171)
+#define __NR_SYSV_sigaltstack           (__NR_SYSV + 172)
+#define __NR_SYSV_sigsendset            (__NR_SYSV + 173)
+#define __NR_SYSV_statvfs               (__NR_SYSV + 174)
+#define __NR_SYSV_fstatvfs              (__NR_SYSV + 175)
+#define __NR_SYSV_getpmsg               (__NR_SYSV + 176)
+#define __NR_SYSV_putpmsg               (__NR_SYSV + 177)
+#define __NR_SYSV_lchown                (__NR_SYSV + 178)
+#define __NR_SYSV_priocntl              (__NR_SYSV + 179)
+#define __NR_SYSV_ksigqueue             (__NR_SYSV + 180)
+#define __NR_SYSV_readv                 (__NR_SYSV + 181)
+#define __NR_SYSV_writev                (__NR_SYSV + 182)
+#define __NR_SYSV_truncate64            (__NR_SYSV + 183)
+#define __NR_SYSV_ftruncate64           (__NR_SYSV + 184)
+#define __NR_SYSV_mmap64                (__NR_SYSV + 185)
+#define __NR_SYSV_dmi                   (__NR_SYSV + 186)
+#define __NR_SYSV_pread                 (__NR_SYSV + 187)
+#define __NR_SYSV_pwrite                (__NR_SYSV + 188)
+
+/*
+ * BSD 4.3 syscalls are in the range from 2000 to 2999
+ */
+#define __NR_BSD43                      2000
+#define __NR_BSD43_syscall              (__NR_BSD43 +   0)
+#define __NR_BSD43_exit                 (__NR_BSD43 +   1)
+#define __NR_BSD43_fork                 (__NR_BSD43 +   2)
+#define __NR_BSD43_read                 (__NR_BSD43 +   3)
+#define __NR_BSD43_write                (__NR_BSD43 +   4)
+#define __NR_BSD43_open                 (__NR_BSD43 +   5)
+#define __NR_BSD43_close                (__NR_BSD43 +   6)
+#define __NR_BSD43_wait                 (__NR_BSD43 +   7)
+#define __NR_BSD43_creat                (__NR_BSD43 +   8)
+#define __NR_BSD43_link                 (__NR_BSD43 +   9)
+#define __NR_BSD43_unlink               (__NR_BSD43 +  10)
+#define __NR_BSD43_exec                 (__NR_BSD43 +  11)
+#define __NR_BSD43_chdir                (__NR_BSD43 +  12)
+#define __NR_BSD43_time                 (__NR_BSD43 +  13)
+#define __NR_BSD43_mknod                (__NR_BSD43 +  14)
+#define __NR_BSD43_chmod                (__NR_BSD43 +  15)
+#define __NR_BSD43_chown                (__NR_BSD43 +  16)
+#define __NR_BSD43_sbreak               (__NR_BSD43 +  17)
+#define __NR_BSD43_oldstat              (__NR_BSD43 +  18)
+#define __NR_BSD43_lseek                (__NR_BSD43 +  19)
+#define __NR_BSD43_getpid               (__NR_BSD43 +  20)
+#define __NR_BSD43_oldmount             (__NR_BSD43 +  21)
+#define __NR_BSD43_umount               (__NR_BSD43 +  22)
+#define __NR_BSD43_setuid               (__NR_BSD43 +  23)
+#define __NR_BSD43_getuid               (__NR_BSD43 +  24)
+#define __NR_BSD43_stime                (__NR_BSD43 +  25)
+#define __NR_BSD43_ptrace               (__NR_BSD43 +  26)
+#define __NR_BSD43_alarm                (__NR_BSD43 +  27)
+#define __NR_BSD43_oldfstat             (__NR_BSD43 +  28)
+#define __NR_BSD43_pause                (__NR_BSD43 +  29)
+#define __NR_BSD43_utime                (__NR_BSD43 +  30)
+#define __NR_BSD43_stty                 (__NR_BSD43 +  31)
+#define __NR_BSD43_gtty                 (__NR_BSD43 +  32)
+#define __NR_BSD43_access               (__NR_BSD43 +  33)
+#define __NR_BSD43_nice                 (__NR_BSD43 +  34)
+#define __NR_BSD43_ftime                (__NR_BSD43 +  35)
+#define __NR_BSD43_sync                 (__NR_BSD43 +  36)
+#define __NR_BSD43_kill                 (__NR_BSD43 +  37)
+#define __NR_BSD43_stat                 (__NR_BSD43 +  38)
+#define __NR_BSD43_oldsetpgrp           (__NR_BSD43 +  39)
+#define __NR_BSD43_lstat                (__NR_BSD43 +  40)
+#define __NR_BSD43_dup                  (__NR_BSD43 +  41)
+#define __NR_BSD43_pipe                 (__NR_BSD43 +  42)
+#define __NR_BSD43_times                (__NR_BSD43 +  43)
+#define __NR_BSD43_profil               (__NR_BSD43 +  44)
+#define __NR_BSD43_msgsys               (__NR_BSD43 +  45)
+#define __NR_BSD43_setgid               (__NR_BSD43 +  46)
+#define __NR_BSD43_getgid               (__NR_BSD43 +  47)
+#define __NR_BSD43_ssig                 (__NR_BSD43 +  48)
+#define __NR_BSD43_reserved1            (__NR_BSD43 +  49)
+#define __NR_BSD43_reserved2            (__NR_BSD43 +  50)
+#define __NR_BSD43_sysacct              (__NR_BSD43 +  51)
+#define __NR_BSD43_phys                 (__NR_BSD43 +  52)
+#define __NR_BSD43_lock                 (__NR_BSD43 +  53)
+#define __NR_BSD43_ioctl                (__NR_BSD43 +  54)
+#define __NR_BSD43_reboot               (__NR_BSD43 +  55)
+#define __NR_BSD43_mpxchan              (__NR_BSD43 +  56)
+#define __NR_BSD43_symlink              (__NR_BSD43 +  57)
+#define __NR_BSD43_readlink             (__NR_BSD43 +  58)
+#define __NR_BSD43_execve               (__NR_BSD43 +  59)
+#define __NR_BSD43_umask                (__NR_BSD43 +  60)
+#define __NR_BSD43_chroot               (__NR_BSD43 +  61)
+#define __NR_BSD43_fstat                (__NR_BSD43 +  62)
+#define __NR_BSD43_reserved3            (__NR_BSD43 +  63)
+#define __NR_BSD43_getpagesize          (__NR_BSD43 +  64)
+#define __NR_BSD43_mremap               (__NR_BSD43 +  65)
+#define __NR_BSD43_vfork                (__NR_BSD43 +  66)
+#define __NR_BSD43_vread                (__NR_BSD43 +  67)
+#define __NR_BSD43_vwrite               (__NR_BSD43 +  68)
+#define __NR_BSD43_sbrk                 (__NR_BSD43 +  69)
+#define __NR_BSD43_sstk                 (__NR_BSD43 +  70)
+#define __NR_BSD43_mmap                 (__NR_BSD43 +  71)
+#define __NR_BSD43_vadvise              (__NR_BSD43 +  72)
+#define __NR_BSD43_munmap               (__NR_BSD43 +  73)
+#define __NR_BSD43_mprotect             (__NR_BSD43 +  74)
+#define __NR_BSD43_madvise              (__NR_BSD43 +  75)
+#define __NR_BSD43_vhangup              (__NR_BSD43 +  76)
+#define __NR_BSD43_vlimit               (__NR_BSD43 +  77)
+#define __NR_BSD43_mincore              (__NR_BSD43 +  78)
+#define __NR_BSD43_getgroups            (__NR_BSD43 +  79)
+#define __NR_BSD43_setgroups            (__NR_BSD43 +  80)
+#define __NR_BSD43_getpgrp              (__NR_BSD43 +  81)
+#define __NR_BSD43_setpgrp              (__NR_BSD43 +  82)
+#define __NR_BSD43_setitimer            (__NR_BSD43 +  83)
+#define __NR_BSD43_wait3                (__NR_BSD43 +  84)
+#define __NR_BSD43_swapon               (__NR_BSD43 +  85)
+#define __NR_BSD43_getitimer            (__NR_BSD43 +  86)
+#define __NR_BSD43_gethostname          (__NR_BSD43 +  87)
+#define __NR_BSD43_sethostname          (__NR_BSD43 +  88)
+#define __NR_BSD43_getdtablesize        (__NR_BSD43 +  89)
+#define __NR_BSD43_dup2                 (__NR_BSD43 +  90)
+#define __NR_BSD43_getdopt              (__NR_BSD43 +  91)
+#define __NR_BSD43_fcntl                (__NR_BSD43 +  92)
+#define __NR_BSD43_select               (__NR_BSD43 +  93)
+#define __NR_BSD43_setdopt              (__NR_BSD43 +  94)
+#define __NR_BSD43_fsync                (__NR_BSD43 +  95)
+#define __NR_BSD43_setpriority          (__NR_BSD43 +  96)
+#define __NR_BSD43_socket               (__NR_BSD43 +  97)
+#define __NR_BSD43_connect              (__NR_BSD43 +  98)
+#define __NR_BSD43_oldaccept            (__NR_BSD43 +  99)
+#define __NR_BSD43_getpriority          (__NR_BSD43 + 100)
+#define __NR_BSD43_send                 (__NR_BSD43 + 101)
+#define __NR_BSD43_recv                 (__NR_BSD43 + 102)
+#define __NR_BSD43_sigreturn            (__NR_BSD43 + 103)
+#define __NR_BSD43_bind                 (__NR_BSD43 + 104)
+#define __NR_BSD43_setsockopt           (__NR_BSD43 + 105)
+#define __NR_BSD43_listen               (__NR_BSD43 + 106)
+#define __NR_BSD43_vtimes               (__NR_BSD43 + 107)
+#define __NR_BSD43_sigvec               (__NR_BSD43 + 108)
+#define __NR_BSD43_sigblock             (__NR_BSD43 + 109)
+#define __NR_BSD43_sigsetmask           (__NR_BSD43 + 110)
+#define __NR_BSD43_sigpause             (__NR_BSD43 + 111)
+#define __NR_BSD43_sigstack             (__NR_BSD43 + 112)
+#define __NR_BSD43_oldrecvmsg           (__NR_BSD43 + 113)
+#define __NR_BSD43_oldsendmsg           (__NR_BSD43 + 114)
+#define __NR_BSD43_vtrace               (__NR_BSD43 + 115)
+#define __NR_BSD43_gettimeofday         (__NR_BSD43 + 116)
+#define __NR_BSD43_getrusage            (__NR_BSD43 + 117)
+#define __NR_BSD43_getsockopt           (__NR_BSD43 + 118)
+#define __NR_BSD43_reserved4            (__NR_BSD43 + 119)
+#define __NR_BSD43_readv                (__NR_BSD43 + 120)
+#define __NR_BSD43_writev               (__NR_BSD43 + 121)
+#define __NR_BSD43_settimeofday         (__NR_BSD43 + 122)
+#define __NR_BSD43_fchown               (__NR_BSD43 + 123)
+#define __NR_BSD43_fchmod               (__NR_BSD43 + 124)
+#define __NR_BSD43_oldrecvfrom          (__NR_BSD43 + 125)
+#define __NR_BSD43_setreuid             (__NR_BSD43 + 126)
+#define __NR_BSD43_setregid             (__NR_BSD43 + 127)
+#define __NR_BSD43_rename               (__NR_BSD43 + 128)
+#define __NR_BSD43_truncate             (__NR_BSD43 + 129)
+#define __NR_BSD43_ftruncate            (__NR_BSD43 + 130)
+#define __NR_BSD43_flock                (__NR_BSD43 + 131)
+#define __NR_BSD43_semsys               (__NR_BSD43 + 132)
+#define __NR_BSD43_sendto               (__NR_BSD43 + 133)
+#define __NR_BSD43_shutdown             (__NR_BSD43 + 134)
+#define __NR_BSD43_socketpair           (__NR_BSD43 + 135)
+#define __NR_BSD43_mkdir                (__NR_BSD43 + 136)
+#define __NR_BSD43_rmdir                (__NR_BSD43 + 137)
+#define __NR_BSD43_utimes               (__NR_BSD43 + 138)
+#define __NR_BSD43_sigcleanup           (__NR_BSD43 + 139)
+#define __NR_BSD43_adjtime              (__NR_BSD43 + 140)
+#define __NR_BSD43_oldgetpeername       (__NR_BSD43 + 141)
+#define __NR_BSD43_gethostid            (__NR_BSD43 + 142)
+#define __NR_BSD43_sethostid            (__NR_BSD43 + 143)
+#define __NR_BSD43_getrlimit            (__NR_BSD43 + 144)
+#define __NR_BSD43_setrlimit            (__NR_BSD43 + 145)
+#define __NR_BSD43_killpg               (__NR_BSD43 + 146)
+#define __NR_BSD43_shmsys               (__NR_BSD43 + 147)
+#define __NR_BSD43_quota                (__NR_BSD43 + 148)
+#define __NR_BSD43_qquota               (__NR_BSD43 + 149)
+#define __NR_BSD43_oldgetsockname       (__NR_BSD43 + 150)
+#define __NR_BSD43_sysmips              (__NR_BSD43 + 151)
+#define __NR_BSD43_cacheflush           (__NR_BSD43 + 152)
+#define __NR_BSD43_cachectl             (__NR_BSD43 + 153)
+#define __NR_BSD43_debug                (__NR_BSD43 + 154)
+#define __NR_BSD43_reserved5            (__NR_BSD43 + 155)
+#define __NR_BSD43_reserved6            (__NR_BSD43 + 156)
+#define __NR_BSD43_nfs_mount            (__NR_BSD43 + 157)
+#define __NR_BSD43_nfs_svc              (__NR_BSD43 + 158)
+#define __NR_BSD43_getdirentries        (__NR_BSD43 + 159)
+#define __NR_BSD43_statfs               (__NR_BSD43 + 160)
+#define __NR_BSD43_fstatfs              (__NR_BSD43 + 161)
+#define __NR_BSD43_unmount              (__NR_BSD43 + 162)
+#define __NR_BSD43_async_daemon         (__NR_BSD43 + 163)
+#define __NR_BSD43_nfs_getfh            (__NR_BSD43 + 164)
+#define __NR_BSD43_getdomainname        (__NR_BSD43 + 165)
+#define __NR_BSD43_setdomainname        (__NR_BSD43 + 166)
+#define __NR_BSD43_pcfs_mount           (__NR_BSD43 + 167)
+#define __NR_BSD43_quotactl             (__NR_BSD43 + 168)
+#define __NR_BSD43_oldexportfs          (__NR_BSD43 + 169)
+#define __NR_BSD43_smount               (__NR_BSD43 + 170)
+#define __NR_BSD43_mipshwconf           (__NR_BSD43 + 171)
+#define __NR_BSD43_exportfs             (__NR_BSD43 + 172)
+#define __NR_BSD43_nfsfh_open           (__NR_BSD43 + 173)
+#define __NR_BSD43_libattach            (__NR_BSD43 + 174)
+#define __NR_BSD43_libdetach            (__NR_BSD43 + 175)
+#define __NR_BSD43_accept               (__NR_BSD43 + 176)
+#define __NR_BSD43_reserved7            (__NR_BSD43 + 177)
+#define __NR_BSD43_reserved8            (__NR_BSD43 + 178)
+#define __NR_BSD43_recvmsg              (__NR_BSD43 + 179)
+#define __NR_BSD43_recvfrom             (__NR_BSD43 + 180)
+#define __NR_BSD43_sendmsg              (__NR_BSD43 + 181)
+#define __NR_BSD43_getpeername          (__NR_BSD43 + 182)
+#define __NR_BSD43_getsockname          (__NR_BSD43 + 183)
+#define __NR_BSD43_aread                (__NR_BSD43 + 184)
+#define __NR_BSD43_awrite               (__NR_BSD43 + 185)
+#define __NR_BSD43_listio               (__NR_BSD43 + 186)
+#define __NR_BSD43_acancel              (__NR_BSD43 + 187)
+#define __NR_BSD43_astatus              (__NR_BSD43 + 188)
+#define __NR_BSD43_await                (__NR_BSD43 + 189)
+#define __NR_BSD43_areadv               (__NR_BSD43 + 190)
+#define __NR_BSD43_awritev              (__NR_BSD43 + 191)
+
+/*
+ * POSIX syscalls are in the range from 3000 to 3999
+ */
+#define __NR_POSIX                      3000
+#define __NR_POSIX_syscall              (__NR_POSIX +   0)
+#define __NR_POSIX_exit                 (__NR_POSIX +   1)
+#define __NR_POSIX_fork                 (__NR_POSIX +   2)
+#define __NR_POSIX_read                 (__NR_POSIX +   3)
+#define __NR_POSIX_write                (__NR_POSIX +   4)
+#define __NR_POSIX_open                 (__NR_POSIX +   5)
+#define __NR_POSIX_close                (__NR_POSIX +   6)
+#define __NR_POSIX_wait                 (__NR_POSIX +   7)
+#define __NR_POSIX_creat                (__NR_POSIX +   8)
+#define __NR_POSIX_link                 (__NR_POSIX +   9)
+#define __NR_POSIX_unlink               (__NR_POSIX +  10)
+#define __NR_POSIX_exec                 (__NR_POSIX +  11)
+#define __NR_POSIX_chdir                (__NR_POSIX +  12)
+#define __NR_POSIX_gtime                (__NR_POSIX +  13)
+#define __NR_POSIX_mknod                (__NR_POSIX +  14)
+#define __NR_POSIX_chmod                (__NR_POSIX +  15)
+#define __NR_POSIX_chown                (__NR_POSIX +  16)
+#define __NR_POSIX_sbreak               (__NR_POSIX +  17)
+#define __NR_POSIX_stat                 (__NR_POSIX +  18)
+#define __NR_POSIX_lseek                (__NR_POSIX +  19)
+#define __NR_POSIX_getpid               (__NR_POSIX +  20)
+#define __NR_POSIX_mount                (__NR_POSIX +  21)
+#define __NR_POSIX_umount               (__NR_POSIX +  22)
+#define __NR_POSIX_setuid               (__NR_POSIX +  23)
+#define __NR_POSIX_getuid               (__NR_POSIX +  24)
+#define __NR_POSIX_stime                (__NR_POSIX +  25)
+#define __NR_POSIX_ptrace               (__NR_POSIX +  26)
+#define __NR_POSIX_alarm                (__NR_POSIX +  27)
+#define __NR_POSIX_fstat                (__NR_POSIX +  28)
+#define __NR_POSIX_pause                (__NR_POSIX +  29)
+#define __NR_POSIX_utime                (__NR_POSIX +  30)
+#define __NR_POSIX_stty                 (__NR_POSIX +  31)
+#define __NR_POSIX_gtty                 (__NR_POSIX +  32)
+#define __NR_POSIX_access               (__NR_POSIX +  33)
+#define __NR_POSIX_nice                 (__NR_POSIX +  34)
+#define __NR_POSIX_statfs               (__NR_POSIX +  35)
+#define __NR_POSIX_sync                 (__NR_POSIX +  36)
+#define __NR_POSIX_kill                 (__NR_POSIX +  37)
+#define __NR_POSIX_fstatfs              (__NR_POSIX +  38)
+#define __NR_POSIX_getpgrp              (__NR_POSIX +  39)
+#define __NR_POSIX_syssgi               (__NR_POSIX +  40)
+#define __NR_POSIX_dup                  (__NR_POSIX +  41)
+#define __NR_POSIX_pipe                 (__NR_POSIX +  42)
+#define __NR_POSIX_times                (__NR_POSIX +  43)
+#define __NR_POSIX_profil               (__NR_POSIX +  44)
+#define __NR_POSIX_lock                 (__NR_POSIX +  45)
+#define __NR_POSIX_setgid               (__NR_POSIX +  46)
+#define __NR_POSIX_getgid               (__NR_POSIX +  47)
+#define __NR_POSIX_sig                  (__NR_POSIX +  48)
+#define __NR_POSIX_msgsys               (__NR_POSIX +  49)
+#define __NR_POSIX_sysmips              (__NR_POSIX +  50)
+#define __NR_POSIX_sysacct              (__NR_POSIX +  51)
+#define __NR_POSIX_shmsys               (__NR_POSIX +  52)
+#define __NR_POSIX_semsys               (__NR_POSIX +  53)
+#define __NR_POSIX_ioctl                (__NR_POSIX +  54)
+#define __NR_POSIX_uadmin               (__NR_POSIX +  55)
+#define __NR_POSIX_exch                 (__NR_POSIX +  56)
+#define __NR_POSIX_utssys               (__NR_POSIX +  57)
+#define __NR_POSIX_USG_reserved1        (__NR_POSIX +  58)
+#define __NR_POSIX_exece                (__NR_POSIX +  59)
+#define __NR_POSIX_umask                (__NR_POSIX +  60)
+#define __NR_POSIX_chroot               (__NR_POSIX +  61)
+#define __NR_POSIX_fcntl                (__NR_POSIX +  62)
+#define __NR_POSIX_ulimit               (__NR_POSIX +  63)
+#define __NR_POSIX_SAFARI4_reserved1    (__NR_POSIX +  64)
+#define __NR_POSIX_SAFARI4_reserved2    (__NR_POSIX +  65)
+#define __NR_POSIX_SAFARI4_reserved3    (__NR_POSIX +  66)
+#define __NR_POSIX_SAFARI4_reserved4    (__NR_POSIX +  67)
+#define __NR_POSIX_SAFARI4_reserved5    (__NR_POSIX +  68)
+#define __NR_POSIX_SAFARI4_reserved6    (__NR_POSIX +  69)
+#define __NR_POSIX_advfs                (__NR_POSIX +  70)
+#define __NR_POSIX_unadvfs              (__NR_POSIX +  71)
+#define __NR_POSIX_rmount               (__NR_POSIX +  72)
+#define __NR_POSIX_rumount              (__NR_POSIX +  73)
+#define __NR_POSIX_rfstart              (__NR_POSIX +  74)
+#define __NR_POSIX_reserved1            (__NR_POSIX +  75)
+#define __NR_POSIX_rdebug               (__NR_POSIX +  76)
+#define __NR_POSIX_rfstop               (__NR_POSIX +  77)
+#define __NR_POSIX_rfsys                (__NR_POSIX +  78)
+#define __NR_POSIX_rmdir                (__NR_POSIX +  79)
+#define __NR_POSIX_mkdir                (__NR_POSIX +  80)
+#define __NR_POSIX_getdents             (__NR_POSIX +  81)
+#define __NR_POSIX_sginap               (__NR_POSIX +  82)
+#define __NR_POSIX_sgikopt              (__NR_POSIX +  83)
+#define __NR_POSIX_sysfs                (__NR_POSIX +  84)
+#define __NR_POSIX_getmsg               (__NR_POSIX +  85)
+#define __NR_POSIX_putmsg               (__NR_POSIX +  86)
+#define __NR_POSIX_poll                 (__NR_POSIX +  87)
+#define __NR_POSIX_sigreturn            (__NR_POSIX +  88)
+#define __NR_POSIX_accept               (__NR_POSIX +  89)
+#define __NR_POSIX_bind                 (__NR_POSIX +  90)
+#define __NR_POSIX_connect              (__NR_POSIX +  91)
+#define __NR_POSIX_gethostid            (__NR_POSIX +  92)
+#define __NR_POSIX_getpeername          (__NR_POSIX +  93)
+#define __NR_POSIX_getsockname          (__NR_POSIX +  94)
+#define __NR_POSIX_getsockopt           (__NR_POSIX +  95)
+#define __NR_POSIX_listen               (__NR_POSIX +  96)
+#define __NR_POSIX_recv                 (__NR_POSIX +  97)
+#define __NR_POSIX_recvfrom             (__NR_POSIX +  98)
+#define __NR_POSIX_recvmsg              (__NR_POSIX +  99)
+#define __NR_POSIX_select               (__NR_POSIX + 100)
+#define __NR_POSIX_send                 (__NR_POSIX + 101)
+#define __NR_POSIX_sendmsg              (__NR_POSIX + 102)
+#define __NR_POSIX_sendto               (__NR_POSIX + 103)
+#define __NR_POSIX_sethostid            (__NR_POSIX + 104)
+#define __NR_POSIX_setsockopt           (__NR_POSIX + 105)
+#define __NR_POSIX_shutdown             (__NR_POSIX + 106)
+#define __NR_POSIX_socket               (__NR_POSIX + 107)
+#define __NR_POSIX_gethostname          (__NR_POSIX + 108)
+#define __NR_POSIX_sethostname          (__NR_POSIX + 109)
+#define __NR_POSIX_getdomainname        (__NR_POSIX + 110)
+#define __NR_POSIX_setdomainname        (__NR_POSIX + 111)
+#define __NR_POSIX_truncate             (__NR_POSIX + 112)
+#define __NR_POSIX_ftruncate            (__NR_POSIX + 113)
+#define __NR_POSIX_rename               (__NR_POSIX + 114)
+#define __NR_POSIX_symlink              (__NR_POSIX + 115)
+#define __NR_POSIX_readlink             (__NR_POSIX + 116)
+#define __NR_POSIX_lstat                (__NR_POSIX + 117)
+#define __NR_POSIX_nfs_mount            (__NR_POSIX + 118)
+#define __NR_POSIX_nfs_svc              (__NR_POSIX + 119)
+#define __NR_POSIX_nfs_getfh            (__NR_POSIX + 120)
+#define __NR_POSIX_async_daemon         (__NR_POSIX + 121)
+#define __NR_POSIX_exportfs             (__NR_POSIX + 122)
+#define __NR_POSIX_SGI_setregid         (__NR_POSIX + 123)
+#define __NR_POSIX_SGI_setreuid         (__NR_POSIX + 124)
+#define __NR_POSIX_getitimer            (__NR_POSIX + 125)
+#define __NR_POSIX_setitimer            (__NR_POSIX + 126)
+#define __NR_POSIX_adjtime              (__NR_POSIX + 127)
+#define __NR_POSIX_SGI_bsdgettime       (__NR_POSIX + 128)
+#define __NR_POSIX_SGI_sproc            (__NR_POSIX + 129)
+#define __NR_POSIX_SGI_prctl            (__NR_POSIX + 130)
+#define __NR_POSIX_SGI_blkproc          (__NR_POSIX + 131)
+#define __NR_POSIX_SGI_reserved1        (__NR_POSIX + 132)
+#define __NR_POSIX_SGI_sgigsc           (__NR_POSIX + 133)
+#define __NR_POSIX_SGI_mmap             (__NR_POSIX + 134)
+#define __NR_POSIX_SGI_munmap           (__NR_POSIX + 135)
+#define __NR_POSIX_SGI_mprotect         (__NR_POSIX + 136)
+#define __NR_POSIX_SGI_msync            (__NR_POSIX + 137)
+#define __NR_POSIX_SGI_madvise          (__NR_POSIX + 138)
+#define __NR_POSIX_SGI_mpin             (__NR_POSIX + 139)
+#define __NR_POSIX_SGI_getpagesize      (__NR_POSIX + 140)
+#define __NR_POSIX_SGI_libattach        (__NR_POSIX + 141)
+#define __NR_POSIX_SGI_libdetach        (__NR_POSIX + 142)
+#define __NR_POSIX_SGI_getpgrp          (__NR_POSIX + 143)
+#define __NR_POSIX_SGI_setpgrp          (__NR_POSIX + 144)
+#define __NR_POSIX_SGI_reserved2        (__NR_POSIX + 145)
+#define __NR_POSIX_SGI_reserved3        (__NR_POSIX + 146)
+#define __NR_POSIX_SGI_reserved4        (__NR_POSIX + 147)
+#define __NR_POSIX_SGI_reserved5        (__NR_POSIX + 148)
+#define __NR_POSIX_SGI_reserved6        (__NR_POSIX + 149)
+#define __NR_POSIX_cacheflush           (__NR_POSIX + 150)
+#define __NR_POSIX_cachectl             (__NR_POSIX + 151)
+#define __NR_POSIX_fchown               (__NR_POSIX + 152)
+#define __NR_POSIX_fchmod               (__NR_POSIX + 153)
+#define __NR_POSIX_wait3                (__NR_POSIX + 154)
+#define __NR_POSIX_mmap                 (__NR_POSIX + 155)
+#define __NR_POSIX_munmap               (__NR_POSIX + 156)
+#define __NR_POSIX_madvise              (__NR_POSIX + 157)
+#define __NR_POSIX_BSD_getpagesize      (__NR_POSIX + 158)
+#define __NR_POSIX_setreuid             (__NR_POSIX + 159)
+#define __NR_POSIX_setregid             (__NR_POSIX + 160)
+#define __NR_POSIX_setpgid              (__NR_POSIX + 161)
+#define __NR_POSIX_getgroups            (__NR_POSIX + 162)
+#define __NR_POSIX_setgroups            (__NR_POSIX + 163)
+#define __NR_POSIX_gettimeofday         (__NR_POSIX + 164)
+#define __NR_POSIX_getrusage            (__NR_POSIX + 165)
+#define __NR_POSIX_getrlimit            (__NR_POSIX + 166)
+#define __NR_POSIX_setrlimit            (__NR_POSIX + 167)
+#define __NR_POSIX_waitpid              (__NR_POSIX + 168)
+#define __NR_POSIX_dup2                 (__NR_POSIX + 169)
+#define __NR_POSIX_reserved2            (__NR_POSIX + 170)
+#define __NR_POSIX_reserved3            (__NR_POSIX + 171)
+#define __NR_POSIX_reserved4            (__NR_POSIX + 172)
+#define __NR_POSIX_reserved5            (__NR_POSIX + 173)
+#define __NR_POSIX_reserved6            (__NR_POSIX + 174)
+#define __NR_POSIX_reserved7            (__NR_POSIX + 175)
+#define __NR_POSIX_reserved8            (__NR_POSIX + 176)
+#define __NR_POSIX_reserved9            (__NR_POSIX + 177)
+#define __NR_POSIX_reserved10           (__NR_POSIX + 178)
+#define __NR_POSIX_reserved11           (__NR_POSIX + 179)
+#define __NR_POSIX_reserved12           (__NR_POSIX + 180)
+#define __NR_POSIX_reserved13           (__NR_POSIX + 181)
+#define __NR_POSIX_reserved14           (__NR_POSIX + 182)
+#define __NR_POSIX_reserved15           (__NR_POSIX + 183)
+#define __NR_POSIX_reserved16           (__NR_POSIX + 184)
+#define __NR_POSIX_reserved17           (__NR_POSIX + 185)
+#define __NR_POSIX_reserved18           (__NR_POSIX + 186)
+#define __NR_POSIX_reserved19           (__NR_POSIX + 187)
+#define __NR_POSIX_reserved20           (__NR_POSIX + 188)
+#define __NR_POSIX_reserved21           (__NR_POSIX + 189)
+#define __NR_POSIX_reserved22           (__NR_POSIX + 190)
+#define __NR_POSIX_reserved23           (__NR_POSIX + 191)
+#define __NR_POSIX_reserved24           (__NR_POSIX + 192)
+#define __NR_POSIX_reserved25           (__NR_POSIX + 193)
+#define __NR_POSIX_reserved26           (__NR_POSIX + 194)
+#define __NR_POSIX_reserved27           (__NR_POSIX + 195)
+#define __NR_POSIX_reserved28           (__NR_POSIX + 196)
+#define __NR_POSIX_reserved29           (__NR_POSIX + 197)
+#define __NR_POSIX_reserved30           (__NR_POSIX + 198)
+#define __NR_POSIX_reserved31           (__NR_POSIX + 199)
+#define __NR_POSIX_reserved32           (__NR_POSIX + 200)
+#define __NR_POSIX_reserved33           (__NR_POSIX + 201)
+#define __NR_POSIX_reserved34           (__NR_POSIX + 202)
+#define __NR_POSIX_reserved35           (__NR_POSIX + 203)
+#define __NR_POSIX_reserved36           (__NR_POSIX + 204)
+#define __NR_POSIX_reserved37           (__NR_POSIX + 205)
+#define __NR_POSIX_reserved38           (__NR_POSIX + 206)
+#define __NR_POSIX_reserved39           (__NR_POSIX + 207)
+#define __NR_POSIX_reserved40           (__NR_POSIX + 208)
+#define __NR_POSIX_reserved41           (__NR_POSIX + 209)
+#define __NR_POSIX_reserved42           (__NR_POSIX + 210)
+#define __NR_POSIX_reserved43           (__NR_POSIX + 211)
+#define __NR_POSIX_reserved44           (__NR_POSIX + 212)
+#define __NR_POSIX_reserved45           (__NR_POSIX + 213)
+#define __NR_POSIX_reserved46           (__NR_POSIX + 214)
+#define __NR_POSIX_reserved47           (__NR_POSIX + 215)
+#define __NR_POSIX_reserved48           (__NR_POSIX + 216)
+#define __NR_POSIX_reserved49           (__NR_POSIX + 217)
+#define __NR_POSIX_reserved50           (__NR_POSIX + 218)
+#define __NR_POSIX_reserved51           (__NR_POSIX + 219)
+#define __NR_POSIX_reserved52           (__NR_POSIX + 220)
+#define __NR_POSIX_reserved53           (__NR_POSIX + 221)
+#define __NR_POSIX_reserved54           (__NR_POSIX + 222)
+#define __NR_POSIX_reserved55           (__NR_POSIX + 223)
+#define __NR_POSIX_reserved56           (__NR_POSIX + 224)
+#define __NR_POSIX_reserved57           (__NR_POSIX + 225)
+#define __NR_POSIX_reserved58           (__NR_POSIX + 226)
+#define __NR_POSIX_reserved59           (__NR_POSIX + 227)
+#define __NR_POSIX_reserved60           (__NR_POSIX + 228)
+#define __NR_POSIX_reserved61           (__NR_POSIX + 229)
+#define __NR_POSIX_reserved62           (__NR_POSIX + 230)
+#define __NR_POSIX_reserved63           (__NR_POSIX + 231)
+#define __NR_POSIX_reserved64           (__NR_POSIX + 232)
+#define __NR_POSIX_reserved65           (__NR_POSIX + 233)
+#define __NR_POSIX_reserved66           (__NR_POSIX + 234)
+#define __NR_POSIX_reserved67           (__NR_POSIX + 235)
+#define __NR_POSIX_reserved68           (__NR_POSIX + 236)
+#define __NR_POSIX_reserved69           (__NR_POSIX + 237)
+#define __NR_POSIX_reserved70           (__NR_POSIX + 238)
+#define __NR_POSIX_reserved71           (__NR_POSIX + 239)
+#define __NR_POSIX_reserved72           (__NR_POSIX + 240)
+#define __NR_POSIX_reserved73           (__NR_POSIX + 241)
+#define __NR_POSIX_reserved74           (__NR_POSIX + 242)
+#define __NR_POSIX_reserved75           (__NR_POSIX + 243)
+#define __NR_POSIX_reserved76           (__NR_POSIX + 244)
+#define __NR_POSIX_reserved77           (__NR_POSIX + 245)
+#define __NR_POSIX_reserved78           (__NR_POSIX + 246)
+#define __NR_POSIX_reserved79           (__NR_POSIX + 247)
+#define __NR_POSIX_reserved80           (__NR_POSIX + 248)
+#define __NR_POSIX_reserved81           (__NR_POSIX + 249)
+#define __NR_POSIX_reserved82           (__NR_POSIX + 250)
+#define __NR_POSIX_reserved83           (__NR_POSIX + 251)
+#define __NR_POSIX_reserved84           (__NR_POSIX + 252)
+#define __NR_POSIX_reserved85           (__NR_POSIX + 253)
+#define __NR_POSIX_reserved86           (__NR_POSIX + 254)
+#define __NR_POSIX_reserved87           (__NR_POSIX + 255)
+#define __NR_POSIX_reserved88           (__NR_POSIX + 256)
+#define __NR_POSIX_reserved89           (__NR_POSIX + 257)
+#define __NR_POSIX_reserved90           (__NR_POSIX + 258)
+#define __NR_POSIX_reserved91           (__NR_POSIX + 259)
+#define __NR_POSIX_netboot              (__NR_POSIX + 260)
+#define __NR_POSIX_netunboot            (__NR_POSIX + 261)
+#define __NR_POSIX_rdump                (__NR_POSIX + 262)
+#define __NR_POSIX_setsid               (__NR_POSIX + 263)
+#define __NR_POSIX_getmaxsig            (__NR_POSIX + 264)
+#define __NR_POSIX_sigpending           (__NR_POSIX + 265)
+#define __NR_POSIX_sigprocmask          (__NR_POSIX + 266)
+#define __NR_POSIX_sigsuspend           (__NR_POSIX + 267)
+#define __NR_POSIX_sigaction            (__NR_POSIX + 268)
+#define __NR_POSIX_MIPS_reserved1       (__NR_POSIX + 269)
+#define __NR_POSIX_MIPS_reserved2       (__NR_POSIX + 270)
+#define __NR_POSIX_MIPS_reserved3       (__NR_POSIX + 271)
+#define __NR_POSIX_MIPS_reserved4       (__NR_POSIX + 272)
+#define __NR_POSIX_MIPS_reserved5       (__NR_POSIX + 273)
+#define __NR_POSIX_MIPS_reserved6       (__NR_POSIX + 274)
+#define __NR_POSIX_MIPS_reserved7       (__NR_POSIX + 275)
+#define __NR_POSIX_MIPS_reserved8       (__NR_POSIX + 276)
+#define __NR_POSIX_MIPS_reserved9       (__NR_POSIX + 277)
+#define __NR_POSIX_MIPS_reserved10      (__NR_POSIX + 278)
+#define __NR_POSIX_MIPS_reserved11      (__NR_POSIX + 279)
+#define __NR_POSIX_TANDEM_reserved1     (__NR_POSIX + 280)
+#define __NR_POSIX_TANDEM_reserved2     (__NR_POSIX + 281)
+#define __NR_POSIX_TANDEM_reserved3     (__NR_POSIX + 282)
+#define __NR_POSIX_TANDEM_reserved4     (__NR_POSIX + 283)
+#define __NR_POSIX_TANDEM_reserved5     (__NR_POSIX + 284)
+#define __NR_POSIX_TANDEM_reserved6     (__NR_POSIX + 285)
+#define __NR_POSIX_TANDEM_reserved7     (__NR_POSIX + 286)
+#define __NR_POSIX_TANDEM_reserved8     (__NR_POSIX + 287)
+#define __NR_POSIX_TANDEM_reserved9     (__NR_POSIX + 288)
+#define __NR_POSIX_TANDEM_reserved10    (__NR_POSIX + 289)
+#define __NR_POSIX_TANDEM_reserved11    (__NR_POSIX + 290)
+#define __NR_POSIX_TANDEM_reserved12    (__NR_POSIX + 291)
+#define __NR_POSIX_TANDEM_reserved13    (__NR_POSIX + 292)
+#define __NR_POSIX_TANDEM_reserved14    (__NR_POSIX + 293)
+#define __NR_POSIX_TANDEM_reserved15    (__NR_POSIX + 294)
+#define __NR_POSIX_TANDEM_reserved16    (__NR_POSIX + 295)
+#define __NR_POSIX_TANDEM_reserved17    (__NR_POSIX + 296)
+#define __NR_POSIX_TANDEM_reserved18    (__NR_POSIX + 297)
+#define __NR_POSIX_TANDEM_reserved19    (__NR_POSIX + 298)
+#define __NR_POSIX_TANDEM_reserved20    (__NR_POSIX + 299)
+#define __NR_POSIX_SGI_reserved7        (__NR_POSIX + 300)
+#define __NR_POSIX_SGI_reserved8        (__NR_POSIX + 301)
+#define __NR_POSIX_SGI_reserved9        (__NR_POSIX + 302)
+#define __NR_POSIX_SGI_reserved10       (__NR_POSIX + 303)
+#define __NR_POSIX_SGI_reserved11       (__NR_POSIX + 304)
+#define __NR_POSIX_SGI_reserved12       (__NR_POSIX + 305)
+#define __NR_POSIX_SGI_reserved13       (__NR_POSIX + 306)
+#define __NR_POSIX_SGI_reserved14       (__NR_POSIX + 307)
+#define __NR_POSIX_SGI_reserved15       (__NR_POSIX + 308)
+#define __NR_POSIX_SGI_reserved16       (__NR_POSIX + 309)
+#define __NR_POSIX_SGI_reserved17       (__NR_POSIX + 310)
+#define __NR_POSIX_SGI_reserved18       (__NR_POSIX + 311)
+#define __NR_POSIX_SGI_reserved19       (__NR_POSIX + 312)
+#define __NR_POSIX_SGI_reserved20       (__NR_POSIX + 313)
+#define __NR_POSIX_SGI_reserved21       (__NR_POSIX + 314)
+#define __NR_POSIX_SGI_reserved22       (__NR_POSIX + 315)
+#define __NR_POSIX_SGI_reserved23       (__NR_POSIX + 316)
+#define __NR_POSIX_SGI_reserved24       (__NR_POSIX + 317)
+#define __NR_POSIX_SGI_reserved25       (__NR_POSIX + 318)
+#define __NR_POSIX_SGI_reserved26       (__NR_POSIX + 319)
+
+#endif /* _ASM_RISCOS_SYSCALL_H */
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
new file mode 100644
index 000000000000..31c0c2347f4f
--- /dev/null
+++ b/include/asm-mips/rtc.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-mips/rtc.h 
+ *
+ * (Really an interface for drivers/char/genrtc.c)
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * Please read the COPYING file for all license details.
+ */
+
+#ifndef _MIPS_RTC_H
+#define _MIPS_RTC_H
+
+#ifdef __KERNEL__
+
+#include <linux/rtc.h>
+
+#define RTC_PIE 0x40            /* periodic interrupt enable */
+#define RTC_AIE 0x20            /* alarm interrupt enable */
+#define RTC_UIE 0x10            /* update-finished interrupt enable */
+
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+unsigned int get_rtc_time(struct rtc_time *time);
+int set_rtc_time(struct rtc_time *time);
+unsigned int get_rtc_ss(void);
+int get_rtc_pll(struct rtc_pll_info *pll);
+int set_rtc_pll(struct rtc_pll_info *pll);
+
+#endif
+#endif
diff --git a/include/asm-mips/scatterlist.h b/include/asm-mips/scatterlist.h
new file mode 100644
index 000000000000..22634706e9d5
--- /dev/null
+++ b/include/asm-mips/scatterlist.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_SCATTERLIST_H
+#define __ASM_SCATTERLIST_H
+
+struct scatterlist {
+        struct page *   page;
+        unsigned int    offset;
+        dma_addr_t      dma_address;
+        unsigned int    length;
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#define ISA_DMA_THRESHOLD (0x00ffffffUL)
+
+#endif /* __ASM_SCATTERLIST_H */
diff --git a/include/asm-mips/sections.h b/include/asm-mips/sections.h
new file mode 100644
index 000000000000..f7016278b266
--- /dev/null
+++ b/include/asm-mips/sections.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_SECTIONS_H
+#define _ASM_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern char _fdata;
+
+#endif /* _ASM_SECTIONS_H */
diff --git a/include/asm-mips/segment.h b/include/asm-mips/segment.h
new file mode 100644
index 000000000000..92ac001fc483
--- /dev/null
+++ b/include/asm-mips/segment.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_SEGMENT_H
+#define _ASM_SEGMENT_H
+
+/* Only here because we have some old header files that expect it.. */
+
+#endif /* _ASM_SEGMENT_H */
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
new file mode 100644
index 000000000000..c2c97dec661b
--- /dev/null
+++ b/include/asm-mips/semaphore.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996  Linus Torvalds
+ * Copyright (C) 1998, 99, 2000, 01, 04  Ralf Baechle
+ * Copyright (C) 1999, 2000, 01  Silicon Graphics, Inc.
+ * Copyright (C) 2000, 01 MIPS Technologies, Inc.
+ *
+ * In all honesty, little of the old MIPS code left - the PPC64 variant was
+ * just looking nice and portable so I ripped it.  Credits to whoever wrote
+ * it.
+ */
+#ifndef __ASM_SEMAPHORE_H
+#define __ASM_SEMAPHORE_H
+
+/*
+ * Remove spinlock-based RW semaphores; RW semaphore definitions are
+ * now in rwsem.h and we use the generic lib/rwsem.c implementation.
+ * Rework semaphores to use atomic_dec_if_positive.
+ * -- Paul Mackerras (paulus@samba.org)
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <linux/wait.h>
+#include <linux/rwsem.h>
+
+struct semaphore {
+        /*
+         * Note that any negative value of count is equivalent to 0,
+         * but additionally indicates that some process(es) might be
+         * sleeping on `wait'.
+         */
+        atomic_t count;
+        wait_queue_head_t wait;
+};
+
+#define __SEMAPHORE_INITIALIZER(name, n)                                \
+{                                                                       \
+        .count          = ATOMIC_INIT(n),                               \
+        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
+}
+
+#define __MUTEX_INITIALIZER(name) \
+        __SEMAPHORE_INITIALIZER(name, 1)
+
+#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
+        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
+
+#define DECLARE_MUTEX(name)             __DECLARE_SEMAPHORE_GENERIC(name, 1)
+#define DECLARE_MUTEX_LOCKED(name)      __DECLARE_SEMAPHORE_GENERIC(name, 0)
+
+static inline void sema_init (struct semaphore *sem, int val)
+{
+        atomic_set(&sem->count, val);
+        init_waitqueue_head(&sem->wait);
+}
+
+static inline void init_MUTEX (struct semaphore *sem)
+{
+        sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED (struct semaphore *sem)
+{
+        sema_init(sem, 0);
+}
+
+extern void __down(struct semaphore * sem);
+extern int  __down_interruptible(struct semaphore * sem);
+extern void __up(struct semaphore * sem);
+
+static inline void down(struct semaphore * sem)
+{
+        might_sleep();
+
+        /*
+         * Try to get the semaphore, take the slow path if we fail.
+         */
+        if (unlikely(atomic_dec_return(&sem->count) < 0))
+                __down(sem);
+}
+
+static inline int down_interruptible(struct semaphore * sem)
+{
+        int ret = 0;
+
+        might_sleep();
+
+        if (unlikely(atomic_dec_return(&sem->count) < 0))
+                ret = __down_interruptible(sem);
+        return ret;
+}
+
+static inline int down_trylock(struct semaphore * sem)
+{
+        return atomic_dec_if_positive(&sem->count) < 0;
+}
+
+static inline void up(struct semaphore * sem)
+{
+        if (unlikely(atomic_inc_return(&sem->count) <= 0))
+                __up(sem);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SEMAPHORE_H */
diff --git a/include/asm-mips/sembuf.h b/include/asm-mips/sembuf.h
new file mode 100644
index 000000000000..7281a4decaa0
--- /dev/null
+++ b/include/asm-mips/sembuf.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_SEMBUF_H
+#define _ASM_SEMBUF_H
+
+/*
+ * The semid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_SEMBUF_H */
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
new file mode 100644
index 000000000000..8a70ff58f760
--- /dev/null
+++ b/include/asm-mips/serial.h
@@ -0,0 +1,444 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
+#include <linux/config.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1843200 / 16)
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define FOURPORT_FLAGS ASYNC_FOURPORT
+#define ACCENT_FLAGS 0
+#define BOCA_FLAGS 0
+#define HUB6_FLAGS 0
+#define RS_TABLE_SIZE   64
+#else
+#define RS_TABLE_SIZE
+#endif
+
+/*
+ * The following define the access methods for the HUB6 card. All
+ * access is through two ports for all 24 possible chips. The card is
+ * selected through the high 2 bits, the port on that card with the
+ * "middle" 3 bits, and the register on that port with the bottom
+ * 3 bits.
+ *
+ * While the access port and interrupt is configurable, the default
+ * port locations are 0x302 for the port control register, and 0x303
+ * for the data read/write register. Normally, the interrupt is at irq3
+ * but can be anything from 3 to 7 inclusive. Note that using 3 will
+ * require disabling com2.
+ */
+
+#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+
+#ifdef CONFIG_MACH_JAZZ
+#include <asm/jazz.h>
+
+#ifndef CONFIG_OLIVETTI_M700
+   /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
+      exactly which ones ... XXX */
+#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
+#else
+/* but the M700 isn't such a strange beast */
+#define JAZZ_BASE_BAUD BASE_BAUD
+#endif
+
+#define _JAZZ_SERIAL_INIT(int, base)                                    \
+        { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
+          .iomem_base = (u8 *) base, .iomem_reg_shift = 0,                      \
+          .io_type = SERIAL_IO_MEM }
+#define JAZZ_SERIAL_PORT_DEFNS                                          \
+        _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE),         \
+        _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
+#else
+#define JAZZ_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MIPS_COBALT
+#include <asm/cobalt/cobalt.h>
+#define COBALT_BASE_BAUD  (18432000 / 16)
+#define COBALT_SERIAL_PORT_DEFNS                \
+        /* UART CLK   PORT  IRQ  FLAGS    */            \
+        { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS },   /* ttyS0 */
+#else
+#define COBALT_SERIAL_PORT_DEFNS
+#endif
+
+/*
+ * Both Galileo boards have the same UART mappings.
+ */
+#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
+#include <asm/galileo-boards/ev96100.h>
+#include <asm/galileo-boards/ev96100int.h>
+#define EV96100_SERIAL_PORT_DEFNS                                  \
+    { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
+      .flags = STD_COM_FLAGS,  \
+      .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
+      .io_type = SERIAL_IO_MEM }, \
+    { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
+      .flags = STD_COM_FLAGS, \
+      .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
+      .io_type = SERIAL_IO_MEM },
+#else
+#define EV96100_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MIPS_ITE8172
+#include <asm/it8172/it8172.h>
+#include <asm/it8172/it8172_int.h>
+#include <asm/it8712.h>
+#define ITE_SERIAL_PORT_DEFNS                                  \
+    { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
+      .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
+    { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
+      .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
+    /* Smart Card Reader 0 */ \
+    { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
+      .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
+    /* Smart Card Reader 1 */ \
+    { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
+      .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
+#else
+#define ITE_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MIPS_IVR
+#include <asm/it8172/it8172.h>
+#include <asm/it8172/it8172_int.h>
+#define IVR_SERIAL_PORT_DEFNS                                  \
+    { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
+      .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },         \
+    /* Smart Card Reader 1 */ \
+    { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
+      .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
+#else
+#define IVR_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_TOSHIBA_JMR3927
+#include <asm/jmr3927/jmr3927.h>
+#define TXX927_SERIAL_PORT_DEFNS                              \
+    { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT,  \
+      .flags = UART0_FLAGS, .type = 1 },                        \
+    { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT,  \
+      .flags = UART1_FLAGS, .type = 1 },
+#else
+#define TXX927_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_SERIAL_AU1X00
+#include <asm/mach-au1x00/au1000.h>
+#ifdef CONFIG_SOC_AU1000
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART2_ADDR,              \
+      .iomem_base = (unsigned char *)UART2_ADDR,       \
+      .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1500
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1100
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1550
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1550_UART3_INT,  .flags = STD_COM_FLAGS,\
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#else
+#define AU1000_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
+#define STD_SERIAL_PORT_DEFNS                   \
+        /* UART CLK   PORT IRQ     FLAGS        */                      \
+        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
+        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
+        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
+        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define EXTRA_SERIAL_PORT_DEFNS                 \
+        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
+        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
+        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
+        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
+        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
+        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
+        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
+        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
+        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
+        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
+        { 0, BASE_BAUD, 0x000, 0, 0 },                  /* ttyS14 (spare) */ \
+        { 0, BASE_BAUD, 0x000, 0, 0 },                  /* ttyS15 (spare) */ \
+        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
+        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
+        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
+        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
+        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
+        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
+        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
+        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
+        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
+        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
+        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
+        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
+        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
+        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
+        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
+        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
+#else /* CONFIG_SERIAL_MANY_PORTS */
+#define EXTRA_SERIAL_PORT_DEFNS
+#endif /* CONFIG_SERIAL_MANY_PORTS */
+
+#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+#define STD_SERIAL_PORT_DEFNS
+#define EXTRA_SERIAL_PORT_DEFNS
+#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+
+/* You can have up to four HUB6's in the system, but I've only
+ * included two cards here for a total of twelve ports.
+ */
+#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
+#define HUB6_SERIAL_PORT_DFNS           \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
+#else
+#define HUB6_SERIAL_PORT_DFNS
+#endif
+
+#ifdef CONFIG_MOMENCO_JAGUAR_ATX
+/* Ordinary NS16552 duart with a 20MHz crystal.  */
+#define JAGUAR_ATX_UART_CLK     20000000
+#define JAGUAR_ATX_BASE_BAUD    (JAGUAR_ATX_UART_CLK / 16)
+
+#define JAGUAR_ATX_SERIAL1_IRQ  6
+#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
+
+#define _JAGUAR_ATX_SERIAL_INIT(int, base)                              \
+        { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int,                    \
+          flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),               \
+          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+          io_type: SERIAL_IO_MEM }
+#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS                            \
+        _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
+#else
+#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MOMENCO_OCELOT_3
+#define OCELOT_3_BASE_BAUD      ( 20000000 / 16 )
+#define OCELOT_3_SERIAL_IRQ     6
+#define OCELOT_3_SERIAL_BASE    (signed)0xfd000020
+
+#define _OCELOT_3_SERIAL_INIT(int, base)                                \
+        { baud_base: OCELOT_3_BASE_BAUD, irq: int,                      \
+          flags: STD_COM_FLAGS,                                         \
+          iomem_base: (u8 *) base, iomem_reg_shift: 2,                  \
+          io_type: SERIAL_IO_MEM }
+
+#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS                              \
+        _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
+#else
+#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MOMENCO_OCELOT
+/* Ordinary NS16552 duart with a 20MHz crystal.  */
+#define OCELOT_BASE_BAUD ( 20000000 / 16 )
+
+#define OCELOT_SERIAL1_IRQ      4
+#define OCELOT_SERIAL1_BASE     0xe0001020
+
+#define _OCELOT_SERIAL_INIT(int, base)                                  \
+        { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,    \
+          .iomem_base = (u8 *) base, .iomem_reg_shift = 2,                      \
+          .io_type = SERIAL_IO_MEM }
+#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS                                \
+        _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
+#else
+#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MOMENCO_OCELOT_G
+/* Ordinary NS16552 duart with a 20MHz crystal.  */
+#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
+
+#define OCELOT_G_SERIAL1_IRQ    4
+#if 0
+#define OCELOT_G_SERIAL1_BASE   0xe0001020
+#else
+#define OCELOT_G_SERIAL1_BASE   0xfd000020
+#endif
+
+#define _OCELOT_G_SERIAL_INIT(int, base)                                \
+        { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
+          .iomem_base = (u8 *) base, .iomem_reg_shift = 2,                      \
+          .io_type = SERIAL_IO_MEM }
+#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS                              \
+        _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
+#else
+#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_MOMENCO_OCELOT_C
+/* Ordinary NS16552 duart with a 20MHz crystal.  */
+#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
+
+#define OCELOT_C_SERIAL1_IRQ    80
+#define OCELOT_C_SERIAL1_BASE   0xfd000020
+
+#define OCELOT_C_SERIAL2_IRQ    81
+#define OCELOT_C_SERIAL2_BASE   0xfd000000
+
+#define _OCELOT_C_SERIAL_INIT(int, base)                                \
+        { .baud_base            = OCELOT_C_BASE_BAUD,                   \
+          .irq                  = (int),                                \
+          .flags                = STD_COM_FLAGS,                        \
+          .iomem_base           = (u8 *) base,                          \
+          .iomem_reg_shift      = 2,                                    \
+          .io_type              = SERIAL_IO_MEM                         \
+         }
+#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS                              \
+        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
+        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
+#else
+#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_DDB5477
+#include <asm/ddb5xxx/ddb5477.h>
+#define DDB5477_SERIAL_PORT_DEFNS                                       \
+        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0,             \
+          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200,        \
+          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},              \
+        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1,             \
+          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240,        \
+          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
+#else
+#define DDB5477_SERIAL_PORT_DEFNS
+#endif
+
+#ifdef CONFIG_SGI_IP32
+/*
+ * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
+ * They are initialized in ip32_setup
+ */
+#define IP32_SERIAL_PORT_DEFNS                          \
+        {},{},
+#else
+#define IP32_SERIAL_PORT_DEFNS
+#endif /* CONFIG_SGI_IP32 */
+
+#define SERIAL_PORT_DFNS                                \
+        COBALT_SERIAL_PORT_DEFNS                        \
+        DDB5477_SERIAL_PORT_DEFNS                       \
+        EV96100_SERIAL_PORT_DEFNS                       \
+        EXTRA_SERIAL_PORT_DEFNS                         \
+        HUB6_SERIAL_PORT_DFNS                           \
+        IP32_SERIAL_PORT_DEFNS                          \
+        ITE_SERIAL_PORT_DEFNS                           \
+        IVR_SERIAL_PORT_DEFNS                           \
+        JAZZ_SERIAL_PORT_DEFNS                          \
+        STD_SERIAL_PORT_DEFNS                           \
+        MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS              \
+        MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS              \
+        MOMENCO_OCELOT_SERIAL_PORT_DEFNS                \
+        MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS              \
+        TXX927_SERIAL_PORT_DEFNS                        \
+        AU1000_SERIAL_PORT_DEFNS
+
+#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
new file mode 100644
index 000000000000..737fa4a6912e
--- /dev/null
+++ b/include/asm-mips/setup.h
@@ -0,0 +1,8 @@
+#ifdef __KERNEL__
+#ifndef _MIPS_SETUP_H
+#define _MIPS_SETUP_H
+
+#define COMMAND_LINE_SIZE       256
+
+#endif /* __SETUP_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
new file mode 100644
index 000000000000..a38d66f99872
--- /dev/null
+++ b/include/asm-mips/sgi/gio.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * gio.h: Definitions for SGI GIO bus
+ *
+ * Copyright (C) 2002 Ladislav Michl
+ */
+
+#ifndef _SGI_GIO_H
+#define _SGI_GIO_H
+
+/*
+ * GIO bus addresses
+ *
+ * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
+ * three physical connectors, but only two slots, GFX and EXP0.
+ * 
+ * There is 10MB of GIO address space for GIO64 slot devices
+ * slot#   slot type address range            size
+ * -----   --------- ----------------------- -----
+ *   0     GFX       0x1f000000 - 0x1f3fffff   4MB
+ *   1     EXP0      0x1f400000 - 0x1f5fffff   2MB
+ *   2     EXP1      0x1f600000 - 0x1f9fffff   4MB
+ *
+ * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
+ * into the HPC address space.
+ *   -     MISC      0x1fb00000 - 0x1fbfffff   1MB
+ *
+ * Following space is reserved and unused
+ *   -     RESERVED  0x18000000 - 0x1effffff 112MB
+ *
+ * GIO bus IDs
+ *
+ * Each GIO bus device identifies itself to the system by answering a
+ * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
+ * than 128 are 8 bits long, with the most significant 24 bits read from
+ * the slot undefined.
+ *
+ * 32-bit IDs are divided into
+ *      bits 0:6        the product ID; ranges from 0x00 to 0x7F.
+ *      bit 7           0=GIO Product ID is 8 bits wide
+ *                      1=GIO Product ID is 32 bits wide.
+ *      bits 8:15       manufacturer version for the product.
+ *      bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
+ *      bit 17          0=no ROM present
+ *                      1=ROM present on this board AND next three words
+ *                      space define the ROM.
+ *      bits 18:31      up to manufacturer.
+ *
+ * IDs above 0x50/0xd0 are of 3rd party boards.
+ *
+ * 8-bit IDs
+ *      0x01            XPI low cost FDDI
+ *      0x02            GTR TokenRing
+ *      0x04            Synchronous ISDN
+ *      0x05            ATM board [*]
+ *      0x06            Canon Interface
+ *      0x07            16 bit SCSI Card [*]
+ *      0x08            JPEG (Double Wide)
+ *      0x09            JPEG (Single Wide)
+ *      0x0a            XPI mez. FDDI device 0
+ *      0x0b            XPI mez. FDDI device 1
+ *      0x0c            SMPTE 259M Video [*]
+ *      0x0d            Babblefish Compression [*]
+ *      0x0e            E-Plex 8-port Ethernet
+ *      0x30            Lyon Lamb IVAS
+ *      0xb8            GIO 100BaseTX Fast Ethernet (gfe)
+ *
+ * [*] Device provide 32-bit ID.
+ *
+ */
+
+#define GIO_ID(x)               (x & 0x7f)
+#define GIO_32BIT_ID            0x80
+#define GIO_REV(x)              ((x >> 8) & 0xff)
+#define GIO_64BIT_IFACE         0x10000
+#define GIO_ROM_PRESENT         0x20000
+#define GIO_VENDOR_CODE(x)      ((x >> 18) & 0x3fff)
+
+#define GIO_SLOT_GFX_BASE       0x1f000000
+#define GIO_SLOT_EXP0_BASE      0x1f400000
+#define GIO_SLOT_EXP1_BASE      0x1f600000
+
+#endif /* _SGI_GIO_H */
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
new file mode 100644
index 000000000000..a5b988d7327a
--- /dev/null
+++ b/include/asm-mips/sgi/hpc3.h
@@ -0,0 +1,317 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * hpc3.h: Definitions for SGI HPC3 controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1998 Ralf Baechle
+ */
+
+#ifndef _SGI_HPC3_H
+#define _SGI_HPC3_H
+
+#include <linux/types.h>
+#include <asm/page.h>
+
+/* An HPC DMA descriptor. */
+struct hpc_dma_desc {
+        u32 pbuf;       /* physical address of data buffer */
+        u32 cntinfo;    /* counter and info bits */
+#define HPCDMA_EOX      0x80000000 /* last desc in chain for tx */
+#define HPCDMA_EOR      0x80000000 /* last desc in chain for rx */
+#define HPCDMA_EOXP     0x40000000 /* end of packet for tx */
+#define HPCDMA_EORP     0x40000000 /* end of packet for rx */
+#define HPCDMA_XIE      0x20000000 /* irq generated when at end of this desc */
+#define HPCDMA_XIU      0x01000000 /* Tx buffer in use by CPU. */
+#define HPCDMA_EIPC     0x00ff0000 /* SEEQ ethernet special xternal bytecount */
+#define HPCDMA_ETXD     0x00008000 /* set to one by HPC when packet tx'd */
+#define HPCDMA_OWN      0x00004000 /* Denotes ring buffer ownership on rx */
+#define HPCDMA_BCNT     0x00003fff /* size in bytes of this dma buffer */
+
+        u32 pnext;      /* paddr of next hpc_dma_desc if any */
+};
+
+/* The set of regs for each HPC3 PBUS DMA channel. */
+struct hpc3_pbus_dmacregs {
+        volatile u32 pbdma_bptr;        /* pbus dma channel buffer ptr */
+        volatile u32 pbdma_dptr;        /* pbus dma channel desc ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 pbdma_ctrl;        /* pbus dma channel control register has
+                                         * copletely different meaning for read
+                                         * compared with write */
+        /* read */
+#define HPC3_PDMACTRL_INT       0x00000001 /* interrupt (cleared after read) */
+#define HPC3_PDMACTRL_ISACT     0x00000002 /* channel active */
+        /* write */
+#define HPC3_PDMACTRL_SEL       0x00000002 /* little endian transfer */
+#define HPC3_PDMACTRL_RCV       0x00000004 /* direction is receive */
+#define HPC3_PDMACTRL_FLSH      0x00000008 /* enable flush for receive DMA */
+#define HPC3_PDMACTRL_ACT       0x00000010 /* start dma transfer */
+#define HPC3_PDMACTRL_LD        0x00000020 /* load enable for ACT */
+#define HPC3_PDMACTRL_RT        0x00000040 /* Use realtime GIO bus servicing */
+#define HPC3_PDMACTRL_HW        0x0000ff00 /* DMA High-water mark */
+#define HPC3_PDMACTRL_FB        0x003f0000 /* Ptr to beginning of fifo */
+#define HPC3_PDMACTRL_FE        0x3f000000 /* Ptr to end of fifo */
+
+        u32 _unused1[0x1000/4 - 1];     /* padding */
+};
+
+/* The HPC3 SCSI registers, this does not include external ones. */
+struct hpc3_scsiregs {
+        volatile u32 cbptr;     /* current dma buffer ptr, diagnostic use only */
+        volatile u32 ndptr;     /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 bcd;       /* byte count info */
+#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
+#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
+#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
+
+        volatile u32 ctrl;    /* control register */
+#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
+#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
+#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
+#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
+#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
+#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
+#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
+#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
+
+        volatile u32 gfptr;     /* current GIO fifo ptr */
+        volatile u32 dfptr;     /* current device fifo ptr */
+        volatile u32 dconfig;   /* DMA configuration register */
+#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
+#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
+#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
+#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
+#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
+#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
+#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
+#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
+#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
+#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
+#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
+#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
+#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
+#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
+#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
+#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
+#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
+
+        u32 _unused1[0x1000/4 - 6];     /* padding */
+};
+
+/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
+struct hpc3_ethregs {
+        /* Receiver registers. */
+        volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
+        volatile u32 rx_ndptr;   /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 rx_bcd;    /* byte count info */
+#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
+#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
+#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
+
+        volatile u32 rx_ctrl;   /* control register */
+#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
+#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
+#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
+#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
+#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
+#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
+#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
+
+        volatile u32 rx_gfptr;  /* current GIO fifo ptr */
+        volatile u32 rx_dfptr;  /* current device fifo ptr */
+        u32 _unused1;           /* padding */
+        volatile u32 rx_reset;  /* reset register */
+#define HPC3_ERXRST_CRESET 0x1  /* Reset dma channel and external controller */
+#define HPC3_ERXRST_CLRIRQ 0x2  /* Clear channel interrupt */
+#define HPC3_ERXRST_LBACK  0x4  /* Enable diagnostic loopback mode of Seeq8003 */
+
+        volatile u32 rx_dconfig;        /* DMA configuration register */
+#define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
+#define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
+#define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
+#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
+#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
+#define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
+#define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
+#define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */
+
+        volatile u32 rx_pconfig;        /* PIO configuration register */
+#define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
+#define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
+#define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
+#define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
+
+        u32 _unused2[0x1000/4 - 8];     /* padding */
+
+        /* Transmitter registers. */
+        volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
+        volatile u32 tx_ndptr;  /* next dma descriptor ptr */
+        u32 _unused3[0x1000/4 - 2];     /* padding */
+        volatile u32 tx_bcd;            /* byte count info */
+#define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
+#define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
+#define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
+#define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
+#define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
+
+        volatile u32 tx_ctrl;           /* control register */
+#define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
+#define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
+#define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
+#define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
+#define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
+#define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
+
+        volatile u32 tx_gfptr;          /* current GIO fifo ptr */
+        volatile u32 tx_dfptr;          /* current device fifo ptr */
+        u32 _unused4[0x1000/4 - 4];     /* padding */
+};
+
+struct hpc3_regs {
+        /* First regs for the PBUS 8 dma channels. */
+        struct hpc3_pbus_dmacregs pbdma[8];
+
+        /* Now the HPC scsi registers, we get two scsi reg sets. */
+        struct hpc3_scsiregs scsi_chan0, scsi_chan1;
+
+        /* The SEEQ hpc3 ethernet dma/control registers. */
+        struct hpc3_ethregs ethregs;
+
+        /* Here are where the hpc3 fifo's can be directly accessed
+         * via PIO accesses.  Under normal operation we never stick
+         * our grubby paws in here so it's just padding. */
+        u32 _unused0[0x18000/4];
+
+        /* HPC3 irq status regs.  Due to a peculiar bug you need to
+         * look at two different register addresses to get at all of
+         * the status bits.  The first reg can only reliably report
+         * bits 4:0 of the status, and the second reg can only
+         * reliably report bits 9:5 of the hpc3 irq status.  I told
+         * you it was a peculiar bug. ;-)
+         */
+        volatile u32 istat0;            /* Irq status, only bits <4:0> reliable. */
+#define HPC3_ISTAT_PBIMASK      0x0ff   /* irq bits for pbus devs 0 --> 7 */
+#define HPC3_ISTAT_SC0MASK      0x100   /* irq bit for scsi channel 0 */
+#define HPC3_ISTAT_SC1MASK      0x200   /* irq bit for scsi channel 1 */
+
+        volatile u32 gio_misc;          /* GIO misc control bits. */
+#define HPC3_GIOMISC_ERTIME     0x1     /* Enable external timer real time. */
+#define HPC3_GIOMISC_DENDIAN    0x2     /* dma descriptor endian, 1=lit 0=big */
+
+        volatile u32 eeprom;            /* EEPROM data reg. */
+#define HPC3_EEPROM_EPROT       0x01    /* Protect register enable */
+#define HPC3_EEPROM_CSEL        0x02    /* Chip select */
+#define HPC3_EEPROM_ECLK        0x04    /* EEPROM clock */
+#define HPC3_EEPROM_DATO        0x08    /* Data out */
+#define HPC3_EEPROM_DATI        0x10    /* Data in */
+
+        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
+        volatile u32 bestat;            /* Bus error interrupt status reg. */
+#define HPC3_BESTAT_BLMASK      0x000ff /* Bus lane where bad parity occurred */
+#define HPC3_BESTAT_CTYPE       0x00100 /* Bus cycle type, 0=PIO 1=DMA */
+#define HPC3_BESTAT_PIDSHIFT    9
+#define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
+
+        u32 _unused1[0x14000/4 - 5];    /* padding */
+        
+        /* Now direct PIO per-HPC3 peripheral access to external regs. */
+        volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
+        u32 _unused2[0x7c00/4];
+        volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
+        u32 _unused3[0x7c00/4];
+        volatile u32 eth_ext[320];      /* Ethernet external registers */
+        u32 _unused4[0x3b00/4];
+
+        /* Per-peripheral device external registers and DMA/PIO control. */
+        volatile u32 pbus_extregs[16][256];
+        volatile u32 pbus_dmacfg[8][128];
+        /* Cycles to spend in D3 for reads */
+#define HPC3_DMACFG_D3R_MASK            0x00000001
+#define HPC3_DMACFG_D3R_SHIFT           0
+        /* Cycles to spend in D4 for reads */
+#define HPC3_DMACFG_D4R_MASK            0x0000001e
+#define HPC3_DMACFG_D4R_SHIFT           1
+        /* Cycles to spend in D5 for reads */
+#define HPC3_DMACFG_D5R_MASK            0x000001e0
+#define HPC3_DMACFG_D5R_SHIFT           5
+        /* Cycles to spend in D3 for writes */
+#define HPC3_DMACFG_D3W_MASK            0x00000200
+#define HPC3_DMACFG_D3W_SHIFT           9
+        /* Cycles to spend in D4 for writes */
+#define HPC3_DMACFG_D4W_MASK            0x00003c00
+#define HPC3_DMACFG_D4W_SHIFT           10
+        /* Cycles to spend in D5 for writes */
+#define HPC3_DMACFG_D5W_MASK            0x0003c000
+#define HPC3_DMACFG_D5W_SHIFT           14
+        /* Enable 16-bit DMA access mode */
+#define HPC3_DMACFG_DS16                0x00040000
+        /* Places halfwords on high 16 bits of bus */
+#define HPC3_DMACFG_EVENHI              0x00080000
+        /* Make this device real time */
+#define HPC3_DMACFG_RTIME               0x00200000
+        /* 5 bit burst count for DMA device */
+#define HPC3_DMACFG_BURST_MASK          0x07c00000
+#define HPC3_DMACFG_BURST_SHIFT 22
+        /* Use live pbus_dreq unsynchronized signal */
+#define HPC3_DMACFG_DRQLIVE             0x08000000
+        volatile u32 pbus_piocfg[16][64];
+        /* Cycles to spend in P2 state for reads */
+#define HPC3_PIOCFG_P2R_MASK            0x00001
+#define HPC3_PIOCFG_P2R_SHIFT           0
+        /* Cycles to spend in P3 state for reads */
+#define HPC3_PIOCFG_P3R_MASK            0x0001e
+#define HPC3_PIOCFG_P3R_SHIFT           1
+        /* Cycles to spend in P4 state for reads */
+#define HPC3_PIOCFG_P4R_MASK            0x001e0
+#define HPC3_PIOCFG_P4R_SHIFT           5
+        /* Cycles to spend in P2 state for writes */
+#define HPC3_PIOCFG_P2W_MASK            0x00200
+#define HPC3_PIOCFG_P2W_SHIFT           9
+        /* Cycles to spend in P3 state for writes */
+#define HPC3_PIOCFG_P3W_MASK            0x03c00
+#define HPC3_PIOCFG_P3W_SHIFT           10
+        /* Cycles to spend in P4 state for writes */
+#define HPC3_PIOCFG_P4W_MASK            0x3c000
+#define HPC3_PIOCFG_P4W_SHIFT           14
+        /* Enable 16-bit PIO accesses */
+#define HPC3_PIOCFG_DS16                0x40000
+        /* Place even address bits in bits <15:8> */
+#define HPC3_PIOCFG_EVENHI              0x80000
+
+        /* PBUS PROM control regs. */
+        volatile u32 pbus_promwe;       /* PROM write enable register */
+#define HPC3_PROM_WENAB 0x1     /* Enable writes to the PROM */
+
+        u32 _unused5[0x0800/4 - 1];
+        volatile u32 pbus_promswap;     /* Chip select swap reg */
+#define HPC3_PROM_SWAP  0x1     /* invert GIO addr bit to select prom0 or prom1 */
+
+        u32 _unused6[0x0800/4 - 1];
+        volatile u32 pbus_gout; /* PROM general purpose output reg */
+#define HPC3_PROM_STAT  0x1     /* General purpose status bit in gout */
+
+        u32 _unused7[0x1000/4 - 1];
+        volatile u32 rtcregs[14];       /* Dallas clock registers */
+        u32 _unused8[50];
+        volatile u32 bbram[8192-50-14]; /* Battery backed ram */
+};
+
+/* 
+ * It is possible to have two HPC3's within the address space on
+ * one machine, though only having one is more likely on an Indy.
+ */
+extern struct hpc3_regs *hpc3c0, *hpc3c1;
+#define HPC3_CHIP0_BASE         0x1fb80000      /* physical */
+#define HPC3_CHIP1_BASE         0x1fb00000      /* physical */
+
+extern void sgihpc_init(void);
+
+#endif /* _SGI_HPC3_H */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
new file mode 100644
index 000000000000..169187f53fbc
--- /dev/null
+++ b/include/asm-mips/sgi/ioc.h
@@ -0,0 +1,200 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ioc.h: Definitions for SGI I/O Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2001, 2003 Ladislav Michl
+ */
+
+#ifndef _SGI_IOC_H
+#define _SGI_IOC_H
+
+#include <linux/types.h>
+#include <asm/sgi/pi1.h>
+
+/* 
+ * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
+ * happen if you try word access them. You have been warned.
+ */
+
+struct sgioc_uart_regs {
+        u8 _ctrl1[3];
+        volatile u8 ctrl1;
+        u8 _data1[3];
+        volatile u8 data1;
+        u8 _ctrl2[3];
+        volatile u8 ctrl2;
+        u8 _data2[3];
+        volatile u8 data2;
+};
+
+struct sgioc_keyb_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _command[3];
+        volatile u8 command;
+};
+
+struct sgint_regs {
+        u8 _istat0[3];
+        volatile u8 istat0;             /* Interrupt status zero */
+#define SGINT_ISTAT0_FFULL      0x01
+#define SGINT_ISTAT0_SCSI0      0x02
+#define SGINT_ISTAT0_SCSI1      0x04
+#define SGINT_ISTAT0_ENET       0x08
+#define SGINT_ISTAT0_GFXDMA     0x10
+#define SGINT_ISTAT0_PPORT      0x20
+#define SGINT_ISTAT0_HPC2       0x40
+#define SGINT_ISTAT0_LIO2       0x80
+        u8 _imask0[3];
+        volatile u8 imask0;             /* Interrupt mask zero */
+        u8 _istat1[3];
+        volatile u8 istat1;             /* Interrupt status one */
+#define SGINT_ISTAT1_ISDNI      0x01
+#define SGINT_ISTAT1_PWR        0x02
+#define SGINT_ISTAT1_ISDNH      0x04
+#define SGINT_ISTAT1_LIO3       0x08
+#define SGINT_ISTAT1_HPC3       0x10
+#define SGINT_ISTAT1_AFAIL      0x20
+#define SGINT_ISTAT1_VIDEO      0x40
+#define SGINT_ISTAT1_GIO2       0x80
+        u8 _imask1[3];
+        volatile u8 imask1;             /* Interrupt mask one */
+        u8 _vmeistat[3];
+        volatile u8 vmeistat;           /* VME interrupt status */
+        u8 _cmeimask0[3];
+        volatile u8 cmeimask0;          /* VME interrupt mask zero */
+        u8 _cmeimask1[3];
+        volatile u8 cmeimask1;          /* VME interrupt mask one */
+        u8 _cmepol[3];
+        volatile u8 cmepol;             /* VME polarity */
+        u8 _tclear[3];
+        volatile u8 tclear;
+        u8 _errstat[3];
+        volatile u8 errstat;    /* Error status reg, reserved on INT2 */
+        u32 _unused0[2];
+        u8 _tcnt0[3];
+        volatile u8 tcnt0;              /* counter 0 */
+        u8 _tcnt1[3];
+        volatile u8 tcnt1;              /* counter 1 */
+        u8 _tcnt2[3];
+        volatile u8 tcnt2;              /* counter 2 */
+        u8 _tcword[3];
+        volatile u8 tcword;             /* control word */
+#define SGINT_TCWORD_BCD        0x01    /* Use BCD mode for counters */
+#define SGINT_TCWORD_MMASK      0x0e    /* Mode bitmask. */
+#define SGINT_TCWORD_MITC       0x00    /* IRQ on terminal count (doesn't work) */
+#define SGINT_TCWORD_MOS        0x02    /* One-shot IRQ mode. */
+#define SGINT_TCWORD_MRGEN      0x04    /* Normal rate generation */
+#define SGINT_TCWORD_MSWGEN     0x06    /* Square wave generator mode */
+#define SGINT_TCWORD_MSWST      0x08    /* Software strobe */
+#define SGINT_TCWORD_MHWST      0x0a    /* Hardware strobe */
+#define SGINT_TCWORD_CMASK      0x30    /* Command mask */
+#define SGINT_TCWORD_CLAT       0x00    /* Latch command */
+#define SGINT_TCWORD_CLSB       0x10    /* LSB read/write */
+#define SGINT_TCWORD_CMSB       0x20    /* MSB read/write */
+#define SGINT_TCWORD_CALL       0x30    /* Full counter read/write */
+#define SGINT_TCWORD_CNT0       0x00    /* Select counter zero */
+#define SGINT_TCWORD_CNT1       0x40    /* Select counter one */
+#define SGINT_TCWORD_CNT2       0x80    /* Select counter two */
+#define SGINT_TCWORD_CRBCK      0xc0    /* Readback command */
+};
+
+/*
+ * The timer is the good old 8254.  Unlike in PCs it's clocked at exactly 1MHz
+ */
+#define SGINT_TIMER_CLOCK       1000000
+
+/*
+ * This is the constant we're using for calibrating the counter.
+ */
+#define SGINT_TCSAMP_COUNTER    ((SGINT_TIMER_CLOCK / HZ) + 255)
+
+/* We need software copies of these because they are write only. */
+extern u8 sgi_ioc_reset, sgi_ioc_write;
+
+struct sgioc_regs {
+        struct pi1_regs pport;
+        u32 _unused0[2];
+        struct sgioc_uart_regs uart;
+        struct sgioc_keyb_regs kbdmouse;
+        u8 _gcsel[3];
+        volatile u8 gcsel;
+        u8 _genctrl[3];
+        volatile u8 genctrl;
+        u8 _panel[3];
+        volatile u8 panel;
+#define SGIOC_PANEL_POWERON     0x01
+#define SGIOC_PANEL_POWERINTR   0x02
+#define SGIOC_PANEL_VOLDNINTR   0x10
+#define SGIOC_PANEL_VOLDNHOLD   0x20
+#define SGIOC_PANEL_VOLUPINTR   0x40
+#define SGIOC_PANEL_VOLUPHOLD   0x80
+        u32 _unused1;
+        u8 _sysid[3];
+        volatile u8 sysid;
+#define SGIOC_SYSID_FULLHOUSE   0x01
+#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 
+#define SGIOC_SYSID_CHIPREV(x)  ((x & 0x1e) > 1)
+        u32 _unused2;
+        u8 _read[3];
+        volatile u8 read;
+        u32 _unused3;
+        u8 _dmasel[3];
+        volatile u8 dmasel;
+#define SGIOC_DMASEL_SCLK10MHZ  0x00    /* use 10MHZ serial clock */
+#define SGIOC_DMASEL_ISDNB      0x01    /* enable isdn B */
+#define SGIOC_DMASEL_ISDNA      0x02    /* enable isdn A */
+#define SGIOC_DMASEL_PPORT      0x04    /* use parallel DMA */
+#define SGIOC_DMASEL_SCLK667MHZ 0x10    /* use 6.67MHZ serial clock */
+#define SGIOC_DMASEL_SCLKEXT    0x20    /* use external serial clock */
+        u32 _unused4;
+        u8 _reset[3];
+        volatile u8 reset;
+#define SGIOC_RESET_PPORT       0x01    /* 0=parport reset, 1=nornal */
+#define SGIOC_RESET_KBDMOUSE    0x02    /* 0=kbdmouse reset, 1=normal */
+#define SGIOC_RESET_EISA        0x04    /* 0=eisa reset, 1=normal */
+#define SGIOC_RESET_ISDN        0x08    /* 0=isdn reset, 1=normal */
+#define SGIOC_RESET_LC0OFF      0x10    /* guiness: turn led off (red, else green) */
+#define SGIOC_RESET_LC1OFF      0x20    /* guiness: turn led off (green, else amber) */
+        u32 _unused5;
+        u8 _write[3];
+        volatile u8 write;
+#define SGIOC_WRITE_NTHRESH     0x01    /* use 4.5db threshhold */
+#define SGIOC_WRITE_TPSPEED     0x02    /* use 100ohm TP speed */
+#define SGIOC_WRITE_EPSEL       0x04    /* force cable mode: 1=AUI 0=TP */
+#define SGIOC_WRITE_EASEL       0x08    /* 1=autoselect 0=manual cable selection */
+#define SGIOC_WRITE_U1AMODE     0x10    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_U0AMODE     0x20    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_MLO         0x40    /* 1=4.75V 0=+5V */
+#define SGIOC_WRITE_MHI         0x80    /* 1=5.25V 0=+5V */
+        u32 _unused6;
+        struct sgint_regs int3;
+        u32 _unused7[16];
+        volatile u32 extio;             /* FullHouse only */
+#define EXTIO_S0_IRQ_3          0x8000  /* S0: vid.vsync */
+#define EXTIO_S0_IRQ_2          0x4000  /* S0: gfx.fifofull */
+#define EXTIO_S0_IRQ_1          0x2000  /* S0: gfx.int */
+#define EXTIO_S0_RETRACE        0x1000
+#define EXTIO_SG_IRQ_3          0x0800  /* SG: vid.vsync */
+#define EXTIO_SG_IRQ_2          0x0400  /* SG: gfx.fifofull */
+#define EXTIO_SG_IRQ_1          0x0200  /* SG: gfx.int */
+#define EXTIO_SG_RETRACE        0x0100
+#define EXTIO_GIO_33MHZ         0x0080
+#define EXTIO_EISA_BUSERR       0x0040
+#define EXTIO_MC_BUSERR         0x0020
+#define EXTIO_HPC3_BUSERR       0x0010
+#define EXTIO_S0_STAT_1         0x0008
+#define EXTIO_S0_STAT_0         0x0004
+#define EXTIO_SG_STAT_1         0x0002
+#define EXTIO_SG_STAT_0         0x0001
+};
+
+extern struct sgioc_regs *sgioc;
+extern struct sgint_regs *sgint;
+
+#endif
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
new file mode 100644
index 000000000000..97d73adb4e40
--- /dev/null
+++ b/include/asm-mips/sgi/ip22.h
@@ -0,0 +1,77 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ip22.h: Definitions for SGI IP22 machines
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ */
+
+#ifndef _SGI_IP22_H
+#define _SGI_IP22_H
+
+/* 
+ * These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
+ * are not supported this way. Driver is supposed to allocate HPC/MC
+ * interrupt as shareable and then look to proper status bit (see
+ * HAL2 driver). This will prevent many complications, trust me ;-)
+ */
+
+#include <asm/sgi/ioc.h>
+
+#define SGINT_EISA      0       /* 16 EISA irq levels (Indigo2) */
+#define SGINT_CPU       16      /* MIPS CPU define 8 interrupt sources */
+#define SGINT_LOCAL0    24      /* 8 local0 irq levels */
+#define SGINT_LOCAL1    32      /* 8 local1 irq levels */
+#define SGINT_LOCAL2    40      /* 8 local2 vectored irq levels */
+#define SGINT_LOCAL3    48      /* 8 local3 vectored irq levels */
+#define SGINT_END       56      /* End of 'spaces' */
+
+/*
+ * Individual interrupt definitions for the Indy and Indigo2
+ */
+
+#define SGI_SOFT_0_IRQ  SGINT_CPU + 0
+#define SGI_SOFT_1_IRQ  SGINT_CPU + 1
+#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
+#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
+#define SGI_8254_0_IRQ  SGINT_CPU + 4
+#define SGI_8254_1_IRQ  SGINT_CPU + 5
+#define SGI_BUSERR_IRQ  SGINT_CPU + 6
+#define SGI_TIMER_IRQ   SGINT_CPU + 7
+
+#define SGI_FIFO_IRQ    SGINT_LOCAL0 + 0        /* FIFO full */
+#define SGI_GIO_0_IRQ   SGI_FIFO_IRQ            /* GIO-0 */
+#define SGI_WD93_0_IRQ  SGINT_LOCAL0 + 1        /* 1st onboard WD93 */
+#define SGI_WD93_1_IRQ  SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
+#define SGI_ENET_IRQ    SGINT_LOCAL0 + 3        /* onboard ethernet */
+#define SGI_MCDMA_IRQ   SGINT_LOCAL0 + 4        /* MC DMA done */
+#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5        /* Parallel port */
+#define SGI_GIO_1_IRQ   SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
+#define SGI_MAP_0_IRQ   SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
+
+#define SGI_GPL0_IRQ    SGINT_LOCAL1 + 0        /* General Purpose LOCAL1_N<0> */
+#define SGI_PANEL_IRQ   SGINT_LOCAL1 + 1        /* front panel */
+#define SGI_GPL2_IRQ    SGINT_LOCAL1 + 2        /* General Purpose LOCAL1_N<2> */
+#define SGI_MAP_1_IRQ   SGINT_LOCAL1 + 3        /* Mappable interrupt 1 */
+#define SGI_HPCDMA_IRQ  SGINT_LOCAL1 + 4        /* HPC DMA done */
+#define SGI_ACFAIL_IRQ  SGINT_LOCAL1 + 5        /* AC fail */
+#define SGI_VINO_IRQ    SGINT_LOCAL1 + 6        /* Indy VINO */
+#define SGI_GIO_2_IRQ   SGINT_LOCAL1 + 7        /* Vert retrace / GIO-2 */
+
+/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
+#define SGI_VERT_IRQ    SGINT_LOCAL2 + 0        /* INT3: newport vertical status */
+#define SGI_EISA_IRQ    SGINT_LOCAL2 + 3        /* EISA interrupts */
+#define SGI_KEYBD_IRQ   SGINT_LOCAL2 + 4        /* keyboard */
+#define SGI_SERIAL_IRQ  SGINT_LOCAL2 + 5        /* onboard serial */
+
+#define ip22_is_fullhouse()     (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
+
+extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
+extern unsigned short ip22_nvram_read(int reg);
+
+#endif
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
new file mode 100644
index 000000000000..fd98f930607c
--- /dev/null
+++ b/include/asm-mips/sgi/mc.h
@@ -0,0 +1,231 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * mc.h: Definitions for SGI Memory Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#ifndef _SGI_MC_H
+#define _SGI_MC_H
+
+struct sgimc_regs {
+        u32 _unused0;
+        volatile u32 cpuctrl0;  /* CPU control register 0, readwrite */
+#define SGIMC_CCTRL0_REFS       0x0000000f /* REFS mask */
+#define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
+#define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
+#define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
+#define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
+#define SGIMC_CCTRL0_WDOG       0x00000100 /* Watchdog timer enable */
+#define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
+#define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
+#define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
+#define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
+#define SGIMC_CCTRL0_IENAB      0x00002000 /* Allow interrupts from MC */
+#define SGIMC_CCTRL0_ESNOOP     0x00004000 /* Snooping I/O enable */
+#define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
+#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
+#define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
+#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
+#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
+#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
+#define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
+        u32 _unused1;
+        volatile u32 cpuctrl1;  /* CPU control register 1, readwrite */
+#define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
+#define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
+#define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
+#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
+#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
+
+        u32 _unused2;
+        volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
+
+        u32 _unused3;
+        volatile u32 systemid;  /* MC system ID register, readonly */
+#define SGIMC_SYSID_MASKREV     0x0000000f /* Revision of MC controller */
+#define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
+
+        u32 _unused4[3];
+        volatile u32 divider;   /* Divider reg for RPSS */
+
+        u32 _unused5;
+        volatile u32 eeprom;    /* EEPROM byte reg for r4k */
+#define SGIMC_EEPROM_PRE        0x00000001 /* eeprom chip PRE pin assertion */
+#define SGIMC_EEPROM_CSEL       0x00000002 /* Active high, eeprom chip select */
+#define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
+#define SGIMC_EEPROM_SDATAO     0x00000008 /* Serial EEPROM data-out */
+#define SGIMC_EEPROM_SDATAI     0x00000010 /* Serial EEPROM data-in */
+
+        u32 _unused6[3];
+        volatile u32 rcntpre;   /* Preload refresh counter */
+
+        u32 _unused7;
+        volatile u32 rcounter;  /* Readonly refresh counter */
+
+        u32 _unused8[13];
+        volatile u32 giopar;    /* Parameter word for GIO64 */
+#define SGIMC_GIOPAR_HPC64      0x00000001 /* HPC talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_GFX64      0x00000002 /* GFX talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_EXP064     0x00000004 /* EXP(slot0) talks using 64-bits */
+#define SGIMC_GIOPAR_EXP164     0x00000008 /* EXP(slot1) talks using 64-bits */
+#define SGIMC_GIOPAR_EISA64     0x00000010 /* EISA bus talks 64-bits to GIO */
+#define SGIMC_GIOPAR_HPC264     0x00000020 /* 2nd HPX talks 64-bits to GIO */
+#define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
+#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
+#define SGIMC_GIOPAR_ONEBUS     0x00000400 /* Exists one GIO64 pipelined bus */
+#define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
+#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
+#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
+#define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
+#define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
+
+        u32 _unused9;
+        volatile u32 cputp;     /* CPU bus arb time period */
+
+        u32 _unused10[3];
+        volatile u32 lbursttp;  /* Time period for long bursts */
+
+        /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
+         * be the same size. The size encoding for supported SIMMs is bellow */
+        u32 _unused11[9];
+        volatile u32 mconfig0;  /* Memory config register zero */
+        u32 _unused12;
+        volatile u32 mconfig1;  /* Memory config register one */
+#define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
+#define SGIMC_MCONFIG_RMASK     0x00001f00 /* Ram config bitmask */
+#define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
+#define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
+
+        u32 _unused13;
+        volatile u32 cmacc;        /* Mem access config for CPU */
+        u32 _unused14;
+        volatile u32 gmacc;        /* Mem access config for GIO */
+
+        /* This define applies to both cmacc and gmacc registers above. */
+#define SGIMC_MACC_ALIASBIG     0x20000000 /* 512MB home for alias */
+
+        /* Error address/status regs from GIO and CPU perspectives. */
+        u32 _unused15;
+        volatile u32 cerr;      /* Error address reg for CPU */
+        u32 _unused16;
+        volatile u32 cstat;     /* Status reg for CPU */
+#define SGIMC_CSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_CSTAT_PAR         0x00000200 /* CPU parity error */
+#define SGIMC_CSTAT_ADDR        0x00000400 /* memory bus error bad addr */
+#define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
+#define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
+#define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
+#define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
+#define SGIMC_CSTAT_RD_PAR      (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
+
+        u32 _unused17;
+        volatile u32 gerr;      /* Error address reg for GIO */
+        u32 _unused18;
+        volatile u32 gstat;     /* Status reg for GIO */
+#define SGIMC_GSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_GSTAT_WR          0x00000200 /* write parity error */
+#define SGIMC_GSTAT_TIME        0x00000400 /* GIO bus timed out */
+#define SGIMC_GSTAT_PROM        0x00000800 /* write to PROM when PROM_EN not set */
+#define SGIMC_GSTAT_ADDR        0x00001000 /* parity error on addr cycle */
+#define SGIMC_GSTAT_BC          0x00002000 /* parity error on byte count cycle */
+#define SGIMC_GSTAT_PIO_RD      0x00004000 /* read data parity on pio */
+#define SGIMC_GSTAT_PIO_WR      0x00008000 /* write data parity on pio */
+
+        /* Special hard bus locking registers. */
+        u32 _unused19;
+        volatile u32 syssembit;         /* Uni-bit system semaphore */
+        u32 _unused20;
+        volatile u32 mlock;             /* Global GIO memory access lock */
+        u32 _unused21;
+        volatile u32 elock;             /* Locks EISA from GIO accesses */
+
+        /* GIO dma control registers. */
+        u32 _unused22[15];
+        volatile u32 gio_dma_trans;     /* DMA mask to translation GIO addrs */
+        u32 _unused23;
+        volatile u32 gio_dma_sbits;     /* DMA GIO addr substitution bits */
+        u32 _unused24;
+        volatile u32 dma_intr_cause;    /* DMA IRQ cause indicator bits */
+        u32 _unused25;
+        volatile u32 dma_ctrl;          /* Main DMA control reg */
+
+        /* DMA TLB entry 0 */
+        u32 _unused26[5];
+        volatile u32 dtlb_hi0;
+        u32 _unused27;
+        volatile u32 dtlb_lo0;
+
+        /* DMA TLB entry 1 */
+        u32 _unused28;
+        volatile u32 dtlb_hi1;
+        u32 _unused29;
+        volatile u32 dtlb_lo1;
+
+        /* DMA TLB entry 2 */
+        u32 _unused30;
+        volatile u32 dtlb_hi2;
+        u32 _unused31;
+        volatile u32 dtlb_lo2;
+
+        /* DMA TLB entry 3 */
+        u32 _unused32;
+        volatile u32 dtlb_hi3;
+        u32 _unused33;
+        volatile u32 dtlb_lo3;
+        
+        u32 _unused34[0x0392];
+        
+        u32 _unused35;
+        volatile u32 rpsscounter;       /* Chirps at 100ns */
+
+        u32 _unused36[0x1000/4-2*4];
+        
+        u32 _unused37;
+        volatile u32 maddronly;         /* Address DMA goes at */
+        u32 _unused38;
+        volatile u32 maddrpdeflts;      /* Same as above, plus set defaults */
+        u32 _unused39;
+        volatile u32 dmasz;             /* DMA count */
+        u32 _unused40;
+        volatile u32 ssize;             /* DMA stride size */
+        u32 _unused41;
+        volatile u32 gmaddronly;        /* Set GIO DMA but don't start trans */
+        u32 _unused42;
+        volatile u32 dmaddnpgo;         /* Set GIO DMA addr + start transfer */
+        u32 _unused43;
+        volatile u32 dmamode;           /* DMA mode config bit settings */
+        u32 _unused44;
+        volatile u32 dmaccount;         /* Zoom and byte count for DMA */
+        u32 _unused45;
+        volatile u32 dmastart;          /* Pedal to the metal. */
+        u32 _unused46;
+        volatile u32 dmarunning;        /* DMA op is in progress */
+        u32 _unused47;
+        volatile u32 maddrdefstart;     /* Set dma addr, defaults, and kick it */
+};
+
+extern struct sgimc_regs *sgimc;
+#define SGIMC_BASE              0x1fa00000      /* physical */
+
+/* Base location of the two ram banks found in IP2[0268] machines. */
+#define SGIMC_SEG0_BADDR        0x08000000
+#define SGIMC_SEG1_BADDR        0x20000000
+
+/* Maximum size of the above banks are per machine. */
+#define SGIMC_SEG0_SIZE_ALL             0x10000000 /* 256MB */
+#define SGIMC_SEG1_SIZE_IP20_IP22       0x08000000 /* 128MB */
+#define SGIMC_SEG1_SIZE_IP26_IP28       0x20000000 /* 512MB */
+
+extern void sgimc_init(void);
+
+#endif /* _SGI_MC_H */
diff --git a/include/asm-mips/sgi/pi1.h b/include/asm-mips/sgi/pi1.h
new file mode 100644
index 000000000000..c9506915dc5c
--- /dev/null
+++ b/include/asm-mips/sgi/pi1.h
@@ -0,0 +1,71 @@
+/*
+ * pi1.h: Definitions for SGI PI1 parallel port
+ */
+
+#ifndef _SGI_PI1_H
+#define _SGI_PI1_H
+
+struct pi1_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _ctrl[3];
+        volatile u8 ctrl;
+#define PI1_CTRL_STROBE_N       0x01
+#define PI1_CTRL_AFD_N          0x02
+#define PI1_CTRL_INIT_N         0x04
+#define PI1_CTRL_SLIN_N         0x08
+#define PI1_CTRL_IRQ_ENA        0x10
+#define PI1_CTRL_DIR            0x20
+#define PI1_CTRL_SEL            0x40
+        u8 _status[3];
+        volatile u8 status;
+#define PI1_STAT_DEVID          0x03    /* bits 0-1 */
+#define PI1_STAT_NOINK          0x04    /* SGI MODE only */
+#define PI1_STAT_ERROR          0x08
+#define PI1_STAT_ONLINE         0x10
+#define PI1_STAT_PE             0x20
+#define PI1_STAT_ACK            0x40
+#define PI1_STAT_BUSY           0x80
+        u8 _dmactrl[3];
+        volatile u8 dmactrl;
+#define PI1_DMACTRL_FIFO_EMPTY  0x01    /* fifo empty R/O */
+#define PI1_DMACTRL_ABORT       0x02    /* reset DMA and internal fifo W/O */
+#define PI1_DMACTRL_STDMODE     0x00    /* bits 2-3 */
+#define PI1_DMACTRL_SGIMODE     0x04    /* bits 2-3 */
+#define PI1_DMACTRL_RICOHMODE   0x08    /* bits 2-3 */
+#define PI1_DMACTRL_HPMODE      0x0c    /* bits 2-3 */
+#define PI1_DMACTRL_BLKMODE     0x10    /* block mode */
+#define PI1_DMACTRL_FIFO_CLEAR  0x20    /* clear fifo W/O */
+#define PI1_DMACTRL_READ        0x40    /* read */
+#define PI1_DMACTRL_RUN         0x80    /* pedal to the metal */
+        u8 _intstat[3];
+        volatile u8 intstat;
+#define PI1_INTSTAT_ACK         0x04
+#define PI1_INTSTAT_FEMPTY      0x08
+#define PI1_INTSTAT_NOINK       0x10
+#define PI1_INTSTAT_ONLINE      0x20
+#define PI1_INTSTAT_ERR         0x40
+#define PI1_INTSTAT_PE          0x80
+        u8 _intmask[3];
+        volatile u8 intmask;            /* enabled low, reset high*/
+#define PI1_INTMASK_ACK         0x04
+#define PI1_INTMASK_FIFO_EMPTY  0x08
+#define PI1_INTMASK_NOINK       0x10
+#define PI1_INTMASK_ONLINE      0x20
+#define PI1_INTMASK_ERR         0x40
+#define PI1_INTMASK_PE          0x80
+        u8 _timer1[3];
+        volatile u8 timer1;
+#define PI1_TIME1               0x27
+        u8 _timer2[3];
+        volatile u8 timer2;
+#define PI1_TIME2               0x13
+        u8 _timer3[3];
+        volatile u8 timer3;
+#define PI1_TIME3               0x10
+        u8 _timer4[3];
+        volatile u8 timer4;
+#define PI1_TIME4               0x00
+};
+
+#endif
diff --git a/include/asm-mips/sgi/sgi.h b/include/asm-mips/sgi/sgi.h
new file mode 100644
index 000000000000..645cea7c0f8e
--- /dev/null
+++ b/include/asm-mips/sgi/sgi.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * sgi.h: Definitions specific to SGI machines.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@sgi.com)
+ */
+#ifndef _ASM_SGI_SGI_H
+#define _ASM_SGI_SGI_H
+
+/* UP=UniProcessor MP=MultiProcessor(capable) */
+enum sgi_mach {
+        ip4,    /* R2k UP */
+        ip5,    /* R2k MP */
+        ip6,    /* R3k UP */
+        ip7,    /* R3k MP */
+        ip9,    /* R3k UP */
+        ip12,   /* R3kA UP, Indigo */
+        ip15,   /* R3kA MP */
+        ip17,   /* R4K UP */
+        ip19,   /* R4K MP */
+        ip20,   /* R4K UP, Indigo */
+        ip21,   /* TFP MP */
+        ip22,   /* R4x00 UP, Indigo2 */
+        ip25,   /* R10k MP */
+        ip26,   /* TFP UP, Indigo2 */
+        ip27,   /* R10k MP, R12k MP, Origin */
+        ip28,   /* R10k UP, Indigo2 */
+        ip30,   /* Octane */
+        ip32,   /* O2 */
+};
+
+extern enum sgi_mach sgimach;
+extern void sgi_sysinit(void);
+
+/* Many I/O space registers are byte sized and are contained within
+ * one byte per word, specifically the MSB, this macro helps out.
+ */
+#ifdef __MIPSEL__
+#define SGI_MSB(regaddr)   (regaddr)
+#else
+#define SGI_MSB(regaddr)   ((regaddr) | 0x3)
+#endif
+
+#endif /* _ASM_SGI_SGI_H */
diff --git a/include/asm-mips/sgialib.h b/include/asm-mips/sgialib.h
new file mode 100644
index 000000000000..73f097315502
--- /dev/null
+++ b/include/asm-mips/sgialib.h
@@ -0,0 +1,127 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI ARCS firmware interface library for the Linux kernel.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGIALIB_H
+#define _ASM_SGIALIB_H
+
+#include <asm/sgiarcs.h>
+
+extern struct linux_romvec *romvec;
+extern int prom_argc;
+
+extern LONG *_prom_argv, *_prom_envp;
+
+/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer.
+   These macros take care of sign extension.  */
+#define prom_argv(index) ((char *) (long) _prom_argv[(index)])
+#define prom_argc(index) ((char *) (long) _prom_argc[(index)])
+
+extern int prom_flags;
+
+#define PROM_FLAG_ARCS                  1
+#define PROM_FLAG_USE_AS_CONSOLE        2
+#define PROM_FLAG_DONT_FREE_TEMP        4
+
+/* Simple char-by-char console I/O. */
+extern void prom_putchar(char c);
+extern char prom_getchar(void);
+
+/* Generic printf() using ARCS console I/O. */
+extern void prom_printf(char *fmt, ...);
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    32
+struct prom_pmemblock {
+        LONG    base;           /* Within KSEG0 or XKPHYS. */
+        ULONG   size;           /* In bytes. */
+        ULONG   type;           /* free or prom memory */
+};
+
+/* Get next memory descriptor after CURR, returns first descriptor
+ * in chain is CURR is NULL.
+ */
+extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
+#define PROM_NULL_MDESC   ((struct linux_mdesc *) 0)
+
+/* Called by prom_init to setup the physical memory pmemblock
+ * array.
+ */
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+
+/* PROM device tree library routines. */
+#define PROM_NULL_COMPONENT ((pcomponent *) 0)
+
+/* Get sibling component of THIS. */
+extern pcomponent *ArcGetPeer(pcomponent *this);
+
+/* Get child component of THIS. */
+extern pcomponent *ArcGetChild(pcomponent *this);
+
+/* Get parent component of CHILD. */
+extern pcomponent *prom_getparent(pcomponent *child);
+
+/* Copy component opaque data of component THIS into BUFFER
+ * if component THIS has opaque data.  Returns success or
+ * failure status.
+ */
+extern long prom_getcdata(void *buffer, pcomponent *this);
+
+/* Other misc. component routines. */
+extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
+extern long prom_delcomponent(pcomponent *this);
+extern pcomponent *prom_componentbypath(char *path);
+
+/* This is called at prom_init time to identify the
+ * ARC architecture we are running on
+ */
+extern void prom_identify_arch(void);
+
+/* Environment variable routines. */
+extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
+extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
+
+/* ARCS command line acquisition and parsing. */
+extern char *prom_getcmdline(void);
+extern void prom_init_cmdline(void);
+
+/* Acquiring info about the current time, etc. */
+extern struct linux_tinfo *prom_gettinfo(void);
+extern unsigned long prom_getrtime(void);
+
+/* File operations. */
+extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
+extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
+extern long prom_close(unsigned long fd);
+extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+extern long prom_getrstatus(unsigned long fd);
+extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
+extern long prom_mount(char *name, enum linux_mountops op);
+extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
+extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
+
+/* Running stand-along programs. */
+extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
+extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
+extern long prom_exec(char *name, long argc, char **argv, char **envp);
+
+/* Misc. routines. */
+extern VOID prom_halt(VOID) __attribute__((noreturn));
+extern VOID prom_powerdown(VOID) __attribute__((noreturn));
+extern VOID prom_restart(VOID) __attribute__((noreturn));
+extern VOID ArcReboot(VOID) __attribute__((noreturn));
+extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
+extern long prom_cfgsave(VOID);
+extern struct linux_sysid *prom_getsysid(VOID);
+extern VOID ArcFlushAllCaches(VOID);
+extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
+
+#endif /* _ASM_SGIALIB_H */
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
new file mode 100644
index 000000000000..59450335f049
--- /dev/null
+++ b/include/asm-mips/sgiarcs.h
@@ -0,0 +1,549 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ARC firmware interface defines.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SGIARCS_H
+#define _ASM_SGIARCS_H
+
+#include <linux/config.h>
+#include <asm/types.h>
+#include <asm/arc/types.h>
+
+/* Various ARCS error codes. */
+#define PROM_ESUCCESS                   0x00
+#define PROM_E2BIG                      0x01
+#define PROM_EACCESS                    0x02
+#define PROM_EAGAIN                     0x03
+#define PROM_EBADF                      0x04
+#define PROM_EBUSY                      0x05
+#define PROM_EFAULT                     0x06
+#define PROM_EINVAL                     0x07
+#define PROM_EIO                        0x08
+#define PROM_EISDIR                     0x09
+#define PROM_EMFILE                     0x0a
+#define PROM_EMLINK                     0x0b
+#define PROM_ENAMETOOLONG               0x0c
+#define PROM_ENODEV                     0x0d
+#define PROM_ENOENT                     0x0e
+#define PROM_ENOEXEC                    0x0f
+#define PROM_ENOMEM                     0x10
+#define PROM_ENOSPC                     0x11
+#define PROM_ENOTDIR                    0x12
+#define PROM_ENOTTY                     0x13
+#define PROM_ENXIO                      0x14
+#define PROM_EROFS                      0x15
+/* SGI ARCS specific errno's. */
+#define PROM_EADDRNOTAVAIL              0x1f
+#define PROM_ETIMEDOUT                  0x20
+#define PROM_ECONNABORTED               0x21
+#define PROM_ENOCONNECT                 0x22
+
+/* Device classes, types, and identifiers for prom
+ * device inventory queries.
+ */
+enum linux_devclass {
+        system, processor, cache, adapter, controller, peripheral, memory
+};
+
+enum linux_devtypes {
+        /* Generic stuff. */
+        Arc, Cpu, Fpu,
+
+        /* Primary insn and data caches. */
+        picache, pdcache,
+
+        /* Secondary insn, data, and combined caches. */
+        sicache, sdcache, sccache,
+
+        memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter,
+        multifunc_adapter, dsk_controller, tp_controller, cdrom_controller,
+        worm_controller, serial_controller, net_controller, disp_controller,
+        parallel_controller, ptr_controller, kbd_controller, audio_controller,
+        misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral,
+        modem_peripheral, monitor_peripheral, printer_peripheral,
+        ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral,
+        net_peripheral, misc_peripheral, anon
+};
+
+enum linux_identifier {
+        bogus, ronly, removable, consin, consout, input, output
+};
+
+/* A prom device tree component. */
+struct linux_component {
+        enum linux_devclass     class;  /* node class */
+        enum linux_devtypes     type;   /* node type */
+        enum linux_identifier   iflags; /* node flags */
+        USHORT                  vers;   /* node version */
+        USHORT                  rev;    /* node revision */
+        ULONG                   key;    /* completely magic */
+        ULONG                   amask;  /* XXX affinity mask??? */
+        ULONG                   cdsize; /* size of configuration data */
+        ULONG                   ilen;   /* length of string identifier */
+        _PULONG                 iname;  /* string identifier */
+};
+typedef struct linux_component pcomponent;
+
+struct linux_sysid {
+        char vend[8], prod[8];
+};
+
+/* ARCS prom memory descriptors. */
+enum arcs_memtypes {
+        arcs_eblock,  /* exception block */
+        arcs_rvpage,  /* ARCS romvec page */
+        arcs_fcontig, /* Contiguous and free */
+        arcs_free,    /* Generic free memory */
+        arcs_bmem,    /* Borken memory, don't use */
+        arcs_prog,    /* A loaded program resides here */
+        arcs_atmp,    /* ARCS temporary storage area, wish Sparc OpenBoot told this */
+        arcs_aperm,   /* ARCS permanent storage... */
+};
+
+/* ARC has slightly different types than ARCS */
+enum arc_memtypes {
+        arc_eblock,  /* exception block */
+        arc_rvpage,  /* romvec page */
+        arc_free,    /* Generic free memory */
+        arc_bmem,    /* Borken memory, don't use */
+        arc_prog,    /* A loaded program resides here */
+        arc_atmp,    /* temporary storage area */
+        arc_aperm,   /* permanent storage */
+        arc_fcontig, /* Contiguous and free */
+};
+
+union linux_memtypes {
+    enum arcs_memtypes arcs;
+    enum arc_memtypes arc;
+};
+
+struct linux_mdesc {
+        union linux_memtypes type;
+        ULONG base;
+        ULONG pages;
+};
+
+/* Time of day descriptor. */
+struct linux_tinfo {
+        unsigned short yr;
+        unsigned short mnth;
+        unsigned short day;
+        unsigned short hr;
+        unsigned short min;
+        unsigned short sec;
+        unsigned short msec;
+};
+
+/* ARCS virtual dirents. */
+struct linux_vdirent {
+        ULONG namelen;
+        unsigned char attr;
+        char fname[32]; /* XXX imperical, should be a define */
+};
+
+/* Other stuff for files. */
+enum linux_omode {
+        rdonly, wronly, rdwr, wronly_creat, rdwr_creat,
+        wronly_ssede, rdwr_ssede, dirent, dirent_creat
+};
+
+enum linux_seekmode {
+        absolute, relative
+};
+
+enum linux_mountops {
+        media_load, media_unload
+};
+
+/* This prom has a bolixed design. */
+struct linux_bigint {
+#ifdef __MIPSEL__
+        u32 lo;
+        s32 hi;
+#else /* !(__MIPSEL__) */
+        s32 hi;
+        u32 lo;
+#endif
+};
+
+struct linux_finfo {
+        struct linux_bigint   begin;
+        struct linux_bigint   end;
+        struct linux_bigint   cur;
+        enum linux_devtypes   dtype;
+        unsigned long         namelen;
+        unsigned char         attr;
+        char                  name[32]; /* XXX imperical, should be define */
+};
+
+/* This describes the vector containing function pointers to the ARC
+   firmware functions.  */
+struct linux_romvec {
+        LONG    load;                   /* Load an executable image. */
+        LONG    invoke;                 /* Invoke a standalong image. */
+        LONG    exec;                   /* Load and begin execution of a
+                                           standalone image. */
+        LONG    halt;                   /* Halt the machine. */
+        LONG    pdown;                  /* Power down the machine. */
+        LONG    restart;                /* XXX soft reset??? */
+        LONG    reboot;                 /* Reboot the machine. */
+        LONG    imode;                  /* Enter PROM interactive mode. */
+        LONG    _unused1;               /* Was ReturnFromMain(). */
+
+        /* PROM device tree interface. */
+        LONG    next_component;
+        LONG    child_component;
+        LONG    parent_component;
+        LONG    component_data;
+        LONG    child_add;
+        LONG    comp_del;
+        LONG    component_by_path;
+
+        /* Misc. stuff. */
+        LONG    cfg_save;
+        LONG    get_sysid;
+
+        /* Probing for memory. */
+        LONG    get_mdesc;
+        LONG    _unused2;               /* was Signal() */
+
+        LONG    get_tinfo;
+        LONG    get_rtime;
+
+        /* File type operations. */
+        LONG    get_vdirent;
+        LONG    open;
+        LONG    close;
+        LONG    read;
+        LONG    get_rstatus;
+        LONG    write;
+        LONG    seek;
+        LONG    mount;
+
+        /* Dealing with firmware environment variables. */
+        LONG    get_evar;
+        LONG    set_evar;
+
+        LONG    get_finfo;
+        LONG    set_finfo;
+
+        /* Miscellaneous. */
+        LONG    cache_flush;
+        LONG    TestUnicodeCharacter;           /* ARC; not sure if ARCS too */
+        LONG    GetDisplayStatus;
+};
+
+/* The SGI ARCS parameter block is in a fixed location for standalone
+ * programs to access PROM facilities easily.
+ */
+typedef struct _SYSTEM_PARAMETER_BLOCK {
+        ULONG                   magic;          /* magic cookie */
+#define PROMBLOCK_MAGIC      0x53435241
+
+        ULONG                   len;            /* length of parm block */
+        USHORT                  ver;            /* ARCS firmware version */
+        USHORT                  rev;            /* ARCS firmware revision */
+        _PLONG                  rs_block;       /* Restart block. */
+        _PLONG                  dbg_block;      /* Debug block. */
+        _PLONG                  gevect;         /* XXX General vector??? */
+        _PLONG                  utlbvect;       /* XXX UTLB vector??? */
+        ULONG                   rveclen;        /* Size of romvec struct. */
+        _PVOID                  romvec;         /* Function interface. */
+        ULONG                   pveclen;        /* Length of private vector. */
+        _PVOID                  pvector;        /* Private vector. */
+        ULONG                   adap_cnt;       /* Adapter count. */
+        ULONG                   adap_typ0;      /* First adapter type. */
+        ULONG                   adap_vcnt0;     /* Adapter 0 vector count. */
+        _PVOID                  adap_vector;    /* Adapter 0 vector ptr. */
+        ULONG                   adap_typ1;      /* Second adapter type. */
+        ULONG                   adap_vcnt1;     /* Adapter 1 vector count. */
+        _PVOID                  adap_vector1;   /* Adapter 1 vector ptr. */
+        /* More adapter vectors go here... */
+} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK;
+
+#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000)
+#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec)
+
+/* Cache layout parameter block. */
+union linux_cache_key {
+        struct param {
+#ifdef __MIPSEL__
+                unsigned short size;
+                unsigned char lsize;
+                unsigned char bsize;
+#else /* !(__MIPSEL__) */
+                unsigned char bsize;
+                unsigned char lsize;
+                unsigned short size;
+#endif
+        } info;
+        unsigned long allinfo;
+};
+
+/* Configuration data. */
+struct linux_cdata {
+        char *name;
+        int mlen;
+        enum linux_devtypes type;
+};
+
+/* Common SGI ARCS firmware file descriptors. */
+#define SGIPROM_STDIN     0
+#define SGIPROM_STDOUT    1
+
+/* Common SGI ARCS firmware file types. */
+#define SGIPROM_ROFILE    0x01  /* read-only file */
+#define SGIPROM_HFILE     0x02  /* hidden file */
+#define SGIPROM_SFILE     0x04  /* System file */
+#define SGIPROM_AFILE     0x08  /* Archive file */
+#define SGIPROM_DFILE     0x10  /* Directory file */
+#define SGIPROM_DELFILE   0x20  /* Deleted file */
+
+/* SGI ARCS boot record information. */
+struct sgi_partition {
+        unsigned char flag;
+#define SGIPART_UNUSED 0x00
+#define SGIPART_ACTIVE 0x80
+
+        unsigned char shead, ssect, scyl; /* unused */
+        unsigned char systype; /* OS type, Irix or NT */
+        unsigned char ehead, esect, ecyl; /* unused */
+        unsigned char rsect0, rsect1, rsect2, rsect3;
+        unsigned char tsect0, tsect1, tsect2, tsect3;
+};
+
+#define SGIBBLOCK_MAGIC   0xaa55
+#define SGIBBLOCK_MAXPART 0x0004
+
+struct sgi_bootblock {
+        unsigned char _unused[446];
+        struct sgi_partition partitions[SGIBBLOCK_MAXPART];
+        unsigned short magic;
+};
+
+/* BIOS parameter block. */
+struct sgi_bparm_block {
+        unsigned short bytes_sect;    /* bytes per sector */
+        unsigned char  sect_clust;    /* sectors per cluster */
+        unsigned short sect_resv;     /* reserved sectors */
+        unsigned char  nfats;         /* # of allocation tables */
+        unsigned short nroot_dirents; /* # of root directory entries */
+        unsigned short sect_volume;   /* sectors in volume */
+        unsigned char  media_type;    /* media descriptor */
+        unsigned short sect_fat;      /* sectors per allocation table */
+        unsigned short sect_track;    /* sectors per track */
+        unsigned short nheads;        /* # of heads */
+        unsigned short nhsects;       /* # of hidden sectors */
+};
+
+struct sgi_bsector {
+        unsigned char   jmpinfo[3];
+        unsigned char   manuf_name[8];
+        struct sgi_bparm_block info;
+};
+
+/* Debugging block used with SGI symmon symbolic debugger. */
+#define SMB_DEBUG_MAGIC   0xfeeddead
+struct linux_smonblock {
+        unsigned long   magic;
+        void            (*handler)(void);  /* Breakpoint routine. */
+        unsigned long   dtable_base;       /* Base addr of dbg table. */
+        int             (*printf)(const char *fmt, ...);
+        unsigned long   btable_base;       /* Breakpoint table. */
+        unsigned long   mpflushreqs;       /* SMP cache flush request list. */
+        unsigned long   ntab;              /* Name table. */
+        unsigned long   stab;              /* Symbol table. */
+        int             smax;              /* Max # of symbols. */
+};
+
+/*
+ * Macros for calling a 32-bit ARC implementation from 64-bit code
+ */
+
+#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32)
+
+#define __arc_clobbers                                                  \
+        "$2","$3" /* ... */, "$8","$9","$10","$11",                     \
+        "$12","$13","$14","$15","$16","$24","$25","$31"
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec)                                                   \
+        : __arc_clobbers, "$4","$5","$6","$7");                         \
+        (unsigned long) __res;                                          \
+})
+
+#define ARC_CALL1(dest,a1)                                              \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1)                                       \
+        : __arc_clobbers, "$5","$6","$7");                              \
+        (unsigned long) __res;                                          \
+})
+
+#define ARC_CALL2(dest,a1,a2)                                           \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2)                           \
+        : __arc_clobbers, "$6","$7");                                   \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest,a1,a2,a3)                                        \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3)               \
+        : __arc_clobbers, "$7");                                        \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest,a1,a2,a3,a4)                                     \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3),              \
+          "r" (__a4)                                                    \
+        : __arc_clobbers);                                              \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest,a1,a2,a3,a4,a5)                                  \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
+        register signed int __a5 = (a5);                                \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "sw\t%7, 16($29)\n\t"                                           \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec),                                                  \
+          "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4),               \
+          "r" (__a5)                                                    \
+        : __arc_clobbers);                                              \
+        __res;                                                          \
+})
+
+#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */
+
+#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) ||                \
+    (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64))
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long (*__vec)(void) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec();                                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL1(dest,a1)                                              \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long (*__vec)(long) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec(__a1);                                            \
+        __res;                                                          \
+})
+
+#define ARC_CALL2(dest,a1,a2)                                           \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long (*__vec)(long, long) = (void *) romvec->dest;              \
+                                                                        \
+        __res = __vec(__a1, __a2);                                      \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest,a1,a2,a3)                                        \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long (*__vec)(long, long, long) = (void *) romvec->dest;        \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3);                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest,a1,a2,a3,a4)                                     \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long (*__vec)(long, long, long, long) = (void *) romvec->dest;  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4);                          \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest,a1,a2,a3,a4,a5)                                  \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long __a5 = (long) (a5);                                        \
+        long (*__vec)(long, long, long, long, long);                    \
+        __vec = (void *) romvec->dest;                                  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4, __a5);                    \
+        __res;                                                          \
+})
+#endif /* both kernel and ARC either 32-bit or 64-bit */
+
+#endif /* _ASM_SGIARCS_H */
diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h
new file mode 100644
index 000000000000..876442fcfb32
--- /dev/null
+++ b/include/asm-mips/sgidefs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Using a Linux compiler for building Linux seems logic but not to
+ * everybody.
+ */
+#ifndef __linux__
+#error Use a Linux compiler or give up.
+#endif
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1         1
+#define _MIPS_ISA_MIPS2         2
+#define _MIPS_ISA_MIPS3         3
+#define _MIPS_ISA_MIPS4         4
+#define _MIPS_ISA_MIPS5         5
+#define _MIPS_ISA_MIPS32        6
+#define _MIPS_ISA_MIPS64        7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32         1
+#define _MIPS_SIM_NABI32        2
+#define _MIPS_SIM_ABI64         3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/include/asm-mips/shmbuf.h b/include/asm-mips/shmbuf.h
new file mode 100644
index 000000000000..f994438277bf
--- /dev/null
+++ b/include/asm-mips/shmbuf.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_SHMBUF_H
+#define _ASM_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 32-bit rsp. 64-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        __kernel_time_t         shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASM_SHMBUF_H */
diff --git a/include/asm-mips/shmparam.h b/include/asm-mips/shmparam.h
new file mode 100644
index 000000000000..09290720751c
--- /dev/null
+++ b/include/asm-mips/shmparam.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_SHMPARAM_H
+#define _ASM_SHMPARAM_H
+
+#define __ARCH_FORCE_SHMLBA     1
+
+#define SHMLBA 0x40000                  /* attach addr a multiple of this */
+
+#endif /* _ASM_SHMPARAM_H */
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
new file mode 100644
index 000000000000..d7b11b6c7c32
--- /dev/null
+++ b/include/asm-mips/sibyte/board.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _SIBYTE_BOARD_H
+#define _SIBYTE_BOARD_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SIBYTE_BOARD
+
+#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
+    defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
+    defined(CONFIG_SIBYTE_LITTLESUR)
+#include <asm/sibyte/swarm.h>
+#endif
+
+#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
+#include <asm/sibyte/sentosa.h>
+#endif
+
+#ifdef CONFIG_SIBYTE_CARMEL
+#include <asm/sibyte/carmel.h>
+#endif
+
+#ifdef __ASSEMBLY__
+
+#ifdef LEDS_PHYS
+#define setleds(t0,t1,c0,c1,c2,c3) \
+        li      t0, (LEDS_PHYS|0xa0000000); \
+        li      t1, c0; \
+        sb      t1, 0x18(t0); \
+        li      t1, c1; \
+        sb      t1, 0x10(t0); \
+        li      t1, c2; \
+        sb      t1, 0x08(t0); \
+        li      t1, c3; \
+        sb      t1, 0x00(t0)
+#else
+#define setleds(t0,t1,c0,c1,c2,c3)
+#endif /* LEDS_PHYS */
+
+#else
+
+#ifdef LEDS_PHYS
+extern void setleds(char *str);
+#else
+#define setleds(s) do { } while (0)
+#endif /* LEDS_PHYS */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_SIBYTE_BOARD */
+
+#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
new file mode 100644
index 000000000000..7ac5da13ce8a
--- /dev/null
+++ b/include/asm-mips/sibyte/carmel.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_CARMEL_H
+#define __ASM_SIBYTE_CARMEL_H
+
+#include <linux/config.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#define SIBYTE_BOARD_NAME "Carmel"
+
+#define GPIO_PHY_INTERRUPT      2 
+#define GPIO_NONMASKABLE_INT    3 
+#define GPIO_CF_INSERTED        6 
+#define GPIO_MONTEREY_RESET     7 
+#define GPIO_QUADUART_INT       8 
+#define GPIO_CF_INT             9 
+#define GPIO_FPGA_CCLK          10
+#define GPIO_FPGA_DOUT          11
+#define GPIO_FPGA_DIN           12
+#define GPIO_FPGA_PGM           13
+#define GPIO_FPGA_DONE          14
+#define GPIO_FPGA_INIT          15
+
+#define LEDS_CS                 2
+#define LEDS_PHYS               0x100C0000
+#define MLEDS_CS                3
+#define MLEDS_PHYS              0x100A0000
+#define UART_CS                 4
+#define UART_PHYS               0x100D0000
+#define ARAVALI_CS              5
+#define ARAVALI_PHYS            0x11000000
+#define IDE_CS                  6
+#define IDE_PHYS                0x100B0000
+#define ARAVALI2_CS             7
+#define ARAVALI2_PHYS           0x100E0000
+
+#if defined(CONFIG_SIBYTE_CARMEL)
+#define K_GPIO_GB_IDE   9
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+
+#endif /* __ASM_SIBYTE_CARMEL_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
new file mode 100644
index 000000000000..d62da4e2dd36
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _ASM_SIBYTE_SB1250_H
+#define _ASM_SIBYTE_SB1250_H
+
+/*
+ * yymmddpp: year, month, day, patch.
+ * should sync with Makefile EXTRAVERSION
+ */
+#define SIBYTE_RELEASE 0x02111403
+
+#define SB1250_NR_IRQS 64
+
+#define SB1250_DUART_MINOR_BASE         64
+
+#ifndef __ASSEMBLY__
+
+#include <asm/addrspace.h>
+
+/* For revision/pass information */
+#include <asm/sibyte/sb1250_scd.h>
+extern unsigned int sb1_pass;
+extern unsigned int soc_pass;
+extern unsigned int soc_type;
+extern unsigned int periph_rev;
+extern unsigned int zbbus_mhz;
+
+extern void sb1250_time_init(void);
+extern unsigned long sb1250_gettimeoffset(void);
+extern void sb1250_mask_irq(int cpu, int irq);
+extern void sb1250_unmask_irq(int cpu, int irq);
+extern void sb1250_smp_finish(void);
+extern void prom_printf(char *fmt, ...);
+
+#define AT_spin \
+        __asm__ __volatile__ (          \
+                ".set noat\n"           \
+                "li $at, 0\n"           \
+                "1: beqz $at, 1b\n"     \
+                ".set at\n"             \
+                )
+
+#endif
+
+#define IOADDR(a) (IO_BASE + (a))
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
new file mode 100644
index 000000000000..96088fb074a4
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -0,0 +1,242 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  Global constants and macros              File: sb1250_defs.h     
+    *  
+    *  This file contains macros and definitions used by the other
+    *  include files.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _SB1250_DEFS_H
+#define _SB1250_DEFS_H
+
+/*
+ * These headers require ANSI C89 string concatenation, and GCC or other
+ * 'long long' (64-bit integer) support.
+ */
+#if !defined(__STDC__) && !defined(_MSC_VER)
+#error SiByte headers require ANSI C89 support
+#endif
+
+
+/*  *********************************************************************
+    *  Macros for feature tests, used to enable include file features
+    *  for chip features only present in certain chip revisions.
+    *
+    *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
+    *  which is to be exposed by the headers.  If undefined, it defaults to
+    *  "all features."
+    *
+    *  Use like:
+    *
+    *    #define SIBYTE_HDR_FEATURES    SIBYTE_HDR_FMASK_112x_PASS1
+    *
+    *           Generate defines only for that revision of chip.
+    *
+    *    #if SIBYTE_HDR_FEATURE(chip,pass)
+    *
+    *           True if header features for that revision or later of
+    *           that particular chip type are enabled in SIBYTE_HDR_FEATURES.
+    *           (Use this to bracket #defines for features present in a given
+    *           revision and later.)
+    *
+    *           Note that there is no implied ordering between chip types.
+    *
+    *           Note also that 'chip' and 'pass' must textually exactly
+    *           match the defines below.  So, for example,
+    *           SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
+    *           SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
+    *
+    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but true for the named revision
+    *           and earlier revisions of the named chip type.
+    *
+    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but only true for the named
+    *           revision of the named chip type.  (Note that this CANNOT
+    *           be used to verify that you're compiling only for that
+    *           particular chip/revision.  It will be true any time this
+    *           chip/revision is included in SIBYTE_HDR_FEATURES.)
+    *
+    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
+    *
+    *           True if header features for (any revision of) that chip type
+    *           are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
+    *           #defines for features specific to a given chip type.)
+    *
+    *  Mask values currently include room for additional revisions of each
+    *  chip type, but can be renumbered at will.  Note that they MUST fit
+    *  into 31 bits and may not include C type constructs, for safe use in
+    *  CPP conditionals.  Bit positions within chip types DO indicate
+    *  ordering, so be careful when adding support for new minor revs.
+    ********************************************************************* */
+
+#define SIBYTE_HDR_FMASK_1250_ALL               0x00000ff
+#define SIBYTE_HDR_FMASK_1250_PASS1             0x0000001
+#define SIBYTE_HDR_FMASK_1250_PASS2             0x0000002
+#define SIBYTE_HDR_FMASK_1250_PASS3             0x0000004
+
+#define SIBYTE_HDR_FMASK_112x_ALL               0x0000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1             0x0000100
+
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */ 
+#define SIBYTE_HDR_FMASK(chip, pass)                                    \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
+#define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
+
+#define SIBYTE_HDR_FMASK_ALL                                            \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
+
+#ifndef SIBYTE_HDR_FEATURES
+#define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
+#endif
+
+
+/* Bit mask for revisions of chip exclusively before the named revision.  */
+#define SIBYTE_HDR_FMASK_BEFORE(chip, pass)                             \
+    ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+/* Bit mask for revisions of chip exclusively after the named revision.  */
+#define SIBYTE_HDR_FMASK_AFTER(chip, pass)                              \
+    (~(SIBYTE_HDR_FMASK(chip, pass)                                     \
+     | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+
+/* True if header features enabled for (any revision of) that chip type.  */
+#define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
+    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for that rev or later, inclusive.  */
+#define SIBYTE_HDR_FEATURE(chip, pass)                                  \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+          | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for exactly that rev.  */
+#define SIBYTE_HDR_FEATURE_EXACT(chip, pass)                            \
+    (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for that rev or before, inclusive.  */
+#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)                            \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+         | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+
+/*  *********************************************************************
+    *  Naming schemes for constants in these files:
+    *  
+    *  M_xxx           MASK constant (identifies bits in a register). 
+    *                  For multi-bit fields, all bits in the field will
+    *                  be set.
+    *
+    *  K_xxx           "Code" constant (value for data in a multi-bit
+    *                  field).  The value is right justified.
+    *
+    *  V_xxx           "Value" constant.  This is the same as the 
+    *                  corresponding "K_xxx" constant, except it is
+    *                  shifted to the correct position in the register.
+    *
+    *  S_xxx           SHIFT constant.  This is the number of bits that
+    *                  a field value (code) needs to be shifted 
+    *                  (towards the left) to put the value in the right
+    *                  position for the register.
+    *
+    *  A_xxx           ADDRESS constant.  This will be a physical 
+    *                  address.  Use the PHYS_TO_K1 macro to generate
+    *                  a K1SEG address.
+    *
+    *  R_xxx           RELATIVE offset constant.  This is an offset from
+    *                  an A_xxx constant (usually the first register in
+    *                  a group).
+    *  
+    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
+    *                  from a register, masks it, and shifts it to
+    *                  the bottom of the register (retrieving a K_xxx
+    *                  value, for example).
+    *
+    *  V_xxx(X)        VALUE.  This macro computes the value of a
+    *                  K_xxx constant shifted to the correct position
+    *                  in the register.
+    ********************************************************************* */
+
+
+
+
+/*
+ * Cast to 64-bit number.  Presumably the syntax is different in 
+ * assembly language.
+ *
+ * Note: you'll need to define uint32_t and uint64_t in your headers.
+ */
+
+#if !defined(__ASSEMBLER__)
+#define _SB_MAKE64(x) ((uint64_t)(x))
+#define _SB_MAKE32(x) ((uint32_t)(x))
+#else
+#define _SB_MAKE64(x) (x)
+#define _SB_MAKE32(x) (x)
+#endif
+
+
+/*
+ * Make a mask for 1 bit at position 'n'
+ */
+
+#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
+
+/*
+ * Make a mask for 'v' bits at position 'n'
+ */
+
+#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
+
+/*
+ * Make a value at 'v' at bit position 'n'
+ */
+
+#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
+#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
+
+#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
+#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
+
+/*
+ * Macros to read/write on-chip registers
+ * XXX should we do the PHYS_TO_K1 here?
+ */
+
+
+#if defined(__mips64) && !defined(__ASSEMBLER__)
+#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
+#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
new file mode 100644
index 000000000000..f1b08d32338d
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -0,0 +1,594 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  DMA definitions                          File: sb1250_dma.h
+    *  
+    *  This module contains constants and macros useful for
+    *  programming the SB1250's DMA controllers, both the data mover
+    *  and the Ethernet DMA.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_DMA_H
+#define _SB1250_DMA_H
+
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  DMA Registers
+    ********************************************************************* */
+
+/* 
+ * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
+ * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
+ * Registers: DMA_CONFIG0_SER_x_RX
+ * Registers: DMA_CONFIG0_SER_x_TX
+ */
+
+
+#define M_DMA_DROP                  _SB_MAKEMASK1(0)
+
+#define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
+#define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
+
+#define S_DMA_DESC_TYPE             _SB_MAKE64(1)
+#define M_DMA_DESC_TYPE             _SB_MAKE64(2,S_DMA_DESC_TYPE)
+#define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
+#define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
+
+#define K_DMA_DESC_TYPE_RING_AL         0
+#define K_DMA_DESC_TYPE_CHAIN_AL        1
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_DMA_DESC_TYPE_RING_UAL_WI     2
+#define K_DMA_DESC_TYPE_RING_UAL_RMW    3
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
+#define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
+#define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
+#define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
+#define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
+
+#define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
+#define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
+#define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
+#define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
+
+#define S_DMA_RINGSZ                _SB_MAKE64(16)
+#define M_DMA_RINGSZ                _SB_MAKEMASK(16,S_DMA_RINGSZ)
+#define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x,S_DMA_RINGSZ)
+#define G_DMA_RINGSZ(x)             _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
+
+#define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
+#define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
+#define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
+#define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
+
+#define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
+#define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
+#define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
+#define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
+
+/*
+ * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
+ * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
+ * Registers: DMA_CONFIG1_SER_x_RX
+ * Registers: DMA_CONFIG1_SER_x_TX
+ */
+
+#define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
+#define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
+#define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
+#define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
+#define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
+#define M_DMA_L2CA                  _SB_MAKEMASK1(5)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
+#define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
+#define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_DMA_MBZ1                  _SB_MAKEMASK(6,15)
+
+#define S_DMA_HDR_SIZE              _SB_MAKE64(21)
+#define M_DMA_HDR_SIZE              _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
+#define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
+#define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
+
+#define M_DMA_MBZ2                  _SB_MAKEMASK(5,32)
+
+#define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
+#define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
+#define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
+#define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
+
+#define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
+#define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
+#define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
+#define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
+
+/*
+ * Ethernet and Serial DMA Descriptor base address (Table 7-6)
+ */
+
+#define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4,0)
+
+
+/*
+ * ASIC Mode Base Address (Table 7-7)
+ */
+
+#define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20,0)
+
+/*
+ * DMA Descriptor Count Registers (Table 7-8)
+ */
+ 
+/* No bitfields */
+
+
+/* 
+ * Current Descriptor Address Register (Table 7-11)
+ */
+
+#define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
+#define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
+#define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
+#define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * Receive Packet Drop Registers
+ */
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_DMA_OODLOST_RX           _SB_MAKE64(0)
+#define M_DMA_OODLOST_RX           _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
+#define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
+
+#define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
+#define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
+#define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*  *********************************************************************
+    *  DMA Descriptors
+    ********************************************************************* */
+
+/*
+ * Descriptor doubleword "A"  (Table 7-12)
+ */
+
+#define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
+#define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
+#define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)
+#define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
+
+#define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
+#define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
+#define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
+#define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
+#define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
+#define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
+#define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
+
+#define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
+#define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
+#define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
+#define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
+
+/*
+ * Descriptor doubleword "B"  (Table 7-13)
+ */
+
+
+#define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
+#define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
+#define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
+#define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
+#define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
+#define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
+#define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
+
+#define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
+#define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
+#define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
+
+#define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
+#define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
+#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
+#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
+#define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
+#define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
+#define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
+
+/*
+ * from pass2 some bits in dscr_b are also used for rx status
+ */
+#define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
+#define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)
+#define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
+#define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
+
+/* 
+ * Ethernet Descriptor Status Bits (Table 7-15)
+ */
+
+#define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
+#define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 
+/* Note: BADTCPCS is actually in DSCR_B options field */
+#define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
+#define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define S_DMA_ETHRX_RXCH            53
+#define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
+#define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
+#define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
+
+#define S_DMA_ETHRX_PKTTYPE         55
+#define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
+#define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
+#define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
+
+#define K_DMA_ETHRX_PKTTYPE_IPV4    0
+#define K_DMA_ETHRX_PKTTYPE_ARPV4   1
+#define K_DMA_ETHRX_PKTTYPE_802     2
+#define K_DMA_ETHRX_PKTTYPE_OTHER   3
+#define K_DMA_ETHRX_PKTTYPE_USER0   4
+#define K_DMA_ETHRX_PKTTYPE_USER1   5
+#define K_DMA_ETHRX_PKTTYPE_USER2   6
+#define K_DMA_ETHRX_PKTTYPE_USER3   7
+
+#define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
+#define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
+#define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
+#define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
+#define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
+#define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Ethernet Transmit Status Bits (Table 7-16)
+ */
+
+#define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
+
+/* 
+ * Ethernet Transmit Options (Table 7-17)
+ */
+
+#define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
+#define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
+#define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
+#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
+#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
+#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
+#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
+#define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
+#define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
+#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
+#define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
+
+/*
+ * Serial Receive Options (Table 7-18)
+ */
+#define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
+#define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
+#define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
+#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
+#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
+#define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
+#define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
+#define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Status Bits (Table 7-20)
+ */
+
+#define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Options (Table 7-21)
+ */
+
+#define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
+#define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
+#define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
+#define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
+
+
+/*  *********************************************************************
+    *  Data Mover Registers
+    ********************************************************************* */
+
+/* 
+ * Data Mover Descriptor Base Address Register (Table 7-22)
+ * Register: DM_DSCR_BASE_0
+ * Register: DM_DSCR_BASE_1
+ * Register: DM_DSCR_BASE_2
+ * Register: DM_DSCR_BASE_3
+ */
+
+#define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4,0)
+
+/*  Note: Just mask the base address and then OR it in. */
+#define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
+#define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
+
+#define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
+#define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
+#define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
+#define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
+
+#define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
+#define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
+#define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
+#define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
+
+#define K_DM_DSCR_BASE_PRIORITY_1   0
+#define K_DM_DSCR_BASE_PRIORITY_2   1
+#define K_DM_DSCR_BASE_PRIORITY_4   2
+#define K_DM_DSCR_BASE_PRIORITY_8   3
+#define K_DM_DSCR_BASE_PRIORITY_16  4
+
+#define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
+#define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
+#define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
+#define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
+#define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
+#define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
+
+/* 
+ * Data Mover Descriptor Count Register (Table 7-25)
+ */
+
+/* no bitfields */
+
+/*
+ * Data Mover Current Descriptor Address (Table 7-24)
+ * Register: DM_CUR_DSCR_ADDR_0
+ * Register: DM_CUR_DSCR_ADDR_1
+ * Register: DM_CUR_DSCR_ADDR_2
+ * Register: DM_CUR_DSCR_ADDR_3
+ */
+
+#define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
+#define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
+
+#define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
+#define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
+#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
+#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
+                                     M_DM_CUR_DSCR_DSCR_COUNT)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Data Mover Channel Partial Result Registers
+ * Register: DM_PARTIAL_0
+ * Register: DM_PARTIAL_1
+ * Register: DM_PARTIAL_2
+ * Register: DM_PARTIAL_3
+ */
+#define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
+#define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL)
+#define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL)
+#define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\
+                                       M_DM_PARTIAL_CRC_PARTIAL)
+
+#define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
+#define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL)
+#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL)
+#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\
+                                       M_DM_PARTIAL_TCPCS_PARTIAL)
+
+#define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Data Mover CRC Definition Registers
+ * Register: CRC_DEF_0
+ * Register: CRC_DEF_1
+ */
+#define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
+#define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT)
+#define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT)
+#define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\
+                                       M_CRC_DEF_CRC_INIT)
+
+#define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
+#define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY)
+#define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
+#define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
+                                       M_CRC_DEF_CRC_POLY)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Data Mover CRC/Checksum Definition Registers
+ * Register: CTCP_DEF_0
+ * Register: CTCP_DEF_1
+ */
+#define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
+#define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR)
+#define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR)
+#define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\
+                                       M_CTCP_DEF_CRC_TXOR)
+
+#define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
+#define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT)
+#define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT)
+#define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\
+                                       M_CTCP_DEF_TCPCS_INIT)
+
+#define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
+#define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH)
+#define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH)
+#define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\
+                                       M_CTCP_DEF_CRC_WIDTH)
+
+#define K_CTCP_DEF_CRC_WIDTH_4        0
+#define K_CTCP_DEF_CRC_WIDTH_2        1
+#define K_CTCP_DEF_CRC_WIDTH_1        2
+
+#define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+/*
+ * Data Mover Descriptor Doubleword "A"  (Table 7-26)
+ */
+
+#define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
+
+#define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
+#define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
+#define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
+#endif /* up to 1250 PASS1 */
+
+#define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
+#define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
+#define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
+
+#define K_DM_DSCRA_DIR_DEST_INCR    0
+#define K_DM_DSCRA_DIR_DEST_DECR    1
+#define K_DM_DSCRA_DIR_DEST_CONST   2
+
+#define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
+
+#define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
+#define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
+#define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
+
+#define K_DM_DSCRA_DIR_SRC_INCR     0
+#define K_DM_DSCRA_DIR_SRC_DECR     1
+#define K_DM_DSCRA_DIR_SRC_CONST    2
+
+#define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
+
+
+#define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
+#define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
+#define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
+#define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
+#define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
+#define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
+#define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
+#define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
+#define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
+#define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
+#define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
+#define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3,61)
+
+/*
+ * Data Mover Descriptor Doubleword "B"  (Table 7-25)
+ */
+
+#define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
+
+#define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
+#define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
+#define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
+#define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
new file mode 100644
index 000000000000..0d9dfac3d7db
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -0,0 +1,276 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  Generic Bus Constants                     File: sb1250_genbus.h
+    *  
+    *  This module contains constants and macros useful for 
+    *  manipulating the SB1250's Generic Bus interface
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_GENBUS_H
+#define _SB1250_GENBUS_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Generic Bus Region Configuration Registers (Table 11-4)
+ */
+
+#define S_IO_RDY_ACTIVE         0
+#define M_IO_RDY_ACTIVE         _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
+
+#define S_IO_ENA_RDY            1
+#define M_IO_ENA_RDY            _SB_MAKEMASK1(S_IO_ENA_RDY)
+
+#define S_IO_WIDTH_SEL          2
+#define M_IO_WIDTH_SEL          _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
+#define K_IO_WIDTH_SEL_1        0
+#define K_IO_WIDTH_SEL_2        1
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_IO_WIDTH_SEL_1L       2
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define K_IO_WIDTH_SEL_4        3
+#define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
+#define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
+
+#define S_IO_PARITY_ENA         4
+#define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_IO_BURST_EN           5
+#define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define S_IO_PARITY_ODD         6
+#define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
+#define S_IO_NONMUX             7
+#define M_IO_NONMUX             _SB_MAKEMASK1(S_IO_NONMUX)
+
+#define S_IO_TIMEOUT            8
+#define M_IO_TIMEOUT            _SB_MAKEMASK(8,S_IO_TIMEOUT)
+#define V_IO_TIMEOUT(x)         _SB_MAKEVALUE(x,S_IO_TIMEOUT)
+#define G_IO_TIMEOUT(x)         _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
+
+/*
+ * Generic Bus Region Size register (Table 11-5)
+ */
+
+#define S_IO_MULT_SIZE          0
+#define M_IO_MULT_SIZE          _SB_MAKEMASK(12,S_IO_MULT_SIZE)
+#define V_IO_MULT_SIZE(x)       _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
+#define G_IO_MULT_SIZE(x)       _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
+
+#define S_IO_REGSIZE            16       /* # bits to shift size for this reg */
+
+/*
+ * Generic Bus Region Address (Table 11-6)
+ */
+
+#define S_IO_START_ADDR         0
+#define M_IO_START_ADDR         _SB_MAKEMASK(14,S_IO_START_ADDR)
+#define V_IO_START_ADDR(x)      _SB_MAKEVALUE(x,S_IO_START_ADDR)
+#define G_IO_START_ADDR(x)      _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
+
+#define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
+
+/*
+ * Generic Bus Region 0 Timing Registers (Table 11-7)
+ */
+
+#define S_IO_ALE_WIDTH          0
+#define M_IO_ALE_WIDTH          _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
+#define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
+#define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_IO_ALE_TO_CS          4
+#define M_IO_ALE_TO_CS          _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
+#define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
+#define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_IO_BURST_WIDTH           _SB_MAKE64(6)
+#define M_IO_BURST_WIDTH           _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
+#define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
+#define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_IO_CS_WIDTH           8
+#define M_IO_CS_WIDTH           _SB_MAKEMASK(5,S_IO_CS_WIDTH)
+#define V_IO_CS_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
+#define G_IO_CS_WIDTH(x)        _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
+
+#define S_IO_RDY_SMPLE          13
+#define M_IO_RDY_SMPLE          _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
+#define V_IO_RDY_SMPLE(x)       _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
+#define G_IO_RDY_SMPLE(x)       _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
+
+
+/*
+ * Generic Bus Timing 1 Registers (Table 11-8)
+ */
+
+#define S_IO_ALE_TO_WRITE       0
+#define M_IO_ALE_TO_WRITE       _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
+#define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
+#define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_IO_WRITE_WIDTH        4
+#define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
+#define V_IO_WRITE_WIDTH(x)     _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
+#define G_IO_WRITE_WIDTH(x)     _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
+
+#define S_IO_IDLE_CYCLE         8
+#define M_IO_IDLE_CYCLE         _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
+#define V_IO_IDLE_CYCLE(x)      _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
+#define G_IO_IDLE_CYCLE(x)      _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
+
+#define S_IO_OE_TO_CS           12
+#define M_IO_OE_TO_CS           _SB_MAKEMASK(2,S_IO_OE_TO_CS)
+#define V_IO_OE_TO_CS(x)        _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
+#define G_IO_OE_TO_CS(x)        _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
+
+#define S_IO_CS_TO_OE           14
+#define M_IO_CS_TO_OE           _SB_MAKEMASK(2,S_IO_CS_TO_OE)
+#define V_IO_CS_TO_OE(x)        _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
+#define G_IO_CS_TO_OE(x)        _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
+
+/*
+ * Generic Bus Interrupt Status Register (Table 11-9)
+ */
+
+#define M_IO_CS_ERR_INT         _SB_MAKEMASK(0,8)
+#define M_IO_CS0_ERR_INT        _SB_MAKEMASK1(0)
+#define M_IO_CS1_ERR_INT        _SB_MAKEMASK1(1)
+#define M_IO_CS2_ERR_INT        _SB_MAKEMASK1(2)
+#define M_IO_CS3_ERR_INT        _SB_MAKEMASK1(3)
+#define M_IO_CS4_ERR_INT        _SB_MAKEMASK1(4)
+#define M_IO_CS5_ERR_INT        _SB_MAKEMASK1(5)
+#define M_IO_CS6_ERR_INT        _SB_MAKEMASK1(6)
+#define M_IO_CS7_ERR_INT        _SB_MAKEMASK1(7)
+
+#define M_IO_RD_PAR_INT         _SB_MAKEMASK1(9)
+#define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
+#define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
+#define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_IO_COH_ERR            _SB_MAKEMASK1(14)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * PCMCIA configuration register (Table 12-6)
+ */
+
+#define M_PCMCIA_CFG_ATTRMEM    _SB_MAKEMASK1(0)
+#define M_PCMCIA_CFG_3VEN       _SB_MAKEMASK1(1)
+#define M_PCMCIA_CFG_5VEN       _SB_MAKEMASK1(2)
+#define M_PCMCIA_CFG_VPPEN      _SB_MAKEMASK1(3)
+#define M_PCMCIA_CFG_RESET      _SB_MAKEMASK1(4)
+#define M_PCMCIA_CFG_APWRONEN   _SB_MAKEMASK1(5)
+#define M_PCMCIA_CFG_CDMASK     _SB_MAKEMASK1(6)
+#define M_PCMCIA_CFG_WPMASK     _SB_MAKEMASK1(7)
+#define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
+#define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
+
+/*
+ * PCMCIA status register (Table 12-7)
+ */
+
+#define M_PCMCIA_STATUS_CD1     _SB_MAKEMASK1(0)
+#define M_PCMCIA_STATUS_CD2     _SB_MAKEMASK1(1)
+#define M_PCMCIA_STATUS_VS1     _SB_MAKEMASK1(2)
+#define M_PCMCIA_STATUS_VS2     _SB_MAKEMASK1(3)
+#define M_PCMCIA_STATUS_WP      _SB_MAKEMASK1(4)
+#define M_PCMCIA_STATUS_RDY     _SB_MAKEMASK1(5)
+#define M_PCMCIA_STATUS_3VEN    _SB_MAKEMASK1(6)
+#define M_PCMCIA_STATUS_5VEN    _SB_MAKEMASK1(7)
+#define M_PCMCIA_STATUS_CDCHG   _SB_MAKEMASK1(8)
+#define M_PCMCIA_STATUS_WPCHG   _SB_MAKEMASK1(9)
+#define M_PCMCIA_STATUS_RDYCHG  _SB_MAKEMASK1(10)
+
+/*
+ * GPIO Interrupt Type Register (table 13-3)
+ */
+
+#define K_GPIO_INTR_DISABLE     0
+#define K_GPIO_INTR_EDGE        1
+#define K_GPIO_INTR_LEVEL       2
+#define K_GPIO_INTR_SPLIT       3
+
+#define S_GPIO_INTR_TYPEX(n)    (((n)/2)*2)
+#define M_GPIO_INTR_TYPEX(n)    _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
+#define V_GPIO_INTR_TYPEX(n,x)  _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
+#define G_GPIO_INTR_TYPEX(n,x)  _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
+
+#define S_GPIO_INTR_TYPE0       0
+#define M_GPIO_INTR_TYPE0       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
+#define V_GPIO_INTR_TYPE0(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
+#define G_GPIO_INTR_TYPE0(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
+
+#define S_GPIO_INTR_TYPE2       2
+#define M_GPIO_INTR_TYPE2       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
+#define V_GPIO_INTR_TYPE2(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
+#define G_GPIO_INTR_TYPE2(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
+
+#define S_GPIO_INTR_TYPE4       4
+#define M_GPIO_INTR_TYPE4       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
+#define V_GPIO_INTR_TYPE4(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
+#define G_GPIO_INTR_TYPE4(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
+
+#define S_GPIO_INTR_TYPE6       6
+#define M_GPIO_INTR_TYPE6       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
+#define V_GPIO_INTR_TYPE6(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
+#define G_GPIO_INTR_TYPE6(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
+
+#define S_GPIO_INTR_TYPE8       8
+#define M_GPIO_INTR_TYPE8       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
+#define V_GPIO_INTR_TYPE8(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
+#define G_GPIO_INTR_TYPE8(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
+
+#define S_GPIO_INTR_TYPE10      10
+#define M_GPIO_INTR_TYPE10      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
+#define V_GPIO_INTR_TYPE10(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
+#define G_GPIO_INTR_TYPE10(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
+
+#define S_GPIO_INTR_TYPE12      12
+#define M_GPIO_INTR_TYPE12      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
+#define V_GPIO_INTR_TYPE12(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
+#define G_GPIO_INTR_TYPE12(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
+
+#define S_GPIO_INTR_TYPE14      14
+#define M_GPIO_INTR_TYPE14      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
+#define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
+#define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
new file mode 100644
index 000000000000..c3f74df211f4
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -0,0 +1,247 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  Interrupt Mapper definitions             File: sb1250_int.h
+    *  
+    *  This module contains constants for manipulating the SB1250's
+    *  interrupt mapper and definitions for the interrupt sources.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_INT_H
+#define _SB1250_INT_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * Interrupt sources (Table 4-8, UM 0.2)
+ * 
+ * First, the interrupt numbers.
+ */
+
+#define K_INT_WATCHDOG_TIMER_0      0
+#define K_INT_WATCHDOG_TIMER_1      1
+#define K_INT_TIMER_0               2
+#define K_INT_TIMER_1               3
+#define K_INT_TIMER_2               4
+#define K_INT_TIMER_3               5
+#define K_INT_SMB_0                 6
+#define K_INT_SMB_1                 7
+#define K_INT_UART_0                8
+#define K_INT_UART_1                9
+#define K_INT_SER_0                 10
+#define K_INT_SER_1                 11
+#define K_INT_PCMCIA                12
+#define K_INT_ADDR_TRAP             13
+#define K_INT_PERF_CNT              14
+#define K_INT_TRACE_FREEZE          15
+#define K_INT_BAD_ECC               16
+#define K_INT_COR_ECC               17
+#define K_INT_IO_BUS                18
+#define K_INT_MAC_0                 19
+#define K_INT_MAC_1                 20
+#define K_INT_MAC_2                 21
+#define K_INT_DM_CH_0               22
+#define K_INT_DM_CH_1               23
+#define K_INT_DM_CH_2               24
+#define K_INT_DM_CH_3               25
+#define K_INT_MBOX_0                26
+#define K_INT_MBOX_1                27
+#define K_INT_MBOX_2                28
+#define K_INT_MBOX_3                29
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_CYCLE_CP0_INT         30
+#define K_INT_CYCLE_CP1_INT         31
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define K_INT_GPIO_0                32
+#define K_INT_GPIO_1                33
+#define K_INT_GPIO_2                34
+#define K_INT_GPIO_3                35
+#define K_INT_GPIO_4                36
+#define K_INT_GPIO_5                37
+#define K_INT_GPIO_6                38
+#define K_INT_GPIO_7                39
+#define K_INT_GPIO_8                40
+#define K_INT_GPIO_9                41
+#define K_INT_GPIO_10               42
+#define K_INT_GPIO_11               43
+#define K_INT_GPIO_12               44
+#define K_INT_GPIO_13               45
+#define K_INT_GPIO_14               46
+#define K_INT_GPIO_15               47
+#define K_INT_LDT_FATAL             48
+#define K_INT_LDT_NONFATAL          49
+#define K_INT_LDT_SMI               50
+#define K_INT_LDT_NMI               51
+#define K_INT_LDT_INIT              52
+#define K_INT_LDT_STARTUP           53
+#define K_INT_LDT_EXT               54
+#define K_INT_PCI_ERROR             55
+#define K_INT_PCI_INTA              56
+#define K_INT_PCI_INTB              57
+#define K_INT_PCI_INTC              58
+#define K_INT_PCI_INTD              59
+#define K_INT_SPARE_2               60
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_MAC_0_CH1             61
+#define K_INT_MAC_1_CH1             62
+#define K_INT_MAC_2_CH1             63
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
+#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
+#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
+#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
+#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
+#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
+#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
+#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
+#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
+#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
+#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
+#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
+#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
+#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
+#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
+#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
+#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
+#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
+#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
+#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
+#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
+#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
+#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
+#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
+#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
+#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
+#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
+#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
+#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
+#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_CYCLE_CP0_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
+#define M_INT_CYCLE_CP1_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
+#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
+#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
+#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
+#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
+#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
+#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
+#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
+#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
+#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
+#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
+#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
+#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
+#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
+#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
+#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
+#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
+#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
+#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
+#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
+#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
+#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
+#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
+#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
+#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
+#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
+#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
+#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
+#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_MAC_0_CH1             _SB_MAKEMASK1(K_INT_MAC_0_CH1)
+#define M_INT_MAC_1_CH1             _SB_MAKEMASK1(K_INT_MAC_1_CH1)
+#define M_INT_MAC_2_CH1             _SB_MAKEMASK1(K_INT_MAC_2_CH1)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Interrupt mappings
+ */
+
+#define K_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_INT_MAP_I1    1
+#define K_INT_MAP_I2    2
+#define K_INT_MAP_I3    3
+#define K_INT_MAP_I4    4
+#define K_INT_MAP_I5    5
+#define K_INT_MAP_NMI   6               /* nonmaskable */
+#define K_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * LDT Interrupt Set Register (table 4-5)
+ */
+
+#define S_INT_LDT_INTMSG              0
+#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
+#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
+#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
+
+#define K_INT_LDT_INTMSG_FIXED        0
+#define K_INT_LDT_INTMSG_ARBITRATED   1
+#define K_INT_LDT_INTMSG_SMI          2
+#define K_INT_LDT_INTMSG_NMI          3
+#define K_INT_LDT_INTMSG_INIT         4
+#define K_INT_LDT_INTMSG_STARTUP      5
+#define K_INT_LDT_INTMSG_EXTINT       6
+#define K_INT_LDT_INTMSG_RESERVED     7
+
+#define M_INT_LDT_EDGETRIGGER         0
+#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
+
+#define M_INT_LDT_PHYSICALDEST        0
+#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
+
+#define S_INT_LDT_INTDEST             5
+#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
+#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
+#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
+
+#define S_INT_LDT_VECTOR              13
+#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
+#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
+#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
+
+/*
+ * Vector format (Table 4-6)
+ */
+
+#define M_LDTVECT_RAISEINT              0x00
+#define M_LDTVECT_RAISEMBOX             0x40
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
new file mode 100644
index 000000000000..799db828d963
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -0,0 +1,128 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  L2 Cache constants and macros            File: sb1250_l2c.h
+    *  
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_L2C_H
+#define _SB1250_L2C_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Level 2 Cache Tag register (Table 5-3)
+ */
+
+#define S_L2C_TAG_MBZ               0
+#define M_L2C_TAG_MBZ               _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
+
+#define S_L2C_TAG_INDEX             5
+#define M_L2C_TAG_INDEX             _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
+#define V_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
+#define G_L2C_TAG_INDEX(x)          _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
+
+#define S_L2C_TAG_TAG               17
+#define M_L2C_TAG_TAG               _SB_MAKEMASK(23,S_L2C_TAG_TAG)
+#define V_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
+#define G_L2C_TAG_TAG(x)            _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
+
+#define S_L2C_TAG_ECC               40
+#define M_L2C_TAG_ECC               _SB_MAKEMASK(6,S_L2C_TAG_ECC)
+#define V_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
+#define G_L2C_TAG_ECC(x)            _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
+
+#define S_L2C_TAG_WAY               46
+#define M_L2C_TAG_WAY               _SB_MAKEMASK(2,S_L2C_TAG_WAY)
+#define V_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
+#define G_L2C_TAG_WAY(x)            _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
+
+#define M_L2C_TAG_DIRTY             _SB_MAKEMASK1(48)
+#define M_L2C_TAG_VALID             _SB_MAKEMASK1(49)
+
+/*
+ * Format of level 2 cache management address (table 5-2)
+ */
+
+#define S_L2C_MGMT_INDEX            5
+#define M_L2C_MGMT_INDEX            _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
+#define V_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
+#define G_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
+
+#define S_L2C_MGMT_QUADRANT         15
+#define M_L2C_MGMT_QUADRANT         _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT)
+#define V_L2C_MGMT_QUADRANT(x)      _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT)
+#define G_L2C_MGMT_QUADRANT(x)      _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT)
+
+#define S_L2C_MGMT_HALF             16
+#define M_L2C_MGMT_HALF             _SB_MAKEMASK(1,S_L2C_MGMT_HALF)
+
+#define S_L2C_MGMT_WAY              17
+#define M_L2C_MGMT_WAY              _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
+#define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
+#define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
+
+#define S_L2C_MGMT_TAG              21
+#define M_L2C_MGMT_TAG              _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
+#define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
+#define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
+
+#define M_L2C_MGMT_DIRTY            _SB_MAKEMASK1(19)
+#define M_L2C_MGMT_VALID            _SB_MAKEMASK1(20)
+
+#define A_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define L2C_ENTRIES_PER_WAY       4096
+#define L2C_NUM_WAYS              4
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * L2 Read Misc. register (A_L2_READ_MISC)
+ */
+#define S_L2C_MISC_NO_WAY               10
+#define M_L2C_MISC_NO_WAY               _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY)
+#define V_L2C_MISC_NO_WAY(x)            _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY)
+#define G_L2C_MISC_NO_WAY(x)            _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY)
+
+#define M_L2C_MISC_ECC_CLEANUP_DIS      _SB_MAKEMASK1(9)
+#define M_L2C_MISC_MC_PRIO_LOW          _SB_MAKEMASK1(8)
+#define M_L2C_MISC_SOFT_DISABLE_T       _SB_MAKEMASK1(7)
+#define M_L2C_MISC_SOFT_DISABLE_B       _SB_MAKEMASK1(6)
+#define M_L2C_MISC_SOFT_DISABLE_R       _SB_MAKEMASK1(5)
+#define M_L2C_MISC_SOFT_DISABLE_L       _SB_MAKEMASK1(4)
+#define M_L2C_MISC_SCACHE_DISABLE_T     _SB_MAKEMASK1(3)
+#define M_L2C_MISC_SCACHE_DISABLE_B     _SB_MAKEMASK1(2)
+#define M_L2C_MISC_SCACHE_DISABLE_R     _SB_MAKEMASK1(1)
+#define M_L2C_MISC_SCACHE_DISABLE_L     _SB_MAKEMASK1(0)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
new file mode 100644
index 000000000000..d8753885df17
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -0,0 +1,425 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  LDT constants                            File: sb1250_ldt.h
+    *  
+    *  This module contains constants and macros to describe 
+    *  the LDT interface on the SB1250.  
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_LDT_H
+#define _SB1250_LDT_H
+
+#include "sb1250_defs.h"
+
+#define K_LDT_VENDOR_SIBYTE     0x166D
+#define K_LDT_DEVICE_SB1250     0x0002
+
+/*
+ * LDT Interface Type 1 (bridge) configuration header
+ */
+
+#define R_LDT_TYPE1_DEVICEID    0x0000
+#define R_LDT_TYPE1_CMDSTATUS   0x0004
+#define R_LDT_TYPE1_CLASSREV    0x0008
+#define R_LDT_TYPE1_DEVHDR      0x000C
+#define R_LDT_TYPE1_BAR0        0x0010  /* not used */
+#define R_LDT_TYPE1_BAR1        0x0014  /* not used */
+
+#define R_LDT_TYPE1_BUSID       0x0018  /* bus ID register */
+#define R_LDT_TYPE1_SECSTATUS   0x001C  /* secondary status / I/O base/limit */
+#define R_LDT_TYPE1_MEMLIMIT    0x0020
+#define R_LDT_TYPE1_PREFETCH    0x0024
+#define R_LDT_TYPE1_PREF_BASE   0x0028
+#define R_LDT_TYPE1_PREF_LIMIT  0x002C
+#define R_LDT_TYPE1_IOLIMIT     0x0030
+#define R_LDT_TYPE1_CAPPTR      0x0034
+#define R_LDT_TYPE1_ROMADDR     0x0038
+#define R_LDT_TYPE1_BRCTL       0x003C
+#define R_LDT_TYPE1_CMD         0x0040
+#define R_LDT_TYPE1_LINKCTRL    0x0044
+#define R_LDT_TYPE1_LINKFREQ    0x0048
+#define R_LDT_TYPE1_RESERVED1   0x004C
+#define R_LDT_TYPE1_SRICMD      0x0050
+#define R_LDT_TYPE1_SRITXNUM    0x0054
+#define R_LDT_TYPE1_SRIRXNUM    0x0058
+#define R_LDT_TYPE1_ERRSTATUS   0x0068
+#define R_LDT_TYPE1_SRICTRL     0x006C
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_LDT_TYPE1_ADDSTATUS   0x0070
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define R_LDT_TYPE1_TXBUFCNT    0x00C8
+#define R_LDT_TYPE1_EXPCRC      0x00DC
+#define R_LDT_TYPE1_RXCRC       0x00F0
+
+
+/*
+ * LDT Device ID register
+ */
+
+#define S_LDT_DEVICEID_VENDOR           0
+#define M_LDT_DEVICEID_VENDOR           _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
+#define V_LDT_DEVICEID_VENDOR(x)        _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
+#define G_LDT_DEVICEID_VENDOR(x)        _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
+
+#define S_LDT_DEVICEID_DEVICEID         16
+#define M_LDT_DEVICEID_DEVICEID         _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
+#define V_LDT_DEVICEID_DEVICEID(x)      _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
+#define G_LDT_DEVICEID_DEVICEID(x)      _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
+
+
+/*
+ * LDT Command Register (Table 8-13)
+ */
+
+#define M_LDT_CMD_IOSPACE_EN            _SB_MAKEMASK1_32(0)
+#define M_LDT_CMD_MEMSPACE_EN           _SB_MAKEMASK1_32(1)
+#define M_LDT_CMD_MASTER_EN             _SB_MAKEMASK1_32(2)
+#define M_LDT_CMD_SPECCYC_EN            _SB_MAKEMASK1_32(3)
+#define M_LDT_CMD_MEMWRINV_EN           _SB_MAKEMASK1_32(4)
+#define M_LDT_CMD_VGAPALSNP_EN          _SB_MAKEMASK1_32(5)
+#define M_LDT_CMD_PARERRRESP            _SB_MAKEMASK1_32(6)
+#define M_LDT_CMD_WAITCYCCTRL           _SB_MAKEMASK1_32(7)
+#define M_LDT_CMD_SERR_EN               _SB_MAKEMASK1_32(8)
+#define M_LDT_CMD_FASTB2B_EN            _SB_MAKEMASK1_32(9)
+
+/*
+ * LDT class and revision registers
+ */
+
+#define S_LDT_CLASSREV_REV              0
+#define M_LDT_CLASSREV_REV              _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
+#define V_LDT_CLASSREV_REV(x)           _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
+#define G_LDT_CLASSREV_REV(x)           _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
+
+#define S_LDT_CLASSREV_CLASS            8
+#define M_LDT_CLASSREV_CLASS            _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
+#define V_LDT_CLASSREV_CLASS(x)         _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
+#define G_LDT_CLASSREV_CLASS(x)         _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
+
+#define K_LDT_REV                       0x01
+#define K_LDT_CLASS                     0x060000
+
+/*
+ * Device Header (offset 0x0C)
+ */
+
+#define S_LDT_DEVHDR_CLINESZ            0
+#define M_LDT_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
+#define V_LDT_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
+#define G_LDT_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
+
+#define S_LDT_DEVHDR_LATTMR             8
+#define M_LDT_DEVHDR_LATTMR             _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
+#define V_LDT_DEVHDR_LATTMR(x)          _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
+#define G_LDT_DEVHDR_LATTMR(x)          _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
+
+#define S_LDT_DEVHDR_HDRTYPE            16
+#define M_LDT_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
+#define V_LDT_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
+#define G_LDT_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
+
+#define K_LDT_DEVHDR_HDRTYPE_TYPE1      1
+
+#define S_LDT_DEVHDR_BIST               24
+#define M_LDT_DEVHDR_BIST               _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
+#define V_LDT_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
+#define G_LDT_DEVHDR_BIST(x)            _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
+
+
+
+/*
+ * LDT Status Register (Table 8-14).  Note that these constants
+ * assume you've read the command and status register 
+ * together (32-bit read at offset 0x04)
+ *
+ * These bits also apply to the secondary status
+ * register (Table 8-15), offset 0x1C
+ */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_STATUS_VGAEN              _SB_MAKEMASK1_32(3)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_LDT_STATUS_CAPLIST            _SB_MAKEMASK1_32(20)
+#define M_LDT_STATUS_66MHZCAP           _SB_MAKEMASK1_32(21)
+#define M_LDT_STATUS_RESERVED2          _SB_MAKEMASK1_32(22)
+#define M_LDT_STATUS_FASTB2BCAP         _SB_MAKEMASK1_32(23)
+#define M_LDT_STATUS_MSTRDPARERR        _SB_MAKEMASK1_32(24)
+
+#define S_LDT_STATUS_DEVSELTIMING       25
+#define M_LDT_STATUS_DEVSELTIMING       _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
+#define V_LDT_STATUS_DEVSELTIMING(x)    _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
+#define G_LDT_STATUS_DEVSELTIMING(x)    _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
+
+#define M_LDT_STATUS_SIGDTGTABORT       _SB_MAKEMASK1_32(27)
+#define M_LDT_STATUS_RCVDTGTABORT       _SB_MAKEMASK1_32(28)
+#define M_LDT_STATUS_RCVDMSTRABORT      _SB_MAKEMASK1_32(29)
+#define M_LDT_STATUS_SIGDSERR           _SB_MAKEMASK1_32(30)
+#define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
+
+/*
+ * Bridge Control Register (Table 8-16).  Note that these 
+ * constants assume you've read the register as a 32-bit 
+ * read (offset 0x3C)
+ */
+
+#define M_LDT_BRCTL_PARERRRESP_EN       _SB_MAKEMASK1_32(16)
+#define M_LDT_BRCTL_SERR_EN             _SB_MAKEMASK1_32(17)
+#define M_LDT_BRCTL_ISA_EN              _SB_MAKEMASK1_32(18)
+#define M_LDT_BRCTL_VGA_EN              _SB_MAKEMASK1_32(19)
+#define M_LDT_BRCTL_MSTRABORTMODE       _SB_MAKEMASK1_32(21)
+#define M_LDT_BRCTL_SECBUSRESET         _SB_MAKEMASK1_32(22)
+#define M_LDT_BRCTL_FASTB2B_EN          _SB_MAKEMASK1_32(23)
+#define M_LDT_BRCTL_PRIDISCARD          _SB_MAKEMASK1_32(24)
+#define M_LDT_BRCTL_SECDISCARD          _SB_MAKEMASK1_32(25)
+#define M_LDT_BRCTL_DISCARDSTAT         _SB_MAKEMASK1_32(26)
+#define M_LDT_BRCTL_DISCARDSERR_EN      _SB_MAKEMASK1_32(27)
+
+/*
+ * LDT Command Register (Table 8-17).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x40
+ */
+
+#define M_LDT_CMD_WARMRESET             _SB_MAKEMASK1_32(16)
+#define M_LDT_CMD_DOUBLEENDED           _SB_MAKEMASK1_32(17)
+
+#define S_LDT_CMD_CAPTYPE               29
+#define M_LDT_CMD_CAPTYPE               _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
+#define V_LDT_CMD_CAPTYPE(x)            _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
+#define G_LDT_CMD_CAPTYPE(x)            _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
+
+/*
+ * LDT link control register (Table 8-18), and (Table 8-19)
+ */
+
+#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN  _SB_MAKEMASK1_32(1)
+#define M_LDT_LINKCTRL_CRCSTARTTEST     _SB_MAKEMASK1_32(2)
+#define M_LDT_LINKCTRL_CRCFORCEERR      _SB_MAKEMASK1_32(3)
+#define M_LDT_LINKCTRL_LINKFAIL         _SB_MAKEMASK1_32(4)
+#define M_LDT_LINKCTRL_INITDONE         _SB_MAKEMASK1_32(5)
+#define M_LDT_LINKCTRL_EOC              _SB_MAKEMASK1_32(6)
+#define M_LDT_LINKCTRL_XMITOFF          _SB_MAKEMASK1_32(7)
+
+#define S_LDT_LINKCTRL_CRCERR           8
+#define M_LDT_LINKCTRL_CRCERR           _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
+#define V_LDT_LINKCTRL_CRCERR(x)        _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
+#define G_LDT_LINKCTRL_CRCERR(x)        _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
+
+#define S_LDT_LINKCTRL_MAXIN            16
+#define M_LDT_LINKCTRL_MAXIN            _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
+#define V_LDT_LINKCTRL_MAXIN(x)         _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
+#define G_LDT_LINKCTRL_MAXIN(x)         _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
+
+#define M_LDT_LINKCTRL_DWFCLN           _SB_MAKEMASK1_32(19)
+
+#define S_LDT_LINKCTRL_MAXOUT           20
+#define M_LDT_LINKCTRL_MAXOUT           _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
+#define V_LDT_LINKCTRL_MAXOUT(x)        _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
+#define G_LDT_LINKCTRL_MAXOUT(x)        _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT          _SB_MAKEMASK1_32(23)
+
+#define S_LDT_LINKCTRL_WIDTHIN          24
+#define M_LDT_LINKCTRL_WIDTHIN          _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
+#define V_LDT_LINKCTRL_WIDTHIN(x)       _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
+#define G_LDT_LINKCTRL_WIDTHIN(x)       _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
+
+#define M_LDT_LINKCTRL_DWFCLIN_EN       _SB_MAKEMASK1_32(27)
+
+#define S_LDT_LINKCTRL_WIDTHOUT         28
+#define M_LDT_LINKCTRL_WIDTHOUT         _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
+#define V_LDT_LINKCTRL_WIDTHOUT(x)      _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
+#define G_LDT_LINKCTRL_WIDTHOUT(x)      _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT_EN       _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Link frequency register  (Table 8-20) offset 0x48
+ */
+
+#define S_LDT_LINKFREQ_FREQ             8
+#define M_LDT_LINKFREQ_FREQ             _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
+#define V_LDT_LINKFREQ_FREQ(x)          _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
+#define G_LDT_LINKFREQ_FREQ(x)          _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
+
+#define K_LDT_LINKFREQ_200MHZ           0
+#define K_LDT_LINKFREQ_300MHZ           1
+#define K_LDT_LINKFREQ_400MHZ           2
+#define K_LDT_LINKFREQ_500MHZ           3
+#define K_LDT_LINKFREQ_600MHZ           4
+#define K_LDT_LINKFREQ_800MHZ           5
+#define K_LDT_LINKFREQ_1000MHZ          6
+
+/*
+ * LDT SRI Command Register (Table 8-21).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x50
+ */
+
+#define M_LDT_SRICMD_SIPREADY           _SB_MAKEMASK1_32(16)
+#define M_LDT_SRICMD_SYNCPTRCTL         _SB_MAKEMASK1_32(17)
+#define M_LDT_SRICMD_REDUCESYNCZERO     _SB_MAKEMASK1_32(18)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_LDT_SRICMD_DISSTARVATIONCNT   _SB_MAKEMASK1_32(19)    /* PASS1 */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_SRICMD_DISMULTTXVLD       _SB_MAKEMASK1_32(19)
+#define M_LDT_SRICMD_EXPENDIAN          _SB_MAKEMASK1_32(26)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+#define S_LDT_SRICMD_RXMARGIN           20
+#define M_LDT_SRICMD_RXMARGIN           _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
+#define V_LDT_SRICMD_RXMARGIN(x)        _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
+#define G_LDT_SRICMD_RXMARGIN(x)        _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
+
+#define M_LDT_SRICMD_LDTPLLCOMPAT       _SB_MAKEMASK1_32(25)
+
+#define S_LDT_SRICMD_TXINITIALOFFSET    28
+#define M_LDT_SRICMD_TXINITIALOFFSET    _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
+#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
+#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
+
+#define M_LDT_SRICMD_LINKFREQDIRECT     _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Error control and status register (Table 8-22) (Table 8-23)
+ */
+
+#define M_LDT_ERRCTL_PROTFATAL_EN       _SB_MAKEMASK1_32(0)
+#define M_LDT_ERRCTL_PROTNONFATAL_EN    _SB_MAKEMASK1_32(1)
+#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN   _SB_MAKEMASK1_32(2)
+#define M_LDT_ERRCTL_OVFFATAL_EN        _SB_MAKEMASK1_32(3)
+#define M_LDT_ERRCTL_OVFNONFATAL_EN     _SB_MAKEMASK1_32(4)
+#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN    _SB_MAKEMASK1_32(5)
+#define M_LDT_ERRCTL_EOCNXAFATAL_EN     _SB_MAKEMASK1_32(6)
+#define M_LDT_ERRCTL_EOCNXANONFATAL_EN  _SB_MAKEMASK1_32(7)
+#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
+#define M_LDT_ERRCTL_CRCFATAL_EN        _SB_MAKEMASK1_32(9)
+#define M_LDT_ERRCTL_CRCNONFATAL_EN     _SB_MAKEMASK1_32(10)
+#define M_LDT_ERRCTL_SERRFATAL_EN       _SB_MAKEMASK1_32(11)
+#define M_LDT_ERRCTL_SRCTAGFATAL_EN     _SB_MAKEMASK1_32(12)
+#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN  _SB_MAKEMASK1_32(13)
+#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
+#define M_LDT_ERRCTL_MAPNXAFATAL_EN     _SB_MAKEMASK1_32(15)
+#define M_LDT_ERRCTL_MAPNXANONFATAL_EN  _SB_MAKEMASK1_32(16)
+#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
+
+#define M_LDT_ERRCTL_PROTOERR           _SB_MAKEMASK1_32(24)
+#define M_LDT_ERRCTL_OVFERR             _SB_MAKEMASK1_32(25)
+#define M_LDT_ERRCTL_EOCNXAERR          _SB_MAKEMASK1_32(26)
+#define M_LDT_ERRCTL_SRCTAGERR          _SB_MAKEMASK1_32(27)
+#define M_LDT_ERRCTL_MAPNXAERR          _SB_MAKEMASK1_32(28)
+
+/*
+ * SRI Control register (Table 8-24, 8-25)  Offset 0x6C
+ */
+
+#define S_LDT_SRICTRL_NEEDRESP          0
+#define M_LDT_SRICTRL_NEEDRESP          _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP)
+#define V_LDT_SRICTRL_NEEDRESP(x)       _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP)
+#define G_LDT_SRICTRL_NEEDRESP(x)       _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP)
+
+#define S_LDT_SRICTRL_NEEDNPREQ         2
+#define M_LDT_SRICTRL_NEEDNPREQ         _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ)
+#define V_LDT_SRICTRL_NEEDNPREQ(x)      _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ)
+#define G_LDT_SRICTRL_NEEDNPREQ(x)      _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ)
+
+#define S_LDT_SRICTRL_NEEDPREQ          4
+#define M_LDT_SRICTRL_NEEDPREQ          _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ)
+#define V_LDT_SRICTRL_NEEDPREQ(x)       _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ)
+#define G_LDT_SRICTRL_NEEDPREQ(x)       _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ)
+
+#define S_LDT_SRICTRL_WANTRESP          8
+#define M_LDT_SRICTRL_WANTRESP          _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP)
+#define V_LDT_SRICTRL_WANTRESP(x)       _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP)
+#define G_LDT_SRICTRL_WANTRESP(x)       _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP)
+
+#define S_LDT_SRICTRL_WANTNPREQ         10
+#define M_LDT_SRICTRL_WANTNPREQ         _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ)
+#define V_LDT_SRICTRL_WANTNPREQ(x)      _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ)
+#define G_LDT_SRICTRL_WANTNPREQ(x)      _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ)
+
+#define S_LDT_SRICTRL_WANTPREQ          12
+#define M_LDT_SRICTRL_WANTPREQ          _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ)
+#define V_LDT_SRICTRL_WANTPREQ(x)       _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ)
+#define G_LDT_SRICTRL_WANTPREQ(x)       _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ)
+
+#define S_LDT_SRICTRL_BUFRELSPACE       16
+#define M_LDT_SRICTRL_BUFRELSPACE       _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE)
+#define V_LDT_SRICTRL_BUFRELSPACE(x)    _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE)
+#define G_LDT_SRICTRL_BUFRELSPACE(x)    _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE)
+
+/*
+ * LDT SRI Transmit Buffer Count register (Table 8-26)
+ */
+
+#define S_LDT_TXBUFCNT_PCMD             0
+#define M_LDT_TXBUFCNT_PCMD             _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD)
+#define V_LDT_TXBUFCNT_PCMD(x)          _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD)
+#define G_LDT_TXBUFCNT_PCMD(x)          _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD)
+
+#define S_LDT_TXBUFCNT_PDATA            4
+#define M_LDT_TXBUFCNT_PDATA            _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA)
+#define V_LDT_TXBUFCNT_PDATA(x)         _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA)
+#define G_LDT_TXBUFCNT_PDATA(x)         _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA)
+
+#define S_LDT_TXBUFCNT_NPCMD            8
+#define M_LDT_TXBUFCNT_NPCMD            _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD)
+#define V_LDT_TXBUFCNT_NPCMD(x)         _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD)
+#define G_LDT_TXBUFCNT_NPCMD(x)         _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD)
+
+#define S_LDT_TXBUFCNT_NPDATA           12
+#define M_LDT_TXBUFCNT_NPDATA           _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA)
+#define V_LDT_TXBUFCNT_NPDATA(x)        _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA)
+#define G_LDT_TXBUFCNT_NPDATA(x)        _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA)
+
+#define S_LDT_TXBUFCNT_RCMD             16
+#define M_LDT_TXBUFCNT_RCMD             _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD)
+#define V_LDT_TXBUFCNT_RCMD(x)          _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD)
+#define G_LDT_TXBUFCNT_RCMD(x)          _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD)
+
+#define S_LDT_TXBUFCNT_RDATA            20
+#define M_LDT_TXBUFCNT_RDATA            _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA)
+#define V_LDT_TXBUFCNT_RDATA(x)         _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA)
+#define G_LDT_TXBUFCNT_RDATA(x)         _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Additional Status Register
+ */
+
+#define S_LDT_ADDSTATUS_TGTDONE         0
+#define M_LDT_ADDSTATUS_TGTDONE         _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE)
+#define V_LDT_ADDSTATUS_TGTDONE(x)      _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE)
+#define G_LDT_ADDSTATUS_TGTDONE(x)      _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
+
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
new file mode 100644
index 000000000000..81f603f03a98
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -0,0 +1,643 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  MAC constants and macros                 File: sb1250_mac.h
+    *  
+    *  This module contains constants and macros for the SB1250's
+    *  ethernet controllers.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MAC_H
+#define _SB1250_MAC_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Ethernet MAC Registers
+    ********************************************************************* */
+
+/*
+ * MAC Configuration Register (Table 9-13)
+ * Register: MAC_CFG_0
+ * Register: MAC_CFG_1
+ * Register: MAC_CFG_2
+ */
+
+
+#define M_MAC_RESERVED0             _SB_MAKEMASK1(0)
+#define M_MAC_TX_HOLD_SOP_EN        _SB_MAKEMASK1(1)
+#define M_MAC_RETRY_EN              _SB_MAKEMASK1(2)
+#define M_MAC_RET_DRPREQ_EN         _SB_MAKEMASK1(3)
+#define M_MAC_RET_UFL_EN            _SB_MAKEMASK1(4)
+#define M_MAC_BURST_EN              _SB_MAKEMASK1(5)
+
+#define S_MAC_TX_PAUSE              _SB_MAKE64(6)
+#define M_MAC_TX_PAUSE_CNT          _SB_MAKEMASK(3,S_MAC_TX_PAUSE)
+#define V_MAC_TX_PAUSE_CNT(x)       _SB_MAKEVALUE(x,S_MAC_TX_PAUSE)
+
+#define K_MAC_TX_PAUSE_CNT_512      0
+#define K_MAC_TX_PAUSE_CNT_1K       1
+#define K_MAC_TX_PAUSE_CNT_2K       2
+#define K_MAC_TX_PAUSE_CNT_4K       3
+#define K_MAC_TX_PAUSE_CNT_8K       4
+#define K_MAC_TX_PAUSE_CNT_16K      5
+#define K_MAC_TX_PAUSE_CNT_32K      6
+#define K_MAC_TX_PAUSE_CNT_64K      7
+
+#define V_MAC_TX_PAUSE_CNT_512      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
+#define V_MAC_TX_PAUSE_CNT_1K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
+#define V_MAC_TX_PAUSE_CNT_2K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
+#define V_MAC_TX_PAUSE_CNT_4K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
+#define V_MAC_TX_PAUSE_CNT_8K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
+#define V_MAC_TX_PAUSE_CNT_16K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
+#define V_MAC_TX_PAUSE_CNT_32K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
+#define V_MAC_TX_PAUSE_CNT_64K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
+
+#define M_MAC_RESERVED1             _SB_MAKEMASK(8,9)
+
+#define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
+#define M_MAC_RESERVED2             _SB_MAKEMASK1(18)
+#define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
+#define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
+#define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
+#define M_MAC_DRP_DRBLERRPKT_EN     _SB_MAKEMASK1(22)
+#define M_MAC_DRP_RNTPKT_EN         _SB_MAKEMASK1(23)
+#define M_MAC_DRP_OSZPKT_EN         _SB_MAKEMASK1(24)
+#define M_MAC_DRP_LENERRPKT_EN      _SB_MAKEMASK1(25)
+
+#define M_MAC_RESERVED3             _SB_MAKEMASK(6,26)
+
+#define M_MAC_BYPASS_SEL            _SB_MAKEMASK1(32)
+#define M_MAC_HDX_EN                _SB_MAKEMASK1(33)
+
+#define S_MAC_SPEED_SEL             _SB_MAKE64(34)
+#define M_MAC_SPEED_SEL             _SB_MAKEMASK(2,S_MAC_SPEED_SEL)
+#define V_MAC_SPEED_SEL(x)          _SB_MAKEVALUE(x,S_MAC_SPEED_SEL)
+#define G_MAC_SPEED_SEL(x)          _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL)
+
+#define K_MAC_SPEED_SEL_10MBPS      0
+#define K_MAC_SPEED_SEL_100MBPS     1
+#define K_MAC_SPEED_SEL_1000MBPS    2
+#define K_MAC_SPEED_SEL_RESERVED    3
+
+#define V_MAC_SPEED_SEL_10MBPS      V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
+#define V_MAC_SPEED_SEL_100MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
+#define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
+#define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
+
+#define M_MAC_TX_CLK_EDGE_SEL       _SB_MAKEMASK1(36)
+#define M_MAC_LOOPBACK_SEL          _SB_MAKEMASK1(37)
+#define M_MAC_FAST_SYNC             _SB_MAKEMASK1(38)
+#define M_MAC_SS_EN                 _SB_MAKEMASK1(39)
+
+#define S_MAC_BYPASS_CFG            _SB_MAKE64(40)
+#define M_MAC_BYPASS_CFG            _SB_MAKEMASK(2,S_MAC_BYPASS_CFG)
+#define V_MAC_BYPASS_CFG(x)         _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG)
+#define G_MAC_BYPASS_CFG(x)         _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG)
+
+#define K_MAC_BYPASS_GMII           0
+#define K_MAC_BYPASS_ENCODED        1
+#define K_MAC_BYPASS_SOP            2
+#define K_MAC_BYPASS_EOP            3
+
+#define M_MAC_BYPASS_16             _SB_MAKEMASK1(42)
+#define M_MAC_BYPASS_FCS_CHK        _SB_MAKEMASK1(43)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
+#define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
+#define V_MAC_BYPASS_IFG(x)         _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG)
+#define G_MAC_BYPASS_IFG(x)         _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG)
+
+#define K_MAC_FC_CMD_DISABLED       0
+#define K_MAC_FC_CMD_ENABLED        1
+#define K_MAC_FC_CMD_ENAB_FALSECARR 2
+
+#define V_MAC_FC_CMD_DISABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
+#define V_MAC_FC_CMD_ENABLED        V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
+#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
+
+#define M_MAC_FC_SEL                _SB_MAKEMASK1(54)
+
+#define S_MAC_FC_CMD                _SB_MAKE64(55)
+#define M_MAC_FC_CMD                _SB_MAKEMASK(2,S_MAC_FC_CMD)
+#define V_MAC_FC_CMD(x)             _SB_MAKEVALUE(x,S_MAC_FC_CMD)
+#define G_MAC_FC_CMD(x)             _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD)
+
+#define S_MAC_RX_CH_SEL             _SB_MAKE64(57)
+#define M_MAC_RX_CH_SEL             _SB_MAKEMASK(7,S_MAC_RX_CH_SEL)
+#define V_MAC_RX_CH_SEL(x)          _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL)
+#define G_MAC_RX_CH_SEL(x)          _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL)
+
+
+/*
+ * MAC Enable Registers
+ * Register: MAC_ENABLE_0
+ * Register: MAC_ENABLE_1
+ * Register: MAC_ENABLE_2
+ */
+
+#define M_MAC_RXDMA_EN0             _SB_MAKEMASK1(0)
+#define M_MAC_RXDMA_EN1             _SB_MAKEMASK1(1)
+#define M_MAC_TXDMA_EN0             _SB_MAKEMASK1(4)
+#define M_MAC_TXDMA_EN1             _SB_MAKEMASK1(5)
+
+#define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
+
+#define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
+#define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
+#define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
+#define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+
+/*
+ * MAC DMA Control Register
+ * Register: MAC_TXD_CTL_0
+ * Register: MAC_TXD_CTL_1
+ * Register: MAC_TXD_CTL_2
+ */
+
+#define S_MAC_TXD_WEIGHT0           _SB_MAKE64(0)
+#define M_MAC_TXD_WEIGHT0           _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0)
+#define V_MAC_TXD_WEIGHT0(x)        _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0)
+#define G_MAC_TXD_WEIGHT0(x)        _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0)
+
+#define S_MAC_TXD_WEIGHT1           _SB_MAKE64(4)
+#define M_MAC_TXD_WEIGHT1           _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1)
+#define V_MAC_TXD_WEIGHT1(x)        _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1)
+#define G_MAC_TXD_WEIGHT1(x)        _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1)
+
+/*
+ * MAC Fifo Threshhold registers (Table 9-14)
+ * Register: MAC_THRSH_CFG_0
+ * Register: MAC_THRSH_CFG_1
+ * Register: MAC_THRSH_CFG_2
+ */
+
+#define S_MAC_TX_WR_THRSH           _SB_MAKE64(0)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define V_MAC_TX_WR_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
+#define G_MAC_TX_WR_THRSH(x)        _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
+
+#define S_MAC_TX_RD_THRSH           _SB_MAKE64(8)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define V_MAC_TX_RD_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
+#define G_MAC_TX_RD_THRSH(x)        _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
+
+#define S_MAC_TX_RL_THRSH           _SB_MAKE64(16)
+#define M_MAC_TX_RL_THRSH           _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH)
+#define V_MAC_TX_RL_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH)
+#define G_MAC_TX_RL_THRSH(x)        _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH)
+
+#define S_MAC_RX_PL_THRSH           _SB_MAKE64(24)
+#define M_MAC_RX_PL_THRSH           _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH)
+#define V_MAC_RX_PL_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH)
+#define G_MAC_RX_PL_THRSH(x)        _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH)
+
+#define S_MAC_RX_RD_THRSH           _SB_MAKE64(32)
+#define M_MAC_RX_RD_THRSH           _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH)
+#define V_MAC_RX_RD_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH)
+#define G_MAC_RX_RD_THRSH(x)        _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH)
+
+#define S_MAC_RX_RL_THRSH           _SB_MAKE64(40)
+#define M_MAC_RX_RL_THRSH           _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH)
+#define V_MAC_RX_RL_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
+#define G_MAC_RX_RL_THRSH(x)        _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_ENC_FC_THRSH           _SB_MAKE64(56)
+#define M_MAC_ENC_FC_THRSH           _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
+#define V_MAC_ENC_FC_THRSH(x)        _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
+#define G_MAC_ENC_FC_THRSH(x)        _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * MAC Frame Configuration Registers (Table 9-15)
+ * Register: MAC_FRAME_CFG_0
+ * Register: MAC_FRAME_CFG_1
+ * Register: MAC_FRAME_CFG_2
+ */
+
+/* XXXCGD: ??? Unused in pass2? */
+#define S_MAC_IFG_RX                _SB_MAKE64(0)
+#define M_MAC_IFG_RX                _SB_MAKEMASK(6,S_MAC_IFG_RX)
+#define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x,S_MAC_IFG_RX)
+#define G_MAC_IFG_RX(x)             _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_PRE_LEN               _SB_MAKE64(0)
+#define M_MAC_PRE_LEN               _SB_MAKEMASK(6,S_MAC_PRE_LEN)
+#define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
+#define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define S_MAC_IFG_TX                _SB_MAKE64(6)
+#define M_MAC_IFG_TX                _SB_MAKEMASK(6,S_MAC_IFG_TX)
+#define V_MAC_IFG_TX(x)             _SB_MAKEVALUE(x,S_MAC_IFG_TX)
+#define G_MAC_IFG_TX(x)             _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX)
+
+#define S_MAC_IFG_THRSH             _SB_MAKE64(12)
+#define M_MAC_IFG_THRSH             _SB_MAKEMASK(6,S_MAC_IFG_THRSH)
+#define V_MAC_IFG_THRSH(x)          _SB_MAKEVALUE(x,S_MAC_IFG_THRSH)
+#define G_MAC_IFG_THRSH(x)          _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH)
+
+#define S_MAC_BACKOFF_SEL           _SB_MAKE64(18)
+#define M_MAC_BACKOFF_SEL           _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL)
+#define V_MAC_BACKOFF_SEL(x)        _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL)
+#define G_MAC_BACKOFF_SEL(x)        _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL)
+
+#define S_MAC_LFSR_SEED             _SB_MAKE64(22)
+#define M_MAC_LFSR_SEED             _SB_MAKEMASK(8,S_MAC_LFSR_SEED)
+#define V_MAC_LFSR_SEED(x)          _SB_MAKEVALUE(x,S_MAC_LFSR_SEED)
+#define G_MAC_LFSR_SEED(x)          _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED)
+
+#define S_MAC_SLOT_SIZE             _SB_MAKE64(30)
+#define M_MAC_SLOT_SIZE             _SB_MAKEMASK(10,S_MAC_SLOT_SIZE)
+#define V_MAC_SLOT_SIZE(x)          _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE)
+#define G_MAC_SLOT_SIZE(x)          _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE)
+
+#define S_MAC_MIN_FRAMESZ           _SB_MAKE64(40)
+#define M_MAC_MIN_FRAMESZ           _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ)
+#define V_MAC_MIN_FRAMESZ(x)        _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ)
+#define G_MAC_MIN_FRAMESZ(x)        _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ)
+
+#define S_MAC_MAX_FRAMESZ           _SB_MAKE64(48)
+#define M_MAC_MAX_FRAMESZ           _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ)
+#define V_MAC_MAX_FRAMESZ(x)        _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ)
+#define G_MAC_MAX_FRAMESZ(x)        _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ)
+
+/*
+ * These constants are used to configure the fields within the Frame
+ * Configuration Register.  
+ */
+
+#define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
+#define K_MAC_IFG_RX_100            _SB_MAKE64(0)
+#define K_MAC_IFG_RX_1000           _SB_MAKE64(0)
+
+#define K_MAC_IFG_TX_10             _SB_MAKE64(20)
+#define K_MAC_IFG_TX_100            _SB_MAKE64(20)
+#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)
+
+#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)
+
+#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)
+
+#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)
+#define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
+#define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
+
+#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)
+#define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
+#define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
+
+#define V_MAC_IFG_THRSH_10     V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
+#define V_MAC_IFG_THRSH_100    V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
+#define V_MAC_IFG_THRSH_1000   V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
+
+#define V_MAC_SLOT_SIZE_10     V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
+#define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
+#define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
+
+#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)
+#define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
+#define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)
+#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)
+
+#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
+#define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
+
+/*
+ * MAC VLAN Tag Registers (Table 9-16)
+ * Register: MAC_VLANTAG_0
+ * Register: MAC_VLANTAG_1
+ * Register: MAC_VLANTAG_2
+ */
+
+#define S_MAC_VLAN_TAG           _SB_MAKE64(0)
+#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32,S_MAC_VLAN_TAG)
+#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)
+#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)
+#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)
+#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)
+#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET)
+
+#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)
+#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET)
+#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET)
+#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)
+
+#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * MAC Status Registers (Table 9-17)
+ * Also used for the MAC Interrupt Mask Register (Table 9-18)
+ * Register: MAC_STATUS_0
+ * Register: MAC_STATUS_1
+ * Register: MAC_STATUS_2
+ * Register: MAC_INT_MASK_0
+ * Register: MAC_INT_MASK_1
+ * Register: MAC_INT_MASK_2
+ */
+
+/* 
+ * Use these constants to shift the appropriate channel
+ * into the CH0 position so the same tests can be used
+ * on each channel.
+ */
+
+#define S_MAC_RX_CH0                _SB_MAKE64(0)
+#define S_MAC_RX_CH1                _SB_MAKE64(8)
+#define S_MAC_TX_CH0                _SB_MAKE64(16)
+#define S_MAC_TX_CH1                _SB_MAKE64(24)
+
+#define S_MAC_TXCHANNELS            _SB_MAKE64(16)      /* this is 1st TX chan */
+#define S_MAC_CHANWIDTH             _SB_MAKE64(8)       /* bits between channels */
+
+/*
+ *  These are the same as RX channel 0.  The idea here
+ *  is that you'll use one of the "S_" things above
+ *  and pass just the six bits to a DMA-channel-specific ISR
+ */
+#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8,0)
+#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)
+#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)
+#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)
+#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)
+#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)
+#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)
+#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)
+#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)    /* only for TX channels */
+#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)    /* only for RX channels */
+
+/*
+ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
+ * also DMA_TX/DMA_RX in sb_regs.h).
+ */
+#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
+
+#define M_MAC_STATUS_CHANNEL(ch,txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_EOP_SEEN(ch,txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_HWM(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_LWM(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_DSCR(ch,txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_ERR(ch,txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_DZERO(ch,txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_DROP(ch,txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx))
+#define M_MAC_STATUS_OTHER_ERR          _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40)
+
+
+#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)
+#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)
+#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)
+#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)
+#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)
+#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)
+#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_SPLIT_EN              _SB_MAKEMASK1(47)   /* interrupt mask only */
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)
+#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
+#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
+#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
+ * Register: MAC_FIFO_PTRS_0
+ * Register: MAC_FIFO_PTRS_1
+ * Register: MAC_FIFO_PTRS_2
+ */
+
+#define S_MAC_TX_WRPTR              _SB_MAKE64(0)
+#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6,S_MAC_TX_WRPTR)
+#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x,S_MAC_TX_WRPTR)
+#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR)
+
+#define S_MAC_TX_RDPTR              _SB_MAKE64(8)
+#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6,S_MAC_TX_RDPTR)
+#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x,S_MAC_TX_RDPTR)
+#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR)
+
+#define S_MAC_RX_WRPTR              _SB_MAKE64(16)
+#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6,S_MAC_RX_WRPTR)
+#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x,S_MAC_RX_WRPTR)
+#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR)
+
+#define S_MAC_RX_RDPTR              _SB_MAKE64(24)
+#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6,S_MAC_RX_RDPTR)
+#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x,S_MAC_RX_RDPTR)
+#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR)
+
+/*
+ * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register]
+ * Register: MAC_EOPCNT_0
+ * Register: MAC_EOPCNT_1
+ * Register: MAC_EOPCNT_2
+ */
+
+#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)
+#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER)
+#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER)
+#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER)
+
+#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)
+#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER)
+#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER)
+#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER)
+
+/*
+ * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
+ * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
+ * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
+ * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Receive Address Filter Mask Registers
+ * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
+ * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
+ * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
+ * Registers: MAC_HASH0_0 through MAC_HASH7_0
+ * Registers: MAC_HASH0_1 through MAC_HASH7_1
+ * Registers: MAC_HASH0_2 through MAC_HASH7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Transmit Source Address Registers (Table 9-23)
+ * Register: MAC_ETHERNET_ADDR_0
+ * Register: MAC_ETHERNET_ADDR_1
+ * Register: MAC_ETHERNET_ADDR_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Packet Type Configuration Register
+ * Register: MAC_TYPE_CFG_0
+ * Register: MAC_TYPE_CFG_1
+ * Register: MAC_TYPE_CFG_2
+ */
+
+#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)
+
+#define S_TYPECFG_TYPE0         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16,S_TYPECFG_TYPE0)
+#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE0)
+#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0)
+
+#define S_TYPECFG_TYPE1         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16,S_TYPECFG_TYPE1)
+#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE1)
+#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1)
+
+#define S_TYPECFG_TYPE2         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16,S_TYPECFG_TYPE2)
+#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE2)
+#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2)
+
+#define S_TYPECFG_TYPE3         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16,S_TYPECFG_TYPE3)
+#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x,S_TYPECFG_TYPE3)
+#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3)
+
+/*
+ * MAC Receive Address Filter Control Registers (Table 9-24)
+ * Register: MAC_ADFILTER_CFG_0
+ * Register: MAC_ADFILTER_CFG_1
+ * Register: MAC_ADFILTER_CFG_2
+ */
+
+#define M_MAC_ALLPKT_EN         _SB_MAKEMASK1(0)
+#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)
+#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)
+#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)
+#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)
+#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)
+#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MAC_ALLMCAST_EN       _SB_MAKEMASK1(7)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)
+#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
+#define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
+#define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
+#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
+#define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
+#define G_MAC_RX_CRC_OFFSET(x)  _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET)
+
+#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)
+#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET)
+#define V_MAC_RX_PKT_OFFSET(x)  _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET)
+#define G_MAC_RX_PKT_OFFSET(x)  _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET)
+
+#define M_MAC_FWDPAUSE_EN       _SB_MAKEMASK1(32)
+#define M_MAC_VLAN_DET_EN       _SB_MAKEMASK1(33)
+
+#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)
+#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
+#define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
+#define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * MAC Receive Channel Select Registers (Table 9-25)
+ */
+
+/* no bitfields */
+
+/*
+ * MAC MII Management Interface Registers (Table 9-26)
+ * Register: MAC_MDIO_0
+ * Register: MAC_MDIO_1
+ * Register: MAC_MDIO_2
+ */
+
+#define S_MAC_MDC               0
+#define S_MAC_MDIO_DIR          1
+#define S_MAC_MDIO_OUT          2
+#define S_MAC_GENC              3
+#define S_MAC_MDIO_IN           4
+
+#define M_MAC_MDC               _SB_MAKEMASK1(S_MAC_MDC)
+#define M_MAC_MDIO_DIR          _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_DIR_INPUT    _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_OUT          _SB_MAKEMASK1(S_MAC_MDIO_OUT)
+#define M_MAC_GENC              _SB_MAKEMASK1(S_MAC_GENC)
+#define M_MAC_MDIO_IN           _SB_MAKEMASK1(S_MAC_MDIO_IN)
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
new file mode 100644
index 000000000000..93a48334b874
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -0,0 +1,548 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  Memory Controller constants              File: sb1250_mc.h       
+    *  
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MC_H
+#define _SB1250_MC_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Memory Channel Config Register (table 6-14)
+ */
+
+#define S_MC_RESERVED0              0
+#define M_MC_RESERVED0              _SB_MAKEMASK(8,S_MC_RESERVED0)
+
+#define S_MC_CHANNEL_SEL            8
+#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8,S_MC_CHANNEL_SEL)
+#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL)
+#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL)
+
+#define S_MC_BANK0_MAP              16
+#define M_MC_BANK0_MAP              _SB_MAKEMASK(4,S_MC_BANK0_MAP)
+#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK0_MAP)
+#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP)
+
+#define K_MC_BANK0_MAP_DEFAULT      0x00
+#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
+
+#define S_MC_BANK1_MAP              20
+#define M_MC_BANK1_MAP              _SB_MAKEMASK(4,S_MC_BANK1_MAP)
+#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK1_MAP)
+#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP)
+
+#define K_MC_BANK1_MAP_DEFAULT      0x08
+#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
+
+#define S_MC_BANK2_MAP              24
+#define M_MC_BANK2_MAP              _SB_MAKEMASK(4,S_MC_BANK2_MAP)
+#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK2_MAP)
+#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP)
+
+#define K_MC_BANK2_MAP_DEFAULT      0x09
+#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
+
+#define S_MC_BANK3_MAP              28
+#define M_MC_BANK3_MAP              _SB_MAKEMASK(4,S_MC_BANK3_MAP)
+#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x,S_MC_BANK3_MAP)
+#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP)
+
+#define K_MC_BANK3_MAP_DEFAULT      0x0C
+#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
+
+#define M_MC_RESERVED1              _SB_MAKEMASK(8,32)
+
+#define S_MC_QUEUE_SIZE             40
+#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4,S_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE)
+#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)
+
+#define S_MC_AGE_LIMIT              44
+#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4,S_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x,S_MC_AGE_LIMIT)
+#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)
+
+#define S_MC_WR_LIMIT               48
+#define M_MC_WR_LIMIT               _SB_MAKEMASK(4,S_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x,S_MC_WR_LIMIT)
+#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)
+
+#define M_MC_IOB1HIGHPRIORITY       _SB_MAKEMASK1(52)
+
+#define M_MC_RESERVED2              _SB_MAKEMASK(3,53)
+
+#define S_MC_CS_MODE                56
+#define M_MC_CS_MODE                _SB_MAKEMASK(4,S_MC_CS_MODE)
+#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x,S_MC_CS_MODE)
+#define G_MC_CS_MODE(x)             _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE)
+
+#define K_MC_CS_MODE_MSB_CS         0
+#define K_MC_CS_MODE_INTLV_CS       15
+#define K_MC_CS_MODE_MIXED_CS_10    12
+#define K_MC_CS_MODE_MIXED_CS_30    6
+#define K_MC_CS_MODE_MIXED_CS_32    3
+
+#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
+#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
+#define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
+#define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
+#define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
+
+#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)
+#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)
+#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)
+#define M_MC_DEBUG                  _SB_MAKEMASK1(63)
+
+#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
+                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
+                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
+                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
+
+
+/*
+ * Memory clock config register (Table 6-15)
+ *
+ * Note: this field has been updated to be consistent with the errata to 0.2
+ */
+
+#define S_MC_CLK_RATIO              0
+#define M_MC_CLK_RATIO              _SB_MAKEMASK(4,S_MC_CLK_RATIO)
+#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x,S_MC_CLK_RATIO)
+#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO)
+
+#define K_MC_CLK_RATIO_2X           4
+#define K_MC_CLK_RATIO_25X          5
+#define K_MC_CLK_RATIO_3X           6
+#define K_MC_CLK_RATIO_35X          7
+#define K_MC_CLK_RATIO_4X           8
+#define K_MC_CLK_RATIO_45X          9
+
+#define V_MC_CLK_RATIO_2X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
+#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
+#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
+#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
+#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
+#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
+#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X
+
+#define S_MC_REF_RATE                8
+#define M_MC_REF_RATE                _SB_MAKEMASK(8,S_MC_REF_RATE)
+#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x,S_MC_REF_RATE)
+#define G_MC_REF_RATE(x)             _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE)
+
+#define K_MC_REF_RATE_100MHz         0x62
+#define K_MC_REF_RATE_133MHz         0x81
+#define K_MC_REF_RATE_200MHz         0xC4 
+
+#define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
+#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
+#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
+#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz
+
+#define S_MC_CLOCK_DRIVE             16
+#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE)
+#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
+
+#define S_MC_DATA_DRIVE              20
+#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4,S_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x,S_MC_DATA_DRIVE)
+#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)
+
+#define S_MC_ADDR_DRIVE              24
+#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4,S_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE)
+#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)
+
+#define S_MC_DQI_SKEW               32
+#define M_MC_DQI_SKEW               _SB_MAKEMASK(8,S_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x,S_MC_DQI_SKEW)
+#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)
+
+#define S_MC_DQO_SKEW               40
+#define M_MC_DQO_SKEW               _SB_MAKEMASK(8,S_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x,S_MC_DQO_SKEW)
+#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)
+
+#define S_MC_ADDR_SKEW               48
+#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8,S_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x,S_MC_ADDR_SKEW)
+#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)
+
+#define S_MC_DLL_DEFAULT             56
+#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8,S_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT)
+#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
+
+#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \
+                                     V_MC_ADDR_SKEW_DEFAULT | \
+                                     V_MC_DQO_SKEW_DEFAULT | \
+                                     V_MC_DQI_SKEW_DEFAULT | \
+                                     V_MC_ADDR_DRIVE_DEFAULT | \
+                                     V_MC_DATA_DRIVE_DEFAULT | \
+                                     V_MC_CLOCK_DRIVE_DEFAULT | \
+                                     V_MC_REF_RATE_DEFAULT 
+
+
+
+/*
+ * DRAM Command Register (Table 6-13)
+ */
+
+#define S_MC_COMMAND                0
+#define M_MC_COMMAND                _SB_MAKEMASK(4,S_MC_COMMAND)
+#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x,S_MC_COMMAND)
+#define G_MC_COMMAND(x)             _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND)
+
+#define K_MC_COMMAND_EMRS           0
+#define K_MC_COMMAND_MRS            1
+#define K_MC_COMMAND_PRE            2
+#define K_MC_COMMAND_AR             3
+#define K_MC_COMMAND_SETRFSH        4
+#define K_MC_COMMAND_CLRRFSH        5
+#define K_MC_COMMAND_SETPWRDN       6
+#define K_MC_COMMAND_CLRPWRDN       7
+
+#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)
+#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)
+#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)
+#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)
+#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
+#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
+#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
+#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
+
+#define M_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_MC_CS3                    _SB_MAKEMASK1(7)
+
+/*
+ * DRAM Mode Register (Table 6-14)
+ */
+
+#define S_MC_EMODE                  0
+#define M_MC_EMODE                  _SB_MAKEMASK(15,S_MC_EMODE)
+#define V_MC_EMODE(x)               _SB_MAKEVALUE(x,S_MC_EMODE)
+#define G_MC_EMODE(x)               _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE)
+#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)
+
+#define S_MC_MODE                   16
+#define M_MC_MODE                   _SB_MAKEMASK(15,S_MC_MODE)
+#define V_MC_MODE(x)                _SB_MAKEVALUE(x,S_MC_MODE)
+#define G_MC_MODE(x)                _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE)
+#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)
+
+#define S_MC_DRAM_TYPE              32
+#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3,S_MC_DRAM_TYPE)
+#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x,S_MC_DRAM_TYPE)
+#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE)
+
+#define K_MC_DRAM_TYPE_JEDEC        0
+#define K_MC_DRAM_TYPE_FCRAM        1
+#define K_MC_DRAM_TYPE_SGRAM        2
+
+#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
+#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
+#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
+
+#define M_MC_EXTERNALDECODE         _SB_MAKEMASK1(35)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
+#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(38)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+
+/*
+ * SDRAM Timing Register  (Table 6-15)
+ */
+
+#define M_MC_w2rIDLE_TWOCYCLES    _SB_MAKEMASK1(60)
+#define M_MC_r2wIDLE_TWOCYCLES    _SB_MAKEMASK1(61)
+#define M_MC_r2rIDLE_TWOCYCLES    _SB_MAKEMASK1(62)
+
+#define S_MC_tFIFO                56
+#define M_MC_tFIFO                _SB_MAKEMASK(4,S_MC_tFIFO)
+#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x,S_MC_tFIFO)
+#define G_MC_tFIFO(x)             _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO)
+#define K_MC_tFIFO_DEFAULT        1
+#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
+
+#define S_MC_tRFC                 52
+#define M_MC_tRFC                 _SB_MAKEMASK(4,S_MC_tRFC)
+#define V_MC_tRFC(x)              _SB_MAKEVALUE(x,S_MC_tRFC)
+#define G_MC_tRFC(x)              _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC)
+#define K_MC_tRFC_DEFAULT         12
+#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
+
+#define S_MC_tCwCr                40
+#define M_MC_tCwCr                _SB_MAKEMASK(4,S_MC_tCwCr)
+#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x,S_MC_tCwCr)
+#define G_MC_tCwCr(x)             _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr)
+#define K_MC_tCwCr_DEFAULT        4
+#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
+
+#define S_MC_tRCr                 28
+#define M_MC_tRCr                 _SB_MAKEMASK(4,S_MC_tRCr)
+#define V_MC_tRCr(x)              _SB_MAKEVALUE(x,S_MC_tRCr)
+#define G_MC_tRCr(x)              _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr)
+#define K_MC_tRCr_DEFAULT         9
+#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)
+
+#define S_MC_tRCw                 24
+#define M_MC_tRCw                 _SB_MAKEMASK(4,S_MC_tRCw)
+#define V_MC_tRCw(x)              _SB_MAKEVALUE(x,S_MC_tRCw)
+#define G_MC_tRCw(x)              _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw)
+#define K_MC_tRCw_DEFAULT         10
+#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)
+
+#define S_MC_tRRD                 20
+#define M_MC_tRRD                 _SB_MAKEMASK(4,S_MC_tRRD)
+#define V_MC_tRRD(x)              _SB_MAKEVALUE(x,S_MC_tRRD)
+#define G_MC_tRRD(x)              _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD)
+#define K_MC_tRRD_DEFAULT         2
+#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)
+
+#define S_MC_tRP                  16
+#define M_MC_tRP                  _SB_MAKEMASK(4,S_MC_tRP)
+#define V_MC_tRP(x)               _SB_MAKEVALUE(x,S_MC_tRP)
+#define G_MC_tRP(x)               _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP)
+#define K_MC_tRP_DEFAULT          4
+#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)
+
+#define S_MC_tCwD                 8
+#define M_MC_tCwD                 _SB_MAKEMASK(4,S_MC_tCwD)
+#define V_MC_tCwD(x)              _SB_MAKEVALUE(x,S_MC_tCwD)
+#define G_MC_tCwD(x)              _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD)
+#define K_MC_tCwD_DEFAULT         1
+#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)
+
+#define M_tCrDh                   _SB_MAKEMASK1(7)
+#define M_MC_tCrDh                M_tCrDh
+
+#define S_MC_tCrD                 4
+#define M_MC_tCrD                 _SB_MAKEMASK(3,S_MC_tCrD)
+#define V_MC_tCrD(x)              _SB_MAKEVALUE(x,S_MC_tCrD)
+#define G_MC_tCrD(x)              _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD)
+#define K_MC_tCrD_DEFAULT         2
+#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)
+
+#define S_MC_tRCD                 0
+#define M_MC_tRCD                 _SB_MAKEMASK(4,S_MC_tRCD)
+#define V_MC_tRCD(x)              _SB_MAKEVALUE(x,S_MC_tRCD)
+#define G_MC_tRCD(x)              _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD)
+#define K_MC_tRCD_DEFAULT         3
+#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)
+
+#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
+                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
+                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
+                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
+                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
+                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
+                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
+                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
+                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
+                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
+                                M_MC_r2rIDLE_TWOCYCLES
+
+/*
+ * Errata says these are not the default
+ *                               M_MC_w2rIDLE_TWOCYCLES | \
+ *                               M_MC_r2wIDLE_TWOCYCLES | \
+ */
+
+
+/*
+ * Chip Select Start Address Register (Table 6-17)
+ */
+
+#define S_MC_CS0_START              0
+#define M_MC_CS0_START              _SB_MAKEMASK(16,S_MC_CS0_START)
+#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x,S_MC_CS0_START)
+#define G_MC_CS0_START(x)           _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START)
+
+#define S_MC_CS1_START              16
+#define M_MC_CS1_START              _SB_MAKEMASK(16,S_MC_CS1_START)
+#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x,S_MC_CS1_START)
+#define G_MC_CS1_START(x)           _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START)
+
+#define S_MC_CS2_START              32
+#define M_MC_CS2_START              _SB_MAKEMASK(16,S_MC_CS2_START)
+#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x,S_MC_CS2_START)
+#define G_MC_CS2_START(x)           _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START)
+
+#define S_MC_CS3_START              48
+#define M_MC_CS3_START              _SB_MAKEMASK(16,S_MC_CS3_START)
+#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x,S_MC_CS3_START)
+#define G_MC_CS3_START(x)           _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 6-18)
+ */
+
+#define S_MC_CS0_END                0
+#define M_MC_CS0_END                _SB_MAKEMASK(16,S_MC_CS0_END)
+#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x,S_MC_CS0_END)
+#define G_MC_CS0_END(x)             _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END)
+
+#define S_MC_CS1_END                16
+#define M_MC_CS1_END                _SB_MAKEMASK(16,S_MC_CS1_END)
+#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x,S_MC_CS1_END)
+#define G_MC_CS1_END(x)             _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END)
+
+#define S_MC_CS2_END                32
+#define M_MC_CS2_END                _SB_MAKEMASK(16,S_MC_CS2_END)
+#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x,S_MC_CS2_END)
+#define G_MC_CS2_END(x)             _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END)
+
+#define S_MC_CS3_END                48
+#define M_MC_CS3_END                _SB_MAKEMASK(16,S_MC_CS3_END)
+#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x,S_MC_CS3_END)
+#define G_MC_CS3_END(x)             _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END)
+
+/*
+ * Chip Select Interleave Register (Table 6-19)
+ */
+
+#define S_MC_INTLV_RESERVED         0
+#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5,S_MC_INTLV_RESERVED)
+
+#define S_MC_INTERLEAVE             7
+#define M_MC_INTERLEAVE             _SB_MAKEMASK(18,S_MC_INTERLEAVE)
+#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x,S_MC_INTERLEAVE)
+
+#define S_MC_INTLV_MBZ              25
+#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39,S_MC_INTLV_MBZ)
+
+/*
+ * Row Address Bits Register (Table 6-20)
+ */
+
+#define S_MC_RAS_RESERVED           0
+#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5,S_MC_RAS_RESERVED)
+
+#define S_MC_RAS_SELECT             12
+#define M_MC_RAS_SELECT             _SB_MAKEMASK(25,S_MC_RAS_SELECT)
+#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x,S_MC_RAS_SELECT)
+
+#define S_MC_RAS_MBZ                37
+#define M_MC_RAS_MBZ                _SB_MAKEMASK(27,S_MC_RAS_MBZ)
+
+
+/*
+ * Column Address Bits Register (Table 6-21)
+ */
+
+#define S_MC_CAS_RESERVED           0
+#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5,S_MC_CAS_RESERVED)
+
+#define S_MC_CAS_SELECT             5
+#define M_MC_CAS_SELECT             _SB_MAKEMASK(18,S_MC_CAS_SELECT)
+#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x,S_MC_CAS_SELECT)
+
+#define S_MC_CAS_MBZ                23
+#define M_MC_CAS_MBZ                _SB_MAKEMASK(41,S_MC_CAS_MBZ)
+
+
+/*
+ * Bank Address Address Bits Register (Table 6-22)
+ */
+
+#define S_MC_BA_RESERVED            0
+#define M_MC_BA_RESERVED            _SB_MAKEMASK(5,S_MC_BA_RESERVED)
+
+#define S_MC_BA_SELECT              5
+#define M_MC_BA_SELECT              _SB_MAKEMASK(20,S_MC_BA_SELECT)
+#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x,S_MC_BA_SELECT)
+
+#define S_MC_BA_MBZ                 25
+#define M_MC_BA_MBZ                 _SB_MAKEMASK(39,S_MC_BA_MBZ)
+
+/*
+ * Chip Select Attribute Register (Table 6-23)
+ */
+
+#define K_MC_CS_ATTR_CLOSED         0
+#define K_MC_CS_ATTR_CASCHECK       1
+#define K_MC_CS_ATTR_HINT           2
+#define K_MC_CS_ATTR_OPEN           3
+
+#define S_MC_CS0_PAGE               0
+#define M_MC_CS0_PAGE               _SB_MAKEMASK(2,S_MC_CS0_PAGE)
+#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS0_PAGE)
+#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE)
+
+#define S_MC_CS1_PAGE               16
+#define M_MC_CS1_PAGE               _SB_MAKEMASK(2,S_MC_CS1_PAGE)
+#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS1_PAGE)
+#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE)
+
+#define S_MC_CS2_PAGE               32
+#define M_MC_CS2_PAGE               _SB_MAKEMASK(2,S_MC_CS2_PAGE)
+#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS2_PAGE)
+#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE)
+
+#define S_MC_CS3_PAGE               48
+#define M_MC_CS3_PAGE               _SB_MAKEMASK(2,S_MC_CS3_PAGE)
+#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x,S_MC_CS3_PAGE)
+#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE)
+
+/*
+ * ECC Test ECC Register (Table 6-25)
+ */
+
+#define S_MC_ECC_INVERT             0
+#define M_MC_ECC_INVERT             _SB_MAKEMASK(8,S_MC_ECC_INVERT)
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
new file mode 100644
index 000000000000..5d496c6faba6
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -0,0 +1,836 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  Register Definitions                     File: sb1250_regs.h
+    *  
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the SB1250.
+    *  
+    *  SB1250 specification level:  01/02/2002
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_REGS_H
+#define _SB1250_REGS_H
+
+#include "sb1250_defs.h"
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *  
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.  
+    *  
+    *  The information in this file is based on the SB1250 SOC
+    *  manual version 0.2, July 2000.
+    ********************************************************************* */
+
+
+/*  ********************************************************************* 
+    * Memory Controller Registers
+    ********************************************************************* */
+
+/*
+ * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
+ * since there is one reg there (but it could get its addr/offset constant).
+ */
+#define A_MC_BASE_0                 0x0010051000
+#define A_MC_BASE_1                 0x0010052000
+#define MC_REGISTER_SPACING         0x1000
+
+#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
+#define A_MC_REGISTER(ctlid,reg)    (A_MC_BASE(ctlid)+(reg))
+
+#define R_MC_CONFIG                 0x0000000100
+#define R_MC_DRAMCMD                0x0000000120
+#define R_MC_DRAMMODE               0x0000000140
+#define R_MC_TIMING1                0x0000000160
+#define R_MC_TIMING2                0x0000000180
+#define R_MC_CS_START               0x00000001A0
+#define R_MC_CS_END                 0x00000001C0
+#define R_MC_CS_INTERLEAVE          0x00000001E0
+#define S_MC_CS_STARTEND            16
+
+#define R_MC_CSX_BASE               0x0000000200
+#define R_MC_CSX_ROW                0x0000000000        /* relative to CSX_BASE, above */
+#define R_MC_CSX_COL                0x0000000020        /* relative to CSX_BASE, above */
+#define R_MC_CSX_BA                 0x0000000040        /* relative to CSX_BASE, above */
+#define MC_CSX_SPACING              0x0000000060        /* relative to CSX_BASE, above */
+
+#define R_MC_CS0_ROW                0x0000000200
+#define R_MC_CS0_COL                0x0000000220
+#define R_MC_CS0_BA                 0x0000000240
+#define R_MC_CS1_ROW                0x0000000260
+#define R_MC_CS1_COL                0x0000000280
+#define R_MC_CS1_BA                 0x00000002A0
+#define R_MC_CS2_ROW                0x00000002C0
+#define R_MC_CS2_COL                0x00000002E0
+#define R_MC_CS2_BA                 0x0000000300
+#define R_MC_CS3_ROW                0x0000000320
+#define R_MC_CS3_COL                0x0000000340
+#define R_MC_CS3_BA                 0x0000000360
+#define R_MC_CS_ATTR                0x0000000380
+#define R_MC_TEST_DATA              0x0000000400
+#define R_MC_TEST_ECC               0x0000000420
+#define R_MC_MCLK_CFG               0x0000000500
+
+/*  ********************************************************************* 
+    * L2 Cache Control Registers
+    ********************************************************************* */
+
+#define A_L2_READ_TAG               0x0010040018
+#define A_L2_ECC_TAG                0x0010040038
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_READ_MISC              0x0010040058
+#endif /* 1250 PASS3 || 112x PASS1 */
+#define A_L2_WAY_DISABLE            0x0010041000
+#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
+#define A_L2_MGMT_TAG_BASE          0x00D0000000
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_CACHE_DISABLE         0x0010042000
+#define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
+#define A_L2_MISC_CONFIG           0x0010043000
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/* Backward-compatibility definitions.  */
+/* XXX: discourage people from using these constants.  */
+#define A_L2_READ_ADDRESS           A_L2_READ_TAG
+#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
+
+
+/*  ********************************************************************* 
+    * PCI Interface Registers
+    ********************************************************************* */
+
+#define A_PCI_TYPE00_HEADER         0x00DE000000
+#define A_PCI_TYPE01_HEADER         0x00DE000800
+
+
+/*  ********************************************************************* 
+    * Ethernet DMA and MACs
+    ********************************************************************* */
+
+#define A_MAC_BASE_0                0x0010064000
+#define A_MAC_BASE_1                0x0010065000
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+#define A_MAC_BASE_2                0x0010066000
+#endif /* 1250 */
+
+#define MAC_SPACING                 0x1000
+#define MAC_DMA_TXRX_SPACING        0x0400
+#define MAC_DMA_CHANNEL_SPACING     0x0100
+#define DMA_RX                      0
+#define DMA_TX                      1
+#define MAC_NUM_DMACHAN             2               /* channels per direction */
+
+/* XXX: not correct; depends on SOC type.  */
+#define MAC_NUM_PORTS               3
+
+#define A_MAC_CHANNEL_BASE(macnum)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum))
+
+#define A_MAC_REGISTER(macnum,reg)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum) + (reg))
+
+
+#define R_MAC_DMA_CHANNELS              0x800 /* Relative to A_MAC_CHANNEL_BASE */
+
+#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan)    \
+             ((A_MAC_CHANNEL_BASE(macnum)) +        \
+             R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define R_MAC_DMA_CHANNEL_BASE(txrx,chan)    \
+             (R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg)           \
+            (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) +    \
+            (reg))
+
+#define R_MAC_DMA_REGISTER(txrx,chan,reg)           \
+            (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
+            (reg))
+
+/* 
+ * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
+ */
+
+#define R_MAC_DMA_CONFIG0               0x00000000
+#define R_MAC_DMA_CONFIG1               0x00000008
+#define R_MAC_DMA_DSCR_BASE             0x00000010
+#define R_MAC_DMA_DSCR_CNT              0x00000018
+#define R_MAC_DMA_CUR_DSCRA             0x00000020
+#define R_MAC_DMA_CUR_DSCRB             0x00000028
+#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_MAC_DMA_OODPKTLOST_RX         0x00000038      /* rx only */
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * RMON Counters
+ */
+
+#define R_MAC_RMON_TX_BYTES             0x00000000
+#define R_MAC_RMON_COLLISIONS           0x00000008
+#define R_MAC_RMON_LATE_COL             0x00000010
+#define R_MAC_RMON_EX_COL               0x00000018
+#define R_MAC_RMON_FCS_ERROR            0x00000020
+#define R_MAC_RMON_TX_ABORT             0x00000028
+/* Counter #6 (0x30) now reserved */
+#define R_MAC_RMON_TX_BAD               0x00000038
+#define R_MAC_RMON_TX_GOOD              0x00000040
+#define R_MAC_RMON_TX_RUNT              0x00000048
+#define R_MAC_RMON_TX_OVERSIZE          0x00000050
+#define R_MAC_RMON_RX_BYTES             0x00000080
+#define R_MAC_RMON_RX_MCAST             0x00000088
+#define R_MAC_RMON_RX_BCAST             0x00000090
+#define R_MAC_RMON_RX_BAD               0x00000098
+#define R_MAC_RMON_RX_GOOD              0x000000A0
+#define R_MAC_RMON_RX_RUNT              0x000000A8
+#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
+#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
+#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
+#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
+#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
+
+/* Updated to spec 0.2 */
+#define R_MAC_CFG                       0x00000100
+#define R_MAC_THRSH_CFG                 0x00000108
+#define R_MAC_VLANTAG                   0x00000110
+#define R_MAC_FRAMECFG                  0x00000118
+#define R_MAC_EOPCNT                    0x00000120
+#define R_MAC_FIFO_PTRS                 0x00000130
+#define R_MAC_ADFILTER_CFG              0x00000200
+#define R_MAC_ETHERNET_ADDR             0x00000208
+#define R_MAC_PKT_TYPE                  0x00000210
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_MAC_ADMASK0                   0x00000218
+#define R_MAC_ADMASK1                   0x00000220
+#endif /* 1250 PASS3 || 112x PASS1 */
+#define R_MAC_HASH_BASE                 0x00000240
+#define R_MAC_ADDR_BASE                 0x00000280
+#define R_MAC_CHLO0_BASE                0x00000300
+#define R_MAC_CHUP0_BASE                0x00000320
+#define R_MAC_ENABLE                    0x00000400
+#define R_MAC_STATUS                    0x00000408
+#define R_MAC_INT_MASK                  0x00000410
+#define R_MAC_TXD_CTL                   0x00000420
+#define R_MAC_MDIO                      0x00000428
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_MAC_STATUS1                   0x00000430
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define R_MAC_DEBUG_STATUS              0x00000448
+
+#define MAC_HASH_COUNT                  8
+#define MAC_ADDR_COUNT                  8
+#define MAC_CHMAP_COUNT                 4
+
+
+/*  ********************************************************************* 
+    * DUART Registers
+    ********************************************************************* */
+
+
+#define R_DUART_NUM_PORTS           2
+
+#define A_DUART                     0x0010060000
+
+#define A_DUART_REG(r)
+
+#define DUART_CHANREG_SPACING       0x100
+#define A_DUART_CHANREG(chan,reg)   (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
+#define R_DUART_CHANREG(chan,reg)   (DUART_CHANREG_SPACING*(chan) + (reg))
+
+#define R_DUART_MODE_REG_1          0x100
+#define R_DUART_MODE_REG_2          0x110
+#define R_DUART_STATUS              0x120
+#define R_DUART_CLK_SEL             0x130
+#define R_DUART_CMD                 0x150
+#define R_DUART_RX_HOLD             0x160
+#define R_DUART_TX_HOLD             0x170
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_DUART_FULL_CTL            0x140
+#define R_DUART_OPCR_X              0x180
+#define R_DUART_AUXCTL_X            0x190
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*
+ * The IMR and ISR can't be addressed with A_DUART_CHANREG,
+ * so use this macro instead.
+ */
+
+#define R_DUART_AUX_CTRL            0x310
+#define R_DUART_ISR_A               0x320
+#define R_DUART_IMR_A               0x330
+#define R_DUART_ISR_B               0x340
+#define R_DUART_IMR_B               0x350
+#define R_DUART_OUT_PORT            0x360
+#define R_DUART_OPCR                0x370
+
+#define R_DUART_SET_OPR             0x3B0
+#define R_DUART_CLEAR_OPR           0x3C0
+
+#define DUART_IMRISR_SPACING        0x20
+
+#define R_DUART_IMRREG(chan)        (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
+#define R_DUART_ISRREG(chan)        (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
+
+#define A_DUART_IMRREG(chan)        (A_DUART + R_DUART_IMRREG(chan))
+#define A_DUART_ISRREG(chan)        (A_DUART + R_DUART_ISRREG(chan))
+
+
+
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_DUART_MODE_REG_1_A        0x0010060100
+#define A_DUART_MODE_REG_2_A        0x0010060110
+#define A_DUART_STATUS_A            0x0010060120
+#define A_DUART_CLK_SEL_A           0x0010060130
+#define A_DUART_CMD_A               0x0010060150
+#define A_DUART_RX_HOLD_A           0x0010060160
+#define A_DUART_TX_HOLD_A           0x0010060170
+
+#define A_DUART_MODE_REG_1_B        0x0010060200
+#define A_DUART_MODE_REG_2_B        0x0010060210
+#define A_DUART_STATUS_B            0x0010060220
+#define A_DUART_CLK_SEL_B           0x0010060230
+#define A_DUART_CMD_B               0x0010060250
+#define A_DUART_RX_HOLD_B           0x0010060260
+#define A_DUART_TX_HOLD_B           0x0010060270
+
+#define A_DUART_INPORT_CHNG         0x0010060300
+#define A_DUART_AUX_CTRL            0x0010060310
+#define A_DUART_ISR_A               0x0010060320
+#define A_DUART_IMR_A               0x0010060330
+#define A_DUART_ISR_B               0x0010060340
+#define A_DUART_IMR_B               0x0010060350
+#define A_DUART_OUT_PORT            0x0010060360
+#define A_DUART_OPCR                0x0010060370
+#define A_DUART_IN_PORT             0x0010060380
+#define A_DUART_ISR                 0x0010060390
+#define A_DUART_IMR                 0x00100603A0
+#define A_DUART_SET_OPR             0x00100603B0
+#define A_DUART_CLEAR_OPR           0x00100603C0
+#define A_DUART_INPORT_CHNG_A       0x00100603D0
+#define A_DUART_INPORT_CHNG_B       0x00100603E0
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DUART_FULL_CTL_A          0x0010060140
+#define A_DUART_FULL_CTL_B          0x0010060240
+
+#define A_DUART_OPCR_A              0x0010060180
+#define A_DUART_OPCR_B              0x0010060280
+
+#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*  ********************************************************************* 
+    * Synchronous Serial Registers
+    ********************************************************************* */
+
+
+#define A_SER_BASE_0                0x0010060400
+#define A_SER_BASE_1                0x0010060800
+#define SER_SPACING                 0x400
+
+#define SER_DMA_TXRX_SPACING        0x80
+
+#define SER_NUM_PORTS               2
+
+#define A_SER_CHANNEL_BASE(sernum)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum))
+
+#define A_SER_REGISTER(sernum,reg)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum) + (reg))
+
+
+#define R_SER_DMA_CHANNELS              0   /* Relative to A_SER_BASE_x */
+
+#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
+             ((A_SER_CHANNEL_BASE(sernum)) +        \
+             R_SER_DMA_CHANNELS +                   \
+             (SER_DMA_TXRX_SPACING*(txrx)))
+
+#define A_SER_DMA_REGISTER(sernum,txrx,reg)           \
+            (A_SER_DMA_CHANNEL_BASE(sernum,txrx) +    \
+            (reg))
+
+
+/* 
+ * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
+ */
+
+#define R_SER_DMA_CONFIG0           0x00000000
+#define R_SER_DMA_CONFIG1           0x00000008
+#define R_SER_DMA_DSCR_BASE         0x00000010
+#define R_SER_DMA_DSCR_CNT          0x00000018
+#define R_SER_DMA_CUR_DSCRA         0x00000020
+#define R_SER_DMA_CUR_DSCRB         0x00000028
+#define R_SER_DMA_CUR_DSCRADDR      0x00000030
+
+#define R_SER_DMA_CONFIG0_RX        0x00000000
+#define R_SER_DMA_CONFIG1_RX        0x00000008
+#define R_SER_DMA_DSCR_BASE_RX      0x00000010
+#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
+#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
+#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
+#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
+
+#define R_SER_DMA_CONFIG0_TX        0x00000080
+#define R_SER_DMA_CONFIG1_TX        0x00000088
+#define R_SER_DMA_DSCR_BASE_TX      0x00000090
+#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
+#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
+#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
+#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
+
+#define R_SER_MODE                  0x00000100
+#define R_SER_MINFRM_SZ             0x00000108
+#define R_SER_MAXFRM_SZ             0x00000110
+#define R_SER_ADDR                  0x00000118
+#define R_SER_USR0_ADDR             0x00000120
+#define R_SER_USR1_ADDR             0x00000128
+#define R_SER_USR2_ADDR             0x00000130
+#define R_SER_USR3_ADDR             0x00000138
+#define R_SER_CMD                   0x00000140
+#define R_SER_TX_RD_THRSH           0x00000160
+#define R_SER_TX_WR_THRSH           0x00000168
+#define R_SER_RX_RD_THRSH           0x00000170
+#define R_SER_LINE_MODE             0x00000178
+#define R_SER_DMA_ENABLE            0x00000180
+#define R_SER_INT_MASK              0x00000190
+#define R_SER_STATUS                0x00000188
+#define R_SER_STATUS_DEBUG          0x000001A8
+#define R_SER_RX_TABLE_BASE         0x00000200
+#define SER_RX_TABLE_COUNT          16
+#define R_SER_TX_TABLE_BASE         0x00000300
+#define SER_TX_TABLE_COUNT          16
+
+/* RMON Counters */
+#define R_SER_RMON_TX_BYTE_LO       0x000001C0
+#define R_SER_RMON_TX_BYTE_HI       0x000001C8
+#define R_SER_RMON_RX_BYTE_LO       0x000001D0
+#define R_SER_RMON_RX_BYTE_HI       0x000001D8
+#define R_SER_RMON_TX_UNDERRUN      0x000001E0
+#define R_SER_RMON_RX_OVERFLOW      0x000001E8
+#define R_SER_RMON_RX_ERRORS        0x000001F0
+#define R_SER_RMON_RX_BADADDR       0x000001F8
+
+/*  ********************************************************************* 
+    * Generic Bus Registers
+    ********************************************************************* */
+
+#define IO_EXT_CFG_COUNT            8
+
+#define A_IO_EXT_BASE               0x0010061000
+#define A_IO_EXT_REG(r)             (A_IO_EXT_BASE + (r))
+
+#define A_IO_EXT_CFG_BASE           0x0010061000
+#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
+#define A_IO_EXT_START_ADDR_BASE    0x0010061200
+#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
+#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
+
+#define IO_EXT_REGISTER_SPACING     8
+#define A_IO_EXT_CS_BASE(cs)        (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
+#define R_IO_EXT_REG(reg,cs)        ((cs)*IO_EXT_REGISTER_SPACING + (reg))
+
+#define R_IO_EXT_CFG                0x0000
+#define R_IO_EXT_MULT_SIZE          0x0100
+#define R_IO_EXT_START_ADDR         0x0200
+#define R_IO_EXT_TIME_CFG0          0x0600
+#define R_IO_EXT_TIME_CFG1          0x0700
+
+
+#define A_IO_INTERRUPT_STATUS       0x0010061A00
+#define A_IO_INTERRUPT_DATA0        0x0010061A10
+#define A_IO_INTERRUPT_DATA1        0x0010061A18
+#define A_IO_INTERRUPT_DATA2        0x0010061A20
+#define A_IO_INTERRUPT_DATA3        0x0010061A28
+#define A_IO_INTERRUPT_ADDR0        0x0010061A30
+#define A_IO_INTERRUPT_ADDR1        0x0010061A40
+#define A_IO_INTERRUPT_PARITY       0x0010061A50
+#define A_IO_PCMCIA_CFG             0x0010061A60
+#define A_IO_PCMCIA_STATUS          0x0010061A70
+#define A_IO_DRIVE_0                0x0010061300
+#define A_IO_DRIVE_1                0x0010061308
+#define A_IO_DRIVE_2                0x0010061310
+#define A_IO_DRIVE_3                0x0010061318
+#define A_IO_DRIVE_BASE             A_IO_DRIVE_0
+#define IO_DRIVE_REGISTER_SPACING   8
+#define R_IO_DRIVE(x)               ((x)*IO_DRIVE_REGISTER_SPACING)
+#define A_IO_DRIVE(x)               (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
+
+#define R_IO_INTERRUPT_STATUS       0x0A00
+#define R_IO_INTERRUPT_DATA0        0x0A10
+#define R_IO_INTERRUPT_DATA1        0x0A18
+#define R_IO_INTERRUPT_DATA2        0x0A20
+#define R_IO_INTERRUPT_DATA3        0x0A28
+#define R_IO_INTERRUPT_ADDR0        0x0A30
+#define R_IO_INTERRUPT_ADDR1        0x0A40
+#define R_IO_INTERRUPT_PARITY       0x0A50
+#define R_IO_PCMCIA_CFG             0x0A60
+#define R_IO_PCMCIA_STATUS          0x0A70
+
+/*  ********************************************************************* 
+    * GPIO Registers
+    ********************************************************************* */
+
+#define A_GPIO_CLR_EDGE             0x0010061A80
+#define A_GPIO_INT_TYPE             0x0010061A88
+#define A_GPIO_INPUT_INVERT         0x0010061A90
+#define A_GPIO_GLITCH               0x0010061A98
+#define A_GPIO_READ                 0x0010061AA0
+#define A_GPIO_DIRECTION            0x0010061AA8
+#define A_GPIO_PIN_CLR              0x0010061AB0
+#define A_GPIO_PIN_SET              0x0010061AB8
+
+#define A_GPIO_BASE                 0x0010061A80
+
+#define R_GPIO_CLR_EDGE             0x00
+#define R_GPIO_INT_TYPE             0x08
+#define R_GPIO_INPUT_INVERT         0x10
+#define R_GPIO_GLITCH               0x18
+#define R_GPIO_READ                 0x20
+#define R_GPIO_DIRECTION            0x28
+#define R_GPIO_PIN_CLR              0x30
+#define R_GPIO_PIN_SET              0x38
+
+/*  ********************************************************************* 
+    * SMBus Registers
+    ********************************************************************* */
+
+#define A_SMB_XTRA_0                0x0010060000
+#define A_SMB_XTRA_1                0x0010060008
+#define A_SMB_FREQ_0                0x0010060010
+#define A_SMB_FREQ_1                0x0010060018
+#define A_SMB_STATUS_0              0x0010060020
+#define A_SMB_STATUS_1              0x0010060028
+#define A_SMB_CMD_0                 0x0010060030
+#define A_SMB_CMD_1                 0x0010060038
+#define A_SMB_START_0               0x0010060040
+#define A_SMB_START_1               0x0010060048
+#define A_SMB_DATA_0                0x0010060050
+#define A_SMB_DATA_1                0x0010060058
+#define A_SMB_CONTROL_0             0x0010060060
+#define A_SMB_CONTROL_1             0x0010060068
+#define A_SMB_PEC_0                 0x0010060070
+#define A_SMB_PEC_1                 0x0010060078
+
+#define A_SMB_0                     0x0010060000
+#define A_SMB_1                     0x0010060008
+#define SMB_REGISTER_SPACING        0x8
+#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
+#define A_SMB_REGISTER(idx,reg)     (A_SMB_BASE(idx)+(reg))
+
+#define R_SMB_XTRA                  0x0000000000
+#define R_SMB_FREQ                  0x0000000010
+#define R_SMB_STATUS                0x0000000020
+#define R_SMB_CMD                   0x0000000030
+#define R_SMB_START                 0x0000000040
+#define R_SMB_DATA                  0x0000000050
+#define R_SMB_CONTROL               0x0000000060
+#define R_SMB_PEC                   0x0000000070
+
+/*  ********************************************************************* 
+    * Timer Registers
+    ********************************************************************* */
+
+/*
+ * Watchdog timers
+ */
+
+#define A_SCD_WDOG_0                0x0010020050
+#define A_SCD_WDOG_1                0x0010020150
+#define SCD_WDOG_SPACING            0x100
+#define SCD_NUM_WDOGS               2
+#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
+#define A_SCD_WDOG_REGISTER(w,r)    (A_SCD_WDOG_BASE(w) + (r))
+
+#define R_SCD_WDOG_INIT             0x0000000000
+#define R_SCD_WDOG_CNT              0x0000000008
+#define R_SCD_WDOG_CFG              0x0000000010
+
+#define A_SCD_WDOG_INIT_0           0x0010020050
+#define A_SCD_WDOG_CNT_0            0x0010020058
+#define A_SCD_WDOG_CFG_0            0x0010020060
+
+#define A_SCD_WDOG_INIT_1           0x0010020150
+#define A_SCD_WDOG_CNT_1            0x0010020158
+#define A_SCD_WDOG_CFG_1            0x0010020160
+
+/*
+ * Generic timers
+ */
+
+#define A_SCD_TIMER_0               0x0010020070
+#define A_SCD_TIMER_1               0x0010020078
+#define A_SCD_TIMER_2               0x0010020170
+#define A_SCD_TIMER_3               0x0010020178
+#define SCD_NUM_TIMERS              4
+#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
+#define A_SCD_TIMER_REGISTER(w,r)   (A_SCD_TIMER_BASE(w) + (r))
+
+#define R_SCD_TIMER_INIT            0x0000000000
+#define R_SCD_TIMER_CNT             0x0000000010
+#define R_SCD_TIMER_CFG             0x0000000020
+
+#define A_SCD_TIMER_INIT_0          0x0010020070
+#define A_SCD_TIMER_CNT_0           0x0010020080
+#define A_SCD_TIMER_CFG_0           0x0010020090
+
+#define A_SCD_TIMER_INIT_1          0x0010020078
+#define A_SCD_TIMER_CNT_1           0x0010020088
+#define A_SCD_TIMER_CFG_1           0x0010020098
+
+#define A_SCD_TIMER_INIT_2          0x0010020170
+#define A_SCD_TIMER_CNT_2           0x0010020180
+#define A_SCD_TIMER_CFG_2           0x0010020190
+
+#define A_SCD_TIMER_INIT_3          0x0010020178
+#define A_SCD_TIMER_CNT_3           0x0010020188
+#define A_SCD_TIMER_CFG_3           0x0010020198
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_SCRATCH              0x0010020C10
+
+#define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
+#define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
+#define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*  ********************************************************************* 
+    * System Control Registers
+    ********************************************************************* */
+
+#define A_SCD_SYSTEM_REVISION       0x0010020000
+#define A_SCD_SYSTEM_CFG            0x0010020008
+#define A_SCD_SYSTEM_MANUF          0x0010038000
+
+/*  ********************************************************************* 
+    * System Address Trap Registers
+    ********************************************************************* */
+
+#define A_ADDR_TRAP_INDEX           0x00100200B0
+#define A_ADDR_TRAP_REG             0x00100200B8
+#define A_ADDR_TRAP_UP_0            0x0010020400
+#define A_ADDR_TRAP_UP_1            0x0010020408
+#define A_ADDR_TRAP_UP_2            0x0010020410
+#define A_ADDR_TRAP_UP_3            0x0010020418
+#define A_ADDR_TRAP_DOWN_0          0x0010020420
+#define A_ADDR_TRAP_DOWN_1          0x0010020428
+#define A_ADDR_TRAP_DOWN_2          0x0010020430
+#define A_ADDR_TRAP_DOWN_3          0x0010020438
+#define A_ADDR_TRAP_CFG_0           0x0010020440
+#define A_ADDR_TRAP_CFG_1           0x0010020448
+#define A_ADDR_TRAP_CFG_2           0x0010020450
+#define A_ADDR_TRAP_CFG_3           0x0010020458
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_ADDR_TRAP_REG_DEBUG       0x0010020460
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*  ********************************************************************* 
+    * System Interrupt Mapper Registers
+    ********************************************************************* */
+
+#define A_IMR_CPU0_BASE                 0x0010020000
+#define A_IMR_CPU1_BASE                 0x0010022000
+#define IMR_REGISTER_SPACING            0x2000
+#define IMR_REGISTER_SPACING_SHIFT      13
+
+#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
+#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
+
+#define R_IMR_INTERRUPT_DIAG            0x0010
+#define R_IMR_INTERRUPT_MASK            0x0028
+#define R_IMR_INTERRUPT_TRACE           0x0038
+#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
+#define R_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_IMR_LDT_INTERRUPT             0x0018
+#define R_IMR_LDT_INTERRUPT_CLR         0x0020
+#define R_IMR_MAILBOX_CPU               0x00c0
+#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
+#define R_IMR_MAILBOX_SET_CPU           0x00C8
+#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
+#define R_IMR_MAILBOX_CLR_CPU           0x00D0
+#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
+#define R_IMR_INTERRUPT_STATUS_COUNT    7
+#define R_IMR_INTERRUPT_MAP_BASE        0x0200
+#define R_IMR_INTERRUPT_MAP_COUNT       64
+
+/*  ********************************************************************* 
+    * System Performance Counter Registers
+    ********************************************************************* */
+
+#define A_SCD_PERF_CNT_CFG          0x00100204C0
+#define A_SCD_PERF_CNT_0            0x00100204D0
+#define A_SCD_PERF_CNT_1            0x00100204D8
+#define A_SCD_PERF_CNT_2            0x00100204E0
+#define A_SCD_PERF_CNT_3            0x00100204E8
+
+/*  ********************************************************************* 
+    * System Bus Watcher Registers
+    ********************************************************************* */
+
+#define A_SCD_BUS_ERR_STATUS        0x0010020880
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define A_BUS_ERR_DATA_0            0x00100208A0
+#define A_BUS_ERR_DATA_1            0x00100208A8
+#define A_BUS_ERR_DATA_2            0x00100208B0
+#define A_BUS_ERR_DATA_3            0x00100208B8
+#define A_BUS_L2_ERRORS             0x00100208C0
+#define A_BUS_MEM_IO_ERRORS         0x00100208C8
+
+/*  ********************************************************************* 
+    * System Debug Controller Registers
+    ********************************************************************* */
+
+#define A_SCD_JTAG_BASE             0x0010000000
+
+/*  ********************************************************************* 
+    * System Trace Buffer Registers
+    ********************************************************************* */
+
+#define A_SCD_TRACE_CFG             0x0010020A00
+#define A_SCD_TRACE_READ            0x0010020A08
+#define A_SCD_TRACE_EVENT_0         0x0010020A20
+#define A_SCD_TRACE_EVENT_1         0x0010020A28
+#define A_SCD_TRACE_EVENT_2         0x0010020A30
+#define A_SCD_TRACE_EVENT_3         0x0010020A38
+#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
+#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
+#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
+#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
+#define A_SCD_TRACE_EVENT_4         0x0010020A60
+#define A_SCD_TRACE_EVENT_5         0x0010020A68
+#define A_SCD_TRACE_EVENT_6         0x0010020A70
+#define A_SCD_TRACE_EVENT_7         0x0010020A78
+#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
+#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
+#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
+#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
+
+/*  ********************************************************************* 
+    * System Generic DMA Registers
+    ********************************************************************* */
+
+#define A_DM_0                      0x0010020B00
+#define A_DM_1                      0x0010020B20
+#define A_DM_2                      0x0010020B40
+#define A_DM_3                      0x0010020B60
+#define DM_REGISTER_SPACING         0x20
+#define DM_NUM_CHANNELS             4
+#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
+#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))
+
+#define R_DM_DSCR_BASE              0x0000000000
+#define R_DM_DSCR_COUNT             0x0000000008
+#define R_DM_CUR_DSCR_ADDR          0x0000000010
+#define R_DM_DSCR_BASE_DEBUG        0x0000000018
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_PARTIAL_0              0x0010020ba0
+#define A_DM_PARTIAL_1              0x0010020ba8
+#define A_DM_PARTIAL_2              0x0010020bb0
+#define A_DM_PARTIAL_3              0x0010020bb8
+#define DM_PARTIAL_REGISTER_SPACING 0x8
+#define A_DM_PARTIAL(idx)           (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_CRC_0                  0x0010020b80
+#define A_DM_CRC_1                  0x0010020b90
+#define DM_CRC_REGISTER_SPACING     0x10
+#define DM_CRC_NUM_CHANNELS         2
+#define A_DM_CRC_BASE(idx)          (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
+#define A_DM_CRC_REGISTER(idx,reg)  (A_DM_CRC_BASE(idx) + (reg))
+
+#define R_CRC_DEF_0                 0x00
+#define R_CTCP_DEF_0                0x08
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*  *********************************************************************
+    *  Physical Address Map
+    ********************************************************************* */
+
+#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_PHYS_GENBUS_END               _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
+#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
+#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
+#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
+#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
+#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
+#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
+
+#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define PHYS_L2CACHE_NUM_WAYS           4
+#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
+#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
+#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
+#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
+#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
new file mode 100644
index 000000000000..22e8041959e2
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -0,0 +1,582 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  SCD Constants and Macros                 File: sb1250_scd.h
+    *  
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module on the 1250.
+    *  
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _SB1250_SCD_H
+#define _SB1250_SCD_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Revision Register (Table 4-1)
+ */
+
+#define M_SYS_RESERVED              _SB_MAKEMASK(8,0)
+
+#define S_SYS_REVISION              _SB_MAKE64(8)
+#define M_SYS_REVISION              _SB_MAKEMASK(8,S_SYS_REVISION)
+#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x,S_SYS_REVISION)
+#define G_SYS_REVISION(x)           _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+#define K_SYS_REVISION_BCM1250_PASS1    1
+#define K_SYS_REVISION_BCM1250_PASS2    3
+#define K_SYS_REVISION_BCM1250_A10      11
+#define K_SYS_REVISION_BCM1250_PASS2_2  16
+#define K_SYS_REVISION_BCM1250_B2       17
+#define K_SYS_REVISION_BCM1250_PASS3    32
+#define K_SYS_REVISION_BCM1250_C1       33
+
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
+#define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
+#define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
+#define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
+#endif /* 1250 */
+
+#if SIBYTE_HDR_FEATURE_CHIP(112x)
+#define K_SYS_REVISION_BCM112x_A1       32
+#define K_SYS_REVISION_BCM112x_A2       33
+#endif /* 112x */
+
+/* XXX: discourage people from using these constants.  */
+#define S_SYS_PART                  _SB_MAKE64(16)
+#define M_SYS_PART                  _SB_MAKEMASK(16,S_SYS_PART)
+#define V_SYS_PART(x)               _SB_MAKEVALUE(x,S_SYS_PART)
+#define G_SYS_PART(x)               _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
+
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_PART_SB1250           0x1250
+#define K_SYS_PART_BCM1120          0x1121
+#define K_SYS_PART_BCM1125          0x1123
+#define K_SYS_PART_BCM1125H         0x1124
+
+/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
+#define S_SYS_SOC_TYPE              _SB_MAKE64(16)
+#define M_SYS_SOC_TYPE              _SB_MAKEMASK(4,S_SYS_SOC_TYPE)
+#define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)
+#define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)
+
+#define K_SYS_SOC_TYPE_BCM1250      0x0
+#define K_SYS_SOC_TYPE_BCM1120      0x1
+#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2         /* 1250pass2 w/ 1/4 L2.  */
+#define K_SYS_SOC_TYPE_BCM1125      0x3
+#define K_SYS_SOC_TYPE_BCM1125H     0x4
+#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
+
+/*
+ * Calculate correct SOC type given a copy of system revision register.
+ *
+ * (For the assembler version, sysrev and dest may be the same register.
+ * Also, it clobbers AT.)
+ */
+#ifdef __ASSEMBLER__
+#define SYS_SOC_TYPE(dest, sysrev)                                      \
+        .set push ;                                                     \
+        .set reorder ;                                                  \
+        dsrl    dest, sysrev, S_SYS_SOC_TYPE ;                          \
+        andi    dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);         \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;                \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f  ;              \
+        b       992f ;                                                  \
+991:    li      dest, K_SYS_SOC_TYPE_BCM1250 ;                          \
+992:                                                                    \
+        .set pop
+#else
+#define SYS_SOC_TYPE(sysrev)                                            \
+        ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT          \
+          || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)     \
+         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
+#endif
+
+#define S_SYS_WID                   _SB_MAKE64(32)
+#define M_SYS_WID                   _SB_MAKEMASK(32,S_SYS_WID)
+#define V_SYS_WID(x)                _SB_MAKEVALUE(x,S_SYS_WID)
+#define G_SYS_WID(x)                _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
+
+/* System Manufacturing Register
+* Register: SCD_SYSTEM_MANUF
+*/
+ 
+/* Wafer ID: bits 31:0 */
+#define S_SYS_WAFERID1_200        _SB_MAKE64(0)
+#define M_SYS_WAFERID1_200        _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
+#define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
+#define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
+ 
+#define S_SYS_BIN                 _SB_MAKE64(32)
+#define M_SYS_BIN                 _SB_MAKEMASK(4,S_SYS_BIN)
+#define V_SYS_BIN                 _SB_MAKEVALUE(x,S_SYS_BIN)
+#define G_SYS_BIN                 _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
+ 
+/* Wafer ID: bits 39:36 */
+#define S_SYS_WAFERID2_200        _SB_MAKE64(36)
+#define M_SYS_WAFERID2_200        _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
+#define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
+#define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
+ 
+/* Wafer ID: bits 39:0 */
+#define S_SYS_WAFERID_300         _SB_MAKE64(0)
+#define M_SYS_WAFERID_300         _SB_MAKEMASK(40,S_SYS_WAFERID_300)
+#define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
+#define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
+ 
+#define S_SYS_XPOS                _SB_MAKE64(40)
+#define M_SYS_XPOS                _SB_MAKEMASK(6,S_SYS_XPOS)
+#define V_SYS_XPOS(x)             _SB_MAKEVALUE(x,S_SYS_XPOS)
+#define G_SYS_XPOS(x)             _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
+ 
+#define S_SYS_YPOS                _SB_MAKE64(46)
+#define M_SYS_YPOS                _SB_MAKEMASK(6,S_SYS_YPOS)
+#define V_SYS_YPOS(x)             _SB_MAKEVALUE(x,S_SYS_YPOS)
+#define G_SYS_YPOS(x)             _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
+ 
+/*
+ * System Config Register (Table 4-2)
+ * Register: SCD_SYSTEM_CFG
+ */
+
+#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
+#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
+#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
+#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
+
+#define S_SYS_PLL_DIV               _SB_MAKE64(7)
+#define M_SYS_PLL_DIV               _SB_MAKEMASK(5,S_SYS_PLL_DIV)
+#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
+#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
+
+#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
+#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
+#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
+#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
+#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+
+#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
+#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
+#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
+#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
+#define K_SYS_BOOT_MODE_ROM32       0
+#define K_SYS_BOOT_MODE_ROM8        1
+#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_SYS_BOOT_MODE_SMBUS_BIG   3
+
+#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
+#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
+#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
+#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
+#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
+
+#define S_SYS_CONFIG                26
+#define M_SYS_CONFIG                _SB_MAKEMASK(6,S_SYS_CONFIG)
+#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x,S_SYS_CONFIG)
+#define G_SYS_CONFIG(x)             _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
+
+/* The following bits are writeable by JTAG only. */
+
+#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
+#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
+
+#define S_SYS_CLKCOUNT              34
+#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
+#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
+#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
+
+#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
+
+#define S_SYS_PLL_IREF              43
+#define M_SYS_PLL_IREF              _SB_MAKEMASK(2,S_SYS_PLL_IREF)
+
+#define S_SYS_PLL_VCO               45
+#define M_SYS_PLL_VCO               _SB_MAKEMASK(2,S_SYS_PLL_VCO)
+
+#define S_SYS_PLL_VREG              47
+#define M_SYS_PLL_VREG              _SB_MAKEMASK(2,S_SYS_PLL_VREG)
+
+#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
+#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
+#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
+#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
+#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
+
+/* End of bits writable by JTAG only. */
+
+#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
+#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
+
+#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
+#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
+
+#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
+#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
+#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
+
+#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
+#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*
+ * Mailbox Registers (Table 4-3)
+ * Registers: SCD_MBOX_CPU_x
+ */
+
+#define S_MBOX_INT_3                0
+#define M_MBOX_INT_3                _SB_MAKEMASK(16,S_MBOX_INT_3)
+#define S_MBOX_INT_2                16
+#define M_MBOX_INT_2                _SB_MAKEMASK(16,S_MBOX_INT_2)
+#define S_MBOX_INT_1                32
+#define M_MBOX_INT_1                _SB_MAKEMASK(16,S_MBOX_INT_1)
+#define S_MBOX_INT_0                48
+#define M_MBOX_INT_0                _SB_MAKEMASK(16,S_MBOX_INT_0)
+
+/*
+ * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ */
+
+#define V_SCD_WDOG_FREQ             1000000
+
+#define S_SCD_WDOG_INIT             0
+#define M_SCD_WDOG_INIT             _SB_MAKEMASK(23,S_SCD_WDOG_INIT)
+
+#define S_SCD_WDOG_CNT              0
+#define M_SCD_WDOG_CNT              _SB_MAKEMASK(23,S_SCD_WDOG_CNT)
+
+#define S_SCD_WDOG_ENABLE           0
+#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
+
+#define S_SCD_WDOG_RESET_TYPE       2
+#define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE)
+#define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE)
+#define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE)
+
+#define K_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_SCD_WDOG_RESET_SOFT       1
+#define K_SCD_WDOG_RESET_CPU0       3
+#define K_SCD_WDOG_RESET_CPU1       5
+#define K_SCD_WDOG_RESET_BOTH_CPUS  7
+
+/* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define S_SCD_WDOG_HAS_RESET        8
+#define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
+#endif
+
+
+/*
+ * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
+ */
+
+#define V_SCD_TIMER_FREQ            1000000
+
+#define S_SCD_TIMER_INIT            0
+#define M_SCD_TIMER_INIT            _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
+#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
+#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
+
+#define S_SCD_TIMER_CNT             0
+#define M_SCD_TIMER_CNT             _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
+#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
+#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
+
+#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
+#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
+#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
+
+/*
+ * System Performance Counters
+ */
+
+#define S_SPC_CFG_SRC0            0
+#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
+#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
+#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
+
+#define S_SPC_CFG_SRC1            8
+#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
+#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
+#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
+
+#define S_SPC_CFG_SRC2            16
+#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
+#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
+#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
+
+#define S_SPC_CFG_SRC3            24
+#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
+#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
+#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
+
+#define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
+#define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
+
+
+/*
+ * Bus Watcher
+ */
+
+#define S_SCD_BERR_TID            8
+#define M_SCD_BERR_TID            _SB_MAKEMASK(10,S_SCD_BERR_TID)
+#define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x,S_SCD_BERR_TID)
+#define G_SCD_BERR_TID(x)         _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
+
+#define S_SCD_BERR_RID            18
+#define M_SCD_BERR_RID            _SB_MAKEMASK(4,S_SCD_BERR_RID)
+#define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x,S_SCD_BERR_RID)
+#define G_SCD_BERR_RID(x)         _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
+
+#define S_SCD_BERR_DCODE          22
+#define M_SCD_BERR_DCODE          _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
+#define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
+#define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
+
+#define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
+
+
+#define S_SCD_L2ECC_CORR_D        0
+#define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
+#define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
+#define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
+
+#define S_SCD_L2ECC_BAD_D         8
+#define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
+#define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
+#define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
+
+#define S_SCD_L2ECC_CORR_T        16
+#define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
+#define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
+#define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
+
+#define S_SCD_L2ECC_BAD_T         24
+#define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
+#define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
+#define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
+
+#define S_SCD_MEM_ECC_CORR        0
+#define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
+#define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
+#define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
+
+#define S_SCD_MEM_ECC_BAD         8
+#define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
+#define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
+#define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
+
+#define S_SCD_MEM_BUSERR          16
+#define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
+#define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
+#define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
+
+
+/*
+ * Address Trap Registers
+ */
+
+#define M_ATRAP_INDEX             _SB_MAKEMASK(4,0)
+#define M_ATRAP_ADDRESS           _SB_MAKEMASK(40,0)
+
+#define S_ATRAP_CFG_CNT            0
+#define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
+#define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
+#define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
+
+#define M_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_ATRAP_CFG_AGENTID     8
+#define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
+#define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
+#define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
+
+#define K_BUS_AGENT_CPU0        0
+#define K_BUS_AGENT_CPU1        1
+#define K_BUS_AGENT_IOB0        2
+#define K_BUS_AGENT_IOB1        3
+#define K_BUS_AGENT_SCD 4
+#define K_BUS_AGENT_RESERVED    5
+#define K_BUS_AGENT_L2C 6
+#define K_BUS_AGENT_MC  7
+
+#define S_ATRAP_CFG_CATTR     12
+#define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
+#define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
+#define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
+
+#define K_ATRAP_CFG_CATTR_IGNORE        0
+#define K_ATRAP_CFG_CATTR_UNC           1
+#define K_ATRAP_CFG_CATTR_CACHEABLE     2
+#define K_ATRAP_CFG_CATTR_NONCOH        3
+#define K_ATRAP_CFG_CATTR_COHERENT      4
+#define K_ATRAP_CFG_CATTR_NOTUNC        5
+#define K_ATRAP_CFG_CATTR_NOTNONCOH     6
+#define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
+
+/*
+ * Trace Buffer Config register
+ */
+
+#define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
+#define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
+#define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
+#define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
+#define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
+#define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
+#define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
+#define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#define S_SCD_TRACE_CFG_CUR_ADDR        10
+#define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
+#define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
+#define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
+
+/*
+ * Trace Event registers
+ */
+
+#define S_SCD_TREVT_ADDR_MATCH          0
+#define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
+#define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
+#define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
+
+#define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
+#define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
+#define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
+#define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
+#define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
+#define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
+#define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
+
+#define S_SCD_TREVT_REQID               12
+#define M_SCD_TREVT_REQID               _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
+#define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
+#define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
+
+#define S_SCD_TREVT_RESPID              16
+#define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
+#define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
+#define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
+
+#define S_SCD_TREVT_DATAID              20
+#define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
+#define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
+#define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
+
+#define S_SCD_TREVT_COUNT               24
+#define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
+#define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
+#define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
+
+/*
+ * Trace Sequence registers
+ */
+
+#define S_SCD_TRSEQ_EVENT4              0
+#define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
+#define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
+#define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
+
+#define S_SCD_TRSEQ_EVENT3              4
+#define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
+#define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
+#define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
+
+#define S_SCD_TRSEQ_EVENT2              8
+#define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
+#define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
+#define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
+
+#define S_SCD_TRSEQ_EVENT1              12
+#define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
+#define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
+#define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
+
+#define K_SCD_TRSEQ_E0                  0
+#define K_SCD_TRSEQ_E1                  1
+#define K_SCD_TRSEQ_E2                  2
+#define K_SCD_TRSEQ_E3                  3
+#define K_SCD_TRSEQ_E0_E1               4
+#define K_SCD_TRSEQ_E1_E2               5
+#define K_SCD_TRSEQ_E2_E3               6
+#define K_SCD_TRSEQ_E0_E1_E2            7
+#define K_SCD_TRSEQ_E0_E1_E2_E3         8
+#define K_SCD_TRSEQ_E0E1                9
+#define K_SCD_TRSEQ_E0E1E2              10
+#define K_SCD_TRSEQ_E0E1E2E3            11
+#define K_SCD_TRSEQ_E0E1_E2             12
+#define K_SCD_TRSEQ_E0E1_E2E3           13
+#define K_SCD_TRSEQ_E0E1_E2_E3          14
+#define K_SCD_TRSEQ_IGNORED             15
+
+#define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
+
+#define S_SCD_TRSEQ_FUNCTION            16
+#define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
+#define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
+#define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
+
+#define K_SCD_TRSEQ_FUNC_NOP            0
+#define K_SCD_TRSEQ_FUNC_START          1
+#define K_SCD_TRSEQ_FUNC_STOP           2
+#define K_SCD_TRSEQ_FUNC_FREEZE         3
+
+#define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
+#define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
+#define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
+#define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
+
+#define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
+#define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
+#define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
+#define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
+#define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
new file mode 100644
index 000000000000..287cbfe9efa2
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -0,0 +1,170 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  SMBUS Constants                          File: sb1250_smbus.h
+    *  
+    *  This module contains constants and macros useful for 
+    *  manipulating the SB1250's SMbus devices.
+    *  
+    *  SB1250 specification level:  01/02/2002
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SMBUS_H
+#define _SB1250_SMBUS_H
+
+#include "sb1250_defs.h"
+
+/*
+ * SMBus Clock Frequency Register (Table 14-2)
+ */
+
+#define S_SMB_FREQ_DIV              0
+#define M_SMB_FREQ_DIV              _SB_MAKEMASK(13,S_SMB_FREQ_DIV)
+#define V_SMB_FREQ_DIV(x)           _SB_MAKEVALUE(x,S_SMB_FREQ_DIV)
+
+#define K_SMB_FREQ_400KHZ           0x1F
+#define K_SMB_FREQ_100KHZ           0x7D
+
+#define S_SMB_CMD                   0
+#define M_SMB_CMD                   _SB_MAKEMASK(8,S_SMB_CMD)
+#define V_SMB_CMD(x)                _SB_MAKEVALUE(x,S_SMB_CMD)
+
+/*
+ * SMBus control register (Table 14-4)
+ */
+
+#define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
+#define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
+#define M_SMB_DATA_OUT              _SB_MAKEMASK1(4)
+#define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
+#define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
+#define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
+#define M_SMB_DIRECT_ENABLE         _SB_MAKEMASK1(7)
+
+/*
+ * SMBus status registers (Table 14-5)
+ */
+
+#define M_SMB_BUSY                  _SB_MAKEMASK1(0)
+#define M_SMB_ERROR                 _SB_MAKEMASK1(1)
+#define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
+#define M_SMB_REF                   _SB_MAKEMASK1(6)
+#define M_SMB_DATA_IN               _SB_MAKEMASK1(7)
+
+/*
+ * SMBus Start/Command registers (Table 14-9)
+ */
+
+#define S_SMB_ADDR                  0
+#define M_SMB_ADDR                  _SB_MAKEMASK(7,S_SMB_ADDR)
+#define V_SMB_ADDR(x)               _SB_MAKEVALUE(x,S_SMB_ADDR)
+#define G_SMB_ADDR(x)               _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR)
+
+#define M_SMB_QDATA                 _SB_MAKEMASK1(7)
+
+#define S_SMB_TT                    8
+#define M_SMB_TT                    _SB_MAKEMASK(3,S_SMB_TT)
+#define V_SMB_TT(x)                 _SB_MAKEVALUE(x,S_SMB_TT)
+#define G_SMB_TT(x)                 _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT)
+
+#define K_SMB_TT_WR1BYTE            0
+#define K_SMB_TT_WR2BYTE            1
+#define K_SMB_TT_WR3BYTE            2
+#define K_SMB_TT_CMD_RD1BYTE        3
+#define K_SMB_TT_CMD_RD2BYTE        4
+#define K_SMB_TT_RD1BYTE            5
+#define K_SMB_TT_QUICKCMD           6
+#define K_SMB_TT_EEPROMREAD         7
+
+#define V_SMB_TT_WR1BYTE            V_SMB_TT(K_SMB_TT_WR1BYTE)
+#define V_SMB_TT_WR2BYTE            V_SMB_TT(K_SMB_TT_WR2BYTE)
+#define V_SMB_TT_WR3BYTE            V_SMB_TT(K_SMB_TT_WR3BYTE)
+#define V_SMB_TT_CMD_RD1BYTE        V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
+#define V_SMB_TT_CMD_RD2BYTE        V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
+#define V_SMB_TT_RD1BYTE            V_SMB_TT(K_SMB_TT_RD1BYTE)
+#define V_SMB_TT_QUICKCMD           V_SMB_TT(K_SMB_TT_QUICKCMD)
+#define V_SMB_TT_EEPROMREAD         V_SMB_TT(K_SMB_TT_EEPROMREAD)
+
+#define M_SMB_PEC                   _SB_MAKEMASK1(15)
+
+/*
+ * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
+ */
+
+#define S_SMB_LB                    0
+#define M_SMB_LB                    _SB_MAKEMASK(8,S_SMB_LB)
+#define V_SMB_LB(x)                 _SB_MAKEVALUE(x,S_SMB_LB)
+
+#define S_SMB_MB                    8
+#define M_SMB_MB                    _SB_MAKEMASK(8,S_SMB_MB)
+#define V_SMB_MB(x)                 _SB_MAKEVALUE(x,S_SMB_MB)
+
+
+/*
+ * SMBus Packet Error Check register (Table 14-8)
+ */
+
+#define S_SPEC_PEC                  0
+#define M_SPEC_PEC                  _SB_MAKEMASK(8,S_SPEC_PEC)
+#define V_SPEC_MB(x)                _SB_MAKEVALUE(x,S_SPEC_PEC)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+
+#define S_SMB_CMDH                  8
+#define M_SMB_CMDH                  _SB_MAKEMASK(8,S_SMBH_CMD)
+#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x,S_SMBH_CMD)
+
+#define M_SMB_EXTEND                _SB_MAKEMASK1(14)
+
+#define M_SMB_DIR                   _SB_MAKEMASK1(13)
+
+#define S_SMB_DFMT                  8
+#define M_SMB_DFMT                  _SB_MAKEMASK(3,S_SMB_DFMT)
+#define V_SMB_DFMT(x)               _SB_MAKEVALUE(x,S_SMB_DFMT)
+#define G_SMB_DFMT(x)               _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT)
+
+#define K_SMB_DFMT_1BYTE            0
+#define K_SMB_DFMT_2BYTE            1
+#define K_SMB_DFMT_3BYTE            2
+#define K_SMB_DFMT_4BYTE            3
+#define K_SMB_DFMT_NODATA           4
+#define K_SMB_DFMT_CMD4BYTE         5
+#define K_SMB_DFMT_CMD5BYTE         6
+#define K_SMB_DFMT_RESERVED         7
+
+#define V_SMB_DFMT_1BYTE            V_SMB_DFMT(K_SMB_DFMT_1BYTE)
+#define V_SMB_DFMT_2BYTE            V_SMB_DFMT(K_SMB_DFMT_2BYTE)
+#define V_SMB_DFMT_3BYTE            V_SMB_DFMT(K_SMB_DFMT_3BYTE)
+#define V_SMB_DFMT_4BYTE            V_SMB_DFMT(K_SMB_DFMT_4BYTE)
+#define V_SMB_DFMT_NODATA           V_SMB_DFMT(K_SMB_DFMT_NODATA)
+#define V_SMB_DFMT_CMD4BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
+#define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
+#define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
+
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
new file mode 100644
index 000000000000..8d5e8edd3c4b
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -0,0 +1,148 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Synchronous Serial Constants              File: sb1250_syncser.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's Synchronous Serial
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SYNCSER_H
+#define _SB1250_SYNCSER_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Serial Mode Configuration Register
+ */
+
+#define M_SYNCSER_CRC_MODE                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_MSB_FIRST                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_FLAG_NUM                 2
+#define M_SYNCSER_FLAG_NUM                 _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM)
+#define V_SYNCSER_FLAG_NUM                 _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM)
+
+#define M_SYNCSER_FLAG_EN                  _SB_MAKEMASK1(6)
+#define M_SYNCSER_HDLC_EN                  _SB_MAKEMASK1(7)
+#define M_SYNCSER_LOOP_MODE                _SB_MAKEMASK1(8)
+#define M_SYNCSER_LOOPBACK                 _SB_MAKEMASK1(9)
+
+/*
+ * Serial Clock Source and Line Interface Mode Register
+ */
+
+#define M_SYNCSER_RXCLK_INV                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RXCLK_EXT                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_RXSYNC_DLY               2
+#define M_SYNCSER_RXSYNC_DLY               _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY)
+#define V_SYNCSER_RXSYNC_DLY(x)            _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY)
+
+#define M_SYNCSER_RXSYNC_LOW               _SB_MAKEMASK1(4)
+#define M_SYNCSER_RXSTRB_LOW               _SB_MAKEMASK1(5)
+
+#define M_SYNCSER_RXSYNC_EDGE              _SB_MAKEMASK1(6)
+#define M_SYNCSER_RXSYNC_INT               _SB_MAKEMASK1(7)
+
+#define M_SYNCSER_TXCLK_INV                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TXCLK_EXT                _SB_MAKEMASK1(9)
+
+#define S_SYNCSER_TXSYNC_DLY               10
+#define M_SYNCSER_TXSYNC_DLY               _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY)
+#define V_SYNCSER_TXSYNC_DLY(x)            _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY)
+
+#define M_SYNCSER_TXSYNC_LOW               _SB_MAKEMASK1(12)
+#define M_SYNCSER_TXSTRB_LOW               _SB_MAKEMASK1(13)
+
+#define M_SYNCSER_TXSYNC_EDGE              _SB_MAKEMASK1(14)
+#define M_SYNCSER_TXSYNC_INT               _SB_MAKEMASK1(15)
+
+/*
+ * Serial Command Register
+ */
+
+#define M_SYNCSER_CMD_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_CMD_TX_EN                _SB_MAKEMASK1(1)
+#define M_SYNCSER_CMD_RX_RESET             _SB_MAKEMASK1(2)
+#define M_SYNCSER_CMD_TX_RESET             _SB_MAKEMASK1(3)
+#define M_SYNCSER_CMD_TX_PAUSE             _SB_MAKEMASK1(5)
+
+/*
+ * Serial DMA Enable Register
+ */
+
+#define M_SYNCSER_DMA_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_DMA_TX_EN                _SB_MAKEMASK1(4)
+
+/*
+ * Serial Status Register
+ */
+
+#define M_SYNCSER_RX_CRCERR                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RX_ABORT                 _SB_MAKEMASK1(1)
+#define M_SYNCSER_RX_OCTET                 _SB_MAKEMASK1(2)
+#define M_SYNCSER_RX_LONGFRM               _SB_MAKEMASK1(3)
+#define M_SYNCSER_RX_SHORTFRM              _SB_MAKEMASK1(4)
+#define M_SYNCSER_RX_OVERRUN               _SB_MAKEMASK1(5)
+#define M_SYNCSER_RX_SYNC_ERR              _SB_MAKEMASK1(6)
+#define M_SYNCSER_TX_CRCERR                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TX_UNDERRUN              _SB_MAKEMASK1(9)
+#define M_SYNCSER_TX_SYNC_ERR              _SB_MAKEMASK1(10)
+#define M_SYNCSER_TX_PAUSE_COMPLETE        _SB_MAKEMASK1(11)
+#define M_SYNCSER_RX_EOP_COUNT             _SB_MAKEMASK1(16)
+#define M_SYNCSER_RX_EOP_TIMER             _SB_MAKEMASK1(17)
+#define M_SYNCSER_RX_EOP_SEEN              _SB_MAKEMASK1(18)
+#define M_SYNCSER_RX_HWM                   _SB_MAKEMASK1(19)
+#define M_SYNCSER_RX_LWM                   _SB_MAKEMASK1(20)
+#define M_SYNCSER_RX_DSCR                  _SB_MAKEMASK1(21)
+#define M_SYNCSER_RX_DERR                  _SB_MAKEMASK1(22)
+#define M_SYNCSER_TX_EOP_COUNT             _SB_MAKEMASK1(24)
+#define M_SYNCSER_TX_EOP_TIMER             _SB_MAKEMASK1(25)
+#define M_SYNCSER_TX_EOP_SEEN              _SB_MAKEMASK1(26)
+#define M_SYNCSER_TX_HWM                   _SB_MAKEMASK1(27)
+#define M_SYNCSER_TX_LWM                   _SB_MAKEMASK1(28)
+#define M_SYNCSER_TX_DSCR                  _SB_MAKEMASK1(29)
+#define M_SYNCSER_TX_DERR                  _SB_MAKEMASK1(30)
+#define M_SYNCSER_TX_DZERO                 _SB_MAKEMASK1(31)
+
+/*
+ * Sequencer Table Entry format
+ */
+
+#define M_SYNCSER_SEQ_LAST                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_SEQ_BYTE                 _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_SEQ_COUNT                2
+#define M_SYNCSER_SEQ_COUNT                _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT)
+#define V_SYNCSER_SEQ_COUNT(x)             _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT)
+
+#define M_SYNCSER_SEQ_ENABLE               _SB_MAKEMASK1(6)
+#define M_SYNCSER_SEQ_STROBE               _SB_MAKEMASK1(7)
+
+#endif
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
new file mode 100644
index 000000000000..7655d6945cca
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -0,0 +1,354 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *  
+    *  UART Constants                           File: sb1250_uart.h
+    *  
+    *  This module contains constants and macros useful for 
+    *  manipulating the SB1250's UARTs
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *  
+    *  Author:  Mitch Lichtenberg
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This program is free software; you can redistribute it and/or 
+    *  modify it under the terms of the GNU General Public License as 
+    *  published by the Free Software Foundation; either version 2 of 
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_UART_H
+#define _SB1250_UART_H
+
+#include "sb1250_defs.h"
+
+/* ********************************************************************** 
+   * DUART Registers
+   ********************************************************************** */
+
+/*
+ * DUART Mode Register #1 (Table 10-3)
+ * Register: DUART_MODE_REG_1_A
+ * Register: DUART_MODE_REG_1_B
+ */
+
+#define S_DUART_BITS_PER_CHAR       0
+#define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR)
+#define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR)
+
+#define K_DUART_BITS_PER_CHAR_RSV0  0
+#define K_DUART_BITS_PER_CHAR_RSV1  1
+#define K_DUART_BITS_PER_CHAR_7     2
+#define K_DUART_BITS_PER_CHAR_8     3
+
+#define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
+#define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
+#define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
+#define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
+
+
+#define M_DUART_PARITY_TYPE_EVEN    0x00
+#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
+
+#define S_DUART_PARITY_MODE          3
+#define M_DUART_PARITY_MODE         _SB_MAKEMASK(2,S_DUART_PARITY_MODE)
+#define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x,S_DUART_PARITY_MODE)
+
+#define K_DUART_PARITY_MODE_ADD       0
+#define K_DUART_PARITY_MODE_ADD_FIXED 1
+#define K_DUART_PARITY_MODE_NONE      2
+
+#define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
+#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
+#define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
+
+#define M_DUART_ERR_MODE            _SB_MAKEMASK1(5)    /* must be zero */
+
+#define M_DUART_RX_IRQ_SEL_RXRDY    0
+#define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
+
+#define M_DUART_RX_RTS_ENA          _SB_MAKEMASK1(7)
+
+/*
+ * DUART Mode Register #2 (Table 10-4)
+ * Register: DUART_MODE_REG_2_A
+ * Register: DUART_MODE_REG_2_B
+ */
+
+#define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3,0)   /* ignored */
+
+#define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
+#define M_DUART_STOP_BIT_LEN_1      0
+
+#define M_DUART_TX_CTS_ENA          _SB_MAKEMASK1(4)
+
+
+#define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
+
+#define S_DUART_CHAN_MODE           6
+#define M_DUART_CHAN_MODE           _SB_MAKEMASK(2,S_DUART_CHAN_MODE)
+#define V_DUART_CHAN_MODE(x)        _SB_MAKEVALUE(x,S_DUART_CHAN_MODE)
+
+#define K_DUART_CHAN_MODE_NORMAL    0
+#define K_DUART_CHAN_MODE_LCL_LOOP  2
+#define K_DUART_CHAN_MODE_REM_LOOP  3
+
+#define V_DUART_CHAN_MODE_NORMAL    V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
+#define V_DUART_CHAN_MODE_LCL_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
+#define V_DUART_CHAN_MODE_REM_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
+
+/*
+ * DUART Command Register (Table 10-5)
+ * Register: DUART_CMD_A
+ * Register: DUART_CMD_B
+ */
+
+#define M_DUART_RX_EN               _SB_MAKEMASK1(0)
+#define M_DUART_RX_DIS              _SB_MAKEMASK1(1)
+#define M_DUART_TX_EN               _SB_MAKEMASK1(2)
+#define M_DUART_TX_DIS              _SB_MAKEMASK1(3)
+
+#define S_DUART_MISC_CMD            4
+#define M_DUART_MISC_CMD            _SB_MAKEMASK(3,S_DUART_MISC_CMD)
+#define V_DUART_MISC_CMD(x)         _SB_MAKEVALUE(x,S_DUART_MISC_CMD)
+
+#define K_DUART_MISC_CMD_NOACTION0       0
+#define K_DUART_MISC_CMD_NOACTION1       1
+#define K_DUART_MISC_CMD_RESET_RX        2
+#define K_DUART_MISC_CMD_RESET_TX        3
+#define K_DUART_MISC_CMD_NOACTION4       4
+#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
+#define K_DUART_MISC_CMD_START_BREAK     6
+#define K_DUART_MISC_CMD_STOP_BREAK      7
+
+#define V_DUART_MISC_CMD_NOACTION0       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
+#define V_DUART_MISC_CMD_NOACTION1       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
+#define V_DUART_MISC_CMD_RESET_RX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
+#define V_DUART_MISC_CMD_RESET_TX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
+#define V_DUART_MISC_CMD_NOACTION4       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
+#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
+#define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
+#define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
+
+#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7) 
+
+/*
+ * DUART Status Register (Table 10-6)
+ * Register: DUART_STATUS_A
+ * Register: DUART_STATUS_B
+ * READ-ONLY
+ */
+
+#define M_DUART_RX_RDY              _SB_MAKEMASK1(0)
+#define M_DUART_RX_FFUL             _SB_MAKEMASK1(1)
+#define M_DUART_TX_RDY              _SB_MAKEMASK1(2)
+#define M_DUART_TX_EMT              _SB_MAKEMASK1(3)
+#define M_DUART_OVRUN_ERR           _SB_MAKEMASK1(4)
+#define M_DUART_PARITY_ERR          _SB_MAKEMASK1(5)
+#define M_DUART_FRM_ERR             _SB_MAKEMASK1(6)
+#define M_DUART_RCVD_BRK            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Baud Rate Register (Table 10-7)
+ * Register: DUART_CLK_SEL_A 
+ * Register: DUART_CLK_SEL_B
+ */
+
+#define M_DUART_CLK_COUNTER         _SB_MAKEMASK(12,0)
+#define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
+
+/*
+ * DUART Data Registers (Table 10-8 and 10-9)
+ * Register: DUART_RX_HOLD_A
+ * Register: DUART_RX_HOLD_B
+ * Register: DUART_TX_HOLD_A
+ * Register: DUART_TX_HOLD_B
+ */
+
+#define M_DUART_RX_DATA             _SB_MAKEMASK(8,0)
+#define M_DUART_TX_DATA             _SB_MAKEMASK(8,0)
+
+/*
+ * DUART Input Port Register (Table 10-10)
+ * Register: DUART_IN_PORT
+ */
+
+#define M_DUART_IN_PIN0_VAL         _SB_MAKEMASK1(0)
+#define M_DUART_IN_PIN1_VAL         _SB_MAKEMASK1(1)
+#define M_DUART_IN_PIN2_VAL         _SB_MAKEMASK1(2)
+#define M_DUART_IN_PIN3_VAL         _SB_MAKEMASK1(3)
+#define M_DUART_IN_PIN4_VAL         _SB_MAKEMASK1(4)
+#define M_DUART_IN_PIN5_VAL         _SB_MAKEMASK1(5)
+#define M_DUART_RIN0_PIN            _SB_MAKEMASK1(6)
+#define M_DUART_RIN1_PIN            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
+ * Register: DUART_INPORT_CHNG
+ */
+
+#define S_DUART_IN_PIN_VAL          0
+#define M_DUART_IN_PIN_VAL          _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL)
+
+#define S_DUART_IN_PIN_CHNG         4
+#define M_DUART_IN_PIN_CHNG         _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG)
+
+
+/*
+ * DUART Output port control register (Table 10-14)
+ * Register: DUART_OPCR
+ */
+
+#define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
+#define M_DUART_OPC2_SEL            _SB_MAKEMASK1(1)
+#define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
+#define M_DUART_OPC3_SEL            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4,4)  /* must be zero */
+
+/*
+ * DUART Aux Control Register (Table 10-15)
+ * Register: DUART_AUX_CTRL
+ */
+
+#define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
+#define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
+#define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
+#define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4,4)
+
+#define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
+
+/*
+ * DUART Interrupt Status Register (Table 10-16)
+ * Register: DUART_ISR
+ */
+
+#define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
+#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(1)
+#define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_ISR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_ISR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_ISR_IN_B            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Channel A Interrupt Status Register (Table 10-17)
+ * DUART Channel B Interrupt Status Register (Table 10-18)
+ * Register: DUART_ISR_A
+ * Register: DUART_ISR_B
+ */
+
+#define M_DUART_ISR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_ISR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_ISR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4,4)
+
+/*
+ * DUART Interrupt Mask Register (Table 10-19)
+ * Register: DUART_IMR
+ */
+
+#define M_DUART_IMR_TX_A            _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX_A            _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL_A           _SB_MAKEMASK(4,0)
+
+#define M_DUART_IMR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_IMR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_IMR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_IMR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_IMR_ALL_B           _SB_MAKEMASK(4,4)
+
+/*
+ * DUART Channel A Interrupt Mask Register (Table 10-20)
+ * DUART Channel B Interrupt Mask Register (Table 10-21)
+ * Register: DUART_IMR_A
+ * Register: DUART_IMR_B
+ */
+
+#define M_DUART_IMR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL             _SB_MAKEMASK(4,0)
+#define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4,4)
+
+
+/*
+ * DUART Output Port Set Register (Table 10-22)
+ * Register: DUART_SET_OPR
+ */
+
+#define M_DUART_SET_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_SET_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_SET_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_SET_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4,4)
+
+/*
+ * DUART Output Port Clear Register (Table 10-23)
+ * Register: DUART_CLEAR_OPR
+ */
+
+#define M_DUART_CLR_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_CLR_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_CLR_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_CLR_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4,4)
+
+/*
+ * DUART Output Port RTS Register (Table 10-24)
+ * Register: DUART_OUT_PORT
+ */
+
+#define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
+#define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
+#define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
+#define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
+#define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4,4)
+
+#define M_DUART_OUT_PIN_SET(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
+#define M_DUART_OUT_PIN_CLR(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/* 
+ * Full Interrupt Control Register
+ */
+
+#define S_DUART_SIG_FULL           _SB_MAKE64(0)
+#define M_DUART_SIG_FULL           _SB_MAKEMASK(4,S_DUART_SIG_FULL)
+#define V_DUART_SIG_FULL(x)        _SB_MAKEVALUE(x,S_DUART_SIG_FULL)
+#define G_DUART_SIG_FULL(x)        _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL)
+
+#define S_DUART_INT_TIME           _SB_MAKE64(4)
+#define M_DUART_INT_TIME           _SB_MAKEMASK(4,S_DUART_INT_TIME)
+#define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x,S_DUART_INT_TIME)
+#define G_DUART_INT_TIME(x)        _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/* ********************************************************************** */
+
+
+#endif
diff --git a/include/asm-mips/sibyte/sentosa.h b/include/asm-mips/sibyte/sentosa.h
new file mode 100644
index 000000000000..824605847af4
--- /dev/null
+++ b/include/asm-mips/sibyte/sentosa.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_SENTOSA_H
+#define __ASM_SIBYTE_SENTOSA_H
+
+#include <linux/config.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SENTOSA
+#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
+#endif
+#ifdef CONFIG_SIBYTE_RHONE
+#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
+#endif
+
+/* Generic bus chip selects */
+#ifdef CONFIG_SIBYTE_RHONE
+#define LEDS_CS         6
+#define LEDS_PHYS       0x1d0a0000
+#endif
+
+/* GPIOs */
+#define K_GPIO_DBG_LED  0
+
+#endif /* __ASM_SIBYTE_SENTOSA_H */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
new file mode 100644
index 000000000000..97fa0494c30c
--- /dev/null
+++ b/include/asm-mips/sibyte/swarm.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_SWARM_H
+#define __ASM_SIBYTE_SWARM_H
+
+#include <linux/config.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SWARM
+#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+#ifdef CONFIG_SIBYTE_PTSWARM
+#define SIBYTE_BOARD_NAME "PTSWARM"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
+#endif
+#ifdef CONFIG_SIBYTE_LITTLESUR
+#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_DEFAULT_CONSOLE "cfe0"
+#endif
+#ifdef CONFIG_SIBYTE_CRHONE
+#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+#ifdef CONFIG_SIBYTE_CRHINE
+#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_SWARM_H */
diff --git a/include/asm-mips/sibyte/trace_prof.h b/include/asm-mips/sibyte/trace_prof.h
new file mode 100644
index 000000000000..557792075e9a
--- /dev/null
+++ b/include/asm-mips/sibyte/trace_prof.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_SIBYTE_TRACE_PROF_H
+#define __ASM_SIBYTE_TRACE_PROF_H
+
+#undef DBG
+#if SBPROF_TB_DEBUG
+#define DBG(a) a
+#else
+#define DBG(a)
+#endif
+
+#define SBPROF_TB_MAJOR 240
+#define DEVNAME "bcm1250_tbprof"
+
+typedef u_int64_t tb_sample_t[6*256];
+
+struct sbprof_tb {
+        int          open;
+        tb_sample_t *sbprof_tbbuf;
+        int          next_tb_sample;
+
+        volatile int tb_enable;
+        volatile int tb_armed;
+
+        wait_queue_head_t tb_sync;
+        wait_queue_head_t tb_read;
+};
+
+#define MAX_SAMPLE_BYTES (24*1024*1024)
+#define MAX_TBSAMPLE_BYTES (12*1024*1024)
+
+#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
+#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
+#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
+
+/* IOCTLs */
+#define SBPROF_ZBSTART          _IOW('s', 0, int)
+#define SBPROF_ZBSTOP           _IOW('s', 1, int)
+#define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
+
+/***************************************************************************
+ * Routines for gathering ZBbus profiles using trace buffer
+ ***************************************************************************/
+
+/* Requires: Already called zclk_timer_init with a value that won't
+             saturate 40 bits.  No subsequent use of SCD performance counters
+             or trace buffer.
+   Effect:   Starts gathering random ZBbus profiles using trace buffer. */
+extern int sbprof_zbprof_start(struct file *filp);
+
+/* Effect: Stops collection of ZBbus profiles */
+extern int sbprof_zbprof_stop(void);
+
+
+/***************************************************************************
+ * Routines for using 40-bit SCD cycle counter
+ *
+ * Client responsible for either handling interrupts or making sure
+ * the cycles counter never saturates, e.g., by doing
+ * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
+ ***************************************************************************/
+
+/* Configures SCD counter 0 to count ZCLKs starting from val;
+   Configures SCD counters1,2,3 to count nothing.
+   Must not be called while gathering ZBbus profiles.
+
+unsigned long long val; */
+#define zclk_timer_init(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "sd   %0, 0x10($8);"   /* write val to counter0 */ \
+                        "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
+                        ".set pop" \
+                        : /* no outputs */ \
+                                                     /* enable, counter0 */ \
+                        : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
+                        : /* modifies */ "$8" )
+
+
+/* Reads SCD counter 0 and puts result in value
+   unsigned long long val; */
+#define zclk_get(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "ld   %0, 0x10($8);"   /* write val to counter0 */ \
+                        ".set pop" \
+                        : /* outputs */ "=r"(val) \
+                        : /* inputs */ \
+                        : /* modifies */ "$8" )
+
+#endif /* __ASM_SIBYTE_TRACE_PROF_H */
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
new file mode 100644
index 000000000000..18939e84b6f2
--- /dev/null
+++ b/include/asm-mips/sigcontext.h
@@ -0,0 +1,93 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGCONTEXT_H
+#define _ASM_SIGCONTEXT_H
+
+#include <asm/sgidefs.h>
+                                                                                
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ */
+struct sigcontext {
+        unsigned int            sc_regmask;     /* Unused */
+        unsigned int            sc_status;
+        unsigned long long      sc_pc;
+        unsigned long long      sc_regs[32];
+        unsigned long long      sc_fpregs[32];
+        unsigned int            sc_ownedfp;     /* Unused */
+        unsigned int            sc_fpc_csr;
+        unsigned int            sc_fpc_eir;     /* Unused */
+        unsigned int            sc_used_math;
+        unsigned int            sc_ssflags;     /* Unused */
+        unsigned long long      sc_mdhi;
+        unsigned long long      sc_mdlo;
+
+        unsigned int            sc_cause;       /* Unused */
+        unsigned int            sc_badvaddr;    /* Unused */
+
+        unsigned long           sc_sigset[4];   /* kernel's sigset_t */
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+                                                                                
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ *
+ * Warning: this structure illdefined with sc_badvaddr being just an unsigned
+ * int so it was changed to unsigned long in 2.6.0-test1.  This may break
+ * binary compatibility - no prisoners.
+ */
+struct sigcontext {
+        unsigned long   sc_regs[32];
+        unsigned long   sc_fpregs[32];
+        unsigned long   sc_mdhi;
+        unsigned long   sc_mdlo;
+        unsigned long   sc_pc;
+        unsigned long   sc_badvaddr;
+        unsigned int    sc_status;
+        unsigned int    sc_fpc_csr;
+        unsigned int    sc_fpc_eir;
+        unsigned int    sc_used_math;
+        unsigned int    sc_cause;
+};
+
+#ifdef __KERNEL__
+
+#include <linux/posix_types.h>
+
+struct sigcontext32 {
+        __u32   sc_regmask;             /* Unused */
+        __u32   sc_status;
+        __u64   sc_pc;
+        __u64   sc_regs[32];
+        __u64   sc_fpregs[32];
+        __u32   sc_ownedfp;             /* Unused */
+        __u32   sc_fpc_csr;
+        __u32   sc_fpc_eir;             /* Unused */
+        __u32   sc_used_math;
+        __u32   sc_ssflags;             /* Unused */
+        __u64   sc_mdhi;
+        __u64   sc_mdlo;
+
+        __u32   sc_cause;               /* Unused */
+        __u32   sc_badvaddr;            /* Unused */
+
+        __u32   sc_sigset[4];           /* kernel's sigset_t */
+};
+#endif /* __KERNEL__ */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_SIGCONTEXT_H */
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
new file mode 100644
index 000000000000..8ddd3c99bcf7
--- /dev/null
+++ b/include/asm-mips/siginfo.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGINFO_H
+#define _ASM_SIGINFO_H
+
+#include <linux/config.h>
+
+#define SIGEV_HEAD_SIZE (sizeof(long) + 2*sizeof(int))
+#define SIGEV_PAD_SIZE  ((SIGEV_MAX_SIZE-SIGEV_HEAD_SIZE) / sizeof(int))
+#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
+
+#define HAVE_ARCH_SIGINFO_T
+
+/*
+ * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked
+ * by design ...
+ */
+#define HAVE_ARCH_COPY_SIGINFO
+struct siginfo;
+
+/*
+ * Careful to keep union _sifields from shifting ...
+ */
+#ifdef CONFIG_MIPS32
+#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
+#endif
+#ifdef CONFIG_MIPS64
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#endif
+
+#include <asm-generic/siginfo.h>
+
+typedef struct siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+        int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3];
+
+        union {
+                int _pad[SI_PAD_SIZE];
+
+                /* kill() */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
+                        sigval_t _sigval;       /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        int _status;            /* exit code */
+                        clock_t _utime;
+                        clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        clock_t _utime;
+                        int _status;            /* exit code */
+                        clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        void __user *_addr; /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+                        int _trapno;    /* TRAP # which caused the signal */
+#endif
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} siginfo_t;
+
+/*
+ * si_code values
+ * Again these have been choosen to be IRIX compatible.
+ */
+#undef SI_ASYNCIO
+#undef SI_TIMER
+#undef SI_MESGQ
+#define SI_ASYNCIO      -2      /* sent by AIO completion */
+#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */
+#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */
+
+#ifdef __KERNEL__
+
+/*
+ * Duplicated here because of <asm-generic/siginfo.h> braindamage ...
+ */
+#include <linux/string.h>
+
+static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
+{
+        if (from->si_code < 0)
+                memcpy(to, from, sizeof(*to));
+        else
+                /* _sigchld is currently the largest know union member */
+                memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
+}
+
+#endif
+
+#endif /* _ASM_SIGINFO_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
new file mode 100644
index 000000000000..994987db61be
--- /dev/null
+++ b/include/asm-mips/signal.h
@@ -0,0 +1,178 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGNAL_H
+#define _ASM_SIGNAL_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+#define _NSIG           128
+#define _NSIG_BPW       (sizeof(unsigned long) * 8)
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+#define SIGHUP           1      /* Hangup (POSIX).  */
+#define SIGINT           2      /* Interrupt (ANSI).  */
+#define SIGQUIT          3      /* Quit (POSIX).  */
+#define SIGILL           4      /* Illegal instruction (ANSI).  */
+#define SIGTRAP          5      /* Trace trap (POSIX).  */
+#define SIGIOT           6      /* IOT trap (4.2 BSD).  */
+#define SIGABRT          SIGIOT /* Abort (ANSI).  */
+#define SIGEMT           7
+#define SIGFPE           8      /* Floating-point exception (ANSI).  */
+#define SIGKILL          9      /* Kill, unblockable (POSIX).  */
+#define SIGBUS          10      /* BUS error (4.2 BSD).  */
+#define SIGSEGV         11      /* Segmentation violation (ANSI).  */
+#define SIGSYS          12
+#define SIGPIPE         13      /* Broken pipe (POSIX).  */
+#define SIGALRM         14      /* Alarm clock (POSIX).  */
+#define SIGTERM         15      /* Termination (ANSI).  */
+#define SIGUSR1         16      /* User-defined signal 1 (POSIX).  */
+#define SIGUSR2         17      /* User-defined signal 2 (POSIX).  */
+#define SIGCHLD         18      /* Child status has changed (POSIX).  */
+#define SIGCLD          SIGCHLD /* Same as SIGCHLD (System V).  */
+#define SIGPWR          19      /* Power failure restart (System V).  */
+#define SIGWINCH        20      /* Window size change (4.3 BSD, Sun).  */
+#define SIGURG          21      /* Urgent condition on socket (4.2 BSD).  */
+#define SIGIO           22      /* I/O now possible (4.2 BSD).  */
+#define SIGPOLL         SIGIO   /* Pollable event occurred (System V).  */
+#define SIGSTOP         23      /* Stop, unblockable (POSIX).  */
+#define SIGTSTP         24      /* Keyboard stop (POSIX).  */
+#define SIGCONT         25      /* Continue (POSIX).  */
+#define SIGTTIN         26      /* Background read from tty (POSIX).  */
+#define SIGTTOU         27      /* Background write to tty (POSIX).  */
+#define SIGVTALRM       28      /* Virtual alarm clock (4.2 BSD).  */
+#define SIGPROF         29      /* Profiling alarm clock (4.2 BSD).  */
+#define SIGXCPU         30      /* CPU limit exceeded (4.2 BSD).  */
+#define SIGXFSZ         31      /* File size limit exceeded (4.2 BSD).  */
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_ONSTACK      0x08000000
+#define SA_RESETHAND    0x80000000
+#define SA_RESTART      0x10000000
+#define SA_SIGINFO      0x00000008
+#define SA_NODEFER      0x40000000
+#define SA_NOCLDWAIT    0x00010000
+#define SA_NOCLDSTOP    0x00000001
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+#define SA_INTERRUPT    0x20000000      /* dummy -- ignored */
+
+#define SA_RESTORER     0x04000000      /* Only for o32 */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK     1
+#define SS_DISABLE     2
+
+#define MINSIGSTKSZ    2048
+#define SIGSTKSZ       8192
+
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE                SA_ONESHOT
+#define SA_SAMPLE_RANDOM        SA_RESTART
+#define SA_SHIRQ                0x02000000
+
+#endif /* __KERNEL__ */
+
+#define SIG_BLOCK       1       /* for blocking signals */
+#define SIG_UNBLOCK     2       /* for unblocking signals */
+#define SIG_SETMASK     3       /* for setting the signal mask */
+#define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
+                                   set only the low 32 bit of the sigset.  */
+
+/* Type of a signal handler.  */
+typedef void (*__sighandler_t)(int);
+
+/* Fake signal functions */
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+
+struct sigaction {
+        unsigned int    sa_flags;
+        __sighandler_t  sa_handler;
+        sigset_t        sa_mask;
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+#ifdef CONFIG_BINFMT_IRIX
+        void            (*sa_restorer)(void);
+#endif
+};
+
+/* IRIX compatible stack_t  */
+typedef struct sigaltstack {
+        void *ss_sp;
+        size_t ss_size;
+        int ss_flags;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+/*
+ * The following break codes are or were in use for specific purposes in
+ * other MIPS operating systems.  Linux/MIPS doesn't use all of them.  The
+ * unused ones are here as placeholders; we might encounter them in
+ * non-Linux/MIPS object files or make use of them in the future.
+ */
+#define BRK_USERBP      0       /* User bp (used by debuggers) */
+#define BRK_KERNELBP    1       /* Break in the kernel */
+#define BRK_ABORT       2       /* Sometimes used by abort(3) to SIGIOT */
+#define BRK_BD_TAKEN    3       /* For bd slot emulation - not implemented */
+#define BRK_BD_NOTTAKEN 4       /* For bd slot emulation - not implemented */
+#define BRK_SSTEPBP     5       /* User bp (used by debuggers) */
+#define BRK_OVERFLOW    6       /* Overflow check */
+#define BRK_DIVZERO     7       /* Divide by zero check */
+#define BRK_RANGE       8       /* Range error check */
+#define BRK_STACKOVERFLOW 9     /* For Ada stackchecking */
+#define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
+#define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
+#define BRK_MULOVF      1023    /* Multiply overflow */
+#define BRK_BUG         512     /* Used by BUG() */
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SIGNAL_H */
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
new file mode 100644
index 000000000000..6333169be329
--- /dev/null
+++ b/include/asm-mips/sim.h
@@ -0,0 +1,83 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIM_H
+#define _ASM_SIM_H
+
+#include <linux/config.h>
+
+#include <asm/offset.h>
+
+#define __str2(x) #x
+#define __str(x) __str2(x)
+
+#ifdef CONFIG_MIPS32
+
+#define save_static_function(symbol)                                    \
+__asm__ (                                                               \
+        ".text\n\t"                                                     \
+        ".globl\t" #symbol "\n\t"                                       \
+        ".align\t2\n\t"                                                 \
+        ".type\t" #symbol ", @function\n\t"                             \
+        ".ent\t" #symbol ", 0\n"                                        \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sw\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sw\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sw\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sw\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sw\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sw\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sw\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sw\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t_" #symbol "\n\t"                                           \
+        ".end\t" #symbol "\n\t"                                         \
+        ".size\t" #symbol",. - " #symbol)
+
+#define nabi_no_regargs
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+
+#define save_static_function(symbol)                                    \
+__asm__ (                                                               \
+        ".text\n\t"                                                     \
+        ".globl\t" #symbol "\n\t"                                       \
+        ".align\t2\n\t"                                                 \
+        ".type\t" #symbol ", @function\n\t"                             \
+        ".ent\t" #symbol ", 0\n"                                        \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sd\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sd\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sd\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sd\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sd\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sd\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sd\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sd\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t_" #symbol "\n\t"                                           \
+        ".end\t" #symbol "\n\t"                                         \
+        ".size\t" #symbol",. - " #symbol)
+
+#define nabi_no_regargs                                                 \
+        unsigned long __dummy0,                                         \
+        unsigned long __dummy1,                                         \
+        unsigned long __dummy2,                                         \
+        unsigned long __dummy3,                                         \
+        unsigned long __dummy4,                                         \
+        unsigned long __dummy5,                                         \
+        unsigned long __dummy6,                                         \
+        unsigned long __dummy7,
+
+#endif /* CONFIG_MIPS64 */
+
+#endif /* _ASM_SIM_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
new file mode 100644
index 000000000000..8ba370ecfd4c
--- /dev/null
+++ b/include/asm-mips/smp.h
@@ -0,0 +1,111 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
+ * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001, 2002 Ralf Baechle
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SMP_H
+#define __ASM_SMP_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/bitops.h>
+#include <linux/linkage.h>
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <asm/atomic.h>
+
+#define smp_processor_id()      (current_thread_info()->cpu)
+
+/* Map from cpu id to sequential logical cpu number.  This will only
+   not be idempotent when cpus failed to come on-line.  */
+extern int __cpu_number_map[NR_CPUS];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
+
+#define NO_PROC_ID      (-1)
+
+struct call_data_struct {
+        void            (*func)(void *);
+        void            *info;
+        atomic_t        started;
+        atomic_t        finished;
+        int             wait;
+};
+
+extern struct call_data_struct *call_data;
+
+#define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
+#define SMP_CALL_FUNCTION       0x2
+
+extern cpumask_t phys_cpu_present_map;
+extern cpumask_t cpu_online_map;
+#define cpu_possible_map        phys_cpu_present_map
+
+extern cpumask_t cpu_callout_map;
+/* We don't mark CPUs online until __cpu_up(), so we need another measure */
+static inline int num_booting_cpus(void)
+{
+        return cpus_weight(cpu_callout_map);
+}
+
+/* These are defined by the board-specific code. */
+
+/*
+ * Cause the function described by call_data to be executed on the passed
+ * cpu.  When the function has finished, increment the finished field of
+ * call_data.
+ */
+extern void core_send_ipi(int cpu, unsigned int action);
+
+/*
+ * Firmware CPU startup hook
+ */
+extern void prom_boot_secondary(int cpu, struct task_struct *idle);
+
+/*
+ *  After we've done initial boot, this function is called to allow the
+ *  board code to clean up state, if needed
+ */
+extern void prom_init_secondary(void);
+
+/*
+ * Detect available CPUs, populate phys_cpu_present_map before smp_init
+ */
+extern void prom_prepare_cpus(unsigned int max_cpus);
+
+/*
+ * Last chance for the board code to finish SMP initialization before
+ * the CPU is "online".
+ */
+extern void prom_smp_finish(void);
+
+/* Hook for after all CPUs are online */
+extern void prom_cpus_done(void);
+
+extern void asmlinkage smp_bootstrap(void);
+
+/*
+ * this function sends a 'reschedule' IPI to another CPU.
+ * it goes straight through and wastes no time serializing
+ * anything. Worst case is that we lose a reschedule ...
+ */
+static inline void smp_send_reschedule(int cpu)
+{
+        core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF);
+}
+
+extern asmlinkage void smp_call_function_interrupt(void);
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
new file mode 100644
index 000000000000..2b5cef1ba37f
--- /dev/null
+++ b/include/asm-mips/sn/addrs.h
@@ -0,0 +1,458 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_ADDRS_H
+#define _ASM_SN_ADDRS_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif /* !__ASSEMBLY__ */
+
+#include <asm/addrspace.h>
+#include <asm/sn/kldir.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/addrs.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/addrs.h>
+#endif
+
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_SGI_IO)      /* FIXME */
+#define PS_UINT_CAST            (__psunsigned_t)
+#define UINT64_CAST             (__uint64_t)
+#else   /* CONFIG_SGI_IO */
+#define PS_UINT_CAST            (unsigned long)
+#define UINT64_CAST             (unsigned long)
+#endif  /* CONFIG_SGI_IO */
+
+#define HUBREG_CAST             (volatile hubreg_t *)
+
+#else /* __ASSEMBLY__ */
+
+#define PS_UINT_CAST
+#define UINT64_CAST
+#define HUBREG_CAST
+
+#endif /* __ASSEMBLY__ */
+
+
+#define NASID_GET_META(_n)      ((_n) >> NASID_LOCAL_BITS)
+#ifdef CONFIG_SGI_IP27
+#define NASID_GET_LOCAL(_n)     ((_n) & 0xf)
+#endif
+#define NASID_MAKE(_m, _l)      (((_m) << NASID_LOCAL_BITS) | (_l))
+
+#define NODE_ADDRSPACE_MASK     (NODE_ADDRSPACE_SIZE - 1)
+#define TO_NODE_ADDRSPACE(_pa)  (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
+
+#define CHANGE_ADDR_NASID(_pa, _nasid)  \
+                ((UINT64_CAST (_pa) & ~NASID_MASK) | \
+                 (UINT64_CAST(_nasid) <<  NASID_SHFT))
+
+
+/*
+ * The following macros are used to index to the beginning of a specific
+ * node's address space.
+ */
+
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+
+#define NODE_CAC_BASE(_n)       (CAC_BASE   + NODE_OFFSET(_n))
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_IO_BASE(_n)        (IO_BASE    + NODE_OFFSET(_n))
+#define NODE_MSPEC_BASE(_n)     (MSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_UNCAC_BASE(_n)     (UNCAC_BASE + NODE_OFFSET(_n))
+
+#define TO_NODE(_n, _x)         (NODE_OFFSET(_n)     | ((_x)               ))
+#define TO_NODE_CAC(_n, _x)     (NODE_CAC_BASE(_n)   | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_UNCAC(_n, _x)   (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_MSPEC(_n, _x)   (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_HSPEC(_n, _x)   (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+
+
+#define RAW_NODE_SWIN_BASE(nasid, widget)                               \
+        (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+
+#define WIDGETID_GET(addr)      ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS          24
+#define SWIN_SIZE               (UINT64_CAST 1 << 24)
+#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
+#define SWIN_WIDGET_MASK        0xF
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
+#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to small window address on node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+#define NODE_SWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
+                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
+                 ))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN.
+ *      UALIAS -- 256MB in size, reads in the UALIAS result in
+ *                      uncached references to the memory of the reader's node.
+ *      CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
+ *                      depending on which CPU does the access to provide
+ *                      all CPUs with unique uncached memory at low addresses.
+ *      LBOOT  -- 256MB in size, reads in the LBOOT area result in
+ *                      uncached references to the local hub's boot prom and
+ *                      other directory-bus connected devices.
+ *      IALIAS -- 8MB in size, reads in the IALIAS result in uncached
+ *                      references to the local hub's registers.
+ */
+
+#define UALIAS_BASE             HSPEC_BASE
+#define UALIAS_SIZE             0x10000000      /* 256 Megabytes */
+#define UALIAS_LIMIT            (UALIAS_BASE + UALIAS_SIZE)
+
+/*
+ * The bottom of ualias space is flipped depending on whether you're
+ * processor 0 or 1 within a node.
+ */
+#ifdef CONFIG_SGI_IP27
+#define UALIAS_FLIP_BASE        UALIAS_BASE
+#define UALIAS_FLIP_SIZE        0x20000
+#define UALIAS_FLIP_BIT         0x10000
+#define UALIAS_FLIP_ADDR(_x)    (cputoslice(smp_processor_id()) ? \
+                                 (_x) ^ UALIAS_FLIP_BIT : (_x))
+
+#define LBOOT_BASE              (HSPEC_BASE + 0x10000000)
+#define LBOOT_SIZE              0x10000000
+#define LBOOT_LIMIT             (LBOOT_BASE + LBOOT_SIZE)
+#define LBOOT_STRIDE            0               /* IP27 has only one CPU PROM */
+
+#endif
+
+#define HUB_REGISTER_WIDGET     1
+#define IALIAS_BASE             NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#define IALIAS_SIZE             0x800000        /* 8 Megabytes */
+#define IS_IALIAS(_a)           (((_a) >= IALIAS_BASE) &&               \
+                                 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
+
+/*
+ * Macro for referring to Hub's RBOOT space
+ */
+
+#ifdef CONFIG_SGI_IP27
+#define RBOOT_SIZE              0x10000000      /* 256 Megabytes */
+#define NODE_RBOOT_BASE(_n)     (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_RBOOT_LIMIT(_n)    (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
+
+#endif
+
+/*
+ * Macros for referring the Hub's back door space
+ *
+ *   These macros correctly process addresses in any node's space.
+ *   WARNING: They won't work in assembler.
+ *
+ *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
+ *                  entry corresponding to a physical (Cac or Uncac) address.
+ *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
+ *   BDPRT_ENTRY    returns the address of the double-word protection entry
+ *                  corresponding to the page containing the physical address.
+ *   BDPRT_ENTRY_S  Stores the value into the protection entry.
+ *   BDPRT_ENTRY_L  Load the value from the protection entry.
+ *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
+ *                  double-word at a specified physical address.
+ *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
+ *                  quad-word at a specified physical address.
+ */
+#define NODE_BDOOR_BASE(_n)     (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
+
+#define NODE_BDECC_BASE(_n)     (NODE_BDOOR_BASE(_n))
+#define NODE_BDDIR_BASE(_n)     (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
+#ifdef CONFIG_SGI_IP27
+#define BDDIR_ENTRY_LO(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x200)                                    | \
+                                 UINT64_CAST (_pa)       & NASID_MASK       | \
+                                 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST (_pa) >> 3 & 0x1f << 4)
+
+#define BDDIR_ENTRY_HI(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x208)                                    | \
+                                 UINT64_CAST (_pa)       & NASID_MASK       | \
+                                 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST (_pa) >> 3 & 0x1f << 4)
+
+#define BDPRT_ENTRY(_pa, _rgn)  ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4)              | \
+                                 UINT64_CAST (_pa)       & NASID_MASK       | \
+                                 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 (_rgn) << 3)
+#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
+#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
+#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn)))
+
+#define BDECC_ENTRY(_pa)        ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE / 2)                  | \
+                                 UINT64_CAST (_pa)       & NASID_MASK       | \
+                                 UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK  | \
+                                 UINT64_CAST (_pa) >> 3 & 3)
+
+/*
+ * Macro to convert a back door directory or protection address into the
+ *   raw physical address of the associated cache line or protection page.
+ */
+#define BDADDR_IS_DIR(_ba)      ((UINT64_CAST  (_ba) & 0x200) != 0)
+#define BDADDR_IS_PRT(_ba)      ((UINT64_CAST  (_ba) & 0x200) == 0)
+
+#define BDDIR_TO_MEM(_ba)       (UINT64_CAST  (_ba) & NASID_MASK            | \
+                                 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST (_ba) & 0x1f << 4) << 3)
+
+#define BDPRT_TO_MEM(_ba)       (UINT64_CAST  (_ba) & NASID_MASK            | \
+                                 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2)
+
+#define BDECC_TO_MEM(_ba)       (UINT64_CAST  (_ba) & NASID_MASK            | \
+                                 (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST (_ba) & 3) << 3)
+#endif /* CONFIG_SGI_IP27 */
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers.  The LOCAL_HUB_* macros produce the appropriate
+ * address for the local registers.  The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for _x.
+ */
+
+#ifdef _STANDALONE
+
+/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
+#define LOCAL_HUB(_x)           (HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB(_n, _x)      (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+                                              0x800000 + (_x)))
+#endif /* _STANDALONE */
+
+/*
+ * WARNING:
+ *      When certain Hub chip workaround are defined, it's not sufficient
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *      They're always safe.
+ */
+#define LOCAL_HUB_ADDR(_x)      (HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+                                              0x800000 + (_x)))
+#ifdef CONFIG_SGI_IP27
+#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+                                              0x800000 + (_x)))
+#endif /* CONFIG_SGI_IP27 */
+
+#ifndef __ASSEMBLY__
+
+#define HUB_L(_a)                       *(_a)
+#define HUB_S(_a, _d)                   *(_a) = (_d)
+
+#define LOCAL_HUB_L(_r)                 HUB_L(LOCAL_HUB_ADDR(_r))
+#define LOCAL_HUB_S(_r, _d)             HUB_S(LOCAL_HUB_ADDR(_r), (_d))
+#define REMOTE_HUB_L(_n, _r)            HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
+#define REMOTE_HUB_S(_n, _r, _d)        HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
+#define REMOTE_HUB_PI_L(_n, _sn, _r)    HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
+#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The following macros are used to get to a hub/bridge register, given
+ * the base of the register space.
+ */
+#define HUB_REG_PTR(_base, _off)        \
+        (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define HUB_REG_PTR_L(_base, _off)      \
+        HUB_L(HUB_REG_PTR((_base), (_off)))
+
+#define HUB_REG_PTR_S(_base, _off, _data)       \
+        HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
+
+/*
+ * Software structure locations -- permanently fixed
+ *    See diagram in kldir.h
+ */
+
+#define PHYS_RAMBASE            0x0
+#define K0_RAMBASE              PHYS_TO_K0(PHYS_RAMBASE)
+
+#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
+#define EX_HANDLER_ADDR(nasid, slice)                                   \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
+#define EX_HANDLER_SIZE         0x0400
+
+#define EX_FRAME_OFFSET(slice)  ((slice) << 16 | 0x400)
+#define EX_FRAME_ADDR(nasid, slice)                                     \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
+#define EX_FRAME_SIZE           0x0c00
+
+#define ARCS_SPB_OFFSET         0x1000
+#define ARCS_SPB_ADDR(nasid)                                            \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
+#define ARCS_SPB_SIZE           0x0400
+
+#ifdef _STANDALONE
+
+#define ARCS_TVECTOR_OFFSET     0x2800
+#define ARCS_PVECTOR_OFFSET     0x2c00
+
+/*
+ * These addresses are used by the master CPU to install the transfer
+ * and private vectors.  All others use the SPB to find them.
+ */
+#define TVADDR  (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
+#define PVADDR  (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
+
+#endif /* _STANDALONE */
+
+#define KLDIR_OFFSET            0x2000
+#define KLDIR_ADDR(nasid)                                               \
+        TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
+#define KLDIR_SIZE              0x0400
+
+
+/*
+ * Software structure locations -- indirected through KLDIR
+ *    See diagram in kldir.h
+ *
+ * Important:   All low memory structures must only be accessed
+ *              uncached, except for the symmon stacks.
+ */
+
+#define KLI_LAUNCH              0               /* Dir. entries */
+#define KLI_KLCONFIG            1
+#define KLI_NMI                 2
+#define KLI_GDA                 3
+#define KLI_FREEMEM             4
+#define KLI_SYMMON_STK          5
+#define KLI_PI_ERROR            6
+#define KLI_KERN_VARS           7
+#define KLI_KERN_XP             8
+#define KLI_KERN_PARTID         9
+
+#ifndef __ASSEMBLY__
+
+#define KLD_BASE(nasid)         ((kldir_ent_t *) KLDIR_ADDR(nasid))
+#define KLD_LAUNCH(nasid)       (KLD_BASE(nasid) + KLI_LAUNCH)
+#define KLD_NMI(nasid)          (KLD_BASE(nasid) + KLI_NMI)
+#define KLD_KLCONFIG(nasid)     (KLD_BASE(nasid) + KLI_KLCONFIG)
+#define KLD_PI_ERROR(nasid)     (KLD_BASE(nasid) + KLI_PI_ERROR)
+#define KLD_GDA(nasid)          (KLD_BASE(nasid) + KLI_GDA)
+#define KLD_SYMMON_STK(nasid)   (KLD_BASE(nasid) + KLI_SYMMON_STK)
+#define KLD_FREEMEM(nasid)      (KLD_BASE(nasid) + KLI_FREEMEM)
+#define KLD_KERN_VARS(nasid)    (KLD_BASE(nasid) + KLI_KERN_VARS)
+#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
+#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
+
+#define LAUNCH_OFFSET(nasid, slice)                                     \
+        (KLD_LAUNCH(nasid)->offset +                                    \
+         KLD_LAUNCH(nasid)->stride * (slice))
+#define LAUNCH_ADDR(nasid, slice)                                       \
+        TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
+#define LAUNCH_SIZE(nasid)      KLD_LAUNCH(nasid)->size
+
+#define NMI_OFFSET(nasid, slice)                                        \
+        (KLD_NMI(nasid)->offset +                                       \
+         KLD_NMI(nasid)->stride * (slice))
+#define NMI_ADDR(nasid, slice)                                          \
+        TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
+#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
+
+#define KLCONFIG_OFFSET(nasid)  KLD_KLCONFIG(nasid)->offset
+#define KLCONFIG_ADDR(nasid)                                            \
+        TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+#define KLCONFIG_SIZE(nasid)    KLD_KLCONFIG(nasid)->size
+
+#define GDA_ADDR(nasid)         KLD_GDA(nasid)->pointer
+#define GDA_SIZE(nasid)         KLD_GDA(nasid)->size
+
+#define SYMMON_STK_OFFSET(nasid, slice)                                 \
+        (KLD_SYMMON_STK(nasid)->offset +                                \
+         KLD_SYMMON_STK(nasid)->stride * (slice))
+#define SYMMON_STK_STRIDE(nasid)        KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_ADDR(nasid, slice)                                   \
+        TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
+
+#define SYMMON_STK_SIZE(nasid)  KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_END(nasid)   (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
+
+/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
+ * relocatable program
+ */
+#define UNIX_DEBUG_LOADADDR     0x300000
+#define SYMMON_LOADADDR(nasid)                                          \
+        TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
+
+#define FREEMEM_OFFSET(nasid)   KLD_FREEMEM(nasid)->offset
+#define FREEMEM_ADDR(nasid)     SYMMON_STK_END(nasid)
+/*
+ * XXX
+ * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
+ * Also, it should take into account what prom thinks to be a safe
+ * address
+        PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
+ */
+#define FREEMEM_SIZE(nasid)     KLD_FREEMEM(nasid)->size
+
+#define PI_ERROR_OFFSET(nasid)  KLD_PI_ERROR(nasid)->offset
+#define PI_ERROR_ADDR(nasid)                                            \
+        TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
+#define PI_ERROR_SIZE(nasid)    KLD_PI_ERROR(nasid)->size
+
+#define NODE_OFFSET_TO_K0(_nasid, _off)                                 \
+        PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
+#define NODE_OFFSET_TO_K1(_nasid, _off)                                 \
+        TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
+#define K0_TO_NODE_OFFSET(_k0addr)                                      \
+        ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
+
+#define KERN_VARS_ADDR(nasid)   KLD_KERN_VARS(nasid)->pointer
+#define KERN_VARS_SIZE(nasid)   KLD_KERN_VARS(nasid)->size
+
+#define KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
+#define KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
+
+#define GPDA_ADDR(nasid)        TO_NODE_CAC(nasid, GPDA_OFFSET)
+
+#endif /* !__ASSEMBLY__ */
+
+
+#endif /* _ASM_SN_ADDRS_H */
diff --git a/include/asm-mips/sn/agent.h b/include/asm-mips/sn/agent.h
new file mode 100644
index 000000000000..d6df13aaed49
--- /dev/null
+++ b/include/asm-mips/sn/agent.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file has definitions for the hub and snac interfaces.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
+ * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGI_SN_AGENT_H
+#define _ASM_SGI_SN_AGENT_H
+
+#include <linux/config.h>
+#include <linux/topology.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hub.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/hub.h>
+#endif  /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+/*
+ * NIC register macros
+ */
+
+#if defined(CONFIG_SGI_IP27)
+#define HUB_NIC_ADDR(_cpuid)                                               \
+        REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
+                MD_MLAN_CTL)
+#endif
+
+#define SET_HUB_NIC(_my_cpuid, _val)                                       \
+        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
+
+#define SET_MY_HUB_NIC(_v)                                                 \
+        SET_HUB_NIC(cpuid(), (_v))
+
+#define GET_HUB_NIC(_my_cpuid)                                             \
+        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
+
+#define GET_MY_HUB_NIC()                                                   \
+        GET_HUB_NIC(cpuid())
+
+#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h
new file mode 100644
index 000000000000..d247a819de7f
--- /dev/null
+++ b/include/asm-mips/sn/arch.h
@@ -0,0 +1,66 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_ARCH_H
+#define _ASM_SN_ARCH_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/types.h>
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/sn0/arch.h>
+#endif
+
+typedef u64     hubreg_t;
+typedef u64     nic_t;
+
+#define cputonasid(cpu)                 (cpu_data[(cpu)].p_nasid)
+#define cputoslice(cpu)                 (cpu_data[(cpu)].p_slice)
+#define makespnum(_nasid, _slice)                                       \
+                (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
+
+#define INVALID_NASID           (nasid_t)-1
+#define INVALID_CNODEID         (cnodeid_t)-1
+#define INVALID_PNODEID         (pnodeid_t)-1
+#define INVALID_MODULE          (moduleid_t)-1
+#define INVALID_PARTID          (partid_t)-1
+
+extern nasid_t get_nasid(void);
+extern cnodeid_t get_cpu_cnode(cpuid_t);
+extern int get_cpu_slice(cpuid_t);
+
+/*
+ * NO ONE should access these arrays directly.  The only reason we refer to
+ * them here is to avoid the procedure call that would be required in the
+ * macros below.  (Really want private data members here :-)
+ */
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+
+/*
+ * These macros are used by various parts of the kernel to convert
+ * between the three different kinds of node numbering.   At least some
+ * of them may change to procedure calls in the future, but the macros
+ * will continue to work.  Don't use the arrays above directly.
+ */
+
+#define NASID_TO_REGION(nnode)          \
+    ((nnode) >> \
+     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
+
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
+
+#define NASID_TO_COMPACT_NODEID(nnode)  (nasid_to_compact_node[nnode])
+#define COMPACT_TO_NASID_NODEID(cnode)  (compact_to_nasid_node[cnode])
+#define CPUID_TO_COMPACT_NODEID(cpu)    (cpuid_to_compact_node[(cpu)])
+
+#endif /* _ASM_SN_ARCH_H */
diff --git a/include/asm-mips/sn/gda.h b/include/asm-mips/sn/gda.h
new file mode 100644
index 000000000000..9cb6ff770915
--- /dev/null
+++ b/include/asm-mips/sn/gda.h
@@ -0,0 +1,107 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/gda.h>.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ *
+ * gda.h -- Contains the data structure for the global data area,
+ *      The GDA contains information communicated between the
+ *      PROM, SYMMON, and the kernel.
+ */
+#ifndef _ASM_SN_GDA_H
+#define _ASM_SN_GDA_H
+
+#include <asm/sn/addrs.h>
+
+#define GDA_MAGIC       0x58464552
+
+/*
+ * GDA Version History
+ *
+ * Version #    | Change
+ * -------------+-------------------------------------------------------
+ *      1       | Initial SN0 version
+ *      2       | Prom sets g_partid field to the partition number. 0 IS
+ *              | a valid partition #.
+ */
+
+#define GDA_VERSION     2       /* Current GDA version # */
+
+#define G_MAGICOFF      0
+#define G_VERSIONOFF    4
+#define G_PROMOPOFF     6
+#define G_MASTEROFF     8
+#define G_VDSOFF        12
+#define G_HKDNORMOFF    16
+#define G_HKDUTLBOFF    24
+#define G_HKDXUTLBOFF   32
+#define G_PARTIDOFF     40
+#define G_TABLEOFF      128
+
+#ifndef __ASSEMBLY__
+
+typedef struct gda {
+        u32     g_magic;        /* GDA magic number */
+        u16     g_version;      /* Version of this structure */
+        u16     g_masterid;     /* The NASID:CPUNUM of the master cpu */
+        u32     g_promop;       /* Passes requests from the kernel to prom */
+        u32     g_vds;          /* Store the virtual dipswitches here */
+        void    **g_hooked_norm;/* ptr to pda loc for norm hndlr */
+        void    **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
+        void    **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
+        int     g_partid;       /* partition id */
+        int     g_symmax;       /* Max symbols in name table. */
+        void    *g_dbstab;      /* Address of idbg symbol table */
+        char    *g_nametab;     /* Address of idbg name table */
+        void    *g_ktext_repmask;
+                                /* Pointer to a mask of nodes with copies
+                                 * of the kernel. */
+        char    g_padding[56];  /* pad out to 128 bytes */
+        nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
+                                                  * indexed by cnodeid.
+                                                  */
+} gda_t;
+
+#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
+
+#endif /* !__ASSEMBLY__ */
+/*
+ * Define:      PART_GDA_VERSION
+ * Purpose:     Define the minimum version of the GDA required, lower
+ *              revisions assume GDA is NOT set up, and read partition
+ *              information from the board info.
+ */
+#define PART_GDA_VERSION        2
+
+/*
+ * The following requests can be sent to the PROM during startup.
+ */
+
+#define PROMOP_MAGIC            0x0ead0000
+#define PROMOP_MAGIC_MASK       0x0fff0000
+
+#define PROMOP_BIST_SHIFT       11
+#define PROMOP_BIST_MASK        (0x3 << 11)
+
+#define PROMOP_REG              PI_ERR_STACK_ADDR_A
+
+#define PROMOP_INVALID          (PROMOP_MAGIC | 0x00)
+#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+
+#define PROMOP_CMD_MASK         0x00f0
+#define PROMOP_OPTIONS_MASK     0xfff0
+
+#define PROMOP_SKIP_DIAGS       0x0100          /* don't bother running diags */
+#define PROMOP_SKIP_MEMINIT     0x0200          /* don't bother initing memory */
+#define PROMOP_SKIP_DEVINIT     0x0400          /* don't bother initing devices */
+#define PROMOP_BIST1            0x0800          /* keep track of which BIST ran */
+#define PROMOP_BIST2            0x1000          /* keep track of which BIST ran */
+
+#endif /* _ASM_SN_GDA_H */
diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h
new file mode 100644
index 000000000000..1992d9254a08
--- /dev/null
+++ b/include/asm-mips/sn/hub.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SN_HUB_H
+#define __ASM_SN_HUB_H
+
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm/sn/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/klkernvars.h>
+#include <asm/xtalk/xtalk.h>
+
+/* ip27-hubio.c */
+extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
+                          unsigned long xtalk_addr, size_t size);
+extern void hub_pio_init(cnodeid_t cnode);
+
+#endif /* __ASM_SN_HUB_H */
diff --git a/include/asm-mips/sn/intr.h b/include/asm-mips/sn/intr.h
new file mode 100644
index 000000000000..6718b644b970
--- /dev/null
+++ b/include/asm-mips/sn/intr.h
@@ -0,0 +1,129 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_INTR_H
+#define __ASM_SN_INTR_H
+
+/* Number of interrupt levels associated with each interrupt register. */
+#define N_INTPEND_BITS          64
+
+#define INT_PEND0_BASELVL       0
+#define INT_PEND1_BASELVL       64
+
+#define N_INTPENDJUNK_BITS      8
+#define INTPENDJUNK_CLRBIT      0x80
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(level)                              \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
+#define REMOTE_HUB_SEND_INTR(hub, level)                        \
+        REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
+
+/*
+ * When clearing the interrupt, make sure this clear does make it
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(level)                               \
+do {                                                            \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
+        LOCAL_HUB_L(PI_INT_PEND0);                              \
+} while (0);
+
+#define REMOTE_HUB_CLR_INTR(hub, level)                         \
+do {                                                            \
+        nasid_t  __hub = (hub);                                 \
+                                                                \
+        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
+        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
+} while (0);
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *      L0 = SW1
+ *      L1 = SW2
+ *      L2 = INT_PEND0
+ *      L3 = INT_PEND1
+ *      L4 = RTC
+ *      L5 = Profiling Timer
+ *      L6 = Hub Errors
+ *      L7 = Count/Compare (T5 counters)
+ */
+
+
+/*
+ * INT_PEND0 hard-coded bits.
+ */
+
+/*
+ * INT_PEND0 bits determined by hardware:
+ */
+#define RESERVED_INTR            0      /* What is this bit? */
+#define GFX_INTR_A               1
+#define GFX_INTR_B               2
+#define PG_MIG_INTR              3
+#define UART_INTR                4
+#define CC_PEND_A                5
+#define CC_PEND_B                6
+
+/*
+ * INT_PEND0 used by the kernel for itself ...
+ */
+#define CPU_RESCHED_A_IRQ        7
+#define CPU_RESCHED_B_IRQ        8
+#define CPU_CALL_A_IRQ           9
+#define CPU_CALL_B_IRQ          10
+#define MSC_MESG_INTR           11
+#define BASE_PCI_IRQ            12
+
+/*
+ * INT_PEND0 again, bits determined by hardware / hardcoded:
+ */
+#define SDISK_INTR              63      /* SABLE name */
+#define IP_PEND0_6_63           63      /* What is this bit? */
+
+/*
+ * INT_PEND1 hard-coded bits:
+ */
+#define NI_BRDCAST_ERR_A        39
+#define NI_BRDCAST_ERR_B        40
+
+#define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_B        42
+
+#define TLB_INTR_A              43      /* used for tlb flush random */
+#define TLB_INTR_B              44
+
+#define IP27_INTR_0             45      /* Reserved for PROM use */
+#define IP27_INTR_1             46      /* do not use in Kernel */
+#define IP27_INTR_2             47
+#define IP27_INTR_3             48
+#define IP27_INTR_4             49
+#define IP27_INTR_5             50
+#define IP27_INTR_6             51
+#define IP27_INTR_7             52
+
+#define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
+                                        /* Bridge Errors */
+#define DEBUG_INTR_A            54
+#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define IO_ERROR_INTR           57      /* Setup by PROM */
+#define CLK_ERR_INTR            58
+#define COR_ERR_INTR_A          59
+#define COR_ERR_INTR_B          60
+#define MD_COR_ERR_INTR         61
+#define NI_ERROR_INTR           62
+#define MSC_PANIC_INTR          63
+
+#endif /* __ASM_SN_INTR_H */
diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h
new file mode 100644
index 000000000000..13326453efc9
--- /dev/null
+++ b/include/asm-mips/sn/io.h
@@ -0,0 +1,60 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2003 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+
+#include <linux/config.h>
+#if defined (CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hubio.h>
+#endif
+
+
+#define IIO_ITTE_BASE           0x400160 /* base of translation table entries */
+#define IIO_ITTE(bigwin)        (IIO_ITTE_BASE + 8*(bigwin))
+
+#define IIO_ITTE_OFFSET_BITS    5       /* size of offset field */
+#define IIO_ITTE_OFFSET_MASK    ((1<<IIO_ITTE_OFFSET_BITS)-1)
+#define IIO_ITTE_OFFSET_SHIFT   0
+
+#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
+#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
+#define IIO_ITTE_WIDGET_SHIFT   8
+
+#define IIO_ITTE_IOSP           1       /* I/O Space bit */
+#define IIO_ITTE_IOSP_MASK      1
+#define IIO_ITTE_IOSP_SHIFT     12
+#define HUB_PIO_MAP_TO_MEM      0
+#define HUB_PIO_MAP_TO_IO       1
+
+#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
+
+#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
+        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
+                (((((addr) >> BWIN_SIZE_BITS) & \
+                   IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
+                (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
+                (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
+
+#define IIO_ITTE_DISABLE(nasid, bigwin) \
+        IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
+                     (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
+
+#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+#endif /* _ASM_SN_IO_H */
diff --git a/include/asm-mips/sn/ioc3.h b/include/asm-mips/sn/ioc3.h
new file mode 100644
index 000000000000..f7d530f306f2
--- /dev/null
+++ b/include/asm-mips/sn/ioc3.h
@@ -0,0 +1,661 @@
+/*
+ * Copyright (C) 1999, 2000 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _IOC3_H
+#define _IOC3_H
+
+/* SUPERIO uart register map */
+typedef volatile struct ioc3_uartregs {
+        union {
+                volatile u8     rbr;    /* read only, DLAB == 0 */
+                volatile u8     thr;    /* write only, DLAB == 0 */
+                volatile u8     dll;    /* DLAB == 1 */
+        } u1;
+        union {
+                volatile u8     ier;    /* DLAB == 0 */
+                volatile u8     dlm;    /* DLAB == 1 */
+        } u2;
+        union {
+                volatile u8     iir;    /* read only */
+                volatile u8     fcr;    /* write only */
+        } u3;
+        volatile u8         iu_lcr;
+        volatile u8         iu_mcr;
+        volatile u8         iu_lsr;
+        volatile u8         iu_msr;
+        volatile u8         iu_scr;
+} ioc3_uregs_t;
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+struct ioc3_sioregs {
+        volatile u8             fill[0x141];    /* starts at 0x141 */
+
+        volatile u8             uartc;
+        volatile u8             kbdcg;
+
+        volatile u8             fill0[0x150 - 0x142 - 1];
+
+        volatile u8             pp_data;
+        volatile u8             pp_dsr;
+        volatile u8             pp_dcr;
+
+        volatile u8             fill1[0x158 - 0x152 - 1];
+
+        volatile u8             pp_fifa;
+        volatile u8             pp_cfgb;
+        volatile u8             pp_ecr;
+
+        volatile u8             fill2[0x168 - 0x15a - 1];
+
+        volatile u8             rtcad;
+        volatile u8             rtcdat;
+
+        volatile u8             fill3[0x170 - 0x169 - 1];
+
+        struct ioc3_uartregs    uartb;  /* 0x20170  */
+        struct ioc3_uartregs    uarta;  /* 0x20178  */
+};
+
+/* Register layout of IOC3 in configuration space.  */
+struct ioc3 {
+        volatile u32    pad0[7];        /* 0x00000  */
+        volatile u32    sio_ir;         /* 0x0001c  */
+        volatile u32    sio_ies;        /* 0x00020  */
+        volatile u32    sio_iec;        /* 0x00024  */
+        volatile u32    sio_cr;         /* 0x00028  */
+        volatile u32    int_out;        /* 0x0002c  */
+        volatile u32    mcr;            /* 0x00030  */
+
+        /* General Purpose I/O registers  */
+        volatile u32    gpcr_s;         /* 0x00034  */
+        volatile u32    gpcr_c;         /* 0x00038  */
+        volatile u32    gpdr;           /* 0x0003c  */
+        volatile u32    gppr_0;         /* 0x00040  */
+        volatile u32    gppr_1;         /* 0x00044  */
+        volatile u32    gppr_2;         /* 0x00048  */
+        volatile u32    gppr_3;         /* 0x0004c  */
+        volatile u32    gppr_4;         /* 0x00050  */
+        volatile u32    gppr_5;         /* 0x00054  */
+        volatile u32    gppr_6;         /* 0x00058  */
+        volatile u32    gppr_7;         /* 0x0005c  */
+        volatile u32    gppr_8;         /* 0x00060  */
+        volatile u32    gppr_9;         /* 0x00064  */
+        volatile u32    gppr_10;        /* 0x00068  */
+        volatile u32    gppr_11;        /* 0x0006c  */
+        volatile u32    gppr_12;        /* 0x00070  */
+        volatile u32    gppr_13;        /* 0x00074  */
+        volatile u32    gppr_14;        /* 0x00078  */
+        volatile u32    gppr_15;        /* 0x0007c  */
+
+        /* Parallel Port Registers  */
+        volatile u32    ppbr_h_a;       /* 0x00080  */
+        volatile u32    ppbr_l_a;       /* 0x00084  */
+        volatile u32    ppcr_a;         /* 0x00088  */
+        volatile u32    ppcr;           /* 0x0008c  */
+        volatile u32    ppbr_h_b;       /* 0x00090  */
+        volatile u32    ppbr_l_b;       /* 0x00094  */
+        volatile u32    ppcr_b;         /* 0x00098  */
+
+        /* Keyboard and Mouse Registers  */
+        volatile u32    km_csr;         /* 0x0009c  */
+        volatile u32    k_rd;           /* 0x000a0  */
+        volatile u32    m_rd;           /* 0x000a4  */
+        volatile u32    k_wd;           /* 0x000a8  */
+        volatile u32    m_wd;           /* 0x000ac  */
+
+        /* Serial Port Registers  */
+        volatile u32    sbbr_h;         /* 0x000b0  */
+        volatile u32    sbbr_l;         /* 0x000b4  */
+        volatile u32    sscr_a;         /* 0x000b8  */
+        volatile u32    stpir_a;        /* 0x000bc  */
+        volatile u32    stcir_a;        /* 0x000c0  */
+        volatile u32    srpir_a;        /* 0x000c4  */
+        volatile u32    srcir_a;        /* 0x000c8  */
+        volatile u32    srtr_a;         /* 0x000cc  */
+        volatile u32    shadow_a;       /* 0x000d0  */
+        volatile u32    sscr_b;         /* 0x000d4  */
+        volatile u32    stpir_b;        /* 0x000d8  */
+        volatile u32    stcir_b;        /* 0x000dc  */
+        volatile u32    srpir_b;        /* 0x000e0  */
+        volatile u32    srcir_b;        /* 0x000e4  */
+        volatile u32    srtr_b;         /* 0x000e8  */
+        volatile u32    shadow_b;       /* 0x000ec  */
+
+        /* Ethernet Registers  */
+        volatile u32    emcr;           /* 0x000f0  */
+        volatile u32    eisr;           /* 0x000f4  */
+        volatile u32    eier;           /* 0x000f8  */
+        volatile u32    ercsr;          /* 0x000fc  */
+        volatile u32    erbr_h;         /* 0x00100  */
+        volatile u32    erbr_l;         /* 0x00104  */
+        volatile u32    erbar;          /* 0x00108  */
+        volatile u32    ercir;          /* 0x0010c  */
+        volatile u32    erpir;          /* 0x00110  */
+        volatile u32    ertr;           /* 0x00114  */
+        volatile u32    etcsr;          /* 0x00118  */
+        volatile u32    ersr;           /* 0x0011c  */
+        volatile u32    etcdc;          /* 0x00120  */
+        volatile u32    ebir;           /* 0x00124  */
+        volatile u32    etbr_h;         /* 0x00128  */
+        volatile u32    etbr_l;         /* 0x0012c  */
+        volatile u32    etcir;          /* 0x00130  */
+        volatile u32    etpir;          /* 0x00134  */
+        volatile u32    emar_h;         /* 0x00138  */
+        volatile u32    emar_l;         /* 0x0013c  */
+        volatile u32    ehar_h;         /* 0x00140  */
+        volatile u32    ehar_l;         /* 0x00144  */
+        volatile u32    micr;           /* 0x00148  */
+        volatile u32    midr_r;         /* 0x0014c  */
+        volatile u32    midr_w;         /* 0x00150  */
+        volatile u32    pad1[(0x20000 - 0x00154) / 4];
+
+        /* SuperIO Registers  XXX */
+        struct ioc3_sioregs     sregs;  /* 0x20000 */
+        volatile u32    pad2[(0x40000 - 0x20180) / 4];
+
+        /* SSRAM Diagnostic Access */
+        volatile u32    ssram[(0x80000 - 0x40000) / 4];
+
+        /* Bytebus device offsets
+           0x80000 -   Access to the generic devices selected with   DEV0
+           0x9FFFF     bytebus DEV_SEL_0
+           0xA0000 -   Access to the generic devices selected with   DEV1
+           0xBFFFF     bytebus DEV_SEL_1
+           0xC0000 -   Access to the generic devices selected with   DEV2
+           0xDFFFF     bytebus DEV_SEL_2
+           0xE0000 -   Access to the generic devices selected with   DEV3
+           0xFFFFF     bytebus DEV_SEL_3  */
+};
+
+/*
+ * Ethernet RX Buffer
+ */
+struct ioc3_erxbuf {
+        u32     w0;                     /* first word (valid,bcnt,cksum) */
+        u32     err;                    /* second word various errors */
+        /* next comes n bytes of padding */
+        /* then the received ethernet frame itself */
+};
+
+#define ERXBUF_IPCKSUM_MASK     0x0000ffff
+#define ERXBUF_BYTECNT_MASK     0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT    16
+#define ERXBUF_V                0x80000000
+
+#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
+#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
+#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
+#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
+#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
+#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
+#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
+#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
+#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
+#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
+#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
+#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
+
+/*
+ * Ethernet TX Descriptor
+ */
+#define ETXD_DATALEN    104
+struct ioc3_etxd {
+        u32     cmd;                            /* command field */
+        u32     bufcnt;                         /* buffer counts field */
+        u64     p1;                             /* buffer pointer 1 */
+        u64     p2;                             /* buffer pointer 2 */
+        u8      data[ETXD_DATALEN];             /* opt. tx data */
+};
+
+#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
+#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
+#define ETXD_D0V                0x00010000      /* data 0 valid */
+#define ETXD_B1V                0x00020000      /* buf 1 valid */
+#define ETXD_B2V                0x00040000      /* buf 2 valid */
+#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
+#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT       20
+
+#define ETXD_D0CNT_MASK         0x0000007f
+#define ETXD_B1CNT_MASK         0x0007ff00
+#define ETXD_B1CNT_SHIFT        8
+#define ETXD_B2CNT_MASK         0x7ff00000
+#define ETXD_B2CNT_SHIFT        20
+
+/*
+ * Bytebus device space
+ */
+#define IOC3_BYTEBUS_DEV0       0x80000L
+#define IOC3_BYTEBUS_DEV1       0xa0000L
+#define IOC3_BYTEBUS_DEV2       0xc0000L
+#define IOC3_BYTEBUS_DEV3       0xe0000L
+
+/* ------------------------------------------------------------------------- */
+
+/* Superio Registers (PIO Access) */
+#define IOC3_SIO_BASE           0x20000
+#define IOC3_SIO_UARTC          (IOC3_SIO_BASE+0x141)   /* UART Config */
+#define IOC3_SIO_KBDCG          (IOC3_SIO_BASE+0x142)   /* KBD Config */
+#define IOC3_SIO_PP_BASE        (IOC3_SIO_BASE+PP_BASE)         /* Parallel Port */
+#define IOC3_SIO_RTC_BASE       (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
+#define IOC3_SIO_UB_BASE        (IOC3_SIO_BASE+UARTB_BASE)      /* UART B */
+#define IOC3_SIO_UA_BASE        (IOC3_SIO_BASE+UARTA_BASE)      /* UART A */
+
+/* SSRAM Diagnostic Access */
+#define IOC3_SSRAM      IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
+#define IOC3_SSRAM_LEN  0x40000 /* 256kb (address space size, may not be fully populated) */
+#define IOC3_SSRAM_DM   0x0000ffff      /* data mask */
+#define IOC3_SSRAM_PM   0x00010000      /* parity mask */
+
+/* bitmasks for PCI_SCR */
+#define PCI_SCR_PAR_RESP_EN     0x00000040      /* enb PCI parity checking */
+#define PCI_SCR_SERR_EN         0x00000100      /* enable the SERR# driver */
+#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
+#define PCI_SCR_RX_SERR         (0x1 << 16)
+#define PCI_SCR_DROP_MODE       (0x1 << 17)
+#define PCI_SCR_SIG_PAR_ERR     (0x1 << 24)
+#define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
+#define PCI_SCR_RX_TAR_ABRT     (0x1 << 28)
+#define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
+#define PCI_SCR_SIG_SERR        (0x1 << 30)
+#define PCI_SCR_PAR_ERR         (0x1 << 31)
+
+/* bitmasks for IOC3_KM_CSR */
+#define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
+#define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
+#define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
+#define KM_CSR_M_LCB      0x00000008    /* same for mouse */
+#define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
+#define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
+#define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
+#define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
+#define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
+#define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
+#define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
+#define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
+#define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
+#define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
+#define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
+#define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
+#define KM_CSR_K_TO       0x00010000    /* Keyboard trying to send/receive */
+#define KM_CSR_M_TO       0x00020000    /* Mouse trying to send/receive */
+#define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_K_CLAMP_ONE      0x00100000      /* Pull K_CLK low after rec. one char */
+#define KM_CSR_M_CLAMP_ONE      0x00200000      /* Pull M_CLK low after rec. one char */
+#define KM_CSR_K_CLAMP_THREE    0x00400000      /* Pull K_CLK low after rec. three chars */
+#define KM_CSR_M_CLAMP_THREE    0x00800000      /* Pull M_CLK low after rec. three char */
+
+/* bitmasks for IOC3_K_RD and IOC3_M_RD */
+#define KM_RD_DATA_2    0x000000ff      /* 3rd char recvd since last read */
+#define KM_RD_DATA_2_SHIFT 0
+#define KM_RD_DATA_1    0x0000ff00      /* 2nd char recvd since last read */
+#define KM_RD_DATA_1_SHIFT 8
+#define KM_RD_DATA_0    0x00ff0000      /* 1st char recvd since last read */
+#define KM_RD_DATA_0_SHIFT 16
+#define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
+#define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
+#define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
+
+#define KM_RD_KBD_MSE   0x08000000      /* 0 if from kbd, 1 if from mouse */
+#define KM_RD_OFLO      0x10000000      /* 4th char recvd before this read */
+#define KM_RD_VALID_2   0x20000000      /* DATA_2 valid */
+#define KM_RD_VALID_1   0x40000000      /* DATA_1 valid */
+#define KM_RD_VALID_0   0x80000000      /* DATA_0 valid */
+#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
+
+/* bitmasks for IOC3_K_WD & IOC3_M_WD */
+#define KM_WD_WRT_DATA  0x000000ff      /* write to keyboard/mouse port */
+#define KM_WD_WRT_DATA_SHIFT 0
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN    0x01    /* char(s) lost */
+#define RXSB_PAR_ERR    0x02    /* parity error */
+#define RXSB_FRAME_ERR  0x04    /* framing error */
+#define RXSB_BREAK      0x08    /* break character */
+#define RXSB_CTS        0x10    /* state of CTS */
+#define RXSB_DCD        0x20    /* state of DCD */
+#define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
+#define TXCB_INVALID    0x00    /* byte is invalid */
+#define TXCB_VALID      0x40    /* byte is valid */
+#define TXCB_MCR        0x80    /* data<7:0> to modem control register */
+#define TXCB_DELAY      0xc0    /* delay data<7:0> mSec */
+
+/* bitmasks for IOC3_SBBR_L */
+#define SBBR_L_SIZE     0x00000001      /* 0 == 1KB rings, 1 == 4KB rings */
+#define SBBR_L_BASE     0xfffff000      /* lower serial ring base addr */
+
+/* bitmasks for IOC3_SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
+#define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
+#define SSCR_HFC_EN     0x00020000      /* hardware flow control enabled */
+#define SSCR_RX_RING_DCD 0x00040000     /* post RX record on delta-DCD */
+#define SSCR_RX_RING_CTS 0x00080000     /* post RX record on delta-CTS */
+#define SSCR_HIGH_SPD   0x00100000      /* 4X speed */
+#define SSCR_DIAG       0x00200000      /* bypass clock divider for sim */
+#define SSCR_RX_DRAIN   0x08000000      /* drain RX buffer to memory */
+#define SSCR_DMA_EN     0x10000000      /* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE  0x20000000      /* pause DMA */
+#define SSCR_PAUSE_STATE 0x40000000     /* sets when PAUSE takes effect */
+#define SSCR_RESET      0x80000000      /* reset DMA channels */
+
+/* all producer/comsumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K 0x00000ff8     /* for 4K buffers */
+#define PROD_CONS_PTR_1K 0x000003f8     /* for 1K buffers */
+#define PROD_CONS_PTR_OFF 3
+
+/* bitmasks for IOC3_SRCIR_<A:B> */
+#define SRCIR_ARM       0x80000000      /* arm RX timer */
+
+/* bitmasks for IOC3_SRPIR_<A:B> */
+#define SRPIR_BYTE_CNT  0x07000000      /* bytes in packer */
+#define SRPIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_STCIR_<A:B> */
+#define STCIR_BYTE_CNT  0x0f000000      /* bytes in unpacker */
+#define STCIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_SHADOW_<A:B> */
+#define SHADOW_DR       0x00000001      /* data ready */
+#define SHADOW_OE       0x00000002      /* overrun error */
+#define SHADOW_PE       0x00000004      /* parity error */
+#define SHADOW_FE       0x00000008      /* framing error */
+#define SHADOW_BI       0x00000010      /* break interrupt */
+#define SHADOW_THRE     0x00000020      /* transmit holding register empty */
+#define SHADOW_TEMT     0x00000040      /* transmit shift register empty */
+#define SHADOW_RFCE     0x00000080      /* char in RX fifo has an error */
+#define SHADOW_DCTS     0x00010000      /* delta clear to send */
+#define SHADOW_DDCD     0x00080000      /* delta data carrier detect */
+#define SHADOW_CTS      0x00100000      /* clear to send */
+#define SHADOW_DCD      0x00800000      /* data carrier detect */
+#define SHADOW_DTR      0x01000000      /* data terminal ready */
+#define SHADOW_RTS      0x02000000      /* request to send */
+#define SHADOW_OUT1     0x04000000      /* 16550 OUT1 bit */
+#define SHADOW_OUT2     0x08000000      /* 16550 OUT2 bit */
+#define SHADOW_LOOP     0x10000000      /* loopback enabled */
+
+/* bitmasks for IOC3_SRTR_<A:B> */
+#define SRTR_CNT        0x00000fff      /* reload value for RX timer */
+#define SRTR_CNT_VAL    0x0fff0000      /* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT 16
+#define SRTR_HZ         16000   /* SRTR clock frequency */
+
+/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
+#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
+#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
+#define SIO_IR_SB_TX_MT         0x00000200      /* */
+#define SIO_IR_SB_RX_FULL       0x00000400      /* */
+#define SIO_IR_SB_RX_HIGH       0x00000800      /* */
+#define SIO_IR_SB_RX_TIMER      0x00001000      /* */
+#define SIO_IR_SB_DELTA_DCD     0x00002000      /* */
+#define SIO_IR_SB_DELTA_CTS     0x00004000      /* */
+#define SIO_IR_SB_INT           0x00008000      /* */
+#define SIO_IR_SB_TX_EXPLICIT   0x00010000      /* */
+#define SIO_IR_SB_MEMERR        0x00020000      /* */
+#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
+#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
+#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
+#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
+#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
+#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
+#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT    28
+
+/* per device interrupt masks */
+#define SIO_IR_SA               (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
+                                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
+                                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
+                                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
+                                 SIO_IR_SA_MEMERR)
+#define SIO_IR_SB               (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
+                                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
+                                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
+                                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
+                                 SIO_IR_SB_MEMERR)
+#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* macro to load pending interrupts */
+#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
+                                 PCI_INW(&((mem)->sio_ies_ro)))
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_SIO_RESET        0x00000001      /* reset the SIO */
+#define SIO_CR_SER_A_BASE       0x000000fe      /* DMA poll addr port A */
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE       0x00007f00      /* DMA poll addr port B */
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_SR_CMD_PULSE        0x00078000      /* byte bus strobe length */
+#define SIO_CR_CMD_PULSE_SHIFT  15
+#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA     0x00000000
+#define SIO_CR_ARB_DIAG_RXA     0x00080000
+#define SIO_CR_ARB_DIAG_TXB     0x00100000
+#define SIO_CR_ARB_DIAG_RXB     0x00180000
+#define SIO_CR_ARB_DIAG_PP      0x00200000
+#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
+
+/* bitmasks for INT_OUT */
+#define INT_OUT_COUNT   0x0000ffff      /* pulse interval timer */
+#define INT_OUT_MODE    0x00070000      /* mode mask */
+#define INT_OUT_MODE_0  0x00000000      /* set output to 0 */
+#define INT_OUT_MODE_1  0x00040000      /* set output to 1 */
+#define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
+#define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
+#define INT_OUT_MODE_SQW 0x00070000     /* toggle output every interval */
+#define INT_OUT_DIAG    0x40000000      /* diag mode */
+#define INT_OUT_INT_OUT 0x80000000      /* current state of INT_OUT */
+
+/* time constants for INT_OUT */
+#define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
+#define INT_OUT_TICKS_PER_PULSE 3       /* outgoing pulse lasts 3 ticks */
+#define INT_OUT_US_TO_COUNT(x)          /* convert uS to a count value */ \
+        (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *       \
+         100 / INT_OUT_NS_PER_TICK - 1)
+#define INT_OUT_COUNT_TO_US(x)          /* convert count value to uS */ \
+        (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
+#define INT_OUT_MIN_TICKS 3     /* min period is width of pulse in "ticks" */
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT         /* largest possible count */
+
+/* bitmasks for GPCR */
+#define GPCR_DIR        0x000000ff      /* tristate pin input or output */
+#define GPCR_DIR_PIN(x) (1<<(x))        /* access one of the DIR bits */
+#define GPCR_EDGE       0x000f0000      /* extint edge or level sensitive */
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
+
+/* values for GPCR */
+#define GPCR_INT_OUT_EN 0x00100000      /* enable INT_OUT to pin 0 */
+#define GPCR_MLAN_EN    0x00200000      /* enable MCR to pin 8 */
+#define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
+#define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
+#define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN      5       /* GIO pin controlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin controlling uart b mode select */
+#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin controlling uart a mode select */
+
+#define EMCR_DUPLEX             0x00000001
+#define EMCR_PROMISC            0x00000002
+#define EMCR_PADEN              0x00000004
+#define EMCR_RXOFF_MASK         0x000001f8
+#define EMCR_RXOFF_SHIFT        3
+#define EMCR_RAMPAR             0x00000200
+#define EMCR_BADPAR             0x00000800
+#define EMCR_BUFSIZ             0x00001000
+#define EMCR_TXDMAEN            0x00002000
+#define EMCR_TXEN               0x00004000
+#define EMCR_RXDMAEN            0x00008000
+#define EMCR_RXEN               0x00010000
+#define EMCR_LOOPBACK           0x00020000
+#define EMCR_ARB_DIAG           0x001c0000
+#define EMCR_ARB_DIAG_IDLE      0x00200000
+#define EMCR_RST                0x80000000
+
+#define EISR_RXTIMERINT         0x00000001
+#define EISR_RXTHRESHINT        0x00000002
+#define EISR_RXOFLO             0x00000004
+#define EISR_RXBUFOFLO          0x00000008
+#define EISR_RXMEMERR           0x00000010
+#define EISR_RXPARERR           0x00000020
+#define EISR_TXEMPTY            0x00010000
+#define EISR_TXRTRY             0x00020000
+#define EISR_TXEXDEF            0x00040000
+#define EISR_TXLCOL             0x00080000
+#define EISR_TXGIANT            0x00100000
+#define EISR_TXBUFUFLO          0x00200000
+#define EISR_TXEXPLICIT         0x00400000
+#define EISR_TXCOLLWRAP         0x00800000
+#define EISR_TXDEFERWRAP        0x01000000
+#define EISR_TXMEMERR           0x02000000
+#define EISR_TXPARERR           0x04000000
+
+#define ERCSR_THRESH_MASK       0x000001ff      /* enet RX threshold */
+#define ERCSR_RX_TMR            0x40000000      /* simulation only */
+#define ERCSR_DIAG_OFLO         0x80000000      /* simulation only */
+
+#define ERBR_ALIGNMENT          4096
+#define ERBR_L_RXRINGBASE_MASK  0xfffff000
+
+#define ERBAR_BARRIER_BIT       0x0100
+#define ERBAR_RXBARR_MASK       0xffff0000
+#define ERBAR_RXBARR_SHIFT      16
+
+#define ERCIR_RXCONSUME_MASK    0x00000fff
+
+#define ERPIR_RXPRODUCE_MASK    0x00000fff
+#define ERPIR_ARM               0x80000000
+
+#define ERTR_CNT_MASK           0x000007ff
+
+#define ETCSR_IPGT_MASK         0x0000007f
+#define ETCSR_IPGR1_MASK        0x00007f00
+#define ETCSR_IPGR1_SHIFT       8
+#define ETCSR_IPGR2_MASK        0x007f0000
+#define ETCSR_IPGR2_SHIFT       16
+#define ETCSR_NOTXCLK           0x80000000
+
+#define ETCDC_COLLCNT_MASK      0x0000ffff
+#define ETCDC_DEFERCNT_MASK     0xffff0000
+#define ETCDC_DEFERCNT_SHIFT    16
+
+#define ETBR_ALIGNMENT          (64*1024)
+#define ETBR_L_RINGSZ_MASK      0x00000001
+#define ETBR_L_RINGSZ128        0
+#define ETBR_L_RINGSZ512        1
+#define ETBR_L_TXRINGBASE_MASK  0xffffc000
+
+#define ETCIR_TXCONSUME_MASK    0x0000ffff
+#define ETCIR_IDLE              0x80000000
+
+#define ETPIR_TXPRODUCE_MASK    0x0000ffff
+
+#define EBIR_TXBUFPROD_MASK     0x0000001f
+#define EBIR_TXBUFCONS_MASK     0x00001f00
+#define EBIR_TXBUFCONS_SHIFT    8
+#define EBIR_RXBUFPROD_MASK     0x007fc000
+#define EBIR_RXBUFPROD_SHIFT    14
+#define EBIR_RXBUFCONS_MASK     0xff800000
+#define EBIR_RXBUFCONS_SHIFT    23
+
+#define MICR_REGADDR_MASK       0x0000001f
+#define MICR_PHYADDR_MASK       0x000003e0
+#define MICR_PHYADDR_SHIFT      5
+#define MICR_READTRIG           0x00000400
+#define MICR_BUSY               0x00000800
+
+#define MIDR_DATA_MASK          0x0000ffff
+
+#define ERXBUF_IPCKSUM_MASK     0x0000ffff
+#define ERXBUF_BYTECNT_MASK     0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT    16
+#define ERXBUF_V                0x80000000
+
+#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
+#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
+#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
+#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
+#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
+#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
+#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
+#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
+#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
+#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
+#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
+#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
+
+#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
+#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
+#define ETXD_D0V                0x00010000      /* data 0 valid */
+#define ETXD_B1V                0x00020000      /* buf 1 valid */
+#define ETXD_B2V                0x00040000      /* buf 2 valid */
+#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
+#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT       20
+
+#define ETXD_D0CNT_MASK         0x0000007f
+#define ETXD_B1CNT_MASK         0x0007ff00
+#define ETXD_B1CNT_SHIFT        8
+#define ETXD_B2CNT_MASK         0x7ff00000
+#define ETXD_B2CNT_SHIFT        20
+
+typedef enum ioc3_subdevs_e {
+    ioc3_subdev_ether,
+    ioc3_subdev_generic,
+    ioc3_subdev_nic,
+    ioc3_subdev_kbms,
+    ioc3_subdev_ttya,
+    ioc3_subdev_ttyb,
+    ioc3_subdev_ecpp,
+    ioc3_subdev_rt,
+    ioc3_nsubdevs
+} ioc3_subdev_t;
+
+/* subdevice disable bits,
+ * from the standard INFO_LBL_SUBDEVS
+ */
+#define IOC3_SDB_ETHER          (1<<ioc3_subdev_ether)
+#define IOC3_SDB_GENERIC        (1<<ioc3_subdev_generic)
+#define IOC3_SDB_NIC            (1<<ioc3_subdev_nic)
+#define IOC3_SDB_KBMS           (1<<ioc3_subdev_kbms)
+#define IOC3_SDB_TTYA           (1<<ioc3_subdev_ttya)
+#define IOC3_SDB_TTYB           (1<<ioc3_subdev_ttyb)
+#define IOC3_SDB_ECPP           (1<<ioc3_subdev_ecpp)
+#define IOC3_SDB_RT             (1<<ioc3_subdev_rt)
+
+#define IOC3_ALL_SUBDEVS        ((1<<ioc3_nsubdevs)-1)
+
+#define IOC3_SDB_SERIAL         (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
+
+#define IOC3_STD_SUBDEVS        IOC3_ALL_SUBDEVS
+
+#define IOC3_INTA_SUBDEVS       IOC3_SDB_ETHER
+#define IOC3_INTB_SUBDEVS       (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
+
+#endif /* _IOC3_H */
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
new file mode 100644
index 000000000000..d028e28d6239
--- /dev/null
+++ b/include/asm-mips/sn/klconfig.h
@@ -0,0 +1,980 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLCONFIG_H
+#define _ASM_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+/*
+ * WARNING:
+ *      Certain assembly language routines (notably xxxxx.s) in the IP27PROM
+ *      will depend on the format of the data structures in this file.  In
+ *      most cases, rearranging the fields can seriously break things.
+ *      Adding fields in the beginning or middle can also break things.
+ *      Add fields if necessary, to the end of a struct in such a way
+ *      that offsets of existing fields do not change.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/types.h>
+
+#if defined(CONFIG_SGI_IP27)
+
+#include <asm/sn/sn0/addrs.h>
+//#include <sys/SN/router.h>
+// XXX Stolen from <sys/SN/router.h>:
+#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+#include <asm/sn/sn0/sn0_fru.h>
+//#include <sys/graph.h>
+//#include <sys/xtalk/xbow.h>
+
+#elif defined(CONFIG_SGI_IP35)
+
+#include <asm/sn/sn1/addrs.h>
+#include <sys/sn/router.h>
+#include <sys/graph.h>
+#include <asm/xtalk/xbow.h>
+
+#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
+#include <asm/sn/agent.h>
+#include <asm/arc/types.h>
+#include <asm/arc/hinv.h>
+#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
+// The hack file has to be before vector and after sn0_fru....
+#include <asm/hack.h>
+#include <asm/sn/vector.h>
+#include <asm/xtalk/xtalk.h>
+#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
+#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
+
+#define KLCFGINFO_MAGIC 0xbeedbabe
+
+#ifdef FRUTEST
+typedef u64 klconf_off_t;
+#else
+typedef s32 klconf_off_t;
+#endif
+
+/*
+ * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
+ */
+#if 0
+#define RAMBASE                 0
+#define ARCSSPB_OFF             0x1000 /* shift it to sys/arcs/spb.h */
+
+#define OFF_HWGRAPH             0
+#endif
+
+#define MAX_MODULE_ID           255
+#define SIZE_PAD                4096 /* 4k padding for structures */
+/*
+ * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
+ * 2 Midplanes assuming no pci card cages
+ */
+#define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
+
+/* XXX if each node is guranteed to have some memory */
+
+#define MAX_PCI_DEVS            8
+
+/* lboard_t->brd_flags fields */
+/* All bits in this field are currently used. Try the pad fields if
+   you need more flag bits */
+
+#define ENABLE_BOARD            0x01
+#define FAILED_BOARD            0x02
+#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
+                                           are discovered twice. Use one of them */
+#define VISITED_BOARD           0x08    /* Used for compact hub numbering. */
+#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
+#define GLOBAL_MASTER_IO6       0x20
+#define THIRD_NIC_PRESENT       0x40    /* for future use */
+#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
+
+/* klinfo->flags fields */
+
+#define KLINFO_ENABLE           0x01    /* This component is enabled */
+#define KLINFO_FAILED           0x02    /* This component failed */
+#define KLINFO_DEVICE           0x04    /* This component is a device */
+#define KLINFO_VISITED          0x08    /* This component has been visited */
+#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
+#define KLINFO_INSTALL          0x20    /* Install a driver */
+#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
+#define IS_CONSOLE_IOC3(i)      ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
+
+#define GB2             0x80000000
+
+#define MAX_RSV_PTRS    32
+
+/* Structures to manage various data storage areas */
+/* The numbers must be contiguous since the array index i
+   is used in the code to allocate various areas.
+*/
+
+#define BOARD_STRUCT            0
+#define COMPONENT_STRUCT        1
+#define ERRINFO_STRUCT          2
+#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT           3
+
+
+typedef struct console_s {
+#if defined(CONFIG_SGI_IO)      /* FIXME */
+        __psunsigned_t  uart_base;
+        __psunsigned_t  config_base;
+        __psunsigned_t  memory_base;
+#else
+        unsigned long   uart_base;
+        unsigned long   config_base;
+        unsigned long   memory_base;
+#endif
+        short           baud;
+        short           flag;
+        int             type;
+        nasid_t         nasid;
+        char            wid;
+        char            npci;
+        nic_t           baseio_nic;
+} console_t;
+
+typedef struct klc_malloc_hdr {
+        klconf_off_t km_base;
+        klconf_off_t km_limit;
+        klconf_off_t km_current;
+} klc_malloc_hdr_t;
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
+        u32             ch_version;    /* structure version number */
+        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
+        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
+        klconf_off_t    ch_board_info;  /* the link list of boards */
+        console_t       ch_cons_info;   /* address info of the console */
+        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
+        confidence_t    ch_sw_belief;   /* confidence that software is bad*/
+        confidence_t    ch_sn0net_belief; /* confidence that sn0net is bad */
+} kl_config_hdr_t;
+
+
+#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#if 0
+#define KL_CONFIG_MALLOC_HDR(_nasid) \
+                                (KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
+#endif
+#define KL_CONFIG_INFO_OFFSET(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                         \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+
+#define KL_CONFIG_INFO(_nasid)                                          \
+        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
+         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
+         0)
+#define KL_CONFIG_MAGIC(_nasid)         (KL_CONFIG_HDR(_nasid)->ch_magic)
+
+#define KL_CONFIG_CHECK_MAGIC(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+
+#define KL_CONFIG_HDR_INIT_MAGIC(_nasid)        \
+                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+
+/* --- New Macros for the changed kl_config_hdr_t structure --- */
+
+#if defined(CONFIG_SGI_IO)
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+                        ((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
+#else
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+                        (unsigned long)_k + (_k->ch_malloc_hdr_off)))
+#endif
+
+#define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
+
+#if defined(CONFIG_SGI_IO)
+#define PTR_CH_CONS_INFO(_k)    ((console_t *)\
+                        ((__psunsigned_t)_k + (_k->ch_cons_off)))
+#else
+#define PTR_CH_CONS_INFO(_k)    ((console_t *)\
+                        ((unsigned long)_k + (_k->ch_cons_off)))
+#endif
+
+#define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
+
+/* ------------------------------------------------------------- */
+
+#define KL_CONFIG_INFO_START(_nasid)    \
+        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+
+#define KL_CONFIG_BOARD_NASID(_brd)     ((_brd)->brd_nasid)
+#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)    ((_brd)->brd_next = (_off))
+
+#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
+
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link)  \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+
+#define XBOW_PORT_IO     0x1
+#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_ENABLE 0x4
+
+#define SN0_PORT_FENCE_SHFT     0
+#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
+ * First board info on the remote node. The remote node list is
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ *
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error
+ * information specific to the COMPONENT is present in the respective
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ *
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+/*
+ * Values for CPU types
+ */
+#define KL_CPU_R4000            0x1     /* Standard R4000 */
+#define KL_CPU_TFP              0x2     /* TFP processor */
+#define KL_CPU_R10000           0x3     /* R10000 (T5) */
+#define KL_CPU_NONE             (-1)    /* no cpu present in slot */
+
+/*
+ * IP27 BOARD classes
+ */
+
+#define KLCLASS_MASK    0xf0
+#define KLCLASS_NONE    0x00
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU     KLCLASS_NODE
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
+                                            and the non-graphics widget boards */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_GFX     0x50            /* graphics boards */
+
+#define KLCLASS_PSEUDO_GFX      0x60    /* HDTV type cards that use a gfx
+                                         * hw ifc to xtalk and are not gfx
+                                         * class for sw purposes */
+
+#define KLCLASS_MAX     7               /* Bump this if a new CLASS is added */
+#define KLTYPE_MAX      10              /* Bump this if a new CLASS is added */
+
+#define KLCLASS_UNKNOWN 0xf0
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+/*
+ * IP27 board types
+ */
+
+#define KLTYPE_MASK     0x0f
+#define KLTYPE_NONE     0x00
+#define KLTYPE_EMPTY    0x00
+
+#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
+#define KLTYPE_IP27     (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
+
+#define KLTYPE_WEIRDIO  (KLCLASS_IO  | 0x0)
+#define KLTYPE_BASEIO   (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
+#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_4CHSCSI  (KLCLASS_IO  | 0x2)
+#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
+#define KLTYPE_UNUSED   (KLCLASS_IO  | 0x5) /* XXX UNUSED */
+#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_PCI      KLTYPE_HAROLD
+#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
+#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+
+#define KLTYPE_GFX      (KLCLASS_GFX | 0x0) /* unknown graphics type */
+#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
+#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
+
+#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
+#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+
+#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
+#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
+#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_PBRICK_XBOW      (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_IBRICK           (KLCLASS_IOBRICK | 0x1)
+#define KLTYPE_PBRICK           (KLCLASS_IOBRICK | 0x2)
+#define KLTYPE_XBRICK           (KLCLASS_IOBRICK | 0x3)
+
+#define KLTYPE_PBRICK_BRIDGE    KLTYPE_PBRICK
+
+/* The value of type should be more than 8 so that hinv prints
+ * out the board name from the NIC string. For values less than
+ * 8 the name of the board needs to be hard coded in a few places.
+ * When bringup started nic names had not standardized and so we
+ * had to hard code. (For people interested in history.)
+ */
+#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
+
+#define KLTYPE_UNKNOWN  (KLCLASS_UNKNOWN | 0xf)
+
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+#define IS_MIO_PRESENT(l)       ((l->brd_type == KLTYPE_BASEIO) && \
+                                 (l->brd_flags & SECOND_NIC_PRESENT))
+#define IS_MIO_IOC3(l,n)        (IS_MIO_PRESENT(l) && (n > 2))
+
+/*
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+#define LOCAL_BOARD 1
+#define REMOTE_BOARD 2
+
+#define LBOARD_STRUCT_VERSION   2
+
+typedef struct lboard_s {
+        klconf_off_t    brd_next;         /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        moduleid_t      brd_module;       /* module to which it belongs */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
+        struct lboard_s *brd_parent;      /* Logical parent for this brd */
+        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
+        confidence_t    brd_confidence;   /* confidence that the board is bad */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        char            brd_name[32];
+} lboard_t;
+
+
+/*
+ *      Make sure we pass back the calias space address for local boards.
+ *      klconfig board traversal and error structure extraction defines.
+ */
+
+#define BOARD_SLOT(_brd)        ((_brd)->brd_slot)
+
+#define KLCF_CLASS(_brd)        KLCLASS((_brd)->brd_type)
+#define KLCF_TYPE(_brd)         KLTYPE((_brd)->brd_type)
+#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
+#define KLCF_MODULE_ID(_brd)    ((_brd)->brd_module)
+
+#ifdef FRUTEST
+
+#define KLCF_NEXT(_brd)                 ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next):  NULL)
+#define KLCF_COMP(_brd, _ndx)           (klinfo_t *)((_brd)->brd_compts[(_ndx)])
+#define KLCF_COMP_ERROR(_brd, _comp)    (_brd = _brd , (_comp)->errinfo)
+
+#else
+
+#define KLCF_NEXT(_brd)         \
+        ((_brd)->brd_next ?     \
+         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
+         NULL)
+#define KLCF_COMP(_brd, _ndx)   \
+                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
+                                               (_brd)->brd_compts[(_ndx)]))
+
+#define KLCF_COMP_ERROR(_brd, _comp)    \
+               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+
+#endif
+
+#define KLCF_COMP_TYPE(_comp)   ((_comp)->struct_type)
+#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
+
+
+
+/*
+ * Generic info structure. This stores common info about a
+ * component.
+ */
+
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
+        char            pad1;             /* pad out structure. */
+        char            pad2;             /* pad out structure. */
+        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+#define KLCONFIG_INFO_ENABLED(_i)       ((_i)->flags & KLINFO_ENABLE)
+/*
+ * Component structures.
+ * Following are the currently identified components:
+ *      CPU, HUB, MEM_BANK,
+ *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
+ *      ROUTER
+ *      GRAPHICS
+ */
+#define KLSTRUCT_UNKNOWN        0
+#define KLSTRUCT_CPU            1
+#define KLSTRUCT_HUB            2
+#define KLSTRUCT_MEMBNK         3
+#define KLSTRUCT_XBOW           4
+#define KLSTRUCT_BRI            5
+#define KLSTRUCT_IOC3           6
+#define KLSTRUCT_PCI            7
+#define KLSTRUCT_VME            8
+#define KLSTRUCT_ROU            9
+#define KLSTRUCT_GFX            10
+#define KLSTRUCT_SCSI           11
+#define KLSTRUCT_FDDI           12
+#define KLSTRUCT_MIO            13
+#define KLSTRUCT_DISK           14
+#define KLSTRUCT_TAPE           15
+#define KLSTRUCT_CDROM          16
+#define KLSTRUCT_HUB_UART       17
+#define KLSTRUCT_IOC3ENET       18
+#define KLSTRUCT_IOC3UART       19
+#define KLSTRUCT_UNUSED         20 /* XXX UNUSED */
+#define KLSTRUCT_IOC3PCKM       21
+#define KLSTRUCT_RAD            22
+#define KLSTRUCT_HUB_TTY        23
+#define KLSTRUCT_IOC3_TTY       24
+
+/* Early Access IO proms are compatible
+   only with KLSTRUCT values upto 24. */
+
+#define KLSTRUCT_FIBERCHANNEL   25
+#define KLSTRUCT_MOD_SERIAL_NUM 26
+#define KLSTRUCT_IOC3MS         27
+#define KLSTRUCT_TPU            28
+#define KLSTRUCT_GSN_A          29
+#define KLSTRUCT_GSN_B          30
+#define KLSTRUCT_XTHD           31
+
+/*
+ * These are the indices of various components within a lboard structure.
+ */
+
+#define IP27_CPU0_INDEX 0
+#define IP27_CPU1_INDEX 1
+#define IP27_HUB_INDEX 2
+#define IP27_MEM_INDEX 3
+
+#define BASEIO_BRIDGE_INDEX 0
+#define BASEIO_IOC3_INDEX 1
+#define BASEIO_SCSI1_INDEX 2
+#define BASEIO_SCSI2_INDEX 3
+
+#define MIDPLANE_XBOW_INDEX 0
+#define ROUTER_COMPONENT_INDEX 0
+
+#define CH4SCSI_BRIDGE_INDEX 0
+
+/* Info holders for various hardware components */
+
+typedef u64 *pci_t;
+typedef u64 *vmeb_t;
+typedef u64 *vmed_t;
+typedef u64 *fddi_t;
+typedef u64 *scsi_t;
+typedef u64 *mio_t;
+typedef u64 *graphics_t;
+typedef u64 *router_t;
+
+/*
+ * The port info in ip27_cfg area translates to a lboart_t in the
+ * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
+ * is stored in terms of a nasid and a offset from start of KLCONFIG
+ * area  on that nasid.
+ */
+typedef struct klport_s {
+        nasid_t         port_nasid;
+        unsigned char   port_flag;
+        klconf_off_t    port_offset;
+} klport_t;
+
+#if 0
+/*
+ * This is very similar to the klport_s but instead of having a componant
+ * offset it has a board offset.
+ */
+typedef struct klxbow_port_s {
+        nasid_t         port_nasid;
+        unsigned char   port_flag;
+        klconf_off_t    board_offset;
+} klxbow_port_t;
+#endif
+
+typedef struct klcpu_s {                          /* CPU */
+        klinfo_t        cpu_info;
+        unsigned short  cpu_prid;       /* Processor PRID value */
+        unsigned short  cpu_fpirr;      /* FPU IRR value */
+        unsigned short  cpu_speed;      /* Speed in MHZ */
+        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
+        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
+} klcpu_t ;
+
+#define CPU_STRUCT_VERSION   2
+
+typedef struct klhub_s {                        /* HUB */
+        klinfo_t        hub_info;
+        uint            hub_flags;              /* PCFG_HUB_xxx flags */
+        klport_t        hub_port;               /* hub is connected to this */
+        nic_t           hub_box_nic;            /* nic of containing box */
+        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
+        u64             hub_speed;              /* Speed of hub in HZ */
+} klhub_t ;
+
+typedef struct klhub_uart_s {                   /* HUB */
+        klinfo_t        hubuart_info;
+        uint            hubuart_flags;          /* PCFG_HUB_xxx flags */
+        nic_t           hubuart_box_nic;        /* nic of containing box */
+} klhub_uart_t ;
+
+#define MEMORY_STRUCT_VERSION   2
+
+typedef struct klmembnk_s {                     /* MEMORY BANK */
+        klinfo_t        membnk_info;
+        short           membnk_memsz;           /* Total memory in megabytes */
+        short           membnk_dimm_select; /* bank to physical addr mapping*/
+        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
+        short           membnk_attr;
+} klmembnk_t ;
+
+#define KLCONFIG_MEMBNK_SIZE(_info, _bank)      \
+                            ((_info)->membnk_bnksz[(_bank)])
+
+
+#define MEMBNK_PREMIUM 1
+#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)   \
+                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+
+#define MAX_SERIAL_NUM_SIZE 10
+
+typedef struct klmod_serial_num_s {
+      klinfo_t        snum_info;
+      union {
+              char snum_str[MAX_SERIAL_NUM_SIZE];
+              unsigned long long       snum_int;
+      } snum;
+} klmod_serial_num_t;
+
+/* Macros needed to access serial number structure in lboard_t.
+   Hard coded values are necessary since we cannot treat
+   serial number struct as a component without losing compatibility
+   between prom versions. */
+
+#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
+                                KLCF_COMP(_l, _l->brd_numcompts))
+
+#define MAX_XBOW_LINKS 16
+
+typedef struct klxbow_s {                          /* XBOW */
+        klinfo_t        xbow_info ;
+        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
+        int             xbow_master_hub_link;
+        /* type of brd connected+component struct ptr+flags */
+} klxbow_t ;
+
+#define MAX_PCI_SLOTS 8
+
+typedef struct klpci_device_s {
+        s32     pci_device_id;  /* 32 bits of vendor/device ID. */
+        s32     pci_device_pad; /* 32 bits of padding. */
+} klpci_device_t;
+
+#define BRIDGE_STRUCT_VERSION   2
+
+typedef struct klbri_s {                          /* BRIDGE */
+        klinfo_t        bri_info ;
+        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
+        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+        pci_t           pci_specific  ;    /* PCI Board config info */
+        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
+        klconf_off_t    bri_mfg_nic ;
+} klbri_t ;
+
+#define MAX_IOC3_TTY    2
+
+typedef struct klioc3_s {                          /* IOC3 */
+        klinfo_t        ioc3_info ;
+        unsigned char   ioc3_ssram ;        /* Info about ssram */
+        unsigned char   ioc3_nvram ;        /* Info about nvram */
+        klinfo_t        ioc3_superio ;      /* Info about superio */
+        klconf_off_t    ioc3_tty_off ;
+        klinfo_t        ioc3_enet ;
+        klconf_off_t    ioc3_enet_off ;
+        klconf_off_t    ioc3_kbd_off ;
+} klioc3_t ;
+
+#define MAX_VME_SLOTS 8
+
+typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
+        klinfo_t        vmeb_info ;
+        vmeb_t          vmeb_specific ;
+        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmeb_t ;
+
+typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+        klinfo_t        vmed_info ;
+        vmed_t          vmed_specific ;
+        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmed_t ;
+
+#define ROUTER_VECTOR_VERS      2
+
+/* XXX - Don't we need the number of ports here?!? */
+typedef struct klrou_s {                          /* ROUTER */
+        klinfo_t        rou_info ;
+        uint            rou_flags ;           /* PCFG_ROUTER_xxx flags */
+        nic_t           rou_box_nic ;         /* nic of the containing module */
+        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
+        u64     rou_vector;       /* vector from master node */
+} klrou_t ;
+
+/*
+ *  Graphics Controller/Device
+ *
+ *  (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
+ *  used a couple different structures to store graphics information.
+ *  For compatibility reasons, the newer data structure preserves some
+ *  of the layout so that fields that are used in the old versions remain
+ *  in the same place (with the same info).  Determination of what version
+ *  of this structure we have is done by checking the cookie field.
+ */
+#define KLGFX_COOKIE    0x0c0de000
+
+typedef struct klgfx_s {                /* GRAPHICS Device */
+        klinfo_t        gfx_info;
+        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
+        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
+        uint            cookie;         /* for compatibility with older proms */
+        uint            moduleslot;
+        struct klgfx_s  *gfx_next_pipe;
+        graphics_t      gfx_specific;
+        klconf_off_t    pad0;           /* for compatibility with older proms */
+        klconf_off_t    gfx_mfg_nic;
+} klgfx_t;
+
+typedef struct klxthd_s {
+        klinfo_t        xthd_info ;
+        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
+} klxthd_t ;
+
+typedef struct kltpu_s {                     /* TPU board */
+        klinfo_t        tpu_info ;
+        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
+} kltpu_t ;
+
+typedef struct klgsn_s {                     /* GSN board */
+        klinfo_t        gsn_info ;
+        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
+} klgsn_t ;
+
+#define MAX_SCSI_DEVS 16
+
+/*
+ * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
+ * to allocate space of type COMPONENT. Make sure that if the size of
+ * any other component struct becomes more than this, then redefine
+ * that as the size to be klmalloced.
+ */
+
+typedef struct klscsi_s {                          /* SCSI Controller */
+        klinfo_t        scsi_info ;
+        scsi_t          scsi_specific   ;
+        unsigned char   scsi_numdevs ;
+        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
+} klscsi_t ;
+
+typedef struct klscdev_s {                          /* SCSI device */
+        klinfo_t        scdev_info ;
+        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
+} klscdev_t ;
+
+typedef struct klttydev_s {                          /* TTY device */
+        klinfo_t        ttydev_info ;
+        struct terminal_data *ttydev_cfg ; /* driver fills up this */
+} klttydev_t ;
+
+typedef struct klenetdev_s {                          /* ENET device */
+        klinfo_t        enetdev_info ;
+        struct net_data *enetdev_cfg ; /* driver fills up this */
+} klenetdev_t ;
+
+typedef struct klkbddev_s {                          /* KBD device */
+        klinfo_t        kbddev_info ;
+        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
+} klkbddev_t ;
+
+typedef struct klmsdev_s {                          /* mouse device */
+        klinfo_t        msdev_info ;
+        void            *msdev_cfg ;
+} klmsdev_t ;
+
+#define MAX_FDDI_DEVS 10 /* XXX Is this true */
+
+typedef struct klfddi_s {                          /* FDDI */
+        klinfo_t        fddi_info ;
+        fddi_t          fddi_specific ;
+        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
+} klfddi_t ;
+
+typedef struct klmio_s {                          /* MIO */
+        klinfo_t        mio_info ;
+        mio_t           mio_specific   ;
+} klmio_t ;
+
+
+typedef union klcomp_s {
+        klcpu_t         kc_cpu;
+        klhub_t         kc_hub;
+        klmembnk_t      kc_mem;
+        klxbow_t        kc_xbow;
+        klbri_t         kc_bri;
+        klioc3_t        kc_ioc3;
+        klvmeb_t        kc_vmeb;
+        klvmed_t        kc_vmed;
+        klrou_t         kc_rou;
+        klgfx_t         kc_gfx;
+        klscsi_t        kc_scsi;
+        klscdev_t       kc_scsi_dev;
+        klfddi_t        kc_fddi;
+        klmio_t         kc_mio;
+        klmod_serial_num_t kc_snum ;
+} klcomp_t;
+
+typedef union kldev_s {      /* for device structure allocation */
+        klscdev_t       kc_scsi_dev ;
+        klttydev_t      kc_tty_dev ;
+        klenetdev_t     kc_enet_dev ;
+        klkbddev_t      kc_kbd_dev ;
+} kldev_t ;
+
+/* Data structure interface routines. TBD */
+
+/* Include launch info in this file itself? TBD */
+
+/*
+ * TBD - Can the ARCS and device driver related info also be included in the
+ * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
+ * structure, viz private to the IO4prom.
+ */
+
+/*
+ * TBD - Allocation issues.
+ *
+ * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
+ * errinfo and allocate from them, or have a single heap and allocate all
+ * structures from it. Debug is easier in the former method since we can
+ * dump all similar structs in one command, but there will be lots of holes,
+ * in memory and max limits are needed for number of structures.
+ * Another way to make it organized, is to have a union of all components
+ * and allocate a aligned chunk of memory greater than the biggest
+ * component.
+ */
+
+typedef union {
+        lboard_t *lbinfo ;
+} biptr_t ;
+
+
+#define BRI_PER_XBOW 6
+#define PCI_PER_BRI  8
+#define DEV_PER_PCI  16
+
+
+/* Virtual dipswitch values (starting from switch "7"): */
+
+#define VDS_NOGFX               0x8000  /* Don't enable gfx and autoboot */
+#define VDS_NOMP                0x100   /* Don't start slave processors */
+#define VDS_MANUMODE            0x80    /* Manufacturing mode */
+#define VDS_NOARB               0x40    /* No bootmaster arbitration */
+#define VDS_PODMODE             0x20    /* Go straight to POD mode */
+#define VDS_NO_DIAGS            0x10    /* Don't run any diags after BM arb */
+#define VDS_DEFAULTS            0x08    /* Use default environment values */
+#define VDS_NOMEMCLEAR          0x04    /* Don't run mem cfg code */
+#define VDS_2ND_IO4             0x02    /* Boot from the second IO4 */
+#define VDS_DEBUG_PROM          0x01    /* Print PROM debugging messages */
+
+/* external declarations of Linux kernel functions. */
+
+extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
+extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
+extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
+extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
+extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
+
+
+#if defined(CONFIG_SGI_IO)
+extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
+extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
+extern lboard_t *find_gfxpipe(int pipenum);
+extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
+extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
+                                               unsigned char brd_class);
+extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
+extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
+extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
+extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
+extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
+extern int      config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
+extern int      config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
+extern int      config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
+extern klcpu_t *get_cpuinfo(cpuid_t cpu);
+extern int      update_klcfg_cpuinfo(nasid_t, int);
+extern void     board_to_path(lboard_t *brd, char *path);
+extern moduleid_t get_module_id(nasid_t nasid);
+extern void     nic_name_convert(char *old_name, char *new_name);
+extern int      module_brds(nasid_t nasid, lboard_t **module_brds, int n);
+extern lboard_t *brd_from_key(ulong_t key);
+extern void     device_component_canonical_name_get(lboard_t *,klinfo_t *,
+                                                    char *);
+extern int      board_serial_number_get(lboard_t *,char *);
+extern int      is_master_baseio(nasid_t,moduleid_t,slotid_t);
+extern nasid_t  get_actual_nasid(lboard_t *brd) ;
+extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
+#else   /* CONFIG_SGI_IO */
+extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
+#endif  /* CONFIG_SGI_IO */
+
+#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
new file mode 100644
index 000000000000..f0efab1672ec
--- /dev/null
+++ b/include/asm-mips/sn/kldir.h
@@ -0,0 +1,248 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLDIR_H
+#define _ASM_SN_KLDIR_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_SGI_IO)
+#include <asm/hack.h>
+#endif
+
+/*
+ * The kldir memory area resides at a fixed place in each node's memory and
+ * provides pointers to most other IP27 memory areas.  This allows us to
+ * resize and/or relocate memory areas at a later time without breaking all
+ * firmware and kernels that use them.  Indices in the array are
+ * permanently dedicated to areas listed below.  Some memory areas (marked
+ * below) reside at a permanently fixed location, but are included in the
+ * directory for completeness.
+ */
+
+#define KLDIR_MAGIC             0x434d5f53505f5357
+
+/*
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)         +-----------------------------------------+
+ *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)         +-----------------------------------------+
+ *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)         +-----------------------------------------+
+ *                         |      IP27 CFG                           |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Graphics PROM                      |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)         +-----------------------------------------+
+ *                         |      SYMMON                             |
+ *                         |      (For UNIX Debug only)              |
+ * 0x34000 (208K)          +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x25000 (148K)          +-----------------------------------------+
+ *                         |      KLCONFIG - II (temp)               |
+ *                         |                                         |
+ *                         |    ----------------------------         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP27PROM, IO6PROM and IRIX.
+ *
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (32K)              |
+ *                         |                                         |
+ * 0x12000 (72K)           +-----------------------------------------+
+ *                         |      Unused                             |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Eframe area              |
+ * 0x11a00 (70.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Eframe area              |
+ * 0x11800 (70K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x11000 (68K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x10800  (66k)          +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      KLCONFIG - I (permanent) (48K)     |
+ *                         |                                         |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x4000 (16K)            +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)            +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)            +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)            +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)             +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)             +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)             +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x800  (2k)             +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x400 (1K)              +-----------------------------------------+
+ *                         |      Exception Handlers                 |
+ * 0x0   (0K)              +-----------------------------------------+
+ */
+
+#ifdef __ASSEMBLY__
+#define KLDIR_OFF_MAGIC                 0x00
+#define KLDIR_OFF_OFFSET                0x08
+#define KLDIR_OFF_POINTER               0x10
+#define KLDIR_OFF_SIZE                  0x18
+#define KLDIR_OFF_COUNT                 0x20
+#define KLDIR_OFF_STRIDE                0x28
+#endif /* __ASSEMBLY__ */
+
+#if !defined(CONFIG_SGI_IO)
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE               0x8000
+
+#if defined (PROM) || defined (SABLE)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP27
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET              0x2400
+#define IP27_LAUNCH_SIZE                0x400
+#define IP27_LAUNCH_COUNT               2
+#define IP27_LAUNCH_STRIDE              0x200
+
+#define IP27_KLCONFIG_OFFSET            0x4000
+#define IP27_KLCONFIG_SIZE              0xc000
+#define IP27_KLCONFIG_COUNT             1
+#define IP27_KLCONFIG_STRIDE            0
+
+#define IP27_NMI_OFFSET                 0x3000
+#define IP27_NMI_SIZE                   0x40
+#define IP27_NMI_COUNT                  2
+#define IP27_NMI_STRIDE                 0x40
+
+#define IP27_PI_ERROR_OFFSET            0x12000
+#define IP27_PI_ERROR_SIZE              0x4000
+#define IP27_PI_ERROR_COUNT             1
+#define IP27_PI_ERROR_STRIDE            0
+
+#define IP27_SYMMON_STK_OFFSET          0x25000
+#define IP27_SYMMON_STK_SIZE            0xe000
+#define IP27_SYMMON_STK_COUNT           2
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE          0x7000
+
+#define IP27_FREEMEM_OFFSET             0x19000
+#define IP27_FREEMEM_SIZE               -1
+#define IP27_FREEMEM_COUNT              1
+#define IP27_FREEMEM_STRIDE             0
+
+#endif /* PROM || SABLE*/
+/*
+ * There will be only one of these in a partition so the IO6 must set it up.
+ */
+#define IO6_GDA_OFFSET                  0x11000
+#define IO6_GDA_SIZE                    0x400
+#define IO6_GDA_COUNT                   1
+#define IO6_GDA_STRIDE                  0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET           0x11400
+#define IP27_NMI_KREGS_CPU_SIZE         0x200
+/*
+ * save area of kernel nmi regs in eframe format
+ */
+#define IP27_NMI_EFRAME_OFFSET          0x11800
+#define IP27_NMI_EFRAME_SIZE            0x200
+
+#define KLDIR_ENT_SIZE                  0x40
+#define KLDIR_MAX_ENTRIES               (0x400 / 0x40)
+
+#endif  /* !CONFIG_SGI_IO */
+
+#ifndef __ASSEMBLY__
+typedef struct kldir_ent_s {
+        u64             magic;          /* Indicates validity of entry      */
+        off_t           offset;         /* Offset from start of node space  */
+#if defined(CONFIG_SGI_IO)      /* FIXME */
+        __psunsigned_t  pointer;        /* Pointer to area in some cases    */
+#else
+        unsigned long   pointer;        /* Pointer to area in some cases    */
+#endif
+        size_t          size;           /* Size in bytes                    */
+        u64             count;          /* Repeat count if array, 1 if not  */
+        size_t          stride;         /* Stride if array, 0 if not        */
+        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
+        /* NOTE: These 16 bytes are used in the Partition KLDIR
+           entry to store partition info. Refer to klpart.h for this. */
+} kldir_ent_t;
+#endif /* !__ASSEMBLY__ */
+
+#if defined(CONFIG_SGI_IO)
+
+#define KLDIR_ENT_SIZE                  0x40
+#define KLDIR_MAX_ENTRIES               (0x400 / 0x40)
+
+/*
+ * The actual offsets of each memory area are machine-dependent
+ */
+#ifdef CONFIG_SGI_IP27
+// Not yet #include <asm/sn/sn0/kldir.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/kldir.h>
+#else
+#error "kldir.h is currently defined for IP27 and IP35 platforms only"
+#endif
+
+#endif  /* CONFIG_SGI_IO */
+
+#endif /* _ASM_SN_KLDIR_H */
diff --git a/include/asm-mips/sn/klkernvars.h b/include/asm-mips/sn/klkernvars.h
new file mode 100644
index 000000000000..5de4c5e8ab30
--- /dev/null
+++ b/include/asm-mips/sn/klkernvars.h
@@ -0,0 +1,29 @@
+/*
+ * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_KLKERNVARS_H
+#define __ASM_SN_KLKERNVARS_H
+
+#define KV_MAGIC_OFFSET         0x0
+#define KV_RO_NASID_OFFSET      0x4
+#define KV_RW_NASID_OFFSET      0x6
+
+#define KV_MAGIC                0x5f4b565f
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sn/types.h>
+
+typedef struct kern_vars_s {
+        int             kv_magic;
+        nasid_t         kv_ro_nasid;
+        nasid_t         kv_rw_nasid;
+        unsigned long   kv_ro_baseaddr;
+        unsigned long   kv_rw_baseaddr;
+} kern_vars_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_SN_KLKERNVARS_H */
+
diff --git a/include/asm-mips/sn/launch.h b/include/asm-mips/sn/launch.h
new file mode 100644
index 000000000000..b67699c0c475
--- /dev/null
+++ b/include/asm-mips/sn/launch.h
@@ -0,0 +1,107 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_LAUNCH_H
+#define _ASM_SN_LAUNCH_H
+
+#include <linux/config.h>
+#include <asm/sn/types.h>
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, then returns to the slave loop.  The master may poll or wait
+ * for the slaves to finish.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per local CPU.
+ */
+
+#define LAUNCH_MAGIC            0xaddbead2addbead3
+#ifdef CONFIG_SGI_IP27
+#define LAUNCH_SIZEOF           0x100
+#define LAUNCH_PADSZ            0xa0
+#endif
+
+#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
+#define LAUNCH_OFF_BUSY         0x08
+#define LAUNCH_OFF_CALL         0x10
+#define LAUNCH_OFF_CALLC        0x18
+#define LAUNCH_OFF_CALLPARM     0x20
+#define LAUNCH_OFF_STACK        0x28
+#define LAUNCH_OFF_GP           0x30
+#define LAUNCH_OFF_BEVUTLB      0x38
+#define LAUNCH_OFF_BEVNORMAL    0x40
+#define LAUNCH_OFF_BEVECC       0x48
+
+#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
+#define LAUNCH_STATE_SENT       1
+#define LAUNCH_STATE_RECD       2
+
+/*
+ * The launch routine is called only if the complement address is correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ * The slave_launch routine turns on the BUSY flag, and the slave loop
+ * clears the BUSY flag after control is returned to it.
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef int launch_state_t;
+typedef void (*launch_proc_t)(u64 call_parm);
+
+typedef struct launch_s {
+        volatile u64            magic;  /* Magic number                     */
+        volatile u64            busy;   /* Slave currently active           */
+        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
+        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
+        volatile u64            call_parm;      /* Single parm passed to call*/
+        volatile void *stack_addr;      /* Stack pointer for slave function */
+        volatile void *gp_addr;         /* Global pointer for slave func.   */
+        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
+        volatile char           *bevnormal;/*Address of bev normal ex handler */
+        volatile char           *bevecc;/* Address of bev cache err handler */
+        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
+} launch_t;
+
+/*
+ * PROM entry points for launch routines are determined by IPxxprom/start.s
+ */
+
+#define LAUNCH_SLAVE    (*(void (*)(int nasid, int cpu, \
+                                    launch_proc_t call_addr, \
+                                    u64 call_parm, \
+                                    void *stack_addr, \
+                                    void *gp_addr)) \
+                         IP27PROM_LAUNCHSLAVE)
+
+#define LAUNCH_WAIT     (*(void (*)(int nasid, int cpu, int timeout_msec)) \
+                         IP27PROM_WAITSLAVE)
+
+#define LAUNCH_POLL     (*(launch_state_t (*)(int nasid, int cpu)) \
+                         IP27PROM_POLLSLAVE)
+
+#define LAUNCH_LOOP     (*(void (*)(void)) \
+                         IP27PROM_SLAVELOOP)
+
+#define LAUNCH_FLASH    (*(void (*)(void)) \
+                         IP27PROM_FLASHLEDS)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SN_LAUNCH_H */
diff --git a/include/asm-mips/sn/mapped_kernel.h b/include/asm-mips/sn/mapped_kernel.h
new file mode 100644
index 000000000000..3a17846df849
--- /dev/null
+++ b/include/asm-mips/sn/mapped_kernel.h
@@ -0,0 +1,59 @@
+/*
+ * File created by Kanoj Sarcar 06/06/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_MAPPED_KERNEL_H
+#define __ASM_SN_MAPPED_KERNEL_H
+
+/*
+ * Note on how mapped kernels work: the text and data section is
+ * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
+ * init/setup/data section gets a 16M virtual address bump in the
+ * ld.script file (so that tlblo0 and tlblo1 maps the sections).
+ * The vmlinux.64 section addresses are put in the xkseg range
+ * using the change-addresses makefile option. Use elfdump -of
+ * on IRIX to see where the sections go. The Origin loader loads
+ * the two sections contiguously in physical memory. The loader
+ * sets the entry point into kernel_entry using a xkphys address,
+ * but instead of using 0xa800000001160000, it uses the address
+ * 0xa800000000160000, which is where it physically loaded that
+ * code. So no jumps can be done before we have switched to using
+ * cksseg addresses.
+ */
+#include <linux/config.h>
+#include <asm/addrspace.h>
+
+#ifdef CONFIG_BUILD_ELF64
+#define REP_BASE        CAC_BASE
+#else
+#define REP_BASE        CKSEG0
+#endif
+
+#ifdef CONFIG_MAPPED_KERNEL
+
+#define MAPPED_ADDR_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_ADDR_RW_TO_PHYS(x)       (x - REP_BASE - 16777216)
+
+#define MAPPED_KERN_RO_PHYSBASE(n) \
+                        (PLAT_NODE_DATA(n)->kern_vars.kv_ro_baseaddr)
+#define MAPPED_KERN_RW_PHYSBASE(n) \
+                        (PLAT_NODE_DATA(n)->kern_vars.kv_rw_baseaddr)
+
+#define MAPPED_KERN_RO_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
+                                MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
+#define MAPPED_KERN_RW_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
+                                MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
+
+#else /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_KERN_RW_TO_PHYS(x)       (x - REP_BASE)
+
+#endif /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
+#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
+
+#endif /* __ASM_SN_MAPPED_KERNEL_H  */
diff --git a/include/asm-mips/sn/nmi.h b/include/asm-mips/sn/nmi.h
new file mode 100644
index 000000000000..6b7b0b5f3729
--- /dev/null
+++ b/include/asm-mips/sn/nmi.h
@@ -0,0 +1,125 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_NMI_H
+#define __ASM_SN_NMI_H
+
+#ident "$Revision: 1.5 $"
+
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, followed by an optional rendezvous function, then returns to
+ * the slave loop.  The master does not wait for the slaves before
+ * returning.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per CPU.
+ */
+
+#define NMI_MAGIC               0x48414d4d455201
+#define NMI_SIZEOF              0x40
+
+#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
+#define NMI_OFF_FLAGS           0x08
+#define NMI_OFF_CALL            0x10
+#define NMI_OFF_CALLC           0x18
+#define NMI_OFF_CALLPARM        0x20
+#define NMI_OFF_GMASTER         0x28
+
+/*
+ * The NMI routine is called only if the complement address is
+ * correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct nmi_s {
+        volatile unsigned long   magic;         /* Magic number */
+        volatile unsigned long   flags;         /* Combination of flags above */
+        volatile void *call_addr;       /* Routine for slave to call        */
+        volatile void *call_addr_c;     /* 1's complement of address        */
+        volatile void *call_parm;       /* Single parm passed to call       */
+        volatile unsigned long   gmaster;       /* Flag true only on global master*/
+} nmi_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/* Following definitions are needed both in the prom & the kernel
+ * to identify the format of the nmi cpu register save area in the
+ * low memory on each node.
+ */
+#ifndef __ASSEMBLY__
+
+struct reg_struct {
+        unsigned long   gpr[32];
+        unsigned long   sr;
+        unsigned long   cause;
+        unsigned long   epc;
+        unsigned long   badva;
+        unsigned long   error_epc;
+        unsigned long   cache_err;
+        unsigned long   nmi_sr;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+/* These are the assembly language offsets into the reg_struct structure */
+
+#define R0_OFF          0x0
+#define R1_OFF          0x8
+#define R2_OFF          0x10
+#define R3_OFF          0x18
+#define R4_OFF          0x20
+#define R5_OFF          0x28
+#define R6_OFF          0x30
+#define R7_OFF          0x38
+#define R8_OFF          0x40
+#define R9_OFF          0x48
+#define R10_OFF         0x50
+#define R11_OFF         0x58
+#define R12_OFF         0x60
+#define R13_OFF         0x68
+#define R14_OFF         0x70
+#define R15_OFF         0x78
+#define R16_OFF         0x80
+#define R17_OFF         0x88
+#define R18_OFF         0x90
+#define R19_OFF         0x98
+#define R20_OFF         0xa0
+#define R21_OFF         0xa8
+#define R22_OFF         0xb0
+#define R23_OFF         0xb8
+#define R24_OFF         0xc0
+#define R25_OFF         0xc8
+#define R26_OFF         0xd0
+#define R27_OFF         0xd8
+#define R28_OFF         0xe0
+#define R29_OFF         0xe8
+#define R30_OFF         0xf0
+#define R31_OFF         0xf8
+#define SR_OFF          0x100
+#define CAUSE_OFF       0x108
+#define EPC_OFF         0x110
+#define BADVA_OFF       0x118
+#define ERROR_EPC_OFF   0x120
+#define CACHE_ERR_OFF   0x128
+#define NMISR_OFF       0x130
+
+#endif /* __ASM_SN_NMI_H */
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
new file mode 100644
index 000000000000..398815639fb8
--- /dev/null
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -0,0 +1,364 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_ADDRS_H
+#define _ASM_SN_SN0_ADDRS_H
+
+#include <linux/config.h>
+
+/*
+ * SN0 (on a T5) Address map
+ *
+ * This file contains a set of definitions and macros which are used
+ * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
+ * and UNCAC) used by the SN0 architecture.  It also contains addresses
+ * for "major" statically locatable PROM/Kernel data structures, such as
+ * the partition table, the configuration data structure, etc.
+ * We make an implicit assumption that the processor using this file
+ * follows the R10K's provisions for specifying uncached attributes;
+ * should this change, the base registers may very well become processor-
+ * dependent.
+ *
+ * For more information on the address spaces, see the "Local Resources"
+ * chapter of the Hub specification.
+ *
+ * NOTE: This header file is included both by C and by assembler source
+ *       files.  Please bracket any language-dependent definitions
+ *       appropriately.
+ */
+
+/*
+ * Some of the macros here need to be casted to appropriate types when used
+ * from C.  They definitely must not be casted from assembly language so we
+ * use some new ANSI preprocessor stuff to paste these on where needed.
+ */
+
+/*
+ * The following couple of definitions will eventually need to be variables,
+ * since the amount of address space assigned to each node depends on
+ * whether the system is running in N-mode (more nodes with less memory)
+ * or M-mode (fewer nodes with more memory).  We expect that it will
+ * be a while before we need to make this decision dynamically, though,
+ * so for now we just use defines bracketed by an ifdef.
+ */
+
+#ifdef CONFIG_SGI_SN0_N_MODE
+
+#define NODE_SIZE_BITS          31
+#define BWIN_SIZE_BITS          28
+
+#define NASID_BITS              9
+#define NASID_BITMASK           (0x1ffLL)
+#define NASID_SHFT              31
+#define NASID_META_BITS         5
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
+
+#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
+
+#define NODE_SIZE_BITS          32
+#define BWIN_SIZE_BITS          29
+
+#define NASID_BITMASK           (0xffLL)
+#define NASID_BITS              8
+#define NASID_SHFT              32
+#define NASID_META_BITS         4
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
+
+#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
+
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else /* __ASSEMBLY__ || _STANDALONE */
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+#endif /* __ASSEMBLY__ || _STANDALONE */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN0.
+ *      CALIAS -- Varies in size, points to the first n bytes of memory
+ *                      on the reader's node.
+ */
+
+#define CALIAS_BASE             CAC_BASE
+
+
+
+#define BRIDGE_REG_PTR(_base, _off)     ((volatile bridgereg_t *) \
+        ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
+
+/* Turn on sable logging for the processors whose bits are set. */
+#ifdef SABLE
+#define SABLE_LOG_TRIGGER(_map) \
+                *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
+#else
+#define SABLE_LOG_TRIGGER(_map)
+#endif /* SABLE */
+
+#ifndef __ASSEMBLY__
+#define KERN_NMI_ADDR(nasid, slice)                                     \
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
+                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
+#endif /* !__ASSEMBLY__ */
+
+#ifdef PROM
+
+#define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
+#define MISC_PROM_SIZE          0x200000
+
+#define DIAG_BASE               PHYS_TO_K0(0x01500000)
+#define DIAG_SIZE               0x300000
+
+#define ROUTE_BASE              PHYS_TO_K0(0x01800000)
+#define ROUTE_SIZE              0x200000
+
+#define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
+#define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
+#define IP27PROM_CORP_MAX       32
+#define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
+#define IP27PROM_CORP_SIZE      0x10000
+#define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
+#define IP27PROM_CORP_STKSIZE   0x2000
+#define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
+#define IP27PROM_DECOMP_SIZE    0xfff00
+
+#define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
+#define IP27PROM_BASE_MAPPED    (UNCAC_BASE | 0x1fc00000)
+#define IP27PROM_SIZE_MAX       0x100000
+
+#define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
+#define IP27PROM_PCFG_SIZE      0xd0000
+#define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_ERRDMP_SIZE    0xf000
+
+#define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
+#define IP27PROM_CONSOLE_SIZE   0x200
+#define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
+#define IP27PROM_NETUART_SIZE   0x100
+#define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
+#define IP27PROM_UNUSED1_SIZE   0x500
+#define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
+#define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
+#define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
+#define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
+#define IP27PROM_STACK_SHFT     16
+#define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
+#define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
+
+#define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
+#define SLAVESTACK_SIZE         0x40000
+
+#define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
+#define ENETBUFS_SIZE           0x20000
+
+#define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
+#define IO6PROM_SIZE            0x400000
+#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
+#define IO6DPROM_SIZE           0x200000
+
+#define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
+#define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
+
+#define IP27PROM_INT_LAUNCH     10      /* and 11 */
+#define IP27PROM_INT_NETUART    12      /* through 17 */
+
+#endif /* PROM */
+
+/*
+ * needed by symmon so it needs to be outside #if PROM
+ */
+#define IP27PROM_ELSC_SHFT      10
+#define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
+
+/*
+ * This address is used by IO6PROM to build MemoryDescriptors of
+ * free memory. This address is important since unix gets loaded
+ * at this address, and this memory has to be FREE if unix is to
+ * be loaded.
+ */
+
+#define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
+
+#define IO6PROM_STACK_SHFT      14      /* stack per cpu */
+#define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
+
+/*
+ * IP27 PROM vectors
+ */
+
+#define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
+#define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
+#define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
+#define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
+#define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
+#define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
+#define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
+#define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
+#define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
+#define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
+
+#define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
+#define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
+#define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
+#define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
+
+#ifndef __ASSEMBLY__
+
+/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
+ * CACHE_ERR_SP_PTR could either contain an address to the stack, or
+ * the stack could start at CACHE_ERR_SP_PTR
+ */
+#if defined (HUB_ERR_STS_WAR)
+#define CACHE_ERR_EFRAME        0x480
+#else /* HUB_ERR_STS_WAR */
+#define CACHE_ERR_EFRAME        0x400
+#endif /* HUB_ERR_STS_WAR */
+
+#define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
+#define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
+#define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
+#define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
+#define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
+
+#endif  /* !__ASSEMBLY__ */
+
+#define _ARCSPROM
+
+#ifdef _STANDALONE
+
+/*
+ * The PROM needs to pass the device base address and the
+ * device pci cfg space address to the device drivers during
+ * install. The COMPONENT->Key field is used for this purpose.
+ * Macros needed by SN0 device drivers to convert the
+ * COMPONENT->Key field to the respective base address.
+ * Key field looks as follows:
+ *
+ *  +----------------------------------------------------+
+ *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
+ *  |   2     |   1     |  1   |   1    |    2    |   1  |
+ *  +----------------------------------------------------+
+ *  |         |         |      |        |         |      |
+ *  64        48        40     32       24        8      0
+ *
+ * These are used by standalone drivers till the io infrastructure
+ * is in place.
+ */
+
+#ifndef __ASSEMBLY__
+
+#define uchar unsigned char
+
+#define KEY_DEVNASID_SHFT  48
+#define KEY_WIDID_SHFT     40
+#define KEY_PCIID_SHFT     32
+#define KEY_HUBWID_SHFT    24
+#define KEY_HSTNASID_SHFT  8
+
+#define MK_SN0_KEY(nasid, widid, pciid) \
+                        ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
+                                ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
+                                ((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
+
+#define ADD_HUBWID_KEY(key,hubwid)\
+                        (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
+
+#define ADD_HSTNASID_KEY(key,hstnasid)\
+                        (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
+
+#define GET_DEVNASID_FROM_KEY(key)      ((short)(key >> KEY_DEVNASID_SHFT))
+#define GET_WIDID_FROM_KEY(key)         ((uchar)(key >> KEY_WIDID_SHFT))
+#define GET_PCIID_FROM_KEY(key)         ((uchar)(key >> KEY_PCIID_SHFT))
+#define GET_HUBWID_FROM_KEY(key)        ((uchar)(key >> KEY_HUBWID_SHFT))
+#define GET_HSTNASID_FROM_KEY(key)      ((short)(key >> KEY_HSTNASID_SHFT))
+
+#define PCI_64_TARGID_SHFT              60
+
+#define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                                        GET_WIDID_FROM_KEY(key))\
+                                        | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
+
+#define GET_PCICFGBASE_FROM_KEY(key) \
+                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                              GET_WIDID_FROM_KEY(key))\
+                        | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
+
+#define GET_WIDBASE_FROM_KEY(key) \
+                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                              GET_WIDID_FROM_KEY(key)))
+
+#define PUT_INSTALL_STATUS(c,s)         c->Revision = s
+#define GET_INSTALL_STATUS(c)           c->Revision
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _STANDALONE */
+
+#if defined (HUB_ERR_STS_WAR)
+
+#define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
+#define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
+#define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
+                                /* Used to match addr in error reg. */
+#define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
+
+#endif /* HUB_ERR_STS_WAR */
+
+#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
new file mode 100644
index 000000000000..0e00dd474afc
--- /dev/null
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -0,0 +1,89 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI IP27 specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_ARCH_H
+#define _ASM_SN_SN0_ARCH_H
+
+#include <linux/config.h>
+
+#ifndef SABLE
+
+#ifndef SN0XXL  /* 128 cpu SMP max */
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ */
+#define MAX_COMPACT_NODES       64
+
+/*
+ * MAXCPUS refers to the maximum number of CPUs in a single kernel.
+ * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
+ */
+#define MAXCPUS                 128
+
+#else /* SN0XXL system */
+
+#define MAX_COMPACT_NODES       128
+#define MAXCPUS                 256
+
+#endif /* SN0XXL */
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              256
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define MAX_REGIONS             64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS          MAX_REGIONS
+
+
+#else
+
+#define MAX_COMPACT_NODES       4
+#define MAX_NASIDS              4
+#define MAXCPUS                 8
+
+#endif
+
+#define NASID_MASK_BYTES        ((MAX_NASIDS + 7) / 8)
+
+/*
+ * Slot constants for SN0
+ */
+#ifdef CONFIG_SGI_SN0_N_MODE
+#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
+#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#endif /* defined(N_MODE) */
+
+#if SABLE_RTL
+#define SLOT_SHIFT              (28)
+#define SLOT_MIN_MEM_SIZE       (16*1024*1024)
+#else
+#define SLOT_SHIFT              (27)
+#define SLOT_MIN_MEM_SIZE       (32*1024*1024)
+#endif
+
+#define CPUS_PER_NODE           2       /* CPUs on a single hub */
+#define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
+#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
+
+#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h
new file mode 100644
index 000000000000..f5dbba6f4610
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hub.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUB_H
+#define _ASM_SN_SN0_HUB_H
+
+/* The secret password; used to release protection */
+#define HUB_PASSWORD            0x53474972756c6573ull
+
+#define CHIPID_HUB              0
+#define CHIPID_ROUTER           1
+
+#define HUB_REV_1_0             1
+#define HUB_REV_2_0             2
+#define HUB_REV_2_1             3
+#define HUB_REV_2_2             4
+#define HUB_REV_2_3             5
+#define HUB_REV_2_4             6
+
+#define MAX_HUB_PATH            80
+
+#include <asm/sn/sn0/addrs.h>
+#include <asm/sn/sn0/hubpi.h>
+#include <asm/sn/sn0/hubmd.h>
+#include <asm/sn/sn0/hubio.h>
+#include <asm/sn/sn0/hubni.h>
+//#include <asm/sn/sn0/hubcore.h>
+
+#ifdef SABLE
+#define IP27_NO_HUBUART_INT     1
+#endif
+
+/* Translation of uncached attributes */
+#define UATTR_HSPEC     0
+#define UATTR_IO        1
+#define UATTR_MSPEC     2
+#define UATTR_UNCAC     3
+
+#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
new file mode 100644
index 000000000000..80cf6a52ed3b
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubio.h
@@ -0,0 +1,988 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * In general, the longer software name should be used when available.
+ */
+
+/*
+ * Slightly friendlier names for some common registers.
+ * The hardware definitions follow.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
+#define IIO_WIDGET_FLUSH        IIO_WTFR     /* Widget target flush */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/*
+ * The following definitions use the names defined in the IO interface
+ * document for ease of reference.  When possible, software should
+ * generally use the longer but clearer names defined above.
+ */
+
+#define IIO_BASE        0x400000
+#define IIO_BASE_BTE0   0x410000
+#define IIO_BASE_BTE1   0x420000
+#define IIO_BASE_PERF   0x430000
+#define IIO_PERF_CNT    0x430008
+
+#define IO_PERF_SETS    32
+
+#define IIO_WID         0x400000        /* Widget identification */
+#define IIO_WSTAT       0x400008        /* Widget status */
+#define IIO_WCR         0x400020        /* Widget control */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+#define IIO_ILAPR       0x400100        /* Local Access Protection */
+#define IIO_ILAPO       0x400108        /* Protection override */
+#define IIO_IOWA        0x400110        /* outbound widget access */
+#define IIO_IIWA        0x400118        /* inbound widget access */
+#define IIO_IIDEM       0x400120        /* Inbound Device Error Mask */
+#define IIO_ILCSR       0x400128        /* LLP control and status */
+#define IIO_ILLR        0x400130        /* LLP Log */
+#define IIO_IIDSR       0x400138        /* Interrupt destination */
+
+#define IIO_IIBUSERR    0x1400208       /* Reads here cause a bus error. */
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000003f
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_0      0x400140        /* gfx node/widget register 0 */
+#define IIO_IGFX_1      0x400148        /* gfx node/widget register 1 */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_N_NUM_BITS     9       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    4
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_VLD_BITS       1       /* size of valid field */
+#define IIO_IGFX_VLD_MASK       ((1<<IIO_IGFX_VLD_BITS)-1)
+#define IIO_IGFX_VLD_SHIFT      20
+#define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+
+/* Scratch registers (not all bits available) */
+#define IIO_SCRATCH_REG0        0x400150
+#define IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_MASK        0x0000000f00f11fff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000800000000
+#define IIO_SCRATCH_BIT0_1      0x0000000400000000
+#define IIO_SCRATCH_BIT0_2      0x0000000200000000
+#define IIO_SCRATCH_BIT0_3      0x0000000100000000
+#define IIO_SCRATCH_BIT0_4      0x0000000000800000
+#define IIO_SCRATCH_BIT0_5      0x0000000000400000
+#define IIO_SCRATCH_BIT0_6      0x0000000000200000
+#define IIO_SCRATCH_BIT0_7      0x0000000000100000
+#define IIO_SCRATCH_BIT0_8      0x0000000000010000
+#define IIO_SCRATCH_BIT0_9      0x0000000000001000
+#define IIO_SCRATCH_BIT0_R      0x0000000000000fff
+
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the hub, we've
+ * redefined big window 7 as small window 0.
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+/*
+ * The IO LLP control status register and widget control register
+ */
+#ifndef __ASSEMBLY__
+
+typedef union hubii_wid_u {
+        u64     wid_reg_value;
+        struct {
+                u64     wid_rsvd:       32,     /* unused */
+                        wid_rev_num:     4,     /* revision number */
+                        wid_part_num:   16,     /* the widget type: hub=c101 */
+                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
+                        wid_rsvd1:       1;     /* Reserved */
+        } wid_fields_s;
+} hubii_wid_t;
+
+
+typedef union hubii_wcr_u {
+        u64     wcr_reg_value;
+        struct {
+                u64     wcr_rsvd:       41,     /* unused */
+                        wcr_e_thresh:    5,     /* elasticity threshold */
+                        wcr_dir_con:     1,     /* widget direct connect */
+                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
+                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
+                        wcr_rsvd1:       8,     /* Reserved */
+                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_widget_id:   4;     /* LLP crossbar credit */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+typedef union hubii_wstat_u {
+        u64      reg_value;
+        struct {
+                u64     rsvd1:          31,
+                        crazy:           1,     /* Crazy bit            */
+                        rsvd2:           8,
+                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                        rsvd3:           6,
+                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
+                        rsvd4:           2,
+                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
+                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                        pending:         4;     /* Pending Requests     */
+        } wstat_fields_s;
+} hubii_wstat_t;
+
+
+typedef union hubii_ilcsr_u {
+        u64     icsr_reg_value;
+        struct {
+                u64     icsr_rsvd:      22,     /* unused */
+                        icsr_max_burst: 10,     /* max burst */
+                        icsr_rsvd4:      6,     /* reserved */
+                        icsr_max_retry: 10,     /* max retry */
+                        icsr_rsvd3:      2,     /* reserved */
+                        icsr_lnk_stat:   2,     /* link status */
+                        icsr_bm8:        1,     /* Bit mode 8 */
+                        icsr_llp_en:     1,     /* LLP enable bit */
+                        icsr_rsvd2:      1,     /* reserver */
+                        icsr_wrm_reset:  1,     /* Warm reset bit */
+                        icsr_rsvd1:      2,     /* Data ready offset */
+                        icsr_null_to:    6;     /* Null timeout   */
+
+        } icsr_fields_s;
+} hubii_ilcsr_t;
+
+
+typedef union hubii_iowa_u {
+        u64     iowa_reg_value;
+        struct {
+                u64     iowa_rsvd:      48,     /* unused */
+                        iowa_wxoac:      8,     /* xtalk widget access bits */
+                        iowa_rsvd1:      7,     /* xtalk widget access bits */
+                        iowa_w0oac:      1;     /* xtalk widget access bits */
+        } iowa_fields_s;
+} hubii_iowa_t;
+
+typedef union hubii_iiwa_u {
+        u64     iiwa_reg_value;
+        struct {
+                u64     iiwa_rsvd:      48,     /* unused */
+                        iiwa_wxiac:      8,     /* hub wid access bits */
+                        iiwa_rsvd1:      7,     /* reserved */
+                        iiwa_w0iac:      1;     /* hub wid0 access */
+        } iiwa_fields_s;
+} hubii_iiwa_t;
+
+typedef union   hubii_illr_u {
+        u64     illr_reg_value;
+        struct {
+                u64     illr_rsvd:      32,     /* unused */
+                        illr_cb_cnt:    16,     /* checkbit error count */
+                        illr_sn_cnt:    16;     /* sequence number count */
+        } illr_fields_s;
+} hubii_illr_t;
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+typedef union io_perf_sel {
+        u64 perf_sel_reg;
+        struct {
+                u64     perf_rsvd  : 48,
+                        perf_icct  :  8,
+                        perf_ippr1 :  4,
+                        perf_ippr0 :  4;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the hub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        u64     perf_cnt;
+        struct {
+                u64     perf_rsvd1 : 32,
+                                perf_rsvd2 : 12,
+                                perf_cnt   : 20;
+        } perf_cnt_bits;
+} io_perf_cnt_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define LNK_STAT_WORKING        0x2
+
+#define IIO_LLP_CB_MAX  0xffff
+#define IIO_LLP_SN_MAX  0xffff
+
+/* IO PRB Entries */
+#define IIO_NUM_IPRBS   (9)
+#define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
+#define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
+#define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
+#define IIO_IOPRB_A     0x4001b0        /* PRB entry a */
+#define IIO_IOPRB_B     0x4001b8        /* PRB entry b */
+#define IIO_IOPRB_C     0x4001c0        /* PRB entry c */
+#define IIO_IOPRB_D     0x4001c8        /* PRB entry d */
+#define IIO_IOPRB_E     0x4001d0        /* PRB entry e */
+#define IIO_IOPRB_F     0x4001d8        /* PRB entry f */
+
+
+#define IIO_IXCC        0x4001e0        /* Crosstalk credit count timeout */
+#define IIO_IXTCC       IIO_IXCC
+#define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
+#define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
+#define IIO_IECLR       0x4001f8        /* IO error clear */
+#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/* PIO Read address Table Entries */
+#define IIO_IPCA        0x400300        /* PRB Counter adjust */
+#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
+#define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
+#define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
+#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_IPDR        0x400388        /* PIO table entry deallocation */
+#define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
+#define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
+#define IIO_IIAP        0x4003a0        /* IIQ Arbitration Parameters */
+#define IIO_IMMR        IIO_IIAP
+#define IIO_ICMR        0x4003a8        /* CRB Managment Register */
+#define IIO_ICCR        0x4003b0        /* CRB Control Register */
+#define IIO_ICTO        0x4003b8        /* CRB Time Out Register */
+#define IIO_ICTP        0x4003c0        /* CRB Time Out Prescalar */
+
+
+/*
+ * ICMR register fields
+ */
+#define IIO_ICMR_PC_VLD_SHFT    36
+#define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_P_CNT_SHFT     0
+#define IIO_ICMR_P_CNT_MASK     (0xf << IIO_ICMR_P_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR
+ */
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      (0x800)
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              0x400400
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+
+/* XXX - IBUE register coming for Hub 2 */
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to hub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Fields in CRB Register A
+ */
+#ifndef __ASSEMBLY__
+typedef union icrba_u {
+        u64     reg_value;
+        struct {
+                u64     resvd:  6,
+                        stall_bte0: 1,  /* Stall BTE 0 */
+                        stall_bte1: 1,  /* Stall BTE 1 */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  3,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } icrba_fields_s;
+} icrba_t;
+
+/* This is an alternate typedef for the HUB1 CRB A in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrba_u {
+        u64     reg_value;
+
+        struct {
+                u64     resvd:  6,
+                        unused: 1,      /* Unused but RW!!      */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  4,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } h1_icrba_fields_s;
+} h1_icrba_t;
+
+/* XXX - Is this still right?  Check the spec. */
+#define ICRBN_A_CERR_SHFT       54
+#define ICRBN_A_ERR_MASK        0x3ff
+
+#if 0   /* Disabled, this causes namespace polution and break allmodconfig */
+/*
+ * Easy access macros.
+ */
+#define a_error         icrba_fields_s.error
+#define a_ecode         icrba_fields_s.ecode
+#define a_lnetuce       icrba_fields_s.lnetuce
+#define a_mark          icrba_fields_s.mark
+#define a_xerr          icrba_fields_s.xerr
+#define a_sidn          icrba_fields_s.sidn
+#define a_tnum          icrba_fields_s.tnum
+#define a_addr          icrba_fields_s.addr
+#define a_valid         icrba_fields_s.valid
+#define a_iow           icrba_fields_s.iow
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line.
+                                         */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+
+
+/*
+ * Fields in CRB Register B
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  5,
+                btenum: 1,      /* BTE to which entry belongs to */
+                cohtrans: 1,    /* Coherent transaction */
+                xtsize: 2,      /* Xtalk operation size
+                                 * 0: Double Word
+                                 * 1: 32 Bytes.
+                                 * 2: 128 Bytes,
+                                 * 3: Reserved.
+                                 */
+                srcnode: 9,     /* Source Node ID               */
+                srcinit: 2,     /* Source Initiator:
+                                 * See below for field values.
+                                 */
+                useold: 1,      /* Use OLD command for processing */
+                imsgtype: 2,    /* Incoming message type
+                                 * see below for field values
+                                 */
+                imsg:   8,      /* Incoming message     */
+                initator: 3,    /* Initiator of original request
+                                 * See below for field values.
+                                 */
+                reqtype: 5,     /* Identifies type of request
+                                 * See below for field values.
+                                 */
+                rsvd2:  7,
+                ackcnt: 11,     /* Invalidate ack count */
+                resp:   1,      /* data response  given to processor */
+                ack:    1,      /* indicates data ack received  */
+                hold:   1,      /* entry is gathering inval acks */
+                wb_pend:1,      /* waiting for writeback to complete */
+                intvn:  1,      /* Intervention */
+                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
+                stall_intr: 1;  /* Stall internal interrupts */
+        } icrbb_field_s;
+} icrbb_t;
+
+/* This is an alternate typedef for the HUB1 CRB B in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrbb_u {
+        u64     reg_value;
+        struct {
+                u64     rsvd1:  5,
+                        btenum: 1,      /* BTE to which entry belongs to */
+                        cohtrans: 1,    /* Coherent transaction */
+                        xtsize: 2,      /* Xtalk operation size
+                                         * 0: Double Word
+                                         * 1: 32 Bytes.
+                                         * 2: 128 Bytes,
+                                         * 3: Reserved.
+                                         */
+                        srcnode: 9,     /* Source Node ID               */
+                        srcinit: 2,     /* Source Initiator:
+                                         * See below for field values.
+                                         */
+                        useold: 1,      /* Use OLD command for processing */
+                        imsgtype: 2,    /* Incoming message type
+                                         * see below for field values
+                                         */
+                        imsg:   8,      /* Incoming message     */
+                        initator: 3,    /* Initiator of original request
+                                         * See below for field values.
+                                         */
+                        rsvd2:  1,
+                        pcache: 1,      /* entry belongs to partial cache */
+                        reqtype: 5,     /* Identifies type of request
+                                         * See below for field values.
+                                         */
+                        stl_ib: 1,      /* stall Ibus coming from xtalk */
+                        stl_intr: 1,    /* Stall internal interrupts */
+                        stl_bte0: 1,    /* Stall BTE 0  */
+                        stl_bte1: 1,    /* Stall BTE 1  */
+                        intrvn: 1,      /* Req was target of intervention */
+                        ackcnt: 11,     /* Invalidate ack count */
+                        resp:   1,      /* data response  given to processor */
+                        ack:    1,      /* indicates data ack received  */
+                        hold:   1,      /* entry is gathering inval acks */
+                        wb_pend:1,      /* waiting for writeback to complete */
+                        sleep:  1,      /* xtalk req sleeping till IO-sync */
+                        pnd_reply: 1,   /* replies not issed due to IOQ full */
+                        pnd_req: 1;     /* reqs not issued due to IOQ full */
+        } h1_icrbb_field_s;
+} h1_icrbb_t;
+
+
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_btenum        icrbb_field_s.btenum
+#define b_cohtrans      icrbb_field_s.cohtrans
+#define b_xtsize        icrbb_field_s.xtsize
+#define b_srcnode       icrbb_field_s.srcnode
+#define b_srcinit       icrbb_field_s.srcinit
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_imsg          icrbb_field_s.imsg
+#define b_initiator     icrbb_field_s.initiator
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for field xtsize
+ */
+#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+
+/*
+ * values for field srcinit
+ */
+#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
+#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Values for field reqtype.
+ */
+/* XXX - Need to fix this for Hub 2 */
+#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+
+/*
+ * Fields in CRB Register C
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union icrbc_s {
+        u64     reg_value;
+        struct {
+                u64     rsvd:   6,
+                        sleep:  1,
+                        pricnt: 4,      /* Priority count sent with Read req */
+                        pripsc: 4,      /* Priority Pre scalar  */
+                        bteop:  1,      /* BTE Operation        */
+                        push_be: 34,    /* Push address Byte enable
+                                         * Holds push addr, if CRB is for BTE
+                                         * If CRB belongs to Partial cache,
+                                         * this contains byte enables bits
+                                         * ([47:46] = 0)
+                                         */
+                        suppl:  11,     /* Supplemental field   */
+                        barrop: 1,      /* Barrier Op bit set in xtalk req */
+                        doresp: 1,      /* Xtalk req needs a response   */
+                        gbr:    1;      /* GBR bit set in xtalk packet  */
+        } icrbc_field_s;
+} icrbc_t;
+
+#define c_pricnt        icrbc_field_s.pricnt
+#define c_pripsc        icrbc_field_s.pripsc
+#define c_bteop         icrbc_field_s.bteop
+#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl         icrbc_field_s.suppl
+#define c_barrop        icrbc_field_s.barrop
+#define c_doresp        icrbc_field_s.doresp
+#define c_gbr   icrbc_field_s.gbr
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Fields in CRB Register D
+ */
+
+#ifndef __ASSEMBLY__
+typedef union icrbd_s {
+        u64     reg_value;
+        struct {
+            u64 rsvd:   38,
+                toutvld: 1,     /* Timeout in progress for this CRB */
+                ctxtvld: 1,     /* Context field below is valid */
+                rsvd2:  1,
+                context: 15,    /* Bit vector:
+                                 * Has a bit set for each CRB entry
+                                 * which needs to be deallocated
+                                 * before this CRB entry is processed.
+                                 * Set only for barrier operations.
+                                 */
+                timeout: 8;     /* Timeout Upper 8 bits */
+        } icrbd_field_s;
+} icrbd_t;
+
+#define icrbd_toutvld   icrbd_field_s.toutvld
+#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
+#define icrbd_context   icrbd_field_s.context
+
+
+typedef union hubii_ifdr_u {
+        u64     hi_ifdr_value;
+        struct {
+                u64     ifdr_rsvd:      49,
+                        ifdr_maxrp:      7,
+                        ifdr_rsvd1:      1,
+                        ifdr_maxrq:      7;
+        } hi_ifdr_fields;
+} hubii_ifdr_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Hardware designed names for the BTE control registers.
+ */
+#define IIO_IBLS_0      0x410000        /* BTE length/status 0 */
+#define IIO_IBSA_0      0x410008        /* BTE source address 0 */
+#define IIO_IBDA_0      0x410010        /* BTE destination address 0 */
+#define IIO_IBCT_0      0x410018        /* BTE control/terminate 0 */
+#define IIO_IBNA_0      0x410020        /* BTE notification address 0 */
+#define IIO_IBNR_0      IIO_IBNA_0
+#define IIO_IBIA_0      0x410028        /* BTE interrupt address 0 */
+
+#define IIO_IBLS_1      0x420000        /* BTE length/status 1 */
+#define IIO_IBSA_1      0x420008        /* BTE source address 1 */
+#define IIO_IBDA_1      0x420010        /* BTE destination address 1 */
+#define IIO_IBCT_1      0x420018        /* BTE control/terminate 1 */
+#define IIO_IBNA_1      0x420020        /* BTE notification address 1 */
+#define IIO_IBNR_1      IIO_IBNA_1
+#define IIO_IBIA_1      0x420028        /* BTE interrupt address 1 */
+
+/*
+ * More miscellaneous registers
+ */
+#define IIO_IPCR        0x430000        /* Performance Control */
+#define IIO_IPPR        0x430008        /* Performance Profiling */
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_BTE1              (1 << 18)  /* clear bte error 1 ??? */
+#define IECLR_BTE0              (1 << 17)  /* clear bte error 0 ??? */
+#define IECLR_CRAZY             (1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IO PIO Read Table Entry format
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union iprte_a {
+        u64     entry;
+        struct {
+            u64 rsvd1     : 7,  /* Reserved field               */
+                valid     : 1,  /* Maps to a timeout entry      */
+                rsvd2     : 1,
+                srcnode   : 9,  /* Node which did this PIO      */
+                initiator : 2,  /* If T5A or T5B or IO          */
+                rsvd3     : 3,
+                addr      : 38, /* Physical address of PIO      */
+                rsvd4     : 3;
+        } iprte_fields;
+} iprte_a_t;
+
+#define iprte_valid     iprte_fields.valid
+#define iprte_timeout   iprte_fields.timeout
+#define iprte_srcnode   iprte_fields.srcnode
+#define iprte_init      iprte_fields.initiator
+#define iprte_addr      iprte_fields.addr
+
+#endif /* !__ASSEMBLY__ */
+
+#define IPRTE_ADDRSHFT  3
+
+/*
+ * Hub IIO PRB Register format.
+ */
+
+#ifndef __ASSEMBLY__
+/*
+ * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
+ * "Status" fields, and should only be used in case of clean up after errors.
+ */
+
+typedef union iprb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  15,
+                error:  1,      /* Widget rcvd wr resp pkt w/ error */
+                ovflow: 5,      /* Over flow count. perf measurement */
+                fire_and_forget: 1, /* Launch Write without response */
+                mode:   2,      /* Widget operation Mode        */
+                rsvd2:  2,
+                bnakctr: 14,
+                rsvd3:  2,
+                anakctr: 14,
+                xtalkctr: 8;
+        } iprb_fields_s;
+} iprb_t;
+
+#define iprb_regval     reg_value
+
+#define iprb_error      iprb_fields_s.error
+#define iprb_ovflow     iprb_fields_s.ovflow
+#define iprb_ff         iprb_fields_s.fire_and_forget
+#define iprb_mode       iprb_fields_s.mode
+#define iprb_bnakctr    iprb_fields_s.bnakctr
+#define iprb_anakctr    iprb_fields_s.anakctr
+#define iprb_xtalkctr   iprb_fields_s.xtalkctr
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for mode field in iprb_t.
+ * For details of the meanings of NAK and Accept, refer the PIO flow
+ * document
+ */
+#define IPRB_MODE_NORMAL        (0)
+#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+
+/*
+ * IO CRB entry C_A to E_A : Partial (cache) CRBS
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbp_a {
+        u64   ip_reg;       /* the entire register value        */
+        struct {
+             u64 error: 1,  /*    63, error occurred            */
+                ln_uce: 1,  /*    62: uncorrectable memory      */
+                ln_ae:  1,  /*    61: protection violation      */
+                ln_werr:1,  /*    60: write access error        */
+                ln_aerr:1,  /*    59: sn0net: Address error     */
+                ln_perr:1,  /*    58: sn0net: poison error      */
+                timeout:1,  /*    57: CRB timed out             */
+                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+                c_err:  1,  /*    54: incoming xtalk req, err set*/
+                rsvd1: 12,  /* 53-42: reserved                  */
+                valid:  1,  /*    41: Valid status              */
+                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
+                tnum:   5,  /* 36-32: TNUM of xtalk request     */
+                bo:     1,  /*    31: barrier op set in xtalk rqst*/
+                resprqd:1,  /*    30: xtalk rqst requires response*/
+                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+                size:   2,  /* 28-27: size of xtalk request     */
+                excl:   4,  /* 26-23: exclusive bit(s)          */
+                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
+                intvn:  1,  /*    19: rqst target of intervention*/
+                resp:   1,  /*    18: Data response given to t5 */
+                ack:    1,  /*    17: Data ack received.        */
+                hold:   1,  /*    16: crb gathering invalidate acks*/
+                wb:     1,  /*    15: writeback pending.        */
+                ack_cnt:11, /* 14-04: counter of invalidate acks*/
+                tscaler:4;  /* 03-00: Timeout prescaler         */
+        } ip_fmt;
+} icrbp_a_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * A couple of defines to go with the above structure.
+ */
+#define ICRBP_A_CERR_SHFT       54
+#define ICRBP_A_ERR_MASK        0x3ff
+
+#ifndef __ASSEMBLY__
+typedef union hubii_idsr {
+        u64 iin_reg;
+        struct {
+                u64 rsvd1 : 35,
+                    isent : 1,
+                    rsvd2 : 3,
+                    ienable: 1,
+                    rsvd  : 7,
+                    node  : 9,
+                    rsvd4 : 1,
+                    level : 7;
+        } iin_fmt;
+} hubii_idsr_t;
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1 << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1 << 8)
+#define IBCT_NOTIFY             (0x1 << 4)
+#define IBCT_ZFIL_MODE          (0x1 << 0)
+
+/*
+ * IO BTE Interrupt Address Register (IBIA) register bit field definitions
+ */
+#define IBIA_LEVEL_SHFT         16
+#define IBIA_LEVEL_MASK         (0x7f << IBIA_LEVEL_SHFT)
+#define IBIA_NODE_ID_SHFT       0
+#define IBIA_NODE_ID_MASK       (0x1ff)
+
+/*
+ * Miscellaneous hub constants
+ */
+
+/* Number of widgets supported by hub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc101
+#define MAX_HUBS_PER_XBOW       2
+
+/*
+ * Get a hub's widget id from widget control register
+ */
+#define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
+#define IIO_WST_ERROR_MASK      (UINT64_CAST 1 << 32) /* Widget status error */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h
new file mode 100644
index 000000000000..a66def4e0ba0
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubmd.h
@@ -0,0 +1,790 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H
+
+#include <linux/config.h>
+
+/*
+ * Hub Memory/Directory interface registers
+ */
+#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
+
+#define MAX_REGIONS             64
+
+/* Hardware page size and shift */
+
+#define MD_PAGE_SIZE            4096     /* Page size in bytes              */
+#define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
+
+/* Register offsets from LOCAL_HUB or REMOTE_HUB */
+
+#define MD_BASE                 0x200000
+#define MD_BASE_PERF            0x210000
+#define MD_BASE_JUNK            0x220000
+
+#define MD_IO_PROTECT           0x200000 /* MD and core register protection */
+#define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
+#define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
+#define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
+#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
+#define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
+#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
+#define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
+#define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
+#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
+#define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
+
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
+
+#define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
+#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
+
+#ifdef CONFIG_SGI_SN0_N_MODE
+#define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
+#else
+#define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
+#endif
+
+/*
+ * MD_MEMORY_CONFIG fields
+ *
+ *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
+ *   (SIMM pair).  They correspond to the values needed for the bit
+ *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
+ *   Bits not used by the MD are used by software.
+ */
+
+#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_8MB             1
+#define MD_SIZE_16MB            2
+#define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
+#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_256MB           6
+#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_1GB             8
+#define MD_SIZE_2GB             9
+#define MD_SIZE_4GB             10
+
+#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
+#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
+
+#define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
+#define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
+#define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
+#define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
+#define MMC_UCTLR_CYC_SHFT      39
+#define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
+#define MMC_UCTLR_WR_SHFT       34
+#define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
+#define MMC_DIMM0_SEL_SHFT      32
+#define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
+#define MMC_IO_PROT_EN_SHFT     31
+#define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
+#define MMC_IO_PROT             (UINT64_CAST 1 << 31)
+#define MMC_ARB_MLSS_SHFT       30
+#define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
+#define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
+#define MMC_IGNORE_ECC_SHFT     29
+#define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
+#define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
+#define MMC_DIR_PREMIUM_SHFT    28
+#define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
+#define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
+#define MMC_REPLY_GUAR_SHFT     24
+#define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
+#define MMC_BANK_SHFT(_b)       ((_b) * 3)
+#define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
+#define MMC_BANK_ALL_MASK       0xffffff
+#define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
+                                 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
+                                 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
+                                 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
+                                 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
+                                 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
+                                 MMC_BANK_ALL_MASK)
+
+/* MD_REFRESH_CONTROL fields */
+
+#define MRC_ENABLE_SHFT         63
+#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
+#define MRC_ENABLE              (UINT64_CAST 1 << 63)
+#define MRC_COUNTER_SHFT        12
+#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
+#define MRC_CNT_THRESH_MASK     0xfff
+#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
+
+/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
+
+#define MDI_SELECT_SHFT         32
+#define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
+#define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
+
+/* MD_MOQ_SIZE fields */
+
+#define MMS_RP_SIZE_SHFT        8
+#define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
+#define MMS_RQ_SIZE_SHFT        0
+#define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
+#define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
+
+/* MD_FANDOP_CAC_STAT fields */
+
+#define MFC_VALID_SHFT          63
+#define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
+#define MFC_VALID               (UINT64_CAST 1 << 63)
+#define MFC_ADDR_SHFT           6
+#define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
+
+/* MD_MLAN_CTL fields */
+
+#define MLAN_PHI1_SHFT          27
+#define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PHI0_SHFT          20
+#define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PULSE_SHFT         10
+#define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
+#define MLAN_SAMPLE_SHFT        2
+#define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
+#define MLAN_DONE_SHFT          1
+#define MLAN_DONE_MASK          2
+#define MLAN_DONE               (UINT64_CAST 0x02)
+#define MLAN_RD_DATA            (UINT64_CAST 0x01)
+#define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
+                                 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
+
+/* MD_SLOTID_USTAT bit definitions */
+
+#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
+#define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
+#define MSU_CORECLK             (UINT64_CAST 1 << 6)
+#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
+#define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
+#define MSU_NETSYNC             (UINT64_CAST 1 << 5)
+#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
+#define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
+#define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
+#define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
+#define MSU_I2CINTR             (UINT64_CAST 1 << 3)
+#define MSU_SLOTID_MASK         0xff
+#define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
+#define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
+#define MSU_SN00_SLOTID_SHFT    7
+#define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
+
+#define MSU_PIMM_PSC_SHFT       4
+#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+
+/* MD_MIG_DIFF_THRESH bit definitions */
+
+#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_DIFF_THRES_VALID_SHFT 63
+#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_VALUE_THRESH bit definitions */
+
+#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_VALUE_THRES_VALID_SHFT 63
+#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_CANDIDATE bit definitions */
+
+#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_CANDIDATE_VALID_SHFT 63
+#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
+#define MD_MIG_CANDIDATE_TYPE_SHFT 30
+#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
+#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
+#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
+#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
+#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
+#define MD_MIG_CANDIDATE_NODEID_SHFT 20
+#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
+#define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
+
+/* Other MD definitions */
+
+#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
+#define MD_BANK_MASK            (UINT64_CAST 7 << 29)
+#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
+#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*
+ * The following definitions cover the bit field definitions for the
+ * various MD registers.  For multi-bit registers, we define both
+ * a shift amount and a mask value.  By convention, if you want to
+ * isolate a field, you should mask the field and then shift it down,
+ * since this makes the masks useful without a shift.
+ */
+
+/* Directory entry states for both premium and standard SIMMs. */
+
+#define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
+#define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
+#define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
+#define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
+#define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
+#define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
+#define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
+
+/*
+ * The MD_DIR_FORCE_ECC bit can be added directory entry write data
+ * to forcing the ECC to be written as-is instead of recalculated.
+ */
+
+#define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
+
+/*
+ * Premium SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A, B, and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE = shared, FINE = 1
+ * Format B:  STATE = shared, FINE = 0
+ * Format C:  STATE != shared (FINE must be 0)
+ */
+
+#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
+#define MD_PDIR_ECC_MASK        0x7f
+#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
+#define MD_PDIR_PRIO_MASK       (0xf << 8)
+#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
+#define MD_PDIR_AX_MASK         (1 << 7)
+#define MD_PDIR_AX              (1 << 7)
+#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
+#define MD_PDIR_FINE_MASK       (1 << 12)
+#define MD_PDIR_FINE            (1 << 12)
+#define MD_PDIR_OCT_SHFT        13                      /* A low            */
+#define MD_PDIR_OCT_MASK        (7 << 13)
+#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
+#define MD_PDIR_STATE_MASK      (7 << 13)
+#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
+#define MD_PDIR_ONECNT_MASK     (0x3f << 16)
+#define MD_PDIR_PTR_SHFT        22                      /* C low            */
+#define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
+#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
+#define MD_PDIR_VECMSB_BITMASK  0x3ffffff
+#define MD_PDIR_VECMSB_BITSHFT  27
+#define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
+#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
+#define MD_PDIR_CWOFF_MASK      (7 << 7)
+#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
+#define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
+#define MD_PDIR_VECLSB_BITSHFT  0
+#define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
+                                 MD_PDIR_AX)
+#define MD_PDIR_INIT_HI         0
+#define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
+                                 MD_PROT_RW << MD_PPROT_SHFT)
+
+/*
+ * Standard SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE == shared
+ * Format C:  STATE != shared
+ */
+
+#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
+#define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
+#define MD_SDIR_ECC_MASK        0x1f
+#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
+#define MD_SDIR_PRIO_MASK       (1 << 6)
+#define MD_SDIR_AX_SHFT         5                       /* AC low           */
+#define MD_SDIR_AX_MASK         (1 << 5)
+#define MD_SDIR_AX              (1 << 5)
+#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
+#define MD_SDIR_STATE_MASK      (7 << 7)
+#define MD_SDIR_PTR_SHFT        10                      /* C low            */
+#define MD_SDIR_PTR_MASK        (0x3f << 10)
+#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
+#define MD_SDIR_CWOFF_MASK      (7 << 5)
+#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
+#define MD_SDIR_VECMSB_BITMASK  0x1f
+#define MD_SDIR_VECMSB_BITSHFT  7
+#define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
+#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
+#define MD_SDIR_VECLSB_BITMASK  0x7ff
+#define MD_SDIR_VECLSB_BITSHFT  0
+#define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
+                                 MD_SDIR_AX)
+#define MD_SDIR_INIT_HI         0
+#define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
+
+/* Protection and migration field values */
+
+#define MD_PROT_RW              (UINT64_CAST 0x6)
+#define MD_PROT_RO              (UINT64_CAST 0x3)
+#define MD_PROT_NO              (UINT64_CAST 0x0)
+#define MD_PROT_BAD             (UINT64_CAST 0x5)
+
+/* Premium SIMM protection entry shifts and masks. */
+
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_MASK           7
+#define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_PPROT_MIGMD_MASK     (3 << 3)
+#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_PPROT_REFCNT_WIDTH   0x7ffff
+#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
+
+#define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
+#define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
+
+/* Standard SIMM protection entry shifts and masks. */
+
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_MASK           7
+#define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_SPROT_MIGMD_MASK     (3 << 3)
+#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_SPROT_REFCNT_WIDTH   0x7ff
+#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
+
+/* Migration modes used in protection entries */
+
+#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
+#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
+#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
+#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
+
+
+/*
+ * Operations on page migration threshold register
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * LED register macros
+ */
+
+#define CPU_LED_ADDR(_nasid, _slice)                                       \
+        (private.p_sn00 ?                                                  \
+         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
+
+#define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
+        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
+
+#define SET_MY_LEDS(_v)                                                    \
+        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
+
+/*
+ * Operations on Memory/Directory DIMM control register
+ */
+
+#define DIRTYPE_PREMIUM 1
+#define DIRTYPE_STANDARD 0
+#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
+        (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
+        MMC_DIR_PREMIUM_SHFT)
+
+
+/*
+ * Operations on page migration count difference and absolute threshold
+ * registers
+ */
+
+#define MD_MIG_DIFF_THRESH_GET(region) ( \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
+        MD_MIG_DIFF_THRES_VALUE_MASK)
+
+#define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                MD_MIG_DIFF_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             & ~MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             | MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
+               MD_MIG_DIFF_THRES_VALID_MASK)
+
+#define MD_MIG_VALUE_THRESH_GET(region) (                               \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
+        MD_MIG_VALUE_THRES_VALUE_MASK)
+
+#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
+                             & ~MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
+                             | MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
+               MD_MIG_VALUE_THRES_VALID_MASK)
+
+/*
+ * Operations on page migration candidate register
+ */
+
+#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
+        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
+
+#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
+
+#define MD_MIG_CANDIDATE_NODEID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
+
+#define MD_MIG_CANDIDATE_TYPE(value) ( \
+        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
+
+#define MD_MIG_CANDIDATE_VALID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
+
+/*
+ * Macros to retrieve fields in the protection entry
+ */
+
+/* for Premium SIMM */
+#define MD_PPROT_REFCNT_GET(value) ( \
+        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
+
+#define MD_PPROT_MIGMD_GET(value) ( \
+        ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
+
+/* for Standard SIMM */
+#define MD_SPROT_REFCNT_GET(value) ( \
+        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
+
+#define MD_SPROT_MIGMD_GET(value) ( \
+        ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
+
+/*
+ * Format of dir_error, mem_error, protocol_error and misc_error registers
+ */
+
+struct dir_error_reg {
+        u64     uce_vld:   1,   /*    63: valid directory uce   */
+                ae_vld:    1,   /*    62: valid dir prot ecc error */
+                ce_vld:    1,   /*    61: valid correctable ECC err*/
+                rsvd1:    19,   /* 60-42: reserved              */
+                bad_prot:  3,   /* 41-39: encoding, bad access rights*/
+                bad_syn:   7,   /* 38-32: bad dir syndrome      */
+                rsvd2:     2,   /* 31-30: reserved              */
+                hspec_addr:27,  /* 29-03: bddir space bad entry */
+                uce_ovr:   1,   /*     2: multiple dir uce's    */
+                ae_ovr:    1,   /*     1: multiple prot ecc errs*/
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+typedef union md_dir_error {
+        u64     derr_reg;       /* the entire register          */
+        struct dir_error_reg derr_fmt;  /* the register format          */
+} md_dir_error_t;
+
+
+struct mem_error_reg {
+        u64     uce_vld:   1,   /*    63: valid memory uce      */
+                ce_vld:    1,   /*    62: valid correctable ECC err*/
+                rsvd1:    22,   /* 61-40: reserved              */
+                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
+                address:  29,   /* 31-03: bad entry pointer     */
+                rsvd2:     1,   /*     2: reserved              */
+                uce_ovr:   1,   /*     1: multiple mem uce's    */
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+
+typedef union md_mem_error {
+        u64     merr_reg;       /* the entire register          */
+        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+} md_mem_error_t;
+
+
+struct proto_error_reg {
+        u64     valid:     1,   /*    63: valid protocol error  */
+                rsvd1:     2,   /* 62-61: reserved              */
+                initiator:11,   /* 60-50: id of request initiator*/
+                backoff:   2,   /* 49-48: backoff control       */
+                msg_type:  8,   /* 47-40: type of request       */
+                access:    2,   /* 39-38: access rights of initiator*/
+                priority:  1,   /*    37: priority level of requestor*/
+                dir_state: 4,   /* 36-33: state of directory    */
+                pointer_me:1,   /*    32: initiator same as dir ptr */
+                address:  29,   /* 31-03: request address       */
+                rsvd2:     2,   /* 02-01: reserved              */
+                overrun:   1;   /*     0: multiple protocol errs */
+};
+
+typedef union md_proto_error {
+        u64     perr_reg;       /* the entire register          */
+        struct proto_error_reg  perr_fmt; /* format of the register     */
+} md_proto_error_t;
+
+
+struct md_sdir_high_fmt {
+        unsigned short sd_hi_bvec : 11,
+                       sd_hi_ecc  : 5;
+};
+
+
+typedef union md_sdir_high {
+        /* The 16 bits of standard directory, upper word */
+        unsigned short sd_hi_val;
+        struct  md_sdir_high_fmt sd_hi_fmt;
+}md_sdir_high_t;
+
+
+struct md_sdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        unsigned short  sds_lo_bvec  : 5,
+                        sds_lo_unused: 1,
+                        sds_lo_state : 3,
+                        sds_lo_prio  : 1,
+                        sds_lo_ax    : 1,
+                        sds_lo_ecc   : 5;
+};
+
+struct md_sdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        unsigned short  sde_lo_ptr   : 6,
+                        sde_lo_state : 3,
+                        sde_lo_prio  : 1,
+                        sde_lo_ax    : 1,
+                        sde_lo_ecc   : 5;
+};
+
+
+typedef union md_sdir_low {
+        /* The 16 bits of standard directory, lower word */
+        unsigned short  sd_lo_val;
+        struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
+        struct  md_sdir_low_shared_fmt sds_lo_fmt;
+}md_sdir_low_t;
+
+
+
+struct md_pdir_high_fmt {
+        u64     pd_hi_unused   : 16,
+                pd_hi_bvec     : 38,
+                pd_hi_unused1  : 3,
+                pd_hi_ecc      : 7;
+};
+
+
+typedef union md_pdir_high {
+        /* The 48 bits of standard directory, upper word */
+        u64     pd_hi_val;
+        struct md_pdir_high_fmt pd_hi_fmt;
+}md_pdir_high_t;
+
+
+struct md_pdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        u64     pds_lo_unused   : 16,
+                pds_lo_bvec     : 26,
+                pds_lo_cnt      :  6,
+                pds_lo_state    :  3,
+                pds_lo_ste      :  1,
+                pds_lo_prio     :  4,
+                pds_lo_ax       :  1,
+                pds_lo_ecc      :  7;
+};
+
+struct md_pdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        u64     pde_lo_unused   : 31,
+                pde_lo_ptr      : 11,
+                pde_lo_unused1  :  6,
+                pde_lo_state    :  3,
+                pde_lo_ste      :  1,
+                pde_lo_prio     :  4,
+                pde_lo_ax       :  1,
+                pde_lo_ecc      :  7;
+};
+
+
+typedef union md_pdir_loent {
+        /* The 48 bits of premium directory, lower word */
+        u64     pd_lo_val;
+        struct md_pdir_low_exclusive_fmt pde_lo_fmt;
+        struct md_pdir_low_shared_fmt   pds_lo_fmt;
+}md_pdir_low_t;
+
+
+/*
+ *   the following two "union" definitions and two
+ *   "struct" definitions are used in vmdump.c to
+ *   represent directory memory information.
+ */
+
+typedef union   md_dir_high     {
+        md_sdir_high_t  md_sdir_high;
+        md_pdir_high_t  md_pdir_high;
+} md_dir_high_t;
+
+typedef union   md_dir_low      {
+        md_sdir_low_t   md_sdir_low;
+        md_pdir_low_t   md_pdir_low;
+} md_dir_low_t;
+
+typedef struct  bddir_entry     {
+        md_dir_low_t    md_dir_low;
+        md_dir_high_t   md_dir_high;
+} bddir_entry_t;
+
+typedef struct  dir_mem_entry   {
+        u64             prcpf[MAX_REGIONS];
+        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+} dir_mem_entry_t;
+
+
+
+typedef union md_perf_sel {
+        u64     perf_sel_reg;
+        struct  {
+                u64     perf_rsvd : 60,
+                        perf_en   :  1,
+                        perf_sel  :  3;
+        } perf_sel_bits;
+} md_perf_sel_t;
+
+typedef union md_perf_cnt {
+        u64     perf_cnt;
+        struct  {
+                u64     perf_rsvd : 44,
+                        perf_cnt  : 20;
+        } perf_cnt_bits;
+} md_perf_cnt_t;
+
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define DIR_ERROR_VALID_MASK    0xe000000000000000
+#define DIR_ERROR_VALID_SHFT    61
+#define DIR_ERROR_VALID_UCE     0x8000000000000000
+#define DIR_ERROR_VALID_AE      0x4000000000000000
+#define DIR_ERROR_VALID_CE      0x2000000000000000
+
+#define MEM_ERROR_VALID_MASK    0xc000000000000000
+#define MEM_ERROR_VALID_SHFT    62
+#define MEM_ERROR_VALID_UCE     0x8000000000000000
+#define MEM_ERROR_VALID_CE      0x4000000000000000
+
+#define PROTO_ERROR_VALID_MASK  0x8000000000000000
+
+#define MISC_ERROR_VALID_MASK   0x3ff
+
+/*
+ * Mask for hspec address that is stored in the dir error register.
+ * This represents bits 29 through 3.
+ */
+#define DIR_ERR_HSPEC_MASK      0x3ffffff8
+#define ERROR_HSPEC_MASK        0x3ffffff8
+#define ERROR_HSPEC_SHFT        3
+#define ERROR_ADDR_MASK         0xfffffff8
+#define ERROR_ADDR_SHFT         3
+
+/*
+ * MD_MISC_ERROR register defines.
+ */
+
+#define MMCE_VALID_MASK         0x3ff
+#define MMCE_ILL_MSG_SHFT       8
+#define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
+#define MMCE_ILL_REV_SHFT       6
+#define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
+#define MMCE_LONG_PACK_SHFT     4
+#define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
+#define MMCE_SHORT_PACK_SHFT    2
+#define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
+#define MMCE_BAD_DATA_SHFT      0
+#define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
+
+
+#define MD_PERF_COUNTERS        6
+#define MD_PERF_SETS            6
+
+#define MEM_DIMM_MASK                           0xe0000000
+#define MEM_DIMM_SHFT                           29
+
+#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/include/asm-mips/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h
new file mode 100644
index 000000000000..b40d3ef97a12
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubni.h
@@ -0,0 +1,255 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
+ *
+ * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN0_HUBNI_H
+#define _ASM_SGI_SN0_HUBNI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
+/*
+ * Hub Network Interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ */
+
+#define NI_BASE                 0x600000
+#define NI_BASE_TABLES          0x630000
+
+#define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
+#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
+#define NI_PROTECTION           0x600010 /* NI register access permissions  */
+#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
+#define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
+#define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
+#define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
+
+#define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
+#define NI_VECTOR               0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
+#define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
+
+#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
+#define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
+#define NI_AGE_REG_MAX          NI_AGE_IO_PIO
+
+#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
+
+#define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
+#define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
+#define NI_META_ENTRIES         32
+
+#define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
+#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
+#define NI_LOCAL_ENTRIES        16
+
+/*
+ * NI_STATUS_REV_ID mask and shift definitions
+ * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
+ */
+
+#define NSRI_8BITMODE_SHFT      30
+#define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
+#define NSRI_LINKUP_SHFT        29
+#define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
+#define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
+#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_MORENODES_SHFT     18
+#define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
+#define  MORE_MEMORY            0
+#define  MORE_NODES             1
+#define NSRI_REGIONSIZE_SHFT    17
+#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
+#define  REGIONSIZE_FINE        1
+#define  REGIONSIZE_COARSE      0
+#define NSRI_NODEID_SHFT        8
+#define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
+#define NSRI_REV_SHFT           4
+#define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
+#define NSRI_CHIPID_SHFT        0
+#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
+
+/*
+ * In fine mode, each node is a region.  In coarse mode, there are
+ * eight nodes per region.
+ */
+#define NASID_TO_FINEREG_SHFT   0
+#define NASID_TO_COARSEREG_SHFT 3
+
+/* NI_PORT_RESET mask definitions */
+
+#define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
+#define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
+#define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
+
+/* NI_PROTECTION mask and shift definitions */
+
+#define NPROT_RESETOK           (UINT64_CAST 1)
+
+/* NI_GLOBAL_PARMS mask and shift definitions */
+
+#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
+#define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
+#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
+
+#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
+#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
+
+/* NI_DIAG_PARMS mask and shift definitions */
+
+#define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
+#define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
+
+/*
+ * NI_VECTOR_PARMS mask and shift definitions.
+ * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
+ */
+
+#define NVP_PIOID_SHFT          40
+#define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVP_WRITEID_SHFT        32
+#define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_TYPE_SHFT           0
+#define NVP_TYPE_MASK           (UINT64_CAST 0x3)
+
+/* NI_VECTOR_STATUS mask and shift definitions */
+
+#define NVS_VALID               (UINT64_CAST 1 << 63)
+#define NVS_OVERRUN             (UINT64_CAST 1 << 62)
+#define NVS_TARGET_SHFT         51
+#define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
+#define NVS_PIOID_SHFT          40
+#define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVS_WRITEID_SHFT        32
+#define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_TYPE_SHFT           0
+#define NVS_TYPE_MASK           (UINT64_CAST 0x7)
+#define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
+
+
+#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+
+/* NI_AGE_XXX mask and shift definitions */
+
+#define NAGE_VCH_SHFT           10
+#define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
+#define NAGE_CC_SHFT            8
+#define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
+#define NAGE_AGE_SHFT           0
+#define NAGE_AGE_MASK           (UINT64_CAST 0xff)
+#define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
+
+#define  VCHANNEL_A             0
+#define  VCHANNEL_B             1
+#define  VCHANNEL_ANY           2
+
+/* NI_PORT_PARMS mask and shift definitions */
+
+#define NPP_NULLTO_SHFT         10
+#define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
+#define NPP_MAXBURST_SHFT       0
+#define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
+#define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+#define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+
+
+/* NI_PORT_ERROR mask and shift definitions */
+
+#define NPE_LINKRESET           (UINT64_CAST 1 << 37)
+#define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
+#define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
+#define NPE_BADDEST             (UINT64_CAST 1 << 34)
+#define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
+#define NPE_CREDITTO_SHFT       28
+#define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
+#define NPE_TAILTO_SHFT         24
+#define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
+#define NPE_RETRYCOUNT_SHFT     16
+#define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
+#define NPE_CBERRCOUNT_SHFT     8
+#define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
+#define NPE_SNERRCOUNT_SHFT     0
+#define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
+#define NPE_MASK                0x3effffffff
+
+#define NPE_COUNT_MAX           0xff
+
+#define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
+                                 NPE_BADMESSAGE | NPE_BADDEST |         \
+                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                 NPE_TAILTO_MASK)
+
+/* NI_META_TABLE mask and shift definitions */
+
+#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+/* NI_LOCAL_TABLE mask and shift definitions */
+
+#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+#ifndef __ASSEMBLY__
+
+typedef union   hubni_port_error_u {
+        u64     nipe_reg_value;
+        struct {
+            u64 nipe_rsvd:      26,     /* unused */
+                nipe_lnk_reset:  1,     /* link reset */
+                nipe_intl_err:   1,     /* internal error */
+                nipe_bad_msg:    1,     /* bad message */
+                nipe_bad_dest:   1,     /* bad dest     */
+                nipe_fifo_ovfl:  1,     /* fifo overflow */
+                nipe_rsvd1:      1,     /* unused */
+                nipe_credit_to:  4,     /* credit timeout */
+                nipe_tail_to:    4,     /* tail timeout */
+                nipe_retry_cnt:  8,     /* retry error count */
+                nipe_cb_cnt:     8,     /* checkbit error count */
+                nipe_sn_cnt:     8;     /* sequence number count */
+        } nipe_fields_s;
+} hubni_port_error_t;
+
+#define NI_LLP_RETRY_MAX        0xff
+#define NI_LLP_CB_MAX           0xff
+#define NI_LLP_SN_MAX           0xff
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h
new file mode 100644
index 000000000000..355bba8552e3
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubpi.h
@@ -0,0 +1,427 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H
+
+#include <linux/types.h>
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * All register "addresses" are actually offsets.  Use the LOCAL_HUB
+ * or REMOTE_HUB macros to synthesize an actual address
+ */
+
+#define PI_BASE                 0x000000
+
+/* General protection and control registers */
+
+#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
+#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
+#define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
+
+/* CALIAS values */
+#define PI_CALIAS_SIZE_0        0
+#define PI_CALIAS_SIZE_4K       1
+#define PI_CALIAS_SIZE_8K       2
+#define PI_CALIAS_SIZE_16K      3
+#define PI_CALIAS_SIZE_32K      4
+#define PI_CALIAS_SIZE_64K      5
+#define PI_CALIAS_SIZE_128K     6
+#define PI_CALIAS_SIZE_256K     7
+#define PI_CALIAS_SIZE_512K     8
+#define PI_CALIAS_SIZE_1M       9
+#define PI_CALIAS_SIZE_2M       10
+#define PI_CALIAS_SIZE_4M       11
+#define PI_CALIAS_SIZE_8M       12
+#define PI_CALIAS_SIZE_16M      13
+#define PI_CALIAS_SIZE_32M      14
+#define PI_CALIAS_SIZE_64M      15
+
+/* Processor control and status checking */
+
+#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
+#define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
+#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
+#define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
+#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
+
+/* Regular Interrupt register checking.  */
+
+#define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
+#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
+
+#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
+
+/* Crosscall interrupts */
+
+#define PI_CC_PEND_SET_A        0x0000c8 /* CC Interrupt Pending Set, CPU A */
+#define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
+#define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
+#define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
+#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
+
+#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
+
+/* Realtime Counter and Profiler control registers */
+
+#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
+#define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
+#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
+#define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
+#define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
+#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
+#define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
+
+#define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
+
+/* Built-In Self Test support */
+
+#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
+
+/* Graphics control registers */
+
+#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
+#define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
+#define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
+#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
+#define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
+#define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
+
+#define PI_GFX_OFFSET           (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
+#define PI_GFX_PAGE_ENABLE      0x0000010000000000LL
+
+/* Error and timeout registers */
+#define PI_ERR_INT_PEND         0x000400 /* Error Interrupt Pending         */
+#define PI_ERR_INT_MASK_A       0x000408 /* Error Interrupt mask for CPU A  */
+#define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
+#define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
+#define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
+#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
+#define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
+#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
+#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
+#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
+#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
+#define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
+#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
+#define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
+#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
+#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
+#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
+
+/* Bits in PI_ERR_INT_PEND */
+#define PI_ERR_SPOOL_CMP_B      0x00000001      /* Spool end hit high water */
+#define PI_ERR_SPOOL_CMP_A      0x00000002
+#define PI_ERR_SPUR_MSG_B       0x00000004      /* Spurious message intr.   */
+#define PI_ERR_SPUR_MSG_A       0x00000008
+#define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
+#define PI_ERR_WRB_TERR_A       0x00000020
+#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_A       0x00000080
+#define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
+#define PI_ERR_SYSSTATE_A       0x00000200
+#define PI_ERR_SYSAD_DATA_B     0x00000400      /* SysAD data parity error  */
+#define PI_ERR_SYSAD_DATA_A     0x00000800
+#define PI_ERR_SYSAD_ADDR_B     0x00001000      /* SysAD addr parity error  */
+#define PI_ERR_SYSAD_ADDR_A     0x00002000
+#define PI_ERR_SYSCMD_DATA_B    0x00004000      /* SysCmd data parity error */
+#define PI_ERR_SYSCMD_DATA_A    0x00008000
+#define PI_ERR_SYSCMD_ADDR_B    0x00010000      /* SysCmd addr parity error */
+#define PI_ERR_SYSCMD_ADDR_A    0x00020000
+#define PI_ERR_BAD_SPOOL_B      0x00040000      /* Error spooling to memory */
+#define PI_ERR_BAD_SPOOL_A      0x00080000
+#define PI_ERR_UNCAC_UNCORR_B   0x00100000      /* Uncached uncorrectable   */
+#define PI_ERR_UNCAC_UNCORR_A   0x00200000
+#define PI_ERR_SYSSTATE_TAG_B   0x00400000      /* SysState tag parity error */
+#define PI_ERR_SYSSTATE_TAG_A   0x00800000
+#define PI_ERR_MD_UNCORR        0x01000000      /* Must be cleared in MD    */
+
+#define PI_ERR_CLEAR_ALL_A      0x00aaaaaa
+#define PI_ERR_CLEAR_ALL_B      0x00555555
+
+
+/*
+ * The following three macros define all possible error int pends.
+ */
+
+#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
+                                 PI_ERR_BAD_SPOOL_A     | \
+                                 PI_ERR_SYSCMD_ADDR_A   | \
+                                 PI_ERR_SYSCMD_DATA_A   | \
+                                 PI_ERR_SYSAD_ADDR_A    | \
+                                 PI_ERR_SYSAD_DATA_A    | \
+                                 PI_ERR_SYSSTATE_A)
+
+#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
+                                 PI_ERR_WRB_WERR_A      | \
+                                 PI_ERR_WRB_TERR_A      | \
+                                 PI_ERR_SPUR_MSG_A      | \
+                                 PI_ERR_SPOOL_CMP_A)
+
+#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
+                                 PI_ERR_BAD_SPOOL_B     | \
+                                 PI_ERR_SYSCMD_ADDR_B   | \
+                                 PI_ERR_SYSCMD_DATA_B   | \
+                                 PI_ERR_SYSAD_ADDR_B    | \
+                                 PI_ERR_SYSAD_DATA_B    | \
+                                 PI_ERR_SYSSTATE_B)
+
+#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
+                                 PI_ERR_WRB_WERR_B      | \
+                                 PI_ERR_WRB_TERR_B      | \
+                                 PI_ERR_SPUR_MSG_B      | \
+                                 PI_ERR_SPOOL_CMP_B)
+
+#define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
+
+/*
+ * Error types for PI_ERR_STATUS0_[AB] and error stack:
+ * Use the write types if WRBRRB is 1 else use the read types
+ */
+
+/* Fields in PI_ERR_STATUS0_[AB] */
+#define PI_ERR_ST0_TYPE_MASK    0x0000000000000007
+#define PI_ERR_ST0_TYPE_SHFT    0
+#define PI_ERR_ST0_REQNUM_MASK  0x0000000000000038
+#define PI_ERR_ST0_REQNUM_SHFT  3
+#define PI_ERR_ST0_SUPPL_MASK   0x000000000001ffc0
+#define PI_ERR_ST0_SUPPL_SHFT   6
+#define PI_ERR_ST0_CMD_MASK     0x0000000001fe0000
+#define PI_ERR_ST0_CMD_SHFT     17
+#define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
+#define PI_ERR_ST0_ADDR_SHFT    25
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62
+#define PI_ERR_ST0_VALID_MASK   0x8000000000000000
+#define PI_ERR_ST0_VALID_SHFT   63
+
+/* Fields in PI_ERR_STATUS1_[AB] */
+#define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
+#define PI_ERR_ST1_SPOOL_SHFT   0
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21
+#define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
+#define PI_ERR_ST1_INVCNT_SHFT  29
+#define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
+#define PI_ERR_ST1_CRBNUM_SHFT  39
+#define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
+#define PI_ERR_ST1_WRBRRB_SHFT  42
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43
+#define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
+#define PI_ERR_ST1_MSGSRC_SHFT  53
+
+/* Fields in the error stack */
+#define PI_ERR_STK_TYPE_MASK    0x0000000000000003
+#define PI_ERR_STK_TYPE_SHFT    0
+#define PI_ERR_STK_SUPPL_MASK   0x0000000000000038
+#define PI_ERR_STK_SUPPL_SHFT   3
+#define PI_ERR_STK_REQNUM_MASK  0x00000000000001c0
+#define PI_ERR_STK_REQNUM_SHFT  6
+#define PI_ERR_STK_CRBNUM_MASK  0x0000000000000e00
+#define PI_ERR_STK_CRBNUM_SHFT  9
+#define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
+#define PI_ERR_STK_WRBRRB_SHFT  12
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13
+#define PI_ERR_STK_CMD_MASK     0x000000007f800000
+#define PI_ERR_STK_CMD_SHFT     23
+#define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
+#define PI_ERR_STK_ADDR_SHFT    31
+
+/* Error type in the error status or stack on Read CRBs */
+#define PI_ERR_RD_PRERR         1
+#define PI_ERR_RD_DERR          2
+#define PI_ERR_RD_TERR          3
+
+/* Error type in the error status or stack on Write CRBs */
+#define PI_ERR_WR_WERR          0
+#define PI_ERR_WR_PWERR         1
+#define PI_ERR_WR_TERR          3
+
+/* Read or Write CRB in error status or stack */
+#define PI_ERR_RRB      0
+#define PI_ERR_WRB      1
+#define PI_ERR_ANY_CRB  2
+
+/* Address masks in the error status and error stack are not the same */
+#define ERR_STK_ADDR_SHFT       7
+#define ERR_STAT0_ADDR_SHFT     3
+
+#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
+#define PI_STACK_SIZE_SHFT      12      /* 4k */
+
+#define ERR_STACK_SIZE_BYTES(_sz) \
+       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
+
+#ifndef __ASSEMBLY__
+/*
+ * format of error stack and error status registers.
+ */
+
+struct err_stack_format {
+        u64     sk_addr    : 33,   /* address */
+                sk_cmd     :  8,   /* message command */
+                sk_crb_sts : 10,   /* status from RRB or WRB */
+                sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                sk_t5_req  :  3,   /* RRB T5 request number */
+                sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+                sk_err_type:  3;   /* error type        */
+};
+
+typedef union pi_err_stack {
+        u64     pi_stk_word;
+        struct  err_stack_format pi_stk_fmt;
+} pi_err_stack_t;
+
+struct err_status0_format {
+        u64     s0_valid   :  1,   /* Valid */
+                s0_ovr_run :  1,   /* Overrun, spooled to memory */
+                s0_addr    : 37,   /* address */
+                s0_cmd     :  8,   /* message command */
+                s0_supl    : 11,   /* message supplemental field */
+                s0_t5_req  :  3,   /* RRB T5 request number */
+                s0_err_type:  3;   /* error type */
+};
+
+typedef union pi_err_stat0 {
+        u64     pi_stat0_word;
+        struct err_status0_format pi_stat0_fmt;
+} pi_err_stat0_t;
+
+struct err_status1_format {
+        u64     s1_src     : 11,   /* message source */
+                s1_crb_sts : 10,   /* status from RRB or WRB */
+                s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                s1_inval_cnt:10,   /* signed invalidate counter RRB */
+                s1_to_cnt  :  8,   /* crb timeout counter */
+                s1_spl_cnt : 21;   /* number spooled to memory */
+};
+
+typedef union pi_err_stat1 {
+        u64     pi_stat1_word;
+        struct err_status1_format pi_stat1_fmt;
+} pi_err_stat1_t;
+
+typedef u64     rtc_time_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* Bits in PI_SYSAD_ERRCHK_EN */
+#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
+#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
+
+/* Interrupt pending bits on R10000 */
+
+#define HUB_IP_PEND0            0x0400
+#define HUB_IP_PEND1_CC         0x0800
+#define HUB_IP_RT               0x1000
+#define HUB_IP_PROF             0x2000
+#define HUB_IP_ERROR            0x4000
+#define HUB_IP_MASK             0x7c00
+
+/* PI_RT_LOCAL_CTRL mask and shift definitions */
+
+#define PRLC_USE_INT_SHFT       16
+#define PRLC_USE_INT_MASK       (UINT64_CAST 1 << 16)
+#define PRLC_USE_INT            (UINT64_CAST 1 << 16)
+#define PRLC_GCLK_SHFT          15
+#define PRLC_GCLK_MASK          (UINT64_CAST 1 << 15)
+#define PRLC_GCLK               (UINT64_CAST 1 << 15)
+#define PRLC_GCLK_COUNT_SHFT    8
+#define PRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x7f << 8)
+#define PRLC_MAX_COUNT_SHFT     1
+#define PRLC_MAX_COUNT_MASK     (UINT64_CAST 0x7f << 1)
+#define PRLC_GCLK_EN_SHFT       0
+#define PRLC_GCLK_EN_MASK       (UINT64_CAST 1)
+#define PRLC_GCLK_EN            (UINT64_CAST 1)
+
+/* PI_RT_FILTER_CTRL mask and shift definitions */
+
+#if 0
+/*
+ * XXX - This register's definition has changed, but it's only implemented
+ * in Hub 2.
+ */
+#define PRFC_DROP_COUNT_SHFT    27
+#define PRFC_DROP_COUNT_MASK    (UINT64_CAST 0x3ff << 27)
+#define PRFC_DROP_CTR_SHFT      18
+#define PRFC_DROP_CTR_MASK      (UINT64_CAST 0x1ff << 18)
+#define PRFC_MASK_ENABLE_SHFT   10
+#define PRFC_MASK_ENABLE_MASK   (UINT64_CAST 0x7f << 10)
+#define PRFC_MASK_CTR_SHFT      2
+#define PRFC_MASK_CTR_MASK      (UINT64_CAST 0xff << 2)
+#define PRFC_OFFSET_SHFT        0
+#define PRFC_OFFSET_MASK        (UINT64_CAST 3)
+#endif /* 0 */
+
+
+/*
+ * Bits for NACK_CNT_A/B and NACK_CMP
+ */
+#define PI_NACK_CNT_EN_SHFT     20
+#define PI_NACK_CNT_EN_MASK     0x100000
+#define PI_NACK_CNT_MASK        0x0fffff
+#define PI_NACK_CNT_MAX         0x0fffff
+
+#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h
new file mode 100644
index 000000000000..ade0e974dd78
--- /dev/null
+++ b/include/asm-mips/sn/sn0/ip27.h
@@ -0,0 +1,92 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/IP27.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_IP27_H
+#define _ASM_SN_SN0_IP27_H
+
+#include <asm/mipsregs.h>
+
+/*
+ * Simple definitions for the masks which remove SW bits from pte.
+ */
+
+#define TLBLO_HWBITSHIFT        0               /* Shift value, for masking */
+
+#ifndef __ASSEMBLY__
+
+#define CAUSE_BERRINTR          IE_IRQ5
+
+#define ECCF_CACHE_ERR  0
+#define ECCF_TAGLO      1
+#define ECCF_ECC        2
+#define ECCF_ERROREPC   3
+#define ECCF_PADDR      4
+#define ECCF_SIZE       (5 * sizeof(long))
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
+ * the processor number of the calling processor.  The proc parameters
+ * must be a register.
+ */
+#define KL_GET_CPUNUM(proc)                             \
+        dli     proc, LOCAL_HUB(0);                     \
+        ld      proc, PI_CPU_NUM(proc)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * R10000 status register interrupt bit mask usage for IP27.
+ */
+#define SRB_SWTIMO      IE_SW0          /* 0x0100 */
+#define SRB_NET         IE_SW1          /* 0x0200 */
+#define SRB_DEV0        IE_IRQ0         /* 0x0400 */
+#define SRB_DEV1        IE_IRQ1         /* 0x0800 */
+#define SRB_TIMOCLK     IE_IRQ2         /* 0x1000 */
+#define SRB_PROFCLK     IE_IRQ3         /* 0x2000 */
+#define SRB_ERR         IE_IRQ4         /* 0x4000 */
+#define SRB_SCHEDCLK    IE_IRQ5         /* 0x8000 */
+
+#define SR_IBIT_HI      SRB_DEV0
+#define SR_IBIT_PROF    SRB_PROFCLK
+
+#define SRB_SWTIMO_IDX          0
+#define SRB_NET_IDX             1
+#define SRB_DEV0_IDX            2
+#define SRB_DEV1_IDX            3
+#define SRB_TIMOCLK_IDX         4
+#define SRB_PROFCLK_IDX         5
+#define SRB_ERR_IDX             6
+#define SRB_SCHEDCLK_IDX        7
+
+#define NUM_CAUSE_INTRS         8
+
+#define SCACHE_LINESIZE 128
+#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
+
+#include <asm/sn/addrs.h>
+
+#define LED_CYCLE_MASK  0x0f
+#define LED_CYCLE_SHFT  4
+
+#define SEND_NMI(_nasid, _slice)        \
+          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+
+/* Sanity hazzard ...  Below all the Origin hacks are following.  */
+
+#define SN00_BRIDGE             0x9200000008000000
+#define SN00I_BRIDGE0           0x920000000b000000
+#define SN00I_BRIDGE1           0x920000000e000000
+#define SN00I_BRIDGE2           0x920000000f000000
+
+#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/include/asm-mips/sn/sn0/sn0_fru.h b/include/asm-mips/sn/sn0/sn0_fru.h
new file mode 100644
index 000000000000..82c6377c275a
--- /dev/null
+++ b/include/asm-mips/sn/sn0/sn0_fru.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_SN0_FRU_H
+#define _ASM_SN_SN0_SN0_FRU_H
+
+#define MAX_DIMMS                       8        /* max # of dimm banks */
+#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+        confidence_t km_confidence; /* confidence level that the memory is bad
+                                     * is this necessary ?
+                                     */
+        confidence_t km_dimm[MAX_DIMMS];
+                                    /* confidence level that dimm[i] is bad
+                                     *I think this is the right number
+                                     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+typedef struct kf_pci_bus_s {
+        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
+        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
+                                        /* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+#endif /* _ASM_SN_SN0_SN0_FRU_H */
diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h
new file mode 100644
index 000000000000..1a2c3025bf28
--- /dev/null
+++ b/include/asm-mips/sn/sn_private.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_SN_SN_PRIVATE_H
+#define __ASM_SN_SN_PRIVATE_H
+
+#include <asm/sn/types.h>
+
+extern nasid_t master_nasid;
+
+extern void cpu_node_probe(void);
+extern cnodeid_t get_compact_nodeid(void);
+extern void hub_rtc_init(cnodeid_t);
+extern void cpu_time_init(void);
+extern void per_cpu_init(void);
+extern void install_cpu_nmi_handler(int slice);
+extern void install_ipi(void);
+extern void setup_replication_mask(void);
+extern void replicate_kernel_text(void);
+extern pfn_t node_getfirstfree(cnodeid_t);
+
+#endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/include/asm-mips/sn/types.h b/include/asm-mips/sn/types.h
new file mode 100644
index 000000000000..74d0bb260b86
--- /dev/null
+++ b/include/asm-mips/sn/types.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_TYPES_H
+#define _ASM_SN_TYPES_H
+
+#include <linux/types.h>
+
+typedef unsigned long   cpuid_t;
+typedef unsigned long   cnodemask_t;
+typedef signed short    nasid_t;        /* node id in numa-as-id space */
+typedef signed short    cnodeid_t;      /* node id in compact-id space */
+typedef signed char     partid_t;       /* partition ID type */
+typedef signed short    moduleid_t;     /* user-visible module number type */
+typedef signed short    cmoduleid_t;    /* kernel compact module id type */
+typedef unsigned char   clusterid_t;    /* Clusterid of the cell */
+typedef unsigned long   pfn_t;
+
+typedef dev_t           vertex_hdl_t;   /* hardware graph vertex handle */
+
+#endif /* _ASM_SN_TYPES_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
new file mode 100644
index 000000000000..b3bc698dfdee
--- /dev/null
+++ b/include/asm-mips/sni.h
@@ -0,0 +1,107 @@
+/*
+ * SNI specific definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998 by Ralf Baechle
+ */
+#ifndef __ASM_SNI_H
+#define __ASM_SNI_H
+
+#define SNI_PORT_BASE           0xb4000000
+
+/*
+ * ASIC PCI registers for little endian configuration.
+ */
+#ifndef __MIPSEL__
+#error "Fix me for big endian"
+#endif
+#define PCIMT_UCONF             0xbfff0000
+#define PCIMT_IOADTIMEOUT2      0xbfff0008
+#define PCIMT_IOMEMCONF         0xbfff0010
+#define PCIMT_IOMMU             0xbfff0018
+#define PCIMT_IOADTIMEOUT1      0xbfff0020
+#define PCIMT_DMAACCESS         0xbfff0028
+#define PCIMT_DMAHIT            0xbfff0030
+#define PCIMT_ERRSTATUS         0xbfff0038
+#define PCIMT_ERRADDR           0xbfff0040
+#define PCIMT_SYNDROME          0xbfff0048
+#define PCIMT_ITPEND            0xbfff0050
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            0xbfff0058
+#define PCIMT_TESTMEM           0xbfff0060
+#define PCIMT_ECCREG            0xbfff0068
+#define PCIMT_CONFIG_ADDRESS    0xbfff0070
+#define PCIMT_ASIC_ID           0xbfff0078      /* read */
+#define PCIMT_SOFT_RESET        0xbfff0078      /* write */
+#define PCIMT_PIA_OE            0xbfff0080
+#define PCIMT_PIA_DATAOUT       0xbfff0088
+#define PCIMT_PIA_DATAIN        0xbfff0090
+#define PCIMT_CACHECONF         0xbfff0098
+#define PCIMT_INVSPACE          0xbfff00a0
+#define PCIMT_PCI_CONF          0xbfff0100
+
+/*
+ * Data port for the PCI bus.
+ */
+#define PCIMT_CONFIG_DATA       0xb4000cfc
+
+/*
+ * Board specific registers
+ */
+#define PCIMT_CSMSR             0xbfd00000
+#define PCIMT_CSSWITCH          0xbfd10000
+#define PCIMT_CSITPEND          0xbfd20000
+#define PCIMT_AUTO_PO_EN        0xbfd30000
+#define PCIMT_CLR_TEMP          0xbfd40000
+#define PCIMT_AUTO_PO_DIS       0xbfd50000
+#define PCIMT_EXMSR             0xbfd60000
+#define PCIMT_UNUSED1           0xbfd70000
+#define PCIMT_CSWCSM            0xbfd80000
+#define PCIMT_UNUSED2           0xbfd90000
+#define PCIMT_CSLED             0xbfda0000
+#define PCIMT_CSMAPISA          0xbfdb0000
+#define PCIMT_CSRSTBP           0xbfdc0000
+#define PCIMT_CLRPOFF           0xbfdd0000
+#define PCIMT_CSTIMER           0xbfde0000
+#define PCIMT_PWDN              0xbfdf0000
+
+/*
+ * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
+ * to the other interrupts generated by ASIC PCI.
+ *
+ * INT2 is a wired-or of the push button interrupt, high temperature interrupt
+ * ASIC PCI interrupt.
+ */
+#define PCIMT_KEYBOARD_IRQ       1
+#define PCIMT_IRQ_INT2          16
+#define PCIMT_IRQ_INTD          17
+#define PCIMT_IRQ_INTC          18
+#define PCIMT_IRQ_INTB          19
+#define PCIMT_IRQ_INTA          20
+#define PCIMT_IRQ_EISA          21
+#define PCIMT_IRQ_SCSI          22
+#define PCIMT_IRQ_ETHERNET      23
+#define PCIMT_IRQ_TEMPERATURE   24
+#define PCIMT_IRQ_EISA_NMI      25
+#define PCIMT_IRQ_POWER_OFF     26
+#define PCIMT_IRQ_BUTTON        27
+
+/*
+ * Base address for the mapped 16mb EISA bus segment.
+ */
+#define PCIMT_EISA_BASE         0xb0000000
+
+/* PCI EISA Interrupt acknowledge  */
+#define PCIMT_INT_ACKNOWLEDGE   0xba000000
+
+#endif /* __ASM_SNI_H */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
new file mode 100644
index 000000000000..020b4db70ee5
--- /dev/null
+++ b/include/asm-mips/socket.h
@@ -0,0 +1,102 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/*
+ * For setsockopt(2)
+ *
+ * This defines are ABI conformant as far as Linux supports these ...
+ */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001  /* Record debugging information.  */
+#define SO_REUSEADDR    0x0004  /* Allow reuse of local addresses.  */
+#define SO_KEEPALIVE    0x0008  /* Keep connections alive and send
+                                   SIGPIPE when they die.  */
+#define SO_DONTROUTE    0x0010  /* Don't do local routing.  */
+#define SO_BROADCAST    0x0020  /* Allow transmission of
+                                   broadcast messages.  */
+#define SO_LINGER       0x0080  /* Block on close of a reliable
+                                   socket to transmit pending data.  */
+#define SO_OOBINLINE 0x0100     /* Receive out-of-band data in-band.  */
+#if 0
+To add: #define SO_REUSEPORT 0x0200     /* Allow local address and port reuse.  */
+#endif
+
+#define SO_TYPE         0x1008  /* Compatible name for SO_STYLE.  */
+#define SO_STYLE        SO_TYPE /* Synonym */
+#define SO_ERROR        0x1007  /* get error status and clear */
+#define SO_SNDBUF       0x1001  /* Send buffer size. */
+#define SO_RCVBUF       0x1002  /* Receive buffer. */
+#define SO_SNDLOWAT     0x1003  /* send low-water mark */
+#define SO_RCVLOWAT     0x1004  /* receive low-water mark */
+#define SO_SNDTIMEO     0x1005  /* send timeout */
+#define SO_RCVTIMEO     0x1006  /* receive timeout */
+#define SO_ACCEPTCONN   0x1009
+
+/* linux-specific, might as well be the same as on i386 */
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_BSDCOMPAT    14
+
+#define SO_PASSCRED     17
+#define SO_PEERCRED     18
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE         25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_PEERSEC              30
+
+#ifdef __KERNEL__
+
+/** sock_type - Socket types
+ *
+ * Please notice that for binary compat reasons MIPS has to
+ * override the enum sock_type in include/linux/net.h, so
+ * we define ARCH_HAS_SOCKET_TYPES here.
+ *
+ * @SOCK_DGRAM - datagram (conn.less) socket
+ * @SOCK_STREAM - stream (connection) socket
+ * @SOCK_RAW - raw socket
+ * @SOCK_RDM - reliably-delivered message
+ * @SOCK_SEQPACKET - sequential packet socket 
+ * @SOCK_PACKET - linux specific way of getting packets at the dev level.
+ *                For writing rarp and other similar things on the user level.
+ */
+enum sock_type {
+        SOCK_DGRAM      = 1,
+        SOCK_STREAM     = 2,
+        SOCK_RAW        = 3,
+        SOCK_RDM        = 4,
+        SOCK_SEQPACKET  = 5,
+        SOCK_PACKET     = 10,
+};
+
+#define SOCK_MAX (SOCK_PACKET + 1)
+
+#define ARCH_HAS_SOCKET_TYPES 1
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-mips/sockios.h b/include/asm-mips/sockios.h
new file mode 100644
index 000000000000..87a50bf039ed
--- /dev/null
+++ b/include/asm-mips/sockios.h
@@ -0,0 +1,25 @@
+/*
+ * Socket-level I/O control calls.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SOCKIOS_H
+#define _ASM_SOCKIOS_H
+
+#include <asm/ioctl.h>
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      0x8906                  /* Get stamp - linux-specific */
+
+#endif /* _ASM_SOCKIOS_H */
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
new file mode 100644
index 000000000000..114d3eb98a6a
--- /dev/null
+++ b/include/asm-mips/spinlock.h
@@ -0,0 +1,299 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SPINLOCK_H
+#define _ASM_SPINLOCK_H
+
+#include <linux/config.h>
+#include <asm/war.h>
+
+/*
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ */
+
+typedef struct {
+        volatile unsigned int lock;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} spinlock_t;
+
+#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
+
+#define spin_lock_init(x)       do { (x)->lock = 0; } while(0)
+
+#define spin_is_locked(x)       ((x)->lock != 0)
+#define spin_unlock_wait(x)     do { barrier(); } while ((x)->lock)
+#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
+
+/*
+ * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions.  They have a cost.
+ */
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_spin_lock        \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 1b                                  \n"
+                "        li     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       sync                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (lock->lock), "=&r" (tmp)
+                : "m" (lock->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_spin_lock        \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 1b                                  \n"
+                "        li     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        sync                                           \n"
+                "       .set    reorder                                 \n"
+                : "=m" (lock->lock), "=&r" (tmp)
+                : "m" (lock->lock)
+                : "memory");
+        }
+}
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+        __asm__ __volatile__(
+        "       .set    noreorder       # _raw_spin_unlock      \n"
+        "       sync                                            \n"
+        "       sw      $0, %0                                  \n"
+        "       .set\treorder                                   \n"
+        : "=m" (lock->lock)
+        : "m" (lock->lock)
+        : "memory");
+}
+
+static inline unsigned int _raw_spin_trylock(spinlock_t *lock)
+{
+        unsigned int temp, res;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_spin_trylock     \n"
+                "1:     ll      %0, %3                                  \n"
+                "       ori     %2, %0, 1                               \n"
+                "       sc      %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                "        nop                                            \n"
+                "       andi    %2, %0, 1                               \n"
+                "       sync                                            \n"
+                "       .set    reorder"
+                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
+                : "m" (lock->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_spin_trylock     \n"
+                "1:     ll      %0, %3                                  \n"
+                "       ori     %2, %0, 1                               \n"
+                "       sc      %2, %1                                  \n"
+                "       beqz    %2, 1b                                  \n"
+                "        andi   %2, %0, 1                               \n"
+                "       sync                                            \n"
+                "       .set    reorder"
+                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
+                : "m" (lock->lock)
+                : "memory");
+        }
+
+        return res == 0;
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts but no interrupt
+ * writers. For those circumstances we can "mix" irq-safe locks - any writer
+ * needs to get a irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+typedef struct {
+        volatile unsigned int lock;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
+
+#define rwlock_init(x)  do { *(x) = RW_LOCK_UNLOCKED; } while(0)
+
+static inline void _raw_read_lock(rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_read_lock        \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bltz    %1, 1b                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       sync                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_read_lock        \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bltz    %1, 1b                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        sync                                           \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+}
+
+/* Note the use of sub, not subu which will make the kernel die with an
+   overflow exception if we ever try to unlock an rwlock that is already
+   unlocked or is being held by a writer.  */
+static inline void _raw_read_unlock(rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # _raw_read_unlock      \n"
+                "       sub     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "       sync                                            \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_read_unlock      \n"
+                "1:     ll      %1, %2                                  \n"
+                "       sub     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        sync                                           \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+}
+
+static inline void _raw_write_lock(rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_write_lock       \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 1b                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       sync                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_write_lock       \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 1b                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       sync                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+}
+
+static inline void _raw_write_unlock(rwlock_t *rw)
+{
+        __asm__ __volatile__(
+        "       sync                    # _raw_write_unlock     \n"
+        "       sw      $0, %0                                  \n"
+        : "=m" (rw->lock)
+        : "m" (rw->lock)
+        : "memory");
+}
+
+#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
+
+static inline int _raw_write_trylock(rwlock_t *rw)
+{
+        unsigned int tmp;
+        int ret;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_write_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       sync                                            \n"
+                "       li      %2, 1                                   \n"
+                "       .set    reorder                                 \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # _raw_write_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "       lui     %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        sync                                           \n"
+                "       li      %2, 1                                   \n"
+                "       .set    reorder                                 \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        }
+
+        return ret;
+}
+
+#endif /* _ASM_SPINLOCK_H */
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
new file mode 100644
index 000000000000..86283c25fd5b
--- /dev/null
+++ b/include/asm-mips/stackframe.h
@@ -0,0 +1,346 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_STACKFRAME_H
+#define _ASM_STACKFRAME_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/offset.h>
+
+                .macro  SAVE_AT
+                .set    push
+                .set    noat
+                LONG_S  $1, PT_R1(sp)
+                .set    pop
+                .endm
+
+                .macro  SAVE_TEMP
+                mfhi    v1
+#ifdef CONFIG_MIPS32
+                LONG_S  $8, PT_R8(sp)
+                LONG_S  $9, PT_R9(sp)
+#endif
+                LONG_S  v1, PT_HI(sp)
+                mflo    v1
+                LONG_S  $10, PT_R10(sp)
+                LONG_S  $11, PT_R11(sp)
+                LONG_S  v1,  PT_LO(sp)
+                LONG_S  $12, PT_R12(sp)
+                LONG_S  $13, PT_R13(sp)
+                LONG_S  $14, PT_R14(sp)
+                LONG_S  $15, PT_R15(sp)
+                LONG_S  $24, PT_R24(sp)
+                .endm
+
+                .macro  SAVE_STATIC
+                LONG_S  $16, PT_R16(sp)
+                LONG_S  $17, PT_R17(sp)
+                LONG_S  $18, PT_R18(sp)
+                LONG_S  $19, PT_R19(sp)
+                LONG_S  $20, PT_R20(sp)
+                LONG_S  $21, PT_R21(sp)
+                LONG_S  $22, PT_R22(sp)
+                LONG_S  $23, PT_R23(sp)
+                LONG_S  $30, PT_R30(sp)
+                .endm
+
+#ifdef CONFIG_SMP
+                .macro  get_saved_sp    /* SMP variation */
+#ifdef CONFIG_MIPS32
+                mfc0    k0, CP0_CONTEXT
+                lui     k1, %hi(kernelsp)
+                srl     k0, k0, 23
+                sll     k0, k0, 2
+                addu    k1, k0
+                LONG_L  k1, %lo(kernelsp)(k1)
+#endif
+#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+                MFC0    k1, CP0_CONTEXT
+                dsra    k1, 23
+                lui     k0, %hi(pgd_current)
+                addiu   k0, %lo(pgd_current)
+                dsubu   k1, k0
+                lui     k0, %hi(kernelsp)
+                daddu   k1, k0
+                LONG_L  k1, %lo(kernelsp)(k1)
+#endif
+#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+                MFC0    k1, CP0_CONTEXT
+                dsrl    k1, 23
+                dsll    k1, k1, 3
+                LONG_L  k1, kernelsp(k1)
+#endif
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+#ifdef CONFIG_MIPS32
+                mfc0    \temp, CP0_CONTEXT
+                srl     \temp, 23
+                sll     \temp, 2
+                LONG_S  \stackp, kernelsp(\temp)
+#endif
+#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+                lw      \temp, TI_CPU(gp)
+                dsll    \temp, 3
+                lui     \temp2, %hi(kernelsp)
+                daddu   \temp, \temp2
+                LONG_S  \stackp, %lo(kernelsp)(\temp)
+#endif
+#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+                lw      \temp, TI_CPU(gp)
+                dsll    \temp, 3
+                LONG_S  \stackp, kernelsp(\temp)
+#endif
+                .endm
+#else
+                .macro  get_saved_sp    /* Uniprocessor variation */
+                lui     k1, %hi(kernelsp)
+                LONG_L  k1, %lo(kernelsp)(k1)
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+                LONG_S  \stackp, kernelsp
+                .endm
+#endif
+
+                .macro  SAVE_SOME
+                .set    push
+                .set    noat
+                .set    reorder
+                mfc0    k0, CP0_STATUS
+                sll     k0, 3           /* extract cu0 bit */
+                .set    noreorder
+                bltz    k0, 8f
+                 move   k1, sp
+                .set    reorder
+                /* Called from user mode, new stack. */
+                get_saved_sp
+8:              move    k0, sp
+                PTR_SUBU sp, k1, PT_SIZE
+                LONG_S  k0, PT_R29(sp)
+                LONG_S  $3, PT_R3(sp)
+                LONG_S  $0, PT_R0(sp)
+                mfc0    v1, CP0_STATUS
+                LONG_S  $2, PT_R2(sp)
+                LONG_S  v1, PT_STATUS(sp)
+                LONG_S  $4, PT_R4(sp)
+                mfc0    v1, CP0_CAUSE
+                LONG_S  $5, PT_R5(sp)
+                LONG_S  v1, PT_CAUSE(sp)
+                LONG_S  $6, PT_R6(sp)
+                MFC0    v1, CP0_EPC
+                LONG_S  $7, PT_R7(sp)
+#ifdef CONFIG_MIPS64
+                LONG_S  $8, PT_R8(sp)
+                LONG_S  $9, PT_R9(sp)
+#endif
+                LONG_S  v1, PT_EPC(sp)
+                LONG_S  $25, PT_R25(sp)
+                LONG_S  $28, PT_R28(sp)
+                LONG_S  $31, PT_R31(sp)
+                ori     $28, sp, _THREAD_MASK
+                xori    $28, _THREAD_MASK
+                .set    pop
+                .endm
+
+                .macro  SAVE_ALL
+                SAVE_SOME
+                SAVE_AT
+                SAVE_TEMP
+                SAVE_STATIC
+                .endm
+
+                .macro  RESTORE_AT
+                .set    push
+                .set    noat
+                LONG_L  $1,  PT_R1(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_TEMP
+                LONG_L  $24, PT_LO(sp)
+#ifdef CONFIG_MIPS32
+                LONG_L  $8, PT_R8(sp)
+                LONG_L  $9, PT_R9(sp)
+#endif
+                mtlo    $24
+                LONG_L  $24, PT_HI(sp)
+                LONG_L  $10, PT_R10(sp)
+                LONG_L  $11, PT_R11(sp)
+                mthi    $24
+                LONG_L  $12, PT_R12(sp)
+                LONG_L  $13, PT_R13(sp)
+                LONG_L  $14, PT_R14(sp)
+                LONG_L  $15, PT_R15(sp)
+                LONG_L  $24, PT_R24(sp)
+                .endm
+
+                .macro  RESTORE_STATIC
+                LONG_L  $16, PT_R16(sp)
+                LONG_L  $17, PT_R17(sp)
+                LONG_L  $18, PT_R18(sp)
+                LONG_L  $19, PT_R19(sp)
+                LONG_L  $20, PT_R20(sp)
+                LONG_L  $21, PT_R21(sp)
+                LONG_L  $22, PT_R22(sp)
+                LONG_L  $23, PT_R23(sp)
+                LONG_L  $30, PT_R30(sp)
+                .endm
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+                .macro  RESTORE_SOME
+                .set    push
+                .set    reorder
+                .set    noat
+                mfc0    a0, CP0_STATUS
+                ori     a0, 0x1f
+                xori    a0, 0x1f
+                mtc0    a0, CP0_STATUS
+                li      v1, 0xff00
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+                LONG_L  $31, PT_R31(sp)
+                LONG_L  $28, PT_R28(sp)
+                LONG_L  $25, PT_R25(sp)
+#ifdef CONFIG_MIPS64
+                LONG_L  $8, PT_R8(sp)
+                LONG_L  $9, PT_R9(sp)
+#endif
+                LONG_L  $7,  PT_R7(sp)
+                LONG_L  $6,  PT_R6(sp)
+                LONG_L  $5,  PT_R5(sp)
+                LONG_L  $4,  PT_R4(sp)
+                LONG_L  $3,  PT_R3(sp)
+                LONG_L  $2,  PT_R2(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET
+                .set    push
+                .set    noreorder
+                LONG_L  k0, PT_EPC(sp)
+                LONG_L  sp, PT_R29(sp)
+                jr      k0
+                 rfe
+                .set    pop
+                .endm
+
+#else
+
+                .macro  RESTORE_SOME
+                .set    push
+                .set    reorder
+                .set    noat
+                mfc0    a0, CP0_STATUS
+                ori     a0, 0x1f
+                xori    a0, 0x1f
+                mtc0    a0, CP0_STATUS
+                li      v1, 0xff00
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+                LONG_L  v1, PT_EPC(sp)
+                MTC0    v1, CP0_EPC
+                LONG_L  $31, PT_R31(sp)
+                LONG_L  $28, PT_R28(sp)
+                LONG_L  $25, PT_R25(sp)
+#ifdef CONFIG_MIPS64
+                LONG_L  $8, PT_R8(sp)
+                LONG_L  $9, PT_R9(sp)
+#endif
+                LONG_L  $7,  PT_R7(sp)
+                LONG_L  $6,  PT_R6(sp)
+                LONG_L  $5,  PT_R5(sp)
+                LONG_L  $4,  PT_R4(sp)
+                LONG_L  $3,  PT_R3(sp)
+                LONG_L  $2,  PT_R2(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET
+                LONG_L  sp, PT_R29(sp)
+                .set    mips3
+                eret
+                .set    mips0
+                .endm
+
+#endif
+
+                .macro  RESTORE_SP
+                LONG_L  sp, PT_R29(sp)
+                .endm
+
+                .macro  RESTORE_ALL
+                RESTORE_TEMP
+                RESTORE_STATIC
+                RESTORE_AT
+                RESTORE_SOME
+                RESTORE_SP
+                .endm
+
+                .macro  RESTORE_ALL_AND_RET
+                RESTORE_TEMP
+                RESTORE_STATIC
+                RESTORE_AT
+                RESTORE_SOME
+                RESTORE_SP_AND_RET
+                .endm
+
+/*
+ * Move to kernel mode and disable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  CLI
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | 0x1f
+                or      t0, t1
+                xori    t0, 0x1f
+                mtc0    t0, CP0_STATUS
+                irq_disable_hazard
+                .endm
+
+/*
+ * Move to kernel mode and enable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  STI
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | 0x1f
+                or      t0, t1
+                xori    t0, 0x1e
+                mtc0    t0, CP0_STATUS
+                irq_enable_hazard
+                .endm
+
+/*
+ * Just move to kernel mode and leave interrupts as they are.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  KMODE
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | 0x1e
+                or      t0, t1
+                xori    t0, 0x1e
+                mtc0    t0, CP0_STATUS
+                irq_disable_hazard
+                .endm
+
+#endif /* _ASM_STACKFRAME_H */
diff --git a/include/asm-mips/stat.h b/include/asm-mips/stat.h
new file mode 100644
index 000000000000..6e00f751ab6d
--- /dev/null
+++ b/include/asm-mips/stat.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_STAT_H
+#define _ASM_STAT_H
+
+#include <linux/types.h>
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+struct stat {
+        unsigned        st_dev;
+        long            st_pad1[3];             /* Reserved for network id */
+        ino_t           st_ino;
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned        st_rdev;
+        long            st_pad2[2];
+        off_t           st_size;
+        long            st_pad3;
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        long            st_atime_nsec;
+        time_t          st_mtime;
+        long            st_mtime_nsec;
+        time_t          st_ctime;
+        long            st_ctime_nsec;
+        long            st_blksize;
+        long            st_blocks;
+        long            st_pad4[14];
+};
+
+/*
+ * This matches struct stat64 in glibc2.1, hence the absolutely insane
+ * amounts of padding around dev_t's.  The memory layout is the same as of
+ * struct stat of the 64-bit kernel.
+ */
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_pad0[3];     /* Reserved for st_dev expansion  */
+
+        unsigned long long      st_ino;
+
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+
+        uid_t           st_uid;
+        gid_t           st_gid;
+
+        unsigned long   st_rdev;
+        unsigned long   st_pad1[3];     /* Reserved for st_rdev expansion  */
+
+        long long       st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        unsigned long   st_atime_nsec;  /* Reserved for st_atime expansion  */
+
+        time_t          st_mtime;
+        unsigned long   st_mtime_nsec;  /* Reserved for st_mtime expansion  */
+
+        time_t          st_ctime;
+        unsigned long   st_ctime_nsec;  /* Reserved for st_ctime expansion  */
+
+        unsigned long   st_blksize;
+        unsigned long   st_pad2;
+
+        long long       st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/* The memory layout is the same as of struct stat64 of the 32-bit kernel.  */
+struct stat {
+        unsigned int            st_dev;
+        unsigned int            st_pad0[3]; /* Reserved for st_dev expansion */
+
+        unsigned long           st_ino;
+
+        mode_t                  st_mode;
+        nlink_t                 st_nlink;
+
+        uid_t                   st_uid;
+        gid_t                   st_gid;
+
+        unsigned int            st_rdev;
+        unsigned int            st_pad1[3]; /* Reserved for st_rdev expansion */
+
+        off_t                   st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        unsigned int            st_atime;
+        unsigned int            st_atime_nsec;
+
+        unsigned int            st_mtime;
+        unsigned int            st_mtime_nsec;
+
+        unsigned int            st_ctime;
+        unsigned int            st_ctime_nsec;
+
+        unsigned int            st_blksize;
+        unsigned int            st_pad2;
+
+        unsigned long           st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define STAT_HAVE_NSEC 1
+
+#endif /* _ASM_STAT_H */
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
new file mode 100644
index 000000000000..5076fec65780
--- /dev/null
+++ b/include/asm-mips/statfs.h
@@ -0,0 +1,96 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_STATFS_H
+#define _ASM_STATFS_H
+
+#include <linux/posix_types.h>
+#include <asm/sgidefs.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t        fsid_t;
+
+#endif
+
+struct statfs {
+        long            f_type;
+#define f_fstyp f_type
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_spare[6];
+};
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+/*
+ * Unlike the traditional version the LFAPI version has none of the ABI junk
+ */
+struct statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_spare[6];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+ 
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+struct statfs64 {                       /* Same as struct statfs */
+        long            f_type;
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_spare[6];
+};
+
+struct compat_statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_spare[6];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#endif /* _ASM_STATFS_H */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
new file mode 100644
index 000000000000..b18345504f8a
--- /dev/null
+++ b/include/asm-mips/string.h
@@ -0,0 +1,166 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
+
+#include <linux/config.h>
+
+/*
+ * Most of the inline functions are rather naive implementations so I just
+ * didn't bother updating them for 64-bit ...
+ */
+#ifdef CONFIG_MIPS32
+
+#ifndef IN_STRING_C
+
+#define __HAVE_ARCH_STRCPY
+static __inline__ char *strcpy(char *__dest, __const__ char *__src)
+{
+  char *__xdest = __dest;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "addiu\t%1,1\n\t"
+        "sb\t$1,(%0)\n\t"
+        "bnez\t$1,1b\n\t"
+        "addiu\t%0,1\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__dest), "=r" (__src)
+        : "0" (__dest), "1" (__src)
+        : "memory");
+
+  return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
+{
+  char *__xdest = __dest;
+
+  if (__n == 0)
+    return __xdest;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "subu\t%2,1\n\t"
+        "sb\t$1,(%0)\n\t"
+        "beqz\t$1,2f\n\t"
+        "addiu\t%0,1\n\t"
+        "bnez\t%2,1b\n\t"
+        "addiu\t%1,1\n"
+        "2:\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__dest), "=r" (__src), "=r" (__n)
+        : "0" (__dest), "1" (__src), "2" (__n)
+        : "memory");
+
+  return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
+{
+  int __res;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n\t"
+        "lbu\t%2,(%0)\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "addiu\t%0,1\n\t"
+        "bne\t$1,%2,2f\n\t"
+        "addiu\t%1,1\n\t"
+        "bnez\t%2,1b\n\t"
+        "lbu\t%2,(%0)\n\t"
+#if defined(CONFIG_CPU_R3000)
+        "nop\n\t"
+#endif
+        "move\t%2,$1\n"
+        "2:\tsubu\t%2,$1\n"
+        "3:\t.set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__cs), "=r" (__ct), "=r" (__res)
+        : "0" (__cs), "1" (__ct));
+
+  return __res;
+}
+
+#endif /* !defined(IN_STRING_C) */
+
+#define __HAVE_ARCH_STRNCMP
+static __inline__ int
+strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
+{
+        int __res;
+
+        __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t%3,(%0)\n\t"
+        "beqz\t%2,2f\n\t"
+        "lbu\t$1,(%1)\n\t"
+        "subu\t%2,1\n\t"
+        "bne\t$1,%3,3f\n\t"
+        "addiu\t%0,1\n\t"
+        "bnez\t%3,1b\n\t"
+        "addiu\t%1,1\n"
+        "2:\n\t"
+#if defined(CONFIG_CPU_R3000)
+        "nop\n\t"
+#endif
+        "move\t%3,$1\n"
+        "3:\tsubu\t%3,$1\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
+        : "0" (__cs), "1" (__ct), "2" (__count));
+
+        return __res;
+}
+#endif /* CONFIG_MIPS32 */
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#ifdef CONFIG_MIPS32
+#define __HAVE_ARCH_MEMSCAN
+static __inline__ void *memscan(void *__addr, int __c, size_t __size)
+{
+        char *__end = (char *)__addr + __size;
+        unsigned char __uc = (unsigned char) __c;
+
+        __asm__(".set\tpush\n\t"
+                ".set\tnoat\n\t"
+                ".set\treorder\n\t"
+                "1:\tbeq\t%0,%1,2f\n\t"
+                "addiu\t%0,1\n\t"
+                "lbu\t$1,-1(%0)\n\t"
+                "bne\t$1,%z4,1b\n"
+                "2:\t.set\tpop"
+                : "=r" (__addr), "=r" (__end)
+                : "0" (__addr), "1" (__end), "Jr" (__uc));
+
+        return __addr;
+}
+#endif /* CONFIG_MIPS32 */
+
+#endif /* _ASM_STRING_H */
diff --git a/include/asm-mips/suspend.h b/include/asm-mips/suspend.h
new file mode 100644
index 000000000000..2562f8f9be0e
--- /dev/null
+++ b/include/asm-mips/suspend.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SUSPEND_H
+#define __ASM_SUSPEND_H
+
+/* Somewhen...  Maybe :-)  */
+
+#endif /* __ASM_SUSPEND_H */
diff --git a/include/asm-mips/sysmips.h b/include/asm-mips/sysmips.h
new file mode 100644
index 000000000000..4f47b7d6a5f7
--- /dev/null
+++ b/include/asm-mips/sysmips.h
@@ -0,0 +1,25 @@
+/*
+ * Definitions for the MIPS sysmips(2) call
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SYSMIPS_H
+#define _ASM_SYSMIPS_H
+
+/*
+ * Commands for the sysmips(2) call
+ *
+ * sysmips(2) is deprecated - though some existing software uses it.
+ * We only support the following commands.
+ */
+#define SETNAME                    1    /* set hostname                  */
+#define FLUSH_CACHE                3    /* writeback and invalidate caches */
+#define MIPS_FIXADE                7    /* control address error fixing  */
+#define MIPS_RDNVRAM              10    /* read NVRAM */
+#define MIPS_ATOMIC_SET         2001    /* atomically set variable       */
+
+#endif /* _ASM_SYSMIPS_H */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
new file mode 100644
index 000000000000..888fd8908467
--- /dev/null
+++ b/include/asm-mips/system.h
@@ -0,0 +1,438 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/cpu-features.h>
+#include <asm/ptrace.h>
+#include <asm/war.h>
+#include <asm/interrupt.h>
+
+/*
+ * read_barrier_depends - Flush all pending reads that subsequents reads
+ * depend on.
+ *
+ * No data-dependent reads from memory-like regions are ever reordered
+ * over this barrier.  All reads preceding this primitive are guaranteed
+ * to access memory (but not necessarily other CPUs' caches) before any
+ * reads following this primitive that depend on the data return by
+ * any of the preceding reads.  This primitive is much lighter weight than
+ * rmb() on most CPUs, and is never heavier weight than is
+ * rmb().
+ *
+ * These ordering constraints are respected by both the local CPU
+ * and the compiler.
+ *
+ * Ordering is not guaranteed by anything other than these primitives,
+ * not even by data dependencies.  See the documentation for
+ * memory_barrier() for examples and URLs to more information.
+ *
+ * For example, the following code would force ordering (the initial
+ * value of "a" is zero, "b" is one, and "p" is "&a"):
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      b = 2;
+ *      memory_barrier();
+ *      p = &b;                         q = p;
+ *                                      read_barrier_depends();
+ *                                      d = *q;
+ * </programlisting>
+ *
+ * because the read of "*q" depends on the read of "p" and these
+ * two reads are separated by a read_barrier_depends().  However,
+ * the following code, with the same initial values for "a" and "b":
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      a = 2;
+ *      memory_barrier();
+ *      b = 3;                          y = b;
+ *                                      read_barrier_depends();
+ *                                      x = a;
+ * </programlisting>
+ *
+ * does not enforce ordering, since there is no data dependency between
+ * the read of "a" and the read of "b".  Therefore, on some CPUs, such
+ * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
+ * in cases like thiswhere there are no data dependencies.
+ */
+
+#define read_barrier_depends()  do { } while(0)
+
+#ifdef CONFIG_CPU_HAS_SYNC
+#define __sync()                                \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                ".set   mips2\n\t"              \
+                "sync\n\t"                      \
+                ".set   pop"                    \
+                : /* no output */               \
+                : /* no input */                \
+                : "memory")
+#else
+#define __sync()        do { } while(0)
+#endif
+
+#define __fast_iob()                            \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "nop\n\t"                       \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1)          \
+                : "memory")
+
+#define fast_wmb()      __sync()
+#define fast_rmb()      __sync()
+#define fast_mb()       __sync()
+#define fast_iob()                              \
+        do {                                    \
+                __sync();                       \
+                __fast_iob();                   \
+        } while (0)
+
+#ifdef CONFIG_CPU_HAS_WB
+
+#include <asm/wbflush.h>
+
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            wbflush()
+#define iob()           wbflush()
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            fast_mb()
+#define iob()           fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif
+
+#define set_mb(var, value) \
+do { var = value; mb(); } while (0)
+
+#define set_wmb(var, value) \
+do { var = value; wmb(); } while (0)
+
+/*
+ * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+extern asmlinkage void *resume(void *last, void *next, void *next_ti);
+
+struct task_struct;
+
+#define switch_to(prev,next,last) \
+do { \
+        (last) = resume(prev, next, next->thread_info); \
+} while(0)
+
+#define ROT_IN_PIECES                                                   \
+        "       .set    noreorder       \n"                             \
+        "       .set    reorder         \n"
+
+static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
+{
+        __u32 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       move    %2, %z4                                 \n"
+                "       sc      %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                ROT_IN_PIECES
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       move    %2, %z4                                 \n"
+                "       sc      %2, %1                                  \n"
+                "       beqz    %2, 1b                                  \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+
+#ifdef CONFIG_MIPS64
+static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
+{
+        __u64 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %3                  # xchg_u64      \n"
+                "       move    %2, %z4                                 \n"
+                "       scd     %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                ROT_IN_PIECES
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "1:     lld     %0, %3                  # xchg_u64      \n"
+                "       move    %2, %z4                                 \n"
+                "       scd     %2, %1                                  \n"
+                "       beqz    %2, 1b                                  \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+#else
+extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
+#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid xchg().  */
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+                case 4:
+                        return __xchg_u32(ptr, x);
+                case 8:
+                        return __xchg_u64(ptr, x);
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr) (xchg((ptr),1))
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
+        unsigned long new)
+{
+        __u32 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noat                                    \n"
+                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       sc      $1, %1                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                ROT_IN_PIECES
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "2:                                                     \n"
+                "       .set    at                                      \n"
+                : "=&r" (retval), "=m" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    noat                                    \n"
+                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       sc      $1, %1                                  \n"
+                "       beqz    $1, 1b                                  \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "2:                                                     \n"
+                "       .set    at                                      \n"
+                : "=&r" (retval), "=m" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                if (retval == old)
+                        *m = new;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+
+#ifdef CONFIG_MIPS64
+static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
+        unsigned long new)
+{
+        __u64 retval;
+
+        if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    noat                                    \n"
+                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       scd     $1, %1                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                ROT_IN_PIECES
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "2:                                                     \n"
+                "       .set    at                                      \n"
+                : "=&r" (retval), "=m" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    noat                                    \n"
+                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       scd     $1, %1                                  \n"
+                "       beqz    $1, 1b                                  \n"
+#ifdef CONFIG_SMP
+                "       sync                                            \n"
+#endif
+                "2:                                                     \n"
+                "       .set    at                                      \n"
+                : "=&r" (retval), "=m" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                if (retval == old)
+                        *m = new;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+#else
+extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
+        volatile int * m, unsigned long old, unsigned long new);
+#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+        unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+        case 8:
+                return __cmpxchg_u64(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
+
+extern void *set_except_vector(int n, void *addr);
+extern void per_cpu_trap_init(void);
+
+extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
+        const char *func, unsigned long line);
+extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
+        const char *func, unsigned long line);
+
+#define die(msg, regs)                                                  \
+        __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
+#define die_if_kernel(msg, regs)                                        \
+        __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
+
+extern int stop_a_enabled;
+
+/*
+ * Taken from include/asm-ia64/system.h; prevents deadlock on SMP
+ * systems.
+ */
+#define prepare_arch_switch(rq, next)           \
+do {                                            \
+        spin_lock(&(next)->switch_lock);        \
+        spin_unlock(&(rq)->lock);               \
+} while (0)
+#define finish_arch_switch(rq, prev)    spin_unlock_irq(&(prev)->switch_lock)
+#define task_running(rq, p)             ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
+
+#define arch_align_stack(x) (x)
+
+#endif /* _ASM_SYSTEM_H */
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
new file mode 100644
index 000000000000..c29c65b7818e
--- /dev/null
+++ b/include/asm-mips/termbits.h
@@ -0,0 +1,207 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_TERMBITS_H
+#define _ASM_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned long speed_t;
+typedef unsigned long tcflag_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef __u32 speed_t;
+typedef __u32 tcflag_t;
+#endif
+
+/*
+ * The ABI says nothing about NCC but seems to use NCCS as
+ * replacement for it in struct termio
+ */
+#define NCCS    23
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+/* c_cc characters */
+#define VINTR            0              /* Interrupt character [ISIG].  */
+#define VQUIT            1              /* Quit character [ISIG].  */
+#define VERASE           2              /* Erase character [ICANON].  */
+#define VKILL            3              /* Kill-line character [ICANON].  */
+#define VMIN             4              /* Minimum number of bytes read at once [!ICANON].  */
+#define VTIME            5              /* Time-out value (tenths of a second) [!ICANON].  */
+#define VEOL2            6              /* Second EOL character [ICANON].  */
+#define VSWTC            7              /* ??? */
+#define VSWTCH          VSWTC
+#define VSTART           8              /* Start (X-ON) character [IXON, IXOFF].  */
+#define VSTOP            9              /* Stop (X-OFF) character [IXON, IXOFF].  */
+#define VSUSP           10              /* Suspend character [ISIG].  */
+#if 0
+/*
+ * VDSUSP is not supported
+ */
+#define VDSUSP          11              /* Delayed suspend character [ISIG].  */
+#endif
+#define VREPRINT        12              /* Reprint-line character [ICANON].  */
+#define VDISCARD        13              /* Discard character [IEXTEN].  */
+#define VWERASE         14              /* Word-erase character [ICANON].  */
+#define VLNEXT          15              /* Literal-next character [IEXTEN].  */
+#define VEOF            16              /* End-of-file character [ICANON].  */
+#define VEOL            17              /* End-of-line character [ICANON].  */
+
+/* c_iflag bits */
+#define IGNBRK  0000001         /* Ignore break condition.  */
+#define BRKINT  0000002         /* Signal interrupt on break.  */
+#define IGNPAR  0000004         /* Ignore characters with parity errors.  */
+#define PARMRK  0000010         /* Mark parity and framing errors.  */
+#define INPCK   0000020         /* Enable input parity check.  */
+#define ISTRIP  0000040         /* Strip 8th bit off characters.  */
+#define INLCR   0000100         /* Map NL to CR on input.  */
+#define IGNCR   0000200         /* Ignore CR.  */
+#define ICRNL   0000400         /* Map CR to NL on input.  */
+#define IUCLC   0001000         /* Map upper case to lower case on input.  */
+#define IXON    0002000         /* Enable start/stop output control.  */
+#define IXANY   0004000         /* Any character will restart after stop.  */
+#define IXOFF   0010000         /* Enable start/stop input control.  */
+#define IMAXBEL 0020000         /* Ring bell when input queue is full.  */
+#define IUTF8   0040000         /* Input is UTF8 */
+
+/* c_oflag bits */
+#define OPOST   0000001         /* Perform output processing.  */
+#define OLCUC   0000002         /* Map lower case to upper case on output.  */
+#define ONLCR   0000004         /* Map NL to CR-NL on output.  */
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+/*
+#define PAGEOUT ???
+#define WRAP    ???
+ */
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060         /* Number of bits per byte (mask).  */
+#define   CS5   0000000         /* 5 bits per byte.  */
+#define   CS6   0000020         /* 6 bits per byte.  */
+#define   CS7   0000040         /* 7 bits per byte.  */
+#define   CS8   0000060         /* 8 bits per byte.  */
+#define CSTOPB  0000100         /* Two stop bits instead of one.  */
+#define CREAD   0000200         /* Enable receiver.  */
+#define PARENB  0000400         /* Parity enable.  */
+#define PARODD  0001000         /* Odd parity instead of even.  */
+#define HUPCL   0002000         /* Hang up on last close.  */
+#define CLOCAL  0004000         /* Ignore modem status lines.  */
+#define CBAUDEX 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CMSPAR    010000000000  /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+/* c_lflag bits */
+#define ISIG    0000001         /* Enable signals.  */
+#define ICANON  0000002         /* Do erase and kill processing.  */
+#define XCASE   0000004
+#define ECHO    0000010         /* Enable echo.  */
+#define ECHOE   0000020         /* Visual erase for ERASE.  */
+#define ECHOK   0000040         /* Echo NL after KILL.  */
+#define ECHONL  0000100         /* Echo NL even if ECHO is off.  */
+#define NOFLSH  0000200         /* Disable flush after interrupt.  */
+#define IEXTEN  0000400         /* Enable DISCARD and LNEXT.  */
+#define ECHOCTL 0001000         /* Echo control characters as ^X.  */
+#define ECHOPRT 0002000         /* Hardcopy visual erase.  */
+#define ECHOKE  0004000         /* Visual erase for KILL.  */
+#define FLUSHO  0020000
+#define PENDIN  0040000         /* Retype pending input (state).  */
+#define TOSTOP  0100000         /* Send SIGTTOU for background output.  */
+#define ITOSTOP TOSTOP
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0       /* Suspend output.  */
+#define TCOON           1       /* Restart suspended output.  */
+#define TCIOFF          2       /* Send a STOP character.  */
+#define TCION           3       /* Send a START character.  */
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0       /* Discard data received but not yet read.  */
+#define TCOFLUSH        1       /* Discard data written but not yet sent.  */
+#define TCIOFLUSH       2       /* Discard all pending data.  */
+
+/* tcsetattr uses these */
+#define TCSANOW         TCSETS  /* Change immediately.  */
+#define TCSADRAIN       TCSETSW /* Change when pending output is written.  */
+#define TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
+
+#endif /* _ASM_TERMBITS_H */
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h
new file mode 100644
index 000000000000..4906204d34fe
--- /dev/null
+++ b/include/asm-mips/termios.h
@@ -0,0 +1,148 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TERMIOS_H
+#define _ASM_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        int     sg_flags;       /* SGI special - int, not short */
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;        /* stop process signal */
+        char    t_dsuspc;       /* delayed stop process signal */
+        char    t_rprntc;       /* reprint line */
+        char    t_flushc;       /* flush output (toggles) */
+        char    t_werasc;       /* word erase */
+        char    t_lnextc;       /* literal next character */
+};
+
+/* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
+   compatibility anyway ... */
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC     8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        char c_line;                    /* line discipline */
+        unsigned char c_cc[NCCS];       /* control characters */
+};
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+
+/*
+ *      intr=^C         quit=^\         erase=del       kill=^U
+ *      vmin=\1         vtime=\0        eol2=\0         swtc=\0
+ *      start=^Q        stop=^S         susp=^Z         vdsusp=
+ *      reprint=^R      discard=^U      werase=^W       lnext=^V
+ *      eof=^D          eol=\0
+ */
+#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE        0x001           /* line enable */
+#define TIOCM_DTR       0x002           /* data terminal ready */
+#define TIOCM_RTS       0x004           /* request to send */
+#define TIOCM_ST        0x010           /* secondary transmit */
+#define TIOCM_SR        0x020           /* secondary receive */
+#define TIOCM_CTS       0x040           /* clear to send */
+#define TIOCM_CAR       0x100           /* carrier detect */
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RNG       0x200           /* ring */
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_DSR       0x400           /* data set ready */
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* line disciplines */
+#define N_TTY           0
+#define N_SLIP          1
+#define N_MOUSE         2
+#define N_PPP           3
+#define N_STRIP         4
+#define N_AX25          5
+#define N_X25           6               /* X.25 async */
+#define N_6PACK         7
+#define N_MASC          8       /* Reserved fo Mobitex module <kaz@cafe.net> */
+#define N_R3964         9       /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA          11      /* Linux IrDa - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC          13      /* synchronous HDLC */
+#define N_SYNC_PPP      14      /* synchronous PPP */
+#define N_HCI           15      /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+
+#include <linux/string.h>
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        unsigned short tmp; \
+        get_user(tmp, &(termio)->c_iflag); \
+        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
+        get_user(tmp, &(termio)->c_oflag); \
+        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
+        get_user(tmp, &(termio)->c_cflag); \
+        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
+        get_user(tmp, &(termio)->c_lflag); \
+        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
+        get_user((termios)->c_line, &(termio)->c_line); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line, &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* _ASM_TERMIOS_H */
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
new file mode 100644
index 000000000000..768900305e2f
--- /dev/null
+++ b/include/asm-mips/thread_info.h
@@ -0,0 +1,137 @@
+/* thread_info.h: MIPS low-level thread information
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/processor.h>
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ *   must also be changed
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        __u32                   cpu;            /* current CPU */
+        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+
+        mm_segment_t            addr_limit;     /* thread address space:
+                                                   0-0xBFFFFFFF for user-thead
+                                                   0-0xFFFFFFFF for kernel-thread
+                                                */
+        struct restart_block    restart_block;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* How to get the thread information struct from C.  */
+register struct thread_info *__current_thread_info __asm__("$28");
+#define current_thread_info()  __current_thread_info
+
+/* thread information allocation */
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32)
+#define THREAD_SIZE_ORDER (1)
+#endif
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64)
+#define THREAD_SIZE_ORDER (2)
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define THREAD_SIZE_ORDER (1)
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+
+#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_MASK (THREAD_SIZE - 1UL)
+
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk)                                  \
+({                                                              \
+        struct thread_info *ret;                                \
+                                                                \
+        ret = kmalloc(THREAD_SIZE, GFP_KERNEL);                 \
+        if (ret)                                                \
+                memset(ret, 0, THREAD_SIZE);                    \
+        ret;                                                    \
+})
+#else
+#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#endif
+
+#define free_thread_info(info) kfree(info)
+#define get_thread_info(ti) get_task_struct((ti)->task)
+#define put_thread_info(ti) put_task_struct((ti)->task)
+
+#endif /* !__ASSEMBLY__ */
+
+#define PREEMPT_ACTIVE          0x10000000
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to
+ *   access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_SYSCALL_AUDIT       4       /* syscall auditing active */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              18
+#define TIF_SYSCALL_TRACE       31      /* syscall trace active */
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_WORK_MASK          0x0000ffef      /* work to do on
+                                                   interrupt/exception return */
+#define _TIF_ALLWORK_MASK       0x8000ffff      /* work to do on any return to
+                                                   u-space */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
new file mode 100644
index 000000000000..e22a20665871
--- /dev/null
+++ b/include/asm-mips/time.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2001, 2002, MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (c) 2003  Maciej W. Rozycki
+ *
+ * include/asm-mips/time.h
+ *     header file for the new style time.c file and time services.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Please refer to Documentation/mips/time.README.
+ */
+#ifndef _ASM_TIME_H
+#define _ASM_TIME_H
+
+#include <linux/interrupt.h>
+#include <linux/linkage.h>
+#include <linux/ptrace.h>
+#include <linux/rtc.h>
+
+/*
+ * RTC ops.  By default, they point to no-RTC functions.
+ *      rtc_get_time - mktime(year, mon, day, hour, min, sec) in seconds.
+ *      rtc_set_time - reverse the above translation and set time to RTC.
+ *      rtc_set_mmss - similar to rtc_set_time, but only min and sec need
+ *                      to be set.  Used by RTC sync-up.
+ */
+extern unsigned long (*rtc_get_time)(void);
+extern int (*rtc_set_time)(unsigned long);
+extern int (*rtc_set_mmss)(unsigned long);
+
+/*
+ * Timer interrupt functions.
+ * mips_timer_state is needed for high precision timer calibration.
+ * mips_timer_ack may be NULL if the interrupt is self-recoverable.
+ */
+extern int (*mips_timer_state)(void);
+extern void (*mips_timer_ack)(void);
+
+/*
+ * High precision timer functions.
+ * If mips_hpt_read is NULL, an R4k-compatible timer setup is attempted.
+ */
+extern unsigned int (*mips_hpt_read)(void);
+extern void (*mips_hpt_init)(unsigned int);
+
+/*
+ * to_tm() converts system time back to (year, mon, day, hour, min, sec).
+ * It is intended to help implement rtc_set_time() functions.
+ * Copied from PPC implementation.
+ */
+extern void to_tm(unsigned long tim, struct rtc_time *tm);
+
+/*
+ * do_gettimeoffset(). By default, this func pointer points to
+ * do_null_gettimeoffset(), which leads to the same resolution as HZ.
+ * Higher resolution versions are available, which give ~1us resolution.
+ */
+extern unsigned long (*do_gettimeoffset)(void);
+
+/*
+ * high-level timer interrupt routines.
+ */
+extern irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+
+/*
+ * the corresponding low-level timer interrupt routine.
+ */
+extern asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs);
+
+/*
+ * profiling and process accouting is done separately in local_timer_interrupt
+ */
+extern void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
+
+/*
+ * board specific routines required by time_init().
+ * board_time_init is defaulted to NULL and can remain so.
+ * board_timer_setup must be setup properly in machine setup routine.
+ */
+struct irqaction;
+extern void (*board_time_init)(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+
+/*
+ * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
+ * counter as a timer interrupt source; otherwise it can be set up
+ * automagically with an aid of mips_timer_state.
+ */
+extern unsigned int mips_hpt_frequency;
+
+#endif /* _ASM_TIME_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
new file mode 100644
index 000000000000..98aa737b34aa
--- /dev/null
+++ b/include/asm-mips/timex.h
@@ -0,0 +1,54 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_TIMEX_H
+#define _ASM_TIMEX_H
+
+#include <asm/mipsregs.h>
+
+/*
+ * This is the frequency of the timer used for Linux's timer interrupt.
+ * The value should be defined as accurate as possible or under certain
+ * circumstances Linux timekeeping might become inaccurate or fail.
+ *
+ * For many system the exact clockrate of the timer isn't known but due to
+ * the way this value is used we can get away with a wrong value as long
+ * as this value is:
+ *
+ *  - a multiple of HZ
+ *  - a divisor of the actual rate
+ *
+ * 500000 is a good such cheat value.
+ *
+ * The obscure number 1193182 is the same as used by the original i8254
+ * time in legacy PC hardware; the chip unfortunately also found in a
+ * bunch of MIPS systems.  The last remaining user of the i8254 for the
+ * timer interrupt is the RM200; it's a very standard system so there is
+ * no reason to make this a separate architecture.
+ */
+
+#include <timex.h>
+
+/*
+ * Standard way to access the cycle counter.
+ * Currently only used on SMP for scheduling.
+ *
+ * Only the low 32 bits are available as a continuously counting entity.
+ * But this only means we'll force a reschedule every 8 seconds or so,
+ * which isn't an evil thing.
+ *
+ * We know that all SMP capable CPUs have cycle counters.
+ */
+
+typedef unsigned int cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+        return read_c0_count();
+}
+
+#endif /*  _ASM_TIMEX_H */
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
new file mode 100644
index 000000000000..fd9599e40a0a
--- /dev/null
+++ b/include/asm-mips/titan_dep.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Board specific definititions for the PMC-Sierra Yosemite
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __TITAN_DEP_H__
+#define __TITAN_DEP_H__
+
+#include <asm/addrspace.h>              /* for KSEG1ADDR() */
+#include <asm/byteorder.h>              /* for cpu_to_le32() */
+
+#define TITAN_READ(ofs)                                                 \
+        (*(volatile u32 *)(ocd_base+(ofs)))
+#define TITAN_READ_16(ofs)                                              \
+        (*(volatile u16 *)(ocd_base+(ofs)))
+#define TITAN_READ_8(ofs)                                               \
+        (*(volatile u8 *)(ocd_base+(ofs)))
+
+#define TITAN_WRITE(ofs, data)                                          \
+        do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_16(ofs, data)                                       \
+        do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_8(ofs, data)                                        \
+        do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
+
+/*
+ * PCI specific defines
+ */
+#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
+#define TITAN_PCI_0_CONFIG_DATA         0x784
+
+/*
+ * HT specific defines
+ */
+#define RM9000x2_HTLINK_REG             0xbb000644
+#define RM9000x2_BASE_ADDR              0xbb000000
+
+#define OCD_BASE                        0xfb000000UL
+#define OCD_SIZE                        0x3000UL
+
+extern unsigned long ocd_base;
+
+/*
+ * OCD Registers
+ */
+#define RM9000x2_OCD_LKB5               0x0128          /* Ethernet */
+#define RM9000x2_OCD_LKM5               0x012c
+
+#define RM9000x2_OCD_LKB7               0x0138          /* HT Region 0 */
+#define RM9000x2_OCD_LKM7               0x013c
+#define RM9000x2_OCD_LKB8               0x0140          /* HT Region 1 */
+#define RM9000x2_OCD_LKM8               0x0144
+
+#define RM9000x2_OCD_LKB9               0x0148          /* Local Bus */
+#define RM9000x2_OCD_LKM9               0x014c
+#define RM9000x2_OCD_LKB10              0x0150
+#define RM9000x2_OCD_LKM10              0x0154
+#define RM9000x2_OCD_LKB11              0x0158
+#define RM9000x2_OCD_LKM11              0x015c
+#define RM9000x2_OCD_LKB12              0x0160
+#define RM9000x2_OCD_LKM12              0x0164
+
+#define RM9000x2_OCD_LKB13              0x0168          /* Scratch RAM */
+#define RM9000x2_OCD_LKM13              0x016c
+
+#define RM9000x2_OCD_LPD0               0x0200          /* Local Bus */
+#define RM9000x2_OCD_LPD1               0x0210
+#define RM9000x2_OCD_LPD2               0x0220
+#define RM9000x2_OCD_LPD3               0x0230
+
+#define RM9000x2_OCD_HTDVID             0x0600  /* HT Device Header */
+#define RM9000x2_OCD_HTSC               0x0604
+#define RM9000x2_OCD_HTCCR              0x0608
+#define RM9000x2_OCD_HTBHL              0x060c
+#define RM9000x2_OCD_HTBAR0             0x0610
+#define RM9000x2_OCD_HTBAR1             0x0614
+#define RM9000x2_OCD_HTBAR2             0x0618
+#define RM9000x2_OCD_HTBAR3             0x061c
+#define RM9000x2_OCD_HTBAR4             0x0620
+#define RM9000x2_OCD_HTBAR5             0x0624
+#define RM9000x2_OCD_HTCBCPT            0x0628
+#define RM9000x2_OCD_HTSDVID            0x062c
+#define RM9000x2_OCD_HTXRA              0x0630
+#define RM9000x2_OCD_HTCAP1             0x0634
+#define RM9000x2_OCD_HTIL               0x063c
+
+#define RM9000x2_OCD_HTLCC              0x0640  /* HT Capability Block */
+#define RM9000x2_OCD_HTLINK             0x0644
+#define RM9000x2_OCD_HTFQREV            0x0648
+
+#define RM9000x2_OCD_HTERCTL            0x0668  /* HT Controller */
+#define RM9000x2_OCD_HTRXDB             0x066c
+#define RM9000x2_OCD_HTIMPED            0x0670
+#define RM9000x2_OCD_HTSWIMP            0x0674
+#define RM9000x2_OCD_HTCAL              0x0678
+
+#define RM9000x2_OCD_HTBAA30            0x0680
+#define RM9000x2_OCD_HTBAA54            0x0684
+#define RM9000x2_OCD_HTMASK0            0x0688
+#define RM9000x2_OCD_HTMASK1            0x068c
+#define RM9000x2_OCD_HTMASK2            0x0690
+#define RM9000x2_OCD_HTMASK3            0x0694
+#define RM9000x2_OCD_HTMASK4            0x0698
+#define RM9000x2_OCD_HTMASK5            0x069c
+
+#define RM9000x2_OCD_HTIFCTL            0x06a0
+#define RM9000x2_OCD_HTPLL              0x06a4
+
+#define RM9000x2_OCD_HTSRI              0x06b0
+#define RM9000x2_OCD_HTRXNUM            0x06b4
+#define RM9000x2_OCD_HTTXNUM            0x06b8
+
+#define RM9000x2_OCD_HTTXCNT            0x06c8
+
+#define RM9000x2_OCD_HTERROR            0x06d8
+#define RM9000x2_OCD_HTRCRCE            0x06dc
+#define RM9000x2_OCD_HTEOI              0x06e0
+
+#define RM9000x2_OCD_CRCR               0x06f0
+
+#define RM9000x2_OCD_HTCFGA             0x06f8
+#define RM9000x2_OCD_HTCFGD             0x06fc
+
+#define RM9000x2_OCD_INTMSG             0x0a00
+
+#define RM9000x2_OCD_INTPIN0            0x0a40
+#define RM9000x2_OCD_INTPIN1            0x0a44
+#define RM9000x2_OCD_INTPIN2            0x0a48
+#define RM9000x2_OCD_INTPIN3            0x0a4c
+#define RM9000x2_OCD_INTPIN4            0x0a50
+#define RM9000x2_OCD_INTPIN5            0x0a54
+#define RM9000x2_OCD_INTPIN6            0x0a58
+#define RM9000x2_OCD_INTPIN7            0x0a5c
+#define RM9000x2_OCD_SEM                0x0a60
+#define RM9000x2_OCD_SEMSET             0x0a64
+#define RM9000x2_OCD_SEMCLR             0x0a68
+
+#define RM9000x2_OCD_TKT                0x0a70
+#define RM9000x2_OCD_TKTINC             0x0a74
+
+#define RM9000x2_OCD_NMICONFIG          0x0ac0          /* Interrupts */
+#define RM9000x2_OCD_INTP0PRI           0x1a80
+#define RM9000x2_OCD_INTP1PRI           0x1a80
+#define RM9000x2_OCD_INTP0STATUS0       0x1b00
+#define RM9000x2_OCD_INTP0MASK0         0x1b04
+#define RM9000x2_OCD_INTP0SET0          0x1b08
+#define RM9000x2_OCD_INTP0CLEAR0        0x1b0c
+#define RM9000x2_OCD_INTP0STATUS1       0x1b10
+#define RM9000x2_OCD_INTP0MASK1         0x1b14
+#define RM9000x2_OCD_INTP0SET1          0x1b18
+#define RM9000x2_OCD_INTP0CLEAR1        0x1b1c
+#define RM9000x2_OCD_INTP0STATUS2       0x1b20
+#define RM9000x2_OCD_INTP0MASK2         0x1b24
+#define RM9000x2_OCD_INTP0SET2          0x1b28
+#define RM9000x2_OCD_INTP0CLEAR2        0x1b2c
+#define RM9000x2_OCD_INTP0STATUS3       0x1b30
+#define RM9000x2_OCD_INTP0MASK3         0x1b34
+#define RM9000x2_OCD_INTP0SET3          0x1b38
+#define RM9000x2_OCD_INTP0CLEAR3        0x1b3c
+#define RM9000x2_OCD_INTP0STATUS4       0x1b40
+#define RM9000x2_OCD_INTP0MASK4         0x1b44
+#define RM9000x2_OCD_INTP0SET4          0x1b48
+#define RM9000x2_OCD_INTP0CLEAR4        0x1b4c
+#define RM9000x2_OCD_INTP0STATUS5       0x1b50
+#define RM9000x2_OCD_INTP0MASK5         0x1b54
+#define RM9000x2_OCD_INTP0SET5          0x1b58
+#define RM9000x2_OCD_INTP0CLEAR5        0x1b5c
+#define RM9000x2_OCD_INTP0STATUS6       0x1b60
+#define RM9000x2_OCD_INTP0MASK6         0x1b64
+#define RM9000x2_OCD_INTP0SET6          0x1b68
+#define RM9000x2_OCD_INTP0CLEAR6        0x1b6c
+#define RM9000x2_OCD_INTP0STATUS7       0x1b70
+#define RM9000x2_OCD_INTP0MASK7         0x1b74
+#define RM9000x2_OCD_INTP0SET7          0x1b78
+#define RM9000x2_OCD_INTP0CLEAR7        0x1b7c
+#define RM9000x2_OCD_INTP1STATUS0       0x2b00
+#define RM9000x2_OCD_INTP1MASK0         0x2b04
+#define RM9000x2_OCD_INTP1SET0          0x2b08
+#define RM9000x2_OCD_INTP1CLEAR0        0x2b0c
+#define RM9000x2_OCD_INTP1STATUS1       0x2b10
+#define RM9000x2_OCD_INTP1MASK1         0x2b14
+#define RM9000x2_OCD_INTP1SET1          0x2b18
+#define RM9000x2_OCD_INTP1CLEAR1        0x2b1c
+#define RM9000x2_OCD_INTP1STATUS2       0x2b20
+#define RM9000x2_OCD_INTP1MASK2         0x2b24
+#define RM9000x2_OCD_INTP1SET2          0x2b28
+#define RM9000x2_OCD_INTP1CLEAR2        0x2b2c
+#define RM9000x2_OCD_INTP1STATUS3       0x2b30
+#define RM9000x2_OCD_INTP1MASK3         0x2b34
+#define RM9000x2_OCD_INTP1SET3          0x2b38
+#define RM9000x2_OCD_INTP1CLEAR3        0x2b3c
+#define RM9000x2_OCD_INTP1STATUS4       0x2b40
+#define RM9000x2_OCD_INTP1MASK4         0x2b44
+#define RM9000x2_OCD_INTP1SET4          0x2b48
+#define RM9000x2_OCD_INTP1CLEAR4        0x2b4c
+#define RM9000x2_OCD_INTP1STATUS5       0x2b50
+#define RM9000x2_OCD_INTP1MASK5         0x2b54
+#define RM9000x2_OCD_INTP1SET5          0x2b58
+#define RM9000x2_OCD_INTP1CLEAR5        0x2b5c
+#define RM9000x2_OCD_INTP1STATUS6       0x2b60
+#define RM9000x2_OCD_INTP1MASK6         0x2b64
+#define RM9000x2_OCD_INTP1SET6          0x2b68
+#define RM9000x2_OCD_INTP1CLEAR6        0x2b6c
+#define RM9000x2_OCD_INTP1STATUS7       0x2b70
+#define RM9000x2_OCD_INTP1MASK7         0x2b74
+#define RM9000x2_OCD_INTP1SET7          0x2b78
+#define RM9000x2_OCD_INTP1CLEAR7        0x2b7c
+
+#define OCD_READ(reg)           (*(volatile unsigned int *)(ocd_base + (reg)))
+#define OCD_WRITE(reg, val)                                     \
+        do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
+
+/*
+ * Hypertransport specific macros
+ */
+#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
+
+#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
+
+#endif 
diff --git a/include/asm-mips/tlb.h b/include/asm-mips/tlb.h
new file mode 100644
index 000000000000..80d9dfcf1e88
--- /dev/null
+++ b/include/asm-mips/tlb.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+/*
+ * MIPS doesn't need any special per-pte or per-vma handling, except
+ * we need to flush cache for area to be unmapped.
+ */
+#define tlb_start_vma(tlb, vma)                                 \
+        do {                                                    \
+                if (!tlb->fullmm)                               \
+                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+        }  while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* __ASM_TLB_H */
diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h
new file mode 100644
index 000000000000..fff7a73e22d0
--- /dev/null
+++ b/include/asm-mips/tlbdebug.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 by Ralf Baechle
+ */
+#ifndef __ASM_TLBDEBUG_H
+#define __ASM_TLBDEBUG_H
+
+/*
+ * TLB debugging functions:
+ */
+extern void dump_tlb(int first, int last);
+extern void dump_tlb_all(void);
+extern void dump_tlb_wired(void);
+extern void dump_tlb_addr(unsigned long addr);
+extern void dump_tlb_nonwired(void);
+
+#endif /* __ASM_TLBDEBUG_H */
diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h
new file mode 100644
index 000000000000..bb4ae3cdcbf1
--- /dev/null
+++ b/include/asm-mips/tlbflush.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_TLBFLUSH_H
+#define __ASM_TLBFLUSH_H
+
+#include <linux/config.h>
+#include <linux/mm.h>
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
+ */
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *mm);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void local_flush_tlb_kernel_range(unsigned long start,
+        unsigned long end);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+        unsigned long page);
+extern void local_flush_tlb_one(unsigned long vaddr);
+
+#ifdef CONFIG_SMP
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long,
+        unsigned long);
+extern void flush_tlb_kernel_range(unsigned long, unsigned long);
+extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void flush_tlb_one(unsigned long vaddr);
+
+#else /* CONFIG_SMP */
+
+#define flush_tlb_all()                 local_flush_tlb_all()
+#define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
+#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end)
+#define flush_tlb_kernel_range(vmaddr,end) \
+        local_flush_tlb_kernel_range(vmaddr, end)
+#define flush_tlb_page(vma,page)        local_flush_tlb_page(vma, page)
+#define flush_tlb_one(vaddr)            local_flush_tlb_one(vaddr)
+
+#endif /* CONFIG_SMP */
+
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
+        unsigned long start, unsigned long end)
+{
+        /* Nothing to do on MIPS.  */
+}
+
+#endif /* __ASM_TLBFLUSH_H */
diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h
new file mode 100644
index 000000000000..0440fb9f2180
--- /dev/null
+++ b/include/asm-mips/topology.h
@@ -0,0 +1 @@
+#include <topology.h>
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
new file mode 100644
index 000000000000..179012263007
--- /dev/null
+++ b/include/asm-mips/traps.h
@@ -0,0 +1,24 @@
+/*
+ *      Trap handling definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_TRAPS_H
+#define _ASM_TRAPS_H
+
+/*
+ * Possible status responses for a board_be_handler backend.
+ */
+#define MIPS_BE_DISCARD 0               /* return with no action */
+#define MIPS_BE_FIXUP   1               /* return to the fixup code */
+#define MIPS_BE_FATAL   2               /* treat as an unrecoverable error */
+
+extern void (*board_be_init)(void);
+extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+
+#endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx3912.h b/include/asm-mips/tx3912.h
new file mode 100644
index 000000000000..d709d87363d0
--- /dev/null
+++ b/include/asm-mips/tx3912.h
@@ -0,0 +1,361 @@
+/*
+ *  include/asm-mips/tx3912.h
+ *
+ *  Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Registers for TMPR3912/05 and PR31700 processors
+ */
+#ifndef _TX3912_H_
+#define _TX3912_H_
+
+/*****************************************************************************
+ *      Clock Subsystem                                                      *
+ *      ---------------                                                      *
+ *      Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals    *
+ *****************************************************************************/
+#define TX3912_CLK_CTRL                                 0x01c0
+
+/*
+ * Clock control register values
+ */
+#define TX3912_CLK_CTRL_CHICLKDIV_MASK                  0xff000000
+#define TX3912_CLK_CTRL_ENCLKTEST                       0x00800000
+#define TX3912_CLK_CTRL_CLKTESTSELSIB                   0x00400000
+#define TX3912_CLK_CTRL_CHIMCLKSEL                      0x00200000
+#define TX3912_CLK_CTRL_CHICLKDIR                       0x00100000
+#define TX3912_CLK_CTRL_ENCHIMCLK                       0x00080000
+#define TX3912_CLK_CTRL_ENVIDCLK                        0x00040000
+#define TX3912_CLK_CTRL_ENMBUSCLK                       0x00020000
+#define TX3912_CLK_CTRL_ENSPICLK                        0x00010000
+#define TX3912_CLK_CTRL_ENTIMERCLK                      0x00008000
+#define TX3912_CLK_CTRL_ENFASTTIMERCLK                  0x00004000
+#define TX3912_CLK_CTRL_SIBMCLKDIR                      0x00002000
+#define TX3912_CLK_CTRL_reserved1                       0x00001000
+#define TX3912_CLK_CTRL_ENSIBMCLK                       0x00000800
+#define TX3912_CLK_CTRL_SIBMCLKDIV_6                    0x00000600
+#define TX3912_CLK_CTRL_SIBMCLKDIV_5                    0x00000500
+#define TX3912_CLK_CTRL_SIBMCLKDIV_4                    0x00000400
+#define TX3912_CLK_CTRL_SIBMCLKDIV_3                    0x00000300
+#define TX3912_CLK_CTRL_SIBMCLKDIV_2                    0x00000200
+#define TX3912_CLK_CTRL_SIBMCLKDIV_1                    0x00000100
+#define TX3912_CLK_CTRL_CSERSEL                         0x00000080
+#define TX3912_CLK_CTRL_CSERDIV_6                       0x00000060
+#define TX3912_CLK_CTRL_CSERDIV_5                       0x00000050
+#define TX3912_CLK_CTRL_CSERDIV_4                       0x00000040
+#define TX3912_CLK_CTRL_CSERDIV_3                       0x00000030
+#define TX3912_CLK_CTRL_CSERDIV_2                       0x00000020
+#define TX3912_CLK_CTRL_CSERDIV_1                       0x00000010
+#define TX3912_CLK_CTRL_ENCSERCLK                       0x00000008
+#define TX3912_CLK_CTRL_ENIRCLK                         0x00000004
+#define TX3912_CLK_CTRL_ENUARTACLK                      0x00000002
+#define TX3912_CLK_CTRL_ENUARTBCLK                      0x00000001
+
+
+/*****************************************************************************
+ *      Interrupt Subsystem                                                  *
+ *      -------------------                                                  *
+ *      Chapter 8 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals    *
+ *****************************************************************************/
+#define TX3912_INT1_CLEAR                               0x0100
+#define TX3912_INT2_CLEAR                               0x0104
+#define TX3912_INT3_CLEAR                               0x0108
+#define TX3912_INT4_CLEAR                               0x010c
+#define TX3912_INT5_CLEAR                               0x0110
+#define TX3912_INT1_ENABLE                              0x0118
+#define TX3912_INT2_ENABLE                              0x011c
+#define TX3912_INT3_ENABLE                              0x0120
+#define TX3912_INT4_ENABLE                              0x0124
+#define TX3912_INT5_ENABLE                              0x0128
+#define TX3912_INT6_ENABLE                              0x012c
+#define TX3912_INT1_STATUS                              0x0100
+#define TX3912_INT2_STATUS                              0x0104
+#define TX3912_INT3_STATUS                              0x0108
+#define TX3912_INT4_STATUS                              0x010c
+#define TX3912_INT5_STATUS                              0x0110
+#define TX3912_INT6_STATUS                              0x0114
+
+/*
+ * Interrupt 2 register values
+ */
+#define TX3912_INT2_UARTARXINT                          0x80000000
+#define TX3912_INT2_UARTARXOVERRUNINT                   0x40000000
+#define TX3912_INT2_UARTAFRAMEERRINT                    0x20000000
+#define TX3912_INT2_UARTABREAKINT                       0x10000000
+#define TX3912_INT2_UARTAPARITYINT                      0x08000000
+#define TX3912_INT2_UARTATXINT                          0x04000000
+#define TX3912_INT2_UARTATXOVERRUNINT                   0x02000000
+#define TX3912_INT2_UARTAEMPTYINT                       0x01000000
+#define TX3912_INT2_UARTADMAFULLINT                     0x00800000
+#define TX3912_INT2_UARTADMAHALFINT                     0x00400000
+#define TX3912_INT2_UARTBRXINT                          0x00200000
+#define TX3912_INT2_UARTBRXOVERRUNINT                   0x00100000
+#define TX3912_INT2_UARTBFRAMEERRINT                    0x00080000
+#define TX3912_INT2_UARTBBREAKINT                       0x00040000
+#define TX3912_INT2_UARTBPARITYINT                      0x00020000
+#define TX3912_INT2_UARTBTXINT                          0x00010000
+#define TX3912_INT2_UARTBTXOVERRUNINT                   0x00008000
+#define TX3912_INT2_UARTBEMPTYINT                       0x00004000
+#define TX3912_INT2_UARTBDMAFULLINT                     0x00002000
+#define TX3912_INT2_UARTBDMAHALFINT                     0x00001000
+#define TX3912_INT2_UARTA_RX_BITS                       0xf8000000
+#define TX3912_INT2_UARTA_TX_BITS                       0x07c00000
+#define TX3912_INT2_UARTB_RX_BITS                       0x003e0000
+#define TX3912_INT2_UARTB_TX_BITS                       0x0001f000
+
+/*
+ * Interrupt 5 register values
+ */
+#define TX3912_INT5_RTCINT                              0x80000000
+#define TX3912_INT5_ALARMINT                            0x40000000
+#define TX3912_INT5_PERINT                              0x20000000
+#define TX3912_INT5_STPTIMERINT                         0x10000000
+#define TX3912_INT5_POSPWRINT                           0x08000000
+#define TX3912_INT5_NEGPWRINT                           0x04000000
+#define TX3912_INT5_POSPWROKINT                         0x02000000
+#define TX3912_INT5_NEGPWROKINT                         0x01000000
+#define TX3912_INT5_POSONBUTINT                         0x00800000
+#define TX3912_INT5_NEGONBUTINT                         0x00400000
+#define TX3912_INT5_SPIBUFAVAILINT                      0x00200000
+#define TX3912_INT5_SPIERRINT                           0x00100000
+#define TX3912_INT5_SPIRCVINT                           0x00080000
+#define TX3912_INT5_SPIEMPTYINT                         0x00040000
+#define TX3912_INT5_IRCONSMINT                          0x00020000
+#define TX3912_INT5_CARSTINT                            0x00010000
+#define TX3912_INT5_POSCARINT                           0x00008000
+#define TX3912_INT5_NEGCARINT                           0x00004000
+#define TX3912_INT5_IOPOSINT6                           0x00002000
+#define TX3912_INT5_IOPOSINT5                           0x00001000
+#define TX3912_INT5_IOPOSINT4                           0x00000800
+#define TX3912_INT5_IOPOSINT3                           0x00000400
+#define TX3912_INT5_IOPOSINT2                           0x00000200
+#define TX3912_INT5_IOPOSINT1                           0x00000100
+#define TX3912_INT5_IOPOSINT0                           0x00000080
+#define TX3912_INT5_IONEGINT6                           0x00000040
+#define TX3912_INT5_IONEGINT5                           0x00000020
+#define TX3912_INT5_IONEGINT4                           0x00000010
+#define TX3912_INT5_IONEGINT3                           0x00000008
+#define TX3912_INT5_IONEGINT2                           0x00000004
+#define TX3912_INT5_IONEGINT1                           0x00000002
+#define TX3912_INT5_IONEGINT0                           0x00000001
+
+/*
+ * Interrupt 6 status register values
+ */
+#define TX3912_INT6_STATUS_IRQHIGH                      0x80000000
+#define TX3912_INT6_STATUS_IRQLOW                       0x40000000
+#define TX3912_INT6_STATUS_reserved6                    0x3fffffc0
+#define TX3912_INT6_STATUS_INTVEC_POSNEGPWROKINT        0x0000003c
+#define TX3912_INT6_STATUS_INTVEC_ALARMINT              0x00000038
+#define TX3912_INT6_STATUS_INTVEC_PERINT                0x00000034
+#define TX3912_INT6_STATUS_INTVEC_reserved5             0x00000030
+#define TX3912_INT6_STATUS_INTVEC_UARTARXINT            0x0000002c
+#define TX3912_INT6_STATUS_INTVEC_UARTBRXINT            0x00000028
+#define TX3912_INT6_STATUS_INTVEC_reserved4             0x00000024
+#define TX3912_INT6_STATUS_INTVEC_IOPOSINT65            0x00000020
+#define TX3912_INT6_STATUS_INTVEC_reserved3             0x0000001c
+#define TX3912_INT6_STATUS_INTVEC_IONEGINT65            0x00000018
+#define TX3912_INT6_STATUS_INTVEC_reserved2             0x00000014
+#define TX3912_INT6_STATUS_INTVEC_SNDDMACNTINT          0x00000010
+#define TX3912_INT6_STATUS_INTVEC_TELDMACNTINT          0x0000000c
+#define TX3912_INT6_STATUS_INTVEC_CHIDMACNTINT          0x00000008
+#define TX3912_INT6_STATUS_INTVEC_IOPOSNEGINT0          0x00000004
+#define TX3912_INT6_STATUS_INTVEC_STDHANDLER            0x00000000
+#define TX3912_INT6_STATUS_reserved1                    0x00000003
+
+/*
+ * Interrupt 6 enable register values
+ */
+#define TX3912_INT6_ENABLE_reserved5                    0xfff80000
+#define TX3912_INT6_ENABLE_GLOBALEN                     0x00040000
+#define TX3912_INT6_ENABLE_IRQPRITEST                   0x00020000
+#define TX3912_INT6_ENABLE_IRQTEST                      0x00010000
+#define TX3912_INT6_ENABLE_PRIORITYMASK_POSNEGPWROKINT  0x00008000
+#define TX3912_INT6_ENABLE_PRIORITYMASK_ALARMINT        0x00004000
+#define TX3912_INT6_ENABLE_PRIORITYMASK_PERINT          0x00002000
+#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved4       0x00001000
+#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT      0x00000800
+#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTBRXINT      0x00000400
+#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved3       0x00000200
+#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSINT65      0x00000100
+#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved2       0x00000080
+#define TX3912_INT6_ENABLE_PRIORITYMASK_IONEGINT65      0x00000040
+#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved1       0x00000020
+#define TX3912_INT6_ENABLE_PRIORITYMASK_SNDDMACNTINT    0x00000010
+#define TX3912_INT6_ENABLE_PRIORITYMASK_TELDMACNTINT    0x00000008
+#define TX3912_INT6_ENABLE_PRIORITYMASK_CHIDMACNTINT    0x00000004
+#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSNEGINT0    0x00000002
+#define TX3912_INT6_ENABLE_PRIORITYMASK_STDHANDLER      0x00000001
+#define TX3912_INT6_ENABLE_HIGH_PRIORITY                0x0000ffff
+
+
+/*****************************************************************************
+ *      Power Subsystem                                                      *
+ *      ---------------                                                      *
+ *      Chapter 11 in Philips PR31700 User Manual                            *
+ *      Chapter 12 in Toshiba TMPR3905/12 User Manual                        *
+ *****************************************************************************/
+#define TX3912_POWER_CTRL                               0x01c4
+
+/*
+ * Power control register values
+ */
+#define TX3912_POWER_CTRL_ONBUTN                        0x80000000
+#define TX3912_POWER_CTRL_PWRINT                        0x40000000
+#define TX3912_POWER_CTRL_PWROK                         0x20000000
+#define TX3912_POWER_CTRL_VIDRF_MASK                    0x18000000
+#define TX3912_POWER_CTRL_SLOWBUS                       0x04000000
+#define TX3912_POWER_CTRL_DIVMOD                        0x02000000
+#define TX3912_POWER_CTRL_reserved2                     0x01ff0000
+#define TX3912_POWER_CTRL_STPTIMERVAL_MASK              0x0000f000
+#define TX3912_POWER_CTRL_ENSTPTIMER                    0x00000800
+#define TX3912_POWER_CTRL_ENFORCESHUTDWN                0x00000400
+#define TX3912_POWER_CTRL_FORCESHUTDWN                  0x00000200
+#define TX3912_POWER_CTRL_FORCESHUTDWNOCC               0x00000100
+#define TX3912_POWER_CTRL_SELC2MS                       0x00000080
+#define TX3912_POWER_CTRL_reserved1                     0x00000040
+#define TX3912_POWER_CTRL_BPDBVCC3                      0x00000020
+#define TX3912_POWER_CTRL_STOPCPU                       0x00000010
+#define TX3912_POWER_CTRL_DBNCONBUTN                    0x00000008
+#define TX3912_POWER_CTRL_COLDSTART                     0x00000004
+#define TX3912_POWER_CTRL_PWRCS                         0x00000002
+#define TX3912_POWER_CTRL_VCCON                         0x00000001
+
+
+/*****************************************************************************
+ *      Timer Subsystem                                                      *
+ *      ---------------                                                      *
+ *      Chapter 14 in Philips PR31700 User Manual                            *
+ *      Chapter 15 in Toshiba TMPR3905/12 User Manual                        *
+ *****************************************************************************/
+#define TX3912_RTC_HIGH                                 0x0140
+#define TX3912_RTC_LOW                                  0x0144
+#define TX3912_RTC_ALARM_HIGH                           0x0148
+#define TX3912_RTC_ALARM_LOW                            0x014c
+#define TX3912_TIMER_CTRL                               0x0150
+#define TX3912_TIMER_PERIOD                             0x0154
+
+/*
+ * Timer control register values
+ */
+#define TX3912_TIMER_CTRL_FREEZEPRE                     0x00000080
+#define TX3912_TIMER_CTRL_FREEZERTC                     0x00000040
+#define TX3912_TIMER_CTRL_FREEZETIMER                   0x00000020
+#define TX3912_TIMER_CTRL_ENPERTIMER                    0x00000010
+#define TX3912_TIMER_CTRL_RTCCLEAR                      0x00000008
+#define TX3912_TIMER_CTRL_TESTC8MS                      0x00000004
+#define TX3912_TIMER_CTRL_ENTESTCLK                     0x00000002
+#define TX3912_TIMER_CTRL_ENRTCTST                      0x00000001
+
+/*
+ * The periodic timer has granularity of 868 nanoseconds which
+ * results in a count of (1.152 x 10^6 / 100) in order to achieve
+ * a 10 millisecond periodic system clock.
+ */
+#define TX3912_SYS_TIMER_VALUE                          (1152000/HZ)
+
+
+/*****************************************************************************
+ *      UART Subsystem                                                       *
+ *      --------------                                                       *
+ *      Chapter 15 in Philips PR31700 User Manual                            *
+ *      Chapter 16 in Toshiba TMPR3905/12 User Manual                        *
+ *****************************************************************************/
+#define TX3912_UARTA_CTRL1                              0x00b0
+#define TX3912_UARTA_CTRL2                              0x00b4
+#define TX3912_UARTA_DMA_CTRL1                          0x00b8
+#define TX3912_UARTA_DMA_CTRL2                          0x00bc
+#define TX3912_UARTA_DMA_CNT                            0x00c0
+#define TX3912_UARTA_DATA                               0x00c4
+#define TX3912_UARTB_CTRL1                              0x00c8
+#define TX3912_UARTB_CTRL2                              0x00cc
+#define TX3912_UARTB_DMA_CTRL1                          0x00d0
+#define TX3912_UARTB_DMA_CTRL2                          0x00d4
+#define TX3912_UARTB_DMA_CNT                            0x00d8
+#define TX3912_UARTB_DATA                               0x00dc
+
+/*
+ * UART Control Register 1 values
+ */
+#define TX3912_UART_CTRL1_UARTON                        0x80000000
+#define TX3912_UART_CTRL1_EMPTY                         0x40000000
+#define TX3912_UART_CTRL1_PRXHOLDFULL                   0x20000000
+#define TX3912_UART_CTRL1_RXHOLDFULL                    0x10000000
+#define TX3912_UART_CTRL1_reserved1                     0x0fff0000
+#define TX3912_UART_CTRL1_ENDMARX                       0x00008000
+#define TX3912_UART_CTRL1_ENDMATX                       0x00004000
+#define TX3912_UART_CTRL1_TESTMODE                      0x00002000
+#define TX3912_UART_CTRL1_ENBREAKHALT                   0x00001000
+#define TX3912_UART_CTRL1_ENDMATEST                     0x00000800
+#define TX3912_UART_CTRL1_ENDMALOOP                     0x00000400
+#define TX3912_UART_CTRL1_PULSEOPT1                     0x00000200
+#define TX3912_UART_CTRL1_PULSEOPT1                     0x00000100
+#define TX3912_UART_CTRL1_DTINVERT                      0x00000080
+#define TX3912_UART_CTRL1_DISTXD                        0x00000040
+#define TX3912_UART_CTRL1_TWOSTOP                       0x00000020
+#define TX3912_UART_CTRL1_LOOPBACK                      0x00000010
+#define TX3912_UART_CTRL1_BIT_7                         0x00000008
+#define TX3912_UART_CTRL1_EVENPARITY                    0x00000004
+#define TX3912_UART_CTRL1_ENPARITY                      0x00000002
+#define TX3912_UART_CTRL1_ENUART                        0x00000001
+
+/*
+ * UART Control Register 2 values
+ */
+#define TX3912_UART_CTRL2_B230400                       0x0000  /*   0 */
+#define TX3912_UART_CTRL2_B115200                       0x0001  /*   1 */
+#define TX3912_UART_CTRL2_B76800                        0x0002  /*   2 */
+#define TX3912_UART_CTRL2_B57600                        0x0003  /*   3 */
+#define TX3912_UART_CTRL2_B38400                        0x0005  /*   5 */
+#define TX3912_UART_CTRL2_B19200                        0x000b  /*  11 */
+#define TX3912_UART_CTRL2_B9600                         0x0016  /*  22 */
+#define TX3912_UART_CTRL2_B4800                         0x002f  /*  47 */
+#define TX3912_UART_CTRL2_B2400                         0x005f  /*  95 */
+#define TX3912_UART_CTRL2_B1200                         0x00bf  /* 191 */
+#define TX3912_UART_CTRL2_B600                          0x017f  /* 383 */
+#define TX3912_UART_CTRL2_B300                          0x02ff  /* 767 */
+
+/*****************************************************************************
+ *      Video Subsystem                                                      *
+ *      ---------------                                                      *
+ *      Chapter 16 in Philips PR31700 User Manual                            *
+ *      Chapter 17 in Toshiba TMPR3905/12 User Manual                        *
+ *****************************************************************************/
+#define TX3912_VIDEO_CTRL1                              0x0028
+#define TX3912_VIDEO_CTRL2                              0x002c
+#define TX3912_VIDEO_CTRL3                              0x0030
+#define TX3912_VIDEO_CTRL4                              0x0034
+#define TX3912_VIDEO_CTRL5                              0x0038
+#define TX3912_VIDEO_CTRL6                              0x003c
+#define TX3912_VIDEO_CTRL7                              0x0040
+#define TX3912_VIDEO_CTRL8                              0x0044
+#define TX3912_VIDEO_CTRL9                              0x0048
+#define TX3912_VIDEO_CTRL10                             0x004c
+#define TX3912_VIDEO_CTRL11                             0x0050
+#define TX3912_VIDEO_CTRL12                             0x0054
+#define TX3912_VIDEO_CTRL13                             0x0058
+#define TX3912_VIDEO_CTRL14                             0x005c
+
+/*
+ * Video Control Register 1 values
+ */
+#define TX3912_VIDEO_CTRL1_LINECNT                      0xffc00000
+#define TX3912_VIDEO_CTRL1_LOADDLY                      0x00200000
+#define TX3912_VIDEO_CTRL1_BAUDVAL                      0x001f0000
+#define TX3912_VIDEO_CTRL1_VIDDONEVAL                   0x0000fe00
+#define TX3912_VIDEO_CTRL1_ENFREEZEFRAME                0x00000100
+#define TX3912_VIDEO_CTRL1_BITSEL_MASK                  0x000000c0
+#define TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR            0x000000c0
+#define TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY             0x00000080
+#define TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY             0x00000040
+#define TX3912_VIDEO_CTRL1_DISPSPLIT                    0x00000020
+#define TX3912_VIDEO_CTRL1_DISP8                        0x00000010
+#define TX3912_VIDEO_CTRL1_DFMODE                       0x00000008
+#define TX3912_VIDEO_CTRL1_INVVID                       0x00000004
+#define TX3912_VIDEO_CTRL1_DISPON                       0x00000002
+#define TX3912_VIDEO_CTRL1_ENVID                        0x00000001
+
+#endif  /* _TX3912_H_ */
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h
new file mode 100644
index 000000000000..5d93bab51254
--- /dev/null
+++ b/include/asm-mips/tx4927/smsc_fdc37m81x.h
@@ -0,0 +1,69 @@
+/*
+ * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
+ *
+ * Interface for smsc fdc48m81x Super IO chip
+ *
+ * Author: MontaVista Software, Inc. source@mvista.com
+ *
+ * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Manish Lachwani, mlachwani@mvista.com
+ */
+
+#ifndef _SMSC_FDC37M81X_H_
+#define _SMSC_FDC37M81X_H_
+
+/* Common Registers */
+#define SMSC_FDC37M81X_CONFIG_INDEX  0x00
+#define SMSC_FDC37M81X_CONFIG_DATA   0x01
+#define SMSC_FDC37M81X_CONF          0x02
+#define SMSC_FDC37M81X_INDEX         0x03
+#define SMSC_FDC37M81X_DNUM          0x07
+#define SMSC_FDC37M81X_DID           0x20
+#define SMSC_FDC37M81X_DREV          0x21
+#define SMSC_FDC37M81X_PCNT          0x22
+#define SMSC_FDC37M81X_PMGT          0x23
+#define SMSC_FDC37M81X_OSC           0x24
+#define SMSC_FDC37M81X_CONFPA0       0x26
+#define SMSC_FDC37M81X_CONFPA1       0x27
+#define SMSC_FDC37M81X_TEST4         0x2B
+#define SMSC_FDC37M81X_TEST5         0x2C
+#define SMSC_FDC37M81X_TEST1         0x2D
+#define SMSC_FDC37M81X_TEST2         0x2E
+#define SMSC_FDC37M81X_TEST3         0x2F
+
+/* Logical device numbers */
+#define SMSC_FDC37M81X_FDD           0x00
+#define SMSC_FDC37M81X_PARALLEL      0x03
+#define SMSC_FDC37M81X_SERIAL1       0x04
+#define SMSC_FDC37M81X_SERIAL2       0x05
+#define SMSC_FDC37M81X_KBD           0x07
+#define SMSC_FDC37M81X_AUXIO         0x08
+#define SMSC_FDC37M81X_NONE          0xff
+
+/* Logical device Config Registers */
+#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_BASEADDR0     0x60
+#define SMSC_FDC37M81X_BASEADDR1     0x61
+#define SMSC_FDC37M81X_INT           0x70
+#define SMSC_FDC37M81X_INT2          0x72
+#define SMSC_FDC37M81X_LDCR_F0       0xF0
+
+/* Chip Config Values */
+#define SMSC_FDC37M81X_CONFIG_ENTER  0x55
+#define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
+#define SMSC_FDC37M81X_CHIP_ID       0x4d
+
+unsigned long __init smsc_fdc37m81x_init(unsigned long port);
+
+void smsc_fdc37m81x_config_beg(void);
+
+void smsc_fdc37m81x_config_end(void);
+
+void smsc_fdc37m81x_config_set(u8 reg, u8 val);
+
+#endif
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
new file mode 100644
index 000000000000..6ce1e9475f99
--- /dev/null
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -0,0 +1,56 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
+#define __ASM_TX4927_TOSHIBA_RBTX4927_H
+
+#include <linux/config.h>
+#include <asm/tx4927/tx4927.h>
+#include <asm/tx4927/tx4927_mips.h>
+#ifdef CONFIG_PCI
+#include <asm/tx4927/tx4927_pci.h>
+#endif
+
+#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 )
+
+
+#ifdef CONFIG_PCI
+#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
+#else
+#define TBTX4927_ISA_IO_OFFSET 0
+#endif
+
+#define RBTX4927_SW_RESET_DO         0xbc00f000
+#define RBTX4927_SW_RESET_DO_SET                0x01
+
+#define RBTX4927_SW_RESET_ENABLE     0xbc00f002
+#define RBTX4927_SW_RESET_ENABLE_SET            0x01
+
+
+#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
+#define RBTX4927_RTL_8019_IRQ  (29)
+
+#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
new file mode 100644
index 000000000000..5d939db6e220
--- /dev/null
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -0,0 +1,525 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TX4927_TX4927_H
+#define __ASM_TX4927_TX4927_H
+
+#include <asm/tx4927/tx4927_mips.h>
+
+/*
+ This register naming came from the intergrate cpu/controoler name TX4927
+ followed by the device name from table 4.2.2 on page 4-3 and then followed
+ by the register name from table 4.2.3 on pages 4-4 to 4-8.  The manaul
+ used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
+ */
+
+#define TX4927_SIO_0_BASE
+
+/* TX4927 controller */
+#define TX4927_BASE                     0xfff1f0000
+#define TX4927_BASE                     0xfff1f0000
+#define TX4927_LIMIT                    0xfff1fffff
+
+
+/* TX4927 SDRAM controller (64-bit registers) */
+#define TX4927_SDRAMC_BASE              0x8000 
+#define TX4927_SDRAMC_SDCCR0            0x8000 
+#define TX4927_SDRAMC_SDCCR1            0x8008
+#define TX4927_SDRAMC_SDCCR2            0x8010
+#define TX4927_SDRAMC_SDCCR3            0x8018
+#define TX4927_SDRAMC_SDCTR             0x8040
+#define TX4927_SDRAMC_SDCMD             0x8058
+#define TX4927_SDRAMC_LIMIT             0x8fff 
+
+
+/* TX4927 external bus controller (64-bit registers) */
+#define TX4927_EBUSC_BASE               0x9000
+#define TX4927_EBUSC_EBCCR0             0x9000
+#define TX4927_EBUSC_EBCCR1             0x9008
+#define TX4927_EBUSC_EBCCR2             0x9010
+#define TX4927_EBUSC_EBCCR3             0x9018
+#define TX4927_EBUSC_EBCCR4             0x9020
+#define TX4927_EBUSC_EBCCR5             0x9028
+#define TX4927_EBUSC_EBCCR6             0x9030
+#define TX4927_EBUSC_EBCCR7             0x9008
+#define TX4927_EBUSC_LIMIT              0x9fff
+
+
+/* TX4927 SDRRAM Error Check Correction (64-bit registers) */
+#define TX4927_ECC_BASE                 0xa000
+#define TX4927_ECC_ECCCR                0xa000
+#define TX4927_ECC_ECCSR                0xa008
+#define TX4927_ECC_LIMIT                0xafff
+
+
+/* TX4927 DMA Controller (64-bit registers) */
+#define TX4927_DMAC_BASE                0xb000
+#define TX4927_DMAC_TBD                 0xb000
+#define TX4927_DMAC_LIMIT               0xbfff
+
+
+/* TX4927 PCI Controller (32-bit registers) */
+#define TX4927_PCIC_BASE                0xd000
+#define TX4927_PCIC_TBD                 0xb000
+#define TX4927_PCIC_LIMIT               0xdfff
+
+
+/* TX4927 Configuration registers (64-bit registers) */
+#define TX4927_CONFIG_BASE                       0xe000
+#define TX4927_CONFIG_CCFG                       0xe000
+#define TX4927_CONFIG_CCFG_RESERVED_42_63                BM_63_42
+#define TX4927_CONFIG_CCFG_WDRST                         BM_41_41
+#define TX4927_CONFIG_CCFG_WDREXEN                       BM_40_40
+#define TX4927_CONFIG_CCFG_BCFG                          BM_39_32
+#define TX4927_CONFIG_CCFG_RESERVED_27_31                BM_31_27
+#define TX4927_CONFIG_CCFG_GTOT                          BM_26_25
+#define TX4927_CONFIG_CCFG_GTOT_4096                     BM_26_25
+#define TX4927_CONFIG_CCFG_GTOT_2048                     BM_26_26
+#define TX4927_CONFIG_CCFG_GTOT_1024                     BM_25_25
+#define TX4927_CONFIG_CCFG_GTOT_0512                   (~BM_26_25)
+#define TX4927_CONFIG_CCFG_TINTDIS                       BM_24_24
+#define TX4927_CONFIG_CCFG_PCI66                         BM_23_23
+#define TX4927_CONFIG_CCFG_PCIMODE                       BM_22_22
+#define TX4927_CONFIG_CCFG_RESERVED_20_21                BM_21_20
+#define TX4927_CONFIG_CCFG_DIVMODE                       BM_19_17
+#define TX4927_CONFIG_CCFG_DIVMODE_2_0                   BM_19_19
+#define TX4927_CONFIG_CCFG_DIVMODE_3_0                  (BM_19_19|BM_17_17)
+#define TX4927_CONFIG_CCFG_DIVMODE_4_0                   BM_19_18
+#define TX4927_CONFIG_CCFG_DIVMODE_2_5                   BM_19_17
+#define TX4927_CONFIG_CCFG_DIVMODE_8_0                 (~BM_19_17)
+#define TX4927_CONFIG_CCFG_DIVMODE_12_0                  BM_17_17
+#define TX4927_CONFIG_CCFG_DIVMODE_16_0                  BM_18_18
+#define TX4927_CONFIG_CCFG_DIVMODE_10_0                  BM_18_17
+#define TX4927_CONFIG_CCFG_BEOW                          BM_16_16
+#define TX4927_CONFIG_CCFG_WR                            BM_15_15
+#define TX4927_CONFIG_CCFG_TOE                           BM_14_14
+#define TX4927_CONFIG_CCFG_PCIARB                        BM_13_13
+#define TX4927_CONFIG_CCFG_PCIDIVMODE                    BM_12_11
+#define TX4927_CONFIG_CCFG_RESERVED_08_10                BM_10_08
+#define TX4927_CONFIG_CCFG_SYSSP                         BM_07_06
+#define TX4927_CONFIG_CCFG_RESERVED_03_05                BM_05_03
+#define TX4927_CONFIG_CCFG_ENDIAN                        BM_02_02
+#define TX4927_CONFIG_CCFG_ARMODE                        BM_01_01
+#define TX4927_CONFIG_CCFG_ACEHOLD                       BM_00_00
+#define TX4927_CONFIG_REVID                      0xe008
+#define TX4927_CONFIG_REVID_RESERVED_32_63               BM_32_63
+#define TX4927_CONFIG_REVID_PCODE                        BM_16_31
+#define TX4927_CONFIG_REVID_MJERREV                      BM_12_15
+#define TX4927_CONFIG_REVID_MINEREV                      BM_08_11
+#define TX4927_CONFIG_REVID_MJREV                        BM_04_07
+#define TX4927_CONFIG_REVID_MINREV                       BM_00_03
+#define TX4927_CONFIG_PCFG                       0xe010
+#define TX4927_CONFIG_PCFG_RESERVED_57_63                BM_57_63
+#define TX4927_CONFIG_PCFG_DRVDATA                       BM_56_56
+#define TX4927_CONFIG_PCFG_DRVCB                         BM_55_55
+#define TX4927_CONFIG_PCFG_DRVDQM                        BM_54_54
+#define TX4927_CONFIG_PCFG_DRVADDR                       BM_53_53
+#define TX4927_CONFIG_PCFG_DRVCKE                        BM_52_52
+#define TX4927_CONFIG_PCFG_DRVRAS                        BM_51_51
+#define TX4927_CONFIG_PCFG_DRVCAS                        BM_50_50
+#define TX4927_CONFIG_PCFG_DRVWE                         BM_49_49
+#define TX4927_CONFIG_PCFG_DRVCS3                        BM_48_48
+#define TX4927_CONFIG_PCFG_DRVCS2                        BM_47_47
+#define TX4927_CONFIG_PCFG_DRVCS1                        BM_46_4k
+#define TX4927_CONFIG_PCFG_DRVCS0                        BM_45_45
+#define TX4927_CONFIG_PCFG_DRVCK3                        BM_44_44
+#define TX4927_CONFIG_PCFG_DRVCK2                        BM_43_43
+#define TX4927_CONFIG_PCFG_DRVCK1                        BM_42_42
+#define TX4927_CONFIG_PCFG_DRVCK0                        BM_41_41
+#define TX4927_CONFIG_PCFG_DRVCKIN                       BM_40_40
+#define TX4927_CONFIG_PCFG_RESERVED_33_39                BM_33_39
+#define TX4927_CONFIG_PCFG_BYPASS_PLL                    BM_32_32
+#define TX4927_CONFIG_PCFG_RESERVED_30_31                BM_30_31
+#define TX4927_CONFIG_PCFG_SDCLKDLY                      BM_28_29
+#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1            (~BM_28_29)
+#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2              BM_28_28
+#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3              BM_29_29
+#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4              BM_28_29
+#define TX4927_CONFIG_PCFG_SYSCLKEN                      BM_27_27
+#define TX4927_CONFIG_PCFG_SDCLKEN3                      BM_26_26
+#define TX4927_CONFIG_PCFG_SDCLKEN2                      BM_25_25
+#define TX4927_CONFIG_PCFG_SDCLKEN1                      BM_24_24
+#define TX4927_CONFIG_PCFG_SDCLKEN0                      BM_23_23
+#define TX4927_CONFIG_PCFG_SDCLKINEN                     BM_22_22
+#define TX4927_CONFIG_PCFG_PCICLKEN5                     BM_21_21
+#define TX4927_CONFIG_PCFG_PCICLKEN4                     BM_20_20
+#define TX4927_CONFIG_PCFG_PCICLKEN3                     BM_19_19
+#define TX4927_CONFIG_PCFG_PCICLKEN2                     BM_18_18
+#define TX4927_CONFIG_PCFG_PCICLKEN1                     BM_17_17
+#define TX4927_CONFIG_PCFG_PCICLKEN0                     BM_16_16
+#define TX4927_CONFIG_PCFG_RESERVED_10_15                BM_10_15
+#define TX4927_CONFIG_PCFG_SEL2                          BM_09_09
+#define TX4927_CONFIG_PCFG_SEL1                          BM_08_08
+#define TX4927_CONFIG_PCFG_DMASEL3                       BM_06_07
+#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3             (~BM_06_07)
+#define TX4927_CONFIG_PCFG_DMASEL3_SIO0                  BM_06_06
+#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3                 BM_07_07
+#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1                 BM_06_07
+#define TX4927_CONFIG_PCFG_DMASEL2                       BM_06_07
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2      (~BM_06_07)
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0           BM_06_06
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10    BM_07_07
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11    BM_06_07
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1        (~BM_06_07)
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0           BM_06_06
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2          BM_07_07
+#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0          BM_06_07
+#define TX4927_CONFIG_PCFG_DMASEL1                       BM_02_03
+#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1             (~BM_02_03)
+#define TX4927_CONFIG_PCFG_DMASEL1_SIO1                  BM_02_02
+#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1                 BM_03_03
+#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3                 BM_02_03
+#define TX4927_CONFIG_PCFG_DMASEL0                       BM_00_01
+#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0             (~BM_00_01)
+#define TX4927_CONFIG_PCFG_DMASEL0_SIO1                  BM_00_00
+#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0                 BM_01_01
+#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2                 BM_00_01
+#define TX4927_CONFIG_TOEA                       0xe018
+#define TX4927_CONFIG_TOEA_RESERVED_36_63                BM_36_63
+#define TX4927_CONFIG_TOEA_TOEA                          BM_00_35
+#define TX4927_CONFIG_CLKCTR                     0xe020
+#define TX4927_CONFIG_CLKCTR_RESERVED_26_63              BM_26_63
+#define TX4927_CONFIG_CLKCTR_ACLCKD                      BM_25_25
+#define TX4927_CONFIG_CLKCTR_PIOCKD                      BM_24_24
+#define TX4927_CONFIG_CLKCTR_DMACKD                      BM_23_23
+#define TX4927_CONFIG_CLKCTR_PCICKD                      BM_22_22
+#define TX4927_CONFIG_CLKCTR_SET_21                      BM_21_21
+#define TX4927_CONFIG_CLKCTR_TM0CKD                      BM_20_20
+#define TX4927_CONFIG_CLKCTR_TM1CKD                      BM_19_19
+#define TX4927_CONFIG_CLKCTR_TM2CKD                      BM_18_18
+#define TX4927_CONFIG_CLKCTR_SIO0CKD                     BM_17_17
+#define TX4927_CONFIG_CLKCTR_SIO1CKD                     BM_16_16
+#define TX4927_CONFIG_CLKCTR_RESERVED_10_15              BM_10_15
+#define TX4927_CONFIG_CLKCTR_ACLRST                      BM_09_09
+#define TX4927_CONFIG_CLKCTR_PIORST                      BM_08_08
+#define TX4927_CONFIG_CLKCTR_DMARST                      BM_07_07
+#define TX4927_CONFIG_CLKCTR_PCIRST                      BM_06_06
+#define TX4927_CONFIG_CLKCTR_RESERVED_05_05              BM_05_05
+#define TX4927_CONFIG_CLKCTR_TM0RST                      BM_04_04
+#define TX4927_CONFIG_CLKCTR_TM1RST                      BM_03_03
+#define TX4927_CONFIG_CLKCTR_TM2RST                      BM_02_02
+#define TX4927_CONFIG_CLKCTR_SIO0RST                     BM_01_01
+#define TX4927_CONFIG_CLKCTR_SIO1RST                     BM_00_00
+#define TX4927_CONFIG_GARBC                      0xe030
+#define TX4927_CONFIG_GARBC_RESERVED_10_63               BM_10_63
+#define TX4927_CONFIG_GARBC_SET_09                       BM_09_09
+#define TX4927_CONFIG_GARBC_ARBMD                        BM_08_08
+#define TX4927_CONFIG_GARBC_RESERVED_06_07               BM_06_07
+#define TX4927_CONFIG_GARBC_PRIORITY_H1                  BM_04_05
+#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI            (~BM_04_05)
+#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC            BM_04_04
+#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC             BM_05_05
+#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE        BM_04_05
+#define TX4927_CONFIG_GARBC_PRIORITY_H2                  BM_02_03
+#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI            (~BM_02_03)
+#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC            BM_02_02
+#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC             BM_03_03
+#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE        BM_02_03
+#define TX4927_CONFIG_GARBC_PRIORITY_H3                  BM_00_01
+#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI            (~BM_00_01)
+#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC            BM_00_00
+#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC             BM_01_01
+#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE        BM_00_01
+#define TX4927_CONFIG_RAMP                       0xe048
+#define TX4927_CONFIG_RAMP_RESERVED_20_63                BM_20_63
+#define TX4927_CONFIG_RAMP_RAMP                          BM_00_19
+#define TX4927_CONFIG_LIMIT                      0xefff
+
+
+/* TX4927 Timer 0 (32-bit registers) */
+#define TX4927_TMR0_BASE                0xf000
+#define TX4927_TMR0_TMTCR0              0xf004
+#define TX4927_TMR0_TMTISR0             0xf008
+#define TX4927_TMR0_TMCPRA0             0xf008
+#define TX4927_TMR0_TMCPRB0             0xf00c
+#define TX4927_TMR0_TMITMR0             0xf010
+#define TX4927_TMR0_TMCCDR0             0xf020
+#define TX4927_TMR0_TMPGMR0             0xf030
+#define TX4927_TMR0_TMTRR0              0xf0f0
+#define TX4927_TMR0_LIMIT               0xf0ff
+
+
+/* TX4927 Timer 1 (32-bit registers) */
+#define TX4927_TMR1_BASE                0xf100
+#define TX4927_TMR1_TMTCR1              0xf104
+#define TX4927_TMR1_TMTISR1             0xf108
+#define TX4927_TMR1_TMCPRA1             0xf108
+#define TX4927_TMR1_TMCPRB1             0xf10c
+#define TX4927_TMR1_TMITMR1             0xf110
+#define TX4927_TMR1_TMCCDR1             0xf120
+#define TX4927_TMR1_TMPGMR1             0xf130
+#define TX4927_TMR1_TMTRR1              0xf1f0
+#define TX4927_TMR1_LIMIT               0xf1ff
+
+
+/* TX4927 Timer 2 (32-bit registers) */
+#define TX4927_TMR2_BASE                0xf200
+#define TX4927_TMR2_TMTCR2              0xf104
+#define TX4927_TMR2_TMTISR2             0xf208
+#define TX4927_TMR2_TMCPRA2             0xf208
+#define TX4927_TMR2_TMCPRB2             0xf20c
+#define TX4927_TMR2_TMITMR2             0xf210
+#define TX4927_TMR2_TMCCDR2             0xf220
+#define TX4927_TMR2_TMPGMR2             0xf230
+#define TX4927_TMR2_TMTRR2              0xf2f0
+#define TX4927_TMR2_LIMIT               0xf2ff
+
+
+/* TX4927 serial port 0 (32-bit registers) */
+#define TX4927_SIO0_BASE                         0xf300 
+#define TX4927_SIO0_SILCR0                       0xf300 
+#define TX4927_SIO0_SILCR0_RESERVED_16_31                BM_16_31
+#define TX4927_SIO0_SILCR0_RWUB                          BM_15_15
+#define TX4927_SIO0_SILCR0_TWUB                          BM_14_14
+#define TX4927_SIO0_SILCR0_UODE                          BM_13_13
+#define TX4927_SIO0_SILCR0_RESERVED_07_12                BM_07_12
+#define TX4927_SIO0_SILCR0_SCS                           BM_05_06
+#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC             (~BM_05_06)
+#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG              BM_05_05
+#define TX4927_SIO0_SILCR0_SCS_SCLK_EC                   BM_06_06
+#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG                  BM_05_06
+#define TX4927_SIO0_SILCR0_UEPS                          BM_04_04
+#define TX4927_SIO0_SILCR0_UPEN                          BM_03_03
+#define TX4927_SIO0_SILCR0_USBL                          BM_02_02
+#define TX4927_SIO0_SILCR0_UMODE                         BM_00_01
+#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT              BM_00_01
+#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)
+#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC           BM_01_01
+#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC           BM_00_01
+#define TX4927_SIO0_SIDICR0                      0xf304 
+#define TX4927_SIO0_SIDICR0_RESERVED_16_31               BM_16_31
+#define TX4927_SIO0_SIDICR0_TDE                          BM_15_15
+#define TX4927_SIO0_SIDICR0_RDE                          BM_14_14
+#define TX4927_SIO0_SIDICR0_TIE                          BM_13_13
+#define TX4927_SIO0_SIDICR0_RIE                          BM_12_12
+#define TX4927_SIO0_SIDICR0_SPIE                         BM_11_11
+#define TX4927_SIO0_SIDICR0_CTSAC                        BM_09_10
+#define TX4927_SIO0_SIDICR0_CTSAC_NONE                 (~BM_09_10)
+#define TX4927_SIO0_SIDICR0_CTSAC_RISE                   BM_09_09
+#define TX4927_SIO0_SIDICR0_CTSAC_FALL                   BM_10_10
+#define TX4927_SIO0_SIDICR0_CTSAC_BOTH                   BM_09_10
+#define TX4927_SIO0_SIDICR0_RESERVED_06_08               BM_06_08
+#define TX4927_SIO0_SIDICR0_STIE                         BM_00_05
+#define TX4927_SIO0_SIDICR0_STIE_NONE                  (~BM_00_05)
+#define TX4927_SIO0_SIDICR0_STIE_OERS                    BM_05_05
+#define TX4927_SIO0_SIDICR0_STIE_CTSAC                   BM_04_04
+#define TX4927_SIO0_SIDICR0_STIE_RBRKD                   BM_03_03
+#define TX4927_SIO0_SIDICR0_STIE_TRDY                    BM_02_02
+#define TX4927_SIO0_SIDICR0_STIE_TXALS                   BM_01_01
+#define TX4927_SIO0_SIDICR0_STIE_UBRKD                   BM_00_00
+#define TX4927_SIO0_SIDISR0                      0xf308 
+#define TX4927_SIO0_SIDISR0_RESERVED_16_31               BM_16_31
+#define TX4927_SIO0_SIDISR0_UBRK                         BM_15_15
+#define TX4927_SIO0_SIDISR0_UVALID                       BM_14_14
+#define TX4927_SIO0_SIDISR0_UFER                         BM_13_13
+#define TX4927_SIO0_SIDISR0_UPER                         BM_12_12
+#define TX4927_SIO0_SIDISR0_UOER                         BM_11_11
+#define TX4927_SIO0_SIDISR0_ERI                          BM_10_10
+#define TX4927_SIO0_SIDISR0_TOUT                         BM_09_09
+#define TX4927_SIO0_SIDISR0_TDIS                         BM_08_08
+#define TX4927_SIO0_SIDISR0_RDIS                         BM_07_07
+#define TX4927_SIO0_SIDISR0_STIS                         BM_06_06
+#define TX4927_SIO0_SIDISR0_RESERVED_05_05               BM_05_05
+#define TX4927_SIO0_SIDISR0_RFDN                         BM_00_04
+#define TX4927_SIO0_SISCISR0                     0xf30c 
+#define TX4927_SIO0_SISCISR0_RESERVED_06_31              BM_06_31
+#define TX4927_SIO0_SISCISR0_OERS                        BM_05_05
+#define TX4927_SIO0_SISCISR0_CTSS                        BM_04_04
+#define TX4927_SIO0_SISCISR0_RBRKD                       BM_03_03
+#define TX4927_SIO0_SISCISR0_TRDY                        BM_02_02
+#define TX4927_SIO0_SISCISR0_TXALS                       BM_01_01
+#define TX4927_SIO0_SISCISR0_UBRKD                       BM_00_00
+#define TX4927_SIO0_SIFCR0                       0xf310 
+#define TX4927_SIO0_SIFCR0_RESERVED_16_31                BM_16_31
+#define TX4927_SIO0_SIFCR0_SWRST                         BM_16_31
+#define TX4927_SIO0_SIFCR0_RESERVED_09_14                BM_09_14
+#define TX4927_SIO0_SIFCR0_RDIL                          BM_16_31
+#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1                (~BM_07_08)
+#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4                  BM_07_07
+#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8                  BM_08_08
+#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12                 BM_07_08
+#define TX4927_SIO0_SIFCR0_RESERVED_05_06                BM_05_06
+#define TX4927_SIO0_SIFCR0_TDIL                          BM_03_04
+#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1                (~BM_03_04)
+#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4                  BM_03_03
+#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8                  BM_04_04
+#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0                  BM_03_04
+#define TX4927_SIO0_SIFCR0_TFRST                         BM_02_02
+#define TX4927_SIO0_SIFCR0_RFRST                         BM_01_01
+#define TX4927_SIO0_SIFCR0_FRSTE                         BM_00_00
+#define TX4927_SIO0_SIFLCR0                      0xf314 
+#define TX4927_SIO0_SIFLCR0_RESERVED_13_31               BM_13_31
+#define TX4927_SIO0_SIFLCR0_RCS                          BM_12_12
+#define TX4927_SIO0_SIFLCR0_TES                          BM_11_11
+#define TX4927_SIO0_SIFLCR0_RESERVED_10_10               BM_10_10
+#define TX4927_SIO0_SIFLCR0_RTSSC                        BM_09_09
+#define TX4927_SIO0_SIFLCR0_RSDE                         BM_08_08
+#define TX4927_SIO0_SIFLCR0_TSDE                         BM_07_07
+#define TX4927_SIO0_SIFLCR0_RESERVED_05_06               BM_05_06
+#define TX4927_SIO0_SIFLCR0_RTSTL                        BM_01_04
+#define TX4927_SIO0_SIFLCR0_TBRK                         BM_00_00
+#define TX4927_SIO0_SIBGR0                       0xf318 
+#define TX4927_SIO0_SIBGR0_RESERVED_10_31                BM_10_31
+#define TX4927_SIO0_SIBGR0_BCLK                          BM_08_09
+#define TX4927_SIO0_SIBGR0_BCLK_T0                     (~BM_08_09)
+#define TX4927_SIO0_SIBGR0_BCLK_T2                       BM_08_08
+#define TX4927_SIO0_SIBGR0_BCLK_T4                       BM_09_09
+#define TX4927_SIO0_SIBGR0_BCLK_T6                       BM_08_09
+#define TX4927_SIO0_SIBGR0_BRD                           BM_00_07
+#define TX4927_SIO0_SITFIF00                     0xf31c 
+#define TX4927_SIO0_SITFIF00_RESERVED_08_31              BM_08_31
+#define TX4927_SIO0_SITFIF00_TXD                         BM_00_07
+#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31              BM_08_31
+#define TX4927_SIO0_SIRFIFO0_RXD                         BM_00_07
+#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_LIMIT                        0xf3ff 
+
+
+/* TX4927 serial port 1 (32-bit registers) */
+#define TX4927_SIO1_BASE                0xf400 
+#define TX4927_SIO1_SILCR1              0xf400 
+#define TX4927_SIO1_SIDICR1             0xf404 
+#define TX4927_SIO1_SIDISR1             0xf408 
+#define TX4927_SIO1_SISCISR1            0xf40c 
+#define TX4927_SIO1_SIFCR1              0xf410 
+#define TX4927_SIO1_SIFLCR1             0xf414 
+#define TX4927_SIO1_SIBGR1              0xf418 
+#define TX4927_SIO1_SITFIF01            0xf41c 
+#define TX4927_SIO1_SIRFIFO1            0xf420 
+#define TX4927_SIO1_LIMIT               0xf4ff 
+
+
+/* TX4927 parallel port (32-bit registers) */
+#define TX4927_PIO_BASE                 0xf500
+#define TX4927_PIO_PIOD0                0xf500
+#define TX4927_PIO_PIODI                0xf504
+#define TX4927_PIO_PIODIR               0xf508
+#define TX4927_PIO_PIOOD                0xf50c
+#define TX4927_PIO_LIMIT                0xf50f
+
+
+/* TX4927 Interrupt Controller (32-bit registers) */
+#define TX4927_IRC_BASE                 0xf510
+#define TX4927_IRC_IRFLAG0              0xf510
+#define TX4927_IRC_IRFLAG1              0xf514
+#define TX4927_IRC_IRPOL                0xf518
+#define TX4927_IRC_IRRCNT               0xf51c
+#define TX4927_IRC_IRMASKINT            0xf520
+#define TX4927_IRC_IRMASKEXT            0xf524
+#define TX4927_IRC_IRDEN                0xf600
+#define TX4927_IRC_IRDM0                0xf604
+#define TX4927_IRC_IRDM1                0xf608
+#define TX4927_IRC_IRLVL0               0xf610
+#define TX4927_IRC_IRLVL1               0xf614
+#define TX4927_IRC_IRLVL2               0xf618
+#define TX4927_IRC_IRLVL3               0xf61c
+#define TX4927_IRC_IRLVL4               0xf620
+#define TX4927_IRC_IRLVL5               0xf624
+#define TX4927_IRC_IRLVL6               0xf628
+#define TX4927_IRC_IRLVL7               0xf62c
+#define TX4927_IRC_IRMSK                0xf640
+#define TX4927_IRC_IREDC                0xf660
+#define TX4927_IRC_IRPND                0xf680
+#define TX4927_IRC_IRCS                 0xf6a0
+#define TX4927_IRC_LIMIT                0xf6ff
+
+
+/* TX4927 AC-link controller (32-bit registers) */
+#define TX4927_ACLC_BASE                0xf700
+#define TX4927_ACLC_ACCTLEN             0xf700
+#define TX4927_ACLC_ACCTLDIS            0xf704
+#define TX4927_ACLC_ACREGACC            0xf708
+#define TX4927_ACLC_ACINTSTS            0xf710
+#define TX4927_ACLC_ACINTMSTS           0xf714
+#define TX4927_ACLC_ACINTEN             0xf718
+#define TX4927_ACLC_ACINTDIS            0xf71c
+#define TX4927_ACLC_ACSEMAPH            0xf720
+#define TX4927_ACLC_ACGPIDAT            0xf740
+#define TX4927_ACLC_ACGPODAT            0xf744
+#define TX4927_ACLC_ACSLTEN             0xf748
+#define TX4927_ACLC_ACSLTDIS            0xf74c
+#define TX4927_ACLC_ACFIFOSTS           0xf750
+#define TX4927_ACLC_ACDMASTS            0xf780
+#define TX4927_ACLC_ACDMASEL            0xf784
+#define TX4927_ACLC_ACAUDODAT           0xf7a0
+#define TX4927_ACLC_ACSURRDAT           0xf7a4
+#define TX4927_ACLC_ACCENTDAT           0xf7a8
+#define TX4927_ACLC_ACLFEDAT            0xf7ac
+#define TX4927_ACLC_ACAUDIDAT           0xf7b0
+#define TX4927_ACLC_ACMODODAT           0xf7b8
+#define TX4927_ACLC_ACMODIDAT           0xf7bc
+#define TX4927_ACLC_ACREVID             0xf7fc
+#define TX4927_ACLC_LIMIT               0xf7ff
+
+
+#define TX4927_REG(x) ((TX4927_BASE)+(x))
+
+#define TX4927_RD08( reg      )   (*(vu08*)(reg))
+#define TX4927_WR08( reg, val )  ((*(vu08*)(reg))=(val))
+
+#define TX4927_RD16( reg      )   (*(vu16*)(reg))
+#define TX4927_WR16( reg, val )  ((*(vu16*)(reg))=(val))
+
+#define TX4927_RD32( reg      )   (*(vu32*)(reg))
+#define TX4927_WR32( reg, val )  ((*(vu32*)(reg))=(val))
+
+#define TX4927_RD64( reg      )   (*(vu64*)(reg))
+#define TX4927_WR64( reg, val )  ((*(vu64*)(reg))=(val))
+
+#define TX4927_RD( reg      ) TX4927_RD32( reg )
+#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
+
+
+
+
+
+#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
+#define MI8259_IRQ_ISA_RAW_END  15
+#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
+#define TX4927_IRQ_CP0_RAW_END   7
+#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
+#define TX4927_IRQ_PIC_RAW_END  31
+
+
+#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
+#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */
+
+#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
+#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */
+
+#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
+#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */
+
+
+#define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
+#define TX4927_IRQ_USER1            (TX4927_IRQ_CP0_BEG+1)
+#define TX4927_IRQ_NEST_PIC_ON_CP0  (TX4927_IRQ_CP0_BEG+2)
+#define TX4927_IRQ_CPU_TIMER        (TX4927_IRQ_CP0_BEG+7)
+
+#define TX4927_IRQ_NEST_EXT_ON_PIC  (TX4927_IRQ_PIC_BEG+3)
+
+#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_mips.h b/include/asm-mips/tx4927/tx4927_mips.h
new file mode 100644
index 000000000000..242ab93bf2e2
--- /dev/null
+++ b/include/asm-mips/tx4927/tx4927_mips.h
@@ -0,0 +1,4177 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TX4927_TX4927_MIPS_H
+#define __ASM_TX4927_TX4927_MIPS_H
+
+#ifndef __ASSEMBLY__
+
+static inline void asm_wait(void)
+{
+        __asm__(".set\tmips3\n\t"
+                "wait\n\t"
+                ".set\tmips0");
+}
+
+#define reg_rd08(r)    ((u8 )(*((vu8 *)(r))))
+#define reg_rd16(r)    ((u16)(*((vu16*)(r))))
+#define reg_rd32(r)    ((u32)(*((vu32*)(r))))
+#define reg_rd64(r)    ((u64)(*((vu64*)(r))))
+
+#define reg_wr08(r,v)  ((*((vu8 *)(r)))=((u8 )(v)))
+#define reg_wr16(r,v)  ((*((vu16*)(r)))=((u16)(v)))
+#define reg_wr32(r,v)  ((*((vu32*)(r)))=((u32)(v)))
+#define reg_wr64(r,v)  ((*((vu64*)(r)))=((u64)(v)))
+
+typedef volatile __signed char vs8;
+typedef volatile unsigned char vu8;
+
+typedef volatile __signed short vs16;
+typedef volatile unsigned short vu16;
+
+typedef volatile __signed int vs32;
+typedef volatile unsigned int vu32;
+
+typedef  s8  s08;
+typedef vs8 vs08;
+
+typedef  u8  u08;
+typedef vu8 vu08;
+
+
+#if (_MIPS_SZLONG == 64)
+
+typedef volatile __signed__ long vs64;
+typedef volatile unsigned long vu64;
+
+#else
+
+typedef volatile __signed__ long long vs64;
+typedef volatile unsigned long long vu64;
+
+#endif
+
+
+#define BM_00_00 0x0000000000000001
+#define BM_01_00 0x0000000000000003
+#define BM_00_01 BM_01_00
+#define BM_02_00 0x0000000000000007
+#define BM_00_02 BM_02_00
+#define BM_03_00 0x000000000000000f
+#define BM_00_03 BM_03_00
+#define BM_04_00 0x000000000000001f
+#define BM_00_04 BM_04_00
+#define BM_05_00 0x000000000000003f
+#define BM_00_05 BM_05_00
+#define BM_06_00 0x000000000000007f
+#define BM_00_06 BM_06_00
+#define BM_07_00 0x00000000000000ff
+#define BM_00_07 BM_07_00
+#define BM_08_00 0x00000000000001ff
+#define BM_00_08 BM_08_00
+#define BM_09_00 0x00000000000003ff
+#define BM_00_09 BM_09_00
+#define BM_10_00 0x00000000000007ff
+#define BM_00_10 BM_10_00
+#define BM_11_00 0x0000000000000fff
+#define BM_00_11 BM_11_00
+#define BM_12_00 0x0000000000001fff
+#define BM_00_12 BM_12_00
+#define BM_13_00 0x0000000000003fff
+#define BM_00_13 BM_13_00
+#define BM_14_00 0x0000000000007fff
+#define BM_00_14 BM_14_00
+#define BM_15_00 0x000000000000ffff
+#define BM_00_15 BM_15_00
+#define BM_16_00 0x000000000001ffff
+#define BM_00_16 BM_16_00
+#define BM_17_00 0x000000000003ffff
+#define BM_00_17 BM_17_00
+#define BM_18_00 0x000000000007ffff
+#define BM_00_18 BM_18_00
+#define BM_19_00 0x00000000000fffff
+#define BM_00_19 BM_19_00
+#define BM_20_00 0x00000000001fffff
+#define BM_00_20 BM_20_00
+#define BM_21_00 0x00000000003fffff
+#define BM_00_21 BM_21_00
+#define BM_22_00 0x00000000007fffff
+#define BM_00_22 BM_22_00
+#define BM_23_00 0x0000000000ffffff
+#define BM_00_23 BM_23_00
+#define BM_24_00 0x0000000001ffffff
+#define BM_00_24 BM_24_00
+#define BM_25_00 0x0000000003ffffff
+#define BM_00_25 BM_25_00
+#define BM_26_00 0x0000000007ffffff
+#define BM_00_26 BM_26_00
+#define BM_27_00 0x000000000fffffff
+#define BM_00_27 BM_27_00
+#define BM_28_00 0x000000001fffffff
+#define BM_00_28 BM_28_00
+#define BM_29_00 0x000000003fffffff
+#define BM_00_29 BM_29_00
+#define BM_30_00 0x000000007fffffff
+#define BM_00_30 BM_30_00
+#define BM_31_00 0x00000000ffffffff
+#define BM_00_31 BM_31_00
+#define BM_32_00 0x00000001ffffffff
+#define BM_00_32 BM_32_00
+#define BM_33_00 0x00000003ffffffff
+#define BM_00_33 BM_33_00
+#define BM_34_00 0x00000007ffffffff
+#define BM_00_34 BM_34_00
+#define BM_35_00 0x0000000fffffffff
+#define BM_00_35 BM_35_00
+#define BM_36_00 0x0000001fffffffff
+#define BM_00_36 BM_36_00
+#define BM_37_00 0x0000003fffffffff
+#define BM_00_37 BM_37_00
+#define BM_38_00 0x0000007fffffffff
+#define BM_00_38 BM_38_00
+#define BM_39_00 0x000000ffffffffff
+#define BM_00_39 BM_39_00
+#define BM_40_00 0x000001ffffffffff
+#define BM_00_40 BM_40_00
+#define BM_41_00 0x000003ffffffffff
+#define BM_00_41 BM_41_00
+#define BM_42_00 0x000007ffffffffff
+#define BM_00_42 BM_42_00
+#define BM_43_00 0x00000fffffffffff
+#define BM_00_43 BM_43_00
+#define BM_44_00 0x00001fffffffffff
+#define BM_00_44 BM_44_00
+#define BM_45_00 0x00003fffffffffff
+#define BM_00_45 BM_45_00
+#define BM_46_00 0x00007fffffffffff
+#define BM_00_46 BM_46_00
+#define BM_47_00 0x0000ffffffffffff
+#define BM_00_47 BM_47_00
+#define BM_48_00 0x0001ffffffffffff
+#define BM_00_48 BM_48_00
+#define BM_49_00 0x0003ffffffffffff
+#define BM_00_49 BM_49_00
+#define BM_50_00 0x0007ffffffffffff
+#define BM_00_50 BM_50_00
+#define BM_51_00 0x000fffffffffffff
+#define BM_00_51 BM_51_00
+#define BM_52_00 0x001fffffffffffff
+#define BM_00_52 BM_52_00
+#define BM_53_00 0x003fffffffffffff
+#define BM_00_53 BM_53_00
+#define BM_54_00 0x007fffffffffffff
+#define BM_00_54 BM_54_00
+#define BM_55_00 0x00ffffffffffffff
+#define BM_00_55 BM_55_00
+#define BM_56_00 0x01ffffffffffffff
+#define BM_00_56 BM_56_00
+#define BM_57_00 0x03ffffffffffffff
+#define BM_00_57 BM_57_00
+#define BM_58_00 0x07ffffffffffffff
+#define BM_00_58 BM_58_00
+#define BM_59_00 0x0fffffffffffffff
+#define BM_00_59 BM_59_00
+#define BM_60_00 0x1fffffffffffffff
+#define BM_00_60 BM_60_00
+#define BM_61_00 0x3fffffffffffffff
+#define BM_00_61 BM_61_00
+#define BM_62_00 0x7fffffffffffffff
+#define BM_00_62 BM_62_00
+#define BM_63_00 0xffffffffffffffff
+#define BM_00_63 BM_63_00
+#define BM_01_01 0x0000000000000002
+#define BM_02_01 0x0000000000000006
+#define BM_01_02 BM_02_01
+#define BM_03_01 0x000000000000000e
+#define BM_01_03 BM_03_01
+#define BM_04_01 0x000000000000001e
+#define BM_01_04 BM_04_01
+#define BM_05_01 0x000000000000003e
+#define BM_01_05 BM_05_01
+#define BM_06_01 0x000000000000007e
+#define BM_01_06 BM_06_01
+#define BM_07_01 0x00000000000000fe
+#define BM_01_07 BM_07_01
+#define BM_08_01 0x00000000000001fe
+#define BM_01_08 BM_08_01
+#define BM_09_01 0x00000000000003fe
+#define BM_01_09 BM_09_01
+#define BM_10_01 0x00000000000007fe
+#define BM_01_10 BM_10_01
+#define BM_11_01 0x0000000000000ffe
+#define BM_01_11 BM_11_01
+#define BM_12_01 0x0000000000001ffe
+#define BM_01_12 BM_12_01
+#define BM_13_01 0x0000000000003ffe
+#define BM_01_13 BM_13_01
+#define BM_14_01 0x0000000000007ffe
+#define BM_01_14 BM_14_01
+#define BM_15_01 0x000000000000fffe
+#define BM_01_15 BM_15_01
+#define BM_16_01 0x000000000001fffe
+#define BM_01_16 BM_16_01
+#define BM_17_01 0x000000000003fffe
+#define BM_01_17 BM_17_01
+#define BM_18_01 0x000000000007fffe
+#define BM_01_18 BM_18_01
+#define BM_19_01 0x00000000000ffffe
+#define BM_01_19 BM_19_01
+#define BM_20_01 0x00000000001ffffe
+#define BM_01_20 BM_20_01
+#define BM_21_01 0x00000000003ffffe
+#define BM_01_21 BM_21_01
+#define BM_22_01 0x00000000007ffffe
+#define BM_01_22 BM_22_01
+#define BM_23_01 0x0000000000fffffe
+#define BM_01_23 BM_23_01
+#define BM_24_01 0x0000000001fffffe
+#define BM_01_24 BM_24_01
+#define BM_25_01 0x0000000003fffffe
+#define BM_01_25 BM_25_01
+#define BM_26_01 0x0000000007fffffe
+#define BM_01_26 BM_26_01
+#define BM_27_01 0x000000000ffffffe
+#define BM_01_27 BM_27_01
+#define BM_28_01 0x000000001ffffffe
+#define BM_01_28 BM_28_01
+#define BM_29_01 0x000000003ffffffe
+#define BM_01_29 BM_29_01
+#define BM_30_01 0x000000007ffffffe
+#define BM_01_30 BM_30_01
+#define BM_31_01 0x00000000fffffffe
+#define BM_01_31 BM_31_01
+#define BM_32_01 0x00000001fffffffe
+#define BM_01_32 BM_32_01
+#define BM_33_01 0x00000003fffffffe
+#define BM_01_33 BM_33_01
+#define BM_34_01 0x00000007fffffffe
+#define BM_01_34 BM_34_01
+#define BM_35_01 0x0000000ffffffffe
+#define BM_01_35 BM_35_01
+#define BM_36_01 0x0000001ffffffffe
+#define BM_01_36 BM_36_01
+#define BM_37_01 0x0000003ffffffffe
+#define BM_01_37 BM_37_01
+#define BM_38_01 0x0000007ffffffffe
+#define BM_01_38 BM_38_01
+#define BM_39_01 0x000000fffffffffe
+#define BM_01_39 BM_39_01
+#define BM_40_01 0x000001fffffffffe
+#define BM_01_40 BM_40_01
+#define BM_41_01 0x000003fffffffffe
+#define BM_01_41 BM_41_01
+#define BM_42_01 0x000007fffffffffe
+#define BM_01_42 BM_42_01
+#define BM_43_01 0x00000ffffffffffe
+#define BM_01_43 BM_43_01
+#define BM_44_01 0x00001ffffffffffe
+#define BM_01_44 BM_44_01
+#define BM_45_01 0x00003ffffffffffe
+#define BM_01_45 BM_45_01
+#define BM_46_01 0x00007ffffffffffe
+#define BM_01_46 BM_46_01
+#define BM_47_01 0x0000fffffffffffe
+#define BM_01_47 BM_47_01
+#define BM_48_01 0x0001fffffffffffe
+#define BM_01_48 BM_48_01
+#define BM_49_01 0x0003fffffffffffe
+#define BM_01_49 BM_49_01
+#define BM_50_01 0x0007fffffffffffe
+#define BM_01_50 BM_50_01
+#define BM_51_01 0x000ffffffffffffe
+#define BM_01_51 BM_51_01
+#define BM_52_01 0x001ffffffffffffe
+#define BM_01_52 BM_52_01
+#define BM_53_01 0x003ffffffffffffe
+#define BM_01_53 BM_53_01
+#define BM_54_01 0x007ffffffffffffe
+#define BM_01_54 BM_54_01
+#define BM_55_01 0x00fffffffffffffe
+#define BM_01_55 BM_55_01
+#define BM_56_01 0x01fffffffffffffe
+#define BM_01_56 BM_56_01
+#define BM_57_01 0x03fffffffffffffe
+#define BM_01_57 BM_57_01
+#define BM_58_01 0x07fffffffffffffe
+#define BM_01_58 BM_58_01
+#define BM_59_01 0x0ffffffffffffffe
+#define BM_01_59 BM_59_01
+#define BM_60_01 0x1ffffffffffffffe
+#define BM_01_60 BM_60_01
+#define BM_61_01 0x3ffffffffffffffe
+#define BM_01_61 BM_61_01
+#define BM_62_01 0x7ffffffffffffffe
+#define BM_01_62 BM_62_01
+#define BM_63_01 0xfffffffffffffffe
+#define BM_01_63 BM_63_01
+#define BM_02_02 0x0000000000000004
+#define BM_03_02 0x000000000000000c
+#define BM_02_03 BM_03_02
+#define BM_04_02 0x000000000000001c
+#define BM_02_04 BM_04_02
+#define BM_05_02 0x000000000000003c
+#define BM_02_05 BM_05_02
+#define BM_06_02 0x000000000000007c
+#define BM_02_06 BM_06_02
+#define BM_07_02 0x00000000000000fc
+#define BM_02_07 BM_07_02
+#define BM_08_02 0x00000000000001fc
+#define BM_02_08 BM_08_02
+#define BM_09_02 0x00000000000003fc
+#define BM_02_09 BM_09_02
+#define BM_10_02 0x00000000000007fc
+#define BM_02_10 BM_10_02
+#define BM_11_02 0x0000000000000ffc
+#define BM_02_11 BM_11_02
+#define BM_12_02 0x0000000000001ffc
+#define BM_02_12 BM_12_02
+#define BM_13_02 0x0000000000003ffc
+#define BM_02_13 BM_13_02
+#define BM_14_02 0x0000000000007ffc
+#define BM_02_14 BM_14_02
+#define BM_15_02 0x000000000000fffc
+#define BM_02_15 BM_15_02
+#define BM_16_02 0x000000000001fffc
+#define BM_02_16 BM_16_02
+#define BM_17_02 0x000000000003fffc
+#define BM_02_17 BM_17_02
+#define BM_18_02 0x000000000007fffc
+#define BM_02_18 BM_18_02
+#define BM_19_02 0x00000000000ffffc
+#define BM_02_19 BM_19_02
+#define BM_20_02 0x00000000001ffffc
+#define BM_02_20 BM_20_02
+#define BM_21_02 0x00000000003ffffc
+#define BM_02_21 BM_21_02
+#define BM_22_02 0x00000000007ffffc
+#define BM_02_22 BM_22_02
+#define BM_23_02 0x0000000000fffffc
+#define BM_02_23 BM_23_02
+#define BM_24_02 0x0000000001fffffc
+#define BM_02_24 BM_24_02
+#define BM_25_02 0x0000000003fffffc
+#define BM_02_25 BM_25_02
+#define BM_26_02 0x0000000007fffffc
+#define BM_02_26 BM_26_02
+#define BM_27_02 0x000000000ffffffc
+#define BM_02_27 BM_27_02
+#define BM_28_02 0x000000001ffffffc
+#define BM_02_28 BM_28_02
+#define BM_29_02 0x000000003ffffffc
+#define BM_02_29 BM_29_02
+#define BM_30_02 0x000000007ffffffc
+#define BM_02_30 BM_30_02
+#define BM_31_02 0x00000000fffffffc
+#define BM_02_31 BM_31_02
+#define BM_32_02 0x00000001fffffffc
+#define BM_02_32 BM_32_02
+#define BM_33_02 0x00000003fffffffc
+#define BM_02_33 BM_33_02
+#define BM_34_02 0x00000007fffffffc
+#define BM_02_34 BM_34_02
+#define BM_35_02 0x0000000ffffffffc
+#define BM_02_35 BM_35_02
+#define BM_36_02 0x0000001ffffffffc
+#define BM_02_36 BM_36_02
+#define BM_37_02 0x0000003ffffffffc
+#define BM_02_37 BM_37_02
+#define BM_38_02 0x0000007ffffffffc
+#define BM_02_38 BM_38_02
+#define BM_39_02 0x000000fffffffffc
+#define BM_02_39 BM_39_02
+#define BM_40_02 0x000001fffffffffc
+#define BM_02_40 BM_40_02
+#define BM_41_02 0x000003fffffffffc
+#define BM_02_41 BM_41_02
+#define BM_42_02 0x000007fffffffffc
+#define BM_02_42 BM_42_02
+#define BM_43_02 0x00000ffffffffffc
+#define BM_02_43 BM_43_02
+#define BM_44_02 0x00001ffffffffffc
+#define BM_02_44 BM_44_02
+#define BM_45_02 0x00003ffffffffffc
+#define BM_02_45 BM_45_02
+#define BM_46_02 0x00007ffffffffffc
+#define BM_02_46 BM_46_02
+#define BM_47_02 0x0000fffffffffffc
+#define BM_02_47 BM_47_02
+#define BM_48_02 0x0001fffffffffffc
+#define BM_02_48 BM_48_02
+#define BM_49_02 0x0003fffffffffffc
+#define BM_02_49 BM_49_02
+#define BM_50_02 0x0007fffffffffffc
+#define BM_02_50 BM_50_02
+#define BM_51_02 0x000ffffffffffffc
+#define BM_02_51 BM_51_02
+#define BM_52_02 0x001ffffffffffffc
+#define BM_02_52 BM_52_02
+#define BM_53_02 0x003ffffffffffffc
+#define BM_02_53 BM_53_02
+#define BM_54_02 0x007ffffffffffffc
+#define BM_02_54 BM_54_02
+#define BM_55_02 0x00fffffffffffffc
+#define BM_02_55 BM_55_02
+#define BM_56_02 0x01fffffffffffffc
+#define BM_02_56 BM_56_02
+#define BM_57_02 0x03fffffffffffffc
+#define BM_02_57 BM_57_02
+#define BM_58_02 0x07fffffffffffffc
+#define BM_02_58 BM_58_02
+#define BM_59_02 0x0ffffffffffffffc
+#define BM_02_59 BM_59_02
+#define BM_60_02 0x1ffffffffffffffc
+#define BM_02_60 BM_60_02
+#define BM_61_02 0x3ffffffffffffffc
+#define BM_02_61 BM_61_02
+#define BM_62_02 0x7ffffffffffffffc
+#define BM_02_62 BM_62_02
+#define BM_63_02 0xfffffffffffffffc
+#define BM_02_63 BM_63_02
+#define BM_03_03 0x0000000000000008
+#define BM_04_03 0x0000000000000018
+#define BM_03_04 BM_04_03
+#define BM_05_03 0x0000000000000038
+#define BM_03_05 BM_05_03
+#define BM_06_03 0x0000000000000078
+#define BM_03_06 BM_06_03
+#define BM_07_03 0x00000000000000f8
+#define BM_03_07 BM_07_03
+#define BM_08_03 0x00000000000001f8
+#define BM_03_08 BM_08_03
+#define BM_09_03 0x00000000000003f8
+#define BM_03_09 BM_09_03
+#define BM_10_03 0x00000000000007f8
+#define BM_03_10 BM_10_03
+#define BM_11_03 0x0000000000000ff8
+#define BM_03_11 BM_11_03
+#define BM_12_03 0x0000000000001ff8
+#define BM_03_12 BM_12_03
+#define BM_13_03 0x0000000000003ff8
+#define BM_03_13 BM_13_03
+#define BM_14_03 0x0000000000007ff8
+#define BM_03_14 BM_14_03
+#define BM_15_03 0x000000000000fff8
+#define BM_03_15 BM_15_03
+#define BM_16_03 0x000000000001fff8
+#define BM_03_16 BM_16_03
+#define BM_17_03 0x000000000003fff8
+#define BM_03_17 BM_17_03
+#define BM_18_03 0x000000000007fff8
+#define BM_03_18 BM_18_03
+#define BM_19_03 0x00000000000ffff8
+#define BM_03_19 BM_19_03
+#define BM_20_03 0x00000000001ffff8
+#define BM_03_20 BM_20_03
+#define BM_21_03 0x00000000003ffff8
+#define BM_03_21 BM_21_03
+#define BM_22_03 0x00000000007ffff8
+#define BM_03_22 BM_22_03
+#define BM_23_03 0x0000000000fffff8
+#define BM_03_23 BM_23_03
+#define BM_24_03 0x0000000001fffff8
+#define BM_03_24 BM_24_03
+#define BM_25_03 0x0000000003fffff8
+#define BM_03_25 BM_25_03
+#define BM_26_03 0x0000000007fffff8
+#define BM_03_26 BM_26_03
+#define BM_27_03 0x000000000ffffff8
+#define BM_03_27 BM_27_03
+#define BM_28_03 0x000000001ffffff8
+#define BM_03_28 BM_28_03
+#define BM_29_03 0x000000003ffffff8
+#define BM_03_29 BM_29_03
+#define BM_30_03 0x000000007ffffff8
+#define BM_03_30 BM_30_03
+#define BM_31_03 0x00000000fffffff8
+#define BM_03_31 BM_31_03
+#define BM_32_03 0x00000001fffffff8
+#define BM_03_32 BM_32_03
+#define BM_33_03 0x00000003fffffff8
+#define BM_03_33 BM_33_03
+#define BM_34_03 0x00000007fffffff8
+#define BM_03_34 BM_34_03
+#define BM_35_03 0x0000000ffffffff8
+#define BM_03_35 BM_35_03
+#define BM_36_03 0x0000001ffffffff8
+#define BM_03_36 BM_36_03
+#define BM_37_03 0x0000003ffffffff8
+#define BM_03_37 BM_37_03
+#define BM_38_03 0x0000007ffffffff8
+#define BM_03_38 BM_38_03
+#define BM_39_03 0x000000fffffffff8
+#define BM_03_39 BM_39_03
+#define BM_40_03 0x000001fffffffff8
+#define BM_03_40 BM_40_03
+#define BM_41_03 0x000003fffffffff8
+#define BM_03_41 BM_41_03
+#define BM_42_03 0x000007fffffffff8
+#define BM_03_42 BM_42_03
+#define BM_43_03 0x00000ffffffffff8
+#define BM_03_43 BM_43_03
+#define BM_44_03 0x00001ffffffffff8
+#define BM_03_44 BM_44_03
+#define BM_45_03 0x00003ffffffffff8
+#define BM_03_45 BM_45_03
+#define BM_46_03 0x00007ffffffffff8
+#define BM_03_46 BM_46_03
+#define BM_47_03 0x0000fffffffffff8
+#define BM_03_47 BM_47_03
+#define BM_48_03 0x0001fffffffffff8
+#define BM_03_48 BM_48_03
+#define BM_49_03 0x0003fffffffffff8
+#define BM_03_49 BM_49_03
+#define BM_50_03 0x0007fffffffffff8
+#define BM_03_50 BM_50_03
+#define BM_51_03 0x000ffffffffffff8
+#define BM_03_51 BM_51_03
+#define BM_52_03 0x001ffffffffffff8
+#define BM_03_52 BM_52_03
+#define BM_53_03 0x003ffffffffffff8
+#define BM_03_53 BM_53_03
+#define BM_54_03 0x007ffffffffffff8
+#define BM_03_54 BM_54_03
+#define BM_55_03 0x00fffffffffffff8
+#define BM_03_55 BM_55_03
+#define BM_56_03 0x01fffffffffffff8
+#define BM_03_56 BM_56_03
+#define BM_57_03 0x03fffffffffffff8
+#define BM_03_57 BM_57_03
+#define BM_58_03 0x07fffffffffffff8
+#define BM_03_58 BM_58_03
+#define BM_59_03 0x0ffffffffffffff8
+#define BM_03_59 BM_59_03
+#define BM_60_03 0x1ffffffffffffff8
+#define BM_03_60 BM_60_03
+#define BM_61_03 0x3ffffffffffffff8
+#define BM_03_61 BM_61_03
+#define BM_62_03 0x7ffffffffffffff8
+#define BM_03_62 BM_62_03
+#define BM_63_03 0xfffffffffffffff8
+#define BM_03_63 BM_63_03
+#define BM_04_04 0x0000000000000010
+#define BM_05_04 0x0000000000000030
+#define BM_04_05 BM_05_04
+#define BM_06_04 0x0000000000000070
+#define BM_04_06 BM_06_04
+#define BM_07_04 0x00000000000000f0
+#define BM_04_07 BM_07_04
+#define BM_08_04 0x00000000000001f0
+#define BM_04_08 BM_08_04
+#define BM_09_04 0x00000000000003f0
+#define BM_04_09 BM_09_04
+#define BM_10_04 0x00000000000007f0
+#define BM_04_10 BM_10_04
+#define BM_11_04 0x0000000000000ff0
+#define BM_04_11 BM_11_04
+#define BM_12_04 0x0000000000001ff0
+#define BM_04_12 BM_12_04
+#define BM_13_04 0x0000000000003ff0
+#define BM_04_13 BM_13_04
+#define BM_14_04 0x0000000000007ff0
+#define BM_04_14 BM_14_04
+#define BM_15_04 0x000000000000fff0
+#define BM_04_15 BM_15_04
+#define BM_16_04 0x000000000001fff0
+#define BM_04_16 BM_16_04
+#define BM_17_04 0x000000000003fff0
+#define BM_04_17 BM_17_04
+#define BM_18_04 0x000000000007fff0
+#define BM_04_18 BM_18_04
+#define BM_19_04 0x00000000000ffff0
+#define BM_04_19 BM_19_04
+#define BM_20_04 0x00000000001ffff0
+#define BM_04_20 BM_20_04
+#define BM_21_04 0x00000000003ffff0
+#define BM_04_21 BM_21_04
+#define BM_22_04 0x00000000007ffff0
+#define BM_04_22 BM_22_04
+#define BM_23_04 0x0000000000fffff0
+#define BM_04_23 BM_23_04
+#define BM_24_04 0x0000000001fffff0
+#define BM_04_24 BM_24_04
+#define BM_25_04 0x0000000003fffff0
+#define BM_04_25 BM_25_04
+#define BM_26_04 0x0000000007fffff0
+#define BM_04_26 BM_26_04
+#define BM_27_04 0x000000000ffffff0
+#define BM_04_27 BM_27_04
+#define BM_28_04 0x000000001ffffff0
+#define BM_04_28 BM_28_04
+#define BM_29_04 0x000000003ffffff0
+#define BM_04_29 BM_29_04
+#define BM_30_04 0x000000007ffffff0
+#define BM_04_30 BM_30_04
+#define BM_31_04 0x00000000fffffff0
+#define BM_04_31 BM_31_04
+#define BM_32_04 0x00000001fffffff0
+#define BM_04_32 BM_32_04
+#define BM_33_04 0x00000003fffffff0
+#define BM_04_33 BM_33_04
+#define BM_34_04 0x00000007fffffff0
+#define BM_04_34 BM_34_04
+#define BM_35_04 0x0000000ffffffff0
+#define BM_04_35 BM_35_04
+#define BM_36_04 0x0000001ffffffff0
+#define BM_04_36 BM_36_04
+#define BM_37_04 0x0000003ffffffff0
+#define BM_04_37 BM_37_04
+#define BM_38_04 0x0000007ffffffff0
+#define BM_04_38 BM_38_04
+#define BM_39_04 0x000000fffffffff0
+#define BM_04_39 BM_39_04
+#define BM_40_04 0x000001fffffffff0
+#define BM_04_40 BM_40_04
+#define BM_41_04 0x000003fffffffff0
+#define BM_04_41 BM_41_04
+#define BM_42_04 0x000007fffffffff0
+#define BM_04_42 BM_42_04
+#define BM_43_04 0x00000ffffffffff0
+#define BM_04_43 BM_43_04
+#define BM_44_04 0x00001ffffffffff0
+#define BM_04_44 BM_44_04
+#define BM_45_04 0x00003ffffffffff0
+#define BM_04_45 BM_45_04
+#define BM_46_04 0x00007ffffffffff0
+#define BM_04_46 BM_46_04
+#define BM_47_04 0x0000fffffffffff0
+#define BM_04_47 BM_47_04
+#define BM_48_04 0x0001fffffffffff0
+#define BM_04_48 BM_48_04
+#define BM_49_04 0x0003fffffffffff0
+#define BM_04_49 BM_49_04
+#define BM_50_04 0x0007fffffffffff0
+#define BM_04_50 BM_50_04
+#define BM_51_04 0x000ffffffffffff0
+#define BM_04_51 BM_51_04
+#define BM_52_04 0x001ffffffffffff0
+#define BM_04_52 BM_52_04
+#define BM_53_04 0x003ffffffffffff0
+#define BM_04_53 BM_53_04
+#define BM_54_04 0x007ffffffffffff0
+#define BM_04_54 BM_54_04
+#define BM_55_04 0x00fffffffffffff0
+#define BM_04_55 BM_55_04
+#define BM_56_04 0x01fffffffffffff0
+#define BM_04_56 BM_56_04
+#define BM_57_04 0x03fffffffffffff0
+#define BM_04_57 BM_57_04
+#define BM_58_04 0x07fffffffffffff0
+#define BM_04_58 BM_58_04
+#define BM_59_04 0x0ffffffffffffff0
+#define BM_04_59 BM_59_04
+#define BM_60_04 0x1ffffffffffffff0
+#define BM_04_60 BM_60_04
+#define BM_61_04 0x3ffffffffffffff0
+#define BM_04_61 BM_61_04
+#define BM_62_04 0x7ffffffffffffff0
+#define BM_04_62 BM_62_04
+#define BM_63_04 0xfffffffffffffff0
+#define BM_04_63 BM_63_04
+#define BM_05_05 0x0000000000000020
+#define BM_06_05 0x0000000000000060
+#define BM_05_06 BM_06_05
+#define BM_07_05 0x00000000000000e0
+#define BM_05_07 BM_07_05
+#define BM_08_05 0x00000000000001e0
+#define BM_05_08 BM_08_05
+#define BM_09_05 0x00000000000003e0
+#define BM_05_09 BM_09_05
+#define BM_10_05 0x00000000000007e0
+#define BM_05_10 BM_10_05
+#define BM_11_05 0x0000000000000fe0
+#define BM_05_11 BM_11_05
+#define BM_12_05 0x0000000000001fe0
+#define BM_05_12 BM_12_05
+#define BM_13_05 0x0000000000003fe0
+#define BM_05_13 BM_13_05
+#define BM_14_05 0x0000000000007fe0
+#define BM_05_14 BM_14_05
+#define BM_15_05 0x000000000000ffe0
+#define BM_05_15 BM_15_05
+#define BM_16_05 0x000000000001ffe0
+#define BM_05_16 BM_16_05
+#define BM_17_05 0x000000000003ffe0
+#define BM_05_17 BM_17_05
+#define BM_18_05 0x000000000007ffe0
+#define BM_05_18 BM_18_05
+#define BM_19_05 0x00000000000fffe0
+#define BM_05_19 BM_19_05
+#define BM_20_05 0x00000000001fffe0
+#define BM_05_20 BM_20_05
+#define BM_21_05 0x00000000003fffe0
+#define BM_05_21 BM_21_05
+#define BM_22_05 0x00000000007fffe0
+#define BM_05_22 BM_22_05
+#define BM_23_05 0x0000000000ffffe0
+#define BM_05_23 BM_23_05
+#define BM_24_05 0x0000000001ffffe0
+#define BM_05_24 BM_24_05
+#define BM_25_05 0x0000000003ffffe0
+#define BM_05_25 BM_25_05
+#define BM_26_05 0x0000000007ffffe0
+#define BM_05_26 BM_26_05
+#define BM_27_05 0x000000000fffffe0
+#define BM_05_27 BM_27_05
+#define BM_28_05 0x000000001fffffe0
+#define BM_05_28 BM_28_05
+#define BM_29_05 0x000000003fffffe0
+#define BM_05_29 BM_29_05
+#define BM_30_05 0x000000007fffffe0
+#define BM_05_30 BM_30_05
+#define BM_31_05 0x00000000ffffffe0
+#define BM_05_31 BM_31_05
+#define BM_32_05 0x00000001ffffffe0
+#define BM_05_32 BM_32_05
+#define BM_33_05 0x00000003ffffffe0
+#define BM_05_33 BM_33_05
+#define BM_34_05 0x00000007ffffffe0
+#define BM_05_34 BM_34_05
+#define BM_35_05 0x0000000fffffffe0
+#define BM_05_35 BM_35_05
+#define BM_36_05 0x0000001fffffffe0
+#define BM_05_36 BM_36_05
+#define BM_37_05 0x0000003fffffffe0
+#define BM_05_37 BM_37_05
+#define BM_38_05 0x0000007fffffffe0
+#define BM_05_38 BM_38_05
+#define BM_39_05 0x000000ffffffffe0
+#define BM_05_39 BM_39_05
+#define BM_40_05 0x000001ffffffffe0
+#define BM_05_40 BM_40_05
+#define BM_41_05 0x000003ffffffffe0
+#define BM_05_41 BM_41_05
+#define BM_42_05 0x000007ffffffffe0
+#define BM_05_42 BM_42_05
+#define BM_43_05 0x00000fffffffffe0
+#define BM_05_43 BM_43_05
+#define BM_44_05 0x00001fffffffffe0
+#define BM_05_44 BM_44_05
+#define BM_45_05 0x00003fffffffffe0
+#define BM_05_45 BM_45_05
+#define BM_46_05 0x00007fffffffffe0
+#define BM_05_46 BM_46_05
+#define BM_47_05 0x0000ffffffffffe0
+#define BM_05_47 BM_47_05
+#define BM_48_05 0x0001ffffffffffe0
+#define BM_05_48 BM_48_05
+#define BM_49_05 0x0003ffffffffffe0
+#define BM_05_49 BM_49_05
+#define BM_50_05 0x0007ffffffffffe0
+#define BM_05_50 BM_50_05
+#define BM_51_05 0x000fffffffffffe0
+#define BM_05_51 BM_51_05
+#define BM_52_05 0x001fffffffffffe0
+#define BM_05_52 BM_52_05
+#define BM_53_05 0x003fffffffffffe0
+#define BM_05_53 BM_53_05
+#define BM_54_05 0x007fffffffffffe0
+#define BM_05_54 BM_54_05
+#define BM_55_05 0x00ffffffffffffe0
+#define BM_05_55 BM_55_05
+#define BM_56_05 0x01ffffffffffffe0
+#define BM_05_56 BM_56_05
+#define BM_57_05 0x03ffffffffffffe0
+#define BM_05_57 BM_57_05
+#define BM_58_05 0x07ffffffffffffe0
+#define BM_05_58 BM_58_05
+#define BM_59_05 0x0fffffffffffffe0
+#define BM_05_59 BM_59_05
+#define BM_60_05 0x1fffffffffffffe0
+#define BM_05_60 BM_60_05
+#define BM_61_05 0x3fffffffffffffe0
+#define BM_05_61 BM_61_05
+#define BM_62_05 0x7fffffffffffffe0
+#define BM_05_62 BM_62_05
+#define BM_63_05 0xffffffffffffffe0
+#define BM_05_63 BM_63_05
+#define BM_06_06 0x0000000000000040
+#define BM_07_06 0x00000000000000c0
+#define BM_06_07 BM_07_06
+#define BM_08_06 0x00000000000001c0
+#define BM_06_08 BM_08_06
+#define BM_09_06 0x00000000000003c0
+#define BM_06_09 BM_09_06
+#define BM_10_06 0x00000000000007c0
+#define BM_06_10 BM_10_06
+#define BM_11_06 0x0000000000000fc0
+#define BM_06_11 BM_11_06
+#define BM_12_06 0x0000000000001fc0
+#define BM_06_12 BM_12_06
+#define BM_13_06 0x0000000000003fc0
+#define BM_06_13 BM_13_06
+#define BM_14_06 0x0000000000007fc0
+#define BM_06_14 BM_14_06
+#define BM_15_06 0x000000000000ffc0
+#define BM_06_15 BM_15_06
+#define BM_16_06 0x000000000001ffc0
+#define BM_06_16 BM_16_06
+#define BM_17_06 0x000000000003ffc0
+#define BM_06_17 BM_17_06
+#define BM_18_06 0x000000000007ffc0
+#define BM_06_18 BM_18_06
+#define BM_19_06 0x00000000000fffc0
+#define BM_06_19 BM_19_06
+#define BM_20_06 0x00000000001fffc0
+#define BM_06_20 BM_20_06
+#define BM_21_06 0x00000000003fffc0
+#define BM_06_21 BM_21_06
+#define BM_22_06 0x00000000007fffc0
+#define BM_06_22 BM_22_06
+#define BM_23_06 0x0000000000ffffc0
+#define BM_06_23 BM_23_06
+#define BM_24_06 0x0000000001ffffc0
+#define BM_06_24 BM_24_06
+#define BM_25_06 0x0000000003ffffc0
+#define BM_06_25 BM_25_06
+#define BM_26_06 0x0000000007ffffc0
+#define BM_06_26 BM_26_06
+#define BM_27_06 0x000000000fffffc0
+#define BM_06_27 BM_27_06
+#define BM_28_06 0x000000001fffffc0
+#define BM_06_28 BM_28_06
+#define BM_29_06 0x000000003fffffc0
+#define BM_06_29 BM_29_06
+#define BM_30_06 0x000000007fffffc0
+#define BM_06_30 BM_30_06
+#define BM_31_06 0x00000000ffffffc0
+#define BM_06_31 BM_31_06
+#define BM_32_06 0x00000001ffffffc0
+#define BM_06_32 BM_32_06
+#define BM_33_06 0x00000003ffffffc0
+#define BM_06_33 BM_33_06
+#define BM_34_06 0x00000007ffffffc0
+#define BM_06_34 BM_34_06
+#define BM_35_06 0x0000000fffffffc0
+#define BM_06_35 BM_35_06
+#define BM_36_06 0x0000001fffffffc0
+#define BM_06_36 BM_36_06
+#define BM_37_06 0x0000003fffffffc0
+#define BM_06_37 BM_37_06
+#define BM_38_06 0x0000007fffffffc0
+#define BM_06_38 BM_38_06
+#define BM_39_06 0x000000ffffffffc0
+#define BM_06_39 BM_39_06
+#define BM_40_06 0x000001ffffffffc0
+#define BM_06_40 BM_40_06
+#define BM_41_06 0x000003ffffffffc0
+#define BM_06_41 BM_41_06
+#define BM_42_06 0x000007ffffffffc0
+#define BM_06_42 BM_42_06
+#define BM_43_06 0x00000fffffffffc0
+#define BM_06_43 BM_43_06
+#define BM_44_06 0x00001fffffffffc0
+#define BM_06_44 BM_44_06
+#define BM_45_06 0x00003fffffffffc0
+#define BM_06_45 BM_45_06
+#define BM_46_06 0x00007fffffffffc0
+#define BM_06_46 BM_46_06
+#define BM_47_06 0x0000ffffffffffc0
+#define BM_06_47 BM_47_06
+#define BM_48_06 0x0001ffffffffffc0
+#define BM_06_48 BM_48_06
+#define BM_49_06 0x0003ffffffffffc0
+#define BM_06_49 BM_49_06
+#define BM_50_06 0x0007ffffffffffc0
+#define BM_06_50 BM_50_06
+#define BM_51_06 0x000fffffffffffc0
+#define BM_06_51 BM_51_06
+#define BM_52_06 0x001fffffffffffc0
+#define BM_06_52 BM_52_06
+#define BM_53_06 0x003fffffffffffc0
+#define BM_06_53 BM_53_06
+#define BM_54_06 0x007fffffffffffc0
+#define BM_06_54 BM_54_06
+#define BM_55_06 0x00ffffffffffffc0
+#define BM_06_55 BM_55_06
+#define BM_56_06 0x01ffffffffffffc0
+#define BM_06_56 BM_56_06
+#define BM_57_06 0x03ffffffffffffc0
+#define BM_06_57 BM_57_06
+#define BM_58_06 0x07ffffffffffffc0
+#define BM_06_58 BM_58_06
+#define BM_59_06 0x0fffffffffffffc0
+#define BM_06_59 BM_59_06
+#define BM_60_06 0x1fffffffffffffc0
+#define BM_06_60 BM_60_06
+#define BM_61_06 0x3fffffffffffffc0
+#define BM_06_61 BM_61_06
+#define BM_62_06 0x7fffffffffffffc0
+#define BM_06_62 BM_62_06
+#define BM_63_06 0xffffffffffffffc0
+#define BM_06_63 BM_63_06
+#define BM_07_07 0x0000000000000080
+#define BM_08_07 0x0000000000000180
+#define BM_07_08 BM_08_07
+#define BM_09_07 0x0000000000000380
+#define BM_07_09 BM_09_07
+#define BM_10_07 0x0000000000000780
+#define BM_07_10 BM_10_07
+#define BM_11_07 0x0000000000000f80
+#define BM_07_11 BM_11_07
+#define BM_12_07 0x0000000000001f80
+#define BM_07_12 BM_12_07
+#define BM_13_07 0x0000000000003f80
+#define BM_07_13 BM_13_07
+#define BM_14_07 0x0000000000007f80
+#define BM_07_14 BM_14_07
+#define BM_15_07 0x000000000000ff80
+#define BM_07_15 BM_15_07
+#define BM_16_07 0x000000000001ff80
+#define BM_07_16 BM_16_07
+#define BM_17_07 0x000000000003ff80
+#define BM_07_17 BM_17_07
+#define BM_18_07 0x000000000007ff80
+#define BM_07_18 BM_18_07
+#define BM_19_07 0x00000000000fff80
+#define BM_07_19 BM_19_07
+#define BM_20_07 0x00000000001fff80
+#define BM_07_20 BM_20_07
+#define BM_21_07 0x00000000003fff80
+#define BM_07_21 BM_21_07
+#define BM_22_07 0x00000000007fff80
+#define BM_07_22 BM_22_07
+#define BM_23_07 0x0000000000ffff80
+#define BM_07_23 BM_23_07
+#define BM_24_07 0x0000000001ffff80
+#define BM_07_24 BM_24_07
+#define BM_25_07 0x0000000003ffff80
+#define BM_07_25 BM_25_07
+#define BM_26_07 0x0000000007ffff80
+#define BM_07_26 BM_26_07
+#define BM_27_07 0x000000000fffff80
+#define BM_07_27 BM_27_07
+#define BM_28_07 0x000000001fffff80
+#define BM_07_28 BM_28_07
+#define BM_29_07 0x000000003fffff80
+#define BM_07_29 BM_29_07
+#define BM_30_07 0x000000007fffff80
+#define BM_07_30 BM_30_07
+#define BM_31_07 0x00000000ffffff80
+#define BM_07_31 BM_31_07
+#define BM_32_07 0x00000001ffffff80
+#define BM_07_32 BM_32_07
+#define BM_33_07 0x00000003ffffff80
+#define BM_07_33 BM_33_07
+#define BM_34_07 0x00000007ffffff80
+#define BM_07_34 BM_34_07
+#define BM_35_07 0x0000000fffffff80
+#define BM_07_35 BM_35_07
+#define BM_36_07 0x0000001fffffff80
+#define BM_07_36 BM_36_07
+#define BM_37_07 0x0000003fffffff80
+#define BM_07_37 BM_37_07
+#define BM_38_07 0x0000007fffffff80
+#define BM_07_38 BM_38_07
+#define BM_39_07 0x000000ffffffff80
+#define BM_07_39 BM_39_07
+#define BM_40_07 0x000001ffffffff80
+#define BM_07_40 BM_40_07
+#define BM_41_07 0x000003ffffffff80
+#define BM_07_41 BM_41_07
+#define BM_42_07 0x000007ffffffff80
+#define BM_07_42 BM_42_07
+#define BM_43_07 0x00000fffffffff80
+#define BM_07_43 BM_43_07
+#define BM_44_07 0x00001fffffffff80
+#define BM_07_44 BM_44_07
+#define BM_45_07 0x00003fffffffff80
+#define BM_07_45 BM_45_07
+#define BM_46_07 0x00007fffffffff80
+#define BM_07_46 BM_46_07
+#define BM_47_07 0x0000ffffffffff80
+#define BM_07_47 BM_47_07
+#define BM_48_07 0x0001ffffffffff80
+#define BM_07_48 BM_48_07
+#define BM_49_07 0x0003ffffffffff80
+#define BM_07_49 BM_49_07
+#define BM_50_07 0x0007ffffffffff80
+#define BM_07_50 BM_50_07
+#define BM_51_07 0x000fffffffffff80
+#define BM_07_51 BM_51_07
+#define BM_52_07 0x001fffffffffff80
+#define BM_07_52 BM_52_07
+#define BM_53_07 0x003fffffffffff80
+#define BM_07_53 BM_53_07
+#define BM_54_07 0x007fffffffffff80
+#define BM_07_54 BM_54_07
+#define BM_55_07 0x00ffffffffffff80
+#define BM_07_55 BM_55_07
+#define BM_56_07 0x01ffffffffffff80
+#define BM_07_56 BM_56_07
+#define BM_57_07 0x03ffffffffffff80
+#define BM_07_57 BM_57_07
+#define BM_58_07 0x07ffffffffffff80
+#define BM_07_58 BM_58_07
+#define BM_59_07 0x0fffffffffffff80
+#define BM_07_59 BM_59_07
+#define BM_60_07 0x1fffffffffffff80
+#define BM_07_60 BM_60_07
+#define BM_61_07 0x3fffffffffffff80
+#define BM_07_61 BM_61_07
+#define BM_62_07 0x7fffffffffffff80
+#define BM_07_62 BM_62_07
+#define BM_63_07 0xffffffffffffff80
+#define BM_07_63 BM_63_07
+#define BM_08_08 0x0000000000000100
+#define BM_09_08 0x0000000000000300
+#define BM_08_09 BM_09_08
+#define BM_10_08 0x0000000000000700
+#define BM_08_10 BM_10_08
+#define BM_11_08 0x0000000000000f00
+#define BM_08_11 BM_11_08
+#define BM_12_08 0x0000000000001f00
+#define BM_08_12 BM_12_08
+#define BM_13_08 0x0000000000003f00
+#define BM_08_13 BM_13_08
+#define BM_14_08 0x0000000000007f00
+#define BM_08_14 BM_14_08
+#define BM_15_08 0x000000000000ff00
+#define BM_08_15 BM_15_08
+#define BM_16_08 0x000000000001ff00
+#define BM_08_16 BM_16_08
+#define BM_17_08 0x000000000003ff00
+#define BM_08_17 BM_17_08
+#define BM_18_08 0x000000000007ff00
+#define BM_08_18 BM_18_08
+#define BM_19_08 0x00000000000fff00
+#define BM_08_19 BM_19_08
+#define BM_20_08 0x00000000001fff00
+#define BM_08_20 BM_20_08
+#define BM_21_08 0x00000000003fff00
+#define BM_08_21 BM_21_08
+#define BM_22_08 0x00000000007fff00
+#define BM_08_22 BM_22_08
+#define BM_23_08 0x0000000000ffff00
+#define BM_08_23 BM_23_08
+#define BM_24_08 0x0000000001ffff00
+#define BM_08_24 BM_24_08
+#define BM_25_08 0x0000000003ffff00
+#define BM_08_25 BM_25_08
+#define BM_26_08 0x0000000007ffff00
+#define BM_08_26 BM_26_08
+#define BM_27_08 0x000000000fffff00
+#define BM_08_27 BM_27_08
+#define BM_28_08 0x000000001fffff00
+#define BM_08_28 BM_28_08
+#define BM_29_08 0x000000003fffff00
+#define BM_08_29 BM_29_08
+#define BM_30_08 0x000000007fffff00
+#define BM_08_30 BM_30_08
+#define BM_31_08 0x00000000ffffff00
+#define BM_08_31 BM_31_08
+#define BM_32_08 0x00000001ffffff00
+#define BM_08_32 BM_32_08
+#define BM_33_08 0x00000003ffffff00
+#define BM_08_33 BM_33_08
+#define BM_34_08 0x00000007ffffff00
+#define BM_08_34 BM_34_08
+#define BM_35_08 0x0000000fffffff00
+#define BM_08_35 BM_35_08
+#define BM_36_08 0x0000001fffffff00
+#define BM_08_36 BM_36_08
+#define BM_37_08 0x0000003fffffff00
+#define BM_08_37 BM_37_08
+#define BM_38_08 0x0000007fffffff00
+#define BM_08_38 BM_38_08
+#define BM_39_08 0x000000ffffffff00
+#define BM_08_39 BM_39_08
+#define BM_40_08 0x000001ffffffff00
+#define BM_08_40 BM_40_08
+#define BM_41_08 0x000003ffffffff00
+#define BM_08_41 BM_41_08
+#define BM_42_08 0x000007ffffffff00
+#define BM_08_42 BM_42_08
+#define BM_43_08 0x00000fffffffff00
+#define BM_08_43 BM_43_08
+#define BM_44_08 0x00001fffffffff00
+#define BM_08_44 BM_44_08
+#define BM_45_08 0x00003fffffffff00
+#define BM_08_45 BM_45_08
+#define BM_46_08 0x00007fffffffff00
+#define BM_08_46 BM_46_08
+#define BM_47_08 0x0000ffffffffff00
+#define BM_08_47 BM_47_08
+#define BM_48_08 0x0001ffffffffff00
+#define BM_08_48 BM_48_08
+#define BM_49_08 0x0003ffffffffff00
+#define BM_08_49 BM_49_08
+#define BM_50_08 0x0007ffffffffff00
+#define BM_08_50 BM_50_08
+#define BM_51_08 0x000fffffffffff00
+#define BM_08_51 BM_51_08
+#define BM_52_08 0x001fffffffffff00
+#define BM_08_52 BM_52_08
+#define BM_53_08 0x003fffffffffff00
+#define BM_08_53 BM_53_08
+#define BM_54_08 0x007fffffffffff00
+#define BM_08_54 BM_54_08
+#define BM_55_08 0x00ffffffffffff00
+#define BM_08_55 BM_55_08
+#define BM_56_08 0x01ffffffffffff00
+#define BM_08_56 BM_56_08
+#define BM_57_08 0x03ffffffffffff00
+#define BM_08_57 BM_57_08
+#define BM_58_08 0x07ffffffffffff00
+#define BM_08_58 BM_58_08
+#define BM_59_08 0x0fffffffffffff00
+#define BM_08_59 BM_59_08
+#define BM_60_08 0x1fffffffffffff00
+#define BM_08_60 BM_60_08
+#define BM_61_08 0x3fffffffffffff00
+#define BM_08_61 BM_61_08
+#define BM_62_08 0x7fffffffffffff00
+#define BM_08_62 BM_62_08
+#define BM_63_08 0xffffffffffffff00
+#define BM_08_63 BM_63_08
+#define BM_09_09 0x0000000000000200
+#define BM_10_09 0x0000000000000600
+#define BM_09_10 BM_10_09
+#define BM_11_09 0x0000000000000e00
+#define BM_09_11 BM_11_09
+#define BM_12_09 0x0000000000001e00
+#define BM_09_12 BM_12_09
+#define BM_13_09 0x0000000000003e00
+#define BM_09_13 BM_13_09
+#define BM_14_09 0x0000000000007e00
+#define BM_09_14 BM_14_09
+#define BM_15_09 0x000000000000fe00
+#define BM_09_15 BM_15_09
+#define BM_16_09 0x000000000001fe00
+#define BM_09_16 BM_16_09
+#define BM_17_09 0x000000000003fe00
+#define BM_09_17 BM_17_09
+#define BM_18_09 0x000000000007fe00
+#define BM_09_18 BM_18_09
+#define BM_19_09 0x00000000000ffe00
+#define BM_09_19 BM_19_09
+#define BM_20_09 0x00000000001ffe00
+#define BM_09_20 BM_20_09
+#define BM_21_09 0x00000000003ffe00
+#define BM_09_21 BM_21_09
+#define BM_22_09 0x00000000007ffe00
+#define BM_09_22 BM_22_09
+#define BM_23_09 0x0000000000fffe00
+#define BM_09_23 BM_23_09
+#define BM_24_09 0x0000000001fffe00
+#define BM_09_24 BM_24_09
+#define BM_25_09 0x0000000003fffe00
+#define BM_09_25 BM_25_09
+#define BM_26_09 0x0000000007fffe00
+#define BM_09_26 BM_26_09
+#define BM_27_09 0x000000000ffffe00
+#define BM_09_27 BM_27_09
+#define BM_28_09 0x000000001ffffe00
+#define BM_09_28 BM_28_09
+#define BM_29_09 0x000000003ffffe00
+#define BM_09_29 BM_29_09
+#define BM_30_09 0x000000007ffffe00
+#define BM_09_30 BM_30_09
+#define BM_31_09 0x00000000fffffe00
+#define BM_09_31 BM_31_09
+#define BM_32_09 0x00000001fffffe00
+#define BM_09_32 BM_32_09
+#define BM_33_09 0x00000003fffffe00
+#define BM_09_33 BM_33_09
+#define BM_34_09 0x00000007fffffe00
+#define BM_09_34 BM_34_09
+#define BM_35_09 0x0000000ffffffe00
+#define BM_09_35 BM_35_09
+#define BM_36_09 0x0000001ffffffe00
+#define BM_09_36 BM_36_09
+#define BM_37_09 0x0000003ffffffe00
+#define BM_09_37 BM_37_09
+#define BM_38_09 0x0000007ffffffe00
+#define BM_09_38 BM_38_09
+#define BM_39_09 0x000000fffffffe00
+#define BM_09_39 BM_39_09
+#define BM_40_09 0x000001fffffffe00
+#define BM_09_40 BM_40_09
+#define BM_41_09 0x000003fffffffe00
+#define BM_09_41 BM_41_09
+#define BM_42_09 0x000007fffffffe00
+#define BM_09_42 BM_42_09
+#define BM_43_09 0x00000ffffffffe00
+#define BM_09_43 BM_43_09
+#define BM_44_09 0x00001ffffffffe00
+#define BM_09_44 BM_44_09
+#define BM_45_09 0x00003ffffffffe00
+#define BM_09_45 BM_45_09
+#define BM_46_09 0x00007ffffffffe00
+#define BM_09_46 BM_46_09
+#define BM_47_09 0x0000fffffffffe00
+#define BM_09_47 BM_47_09
+#define BM_48_09 0x0001fffffffffe00
+#define BM_09_48 BM_48_09
+#define BM_49_09 0x0003fffffffffe00
+#define BM_09_49 BM_49_09
+#define BM_50_09 0x0007fffffffffe00
+#define BM_09_50 BM_50_09
+#define BM_51_09 0x000ffffffffffe00
+#define BM_09_51 BM_51_09
+#define BM_52_09 0x001ffffffffffe00
+#define BM_09_52 BM_52_09
+#define BM_53_09 0x003ffffffffffe00
+#define BM_09_53 BM_53_09
+#define BM_54_09 0x007ffffffffffe00
+#define BM_09_54 BM_54_09
+#define BM_55_09 0x00fffffffffffe00
+#define BM_09_55 BM_55_09
+#define BM_56_09 0x01fffffffffffe00
+#define BM_09_56 BM_56_09
+#define BM_57_09 0x03fffffffffffe00
+#define BM_09_57 BM_57_09
+#define BM_58_09 0x07fffffffffffe00
+#define BM_09_58 BM_58_09
+#define BM_59_09 0x0ffffffffffffe00
+#define BM_09_59 BM_59_09
+#define BM_60_09 0x1ffffffffffffe00
+#define BM_09_60 BM_60_09
+#define BM_61_09 0x3ffffffffffffe00
+#define BM_09_61 BM_61_09
+#define BM_62_09 0x7ffffffffffffe00
+#define BM_09_62 BM_62_09
+#define BM_63_09 0xfffffffffffffe00
+#define BM_09_63 BM_63_09
+#define BM_10_10 0x0000000000000400
+#define BM_11_10 0x0000000000000c00
+#define BM_10_11 BM_11_10
+#define BM_12_10 0x0000000000001c00
+#define BM_10_12 BM_12_10
+#define BM_13_10 0x0000000000003c00
+#define BM_10_13 BM_13_10
+#define BM_14_10 0x0000000000007c00
+#define BM_10_14 BM_14_10
+#define BM_15_10 0x000000000000fc00
+#define BM_10_15 BM_15_10
+#define BM_16_10 0x000000000001fc00
+#define BM_10_16 BM_16_10
+#define BM_17_10 0x000000000003fc00
+#define BM_10_17 BM_17_10
+#define BM_18_10 0x000000000007fc00
+#define BM_10_18 BM_18_10
+#define BM_19_10 0x00000000000ffc00
+#define BM_10_19 BM_19_10
+#define BM_20_10 0x00000000001ffc00
+#define BM_10_20 BM_20_10
+#define BM_21_10 0x00000000003ffc00
+#define BM_10_21 BM_21_10
+#define BM_22_10 0x00000000007ffc00
+#define BM_10_22 BM_22_10
+#define BM_23_10 0x0000000000fffc00
+#define BM_10_23 BM_23_10
+#define BM_24_10 0x0000000001fffc00
+#define BM_10_24 BM_24_10
+#define BM_25_10 0x0000000003fffc00
+#define BM_10_25 BM_25_10
+#define BM_26_10 0x0000000007fffc00
+#define BM_10_26 BM_26_10
+#define BM_27_10 0x000000000ffffc00
+#define BM_10_27 BM_27_10
+#define BM_28_10 0x000000001ffffc00
+#define BM_10_28 BM_28_10
+#define BM_29_10 0x000000003ffffc00
+#define BM_10_29 BM_29_10
+#define BM_30_10 0x000000007ffffc00
+#define BM_10_30 BM_30_10
+#define BM_31_10 0x00000000fffffc00
+#define BM_10_31 BM_31_10
+#define BM_32_10 0x00000001fffffc00
+#define BM_10_32 BM_32_10
+#define BM_33_10 0x00000003fffffc00
+#define BM_10_33 BM_33_10
+#define BM_34_10 0x00000007fffffc00
+#define BM_10_34 BM_34_10
+#define BM_35_10 0x0000000ffffffc00
+#define BM_10_35 BM_35_10
+#define BM_36_10 0x0000001ffffffc00
+#define BM_10_36 BM_36_10
+#define BM_37_10 0x0000003ffffffc00
+#define BM_10_37 BM_37_10
+#define BM_38_10 0x0000007ffffffc00
+#define BM_10_38 BM_38_10
+#define BM_39_10 0x000000fffffffc00
+#define BM_10_39 BM_39_10
+#define BM_40_10 0x000001fffffffc00
+#define BM_10_40 BM_40_10
+#define BM_41_10 0x000003fffffffc00
+#define BM_10_41 BM_41_10
+#define BM_42_10 0x000007fffffffc00
+#define BM_10_42 BM_42_10
+#define BM_43_10 0x00000ffffffffc00
+#define BM_10_43 BM_43_10
+#define BM_44_10 0x00001ffffffffc00
+#define BM_10_44 BM_44_10
+#define BM_45_10 0x00003ffffffffc00
+#define BM_10_45 BM_45_10
+#define BM_46_10 0x00007ffffffffc00
+#define BM_10_46 BM_46_10
+#define BM_47_10 0x0000fffffffffc00
+#define BM_10_47 BM_47_10
+#define BM_48_10 0x0001fffffffffc00
+#define BM_10_48 BM_48_10
+#define BM_49_10 0x0003fffffffffc00
+#define BM_10_49 BM_49_10
+#define BM_50_10 0x0007fffffffffc00
+#define BM_10_50 BM_50_10
+#define BM_51_10 0x000ffffffffffc00
+#define BM_10_51 BM_51_10
+#define BM_52_10 0x001ffffffffffc00
+#define BM_10_52 BM_52_10
+#define BM_53_10 0x003ffffffffffc00
+#define BM_10_53 BM_53_10
+#define BM_54_10 0x007ffffffffffc00
+#define BM_10_54 BM_54_10
+#define BM_55_10 0x00fffffffffffc00
+#define BM_10_55 BM_55_10
+#define BM_56_10 0x01fffffffffffc00
+#define BM_10_56 BM_56_10
+#define BM_57_10 0x03fffffffffffc00
+#define BM_10_57 BM_57_10
+#define BM_58_10 0x07fffffffffffc00
+#define BM_10_58 BM_58_10
+#define BM_59_10 0x0ffffffffffffc00
+#define BM_10_59 BM_59_10
+#define BM_60_10 0x1ffffffffffffc00
+#define BM_10_60 BM_60_10
+#define BM_61_10 0x3ffffffffffffc00
+#define BM_10_61 BM_61_10
+#define BM_62_10 0x7ffffffffffffc00
+#define BM_10_62 BM_62_10
+#define BM_63_10 0xfffffffffffffc00
+#define BM_10_63 BM_63_10
+#define BM_11_11 0x0000000000000800
+#define BM_12_11 0x0000000000001800
+#define BM_11_12 BM_12_11
+#define BM_13_11 0x0000000000003800
+#define BM_11_13 BM_13_11
+#define BM_14_11 0x0000000000007800
+#define BM_11_14 BM_14_11
+#define BM_15_11 0x000000000000f800
+#define BM_11_15 BM_15_11
+#define BM_16_11 0x000000000001f800
+#define BM_11_16 BM_16_11
+#define BM_17_11 0x000000000003f800
+#define BM_11_17 BM_17_11
+#define BM_18_11 0x000000000007f800
+#define BM_11_18 BM_18_11
+#define BM_19_11 0x00000000000ff800
+#define BM_11_19 BM_19_11
+#define BM_20_11 0x00000000001ff800
+#define BM_11_20 BM_20_11
+#define BM_21_11 0x00000000003ff800
+#define BM_11_21 BM_21_11
+#define BM_22_11 0x00000000007ff800
+#define BM_11_22 BM_22_11
+#define BM_23_11 0x0000000000fff800
+#define BM_11_23 BM_23_11
+#define BM_24_11 0x0000000001fff800
+#define BM_11_24 BM_24_11
+#define BM_25_11 0x0000000003fff800
+#define BM_11_25 BM_25_11
+#define BM_26_11 0x0000000007fff800
+#define BM_11_26 BM_26_11
+#define BM_27_11 0x000000000ffff800
+#define BM_11_27 BM_27_11
+#define BM_28_11 0x000000001ffff800
+#define BM_11_28 BM_28_11
+#define BM_29_11 0x000000003ffff800
+#define BM_11_29 BM_29_11
+#define BM_30_11 0x000000007ffff800
+#define BM_11_30 BM_30_11
+#define BM_31_11 0x00000000fffff800
+#define BM_11_31 BM_31_11
+#define BM_32_11 0x00000001fffff800
+#define BM_11_32 BM_32_11
+#define BM_33_11 0x00000003fffff800
+#define BM_11_33 BM_33_11
+#define BM_34_11 0x00000007fffff800
+#define BM_11_34 BM_34_11
+#define BM_35_11 0x0000000ffffff800
+#define BM_11_35 BM_35_11
+#define BM_36_11 0x0000001ffffff800
+#define BM_11_36 BM_36_11
+#define BM_37_11 0x0000003ffffff800
+#define BM_11_37 BM_37_11
+#define BM_38_11 0x0000007ffffff800
+#define BM_11_38 BM_38_11
+#define BM_39_11 0x000000fffffff800
+#define BM_11_39 BM_39_11
+#define BM_40_11 0x000001fffffff800
+#define BM_11_40 BM_40_11
+#define BM_41_11 0x000003fffffff800
+#define BM_11_41 BM_41_11
+#define BM_42_11 0x000007fffffff800
+#define BM_11_42 BM_42_11
+#define BM_43_11 0x00000ffffffff800
+#define BM_11_43 BM_43_11
+#define BM_44_11 0x00001ffffffff800
+#define BM_11_44 BM_44_11
+#define BM_45_11 0x00003ffffffff800
+#define BM_11_45 BM_45_11
+#define BM_46_11 0x00007ffffffff800
+#define BM_11_46 BM_46_11
+#define BM_47_11 0x0000fffffffff800
+#define BM_11_47 BM_47_11
+#define BM_48_11 0x0001fffffffff800
+#define BM_11_48 BM_48_11
+#define BM_49_11 0x0003fffffffff800
+#define BM_11_49 BM_49_11
+#define BM_50_11 0x0007fffffffff800
+#define BM_11_50 BM_50_11
+#define BM_51_11 0x000ffffffffff800
+#define BM_11_51 BM_51_11
+#define BM_52_11 0x001ffffffffff800
+#define BM_11_52 BM_52_11
+#define BM_53_11 0x003ffffffffff800
+#define BM_11_53 BM_53_11
+#define BM_54_11 0x007ffffffffff800
+#define BM_11_54 BM_54_11
+#define BM_55_11 0x00fffffffffff800
+#define BM_11_55 BM_55_11
+#define BM_56_11 0x01fffffffffff800
+#define BM_11_56 BM_56_11
+#define BM_57_11 0x03fffffffffff800
+#define BM_11_57 BM_57_11
+#define BM_58_11 0x07fffffffffff800
+#define BM_11_58 BM_58_11
+#define BM_59_11 0x0ffffffffffff800
+#define BM_11_59 BM_59_11
+#define BM_60_11 0x1ffffffffffff800
+#define BM_11_60 BM_60_11
+#define BM_61_11 0x3ffffffffffff800
+#define BM_11_61 BM_61_11
+#define BM_62_11 0x7ffffffffffff800
+#define BM_11_62 BM_62_11
+#define BM_63_11 0xfffffffffffff800
+#define BM_11_63 BM_63_11
+#define BM_12_12 0x0000000000001000
+#define BM_13_12 0x0000000000003000
+#define BM_12_13 BM_13_12
+#define BM_14_12 0x0000000000007000
+#define BM_12_14 BM_14_12
+#define BM_15_12 0x000000000000f000
+#define BM_12_15 BM_15_12
+#define BM_16_12 0x000000000001f000
+#define BM_12_16 BM_16_12
+#define BM_17_12 0x000000000003f000
+#define BM_12_17 BM_17_12
+#define BM_18_12 0x000000000007f000
+#define BM_12_18 BM_18_12
+#define BM_19_12 0x00000000000ff000
+#define BM_12_19 BM_19_12
+#define BM_20_12 0x00000000001ff000
+#define BM_12_20 BM_20_12
+#define BM_21_12 0x00000000003ff000
+#define BM_12_21 BM_21_12
+#define BM_22_12 0x00000000007ff000
+#define BM_12_22 BM_22_12
+#define BM_23_12 0x0000000000fff000
+#define BM_12_23 BM_23_12
+#define BM_24_12 0x0000000001fff000
+#define BM_12_24 BM_24_12
+#define BM_25_12 0x0000000003fff000
+#define BM_12_25 BM_25_12
+#define BM_26_12 0x0000000007fff000
+#define BM_12_26 BM_26_12
+#define BM_27_12 0x000000000ffff000
+#define BM_12_27 BM_27_12
+#define BM_28_12 0x000000001ffff000
+#define BM_12_28 BM_28_12
+#define BM_29_12 0x000000003ffff000
+#define BM_12_29 BM_29_12
+#define BM_30_12 0x000000007ffff000
+#define BM_12_30 BM_30_12
+#define BM_31_12 0x00000000fffff000
+#define BM_12_31 BM_31_12
+#define BM_32_12 0x00000001fffff000
+#define BM_12_32 BM_32_12
+#define BM_33_12 0x00000003fffff000
+#define BM_12_33 BM_33_12
+#define BM_34_12 0x00000007fffff000
+#define BM_12_34 BM_34_12
+#define BM_35_12 0x0000000ffffff000
+#define BM_12_35 BM_35_12
+#define BM_36_12 0x0000001ffffff000
+#define BM_12_36 BM_36_12
+#define BM_37_12 0x0000003ffffff000
+#define BM_12_37 BM_37_12
+#define BM_38_12 0x0000007ffffff000
+#define BM_12_38 BM_38_12
+#define BM_39_12 0x000000fffffff000
+#define BM_12_39 BM_39_12
+#define BM_40_12 0x000001fffffff000
+#define BM_12_40 BM_40_12
+#define BM_41_12 0x000003fffffff000
+#define BM_12_41 BM_41_12
+#define BM_42_12 0x000007fffffff000
+#define BM_12_42 BM_42_12
+#define BM_43_12 0x00000ffffffff000
+#define BM_12_43 BM_43_12
+#define BM_44_12 0x00001ffffffff000
+#define BM_12_44 BM_44_12
+#define BM_45_12 0x00003ffffffff000
+#define BM_12_45 BM_45_12
+#define BM_46_12 0x00007ffffffff000
+#define BM_12_46 BM_46_12
+#define BM_47_12 0x0000fffffffff000
+#define BM_12_47 BM_47_12
+#define BM_48_12 0x0001fffffffff000
+#define BM_12_48 BM_48_12
+#define BM_49_12 0x0003fffffffff000
+#define BM_12_49 BM_49_12
+#define BM_50_12 0x0007fffffffff000
+#define BM_12_50 BM_50_12
+#define BM_51_12 0x000ffffffffff000
+#define BM_12_51 BM_51_12
+#define BM_52_12 0x001ffffffffff000
+#define BM_12_52 BM_52_12
+#define BM_53_12 0x003ffffffffff000
+#define BM_12_53 BM_53_12
+#define BM_54_12 0x007ffffffffff000
+#define BM_12_54 BM_54_12
+#define BM_55_12 0x00fffffffffff000
+#define BM_12_55 BM_55_12
+#define BM_56_12 0x01fffffffffff000
+#define BM_12_56 BM_56_12
+#define BM_57_12 0x03fffffffffff000
+#define BM_12_57 BM_57_12
+#define BM_58_12 0x07fffffffffff000
+#define BM_12_58 BM_58_12
+#define BM_59_12 0x0ffffffffffff000
+#define BM_12_59 BM_59_12
+#define BM_60_12 0x1ffffffffffff000
+#define BM_12_60 BM_60_12
+#define BM_61_12 0x3ffffffffffff000
+#define BM_12_61 BM_61_12
+#define BM_62_12 0x7ffffffffffff000
+#define BM_12_62 BM_62_12
+#define BM_63_12 0xfffffffffffff000
+#define BM_12_63 BM_63_12
+#define BM_13_13 0x0000000000002000
+#define BM_14_13 0x0000000000006000
+#define BM_13_14 BM_14_13
+#define BM_15_13 0x000000000000e000
+#define BM_13_15 BM_15_13
+#define BM_16_13 0x000000000001e000
+#define BM_13_16 BM_16_13
+#define BM_17_13 0x000000000003e000
+#define BM_13_17 BM_17_13
+#define BM_18_13 0x000000000007e000
+#define BM_13_18 BM_18_13
+#define BM_19_13 0x00000000000fe000
+#define BM_13_19 BM_19_13
+#define BM_20_13 0x00000000001fe000
+#define BM_13_20 BM_20_13
+#define BM_21_13 0x00000000003fe000
+#define BM_13_21 BM_21_13
+#define BM_22_13 0x00000000007fe000
+#define BM_13_22 BM_22_13
+#define BM_23_13 0x0000000000ffe000
+#define BM_13_23 BM_23_13
+#define BM_24_13 0x0000000001ffe000
+#define BM_13_24 BM_24_13
+#define BM_25_13 0x0000000003ffe000
+#define BM_13_25 BM_25_13
+#define BM_26_13 0x0000000007ffe000
+#define BM_13_26 BM_26_13
+#define BM_27_13 0x000000000fffe000
+#define BM_13_27 BM_27_13
+#define BM_28_13 0x000000001fffe000
+#define BM_13_28 BM_28_13
+#define BM_29_13 0x000000003fffe000
+#define BM_13_29 BM_29_13
+#define BM_30_13 0x000000007fffe000
+#define BM_13_30 BM_30_13
+#define BM_31_13 0x00000000ffffe000
+#define BM_13_31 BM_31_13
+#define BM_32_13 0x00000001ffffe000
+#define BM_13_32 BM_32_13
+#define BM_33_13 0x00000003ffffe000
+#define BM_13_33 BM_33_13
+#define BM_34_13 0x00000007ffffe000
+#define BM_13_34 BM_34_13
+#define BM_35_13 0x0000000fffffe000
+#define BM_13_35 BM_35_13
+#define BM_36_13 0x0000001fffffe000
+#define BM_13_36 BM_36_13
+#define BM_37_13 0x0000003fffffe000
+#define BM_13_37 BM_37_13
+#define BM_38_13 0x0000007fffffe000
+#define BM_13_38 BM_38_13
+#define BM_39_13 0x000000ffffffe000
+#define BM_13_39 BM_39_13
+#define BM_40_13 0x000001ffffffe000
+#define BM_13_40 BM_40_13
+#define BM_41_13 0x000003ffffffe000
+#define BM_13_41 BM_41_13
+#define BM_42_13 0x000007ffffffe000
+#define BM_13_42 BM_42_13
+#define BM_43_13 0x00000fffffffe000
+#define BM_13_43 BM_43_13
+#define BM_44_13 0x00001fffffffe000
+#define BM_13_44 BM_44_13
+#define BM_45_13 0x00003fffffffe000
+#define BM_13_45 BM_45_13
+#define BM_46_13 0x00007fffffffe000
+#define BM_13_46 BM_46_13
+#define BM_47_13 0x0000ffffffffe000
+#define BM_13_47 BM_47_13
+#define BM_48_13 0x0001ffffffffe000
+#define BM_13_48 BM_48_13
+#define BM_49_13 0x0003ffffffffe000
+#define BM_13_49 BM_49_13
+#define BM_50_13 0x0007ffffffffe000
+#define BM_13_50 BM_50_13
+#define BM_51_13 0x000fffffffffe000
+#define BM_13_51 BM_51_13
+#define BM_52_13 0x001fffffffffe000
+#define BM_13_52 BM_52_13
+#define BM_53_13 0x003fffffffffe000
+#define BM_13_53 BM_53_13
+#define BM_54_13 0x007fffffffffe000
+#define BM_13_54 BM_54_13
+#define BM_55_13 0x00ffffffffffe000
+#define BM_13_55 BM_55_13
+#define BM_56_13 0x01ffffffffffe000
+#define BM_13_56 BM_56_13
+#define BM_57_13 0x03ffffffffffe000
+#define BM_13_57 BM_57_13
+#define BM_58_13 0x07ffffffffffe000
+#define BM_13_58 BM_58_13
+#define BM_59_13 0x0fffffffffffe000
+#define BM_13_59 BM_59_13
+#define BM_60_13 0x1fffffffffffe000
+#define BM_13_60 BM_60_13
+#define BM_61_13 0x3fffffffffffe000
+#define BM_13_61 BM_61_13
+#define BM_62_13 0x7fffffffffffe000
+#define BM_13_62 BM_62_13
+#define BM_63_13 0xffffffffffffe000
+#define BM_13_63 BM_63_13
+#define BM_14_14 0x0000000000004000
+#define BM_15_14 0x000000000000c000
+#define BM_14_15 BM_15_14
+#define BM_16_14 0x000000000001c000
+#define BM_14_16 BM_16_14
+#define BM_17_14 0x000000000003c000
+#define BM_14_17 BM_17_14
+#define BM_18_14 0x000000000007c000
+#define BM_14_18 BM_18_14
+#define BM_19_14 0x00000000000fc000
+#define BM_14_19 BM_19_14
+#define BM_20_14 0x00000000001fc000
+#define BM_14_20 BM_20_14
+#define BM_21_14 0x00000000003fc000
+#define BM_14_21 BM_21_14
+#define BM_22_14 0x00000000007fc000
+#define BM_14_22 BM_22_14
+#define BM_23_14 0x0000000000ffc000
+#define BM_14_23 BM_23_14
+#define BM_24_14 0x0000000001ffc000
+#define BM_14_24 BM_24_14
+#define BM_25_14 0x0000000003ffc000
+#define BM_14_25 BM_25_14
+#define BM_26_14 0x0000000007ffc000
+#define BM_14_26 BM_26_14
+#define BM_27_14 0x000000000fffc000
+#define BM_14_27 BM_27_14
+#define BM_28_14 0x000000001fffc000
+#define BM_14_28 BM_28_14
+#define BM_29_14 0x000000003fffc000
+#define BM_14_29 BM_29_14
+#define BM_30_14 0x000000007fffc000
+#define BM_14_30 BM_30_14
+#define BM_31_14 0x00000000ffffc000
+#define BM_14_31 BM_31_14
+#define BM_32_14 0x00000001ffffc000
+#define BM_14_32 BM_32_14
+#define BM_33_14 0x00000003ffffc000
+#define BM_14_33 BM_33_14
+#define BM_34_14 0x00000007ffffc000
+#define BM_14_34 BM_34_14
+#define BM_35_14 0x0000000fffffc000
+#define BM_14_35 BM_35_14
+#define BM_36_14 0x0000001fffffc000
+#define BM_14_36 BM_36_14
+#define BM_37_14 0x0000003fffffc000
+#define BM_14_37 BM_37_14
+#define BM_38_14 0x0000007fffffc000
+#define BM_14_38 BM_38_14
+#define BM_39_14 0x000000ffffffc000
+#define BM_14_39 BM_39_14
+#define BM_40_14 0x000001ffffffc000
+#define BM_14_40 BM_40_14
+#define BM_41_14 0x000003ffffffc000
+#define BM_14_41 BM_41_14
+#define BM_42_14 0x000007ffffffc000
+#define BM_14_42 BM_42_14
+#define BM_43_14 0x00000fffffffc000
+#define BM_14_43 BM_43_14
+#define BM_44_14 0x00001fffffffc000
+#define BM_14_44 BM_44_14
+#define BM_45_14 0x00003fffffffc000
+#define BM_14_45 BM_45_14
+#define BM_46_14 0x00007fffffffc000
+#define BM_14_46 BM_46_14
+#define BM_47_14 0x0000ffffffffc000
+#define BM_14_47 BM_47_14
+#define BM_48_14 0x0001ffffffffc000
+#define BM_14_48 BM_48_14
+#define BM_49_14 0x0003ffffffffc000
+#define BM_14_49 BM_49_14
+#define BM_50_14 0x0007ffffffffc000
+#define BM_14_50 BM_50_14
+#define BM_51_14 0x000fffffffffc000
+#define BM_14_51 BM_51_14
+#define BM_52_14 0x001fffffffffc000
+#define BM_14_52 BM_52_14
+#define BM_53_14 0x003fffffffffc000
+#define BM_14_53 BM_53_14
+#define BM_54_14 0x007fffffffffc000
+#define BM_14_54 BM_54_14
+#define BM_55_14 0x00ffffffffffc000
+#define BM_14_55 BM_55_14
+#define BM_56_14 0x01ffffffffffc000
+#define BM_14_56 BM_56_14
+#define BM_57_14 0x03ffffffffffc000
+#define BM_14_57 BM_57_14
+#define BM_58_14 0x07ffffffffffc000
+#define BM_14_58 BM_58_14
+#define BM_59_14 0x0fffffffffffc000
+#define BM_14_59 BM_59_14
+#define BM_60_14 0x1fffffffffffc000
+#define BM_14_60 BM_60_14
+#define BM_61_14 0x3fffffffffffc000
+#define BM_14_61 BM_61_14
+#define BM_62_14 0x7fffffffffffc000
+#define BM_14_62 BM_62_14
+#define BM_63_14 0xffffffffffffc000
+#define BM_14_63 BM_63_14
+#define BM_15_15 0x0000000000008000
+#define BM_16_15 0x0000000000018000
+#define BM_15_16 BM_16_15
+#define BM_17_15 0x0000000000038000
+#define BM_15_17 BM_17_15
+#define BM_18_15 0x0000000000078000
+#define BM_15_18 BM_18_15
+#define BM_19_15 0x00000000000f8000
+#define BM_15_19 BM_19_15
+#define BM_20_15 0x00000000001f8000
+#define BM_15_20 BM_20_15
+#define BM_21_15 0x00000000003f8000
+#define BM_15_21 BM_21_15
+#define BM_22_15 0x00000000007f8000
+#define BM_15_22 BM_22_15
+#define BM_23_15 0x0000000000ff8000
+#define BM_15_23 BM_23_15
+#define BM_24_15 0x0000000001ff8000
+#define BM_15_24 BM_24_15
+#define BM_25_15 0x0000000003ff8000
+#define BM_15_25 BM_25_15
+#define BM_26_15 0x0000000007ff8000
+#define BM_15_26 BM_26_15
+#define BM_27_15 0x000000000fff8000
+#define BM_15_27 BM_27_15
+#define BM_28_15 0x000000001fff8000
+#define BM_15_28 BM_28_15
+#define BM_29_15 0x000000003fff8000
+#define BM_15_29 BM_29_15
+#define BM_30_15 0x000000007fff8000
+#define BM_15_30 BM_30_15
+#define BM_31_15 0x00000000ffff8000
+#define BM_15_31 BM_31_15
+#define BM_32_15 0x00000001ffff8000
+#define BM_15_32 BM_32_15
+#define BM_33_15 0x00000003ffff8000
+#define BM_15_33 BM_33_15
+#define BM_34_15 0x00000007ffff8000
+#define BM_15_34 BM_34_15
+#define BM_35_15 0x0000000fffff8000
+#define BM_15_35 BM_35_15
+#define BM_36_15 0x0000001fffff8000
+#define BM_15_36 BM_36_15
+#define BM_37_15 0x0000003fffff8000
+#define BM_15_37 BM_37_15
+#define BM_38_15 0x0000007fffff8000
+#define BM_15_38 BM_38_15
+#define BM_39_15 0x000000ffffff8000
+#define BM_15_39 BM_39_15
+#define BM_40_15 0x000001ffffff8000
+#define BM_15_40 BM_40_15
+#define BM_41_15 0x000003ffffff8000
+#define BM_15_41 BM_41_15
+#define BM_42_15 0x000007ffffff8000
+#define BM_15_42 BM_42_15
+#define BM_43_15 0x00000fffffff8000
+#define BM_15_43 BM_43_15
+#define BM_44_15 0x00001fffffff8000
+#define BM_15_44 BM_44_15
+#define BM_45_15 0x00003fffffff8000
+#define BM_15_45 BM_45_15
+#define BM_46_15 0x00007fffffff8000
+#define BM_15_46 BM_46_15
+#define BM_47_15 0x0000ffffffff8000
+#define BM_15_47 BM_47_15
+#define BM_48_15 0x0001ffffffff8000
+#define BM_15_48 BM_48_15
+#define BM_49_15 0x0003ffffffff8000
+#define BM_15_49 BM_49_15
+#define BM_50_15 0x0007ffffffff8000
+#define BM_15_50 BM_50_15
+#define BM_51_15 0x000fffffffff8000
+#define BM_15_51 BM_51_15
+#define BM_52_15 0x001fffffffff8000
+#define BM_15_52 BM_52_15
+#define BM_53_15 0x003fffffffff8000
+#define BM_15_53 BM_53_15
+#define BM_54_15 0x007fffffffff8000
+#define BM_15_54 BM_54_15
+#define BM_55_15 0x00ffffffffff8000
+#define BM_15_55 BM_55_15
+#define BM_56_15 0x01ffffffffff8000
+#define BM_15_56 BM_56_15
+#define BM_57_15 0x03ffffffffff8000
+#define BM_15_57 BM_57_15
+#define BM_58_15 0x07ffffffffff8000
+#define BM_15_58 BM_58_15
+#define BM_59_15 0x0fffffffffff8000
+#define BM_15_59 BM_59_15
+#define BM_60_15 0x1fffffffffff8000
+#define BM_15_60 BM_60_15
+#define BM_61_15 0x3fffffffffff8000
+#define BM_15_61 BM_61_15
+#define BM_62_15 0x7fffffffffff8000
+#define BM_15_62 BM_62_15
+#define BM_63_15 0xffffffffffff8000
+#define BM_15_63 BM_63_15
+#define BM_16_16 0x0000000000010000
+#define BM_17_16 0x0000000000030000
+#define BM_16_17 BM_17_16
+#define BM_18_16 0x0000000000070000
+#define BM_16_18 BM_18_16
+#define BM_19_16 0x00000000000f0000
+#define BM_16_19 BM_19_16
+#define BM_20_16 0x00000000001f0000
+#define BM_16_20 BM_20_16
+#define BM_21_16 0x00000000003f0000
+#define BM_16_21 BM_21_16
+#define BM_22_16 0x00000000007f0000
+#define BM_16_22 BM_22_16
+#define BM_23_16 0x0000000000ff0000
+#define BM_16_23 BM_23_16
+#define BM_24_16 0x0000000001ff0000
+#define BM_16_24 BM_24_16
+#define BM_25_16 0x0000000003ff0000
+#define BM_16_25 BM_25_16
+#define BM_26_16 0x0000000007ff0000
+#define BM_16_26 BM_26_16
+#define BM_27_16 0x000000000fff0000
+#define BM_16_27 BM_27_16
+#define BM_28_16 0x000000001fff0000
+#define BM_16_28 BM_28_16
+#define BM_29_16 0x000000003fff0000
+#define BM_16_29 BM_29_16
+#define BM_30_16 0x000000007fff0000
+#define BM_16_30 BM_30_16
+#define BM_31_16 0x00000000ffff0000
+#define BM_16_31 BM_31_16
+#define BM_32_16 0x00000001ffff0000
+#define BM_16_32 BM_32_16
+#define BM_33_16 0x00000003ffff0000
+#define BM_16_33 BM_33_16
+#define BM_34_16 0x00000007ffff0000
+#define BM_16_34 BM_34_16
+#define BM_35_16 0x0000000fffff0000
+#define BM_16_35 BM_35_16
+#define BM_36_16 0x0000001fffff0000
+#define BM_16_36 BM_36_16
+#define BM_37_16 0x0000003fffff0000
+#define BM_16_37 BM_37_16
+#define BM_38_16 0x0000007fffff0000
+#define BM_16_38 BM_38_16
+#define BM_39_16 0x000000ffffff0000
+#define BM_16_39 BM_39_16
+#define BM_40_16 0x000001ffffff0000
+#define BM_16_40 BM_40_16
+#define BM_41_16 0x000003ffffff0000
+#define BM_16_41 BM_41_16
+#define BM_42_16 0x000007ffffff0000
+#define BM_16_42 BM_42_16
+#define BM_43_16 0x00000fffffff0000
+#define BM_16_43 BM_43_16
+#define BM_44_16 0x00001fffffff0000
+#define BM_16_44 BM_44_16
+#define BM_45_16 0x00003fffffff0000
+#define BM_16_45 BM_45_16
+#define BM_46_16 0x00007fffffff0000
+#define BM_16_46 BM_46_16
+#define BM_47_16 0x0000ffffffff0000
+#define BM_16_47 BM_47_16
+#define BM_48_16 0x0001ffffffff0000
+#define BM_16_48 BM_48_16
+#define BM_49_16 0x0003ffffffff0000
+#define BM_16_49 BM_49_16
+#define BM_50_16 0x0007ffffffff0000
+#define BM_16_50 BM_50_16
+#define BM_51_16 0x000fffffffff0000
+#define BM_16_51 BM_51_16
+#define BM_52_16 0x001fffffffff0000
+#define BM_16_52 BM_52_16
+#define BM_53_16 0x003fffffffff0000
+#define BM_16_53 BM_53_16
+#define BM_54_16 0x007fffffffff0000
+#define BM_16_54 BM_54_16
+#define BM_55_16 0x00ffffffffff0000
+#define BM_16_55 BM_55_16
+#define BM_56_16 0x01ffffffffff0000
+#define BM_16_56 BM_56_16
+#define BM_57_16 0x03ffffffffff0000
+#define BM_16_57 BM_57_16
+#define BM_58_16 0x07ffffffffff0000
+#define BM_16_58 BM_58_16
+#define BM_59_16 0x0fffffffffff0000
+#define BM_16_59 BM_59_16
+#define BM_60_16 0x1fffffffffff0000
+#define BM_16_60 BM_60_16
+#define BM_61_16 0x3fffffffffff0000
+#define BM_16_61 BM_61_16
+#define BM_62_16 0x7fffffffffff0000
+#define BM_16_62 BM_62_16
+#define BM_63_16 0xffffffffffff0000
+#define BM_16_63 BM_63_16
+#define BM_17_17 0x0000000000020000
+#define BM_18_17 0x0000000000060000
+#define BM_17_18 BM_18_17
+#define BM_19_17 0x00000000000e0000
+#define BM_17_19 BM_19_17
+#define BM_20_17 0x00000000001e0000
+#define BM_17_20 BM_20_17
+#define BM_21_17 0x00000000003e0000
+#define BM_17_21 BM_21_17
+#define BM_22_17 0x00000000007e0000
+#define BM_17_22 BM_22_17
+#define BM_23_17 0x0000000000fe0000
+#define BM_17_23 BM_23_17
+#define BM_24_17 0x0000000001fe0000
+#define BM_17_24 BM_24_17
+#define BM_25_17 0x0000000003fe0000
+#define BM_17_25 BM_25_17
+#define BM_26_17 0x0000000007fe0000
+#define BM_17_26 BM_26_17
+#define BM_27_17 0x000000000ffe0000
+#define BM_17_27 BM_27_17
+#define BM_28_17 0x000000001ffe0000
+#define BM_17_28 BM_28_17
+#define BM_29_17 0x000000003ffe0000
+#define BM_17_29 BM_29_17
+#define BM_30_17 0x000000007ffe0000
+#define BM_17_30 BM_30_17
+#define BM_31_17 0x00000000fffe0000
+#define BM_17_31 BM_31_17
+#define BM_32_17 0x00000001fffe0000
+#define BM_17_32 BM_32_17
+#define BM_33_17 0x00000003fffe0000
+#define BM_17_33 BM_33_17
+#define BM_34_17 0x00000007fffe0000
+#define BM_17_34 BM_34_17
+#define BM_35_17 0x0000000ffffe0000
+#define BM_17_35 BM_35_17
+#define BM_36_17 0x0000001ffffe0000
+#define BM_17_36 BM_36_17
+#define BM_37_17 0x0000003ffffe0000
+#define BM_17_37 BM_37_17
+#define BM_38_17 0x0000007ffffe0000
+#define BM_17_38 BM_38_17
+#define BM_39_17 0x000000fffffe0000
+#define BM_17_39 BM_39_17
+#define BM_40_17 0x000001fffffe0000
+#define BM_17_40 BM_40_17
+#define BM_41_17 0x000003fffffe0000
+#define BM_17_41 BM_41_17
+#define BM_42_17 0x000007fffffe0000
+#define BM_17_42 BM_42_17
+#define BM_43_17 0x00000ffffffe0000
+#define BM_17_43 BM_43_17
+#define BM_44_17 0x00001ffffffe0000
+#define BM_17_44 BM_44_17
+#define BM_45_17 0x00003ffffffe0000
+#define BM_17_45 BM_45_17
+#define BM_46_17 0x00007ffffffe0000
+#define BM_17_46 BM_46_17
+#define BM_47_17 0x0000fffffffe0000
+#define BM_17_47 BM_47_17
+#define BM_48_17 0x0001fffffffe0000
+#define BM_17_48 BM_48_17
+#define BM_49_17 0x0003fffffffe0000
+#define BM_17_49 BM_49_17
+#define BM_50_17 0x0007fffffffe0000
+#define BM_17_50 BM_50_17
+#define BM_51_17 0x000ffffffffe0000
+#define BM_17_51 BM_51_17
+#define BM_52_17 0x001ffffffffe0000
+#define BM_17_52 BM_52_17
+#define BM_53_17 0x003ffffffffe0000
+#define BM_17_53 BM_53_17
+#define BM_54_17 0x007ffffffffe0000
+#define BM_17_54 BM_54_17
+#define BM_55_17 0x00fffffffffe0000
+#define BM_17_55 BM_55_17
+#define BM_56_17 0x01fffffffffe0000
+#define BM_17_56 BM_56_17
+#define BM_57_17 0x03fffffffffe0000
+#define BM_17_57 BM_57_17
+#define BM_58_17 0x07fffffffffe0000
+#define BM_17_58 BM_58_17
+#define BM_59_17 0x0ffffffffffe0000
+#define BM_17_59 BM_59_17
+#define BM_60_17 0x1ffffffffffe0000
+#define BM_17_60 BM_60_17
+#define BM_61_17 0x3ffffffffffe0000
+#define BM_17_61 BM_61_17
+#define BM_62_17 0x7ffffffffffe0000
+#define BM_17_62 BM_62_17
+#define BM_63_17 0xfffffffffffe0000
+#define BM_17_63 BM_63_17
+#define BM_18_18 0x0000000000040000
+#define BM_19_18 0x00000000000c0000
+#define BM_18_19 BM_19_18
+#define BM_20_18 0x00000000001c0000
+#define BM_18_20 BM_20_18
+#define BM_21_18 0x00000000003c0000
+#define BM_18_21 BM_21_18
+#define BM_22_18 0x00000000007c0000
+#define BM_18_22 BM_22_18
+#define BM_23_18 0x0000000000fc0000
+#define BM_18_23 BM_23_18
+#define BM_24_18 0x0000000001fc0000
+#define BM_18_24 BM_24_18
+#define BM_25_18 0x0000000003fc0000
+#define BM_18_25 BM_25_18
+#define BM_26_18 0x0000000007fc0000
+#define BM_18_26 BM_26_18
+#define BM_27_18 0x000000000ffc0000
+#define BM_18_27 BM_27_18
+#define BM_28_18 0x000000001ffc0000
+#define BM_18_28 BM_28_18
+#define BM_29_18 0x000000003ffc0000
+#define BM_18_29 BM_29_18
+#define BM_30_18 0x000000007ffc0000
+#define BM_18_30 BM_30_18
+#define BM_31_18 0x00000000fffc0000
+#define BM_18_31 BM_31_18
+#define BM_32_18 0x00000001fffc0000
+#define BM_18_32 BM_32_18
+#define BM_33_18 0x00000003fffc0000
+#define BM_18_33 BM_33_18
+#define BM_34_18 0x00000007fffc0000
+#define BM_18_34 BM_34_18
+#define BM_35_18 0x0000000ffffc0000
+#define BM_18_35 BM_35_18
+#define BM_36_18 0x0000001ffffc0000
+#define BM_18_36 BM_36_18
+#define BM_37_18 0x0000003ffffc0000
+#define BM_18_37 BM_37_18
+#define BM_38_18 0x0000007ffffc0000
+#define BM_18_38 BM_38_18
+#define BM_39_18 0x000000fffffc0000
+#define BM_18_39 BM_39_18
+#define BM_40_18 0x000001fffffc0000
+#define BM_18_40 BM_40_18
+#define BM_41_18 0x000003fffffc0000
+#define BM_18_41 BM_41_18
+#define BM_42_18 0x000007fffffc0000
+#define BM_18_42 BM_42_18
+#define BM_43_18 0x00000ffffffc0000
+#define BM_18_43 BM_43_18
+#define BM_44_18 0x00001ffffffc0000
+#define BM_18_44 BM_44_18
+#define BM_45_18 0x00003ffffffc0000
+#define BM_18_45 BM_45_18
+#define BM_46_18 0x00007ffffffc0000
+#define BM_18_46 BM_46_18
+#define BM_47_18 0x0000fffffffc0000
+#define BM_18_47 BM_47_18
+#define BM_48_18 0x0001fffffffc0000
+#define BM_18_48 BM_48_18
+#define BM_49_18 0x0003fffffffc0000
+#define BM_18_49 BM_49_18
+#define BM_50_18 0x0007fffffffc0000
+#define BM_18_50 BM_50_18
+#define BM_51_18 0x000ffffffffc0000
+#define BM_18_51 BM_51_18
+#define BM_52_18 0x001ffffffffc0000
+#define BM_18_52 BM_52_18
+#define BM_53_18 0x003ffffffffc0000
+#define BM_18_53 BM_53_18
+#define BM_54_18 0x007ffffffffc0000
+#define BM_18_54 BM_54_18
+#define BM_55_18 0x00fffffffffc0000
+#define BM_18_55 BM_55_18
+#define BM_56_18 0x01fffffffffc0000
+#define BM_18_56 BM_56_18
+#define BM_57_18 0x03fffffffffc0000
+#define BM_18_57 BM_57_18
+#define BM_58_18 0x07fffffffffc0000
+#define BM_18_58 BM_58_18
+#define BM_59_18 0x0ffffffffffc0000
+#define BM_18_59 BM_59_18
+#define BM_60_18 0x1ffffffffffc0000
+#define BM_18_60 BM_60_18
+#define BM_61_18 0x3ffffffffffc0000
+#define BM_18_61 BM_61_18
+#define BM_62_18 0x7ffffffffffc0000
+#define BM_18_62 BM_62_18
+#define BM_63_18 0xfffffffffffc0000
+#define BM_18_63 BM_63_18
+#define BM_19_19 0x0000000000080000
+#define BM_20_19 0x0000000000180000
+#define BM_19_20 BM_20_19
+#define BM_21_19 0x0000000000380000
+#define BM_19_21 BM_21_19
+#define BM_22_19 0x0000000000780000
+#define BM_19_22 BM_22_19
+#define BM_23_19 0x0000000000f80000
+#define BM_19_23 BM_23_19
+#define BM_24_19 0x0000000001f80000
+#define BM_19_24 BM_24_19
+#define BM_25_19 0x0000000003f80000
+#define BM_19_25 BM_25_19
+#define BM_26_19 0x0000000007f80000
+#define BM_19_26 BM_26_19
+#define BM_27_19 0x000000000ff80000
+#define BM_19_27 BM_27_19
+#define BM_28_19 0x000000001ff80000
+#define BM_19_28 BM_28_19
+#define BM_29_19 0x000000003ff80000
+#define BM_19_29 BM_29_19
+#define BM_30_19 0x000000007ff80000
+#define BM_19_30 BM_30_19
+#define BM_31_19 0x00000000fff80000
+#define BM_19_31 BM_31_19
+#define BM_32_19 0x00000001fff80000
+#define BM_19_32 BM_32_19
+#define BM_33_19 0x00000003fff80000
+#define BM_19_33 BM_33_19
+#define BM_34_19 0x00000007fff80000
+#define BM_19_34 BM_34_19
+#define BM_35_19 0x0000000ffff80000
+#define BM_19_35 BM_35_19
+#define BM_36_19 0x0000001ffff80000
+#define BM_19_36 BM_36_19
+#define BM_37_19 0x0000003ffff80000
+#define BM_19_37 BM_37_19
+#define BM_38_19 0x0000007ffff80000
+#define BM_19_38 BM_38_19
+#define BM_39_19 0x000000fffff80000
+#define BM_19_39 BM_39_19
+#define BM_40_19 0x000001fffff80000
+#define BM_19_40 BM_40_19
+#define BM_41_19 0x000003fffff80000
+#define BM_19_41 BM_41_19
+#define BM_42_19 0x000007fffff80000
+#define BM_19_42 BM_42_19
+#define BM_43_19 0x00000ffffff80000
+#define BM_19_43 BM_43_19
+#define BM_44_19 0x00001ffffff80000
+#define BM_19_44 BM_44_19
+#define BM_45_19 0x00003ffffff80000
+#define BM_19_45 BM_45_19
+#define BM_46_19 0x00007ffffff80000
+#define BM_19_46 BM_46_19
+#define BM_47_19 0x0000fffffff80000
+#define BM_19_47 BM_47_19
+#define BM_48_19 0x0001fffffff80000
+#define BM_19_48 BM_48_19
+#define BM_49_19 0x0003fffffff80000
+#define BM_19_49 BM_49_19
+#define BM_50_19 0x0007fffffff80000
+#define BM_19_50 BM_50_19
+#define BM_51_19 0x000ffffffff80000
+#define BM_19_51 BM_51_19
+#define BM_52_19 0x001ffffffff80000
+#define BM_19_52 BM_52_19
+#define BM_53_19 0x003ffffffff80000
+#define BM_19_53 BM_53_19
+#define BM_54_19 0x007ffffffff80000
+#define BM_19_54 BM_54_19
+#define BM_55_19 0x00fffffffff80000
+#define BM_19_55 BM_55_19
+#define BM_56_19 0x01fffffffff80000
+#define BM_19_56 BM_56_19
+#define BM_57_19 0x03fffffffff80000
+#define BM_19_57 BM_57_19
+#define BM_58_19 0x07fffffffff80000
+#define BM_19_58 BM_58_19
+#define BM_59_19 0x0ffffffffff80000
+#define BM_19_59 BM_59_19
+#define BM_60_19 0x1ffffffffff80000
+#define BM_19_60 BM_60_19
+#define BM_61_19 0x3ffffffffff80000
+#define BM_19_61 BM_61_19
+#define BM_62_19 0x7ffffffffff80000
+#define BM_19_62 BM_62_19
+#define BM_63_19 0xfffffffffff80000
+#define BM_19_63 BM_63_19
+#define BM_20_20 0x0000000000100000
+#define BM_21_20 0x0000000000300000
+#define BM_20_21 BM_21_20
+#define BM_22_20 0x0000000000700000
+#define BM_20_22 BM_22_20
+#define BM_23_20 0x0000000000f00000
+#define BM_20_23 BM_23_20
+#define BM_24_20 0x0000000001f00000
+#define BM_20_24 BM_24_20
+#define BM_25_20 0x0000000003f00000
+#define BM_20_25 BM_25_20
+#define BM_26_20 0x0000000007f00000
+#define BM_20_26 BM_26_20
+#define BM_27_20 0x000000000ff00000
+#define BM_20_27 BM_27_20
+#define BM_28_20 0x000000001ff00000
+#define BM_20_28 BM_28_20
+#define BM_29_20 0x000000003ff00000
+#define BM_20_29 BM_29_20
+#define BM_30_20 0x000000007ff00000
+#define BM_20_30 BM_30_20
+#define BM_31_20 0x00000000fff00000
+#define BM_20_31 BM_31_20
+#define BM_32_20 0x00000001fff00000
+#define BM_20_32 BM_32_20
+#define BM_33_20 0x00000003fff00000
+#define BM_20_33 BM_33_20
+#define BM_34_20 0x00000007fff00000
+#define BM_20_34 BM_34_20
+#define BM_35_20 0x0000000ffff00000
+#define BM_20_35 BM_35_20
+#define BM_36_20 0x0000001ffff00000
+#define BM_20_36 BM_36_20
+#define BM_37_20 0x0000003ffff00000
+#define BM_20_37 BM_37_20
+#define BM_38_20 0x0000007ffff00000
+#define BM_20_38 BM_38_20
+#define BM_39_20 0x000000fffff00000
+#define BM_20_39 BM_39_20
+#define BM_40_20 0x000001fffff00000
+#define BM_20_40 BM_40_20
+#define BM_41_20 0x000003fffff00000
+#define BM_20_41 BM_41_20
+#define BM_42_20 0x000007fffff00000
+#define BM_20_42 BM_42_20
+#define BM_43_20 0x00000ffffff00000
+#define BM_20_43 BM_43_20
+#define BM_44_20 0x00001ffffff00000
+#define BM_20_44 BM_44_20
+#define BM_45_20 0x00003ffffff00000
+#define BM_20_45 BM_45_20
+#define BM_46_20 0x00007ffffff00000
+#define BM_20_46 BM_46_20
+#define BM_47_20 0x0000fffffff00000
+#define BM_20_47 BM_47_20
+#define BM_48_20 0x0001fffffff00000
+#define BM_20_48 BM_48_20
+#define BM_49_20 0x0003fffffff00000
+#define BM_20_49 BM_49_20
+#define BM_50_20 0x0007fffffff00000
+#define BM_20_50 BM_50_20
+#define BM_51_20 0x000ffffffff00000
+#define BM_20_51 BM_51_20
+#define BM_52_20 0x001ffffffff00000
+#define BM_20_52 BM_52_20
+#define BM_53_20 0x003ffffffff00000
+#define BM_20_53 BM_53_20
+#define BM_54_20 0x007ffffffff00000
+#define BM_20_54 BM_54_20
+#define BM_55_20 0x00fffffffff00000
+#define BM_20_55 BM_55_20
+#define BM_56_20 0x01fffffffff00000
+#define BM_20_56 BM_56_20
+#define BM_57_20 0x03fffffffff00000
+#define BM_20_57 BM_57_20
+#define BM_58_20 0x07fffffffff00000
+#define BM_20_58 BM_58_20
+#define BM_59_20 0x0ffffffffff00000
+#define BM_20_59 BM_59_20
+#define BM_60_20 0x1ffffffffff00000
+#define BM_20_60 BM_60_20
+#define BM_61_20 0x3ffffffffff00000
+#define BM_20_61 BM_61_20
+#define BM_62_20 0x7ffffffffff00000
+#define BM_20_62 BM_62_20
+#define BM_63_20 0xfffffffffff00000
+#define BM_20_63 BM_63_20
+#define BM_21_21 0x0000000000200000
+#define BM_22_21 0x0000000000600000
+#define BM_21_22 BM_22_21
+#define BM_23_21 0x0000000000e00000
+#define BM_21_23 BM_23_21
+#define BM_24_21 0x0000000001e00000
+#define BM_21_24 BM_24_21
+#define BM_25_21 0x0000000003e00000
+#define BM_21_25 BM_25_21
+#define BM_26_21 0x0000000007e00000
+#define BM_21_26 BM_26_21
+#define BM_27_21 0x000000000fe00000
+#define BM_21_27 BM_27_21
+#define BM_28_21 0x000000001fe00000
+#define BM_21_28 BM_28_21
+#define BM_29_21 0x000000003fe00000
+#define BM_21_29 BM_29_21
+#define BM_30_21 0x000000007fe00000
+#define BM_21_30 BM_30_21
+#define BM_31_21 0x00000000ffe00000
+#define BM_21_31 BM_31_21
+#define BM_32_21 0x00000001ffe00000
+#define BM_21_32 BM_32_21
+#define BM_33_21 0x00000003ffe00000
+#define BM_21_33 BM_33_21
+#define BM_34_21 0x00000007ffe00000
+#define BM_21_34 BM_34_21
+#define BM_35_21 0x0000000fffe00000
+#define BM_21_35 BM_35_21
+#define BM_36_21 0x0000001fffe00000
+#define BM_21_36 BM_36_21
+#define BM_37_21 0x0000003fffe00000
+#define BM_21_37 BM_37_21
+#define BM_38_21 0x0000007fffe00000
+#define BM_21_38 BM_38_21
+#define BM_39_21 0x000000ffffe00000
+#define BM_21_39 BM_39_21
+#define BM_40_21 0x000001ffffe00000
+#define BM_21_40 BM_40_21
+#define BM_41_21 0x000003ffffe00000
+#define BM_21_41 BM_41_21
+#define BM_42_21 0x000007ffffe00000
+#define BM_21_42 BM_42_21
+#define BM_43_21 0x00000fffffe00000
+#define BM_21_43 BM_43_21
+#define BM_44_21 0x00001fffffe00000
+#define BM_21_44 BM_44_21
+#define BM_45_21 0x00003fffffe00000
+#define BM_21_45 BM_45_21
+#define BM_46_21 0x00007fffffe00000
+#define BM_21_46 BM_46_21
+#define BM_47_21 0x0000ffffffe00000
+#define BM_21_47 BM_47_21
+#define BM_48_21 0x0001ffffffe00000
+#define BM_21_48 BM_48_21
+#define BM_49_21 0x0003ffffffe00000
+#define BM_21_49 BM_49_21
+#define BM_50_21 0x0007ffffffe00000
+#define BM_21_50 BM_50_21
+#define BM_51_21 0x000fffffffe00000
+#define BM_21_51 BM_51_21
+#define BM_52_21 0x001fffffffe00000
+#define BM_21_52 BM_52_21
+#define BM_53_21 0x003fffffffe00000
+#define BM_21_53 BM_53_21
+#define BM_54_21 0x007fffffffe00000
+#define BM_21_54 BM_54_21
+#define BM_55_21 0x00ffffffffe00000
+#define BM_21_55 BM_55_21
+#define BM_56_21 0x01ffffffffe00000
+#define BM_21_56 BM_56_21
+#define BM_57_21 0x03ffffffffe00000
+#define BM_21_57 BM_57_21
+#define BM_58_21 0x07ffffffffe00000
+#define BM_21_58 BM_58_21
+#define BM_59_21 0x0fffffffffe00000
+#define BM_21_59 BM_59_21
+#define BM_60_21 0x1fffffffffe00000
+#define BM_21_60 BM_60_21
+#define BM_61_21 0x3fffffffffe00000
+#define BM_21_61 BM_61_21
+#define BM_62_21 0x7fffffffffe00000
+#define BM_21_62 BM_62_21
+#define BM_63_21 0xffffffffffe00000
+#define BM_21_63 BM_63_21
+#define BM_22_22 0x0000000000400000
+#define BM_23_22 0x0000000000c00000
+#define BM_22_23 BM_23_22
+#define BM_24_22 0x0000000001c00000
+#define BM_22_24 BM_24_22
+#define BM_25_22 0x0000000003c00000
+#define BM_22_25 BM_25_22
+#define BM_26_22 0x0000000007c00000
+#define BM_22_26 BM_26_22
+#define BM_27_22 0x000000000fc00000
+#define BM_22_27 BM_27_22
+#define BM_28_22 0x000000001fc00000
+#define BM_22_28 BM_28_22
+#define BM_29_22 0x000000003fc00000
+#define BM_22_29 BM_29_22
+#define BM_30_22 0x000000007fc00000
+#define BM_22_30 BM_30_22
+#define BM_31_22 0x00000000ffc00000
+#define BM_22_31 BM_31_22
+#define BM_32_22 0x00000001ffc00000
+#define BM_22_32 BM_32_22
+#define BM_33_22 0x00000003ffc00000
+#define BM_22_33 BM_33_22
+#define BM_34_22 0x00000007ffc00000
+#define BM_22_34 BM_34_22
+#define BM_35_22 0x0000000fffc00000
+#define BM_22_35 BM_35_22
+#define BM_36_22 0x0000001fffc00000
+#define BM_22_36 BM_36_22
+#define BM_37_22 0x0000003fffc00000
+#define BM_22_37 BM_37_22
+#define BM_38_22 0x0000007fffc00000
+#define BM_22_38 BM_38_22
+#define BM_39_22 0x000000ffffc00000
+#define BM_22_39 BM_39_22
+#define BM_40_22 0x000001ffffc00000
+#define BM_22_40 BM_40_22
+#define BM_41_22 0x000003ffffc00000
+#define BM_22_41 BM_41_22
+#define BM_42_22 0x000007ffffc00000
+#define BM_22_42 BM_42_22
+#define BM_43_22 0x00000fffffc00000
+#define BM_22_43 BM_43_22
+#define BM_44_22 0x00001fffffc00000
+#define BM_22_44 BM_44_22
+#define BM_45_22 0x00003fffffc00000
+#define BM_22_45 BM_45_22
+#define BM_46_22 0x00007fffffc00000
+#define BM_22_46 BM_46_22
+#define BM_47_22 0x0000ffffffc00000
+#define BM_22_47 BM_47_22
+#define BM_48_22 0x0001ffffffc00000
+#define BM_22_48 BM_48_22
+#define BM_49_22 0x0003ffffffc00000
+#define BM_22_49 BM_49_22
+#define BM_50_22 0x0007ffffffc00000
+#define BM_22_50 BM_50_22
+#define BM_51_22 0x000fffffffc00000
+#define BM_22_51 BM_51_22
+#define BM_52_22 0x001fffffffc00000
+#define BM_22_52 BM_52_22
+#define BM_53_22 0x003fffffffc00000
+#define BM_22_53 BM_53_22
+#define BM_54_22 0x007fffffffc00000
+#define BM_22_54 BM_54_22
+#define BM_55_22 0x00ffffffffc00000
+#define BM_22_55 BM_55_22
+#define BM_56_22 0x01ffffffffc00000
+#define BM_22_56 BM_56_22
+#define BM_57_22 0x03ffffffffc00000
+#define BM_22_57 BM_57_22
+#define BM_58_22 0x07ffffffffc00000
+#define BM_22_58 BM_58_22
+#define BM_59_22 0x0fffffffffc00000
+#define BM_22_59 BM_59_22
+#define BM_60_22 0x1fffffffffc00000
+#define BM_22_60 BM_60_22
+#define BM_61_22 0x3fffffffffc00000
+#define BM_22_61 BM_61_22
+#define BM_62_22 0x7fffffffffc00000
+#define BM_22_62 BM_62_22
+#define BM_63_22 0xffffffffffc00000
+#define BM_22_63 BM_63_22
+#define BM_23_23 0x0000000000800000
+#define BM_24_23 0x0000000001800000
+#define BM_23_24 BM_24_23
+#define BM_25_23 0x0000000003800000
+#define BM_23_25 BM_25_23
+#define BM_26_23 0x0000000007800000
+#define BM_23_26 BM_26_23
+#define BM_27_23 0x000000000f800000
+#define BM_23_27 BM_27_23
+#define BM_28_23 0x000000001f800000
+#define BM_23_28 BM_28_23
+#define BM_29_23 0x000000003f800000
+#define BM_23_29 BM_29_23
+#define BM_30_23 0x000000007f800000
+#define BM_23_30 BM_30_23
+#define BM_31_23 0x00000000ff800000
+#define BM_23_31 BM_31_23
+#define BM_32_23 0x00000001ff800000
+#define BM_23_32 BM_32_23
+#define BM_33_23 0x00000003ff800000
+#define BM_23_33 BM_33_23
+#define BM_34_23 0x00000007ff800000
+#define BM_23_34 BM_34_23
+#define BM_35_23 0x0000000fff800000
+#define BM_23_35 BM_35_23
+#define BM_36_23 0x0000001fff800000
+#define BM_23_36 BM_36_23
+#define BM_37_23 0x0000003fff800000
+#define BM_23_37 BM_37_23
+#define BM_38_23 0x0000007fff800000
+#define BM_23_38 BM_38_23
+#define BM_39_23 0x000000ffff800000
+#define BM_23_39 BM_39_23
+#define BM_40_23 0x000001ffff800000
+#define BM_23_40 BM_40_23
+#define BM_41_23 0x000003ffff800000
+#define BM_23_41 BM_41_23
+#define BM_42_23 0x000007ffff800000
+#define BM_23_42 BM_42_23
+#define BM_43_23 0x00000fffff800000
+#define BM_23_43 BM_43_23
+#define BM_44_23 0x00001fffff800000
+#define BM_23_44 BM_44_23
+#define BM_45_23 0x00003fffff800000
+#define BM_23_45 BM_45_23
+#define BM_46_23 0x00007fffff800000
+#define BM_23_46 BM_46_23
+#define BM_47_23 0x0000ffffff800000
+#define BM_23_47 BM_47_23
+#define BM_48_23 0x0001ffffff800000
+#define BM_23_48 BM_48_23
+#define BM_49_23 0x0003ffffff800000
+#define BM_23_49 BM_49_23
+#define BM_50_23 0x0007ffffff800000
+#define BM_23_50 BM_50_23
+#define BM_51_23 0x000fffffff800000
+#define BM_23_51 BM_51_23
+#define BM_52_23 0x001fffffff800000
+#define BM_23_52 BM_52_23
+#define BM_53_23 0x003fffffff800000
+#define BM_23_53 BM_53_23
+#define BM_54_23 0x007fffffff800000
+#define BM_23_54 BM_54_23
+#define BM_55_23 0x00ffffffff800000
+#define BM_23_55 BM_55_23
+#define BM_56_23 0x01ffffffff800000
+#define BM_23_56 BM_56_23
+#define BM_57_23 0x03ffffffff800000
+#define BM_23_57 BM_57_23
+#define BM_58_23 0x07ffffffff800000
+#define BM_23_58 BM_58_23
+#define BM_59_23 0x0fffffffff800000
+#define BM_23_59 BM_59_23
+#define BM_60_23 0x1fffffffff800000
+#define BM_23_60 BM_60_23
+#define BM_61_23 0x3fffffffff800000
+#define BM_23_61 BM_61_23
+#define BM_62_23 0x7fffffffff800000
+#define BM_23_62 BM_62_23
+#define BM_63_23 0xffffffffff800000
+#define BM_23_63 BM_63_23
+#define BM_24_24 0x0000000001000000
+#define BM_25_24 0x0000000003000000
+#define BM_24_25 BM_25_24
+#define BM_26_24 0x0000000007000000
+#define BM_24_26 BM_26_24
+#define BM_27_24 0x000000000f000000
+#define BM_24_27 BM_27_24
+#define BM_28_24 0x000000001f000000
+#define BM_24_28 BM_28_24
+#define BM_29_24 0x000000003f000000
+#define BM_24_29 BM_29_24
+#define BM_30_24 0x000000007f000000
+#define BM_24_30 BM_30_24
+#define BM_31_24 0x00000000ff000000
+#define BM_24_31 BM_31_24
+#define BM_32_24 0x00000001ff000000
+#define BM_24_32 BM_32_24
+#define BM_33_24 0x00000003ff000000
+#define BM_24_33 BM_33_24
+#define BM_34_24 0x00000007ff000000
+#define BM_24_34 BM_34_24
+#define BM_35_24 0x0000000fff000000
+#define BM_24_35 BM_35_24
+#define BM_36_24 0x0000001fff000000
+#define BM_24_36 BM_36_24
+#define BM_37_24 0x0000003fff000000
+#define BM_24_37 BM_37_24
+#define BM_38_24 0x0000007fff000000
+#define BM_24_38 BM_38_24
+#define BM_39_24 0x000000ffff000000
+#define BM_24_39 BM_39_24
+#define BM_40_24 0x000001ffff000000
+#define BM_24_40 BM_40_24
+#define BM_41_24 0x000003ffff000000
+#define BM_24_41 BM_41_24
+#define BM_42_24 0x000007ffff000000
+#define BM_24_42 BM_42_24
+#define BM_43_24 0x00000fffff000000
+#define BM_24_43 BM_43_24
+#define BM_44_24 0x00001fffff000000
+#define BM_24_44 BM_44_24
+#define BM_45_24 0x00003fffff000000
+#define BM_24_45 BM_45_24
+#define BM_46_24 0x00007fffff000000
+#define BM_24_46 BM_46_24
+#define BM_47_24 0x0000ffffff000000
+#define BM_24_47 BM_47_24
+#define BM_48_24 0x0001ffffff000000
+#define BM_24_48 BM_48_24
+#define BM_49_24 0x0003ffffff000000
+#define BM_24_49 BM_49_24
+#define BM_50_24 0x0007ffffff000000
+#define BM_24_50 BM_50_24
+#define BM_51_24 0x000fffffff000000
+#define BM_24_51 BM_51_24
+#define BM_52_24 0x001fffffff000000
+#define BM_24_52 BM_52_24
+#define BM_53_24 0x003fffffff000000
+#define BM_24_53 BM_53_24
+#define BM_54_24 0x007fffffff000000
+#define BM_24_54 BM_54_24
+#define BM_55_24 0x00ffffffff000000
+#define BM_24_55 BM_55_24
+#define BM_56_24 0x01ffffffff000000
+#define BM_24_56 BM_56_24
+#define BM_57_24 0x03ffffffff000000
+#define BM_24_57 BM_57_24
+#define BM_58_24 0x07ffffffff000000
+#define BM_24_58 BM_58_24
+#define BM_59_24 0x0fffffffff000000
+#define BM_24_59 BM_59_24
+#define BM_60_24 0x1fffffffff000000
+#define BM_24_60 BM_60_24
+#define BM_61_24 0x3fffffffff000000
+#define BM_24_61 BM_61_24
+#define BM_62_24 0x7fffffffff000000
+#define BM_24_62 BM_62_24
+#define BM_63_24 0xffffffffff000000
+#define BM_24_63 BM_63_24
+#define BM_25_25 0x0000000002000000
+#define BM_26_25 0x0000000006000000
+#define BM_25_26 BM_26_25
+#define BM_27_25 0x000000000e000000
+#define BM_25_27 BM_27_25
+#define BM_28_25 0x000000001e000000
+#define BM_25_28 BM_28_25
+#define BM_29_25 0x000000003e000000
+#define BM_25_29 BM_29_25
+#define BM_30_25 0x000000007e000000
+#define BM_25_30 BM_30_25
+#define BM_31_25 0x00000000fe000000
+#define BM_25_31 BM_31_25
+#define BM_32_25 0x00000001fe000000
+#define BM_25_32 BM_32_25
+#define BM_33_25 0x00000003fe000000
+#define BM_25_33 BM_33_25
+#define BM_34_25 0x00000007fe000000
+#define BM_25_34 BM_34_25
+#define BM_35_25 0x0000000ffe000000
+#define BM_25_35 BM_35_25
+#define BM_36_25 0x0000001ffe000000
+#define BM_25_36 BM_36_25
+#define BM_37_25 0x0000003ffe000000
+#define BM_25_37 BM_37_25
+#define BM_38_25 0x0000007ffe000000
+#define BM_25_38 BM_38_25
+#define BM_39_25 0x000000fffe000000
+#define BM_25_39 BM_39_25
+#define BM_40_25 0x000001fffe000000
+#define BM_25_40 BM_40_25
+#define BM_41_25 0x000003fffe000000
+#define BM_25_41 BM_41_25
+#define BM_42_25 0x000007fffe000000
+#define BM_25_42 BM_42_25
+#define BM_43_25 0x00000ffffe000000
+#define BM_25_43 BM_43_25
+#define BM_44_25 0x00001ffffe000000
+#define BM_25_44 BM_44_25
+#define BM_45_25 0x00003ffffe000000
+#define BM_25_45 BM_45_25
+#define BM_46_25 0x00007ffffe000000
+#define BM_25_46 BM_46_25
+#define BM_47_25 0x0000fffffe000000
+#define BM_25_47 BM_47_25
+#define BM_48_25 0x0001fffffe000000
+#define BM_25_48 BM_48_25
+#define BM_49_25 0x0003fffffe000000
+#define BM_25_49 BM_49_25
+#define BM_50_25 0x0007fffffe000000
+#define BM_25_50 BM_50_25
+#define BM_51_25 0x000ffffffe000000
+#define BM_25_51 BM_51_25
+#define BM_52_25 0x001ffffffe000000
+#define BM_25_52 BM_52_25
+#define BM_53_25 0x003ffffffe000000
+#define BM_25_53 BM_53_25
+#define BM_54_25 0x007ffffffe000000
+#define BM_25_54 BM_54_25
+#define BM_55_25 0x00fffffffe000000
+#define BM_25_55 BM_55_25
+#define BM_56_25 0x01fffffffe000000
+#define BM_25_56 BM_56_25
+#define BM_57_25 0x03fffffffe000000
+#define BM_25_57 BM_57_25
+#define BM_58_25 0x07fffffffe000000
+#define BM_25_58 BM_58_25
+#define BM_59_25 0x0ffffffffe000000
+#define BM_25_59 BM_59_25
+#define BM_60_25 0x1ffffffffe000000
+#define BM_25_60 BM_60_25
+#define BM_61_25 0x3ffffffffe000000
+#define BM_25_61 BM_61_25
+#define BM_62_25 0x7ffffffffe000000
+#define BM_25_62 BM_62_25
+#define BM_63_25 0xfffffffffe000000
+#define BM_25_63 BM_63_25
+#define BM_26_26 0x0000000004000000
+#define BM_27_26 0x000000000c000000
+#define BM_26_27 BM_27_26
+#define BM_28_26 0x000000001c000000
+#define BM_26_28 BM_28_26
+#define BM_29_26 0x000000003c000000
+#define BM_26_29 BM_29_26
+#define BM_30_26 0x000000007c000000
+#define BM_26_30 BM_30_26
+#define BM_31_26 0x00000000fc000000
+#define BM_26_31 BM_31_26
+#define BM_32_26 0x00000001fc000000
+#define BM_26_32 BM_32_26
+#define BM_33_26 0x00000003fc000000
+#define BM_26_33 BM_33_26
+#define BM_34_26 0x00000007fc000000
+#define BM_26_34 BM_34_26
+#define BM_35_26 0x0000000ffc000000
+#define BM_26_35 BM_35_26
+#define BM_36_26 0x0000001ffc000000
+#define BM_26_36 BM_36_26
+#define BM_37_26 0x0000003ffc000000
+#define BM_26_37 BM_37_26
+#define BM_38_26 0x0000007ffc000000
+#define BM_26_38 BM_38_26
+#define BM_39_26 0x000000fffc000000
+#define BM_26_39 BM_39_26
+#define BM_40_26 0x000001fffc000000
+#define BM_26_40 BM_40_26
+#define BM_41_26 0x000003fffc000000
+#define BM_26_41 BM_41_26
+#define BM_42_26 0x000007fffc000000
+#define BM_26_42 BM_42_26
+#define BM_43_26 0x00000ffffc000000
+#define BM_26_43 BM_43_26
+#define BM_44_26 0x00001ffffc000000
+#define BM_26_44 BM_44_26
+#define BM_45_26 0x00003ffffc000000
+#define BM_26_45 BM_45_26
+#define BM_46_26 0x00007ffffc000000
+#define BM_26_46 BM_46_26
+#define BM_47_26 0x0000fffffc000000
+#define BM_26_47 BM_47_26
+#define BM_48_26 0x0001fffffc000000
+#define BM_26_48 BM_48_26
+#define BM_49_26 0x0003fffffc000000
+#define BM_26_49 BM_49_26
+#define BM_50_26 0x0007fffffc000000
+#define BM_26_50 BM_50_26
+#define BM_51_26 0x000ffffffc000000
+#define BM_26_51 BM_51_26
+#define BM_52_26 0x001ffffffc000000
+#define BM_26_52 BM_52_26
+#define BM_53_26 0x003ffffffc000000
+#define BM_26_53 BM_53_26
+#define BM_54_26 0x007ffffffc000000
+#define BM_26_54 BM_54_26
+#define BM_55_26 0x00fffffffc000000
+#define BM_26_55 BM_55_26
+#define BM_56_26 0x01fffffffc000000
+#define BM_26_56 BM_56_26
+#define BM_57_26 0x03fffffffc000000
+#define BM_26_57 BM_57_26
+#define BM_58_26 0x07fffffffc000000
+#define BM_26_58 BM_58_26
+#define BM_59_26 0x0ffffffffc000000
+#define BM_26_59 BM_59_26
+#define BM_60_26 0x1ffffffffc000000
+#define BM_26_60 BM_60_26
+#define BM_61_26 0x3ffffffffc000000
+#define BM_26_61 BM_61_26
+#define BM_62_26 0x7ffffffffc000000
+#define BM_26_62 BM_62_26
+#define BM_63_26 0xfffffffffc000000
+#define BM_26_63 BM_63_26
+#define BM_27_27 0x0000000008000000
+#define BM_28_27 0x0000000018000000
+#define BM_27_28 BM_28_27
+#define BM_29_27 0x0000000038000000
+#define BM_27_29 BM_29_27
+#define BM_30_27 0x0000000078000000
+#define BM_27_30 BM_30_27
+#define BM_31_27 0x00000000f8000000
+#define BM_27_31 BM_31_27
+#define BM_32_27 0x00000001f8000000
+#define BM_27_32 BM_32_27
+#define BM_33_27 0x00000003f8000000
+#define BM_27_33 BM_33_27
+#define BM_34_27 0x00000007f8000000
+#define BM_27_34 BM_34_27
+#define BM_35_27 0x0000000ff8000000
+#define BM_27_35 BM_35_27
+#define BM_36_27 0x0000001ff8000000
+#define BM_27_36 BM_36_27
+#define BM_37_27 0x0000003ff8000000
+#define BM_27_37 BM_37_27
+#define BM_38_27 0x0000007ff8000000
+#define BM_27_38 BM_38_27
+#define BM_39_27 0x000000fff8000000
+#define BM_27_39 BM_39_27
+#define BM_40_27 0x000001fff8000000
+#define BM_27_40 BM_40_27
+#define BM_41_27 0x000003fff8000000
+#define BM_27_41 BM_41_27
+#define BM_42_27 0x000007fff8000000
+#define BM_27_42 BM_42_27
+#define BM_43_27 0x00000ffff8000000
+#define BM_27_43 BM_43_27
+#define BM_44_27 0x00001ffff8000000
+#define BM_27_44 BM_44_27
+#define BM_45_27 0x00003ffff8000000
+#define BM_27_45 BM_45_27
+#define BM_46_27 0x00007ffff8000000
+#define BM_27_46 BM_46_27
+#define BM_47_27 0x0000fffff8000000
+#define BM_27_47 BM_47_27
+#define BM_48_27 0x0001fffff8000000
+#define BM_27_48 BM_48_27
+#define BM_49_27 0x0003fffff8000000
+#define BM_27_49 BM_49_27
+#define BM_50_27 0x0007fffff8000000
+#define BM_27_50 BM_50_27
+#define BM_51_27 0x000ffffff8000000
+#define BM_27_51 BM_51_27
+#define BM_52_27 0x001ffffff8000000
+#define BM_27_52 BM_52_27
+#define BM_53_27 0x003ffffff8000000
+#define BM_27_53 BM_53_27
+#define BM_54_27 0x007ffffff8000000
+#define BM_27_54 BM_54_27
+#define BM_55_27 0x00fffffff8000000
+#define BM_27_55 BM_55_27
+#define BM_56_27 0x01fffffff8000000
+#define BM_27_56 BM_56_27
+#define BM_57_27 0x03fffffff8000000
+#define BM_27_57 BM_57_27
+#define BM_58_27 0x07fffffff8000000
+#define BM_27_58 BM_58_27
+#define BM_59_27 0x0ffffffff8000000
+#define BM_27_59 BM_59_27
+#define BM_60_27 0x1ffffffff8000000
+#define BM_27_60 BM_60_27
+#define BM_61_27 0x3ffffffff8000000
+#define BM_27_61 BM_61_27
+#define BM_62_27 0x7ffffffff8000000
+#define BM_27_62 BM_62_27
+#define BM_63_27 0xfffffffff8000000
+#define BM_27_63 BM_63_27
+#define BM_28_28 0x0000000010000000
+#define BM_29_28 0x0000000030000000
+#define BM_28_29 BM_29_28
+#define BM_30_28 0x0000000070000000
+#define BM_28_30 BM_30_28
+#define BM_31_28 0x00000000f0000000
+#define BM_28_31 BM_31_28
+#define BM_32_28 0x00000001f0000000
+#define BM_28_32 BM_32_28
+#define BM_33_28 0x00000003f0000000
+#define BM_28_33 BM_33_28
+#define BM_34_28 0x00000007f0000000
+#define BM_28_34 BM_34_28
+#define BM_35_28 0x0000000ff0000000
+#define BM_28_35 BM_35_28
+#define BM_36_28 0x0000001ff0000000
+#define BM_28_36 BM_36_28
+#define BM_37_28 0x0000003ff0000000
+#define BM_28_37 BM_37_28
+#define BM_38_28 0x0000007ff0000000
+#define BM_28_38 BM_38_28
+#define BM_39_28 0x000000fff0000000
+#define BM_28_39 BM_39_28
+#define BM_40_28 0x000001fff0000000
+#define BM_28_40 BM_40_28
+#define BM_41_28 0x000003fff0000000
+#define BM_28_41 BM_41_28
+#define BM_42_28 0x000007fff0000000
+#define BM_28_42 BM_42_28
+#define BM_43_28 0x00000ffff0000000
+#define BM_28_43 BM_43_28
+#define BM_44_28 0x00001ffff0000000
+#define BM_28_44 BM_44_28
+#define BM_45_28 0x00003ffff0000000
+#define BM_28_45 BM_45_28
+#define BM_46_28 0x00007ffff0000000
+#define BM_28_46 BM_46_28
+#define BM_47_28 0x0000fffff0000000
+#define BM_28_47 BM_47_28
+#define BM_48_28 0x0001fffff0000000
+#define BM_28_48 BM_48_28
+#define BM_49_28 0x0003fffff0000000
+#define BM_28_49 BM_49_28
+#define BM_50_28 0x0007fffff0000000
+#define BM_28_50 BM_50_28
+#define BM_51_28 0x000ffffff0000000
+#define BM_28_51 BM_51_28
+#define BM_52_28 0x001ffffff0000000
+#define BM_28_52 BM_52_28
+#define BM_53_28 0x003ffffff0000000
+#define BM_28_53 BM_53_28
+#define BM_54_28 0x007ffffff0000000
+#define BM_28_54 BM_54_28
+#define BM_55_28 0x00fffffff0000000
+#define BM_28_55 BM_55_28
+#define BM_56_28 0x01fffffff0000000
+#define BM_28_56 BM_56_28
+#define BM_57_28 0x03fffffff0000000
+#define BM_28_57 BM_57_28
+#define BM_58_28 0x07fffffff0000000
+#define BM_28_58 BM_58_28
+#define BM_59_28 0x0ffffffff0000000
+#define BM_28_59 BM_59_28
+#define BM_60_28 0x1ffffffff0000000
+#define BM_28_60 BM_60_28
+#define BM_61_28 0x3ffffffff0000000
+#define BM_28_61 BM_61_28
+#define BM_62_28 0x7ffffffff0000000
+#define BM_28_62 BM_62_28
+#define BM_63_28 0xfffffffff0000000
+#define BM_28_63 BM_63_28
+#define BM_29_29 0x0000000020000000
+#define BM_30_29 0x0000000060000000
+#define BM_29_30 BM_30_29
+#define BM_31_29 0x00000000e0000000
+#define BM_29_31 BM_31_29
+#define BM_32_29 0x00000001e0000000
+#define BM_29_32 BM_32_29
+#define BM_33_29 0x00000003e0000000
+#define BM_29_33 BM_33_29
+#define BM_34_29 0x00000007e0000000
+#define BM_29_34 BM_34_29
+#define BM_35_29 0x0000000fe0000000
+#define BM_29_35 BM_35_29
+#define BM_36_29 0x0000001fe0000000
+#define BM_29_36 BM_36_29
+#define BM_37_29 0x0000003fe0000000
+#define BM_29_37 BM_37_29
+#define BM_38_29 0x0000007fe0000000
+#define BM_29_38 BM_38_29
+#define BM_39_29 0x000000ffe0000000
+#define BM_29_39 BM_39_29
+#define BM_40_29 0x000001ffe0000000
+#define BM_29_40 BM_40_29
+#define BM_41_29 0x000003ffe0000000
+#define BM_29_41 BM_41_29
+#define BM_42_29 0x000007ffe0000000
+#define BM_29_42 BM_42_29
+#define BM_43_29 0x00000fffe0000000
+#define BM_29_43 BM_43_29
+#define BM_44_29 0x00001fffe0000000
+#define BM_29_44 BM_44_29
+#define BM_45_29 0x00003fffe0000000
+#define BM_29_45 BM_45_29
+#define BM_46_29 0x00007fffe0000000
+#define BM_29_46 BM_46_29
+#define BM_47_29 0x0000ffffe0000000
+#define BM_29_47 BM_47_29
+#define BM_48_29 0x0001ffffe0000000
+#define BM_29_48 BM_48_29
+#define BM_49_29 0x0003ffffe0000000
+#define BM_29_49 BM_49_29
+#define BM_50_29 0x0007ffffe0000000
+#define BM_29_50 BM_50_29
+#define BM_51_29 0x000fffffe0000000
+#define BM_29_51 BM_51_29
+#define BM_52_29 0x001fffffe0000000
+#define BM_29_52 BM_52_29
+#define BM_53_29 0x003fffffe0000000
+#define BM_29_53 BM_53_29
+#define BM_54_29 0x007fffffe0000000
+#define BM_29_54 BM_54_29
+#define BM_55_29 0x00ffffffe0000000
+#define BM_29_55 BM_55_29
+#define BM_56_29 0x01ffffffe0000000
+#define BM_29_56 BM_56_29
+#define BM_57_29 0x03ffffffe0000000
+#define BM_29_57 BM_57_29
+#define BM_58_29 0x07ffffffe0000000
+#define BM_29_58 BM_58_29
+#define BM_59_29 0x0fffffffe0000000
+#define BM_29_59 BM_59_29
+#define BM_60_29 0x1fffffffe0000000
+#define BM_29_60 BM_60_29
+#define BM_61_29 0x3fffffffe0000000
+#define BM_29_61 BM_61_29
+#define BM_62_29 0x7fffffffe0000000
+#define BM_29_62 BM_62_29
+#define BM_63_29 0xffffffffe0000000
+#define BM_29_63 BM_63_29
+#define BM_30_30 0x0000000040000000
+#define BM_31_30 0x00000000c0000000
+#define BM_30_31 BM_31_30
+#define BM_32_30 0x00000001c0000000
+#define BM_30_32 BM_32_30
+#define BM_33_30 0x00000003c0000000
+#define BM_30_33 BM_33_30
+#define BM_34_30 0x00000007c0000000
+#define BM_30_34 BM_34_30
+#define BM_35_30 0x0000000fc0000000
+#define BM_30_35 BM_35_30
+#define BM_36_30 0x0000001fc0000000
+#define BM_30_36 BM_36_30
+#define BM_37_30 0x0000003fc0000000
+#define BM_30_37 BM_37_30
+#define BM_38_30 0x0000007fc0000000
+#define BM_30_38 BM_38_30
+#define BM_39_30 0x000000ffc0000000
+#define BM_30_39 BM_39_30
+#define BM_40_30 0x000001ffc0000000
+#define BM_30_40 BM_40_30
+#define BM_41_30 0x000003ffc0000000
+#define BM_30_41 BM_41_30
+#define BM_42_30 0x000007ffc0000000
+#define BM_30_42 BM_42_30
+#define BM_43_30 0x00000fffc0000000
+#define BM_30_43 BM_43_30
+#define BM_44_30 0x00001fffc0000000
+#define BM_30_44 BM_44_30
+#define BM_45_30 0x00003fffc0000000
+#define BM_30_45 BM_45_30
+#define BM_46_30 0x00007fffc0000000
+#define BM_30_46 BM_46_30
+#define BM_47_30 0x0000ffffc0000000
+#define BM_30_47 BM_47_30
+#define BM_48_30 0x0001ffffc0000000
+#define BM_30_48 BM_48_30
+#define BM_49_30 0x0003ffffc0000000
+#define BM_30_49 BM_49_30
+#define BM_50_30 0x0007ffffc0000000
+#define BM_30_50 BM_50_30
+#define BM_51_30 0x000fffffc0000000
+#define BM_30_51 BM_51_30
+#define BM_52_30 0x001fffffc0000000
+#define BM_30_52 BM_52_30
+#define BM_53_30 0x003fffffc0000000
+#define BM_30_53 BM_53_30
+#define BM_54_30 0x007fffffc0000000
+#define BM_30_54 BM_54_30
+#define BM_55_30 0x00ffffffc0000000
+#define BM_30_55 BM_55_30
+#define BM_56_30 0x01ffffffc0000000
+#define BM_30_56 BM_56_30
+#define BM_57_30 0x03ffffffc0000000
+#define BM_30_57 BM_57_30
+#define BM_58_30 0x07ffffffc0000000
+#define BM_30_58 BM_58_30
+#define BM_59_30 0x0fffffffc0000000
+#define BM_30_59 BM_59_30
+#define BM_60_30 0x1fffffffc0000000
+#define BM_30_60 BM_60_30
+#define BM_61_30 0x3fffffffc0000000
+#define BM_30_61 BM_61_30
+#define BM_62_30 0x7fffffffc0000000
+#define BM_30_62 BM_62_30
+#define BM_63_30 0xffffffffc0000000
+#define BM_30_63 BM_63_30
+#define BM_31_31 0x0000000080000000
+#define BM_32_31 0x0000000180000000
+#define BM_31_32 BM_32_31
+#define BM_33_31 0x0000000380000000
+#define BM_31_33 BM_33_31
+#define BM_34_31 0x0000000780000000
+#define BM_31_34 BM_34_31
+#define BM_35_31 0x0000000f80000000
+#define BM_31_35 BM_35_31
+#define BM_36_31 0x0000001f80000000
+#define BM_31_36 BM_36_31
+#define BM_37_31 0x0000003f80000000
+#define BM_31_37 BM_37_31
+#define BM_38_31 0x0000007f80000000
+#define BM_31_38 BM_38_31
+#define BM_39_31 0x000000ff80000000
+#define BM_31_39 BM_39_31
+#define BM_40_31 0x000001ff80000000
+#define BM_31_40 BM_40_31
+#define BM_41_31 0x000003ff80000000
+#define BM_31_41 BM_41_31
+#define BM_42_31 0x000007ff80000000
+#define BM_31_42 BM_42_31
+#define BM_43_31 0x00000fff80000000
+#define BM_31_43 BM_43_31
+#define BM_44_31 0x00001fff80000000
+#define BM_31_44 BM_44_31
+#define BM_45_31 0x00003fff80000000
+#define BM_31_45 BM_45_31
+#define BM_46_31 0x00007fff80000000
+#define BM_31_46 BM_46_31
+#define BM_47_31 0x0000ffff80000000
+#define BM_31_47 BM_47_31
+#define BM_48_31 0x0001ffff80000000
+#define BM_31_48 BM_48_31
+#define BM_49_31 0x0003ffff80000000
+#define BM_31_49 BM_49_31
+#define BM_50_31 0x0007ffff80000000
+#define BM_31_50 BM_50_31
+#define BM_51_31 0x000fffff80000000
+#define BM_31_51 BM_51_31
+#define BM_52_31 0x001fffff80000000
+#define BM_31_52 BM_52_31
+#define BM_53_31 0x003fffff80000000
+#define BM_31_53 BM_53_31
+#define BM_54_31 0x007fffff80000000
+#define BM_31_54 BM_54_31
+#define BM_55_31 0x00ffffff80000000
+#define BM_31_55 BM_55_31
+#define BM_56_31 0x01ffffff80000000
+#define BM_31_56 BM_56_31
+#define BM_57_31 0x03ffffff80000000
+#define BM_31_57 BM_57_31
+#define BM_58_31 0x07ffffff80000000
+#define BM_31_58 BM_58_31
+#define BM_59_31 0x0fffffff80000000
+#define BM_31_59 BM_59_31
+#define BM_60_31 0x1fffffff80000000
+#define BM_31_60 BM_60_31
+#define BM_61_31 0x3fffffff80000000
+#define BM_31_61 BM_61_31
+#define BM_62_31 0x7fffffff80000000
+#define BM_31_62 BM_62_31
+#define BM_63_31 0xffffffff80000000
+#define BM_31_63 BM_63_31
+#define BM_32_32 0x0000000100000000
+#define BM_33_32 0x0000000300000000
+#define BM_32_33 BM_33_32
+#define BM_34_32 0x0000000700000000
+#define BM_32_34 BM_34_32
+#define BM_35_32 0x0000000f00000000
+#define BM_32_35 BM_35_32
+#define BM_36_32 0x0000001f00000000
+#define BM_32_36 BM_36_32
+#define BM_37_32 0x0000003f00000000
+#define BM_32_37 BM_37_32
+#define BM_38_32 0x0000007f00000000
+#define BM_32_38 BM_38_32
+#define BM_39_32 0x000000ff00000000
+#define BM_32_39 BM_39_32
+#define BM_40_32 0x000001ff00000000
+#define BM_32_40 BM_40_32
+#define BM_41_32 0x000003ff00000000
+#define BM_32_41 BM_41_32
+#define BM_42_32 0x000007ff00000000
+#define BM_32_42 BM_42_32
+#define BM_43_32 0x00000fff00000000
+#define BM_32_43 BM_43_32
+#define BM_44_32 0x00001fff00000000
+#define BM_32_44 BM_44_32
+#define BM_45_32 0x00003fff00000000
+#define BM_32_45 BM_45_32
+#define BM_46_32 0x00007fff00000000
+#define BM_32_46 BM_46_32
+#define BM_47_32 0x0000ffff00000000
+#define BM_32_47 BM_47_32
+#define BM_48_32 0x0001ffff00000000
+#define BM_32_48 BM_48_32
+#define BM_49_32 0x0003ffff00000000
+#define BM_32_49 BM_49_32
+#define BM_50_32 0x0007ffff00000000
+#define BM_32_50 BM_50_32
+#define BM_51_32 0x000fffff00000000
+#define BM_32_51 BM_51_32
+#define BM_52_32 0x001fffff00000000
+#define BM_32_52 BM_52_32
+#define BM_53_32 0x003fffff00000000
+#define BM_32_53 BM_53_32
+#define BM_54_32 0x007fffff00000000
+#define BM_32_54 BM_54_32
+#define BM_55_32 0x00ffffff00000000
+#define BM_32_55 BM_55_32
+#define BM_56_32 0x01ffffff00000000
+#define BM_32_56 BM_56_32
+#define BM_57_32 0x03ffffff00000000
+#define BM_32_57 BM_57_32
+#define BM_58_32 0x07ffffff00000000
+#define BM_32_58 BM_58_32
+#define BM_59_32 0x0fffffff00000000
+#define BM_32_59 BM_59_32
+#define BM_60_32 0x1fffffff00000000
+#define BM_32_60 BM_60_32
+#define BM_61_32 0x3fffffff00000000
+#define BM_32_61 BM_61_32
+#define BM_62_32 0x7fffffff00000000
+#define BM_32_62 BM_62_32
+#define BM_63_32 0xffffffff00000000
+#define BM_32_63 BM_63_32
+#define BM_33_33 0x0000000200000000
+#define BM_34_33 0x0000000600000000
+#define BM_33_34 BM_34_33
+#define BM_35_33 0x0000000e00000000
+#define BM_33_35 BM_35_33
+#define BM_36_33 0x0000001e00000000
+#define BM_33_36 BM_36_33
+#define BM_37_33 0x0000003e00000000
+#define BM_33_37 BM_37_33
+#define BM_38_33 0x0000007e00000000
+#define BM_33_38 BM_38_33
+#define BM_39_33 0x000000fe00000000
+#define BM_33_39 BM_39_33
+#define BM_40_33 0x000001fe00000000
+#define BM_33_40 BM_40_33
+#define BM_41_33 0x000003fe00000000
+#define BM_33_41 BM_41_33
+#define BM_42_33 0x000007fe00000000
+#define BM_33_42 BM_42_33
+#define BM_43_33 0x00000ffe00000000
+#define BM_33_43 BM_43_33
+#define BM_44_33 0x00001ffe00000000
+#define BM_33_44 BM_44_33
+#define BM_45_33 0x00003ffe00000000
+#define BM_33_45 BM_45_33
+#define BM_46_33 0x00007ffe00000000
+#define BM_33_46 BM_46_33
+#define BM_47_33 0x0000fffe00000000
+#define BM_33_47 BM_47_33
+#define BM_48_33 0x0001fffe00000000
+#define BM_33_48 BM_48_33
+#define BM_49_33 0x0003fffe00000000
+#define BM_33_49 BM_49_33
+#define BM_50_33 0x0007fffe00000000
+#define BM_33_50 BM_50_33
+#define BM_51_33 0x000ffffe00000000
+#define BM_33_51 BM_51_33
+#define BM_52_33 0x001ffffe00000000
+#define BM_33_52 BM_52_33
+#define BM_53_33 0x003ffffe00000000
+#define BM_33_53 BM_53_33
+#define BM_54_33 0x007ffffe00000000
+#define BM_33_54 BM_54_33
+#define BM_55_33 0x00fffffe00000000
+#define BM_33_55 BM_55_33
+#define BM_56_33 0x01fffffe00000000
+#define BM_33_56 BM_56_33
+#define BM_57_33 0x03fffffe00000000
+#define BM_33_57 BM_57_33
+#define BM_58_33 0x07fffffe00000000
+#define BM_33_58 BM_58_33
+#define BM_59_33 0x0ffffffe00000000
+#define BM_33_59 BM_59_33
+#define BM_60_33 0x1ffffffe00000000
+#define BM_33_60 BM_60_33
+#define BM_61_33 0x3ffffffe00000000
+#define BM_33_61 BM_61_33
+#define BM_62_33 0x7ffffffe00000000
+#define BM_33_62 BM_62_33
+#define BM_63_33 0xfffffffe00000000
+#define BM_33_63 BM_63_33
+#define BM_34_34 0x0000000400000000
+#define BM_35_34 0x0000000c00000000
+#define BM_34_35 BM_35_34
+#define BM_36_34 0x0000001c00000000
+#define BM_34_36 BM_36_34
+#define BM_37_34 0x0000003c00000000
+#define BM_34_37 BM_37_34
+#define BM_38_34 0x0000007c00000000
+#define BM_34_38 BM_38_34
+#define BM_39_34 0x000000fc00000000
+#define BM_34_39 BM_39_34
+#define BM_40_34 0x000001fc00000000
+#define BM_34_40 BM_40_34
+#define BM_41_34 0x000003fc00000000
+#define BM_34_41 BM_41_34
+#define BM_42_34 0x000007fc00000000
+#define BM_34_42 BM_42_34
+#define BM_43_34 0x00000ffc00000000
+#define BM_34_43 BM_43_34
+#define BM_44_34 0x00001ffc00000000
+#define BM_34_44 BM_44_34
+#define BM_45_34 0x00003ffc00000000
+#define BM_34_45 BM_45_34
+#define BM_46_34 0x00007ffc00000000
+#define BM_34_46 BM_46_34
+#define BM_47_34 0x0000fffc00000000
+#define BM_34_47 BM_47_34
+#define BM_48_34 0x0001fffc00000000
+#define BM_34_48 BM_48_34
+#define BM_49_34 0x0003fffc00000000
+#define BM_34_49 BM_49_34
+#define BM_50_34 0x0007fffc00000000
+#define BM_34_50 BM_50_34
+#define BM_51_34 0x000ffffc00000000
+#define BM_34_51 BM_51_34
+#define BM_52_34 0x001ffffc00000000
+#define BM_34_52 BM_52_34
+#define BM_53_34 0x003ffffc00000000
+#define BM_34_53 BM_53_34
+#define BM_54_34 0x007ffffc00000000
+#define BM_34_54 BM_54_34
+#define BM_55_34 0x00fffffc00000000
+#define BM_34_55 BM_55_34
+#define BM_56_34 0x01fffffc00000000
+#define BM_34_56 BM_56_34
+#define BM_57_34 0x03fffffc00000000
+#define BM_34_57 BM_57_34
+#define BM_58_34 0x07fffffc00000000
+#define BM_34_58 BM_58_34
+#define BM_59_34 0x0ffffffc00000000
+#define BM_34_59 BM_59_34
+#define BM_60_34 0x1ffffffc00000000
+#define BM_34_60 BM_60_34
+#define BM_61_34 0x3ffffffc00000000
+#define BM_34_61 BM_61_34
+#define BM_62_34 0x7ffffffc00000000
+#define BM_34_62 BM_62_34
+#define BM_63_34 0xfffffffc00000000
+#define BM_34_63 BM_63_34
+#define BM_35_35 0x0000000800000000
+#define BM_36_35 0x0000001800000000
+#define BM_35_36 BM_36_35
+#define BM_37_35 0x0000003800000000
+#define BM_35_37 BM_37_35
+#define BM_38_35 0x0000007800000000
+#define BM_35_38 BM_38_35
+#define BM_39_35 0x000000f800000000
+#define BM_35_39 BM_39_35
+#define BM_40_35 0x000001f800000000
+#define BM_35_40 BM_40_35
+#define BM_41_35 0x000003f800000000
+#define BM_35_41 BM_41_35
+#define BM_42_35 0x000007f800000000
+#define BM_35_42 BM_42_35
+#define BM_43_35 0x00000ff800000000
+#define BM_35_43 BM_43_35
+#define BM_44_35 0x00001ff800000000
+#define BM_35_44 BM_44_35
+#define BM_45_35 0x00003ff800000000
+#define BM_35_45 BM_45_35
+#define BM_46_35 0x00007ff800000000
+#define BM_35_46 BM_46_35
+#define BM_47_35 0x0000fff800000000
+#define BM_35_47 BM_47_35
+#define BM_48_35 0x0001fff800000000
+#define BM_35_48 BM_48_35
+#define BM_49_35 0x0003fff800000000
+#define BM_35_49 BM_49_35
+#define BM_50_35 0x0007fff800000000
+#define BM_35_50 BM_50_35
+#define BM_51_35 0x000ffff800000000
+#define BM_35_51 BM_51_35
+#define BM_52_35 0x001ffff800000000
+#define BM_35_52 BM_52_35
+#define BM_53_35 0x003ffff800000000
+#define BM_35_53 BM_53_35
+#define BM_54_35 0x007ffff800000000
+#define BM_35_54 BM_54_35
+#define BM_55_35 0x00fffff800000000
+#define BM_35_55 BM_55_35
+#define BM_56_35 0x01fffff800000000
+#define BM_35_56 BM_56_35
+#define BM_57_35 0x03fffff800000000
+#define BM_35_57 BM_57_35
+#define BM_58_35 0x07fffff800000000
+#define BM_35_58 BM_58_35
+#define BM_59_35 0x0ffffff800000000
+#define BM_35_59 BM_59_35
+#define BM_60_35 0x1ffffff800000000
+#define BM_35_60 BM_60_35
+#define BM_61_35 0x3ffffff800000000
+#define BM_35_61 BM_61_35
+#define BM_62_35 0x7ffffff800000000
+#define BM_35_62 BM_62_35
+#define BM_63_35 0xfffffff800000000
+#define BM_35_63 BM_63_35
+#define BM_36_36 0x0000001000000000
+#define BM_37_36 0x0000003000000000
+#define BM_36_37 BM_37_36
+#define BM_38_36 0x0000007000000000
+#define BM_36_38 BM_38_36
+#define BM_39_36 0x000000f000000000
+#define BM_36_39 BM_39_36
+#define BM_40_36 0x000001f000000000
+#define BM_36_40 BM_40_36
+#define BM_41_36 0x000003f000000000
+#define BM_36_41 BM_41_36
+#define BM_42_36 0x000007f000000000
+#define BM_36_42 BM_42_36
+#define BM_43_36 0x00000ff000000000
+#define BM_36_43 BM_43_36
+#define BM_44_36 0x00001ff000000000
+#define BM_36_44 BM_44_36
+#define BM_45_36 0x00003ff000000000
+#define BM_36_45 BM_45_36
+#define BM_46_36 0x00007ff000000000
+#define BM_36_46 BM_46_36
+#define BM_47_36 0x0000fff000000000
+#define BM_36_47 BM_47_36
+#define BM_48_36 0x0001fff000000000
+#define BM_36_48 BM_48_36
+#define BM_49_36 0x0003fff000000000
+#define BM_36_49 BM_49_36
+#define BM_50_36 0x0007fff000000000
+#define BM_36_50 BM_50_36
+#define BM_51_36 0x000ffff000000000
+#define BM_36_51 BM_51_36
+#define BM_52_36 0x001ffff000000000
+#define BM_36_52 BM_52_36
+#define BM_53_36 0x003ffff000000000
+#define BM_36_53 BM_53_36
+#define BM_54_36 0x007ffff000000000
+#define BM_36_54 BM_54_36
+#define BM_55_36 0x00fffff000000000
+#define BM_36_55 BM_55_36
+#define BM_56_36 0x01fffff000000000
+#define BM_36_56 BM_56_36
+#define BM_57_36 0x03fffff000000000
+#define BM_36_57 BM_57_36
+#define BM_58_36 0x07fffff000000000
+#define BM_36_58 BM_58_36
+#define BM_59_36 0x0ffffff000000000
+#define BM_36_59 BM_59_36
+#define BM_60_36 0x1ffffff000000000
+#define BM_36_60 BM_60_36
+#define BM_61_36 0x3ffffff000000000
+#define BM_36_61 BM_61_36
+#define BM_62_36 0x7ffffff000000000
+#define BM_36_62 BM_62_36
+#define BM_63_36 0xfffffff000000000
+#define BM_36_63 BM_63_36
+#define BM_37_37 0x0000002000000000
+#define BM_38_37 0x0000006000000000
+#define BM_37_38 BM_38_37
+#define BM_39_37 0x000000e000000000
+#define BM_37_39 BM_39_37
+#define BM_40_37 0x000001e000000000
+#define BM_37_40 BM_40_37
+#define BM_41_37 0x000003e000000000
+#define BM_37_41 BM_41_37
+#define BM_42_37 0x000007e000000000
+#define BM_37_42 BM_42_37
+#define BM_43_37 0x00000fe000000000
+#define BM_37_43 BM_43_37
+#define BM_44_37 0x00001fe000000000
+#define BM_37_44 BM_44_37
+#define BM_45_37 0x00003fe000000000
+#define BM_37_45 BM_45_37
+#define BM_46_37 0x00007fe000000000
+#define BM_37_46 BM_46_37
+#define BM_47_37 0x0000ffe000000000
+#define BM_37_47 BM_47_37
+#define BM_48_37 0x0001ffe000000000
+#define BM_37_48 BM_48_37
+#define BM_49_37 0x0003ffe000000000
+#define BM_37_49 BM_49_37
+#define BM_50_37 0x0007ffe000000000
+#define BM_37_50 BM_50_37
+#define BM_51_37 0x000fffe000000000
+#define BM_37_51 BM_51_37
+#define BM_52_37 0x001fffe000000000
+#define BM_37_52 BM_52_37
+#define BM_53_37 0x003fffe000000000
+#define BM_37_53 BM_53_37
+#define BM_54_37 0x007fffe000000000
+#define BM_37_54 BM_54_37
+#define BM_55_37 0x00ffffe000000000
+#define BM_37_55 BM_55_37
+#define BM_56_37 0x01ffffe000000000
+#define BM_37_56 BM_56_37
+#define BM_57_37 0x03ffffe000000000
+#define BM_37_57 BM_57_37
+#define BM_58_37 0x07ffffe000000000
+#define BM_37_58 BM_58_37
+#define BM_59_37 0x0fffffe000000000
+#define BM_37_59 BM_59_37
+#define BM_60_37 0x1fffffe000000000
+#define BM_37_60 BM_60_37
+#define BM_61_37 0x3fffffe000000000
+#define BM_37_61 BM_61_37
+#define BM_62_37 0x7fffffe000000000
+#define BM_37_62 BM_62_37
+#define BM_63_37 0xffffffe000000000
+#define BM_37_63 BM_63_37
+#define BM_38_38 0x0000004000000000
+#define BM_39_38 0x000000c000000000
+#define BM_38_39 BM_39_38
+#define BM_40_38 0x000001c000000000
+#define BM_38_40 BM_40_38
+#define BM_41_38 0x000003c000000000
+#define BM_38_41 BM_41_38
+#define BM_42_38 0x000007c000000000
+#define BM_38_42 BM_42_38
+#define BM_43_38 0x00000fc000000000
+#define BM_38_43 BM_43_38
+#define BM_44_38 0x00001fc000000000
+#define BM_38_44 BM_44_38
+#define BM_45_38 0x00003fc000000000
+#define BM_38_45 BM_45_38
+#define BM_46_38 0x00007fc000000000
+#define BM_38_46 BM_46_38
+#define BM_47_38 0x0000ffc000000000
+#define BM_38_47 BM_47_38
+#define BM_48_38 0x0001ffc000000000
+#define BM_38_48 BM_48_38
+#define BM_49_38 0x0003ffc000000000
+#define BM_38_49 BM_49_38
+#define BM_50_38 0x0007ffc000000000
+#define BM_38_50 BM_50_38
+#define BM_51_38 0x000fffc000000000
+#define BM_38_51 BM_51_38
+#define BM_52_38 0x001fffc000000000
+#define BM_38_52 BM_52_38
+#define BM_53_38 0x003fffc000000000
+#define BM_38_53 BM_53_38
+#define BM_54_38 0x007fffc000000000
+#define BM_38_54 BM_54_38
+#define BM_55_38 0x00ffffc000000000
+#define BM_38_55 BM_55_38
+#define BM_56_38 0x01ffffc000000000
+#define BM_38_56 BM_56_38
+#define BM_57_38 0x03ffffc000000000
+#define BM_38_57 BM_57_38
+#define BM_58_38 0x07ffffc000000000
+#define BM_38_58 BM_58_38
+#define BM_59_38 0x0fffffc000000000
+#define BM_38_59 BM_59_38
+#define BM_60_38 0x1fffffc000000000
+#define BM_38_60 BM_60_38
+#define BM_61_38 0x3fffffc000000000
+#define BM_38_61 BM_61_38
+#define BM_62_38 0x7fffffc000000000
+#define BM_38_62 BM_62_38
+#define BM_63_38 0xffffffc000000000
+#define BM_38_63 BM_63_38
+#define BM_39_39 0x0000008000000000
+#define BM_40_39 0x0000018000000000
+#define BM_39_40 BM_40_39
+#define BM_41_39 0x0000038000000000
+#define BM_39_41 BM_41_39
+#define BM_42_39 0x0000078000000000
+#define BM_39_42 BM_42_39
+#define BM_43_39 0x00000f8000000000
+#define BM_39_43 BM_43_39
+#define BM_44_39 0x00001f8000000000
+#define BM_39_44 BM_44_39
+#define BM_45_39 0x00003f8000000000
+#define BM_39_45 BM_45_39
+#define BM_46_39 0x00007f8000000000
+#define BM_39_46 BM_46_39
+#define BM_47_39 0x0000ff8000000000
+#define BM_39_47 BM_47_39
+#define BM_48_39 0x0001ff8000000000
+#define BM_39_48 BM_48_39
+#define BM_49_39 0x0003ff8000000000
+#define BM_39_49 BM_49_39
+#define BM_50_39 0x0007ff8000000000
+#define BM_39_50 BM_50_39
+#define BM_51_39 0x000fff8000000000
+#define BM_39_51 BM_51_39
+#define BM_52_39 0x001fff8000000000
+#define BM_39_52 BM_52_39
+#define BM_53_39 0x003fff8000000000
+#define BM_39_53 BM_53_39
+#define BM_54_39 0x007fff8000000000
+#define BM_39_54 BM_54_39
+#define BM_55_39 0x00ffff8000000000
+#define BM_39_55 BM_55_39
+#define BM_56_39 0x01ffff8000000000
+#define BM_39_56 BM_56_39
+#define BM_57_39 0x03ffff8000000000
+#define BM_39_57 BM_57_39
+#define BM_58_39 0x07ffff8000000000
+#define BM_39_58 BM_58_39
+#define BM_59_39 0x0fffff8000000000
+#define BM_39_59 BM_59_39
+#define BM_60_39 0x1fffff8000000000
+#define BM_39_60 BM_60_39
+#define BM_61_39 0x3fffff8000000000
+#define BM_39_61 BM_61_39
+#define BM_62_39 0x7fffff8000000000
+#define BM_39_62 BM_62_39
+#define BM_63_39 0xffffff8000000000
+#define BM_39_63 BM_63_39
+#define BM_40_40 0x0000010000000000
+#define BM_41_40 0x0000030000000000
+#define BM_40_41 BM_41_40
+#define BM_42_40 0x0000070000000000
+#define BM_40_42 BM_42_40
+#define BM_43_40 0x00000f0000000000
+#define BM_40_43 BM_43_40
+#define BM_44_40 0x00001f0000000000
+#define BM_40_44 BM_44_40
+#define BM_45_40 0x00003f0000000000
+#define BM_40_45 BM_45_40
+#define BM_46_40 0x00007f0000000000
+#define BM_40_46 BM_46_40
+#define BM_47_40 0x0000ff0000000000
+#define BM_40_47 BM_47_40
+#define BM_48_40 0x0001ff0000000000
+#define BM_40_48 BM_48_40
+#define BM_49_40 0x0003ff0000000000
+#define BM_40_49 BM_49_40
+#define BM_50_40 0x0007ff0000000000
+#define BM_40_50 BM_50_40
+#define BM_51_40 0x000fff0000000000
+#define BM_40_51 BM_51_40
+#define BM_52_40 0x001fff0000000000
+#define BM_40_52 BM_52_40
+#define BM_53_40 0x003fff0000000000
+#define BM_40_53 BM_53_40
+#define BM_54_40 0x007fff0000000000
+#define BM_40_54 BM_54_40
+#define BM_55_40 0x00ffff0000000000
+#define BM_40_55 BM_55_40
+#define BM_56_40 0x01ffff0000000000
+#define BM_40_56 BM_56_40
+#define BM_57_40 0x03ffff0000000000
+#define BM_40_57 BM_57_40
+#define BM_58_40 0x07ffff0000000000
+#define BM_40_58 BM_58_40
+#define BM_59_40 0x0fffff0000000000
+#define BM_40_59 BM_59_40
+#define BM_60_40 0x1fffff0000000000
+#define BM_40_60 BM_60_40
+#define BM_61_40 0x3fffff0000000000
+#define BM_40_61 BM_61_40
+#define BM_62_40 0x7fffff0000000000
+#define BM_40_62 BM_62_40
+#define BM_63_40 0xffffff0000000000
+#define BM_40_63 BM_63_40
+#define BM_41_41 0x0000020000000000
+#define BM_42_41 0x0000060000000000
+#define BM_41_42 BM_42_41
+#define BM_43_41 0x00000e0000000000
+#define BM_41_43 BM_43_41
+#define BM_44_41 0x00001e0000000000
+#define BM_41_44 BM_44_41
+#define BM_45_41 0x00003e0000000000
+#define BM_41_45 BM_45_41
+#define BM_46_41 0x00007e0000000000
+#define BM_41_46 BM_46_41
+#define BM_47_41 0x0000fe0000000000
+#define BM_41_47 BM_47_41
+#define BM_48_41 0x0001fe0000000000
+#define BM_41_48 BM_48_41
+#define BM_49_41 0x0003fe0000000000
+#define BM_41_49 BM_49_41
+#define BM_50_41 0x0007fe0000000000
+#define BM_41_50 BM_50_41
+#define BM_51_41 0x000ffe0000000000
+#define BM_41_51 BM_51_41
+#define BM_52_41 0x001ffe0000000000
+#define BM_41_52 BM_52_41
+#define BM_53_41 0x003ffe0000000000
+#define BM_41_53 BM_53_41
+#define BM_54_41 0x007ffe0000000000
+#define BM_41_54 BM_54_41
+#define BM_55_41 0x00fffe0000000000
+#define BM_41_55 BM_55_41
+#define BM_56_41 0x01fffe0000000000
+#define BM_41_56 BM_56_41
+#define BM_57_41 0x03fffe0000000000
+#define BM_41_57 BM_57_41
+#define BM_58_41 0x07fffe0000000000
+#define BM_41_58 BM_58_41
+#define BM_59_41 0x0ffffe0000000000
+#define BM_41_59 BM_59_41
+#define BM_60_41 0x1ffffe0000000000
+#define BM_41_60 BM_60_41
+#define BM_61_41 0x3ffffe0000000000
+#define BM_41_61 BM_61_41
+#define BM_62_41 0x7ffffe0000000000
+#define BM_41_62 BM_62_41
+#define BM_63_41 0xfffffe0000000000
+#define BM_41_63 BM_63_41
+#define BM_42_42 0x0000040000000000
+#define BM_43_42 0x00000c0000000000
+#define BM_42_43 BM_43_42
+#define BM_44_42 0x00001c0000000000
+#define BM_42_44 BM_44_42
+#define BM_45_42 0x00003c0000000000
+#define BM_42_45 BM_45_42
+#define BM_46_42 0x00007c0000000000
+#define BM_42_46 BM_46_42
+#define BM_47_42 0x0000fc0000000000
+#define BM_42_47 BM_47_42
+#define BM_48_42 0x0001fc0000000000
+#define BM_42_48 BM_48_42
+#define BM_49_42 0x0003fc0000000000
+#define BM_42_49 BM_49_42
+#define BM_50_42 0x0007fc0000000000
+#define BM_42_50 BM_50_42
+#define BM_51_42 0x000ffc0000000000
+#define BM_42_51 BM_51_42
+#define BM_52_42 0x001ffc0000000000
+#define BM_42_52 BM_52_42
+#define BM_53_42 0x003ffc0000000000
+#define BM_42_53 BM_53_42
+#define BM_54_42 0x007ffc0000000000
+#define BM_42_54 BM_54_42
+#define BM_55_42 0x00fffc0000000000
+#define BM_42_55 BM_55_42
+#define BM_56_42 0x01fffc0000000000
+#define BM_42_56 BM_56_42
+#define BM_57_42 0x03fffc0000000000
+#define BM_42_57 BM_57_42
+#define BM_58_42 0x07fffc0000000000
+#define BM_42_58 BM_58_42
+#define BM_59_42 0x0ffffc0000000000
+#define BM_42_59 BM_59_42
+#define BM_60_42 0x1ffffc0000000000
+#define BM_42_60 BM_60_42
+#define BM_61_42 0x3ffffc0000000000
+#define BM_42_61 BM_61_42
+#define BM_62_42 0x7ffffc0000000000
+#define BM_42_62 BM_62_42
+#define BM_63_42 0xfffffc0000000000
+#define BM_42_63 BM_63_42
+#define BM_43_43 0x0000080000000000
+#define BM_44_43 0x0000180000000000
+#define BM_43_44 BM_44_43
+#define BM_45_43 0x0000380000000000
+#define BM_43_45 BM_45_43
+#define BM_46_43 0x0000780000000000
+#define BM_43_46 BM_46_43
+#define BM_47_43 0x0000f80000000000
+#define BM_43_47 BM_47_43
+#define BM_48_43 0x0001f80000000000
+#define BM_43_48 BM_48_43
+#define BM_49_43 0x0003f80000000000
+#define BM_43_49 BM_49_43
+#define BM_50_43 0x0007f80000000000
+#define BM_43_50 BM_50_43
+#define BM_51_43 0x000ff80000000000
+#define BM_43_51 BM_51_43
+#define BM_52_43 0x001ff80000000000
+#define BM_43_52 BM_52_43
+#define BM_53_43 0x003ff80000000000
+#define BM_43_53 BM_53_43
+#define BM_54_43 0x007ff80000000000
+#define BM_43_54 BM_54_43
+#define BM_55_43 0x00fff80000000000
+#define BM_43_55 BM_55_43
+#define BM_56_43 0x01fff80000000000
+#define BM_43_56 BM_56_43
+#define BM_57_43 0x03fff80000000000
+#define BM_43_57 BM_57_43
+#define BM_58_43 0x07fff80000000000
+#define BM_43_58 BM_58_43
+#define BM_59_43 0x0ffff80000000000
+#define BM_43_59 BM_59_43
+#define BM_60_43 0x1ffff80000000000
+#define BM_43_60 BM_60_43
+#define BM_61_43 0x3ffff80000000000
+#define BM_43_61 BM_61_43
+#define BM_62_43 0x7ffff80000000000
+#define BM_43_62 BM_62_43
+#define BM_63_43 0xfffff80000000000
+#define BM_43_63 BM_63_43
+#define BM_44_44 0x0000100000000000
+#define BM_45_44 0x0000300000000000
+#define BM_44_45 BM_45_44
+#define BM_46_44 0x0000700000000000
+#define BM_44_46 BM_46_44
+#define BM_47_44 0x0000f00000000000
+#define BM_44_47 BM_47_44
+#define BM_48_44 0x0001f00000000000
+#define BM_44_48 BM_48_44
+#define BM_49_44 0x0003f00000000000
+#define BM_44_49 BM_49_44
+#define BM_50_44 0x0007f00000000000
+#define BM_44_50 BM_50_44
+#define BM_51_44 0x000ff00000000000
+#define BM_44_51 BM_51_44
+#define BM_52_44 0x001ff00000000000
+#define BM_44_52 BM_52_44
+#define BM_53_44 0x003ff00000000000
+#define BM_44_53 BM_53_44
+#define BM_54_44 0x007ff00000000000
+#define BM_44_54 BM_54_44
+#define BM_55_44 0x00fff00000000000
+#define BM_44_55 BM_55_44
+#define BM_56_44 0x01fff00000000000
+#define BM_44_56 BM_56_44
+#define BM_57_44 0x03fff00000000000
+#define BM_44_57 BM_57_44
+#define BM_58_44 0x07fff00000000000
+#define BM_44_58 BM_58_44
+#define BM_59_44 0x0ffff00000000000
+#define BM_44_59 BM_59_44
+#define BM_60_44 0x1ffff00000000000
+#define BM_44_60 BM_60_44
+#define BM_61_44 0x3ffff00000000000
+#define BM_44_61 BM_61_44
+#define BM_62_44 0x7ffff00000000000
+#define BM_44_62 BM_62_44
+#define BM_63_44 0xfffff00000000000
+#define BM_44_63 BM_63_44
+#define BM_45_45 0x0000200000000000
+#define BM_46_45 0x0000600000000000
+#define BM_45_46 BM_46_45
+#define BM_47_45 0x0000e00000000000
+#define BM_45_47 BM_47_45
+#define BM_48_45 0x0001e00000000000
+#define BM_45_48 BM_48_45
+#define BM_49_45 0x0003e00000000000
+#define BM_45_49 BM_49_45
+#define BM_50_45 0x0007e00000000000
+#define BM_45_50 BM_50_45
+#define BM_51_45 0x000fe00000000000
+#define BM_45_51 BM_51_45
+#define BM_52_45 0x001fe00000000000
+#define BM_45_52 BM_52_45
+#define BM_53_45 0x003fe00000000000
+#define BM_45_53 BM_53_45
+#define BM_54_45 0x007fe00000000000
+#define BM_45_54 BM_54_45
+#define BM_55_45 0x00ffe00000000000
+#define BM_45_55 BM_55_45
+#define BM_56_45 0x01ffe00000000000
+#define BM_45_56 BM_56_45
+#define BM_57_45 0x03ffe00000000000
+#define BM_45_57 BM_57_45
+#define BM_58_45 0x07ffe00000000000
+#define BM_45_58 BM_58_45
+#define BM_59_45 0x0fffe00000000000
+#define BM_45_59 BM_59_45
+#define BM_60_45 0x1fffe00000000000
+#define BM_45_60 BM_60_45
+#define BM_61_45 0x3fffe00000000000
+#define BM_45_61 BM_61_45
+#define BM_62_45 0x7fffe00000000000
+#define BM_45_62 BM_62_45
+#define BM_63_45 0xffffe00000000000
+#define BM_45_63 BM_63_45
+#define BM_46_46 0x0000400000000000
+#define BM_47_46 0x0000c00000000000
+#define BM_46_47 BM_47_46
+#define BM_48_46 0x0001c00000000000
+#define BM_46_48 BM_48_46
+#define BM_49_46 0x0003c00000000000
+#define BM_46_49 BM_49_46
+#define BM_50_46 0x0007c00000000000
+#define BM_46_50 BM_50_46
+#define BM_51_46 0x000fc00000000000
+#define BM_46_51 BM_51_46
+#define BM_52_46 0x001fc00000000000
+#define BM_46_52 BM_52_46
+#define BM_53_46 0x003fc00000000000
+#define BM_46_53 BM_53_46
+#define BM_54_46 0x007fc00000000000
+#define BM_46_54 BM_54_46
+#define BM_55_46 0x00ffc00000000000
+#define BM_46_55 BM_55_46
+#define BM_56_46 0x01ffc00000000000
+#define BM_46_56 BM_56_46
+#define BM_57_46 0x03ffc00000000000
+#define BM_46_57 BM_57_46
+#define BM_58_46 0x07ffc00000000000
+#define BM_46_58 BM_58_46
+#define BM_59_46 0x0fffc00000000000
+#define BM_46_59 BM_59_46
+#define BM_60_46 0x1fffc00000000000
+#define BM_46_60 BM_60_46
+#define BM_61_46 0x3fffc00000000000
+#define BM_46_61 BM_61_46
+#define BM_62_46 0x7fffc00000000000
+#define BM_46_62 BM_62_46
+#define BM_63_46 0xffffc00000000000
+#define BM_46_63 BM_63_46
+#define BM_47_47 0x0000800000000000
+#define BM_48_47 0x0001800000000000
+#define BM_47_48 BM_48_47
+#define BM_49_47 0x0003800000000000
+#define BM_47_49 BM_49_47
+#define BM_50_47 0x0007800000000000
+#define BM_47_50 BM_50_47
+#define BM_51_47 0x000f800000000000
+#define BM_47_51 BM_51_47
+#define BM_52_47 0x001f800000000000
+#define BM_47_52 BM_52_47
+#define BM_53_47 0x003f800000000000
+#define BM_47_53 BM_53_47
+#define BM_54_47 0x007f800000000000
+#define BM_47_54 BM_54_47
+#define BM_55_47 0x00ff800000000000
+#define BM_47_55 BM_55_47
+#define BM_56_47 0x01ff800000000000
+#define BM_47_56 BM_56_47
+#define BM_57_47 0x03ff800000000000
+#define BM_47_57 BM_57_47
+#define BM_58_47 0x07ff800000000000
+#define BM_47_58 BM_58_47
+#define BM_59_47 0x0fff800000000000
+#define BM_47_59 BM_59_47
+#define BM_60_47 0x1fff800000000000
+#define BM_47_60 BM_60_47
+#define BM_61_47 0x3fff800000000000
+#define BM_47_61 BM_61_47
+#define BM_62_47 0x7fff800000000000
+#define BM_47_62 BM_62_47
+#define BM_63_47 0xffff800000000000
+#define BM_47_63 BM_63_47
+#define BM_48_48 0x0001000000000000
+#define BM_49_48 0x0003000000000000
+#define BM_48_49 BM_49_48
+#define BM_50_48 0x0007000000000000
+#define BM_48_50 BM_50_48
+#define BM_51_48 0x000f000000000000
+#define BM_48_51 BM_51_48
+#define BM_52_48 0x001f000000000000
+#define BM_48_52 BM_52_48
+#define BM_53_48 0x003f000000000000
+#define BM_48_53 BM_53_48
+#define BM_54_48 0x007f000000000000
+#define BM_48_54 BM_54_48
+#define BM_55_48 0x00ff000000000000
+#define BM_48_55 BM_55_48
+#define BM_56_48 0x01ff000000000000
+#define BM_48_56 BM_56_48
+#define BM_57_48 0x03ff000000000000
+#define BM_48_57 BM_57_48
+#define BM_58_48 0x07ff000000000000
+#define BM_48_58 BM_58_48
+#define BM_59_48 0x0fff000000000000
+#define BM_48_59 BM_59_48
+#define BM_60_48 0x1fff000000000000
+#define BM_48_60 BM_60_48
+#define BM_61_48 0x3fff000000000000
+#define BM_48_61 BM_61_48
+#define BM_62_48 0x7fff000000000000
+#define BM_48_62 BM_62_48
+#define BM_63_48 0xffff000000000000
+#define BM_48_63 BM_63_48
+#define BM_49_49 0x0002000000000000
+#define BM_50_49 0x0006000000000000
+#define BM_49_50 BM_50_49
+#define BM_51_49 0x000e000000000000
+#define BM_49_51 BM_51_49
+#define BM_52_49 0x001e000000000000
+#define BM_49_52 BM_52_49
+#define BM_53_49 0x003e000000000000
+#define BM_49_53 BM_53_49
+#define BM_54_49 0x007e000000000000
+#define BM_49_54 BM_54_49
+#define BM_55_49 0x00fe000000000000
+#define BM_49_55 BM_55_49
+#define BM_56_49 0x01fe000000000000
+#define BM_49_56 BM_56_49
+#define BM_57_49 0x03fe000000000000
+#define BM_49_57 BM_57_49
+#define BM_58_49 0x07fe000000000000
+#define BM_49_58 BM_58_49
+#define BM_59_49 0x0ffe000000000000
+#define BM_49_59 BM_59_49
+#define BM_60_49 0x1ffe000000000000
+#define BM_49_60 BM_60_49
+#define BM_61_49 0x3ffe000000000000
+#define BM_49_61 BM_61_49
+#define BM_62_49 0x7ffe000000000000
+#define BM_49_62 BM_62_49
+#define BM_63_49 0xfffe000000000000
+#define BM_49_63 BM_63_49
+#define BM_50_50 0x0004000000000000
+#define BM_51_50 0x000c000000000000
+#define BM_50_51 BM_51_50
+#define BM_52_50 0x001c000000000000
+#define BM_50_52 BM_52_50
+#define BM_53_50 0x003c000000000000
+#define BM_50_53 BM_53_50
+#define BM_54_50 0x007c000000000000
+#define BM_50_54 BM_54_50
+#define BM_55_50 0x00fc000000000000
+#define BM_50_55 BM_55_50
+#define BM_56_50 0x01fc000000000000
+#define BM_50_56 BM_56_50
+#define BM_57_50 0x03fc000000000000
+#define BM_50_57 BM_57_50
+#define BM_58_50 0x07fc000000000000
+#define BM_50_58 BM_58_50
+#define BM_59_50 0x0ffc000000000000
+#define BM_50_59 BM_59_50
+#define BM_60_50 0x1ffc000000000000
+#define BM_50_60 BM_60_50
+#define BM_61_50 0x3ffc000000000000
+#define BM_50_61 BM_61_50
+#define BM_62_50 0x7ffc000000000000
+#define BM_50_62 BM_62_50
+#define BM_63_50 0xfffc000000000000
+#define BM_50_63 BM_63_50
+#define BM_51_51 0x0008000000000000
+#define BM_52_51 0x0018000000000000
+#define BM_51_52 BM_52_51
+#define BM_53_51 0x0038000000000000
+#define BM_51_53 BM_53_51
+#define BM_54_51 0x0078000000000000
+#define BM_51_54 BM_54_51
+#define BM_55_51 0x00f8000000000000
+#define BM_51_55 BM_55_51
+#define BM_56_51 0x01f8000000000000
+#define BM_51_56 BM_56_51
+#define BM_57_51 0x03f8000000000000
+#define BM_51_57 BM_57_51
+#define BM_58_51 0x07f8000000000000
+#define BM_51_58 BM_58_51
+#define BM_59_51 0x0ff8000000000000
+#define BM_51_59 BM_59_51
+#define BM_60_51 0x1ff8000000000000
+#define BM_51_60 BM_60_51
+#define BM_61_51 0x3ff8000000000000
+#define BM_51_61 BM_61_51
+#define BM_62_51 0x7ff8000000000000
+#define BM_51_62 BM_62_51
+#define BM_63_51 0xfff8000000000000
+#define BM_51_63 BM_63_51
+#define BM_52_52 0x0010000000000000
+#define BM_53_52 0x0030000000000000
+#define BM_52_53 BM_53_52
+#define BM_54_52 0x0070000000000000
+#define BM_52_54 BM_54_52
+#define BM_55_52 0x00f0000000000000
+#define BM_52_55 BM_55_52
+#define BM_56_52 0x01f0000000000000
+#define BM_52_56 BM_56_52
+#define BM_57_52 0x03f0000000000000
+#define BM_52_57 BM_57_52
+#define BM_58_52 0x07f0000000000000
+#define BM_52_58 BM_58_52
+#define BM_59_52 0x0ff0000000000000
+#define BM_52_59 BM_59_52
+#define BM_60_52 0x1ff0000000000000
+#define BM_52_60 BM_60_52
+#define BM_61_52 0x3ff0000000000000
+#define BM_52_61 BM_61_52
+#define BM_62_52 0x7ff0000000000000
+#define BM_52_62 BM_62_52
+#define BM_63_52 0xfff0000000000000
+#define BM_52_63 BM_63_52
+#define BM_53_53 0x0020000000000000
+#define BM_54_53 0x0060000000000000
+#define BM_53_54 BM_54_53
+#define BM_55_53 0x00e0000000000000
+#define BM_53_55 BM_55_53
+#define BM_56_53 0x01e0000000000000
+#define BM_53_56 BM_56_53
+#define BM_57_53 0x03e0000000000000
+#define BM_53_57 BM_57_53
+#define BM_58_53 0x07e0000000000000
+#define BM_53_58 BM_58_53
+#define BM_59_53 0x0fe0000000000000
+#define BM_53_59 BM_59_53
+#define BM_60_53 0x1fe0000000000000
+#define BM_53_60 BM_60_53
+#define BM_61_53 0x3fe0000000000000
+#define BM_53_61 BM_61_53
+#define BM_62_53 0x7fe0000000000000
+#define BM_53_62 BM_62_53
+#define BM_63_53 0xffe0000000000000
+#define BM_53_63 BM_63_53
+#define BM_54_54 0x0040000000000000
+#define BM_55_54 0x00c0000000000000
+#define BM_54_55 BM_55_54
+#define BM_56_54 0x01c0000000000000
+#define BM_54_56 BM_56_54
+#define BM_57_54 0x03c0000000000000
+#define BM_54_57 BM_57_54
+#define BM_58_54 0x07c0000000000000
+#define BM_54_58 BM_58_54
+#define BM_59_54 0x0fc0000000000000
+#define BM_54_59 BM_59_54
+#define BM_60_54 0x1fc0000000000000
+#define BM_54_60 BM_60_54
+#define BM_61_54 0x3fc0000000000000
+#define BM_54_61 BM_61_54
+#define BM_62_54 0x7fc0000000000000
+#define BM_54_62 BM_62_54
+#define BM_63_54 0xffc0000000000000
+#define BM_54_63 BM_63_54
+#define BM_55_55 0x0080000000000000
+#define BM_56_55 0x0180000000000000
+#define BM_55_56 BM_56_55
+#define BM_57_55 0x0380000000000000
+#define BM_55_57 BM_57_55
+#define BM_58_55 0x0780000000000000
+#define BM_55_58 BM_58_55
+#define BM_59_55 0x0f80000000000000
+#define BM_55_59 BM_59_55
+#define BM_60_55 0x1f80000000000000
+#define BM_55_60 BM_60_55
+#define BM_61_55 0x3f80000000000000
+#define BM_55_61 BM_61_55
+#define BM_62_55 0x7f80000000000000
+#define BM_55_62 BM_62_55
+#define BM_63_55 0xff80000000000000
+#define BM_55_63 BM_63_55
+#define BM_56_56 0x0100000000000000
+#define BM_57_56 0x0300000000000000
+#define BM_56_57 BM_57_56
+#define BM_58_56 0x0700000000000000
+#define BM_56_58 BM_58_56
+#define BM_59_56 0x0f00000000000000
+#define BM_56_59 BM_59_56
+#define BM_60_56 0x1f00000000000000
+#define BM_56_60 BM_60_56
+#define BM_61_56 0x3f00000000000000
+#define BM_56_61 BM_61_56
+#define BM_62_56 0x7f00000000000000
+#define BM_56_62 BM_62_56
+#define BM_63_56 0xff00000000000000
+#define BM_56_63 BM_63_56
+#define BM_57_57 0x0200000000000000
+#define BM_58_57 0x0600000000000000
+#define BM_57_58 BM_58_57
+#define BM_59_57 0x0e00000000000000
+#define BM_57_59 BM_59_57
+#define BM_60_57 0x1e00000000000000
+#define BM_57_60 BM_60_57
+#define BM_61_57 0x3e00000000000000
+#define BM_57_61 BM_61_57
+#define BM_62_57 0x7e00000000000000
+#define BM_57_62 BM_62_57
+#define BM_63_57 0xfe00000000000000
+#define BM_57_63 BM_63_57
+#define BM_58_58 0x0400000000000000
+#define BM_59_58 0x0c00000000000000
+#define BM_58_59 BM_59_58
+#define BM_60_58 0x1c00000000000000
+#define BM_58_60 BM_60_58
+#define BM_61_58 0x3c00000000000000
+#define BM_58_61 BM_61_58
+#define BM_62_58 0x7c00000000000000
+#define BM_58_62 BM_62_58
+#define BM_63_58 0xfc00000000000000
+#define BM_58_63 BM_63_58
+#define BM_59_59 0x0800000000000000
+#define BM_60_59 0x1800000000000000
+#define BM_59_60 BM_60_59
+#define BM_61_59 0x3800000000000000
+#define BM_59_61 BM_61_59
+#define BM_62_59 0x7800000000000000
+#define BM_59_62 BM_62_59
+#define BM_63_59 0xf800000000000000
+#define BM_59_63 BM_63_59
+#define BM_60_60 0x1000000000000000
+#define BM_61_60 0x3000000000000000
+#define BM_60_61 BM_61_60
+#define BM_62_60 0x7000000000000000
+#define BM_60_62 BM_62_60
+#define BM_63_60 0xf000000000000000
+#define BM_60_63 BM_63_60
+#define BM_61_61 0x2000000000000000
+#define BM_62_61 0x6000000000000000
+#define BM_61_62 BM_62_61
+#define BM_63_61 0xe000000000000000
+#define BM_61_63 BM_63_61
+#define BM_62_62 0x4000000000000000
+#define BM_63_62 0xc000000000000000
+#define BM_62_63 BM_63_62
+#define BM_63_63 0x8000000000000000
+
+#endif
+
+#endif /* __ASM_TX4927_TX4927_MIPS_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
new file mode 100644
index 000000000000..170433492246
--- /dev/null
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -0,0 +1,275 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ */
+#ifndef __ASM_TX4927_TX4927_PCI_H 
+#define __ASM_TX4927_TX4927_PCI_H 
+
+#define TX4927_CCFG_TOE 0x00004000
+
+#define TX4927_PCIMEM      0x08000000
+#define TX4927_PCIMEM_SIZE 0x08000000
+#define TX4927_PCIIO       0x16000000
+#define TX4927_PCIIO_SIZE  0x01000000
+
+#define TX4927_SDRAMC_REG       0xff1f8000
+#define TX4927_EBUSC_REG        0xff1f9000
+#define TX4927_PCIC_REG         0xff1fd000
+#define TX4927_CCFG_REG         0xff1fe000
+#define TX4927_IRC_REG          0xff1ff600
+#define TX4927_CE3      0x17f00000      /* 1M */
+#define TX4927_PCIRESET_ADDR    0xbc00f006
+#define TX4927_PCI_CLK_ADDR     (KSEG1 + TX4927_CE3 + 0x00040020)
+
+#define TX4927_IMSTAT_ADDR(n)   (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
+#define tx4927_imstat_ptr(n)    \
+        ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
+
+/* bits for ISTAT3/IMASK3/IMSTAT3 */
+#define TX4927_INT3B_PCID       0
+#define TX4927_INT3B_PCIC       1
+#define TX4927_INT3B_PCIB       2
+#define TX4927_INT3B_PCIA       3
+#define TX4927_INT3F_PCID       (1 << TX4927_INT3B_PCID)
+#define TX4927_INT3F_PCIC       (1 << TX4927_INT3B_PCIC)
+#define TX4927_INT3F_PCIB       (1 << TX4927_INT3B_PCIB)
+#define TX4927_INT3F_PCIA       (1 << TX4927_INT3B_PCIA)
+
+/* bits for PCI_CLK (S6) */
+#define TX4927_PCI_CLK_HOST     0x80
+#define TX4927_PCI_CLK_MASK     (0x0f << 3)
+#define TX4927_PCI_CLK_33       (0x01 << 3)
+#define TX4927_PCI_CLK_25       (0x04 << 3)
+#define TX4927_PCI_CLK_66       (0x09 << 3)
+#define TX4927_PCI_CLK_50       (0x0c << 3)
+#define TX4927_PCI_CLK_ACK      0x04
+#define TX4927_PCI_CLK_ACE      0x02
+#define TX4927_PCI_CLK_ENDIAN   0x01
+#define TX4927_NR_IRQ_LOCAL     (8+16)
+#define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
+
+#define TX4927_IR_PCIC          16
+#define TX4927_IR_PCIERR        22
+#define TX4927_IR_PCIPMA        23
+#define TX4927_IRQ_IRC_PCIC     (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
+#define TX4927_IRQ_IRC_PCIERR   (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
+#define TX4927_IRQ_IOC1         (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
+#define TX4927_IRQ_IOC_PCID     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
+#define TX4927_IRQ_IOC_PCIC     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
+#define TX4927_IRQ_IOC_PCIB     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
+#define TX4927_IRQ_IOC_PCIA     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
+
+#ifdef _LANGUAGE_ASSEMBLY
+#define _CONST64(c)     c
+#else
+#define _CONST64(c)     c##ull
+
+#include <asm/byteorder.h>
+
+#define tx4927_pcireset_ptr     \
+        ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
+#define tx4927_pci_clk_ptr      \
+        ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
+
+struct tx4927_sdramc_reg {
+        volatile unsigned long long cr[4];
+        volatile unsigned long long unused0[4];
+        volatile unsigned long long tr;
+        volatile unsigned long long unused1[2];
+        volatile unsigned long long cmd;
+};
+
+struct tx4927_ebusc_reg {
+        volatile unsigned long long cr[8];
+};
+
+struct tx4927_ccfg_reg {
+        volatile unsigned long long ccfg;
+        volatile unsigned long long crir;
+        volatile unsigned long long pcfg;
+        volatile unsigned long long tear;
+        volatile unsigned long long clkctr;
+        volatile unsigned long long unused0;
+        volatile unsigned long long garbc;
+        volatile unsigned long long unused1;
+        volatile unsigned long long unused2;
+        volatile unsigned long long ramp;
+};
+
+struct tx4927_irc_reg {
+        volatile unsigned long cer;
+        volatile unsigned long cr[2];
+        volatile unsigned long unused0;
+        volatile unsigned long ilr[8];
+        volatile unsigned long unused1[4];
+        volatile unsigned long imr;
+        volatile unsigned long unused2[7];
+        volatile unsigned long scr;
+        volatile unsigned long unused3[7];
+        volatile unsigned long ssr;
+        volatile unsigned long unused4[7];
+        volatile unsigned long csr;
+};
+
+struct tx4927_pcic_reg {
+        volatile unsigned long pciid;
+        volatile unsigned long pcistatus;
+        volatile unsigned long pciccrev;
+        volatile unsigned long pcicfg1;
+        volatile unsigned long p2gm0plbase;             /* +10 */
+        volatile unsigned long p2gm0pubase;
+        volatile unsigned long p2gm1plbase;
+        volatile unsigned long p2gm1pubase;
+        volatile unsigned long p2gm2pbase;              /* +20 */
+        volatile unsigned long p2giopbase;
+        volatile unsigned long unused0;
+        volatile unsigned long pcisid;
+        volatile unsigned long unused1;         /* +30 */
+        volatile unsigned long pcicapptr;
+        volatile unsigned long unused2;
+        volatile unsigned long pcicfg2;
+        volatile unsigned long g2ptocnt;                /* +40 */
+        volatile unsigned long unused3[15];
+        volatile unsigned long g2pstatus;               /* +80 */
+        volatile unsigned long g2pmask;
+        volatile unsigned long pcisstatus;
+        volatile unsigned long pcimask;
+        volatile unsigned long p2gcfg;          /* +90 */
+        volatile unsigned long p2gstatus;
+        volatile unsigned long p2gmask;
+        volatile unsigned long p2gccmd;
+        volatile unsigned long unused4[24];             /* +a0 */
+        volatile unsigned long pbareqport;              /* +100 */
+        volatile unsigned long pbacfg;
+        volatile unsigned long pbastatus;
+        volatile unsigned long pbamask;
+        volatile unsigned long pbabm;           /* +110 */
+        volatile unsigned long pbacreq;
+        volatile unsigned long pbacgnt;
+        volatile unsigned long pbacstate;
+        volatile unsigned long long g2pmgbase[3];               /* +120 */
+        volatile unsigned long long g2piogbase;
+        volatile unsigned long g2pmmask[3];             /* +140 */
+        volatile unsigned long g2piomask;
+        volatile unsigned long long g2pmpbase[3];               /* +150 */
+        volatile unsigned long long g2piopbase;
+        volatile unsigned long pciccfg;         /* +170 */
+        volatile unsigned long pcicstatus;
+        volatile unsigned long pcicmask;
+        volatile unsigned long unused5;
+        volatile unsigned long long p2gmgbase[3];               /* +180 */
+        volatile unsigned long long p2giogbase;
+        volatile unsigned long g2pcfgadrs;              /* +1a0 */
+        volatile unsigned long g2pcfgdata;
+        volatile unsigned long unused6[8];
+        volatile unsigned long g2pintack;
+        volatile unsigned long g2pspc;
+        volatile unsigned long unused7[12];             /* +1d0 */
+        volatile unsigned long long pdmca;              /* +200 */
+        volatile unsigned long long pdmga;
+        volatile unsigned long long pdmpa;
+        volatile unsigned long long pdmcut;
+        volatile unsigned long long pdmcnt;             /* +220 */
+        volatile unsigned long long pdmsts;
+        volatile unsigned long long unused8[2];
+        volatile unsigned long long pdmdb[4];           /* +240 */
+        volatile unsigned long long pdmtdh;             /* +260 */
+        volatile unsigned long long pdmdms;
+};
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+/* IRCSR : Int. Current Status */
+#define TX4927_IRCSR_IF         0x00010000
+#define TX4927_IRCSR_ILV_MASK   0x00000700
+#define TX4927_IRCSR_IVL_MASK   0x0000001f
+
+/*
+ * PCIC
+ */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4927_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
+#define TX4927_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL      0x000007dc
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_LBWC_MASK   0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST        0x00000800
+#define TX4927_PCIC_PCICCFG_SRST        0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4927_PCIC_PCICCFG_IMSE0       0x00000100
+#define TX4927_PCIC_PCICCFG_IMSE1       0x00000080
+#define TX4927_PCIC_PCICCFG_IMSE2       0x00000040
+#define TX4927_PCIC_PCICCFG_IISE        0x00000020
+#define TX4927_PCIC_PCICCFG_ATR 0x00000010
+#define TX4927_PCIC_PCICCFG_ICAE        0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4927_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
+#define TX4927_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_PCI66       0x00800000
+#define TX4927_CCFG_PCIMIDE     0x00400000
+#define TX4927_CCFG_PCIXARB     0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_PCICKD    0x00400000
+#define TX4927_CLKCTR_PCIRST    0x00000040
+
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#define tx4927_sdramcptr        ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
+#define tx4927_ircptr           ((struct tx4927_irc_reg *)TX4927_IRC_REG)
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+#endif /* __ASM_TX4927_TX4927_PCI_H */
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
new file mode 100644
index 000000000000..d2f0c76b00a9
--- /dev/null
+++ b/include/asm-mips/types.h
@@ -0,0 +1,108 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long __s64;
+typedef unsigned long __u64;
+
+#else
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+
+typedef __signed char s8;
+typedef unsigned char u8;
+
+typedef __signed short s16;
+typedef unsigned short u16;
+
+typedef __signed int s32;
+typedef unsigned int u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long s64;
+typedef unsigned long u64;
+
+#else
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+#endif
+
+#endif
+
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_MIPS64)
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+typedef unsigned short kmem_bufctl_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
new file mode 100644
index 000000000000..07114898e065
--- /dev/null
+++ b/include/asm-mips/uaccess.h
@@ -0,0 +1,830 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/thread_info.h>
+#include <asm-generic/uaccess.h>
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+#ifdef CONFIG_MIPS32
+
+#define __UA_LIMIT      0x80000000UL
+
+#define __UA_ADDR       ".word"
+#define __UA_LA         "la"
+#define __UA_ADDU       "addu"
+#define __UA_t0         "$8"
+#define __UA_t1         "$9"
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+
+#define __UA_LIMIT      (- TASK_SIZE)
+
+#define __UA_ADDR       ".dword"
+#define __UA_LA         "dla"
+#define __UA_ADDU       "daddu"
+#define __UA_t0         "$12"
+#define __UA_t1         "$13"
+
+#endif /* CONFIG_MIPS64 */
+
+/*
+ * USER_DS is a bitmask that has the bits set that may not be set in a valid
+ * userspace address.  Note that we limit 32-bit userspace to 0x7fff8000 but
+ * the arithmetic we're doing only works if the limit is a power of two, so
+ * we use 0x80000000 here on 32-bit kernels.  If a process passes an invalid
+ * address in this range it's the process's problem, not ours :-)
+ */
+
+#define KERNEL_DS       ((mm_segment_t) { 0UL })
+#define USER_DS         ((mm_segment_t) { __UA_LIMIT })
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+
+/*
+ * Is a address valid? This does a straighforward calculation rather
+ * than tests.
+ *
+ * Address valid if:
+ *  - "addr" doesn't have any high-bits set
+ *  - AND "size" doesn't have any high-bits set
+ *  - AND "addr+size" doesn't have any high-bits set
+ *  - OR we are in kernel mode.
+ *
+ * __ua_size() is a trick to avoid runtime checking of positive constant
+ * sizes; for those we already know at compile time that the size is ok.
+ */
+#define __ua_size(size)                                                 \
+        ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size))
+
+/*
+ * access_ok: - Checks if a user space pointer is valid
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
+ *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
+ *        to write to a block, it is always safe to read from it.
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns true (nonzero) if the memory block may be valid, false (zero)
+ * if it is definitely invalid.
+ *
+ * Note that, depending on architecture, this function probably just
+ * checks that the pointer is in the user space range - after calling
+ * this function, memory access functions may still return -EFAULT.
+ */
+
+#define __access_mask get_fs().seg
+
+#define __access_ok(addr, size, mask)                                   \
+        (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0)
+
+#define access_ok(type, addr, size)                                     \
+        likely(__access_ok((unsigned long)(addr), (size),__access_mask))
+
+/*
+ * verify_area: - Obsolete/deprecated and will go away soon,
+ * use access_ok() instead.
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This function has been replaced by access_ok().
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns zero if the memory block may be valid, -EFAULT
+ * if it is definitely invalid.
+ *
+ * See access_ok() for more details.
+ */
+static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
+{
+        return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+/*
+ * put_user: - Write a simple value into user space.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user(x,ptr) \
+        __put_user_check((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * get_user: - Get a simple variable from user space.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define get_user(x,ptr) \
+        __get_user_check((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * __put_user: - Write a simple value into user space, with less checking.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define __put_user(x,ptr) \
+        __put_user_nocheck((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * __get_user: - Get a simple variable from user space, with less checking.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define __get_user(x,ptr) \
+        __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef __mips64
+#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err)
+#else
+#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err)
+#endif
+
+#define __get_user_nocheck(x,ptr,size)                                  \
+({                                                                      \
+        __typeof(*(ptr)) __gu_val = 0;                                  \
+        long __gu_addr;                                                 \
+        long __gu_err = 0;                                              \
+                                                                        \
+        might_sleep();                                                  \
+        __gu_addr = (long) (ptr);                                       \
+        switch (size) {                                                 \
+        case 1: __get_user_asm("lb", __gu_err); break;                  \
+        case 2: __get_user_asm("lh", __gu_err); break;                  \
+        case 4: __get_user_asm("lw", __gu_err); break;                  \
+        case 8: __GET_USER_DW(__gu_err); break;                         \
+        default: __get_user_unknown(); break;                           \
+        }                                                               \
+        x = (__typeof__(*(ptr))) __gu_val;                              \
+        __gu_err;                                                       \
+})
+
+#define __get_user_check(x,ptr,size)                                    \
+({                                                                      \
+        __typeof__(*(ptr)) __gu_val = 0;                                \
+        long __gu_addr;                                                 \
+        long __gu_err;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __gu_addr = (long) (ptr);                                       \
+        __gu_err = access_ok(VERIFY_READ, (void *) __gu_addr, size)     \
+                                ? 0 : -EFAULT;                          \
+                                                                        \
+        if (likely(!__gu_err)) {                                        \
+                switch (size) {                                         \
+                case 1: __get_user_asm("lb", __gu_err); break;          \
+                case 2: __get_user_asm("lh", __gu_err); break;          \
+                case 4: __get_user_asm("lw", __gu_err); break;          \
+                case 8: __GET_USER_DW(__gu_err); break;                 \
+                default: __get_user_unknown(); break;                   \
+                }                                                       \
+        }                                                               \
+        x = (__typeof__(*(ptr))) __gu_val;                              \
+        __gu_err;                                                       \
+})
+
+#define __get_user_asm(insn,__gu_err)                                   \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %1, %3                          \n"     \
+        "2:                                                     \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 3b                            \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=r" (__gu_val)                              \
+        : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT));         \
+})
+
+/*
+ * Get a long long 64 using 32 bit registers.
+ */
+#define __get_user_asm_ll32(__gu_err)                                   \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:     lw      %1, %3                                  \n"     \
+        "2:     lw      %D1, %4                                 \n"     \
+        "       move    %0, $0                                  \n"     \
+        "3:     .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %5                                  \n"     \
+        "       move    %1, $0                                  \n"     \
+        "       move    %D1, $0                                 \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=&r" (__gu_val)                             \
+        : "0" (__gu_err), "o" (__m(__gu_addr)),                         \
+          "o" (__m(__gu_addr + 4)), "i" (-EFAULT));                     \
+})
+
+extern void __get_user_unknown(void);
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef __mips64
+#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val)
+#else
+#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val)
+#endif
+
+#define __put_user_nocheck(x,ptr,size)                                  \
+({                                                                      \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        long __pu_addr;                                                 \
+        long __pu_err = 0;                                              \
+                                                                        \
+        might_sleep();                                                  \
+        __pu_val = (x);                                                 \
+        __pu_addr = (long) (ptr);                                       \
+        switch (size) {                                                 \
+        case 1: __put_user_asm("sb", __pu_val); break;                  \
+        case 2: __put_user_asm("sh", __pu_val); break;                  \
+        case 4: __put_user_asm("sw", __pu_val); break;                  \
+        case 8: __PUT_USER_DW(__pu_val); break;                         \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_check(x,ptr,size)                                    \
+({                                                                      \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        long __pu_addr;                                                 \
+        long __pu_err;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __pu_val = (x);                                                 \
+        __pu_addr = (long) (ptr);                                       \
+        __pu_err = access_ok(VERIFY_WRITE, (void *) __pu_addr, size)    \
+                                ? 0 : -EFAULT;                          \
+                                                                        \
+        if (likely(!__pu_err)) {                                        \
+                switch (size) {                                         \
+                case 1: __put_user_asm("sb", __pu_val); break;          \
+                case 2: __put_user_asm("sh", __pu_val); break;          \
+                case 4: __put_user_asm("sw", __pu_val); break;          \
+                case 8: __PUT_USER_DW(__pu_val); break;                 \
+                default: __put_user_unknown(); break;                   \
+                }                                                       \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_asm(insn, __pu_val)                                  \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
+        "2:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 3b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__pu_err)                                               \
+        : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)),        \
+          "i" (-EFAULT));                                               \
+})
+
+#define __put_user_asm_ll32(__pu_val)                                   \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "1:     sw      %2, %3          # __put_user_asm_ll32   \n"     \
+        "2:     sw      %D2, %4                                 \n"     \
+        "3:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %5                                  \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous"                                              \
+        : "=r" (__pu_err)                                               \
+        : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)),         \
+          "o" (__m(__pu_addr + 4)), "i" (-EFAULT));                     \
+})
+
+extern void __put_user_unknown(void);
+
+/*
+ * We're generating jump to subroutines which will be outside the range of
+ * jump instructions
+ */
+#ifdef MODULE
+#define __MODULE_JAL(destination)                                       \
+        ".set\tnoat\n\t"                                                \
+        __UA_LA "\t$1, " #destination "\n\t"                            \
+        "jalr\t$1\n\t"                                                  \
+        ".set\tat\n\t"
+#else
+#define __MODULE_JAL(destination)                                       \
+        "jal\t" #destination "\n\t"
+#endif
+
+extern size_t __copy_user(void *__to, const void *__from, size_t __n);
+
+#define __invoke_copy_to_user(to,from,n)                                \
+({                                                                      \
+        register void *__cu_to_r __asm__ ("$4");                        \
+        register const void *__cu_from_r __asm__ ("$5");                \
+        register long __cu_len_r __asm__ ("$6");                        \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        __MODULE_JAL(__copy_user)                                       \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+          "memory");                                                    \
+        __cu_len_r;                                                     \
+})
+
+/*
+ * __copy_to_user: - Copy a block of data into user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define __copy_to_user(to,from,n)                                       \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+        __cu_len;                                                       \
+})
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+/*
+ * copy_to_user: - Copy a block of data into user space.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define copy_to_user(to,from,n)                                         \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len))                 \
+                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
+                                                 __cu_len);             \
+        __cu_len;                                                       \
+})
+
+#define __invoke_copy_from_user(to,from,n)                              \
+({                                                                      \
+        register void *__cu_to_r __asm__ ("$4");                        \
+        register const void *__cu_from_r __asm__ ("$5");                \
+        register long __cu_len_r __asm__ ("$6");                        \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        ".set\tnoreorder\n\t"                                           \
+        __MODULE_JAL(__copy_user)                                       \
+        ".set\tnoat\n\t"                                                \
+        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
+        ".set\tat\n\t"                                                  \
+        ".set\treorder"                                                 \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+          "memory");                                                    \
+        __cu_len_r;                                                     \
+})
+
+/*
+ * __copy_from_user: - Copy a block of data from user space, with less checking. * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define __copy_from_user(to,from,n)                                     \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
+                                           __cu_len);                   \
+        __cu_len;                                                       \
+})
+
+/*
+ * copy_from_user: - Copy a block of data from user space.
+ * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define copy_from_user(to,from,n)                                       \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (access_ok(VERIFY_READ, __cu_from, __cu_len))                \
+                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        __cu_len;                                                       \
+})
+
+#define __copy_in_user(to, from, n)     __copy_from_user(to, from, n)
+
+#define copy_in_user(to,from,n)                                         \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \
+                   access_ok(VERIFY_WRITE, __cu_to, __cu_len)))         \
+                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        __cu_len;                                                       \
+})
+
+/*
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+static inline __kernel_size_t
+__clear_user(void *addr, __kernel_size_t size)
+{
+        __kernel_size_t res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, $0\n\t"
+                "move\t$6, %2\n\t"
+                __MODULE_JAL(__bzero)
+                "move\t%0, $6"
+                : "=r" (res)
+                : "r" (addr), "r" (size)
+                : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31");
+
+        return res;
+}
+
+#define clear_user(addr,n)                                              \
+({                                                                      \
+        void * __cl_addr = (addr);                                      \
+        unsigned long __cl_size = (n);                                  \
+        if (__cl_size && access_ok(VERIFY_WRITE,                        \
+                ((unsigned long)(__cl_addr)), __cl_size))               \
+                __cl_size = __clear_user(__cl_addr, __cl_size);         \
+        __cl_size;                                                      \
+})
+
+/*
+ * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ * Caller must check the specified block with access_ok() before calling
+ * this function.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+static inline long
+__strncpy_from_user(char *__to, const char *__from, long __len)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                "move\t$6, %3\n\t"
+                __MODULE_JAL(__strncpy_from_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (__to), "r" (__from), "r" (__len)
+                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+
+        return res;
+}
+
+/*
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+static inline long
+strncpy_from_user(char *__to, const char *__from, long __len)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                "move\t$6, %3\n\t"
+                __MODULE_JAL(__strncpy_from_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (__to), "r" (__from), "r" (__len)
+                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+
+        return res;
+}
+
+/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
+static inline long __strlen_user(const char *s)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                __MODULE_JAL(__strlen_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s)
+                : "$2", "$4", __UA_t0, "$31");
+
+        return res;
+}
+
+/*
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+static inline long strlen_user(const char *s)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                __MODULE_JAL(__strlen_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s)
+                : "$2", "$4", __UA_t0, "$31");
+
+        return res;
+}
+
+/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
+static inline long __strnlen_user(const char *s, long n)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                __MODULE_JAL(__strnlen_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s), "r" (n)
+                : "$2", "$4", "$5", __UA_t0, "$31");
+
+        return res;
+}
+
+/*
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+static inline long strnlen_user(const char *s, long n)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                __MODULE_JAL(__strnlen_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s), "r" (n)
+                : "$2", "$4", "$5", __UA_t0, "$31");
+
+        return res;
+}
+
+struct exception_table_entry
+{
+        unsigned long insn;
+        unsigned long nextinsn;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#endif /* _ASM_UACCESS_H */
diff --git a/include/asm-mips/ucontext.h b/include/asm-mips/ucontext.h
new file mode 100644
index 000000000000..8a4b20e88b81
--- /dev/null
+++ b/include/asm-mips/ucontext.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Low level exception handling
+ *
+ * Copyright (C) 1998, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_UCONTEXT_H
+#define _ASM_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* _ASM_UCONTEXT_H */
diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h
new file mode 100644
index 000000000000..a0042563838a
--- /dev/null
+++ b/include/asm-mips/unaligned.h
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_UNALIGNED_H
+#define _ASM_UNALIGNED_H
+
+#include <asm-generic/unaligned.h>
+
+#endif /* _ASM_UNALIGNED_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
new file mode 100644
index 000000000000..6d21cc964f76
--- /dev/null
+++ b/include/asm-mips/unistd.h
@@ -0,0 +1,1185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
+ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
+ */
+#ifndef _ASM_UNISTD_H
+#define _ASM_UNISTD_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Linux o32 style syscalls are in the range from 4000 to 4999.
+ */
+#define __NR_Linux                      4000
+#define __NR_syscall                    (__NR_Linux +   0)
+#define __NR_exit                       (__NR_Linux +   1)
+#define __NR_fork                       (__NR_Linux +   2)
+#define __NR_read                       (__NR_Linux +   3)
+#define __NR_write                      (__NR_Linux +   4)
+#define __NR_open                       (__NR_Linux +   5)
+#define __NR_close                      (__NR_Linux +   6)
+#define __NR_waitpid                    (__NR_Linux +   7)
+#define __NR_creat                      (__NR_Linux +   8)
+#define __NR_link                       (__NR_Linux +   9)
+#define __NR_unlink                     (__NR_Linux +  10)
+#define __NR_execve                     (__NR_Linux +  11)
+#define __NR_chdir                      (__NR_Linux +  12)
+#define __NR_time                       (__NR_Linux +  13)
+#define __NR_mknod                      (__NR_Linux +  14)
+#define __NR_chmod                      (__NR_Linux +  15)
+#define __NR_lchown                     (__NR_Linux +  16)
+#define __NR_break                      (__NR_Linux +  17)
+#define __NR_unused18                   (__NR_Linux +  18)
+#define __NR_lseek                      (__NR_Linux +  19)
+#define __NR_getpid                     (__NR_Linux +  20)
+#define __NR_mount                      (__NR_Linux +  21)
+#define __NR_umount                     (__NR_Linux +  22)
+#define __NR_setuid                     (__NR_Linux +  23)
+#define __NR_getuid                     (__NR_Linux +  24)
+#define __NR_stime                      (__NR_Linux +  25)
+#define __NR_ptrace                     (__NR_Linux +  26)
+#define __NR_alarm                      (__NR_Linux +  27)
+#define __NR_unused28                   (__NR_Linux +  28)
+#define __NR_pause                      (__NR_Linux +  29)
+#define __NR_utime                      (__NR_Linux +  30)
+#define __NR_stty                       (__NR_Linux +  31)
+#define __NR_gtty                       (__NR_Linux +  32)
+#define __NR_access                     (__NR_Linux +  33)
+#define __NR_nice                       (__NR_Linux +  34)
+#define __NR_ftime                      (__NR_Linux +  35)
+#define __NR_sync                       (__NR_Linux +  36)
+#define __NR_kill                       (__NR_Linux +  37)
+#define __NR_rename                     (__NR_Linux +  38)
+#define __NR_mkdir                      (__NR_Linux +  39)
+#define __NR_rmdir                      (__NR_Linux +  40)
+#define __NR_dup                        (__NR_Linux +  41)
+#define __NR_pipe                       (__NR_Linux +  42)
+#define __NR_times                      (__NR_Linux +  43)
+#define __NR_prof                       (__NR_Linux +  44)
+#define __NR_brk                        (__NR_Linux +  45)
+#define __NR_setgid                     (__NR_Linux +  46)
+#define __NR_getgid                     (__NR_Linux +  47)
+#define __NR_signal                     (__NR_Linux +  48)
+#define __NR_geteuid                    (__NR_Linux +  49)
+#define __NR_getegid                    (__NR_Linux +  50)
+#define __NR_acct                       (__NR_Linux +  51)
+#define __NR_umount2                    (__NR_Linux +  52)
+#define __NR_lock                       (__NR_Linux +  53)
+#define __NR_ioctl                      (__NR_Linux +  54)
+#define __NR_fcntl                      (__NR_Linux +  55)
+#define __NR_mpx                        (__NR_Linux +  56)
+#define __NR_setpgid                    (__NR_Linux +  57)
+#define __NR_ulimit                     (__NR_Linux +  58)
+#define __NR_unused59                   (__NR_Linux +  59)
+#define __NR_umask                      (__NR_Linux +  60)
+#define __NR_chroot                     (__NR_Linux +  61)
+#define __NR_ustat                      (__NR_Linux +  62)
+#define __NR_dup2                       (__NR_Linux +  63)
+#define __NR_getppid                    (__NR_Linux +  64)
+#define __NR_getpgrp                    (__NR_Linux +  65)
+#define __NR_setsid                     (__NR_Linux +  66)
+#define __NR_sigaction                  (__NR_Linux +  67)
+#define __NR_sgetmask                   (__NR_Linux +  68)
+#define __NR_ssetmask                   (__NR_Linux +  69)
+#define __NR_setreuid                   (__NR_Linux +  70)
+#define __NR_setregid                   (__NR_Linux +  71)
+#define __NR_sigsuspend                 (__NR_Linux +  72)
+#define __NR_sigpending                 (__NR_Linux +  73)
+#define __NR_sethostname                (__NR_Linux +  74)
+#define __NR_setrlimit                  (__NR_Linux +  75)
+#define __NR_getrlimit                  (__NR_Linux +  76)
+#define __NR_getrusage                  (__NR_Linux +  77)
+#define __NR_gettimeofday               (__NR_Linux +  78)
+#define __NR_settimeofday               (__NR_Linux +  79)
+#define __NR_getgroups                  (__NR_Linux +  80)
+#define __NR_setgroups                  (__NR_Linux +  81)
+#define __NR_reserved82                 (__NR_Linux +  82)
+#define __NR_symlink                    (__NR_Linux +  83)
+#define __NR_unused84                   (__NR_Linux +  84)
+#define __NR_readlink                   (__NR_Linux +  85)
+#define __NR_uselib                     (__NR_Linux +  86)
+#define __NR_swapon                     (__NR_Linux +  87)
+#define __NR_reboot                     (__NR_Linux +  88)
+#define __NR_readdir                    (__NR_Linux +  89)
+#define __NR_mmap                       (__NR_Linux +  90)
+#define __NR_munmap                     (__NR_Linux +  91)
+#define __NR_truncate                   (__NR_Linux +  92)
+#define __NR_ftruncate                  (__NR_Linux +  93)
+#define __NR_fchmod                     (__NR_Linux +  94)
+#define __NR_fchown                     (__NR_Linux +  95)
+#define __NR_getpriority                (__NR_Linux +  96)
+#define __NR_setpriority                (__NR_Linux +  97)
+#define __NR_profil                     (__NR_Linux +  98)
+#define __NR_statfs                     (__NR_Linux +  99)
+#define __NR_fstatfs                    (__NR_Linux + 100)
+#define __NR_ioperm                     (__NR_Linux + 101)
+#define __NR_socketcall                 (__NR_Linux + 102)
+#define __NR_syslog                     (__NR_Linux + 103)
+#define __NR_setitimer                  (__NR_Linux + 104)
+#define __NR_getitimer                  (__NR_Linux + 105)
+#define __NR_stat                       (__NR_Linux + 106)
+#define __NR_lstat                      (__NR_Linux + 107)
+#define __NR_fstat                      (__NR_Linux + 108)
+#define __NR_unused109                  (__NR_Linux + 109)
+#define __NR_iopl                       (__NR_Linux + 110)
+#define __NR_vhangup                    (__NR_Linux + 111)
+#define __NR_idle                       (__NR_Linux + 112)
+#define __NR_vm86                       (__NR_Linux + 113)
+#define __NR_wait4                      (__NR_Linux + 114)
+#define __NR_swapoff                    (__NR_Linux + 115)
+#define __NR_sysinfo                    (__NR_Linux + 116)
+#define __NR_ipc                        (__NR_Linux + 117)
+#define __NR_fsync                      (__NR_Linux + 118)
+#define __NR_sigreturn                  (__NR_Linux + 119)
+#define __NR_clone                      (__NR_Linux + 120)
+#define __NR_setdomainname              (__NR_Linux + 121)
+#define __NR_uname                      (__NR_Linux + 122)
+#define __NR_modify_ldt                 (__NR_Linux + 123)
+#define __NR_adjtimex                   (__NR_Linux + 124)
+#define __NR_mprotect                   (__NR_Linux + 125)
+#define __NR_sigprocmask                (__NR_Linux + 126)
+#define __NR_create_module              (__NR_Linux + 127)
+#define __NR_init_module                (__NR_Linux + 128)
+#define __NR_delete_module              (__NR_Linux + 129)
+#define __NR_get_kernel_syms            (__NR_Linux + 130)
+#define __NR_quotactl                   (__NR_Linux + 131)
+#define __NR_getpgid                    (__NR_Linux + 132)
+#define __NR_fchdir                     (__NR_Linux + 133)
+#define __NR_bdflush                    (__NR_Linux + 134)
+#define __NR_sysfs                      (__NR_Linux + 135)
+#define __NR_personality                (__NR_Linux + 136)
+#define __NR_afs_syscall                (__NR_Linux + 137) /* Syscall for Andrew File System */
+#define __NR_setfsuid                   (__NR_Linux + 138)
+#define __NR_setfsgid                   (__NR_Linux + 139)
+#define __NR__llseek                    (__NR_Linux + 140)
+#define __NR_getdents                   (__NR_Linux + 141)
+#define __NR__newselect                 (__NR_Linux + 142)
+#define __NR_flock                      (__NR_Linux + 143)
+#define __NR_msync                      (__NR_Linux + 144)
+#define __NR_readv                      (__NR_Linux + 145)
+#define __NR_writev                     (__NR_Linux + 146)
+#define __NR_cacheflush                 (__NR_Linux + 147)
+#define __NR_cachectl                   (__NR_Linux + 148)
+#define __NR_sysmips                    (__NR_Linux + 149)
+#define __NR_unused150                  (__NR_Linux + 150)
+#define __NR_getsid                     (__NR_Linux + 151)
+#define __NR_fdatasync                  (__NR_Linux + 152)
+#define __NR__sysctl                    (__NR_Linux + 153)
+#define __NR_mlock                      (__NR_Linux + 154)
+#define __NR_munlock                    (__NR_Linux + 155)
+#define __NR_mlockall                   (__NR_Linux + 156)
+#define __NR_munlockall                 (__NR_Linux + 157)
+#define __NR_sched_setparam             (__NR_Linux + 158)
+#define __NR_sched_getparam             (__NR_Linux + 159)
+#define __NR_sched_setscheduler         (__NR_Linux + 160)
+#define __NR_sched_getscheduler         (__NR_Linux + 161)
+#define __NR_sched_yield                (__NR_Linux + 162)
+#define __NR_sched_get_priority_max     (__NR_Linux + 163)
+#define __NR_sched_get_priority_min     (__NR_Linux + 164)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 165)
+#define __NR_nanosleep                  (__NR_Linux + 166)
+#define __NR_mremap                     (__NR_Linux + 167)
+#define __NR_accept                     (__NR_Linux + 168)
+#define __NR_bind                       (__NR_Linux + 169)
+#define __NR_connect                    (__NR_Linux + 170)
+#define __NR_getpeername                (__NR_Linux + 171)
+#define __NR_getsockname                (__NR_Linux + 172)
+#define __NR_getsockopt                 (__NR_Linux + 173)
+#define __NR_listen                     (__NR_Linux + 174)
+#define __NR_recv                       (__NR_Linux + 175)
+#define __NR_recvfrom                   (__NR_Linux + 176)
+#define __NR_recvmsg                    (__NR_Linux + 177)
+#define __NR_send                       (__NR_Linux + 178)
+#define __NR_sendmsg                    (__NR_Linux + 179)
+#define __NR_sendto                     (__NR_Linux + 180)
+#define __NR_setsockopt                 (__NR_Linux + 181)
+#define __NR_shutdown                   (__NR_Linux + 182)
+#define __NR_socket                     (__NR_Linux + 183)
+#define __NR_socketpair                 (__NR_Linux + 184)
+#define __NR_setresuid                  (__NR_Linux + 185)
+#define __NR_getresuid                  (__NR_Linux + 186)
+#define __NR_query_module               (__NR_Linux + 187)
+#define __NR_poll                       (__NR_Linux + 188)
+#define __NR_nfsservctl                 (__NR_Linux + 189)
+#define __NR_setresgid                  (__NR_Linux + 190)
+#define __NR_getresgid                  (__NR_Linux + 191)
+#define __NR_prctl                      (__NR_Linux + 192)
+#define __NR_rt_sigreturn               (__NR_Linux + 193)
+#define __NR_rt_sigaction               (__NR_Linux + 194)
+#define __NR_rt_sigprocmask             (__NR_Linux + 195)
+#define __NR_rt_sigpending              (__NR_Linux + 196)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 197)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 198)
+#define __NR_rt_sigsuspend              (__NR_Linux + 199)
+#define __NR_pread64                    (__NR_Linux + 200)
+#define __NR_pwrite64                   (__NR_Linux + 201)
+#define __NR_chown                      (__NR_Linux + 202)
+#define __NR_getcwd                     (__NR_Linux + 203)
+#define __NR_capget                     (__NR_Linux + 204)
+#define __NR_capset                     (__NR_Linux + 205)
+#define __NR_sigaltstack                (__NR_Linux + 206)
+#define __NR_sendfile                   (__NR_Linux + 207)
+#define __NR_getpmsg                    (__NR_Linux + 208)
+#define __NR_putpmsg                    (__NR_Linux + 209)
+#define __NR_mmap2                      (__NR_Linux + 210)
+#define __NR_truncate64                 (__NR_Linux + 211)
+#define __NR_ftruncate64                (__NR_Linux + 212)
+#define __NR_stat64                     (__NR_Linux + 213)
+#define __NR_lstat64                    (__NR_Linux + 214)
+#define __NR_fstat64                    (__NR_Linux + 215)
+#define __NR_pivot_root                 (__NR_Linux + 216)
+#define __NR_mincore                    (__NR_Linux + 217)
+#define __NR_madvise                    (__NR_Linux + 218)
+#define __NR_getdents64                 (__NR_Linux + 219)
+#define __NR_fcntl64                    (__NR_Linux + 220)
+#define __NR_reserved221                (__NR_Linux + 221)
+#define __NR_gettid                     (__NR_Linux + 222)
+#define __NR_readahead                  (__NR_Linux + 223)
+#define __NR_setxattr                   (__NR_Linux + 224)
+#define __NR_lsetxattr                  (__NR_Linux + 225)
+#define __NR_fsetxattr                  (__NR_Linux + 226)
+#define __NR_getxattr                   (__NR_Linux + 227)
+#define __NR_lgetxattr                  (__NR_Linux + 228)
+#define __NR_fgetxattr                  (__NR_Linux + 229)
+#define __NR_listxattr                  (__NR_Linux + 230)
+#define __NR_llistxattr                 (__NR_Linux + 231)
+#define __NR_flistxattr                 (__NR_Linux + 232)
+#define __NR_removexattr                (__NR_Linux + 233)
+#define __NR_lremovexattr               (__NR_Linux + 234)
+#define __NR_fremovexattr               (__NR_Linux + 235)
+#define __NR_tkill                      (__NR_Linux + 236)
+#define __NR_sendfile64                 (__NR_Linux + 237)
+#define __NR_futex                      (__NR_Linux + 238)
+#define __NR_sched_setaffinity          (__NR_Linux + 239)
+#define __NR_sched_getaffinity          (__NR_Linux + 240)
+#define __NR_io_setup                   (__NR_Linux + 241)
+#define __NR_io_destroy                 (__NR_Linux + 242)
+#define __NR_io_getevents               (__NR_Linux + 243)
+#define __NR_io_submit                  (__NR_Linux + 244)
+#define __NR_io_cancel                  (__NR_Linux + 245)
+#define __NR_exit_group                 (__NR_Linux + 246)
+#define __NR_lookup_dcookie             (__NR_Linux + 247)
+#define __NR_epoll_create               (__NR_Linux + 248)
+#define __NR_epoll_ctl                  (__NR_Linux + 249)
+#define __NR_epoll_wait                 (__NR_Linux + 250)
+#define __NR_remap_file_pages           (__NR_Linux + 251)
+#define __NR_set_tid_address            (__NR_Linux + 252)
+#define __NR_restart_syscall            (__NR_Linux + 253)
+#define __NR_fadvise64                  (__NR_Linux + 254)
+#define __NR_statfs64                   (__NR_Linux + 255)
+#define __NR_fstatfs64                  (__NR_Linux + 256)
+#define __NR_timer_create               (__NR_Linux + 257)
+#define __NR_timer_settime              (__NR_Linux + 258)
+#define __NR_timer_gettime              (__NR_Linux + 259)
+#define __NR_timer_getoverrun           (__NR_Linux + 260)
+#define __NR_timer_delete               (__NR_Linux + 261)
+#define __NR_clock_settime              (__NR_Linux + 262)
+#define __NR_clock_gettime              (__NR_Linux + 263)
+#define __NR_clock_getres               (__NR_Linux + 264)
+#define __NR_clock_nanosleep            (__NR_Linux + 265)
+#define __NR_tgkill                     (__NR_Linux + 266)
+#define __NR_utimes                     (__NR_Linux + 267)
+#define __NR_mbind                      (__NR_Linux + 268)
+#define __NR_get_mempolicy              (__NR_Linux + 269)
+#define __NR_set_mempolicy              (__NR_Linux + 270)
+#define __NR_mq_open                    (__NR_Linux + 271)
+#define __NR_mq_unlink                  (__NR_Linux + 272)
+#define __NR_mq_timedsend               (__NR_Linux + 273)
+#define __NR_mq_timedreceive            (__NR_Linux + 274)
+#define __NR_mq_notify                  (__NR_Linux + 275)
+#define __NR_mq_getsetattr              (__NR_Linux + 276)
+#define __NR_vserver                    (__NR_Linux + 277)
+#define __NR_waitid                     (__NR_Linux + 278)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 279) */
+#define __NR_add_key                    (__NR_Linux + 280)
+#define __NR_request_key                (__NR_Linux + 281)
+#define __NR_keyctl                     (__NR_Linux + 282)
+
+/*
+ * Offset of the last Linux o32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             282
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#define __NR_O32_Linux                  4000
+#define __NR_O32_Linux_syscalls         282
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/*
+ * Linux 64-bit syscalls are in the range from 5000 to 5999.
+ */
+#define __NR_Linux                      5000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_set_tid_address            (__NR_Linux + 212)
+#define __NR_restart_syscall            (__NR_Linux + 213)
+#define __NR_semtimedop                 (__NR_Linux + 214)
+#define __NR_fadvise64                  (__NR_Linux + 215)
+#define __NR_timer_create               (__NR_Linux + 216)
+#define __NR_timer_settime              (__NR_Linux + 217)
+#define __NR_timer_gettime              (__NR_Linux + 218)
+#define __NR_timer_getoverrun           (__NR_Linux + 219)
+#define __NR_timer_delete               (__NR_Linux + 220)
+#define __NR_clock_settime              (__NR_Linux + 221)
+#define __NR_clock_gettime              (__NR_Linux + 222)
+#define __NR_clock_getres               (__NR_Linux + 223)
+#define __NR_clock_nanosleep            (__NR_Linux + 224)
+#define __NR_tgkill                     (__NR_Linux + 225)
+#define __NR_utimes                     (__NR_Linux + 226)
+#define __NR_mbind                      (__NR_Linux + 227)
+#define __NR_get_mempolicy              (__NR_Linux + 228)
+#define __NR_set_mempolicy              (__NR_Linux + 229)
+#define __NR_mq_open                    (__NR_Linux + 230)
+#define __NR_mq_unlink                  (__NR_Linux + 231)
+#define __NR_mq_timedsend               (__NR_Linux + 232)
+#define __NR_mq_timedreceive            (__NR_Linux + 233)
+#define __NR_mq_notify                  (__NR_Linux + 234)
+#define __NR_mq_getsetattr              (__NR_Linux + 235)
+#define __NR_vserver                    (__NR_Linux + 236)
+#define __NR_waitid                     (__NR_Linux + 237)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 238) */
+#define __NR_add_key                    (__NR_Linux + 239)
+#define __NR_request_key                (__NR_Linux + 240)
+#define __NR_keyctl                     (__NR_Linux + 241)
+
+/*
+ * Offset of the last Linux 64-bit flavoured syscall
+ */
+#define __NR_Linux_syscalls             241
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define __NR_64_Linux                   5000
+#define __NR_64_Linux_syscalls          241
+
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+
+/*
+ * Linux N32 syscalls are in the range from 6000 to 6999.
+ */
+#define __NR_Linux                      6000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_fcntl64                    (__NR_Linux + 212)
+#define __NR_set_tid_address            (__NR_Linux + 213)
+#define __NR_restart_syscall            (__NR_Linux + 214)
+#define __NR_semtimedop                 (__NR_Linux + 215)
+#define __NR_fadvise64                  (__NR_Linux + 216)
+#define __NR_statfs64                   (__NR_Linux + 217)
+#define __NR_fstatfs64                  (__NR_Linux + 218)
+#define __NR_sendfile64                 (__NR_Linux + 219)
+#define __NR_timer_create               (__NR_Linux + 220)
+#define __NR_timer_settime              (__NR_Linux + 221)
+#define __NR_timer_gettime              (__NR_Linux + 222)
+#define __NR_timer_getoverrun           (__NR_Linux + 223)
+#define __NR_timer_delete               (__NR_Linux + 224)
+#define __NR_clock_settime              (__NR_Linux + 225)
+#define __NR_clock_gettime              (__NR_Linux + 226)
+#define __NR_clock_getres               (__NR_Linux + 227)
+#define __NR_clock_nanosleep            (__NR_Linux + 228)
+#define __NR_tgkill                     (__NR_Linux + 229)
+#define __NR_utimes                     (__NR_Linux + 230)
+#define __NR_mbind                      (__NR_Linux + 231)
+#define __NR_get_mempolicy              (__NR_Linux + 232)
+#define __NR_set_mempolicy              (__NR_Linux + 233)
+#define __NR_mq_open                    (__NR_Linux + 234)
+#define __NR_mq_unlink                  (__NR_Linux + 235)
+#define __NR_mq_timedsend               (__NR_Linux + 236)
+#define __NR_mq_timedreceive            (__NR_Linux + 237)
+#define __NR_mq_notify                  (__NR_Linux + 238)
+#define __NR_mq_getsetattr              (__NR_Linux + 239)
+#define __NR_vserver                    (__NR_Linux + 240)
+#define __NR_waitid                     (__NR_Linux + 241)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 242) */
+#define __NR_add_key                    (__NR_Linux + 243)
+#define __NR_request_key                (__NR_Linux + 244)
+#define __NR_keyctl                     (__NR_Linux + 245)
+
+/*
+ * Offset of the last N32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             245
+
+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#define __NR_N32_Linux                  6000
+#define __NR_N32_Linux_syscalls         245
+
+#ifndef __ASSEMBLY__
+
+/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
+#define _syscall0(type,name) \
+type name(void) \
+{ \
+        register unsigned long __a3 asm("$7"); \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %2\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "=r" (__a3) \
+        : "i" (__NR_##name) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+/*
+ * DANGER: This macro isn't usable for the pipe(2) call
+ * which has a unusual return convention.
+ */
+#define _syscall1(type,name,atype,a) \
+type name(atype a) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a3 asm("$7"); \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %3\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "=r" (__a3) \
+        : "r" (__a0), "i" (__NR_##name) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#define _syscall2(type,name,atype,a,btype,b) \
+type name(atype a, btype b) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a3 asm("$7"); \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %4\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "=r" (__a3) \
+        : "r" (__a0), "r" (__a1), "i" (__NR_##name) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#define _syscall3(type,name,atype,a,btype,b,ctype,c) \
+type name(atype a, btype b, ctype c) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7"); \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %5\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "=r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
+type name(atype a, btype b, ctype c, dtype d) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7") = (unsigned long) d; \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %5\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "+r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+
+/*
+ * Using those means your brain needs more than an oil change ;-)
+ */
+
+#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
+type name(atype a, btype b, ctype c, dtype d, etype e) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7") = (unsigned long) d; \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "lw\t$2, %6\n\t" \
+        "subu\t$29, 32\n\t" \
+        "sw\t$2, 16($29)\n\t" \
+        "li\t$2, %5\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        "addiu\t$29, 32\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "+r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \
+          "m" ((unsigned long)e) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
+type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7") = (unsigned long) d; \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "lw\t$2, %6\n\t" \
+        "lw\t$8, %7\n\t" \
+        "subu\t$29, 32\n\t" \
+        "sw\t$2, 16($29)\n\t" \
+        "sw\t$8, 20($29)\n\t" \
+        "li\t$2, %5\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        "addiu\t$29, 32\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "+r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \
+          "m" ((unsigned long)e), "m" ((unsigned long)f) \
+        : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
+
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+
+#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
+type name (atype a,btype b,ctype c,dtype d,etype e) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7") = (unsigned long) d; \
+        register unsigned long __a4 asm("$8") = (unsigned long) e; \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %6\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "+r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##name) \
+        : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
+type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
+{ \
+        register unsigned long __a0 asm("$4") = (unsigned long) a; \
+        register unsigned long __a1 asm("$5") = (unsigned long) b; \
+        register unsigned long __a2 asm("$6") = (unsigned long) c; \
+        register unsigned long __a3 asm("$7") = (unsigned long) d; \
+        register unsigned long __a4 asm("$8") = (unsigned long) e; \
+        register unsigned long __a5 asm("$9") = (unsigned long) f; \
+        unsigned long __v0; \
+        \
+        __asm__ volatile ( \
+        ".set\tnoreorder\n\t" \
+        "li\t$2, %7\t\t\t# " #name "\n\t" \
+        "syscall\n\t" \
+        "move\t%0, $2\n\t" \
+        ".set\treorder" \
+        : "=&r" (__v0), "+r" (__a3) \
+        : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "r" (__a5), \
+          "i" (__NR_##name) \
+        : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+          "memory"); \
+        \
+        if (__a3 == 0) \
+                return (type) __v0; \
+        errno = __v0; \
+        return (type) -1; \
+}
+
+#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+# ifndef __mips64
+#  define __ARCH_WANT_STAT64
+# endif
+# ifdef CONFIG_MIPS32
+#  define __ARCH_WANT_SYS_TIME
+# endif
+# ifdef CONFIG_MIPS32_O32
+#  define __ARCH_WANT_COMPAT_SYS_TIME
+# endif
+#endif
+
+#ifdef __KERNEL_SYSCALLS__
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+#include <asm/sim.h>
+
+/*
+ * we need this inline - forking from kernel space will result
+ * in NO COPY ON WRITE (!!!), until an execve is executed. This
+ * is no problem, but for the stack. This is handled by not letting
+ * main() use the stack at all after fork(). Thus, no function
+ * calls - which means inline code for fork too, as otherwise we
+ * would use the stack upon exit from 'fork()'.
+ *
+ * Actually only pause and fork are needed inline, so that there
+ * won't be any messing with the stack from main(), but we define
+ * some others too.
+ */
+static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
+
+asmlinkage unsigned long sys_mmap(
+                                unsigned long addr, size_t len,
+                                int prot, int flags,
+                                int fd, off_t offset);
+asmlinkage long sys_mmap2(
+                        unsigned long addr, unsigned long len,
+                        unsigned long prot, unsigned long flags,
+                        unsigned long fd, unsigned long pgoff);
+asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs);
+asmlinkage int sys_pipe(nabi_no_regargs struct pt_regs regs);
+asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
+struct sigaction;
+asmlinkage long sys_rt_sigaction(int sig,
+                                const struct sigaction __user *act,
+                                struct sigaction __user *oact,
+                                size_t sigsetsize);
+
+#endif /* __KERNEL_SYSCALLS__ */
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
+
+#endif /* _ASM_UNISTD_H */
diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h
new file mode 100644
index 000000000000..89bf8b4cab3c
--- /dev/null
+++ b/include/asm-mips/user.h
@@ -0,0 +1,58 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_USER_H
+#define _ASM_USER_H
+
+#include <asm/page.h>
+#include <asm/reg.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd, NOT the irix-core).  The file
+ * contents are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+struct user {
+        unsigned long   regs[EF_SIZE /          /* integer and fp regs */
+                        sizeof(unsigned long) + 64];
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        struct regs *   u_ar0;                  /* help gdb find registers */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ASM_USER_H */
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
new file mode 100644
index 000000000000..6b35cf054c79
--- /dev/null
+++ b/include/asm-mips/vga.h
@@ -0,0 +1,19 @@
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+#ifndef _ASM_VGA_H
+#define _ASM_VGA_H
+
+/*
+ *      On the PC, we can just recalculate addresses and then
+ *      access the videoram directly without any black magic.
+ */
+
+#define VGA_MAP_MEM(x)  (0xb0000000L + (unsigned long)(x))
+
+#define vga_readb(x)    (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif /* _ASM_VGA_H */
diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h
new file mode 100644
index 000000000000..4bf0ea970ed0
--- /dev/null
+++ b/include/asm-mips/vr4181/irq.h
@@ -0,0 +1,122 @@
+/*
+ * Macros for vr4181 IRQ numbers.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+/*
+ * Strategy:
+ *
+ * Vr4181 has conceptually three levels of interrupt controllers:
+ *  1. the CPU itself with 8 intr level.
+ *  2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
+ *  3. GPIO interrupts : forwarding external interrupts to sys intr controller
+ */
+
+/* decide the irq block assignment */
+#define VR4181_NUM_CPU_IRQ      8
+#define VR4181_NUM_SYS_IRQ      32
+#define VR4181_NUM_GPIO_IRQ     16
+
+#define VR4181_IRQ_BASE         0
+
+#define VR4181_CPU_IRQ_BASE     VR4181_IRQ_BASE
+#define VR4181_SYS_IRQ_BASE     (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
+#define VR4181_GPIO_IRQ_BASE    (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
+
+/* CPU interrupts */
+
+/*
+   IP0 - Software interrupt
+   IP1 - Software interrupt
+   IP2 - All but battery, high speed modem, and real time clock
+   IP3 - RTC Long1 (system timer)
+   IP4 - RTC Long2
+   IP5 - High Speed Modem (unused on VR4181)
+   IP6 - Unused
+   IP7 - Timer interrupt from CPO_COMPARE
+*/
+
+#define VR4181_IRQ_SW1       (VR4181_CPU_IRQ_BASE + 0)
+#define VR4181_IRQ_SW2       (VR4181_CPU_IRQ_BASE + 1)
+#define VR4181_IRQ_INT0      (VR4181_CPU_IRQ_BASE + 2)
+#define VR4181_IRQ_INT1      (VR4181_CPU_IRQ_BASE + 3)
+#define VR4181_IRQ_INT2      (VR4181_CPU_IRQ_BASE + 4)
+#define VR4181_IRQ_INT3      (VR4181_CPU_IRQ_BASE + 5)
+#define VR4181_IRQ_INT4      (VR4181_CPU_IRQ_BASE + 6)
+#define VR4181_IRQ_TIMER     (VR4181_CPU_IRQ_BASE + 7)
+
+
+/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
+
+/*
+   IP2 - same as VR4181_IRQ_INT1
+   IP8 - This is a cascade to GPIO IRQ's. Do not use.
+   IP16 - same as VR4181_IRQ_INT2
+   IP18 - CompactFlash
+*/
+
+#define VR4181_IRQ_BATTERY   (VR4181_SYS_IRQ_BASE + 0)
+#define VR4181_IRQ_POWER     (VR4181_SYS_IRQ_BASE + 1)
+#define VR4181_IRQ_RTCL1     (VR4181_SYS_IRQ_BASE + 2)
+#define VR4181_IRQ_ETIMER    (VR4181_SYS_IRQ_BASE + 3)
+#define VR4181_IRQ_RFU12     (VR4181_SYS_IRQ_BASE + 4)
+#define VR4181_IRQ_PIU       (VR4181_SYS_IRQ_BASE + 5)
+#define VR4181_IRQ_AIU       (VR4181_SYS_IRQ_BASE + 6)
+#define VR4181_IRQ_KIU       (VR4181_SYS_IRQ_BASE + 7)
+#define VR4181_IRQ_GIU       (VR4181_SYS_IRQ_BASE + 8)
+#define VR4181_IRQ_SIU       (VR4181_SYS_IRQ_BASE + 9)
+#define VR4181_IRQ_RFU18     (VR4181_SYS_IRQ_BASE + 10)
+#define VR4181_IRQ_SOFT      (VR4181_SYS_IRQ_BASE + 11)
+#define VR4181_IRQ_RFU20     (VR4181_SYS_IRQ_BASE + 12)
+#define VR4181_IRQ_DOZEPIU   (VR4181_SYS_IRQ_BASE + 13)
+#define VR4181_IRQ_RFU22     (VR4181_SYS_IRQ_BASE + 14)
+#define VR4181_IRQ_RFU23     (VR4181_SYS_IRQ_BASE + 15)
+#define VR4181_IRQ_RTCL2     (VR4181_SYS_IRQ_BASE + 16)
+#define VR4181_IRQ_LED       (VR4181_SYS_IRQ_BASE + 17)
+#define VR4181_IRQ_ECU       (VR4181_SYS_IRQ_BASE + 18)
+#define VR4181_IRQ_CSU       (VR4181_SYS_IRQ_BASE + 19)
+#define VR4181_IRQ_USB       (VR4181_SYS_IRQ_BASE + 20)
+#define VR4181_IRQ_DMA       (VR4181_SYS_IRQ_BASE + 21)
+#define VR4181_IRQ_LCD       (VR4181_SYS_IRQ_BASE + 22)
+#define VR4181_IRQ_RFU31     (VR4181_SYS_IRQ_BASE + 23)
+#define VR4181_IRQ_RFU32     (VR4181_SYS_IRQ_BASE + 24)
+#define VR4181_IRQ_RFU33     (VR4181_SYS_IRQ_BASE + 25)
+#define VR4181_IRQ_RFU34     (VR4181_SYS_IRQ_BASE + 26)
+#define VR4181_IRQ_RFU35     (VR4181_SYS_IRQ_BASE + 27)
+#define VR4181_IRQ_RFU36     (VR4181_SYS_IRQ_BASE + 28)
+#define VR4181_IRQ_RFU37     (VR4181_SYS_IRQ_BASE + 29)
+#define VR4181_IRQ_RFU38     (VR4181_SYS_IRQ_BASE + 30)
+#define VR4181_IRQ_RFU39     (VR4181_SYS_IRQ_BASE + 31)
+
+/* Cascaded from VR4181_IRQ_GIU */
+#define VR4181_IRQ_GPIO0     (VR4181_GPIO_IRQ_BASE + 0)
+#define VR4181_IRQ_GPIO1     (VR4181_GPIO_IRQ_BASE + 1)
+#define VR4181_IRQ_GPIO2     (VR4181_GPIO_IRQ_BASE + 2)
+#define VR4181_IRQ_GPIO3     (VR4181_GPIO_IRQ_BASE + 3)
+#define VR4181_IRQ_GPIO4     (VR4181_GPIO_IRQ_BASE + 4)
+#define VR4181_IRQ_GPIO5     (VR4181_GPIO_IRQ_BASE + 5)
+#define VR4181_IRQ_GPIO6     (VR4181_GPIO_IRQ_BASE + 6)
+#define VR4181_IRQ_GPIO7     (VR4181_GPIO_IRQ_BASE + 7)
+#define VR4181_IRQ_GPIO8     (VR4181_GPIO_IRQ_BASE + 8)
+#define VR4181_IRQ_GPIO9     (VR4181_GPIO_IRQ_BASE + 9)
+#define VR4181_IRQ_GPIO10    (VR4181_GPIO_IRQ_BASE + 10)
+#define VR4181_IRQ_GPIO11    (VR4181_GPIO_IRQ_BASE + 11)
+#define VR4181_IRQ_GPIO12    (VR4181_GPIO_IRQ_BASE + 12)
+#define VR4181_IRQ_GPIO13    (VR4181_GPIO_IRQ_BASE + 13)
+#define VR4181_IRQ_GPIO14    (VR4181_GPIO_IRQ_BASE + 14)
+#define VR4181_IRQ_GPIO15    (VR4181_GPIO_IRQ_BASE + 15)
+
+
+// Alternative to above GPIO IRQ defines
+#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
+
+#define VR4181_IRQ_MAX       (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
+                              VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h
new file mode 100644
index 000000000000..5c5d60741515
--- /dev/null
+++ b/include/asm-mips/vr4181/vr4181.h
@@ -0,0 +1,413 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Michael Klar
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ */
+#ifndef __ASM_VR4181_VR4181_H
+#define __ASM_VR4181_VR4181_H
+
+#include <asm/addrspace.h>
+
+#include <asm/vr4181/irq.h>
+
+#ifndef __ASSEMBLY__
+#define __preg8         (volatile unsigned char*)
+#define __preg16        (volatile unsigned short*)
+#define __preg32        (volatile unsigned int*)
+#else
+#define __preg8
+#define __preg16
+#define __preg32
+#endif
+
+// Embedded CPU peripheral registers
+// Note that many of the registers have different physical address for VR4181
+
+// Bus Control Unit (BCU)
+#define VR4181_BCUCNTREG1       __preg16(KSEG1 + 0x0A000000)    /* BCU control register 1 (R/W) */
+#define VR4181_CMUCLKMSK        __preg16(KSEG1 + 0x0A000004)    /* Clock mask register (R/W) */
+#define VR4181_CMUCLKMSK_MSKCSUPCLK  0x0040
+#define VR4181_CMUCLKMSK_MSKAIUPCLK  0x0020
+#define VR4181_CMUCLKMSK_MSKPIUPCLK  0x0010
+#define VR4181_CMUCLKMSK_MSKADUPCLK  0x0008
+#define VR4181_CMUCLKMSK_MSKSIU18M   0x0004
+#define VR4181_CMUCLKMSK_MSKADU18M   0x0002
+#define VR4181_CMUCLKMSK_MSKUSB      0x0001
+#define VR4181_CMUCLKMSK_MSKSIU      VR4181_CMUCLKMSK_MSKSIU18M
+#define VR4181_BCUSPEEDREG      __preg16(KSEG1 + 0x0A00000C)    /* BCU access time parameter (R/W) */
+#define VR4181_BCURFCNTREG      __preg16(KSEG1 + 0x0A000010)    /* BCU refresh control register (R/W) */
+#define VR4181_REVIDREG         __preg16(KSEG1 + 0x0A000014)    /* Revision ID register (R) */
+#define VR4181_CLKSPEEDREG      __preg16(KSEG1 + 0x0A000018)    /* Clock speed register (R) */
+#define VR4181_EDOMCYTREG       __preg16(KSEG1 + 0x0A000300)    /* Memory cycle timing register (R/W) */
+#define VR4181_MEMCFG_REG       __preg16(KSEG1 + 0x0A000304)    /* Memory configuration register (R/W) */
+#define VR4181_MODE_REG         __preg16(KSEG1 + 0x0A000308)    /* SDRAM mode register (R/W) */
+#define VR4181_SDTIMINGREG      __preg16(KSEG1 + 0x0A00030C)    /* SDRAM timing register (R/W) */
+
+// DMA Control Unit (DCU)
+#define VR4181_MICDEST1REG1     __preg16(KSEG1 + 0x0A000020)    /* Microphone destination 1 address register 1 (R/W) */
+#define VR4181_MICDEST1REG2     __preg16(KSEG1 + 0x0A000022)    /* Microphone destination 1 address register 2 (R/W) */
+#define VR4181_MICDEST2REG1     __preg16(KSEG1 + 0x0A000024)    /* Microphone destination 2 address register 1 (R/W) */
+#define VR4181_MICDEST2REG2     __preg16(KSEG1 + 0x0A000026)    /* Microphone destination 2 address register 2 (R/W) */
+#define VR4181_SPKRRC1REG1      __preg16(KSEG1 + 0x0A000028)    /* Speaker Source 1 address register 1 (R/W) */
+#define VR4181_SPKRRC1REG2      __preg16(KSEG1 + 0x0A00002A)    /* Speaker Source 1 address register 2 (R/W) */
+#define VR4181_SPKRRC2REG1      __preg16(KSEG1 + 0x0A00002C)    /* Speaker Source 2 address register 1 (R/W) */
+#define VR4181_SPKRRC2REG2      __preg16(KSEG1 + 0x0A00002E)    /* Speaker Source 2 address register 2 (R/W) */
+#define VR4181_DMARSTREG        __preg16(KSEG1 + 0x0A000040)    /* DMA Reset register (R/W) */
+#define VR4181_AIUDMAMSKREG     __preg16(KSEG1 + 0x0A000046)    /* Audio DMA mask register (R/W) */
+#define VR4181_USBDMAMSKREG     __preg16(KSEG1 + 0x0A000600)    /* USB DMA Mask register (R/W) */
+#define VR4181_USBRXS1AREG1     __preg16(KSEG1 + 0x0A000602)    /* USB Rx source 1 address register 1 (R/W) */
+#define VR4181_USBRXS1AREG2     __preg16(KSEG1 + 0x0A000604)    /* USB Rx source 1 address register 2 (R/W) */
+#define VR4181_USBRXS2AREG1     __preg16(KSEG1 + 0x0A000606)    /* USB Rx source 2 address register 1 (R/W) */
+#define VR4181_USBRXS2AREG2     __preg16(KSEG1 + 0x0A000608)    /* USB Rx source 2 address register 2 (R/W) */
+#define VR4181_USBTXS1AREG1     __preg16(KSEG1 + 0x0A00060A)    /* USB Tx source 1 address register 1 (R/W) */
+#define VR4181_USBTXS1AREG2     __preg16(KSEG1 + 0x0A00060C)    /* USB Tx source 1 address register 2 (R/W) */
+#define VR4181_USBTXS2AREG1     __preg16(KSEG1 + 0x0A00060E)    /* USB Tx source 2 address register 1 (R/W) */
+#define VR4181_USBTXS2AREG2     __preg16(KSEG1 + 0x0A000610)    /* USB Tx source 2 address register 2 (R/W) */
+#define VR4181_USBRXD1AREG1     __preg16(KSEG1 + 0x0A00062A)    /* USB Rx destination 1 address register 1 (R/W) */
+#define VR4181_USBRXD1AREG2     __preg16(KSEG1 + 0x0A00062C)    /* USB Rx destination 1 address register 2 (R/W) */
+#define VR4181_USBRXD2AREG1     __preg16(KSEG1 + 0x0A00062E)    /* USB Rx destination 2 address register 1 (R/W) */
+#define VR4181_USBRXD2AREG2     __preg16(KSEG1 + 0x0A000630)    /* USB Rx destination 2 address register 2 (R/W) */
+#define VR4181_USBTXD1AREG1     __preg16(KSEG1 + 0x0A000632)    /* USB Tx destination 1 address register 1 (R/W) */
+#define VR4181_USBTXD1AREG2     __preg16(KSEG1 + 0x0A000634)    /* USB Tx destination 1 address register 2 (R/W) */
+#define VR4181_USBTXD2AREG1     __preg16(KSEG1 + 0x0A000636)    /* USB Tx destination 2 address register 1 (R/W) */
+#define VR4181_USBTXD2AREG2     __preg16(KSEG1 + 0x0A000638)    /* USB Tx destination 2 address register 2 (R/W) */
+#define VR4181_RxRCLENREG       __preg16(KSEG1 + 0x0A000652)    /* USB Rx record length register (R/W) */
+#define VR4181_TxRCLENREG       __preg16(KSEG1 + 0x0A000654)    /* USB Tx record length register (R/W) */
+#define VR4181_MICRCLENREG      __preg16(KSEG1 + 0x0A000658)    /* Microphone record length register (R/W) */
+#define VR4181_SPKRCLENREG      __preg16(KSEG1 + 0x0A00065A)    /* Speaker record length register (R/W) */
+#define VR4181_USBCFGREG        __preg16(KSEG1 + 0x0A00065C)    /* USB configuration register (R/W) */
+#define VR4181_MICDMACFGREG     __preg16(KSEG1 + 0x0A00065E)    /* Microphone DMA configuration register (R/W) */
+#define VR4181_SPKDMACFGREG     __preg16(KSEG1 + 0x0A000660)    /* Speaker DMA configuration register (R/W) */
+#define VR4181_DMAITRQREG       __preg16(KSEG1 + 0x0A000662)    /* DMA interrupt request register (R/W) */
+#define VR4181_DMACLTREG        __preg16(KSEG1 + 0x0A000664)    /* DMA control register (R/W) */
+#define VR4181_DMAITMKREG       __preg16(KSEG1 + 0x0A000666)    /* DMA interrupt mask register (R/W) */
+
+// ISA Bridge
+#define VR4181_ISABRGCTL        __preg16(KSEG1 + 0x0B0002C0)    /* ISA Bridge Control Register (R/W) */
+#define VR4181_ISABRGSTS        __preg16(KSEG1 + 0x0B0002C2)    /* ISA Bridge Status Register (R/W) */
+#define VR4181_XISACTL          __preg16(KSEG1 + 0x0B0002C4)    /* External ISA Control Register (R/W) */
+
+// Clocked Serial Interface (CSI)
+#define VR4181_CSIMODE          __preg16(KSEG1 + 0x0B000900)    /* CSI Mode Register (R/W) */
+#define VR4181_CSIRXDATA        __preg16(KSEG1 + 0x0B000902)    /* CSI Receive Data Register (R) */
+#define VR4181_CSITXDATA        __preg16(KSEG1 + 0x0B000904)    /* CSI Transmit Data Register (R/W) */
+#define VR4181_CSILSTAT         __preg16(KSEG1 + 0x0B000906)    /* CSI Line Status Register (R/W) */
+#define VR4181_CSIINTMSK        __preg16(KSEG1 + 0x0B000908)    /* CSI Interrupt Mask Register (R/W) */
+#define VR4181_CSIINTSTAT       __preg16(KSEG1 + 0x0B00090a)    /* CSI Interrupt Status Register (R/W) */
+#define VR4181_CSITXBLEN        __preg16(KSEG1 + 0x0B00090c)    /* CSI Transmit Burst Length Register (R/W) */
+#define VR4181_CSIRXBLEN        __preg16(KSEG1 + 0x0B00090e)    /* CSI Receive Burst Length Register (R/W) */
+
+// Interrupt Control Unit (ICU)
+#define VR4181_SYSINT1REG       __preg16(KSEG1 + 0x0A000080)    /* Level 1 System interrupt register 1 (R) */
+#define VR4181_MSYSINT1REG      __preg16(KSEG1 + 0x0A00008C)    /* Level 1 mask system interrupt register 1 (R/W) */
+#define VR4181_NMIREG           __preg16(KSEG1 + 0x0A000098)    /* NMI register (R/W) */
+#define VR4181_SOFTINTREG       __preg16(KSEG1 + 0x0A00009A)    /* Software interrupt register (R/W) */
+#define VR4181_SYSINT2REG       __preg16(KSEG1 + 0x0A000200)    /* Level 1 System interrupt register 2 (R) */
+#define VR4181_MSYSINT2REG      __preg16(KSEG1 + 0x0A000206)    /* Level 1 mask system interrupt register 2 (R/W) */
+#define VR4181_PIUINTREGro      __preg16(KSEG1 + 0x0B000082)    /* Level 2 PIU interrupt register (R) */
+#define VR4181_AIUINTREG        __preg16(KSEG1 + 0x0B000084)    /* Level 2 AIU interrupt register (R) */
+#define VR4181_MPIUINTREG       __preg16(KSEG1 + 0x0B00008E)    /* Level 2 mask PIU interrupt register (R/W) */
+#define VR4181_MAIUINTREG       __preg16(KSEG1 + 0x0B000090)    /* Level 2 mask AIU interrupt register (R/W) */
+#define VR4181_MKIUINTREG       __preg16(KSEG1 + 0x0B000092)    /* Level 2 mask KIU interrupt register (R/W) */
+#define VR4181_KIUINTREG        __preg16(KSEG1 + 0x0B000198)    /* Level 2 KIU interrupt register (R) */
+
+// Power Management Unit (PMU)
+#define VR4181_PMUINTREG        __preg16(KSEG1 + 0x0B0000A0)    /* PMU Status Register (R/W) */
+#define VR4181_PMUINT_POWERSW  0x1      /* Power switch */
+#define VR4181_PMUINT_BATT     0x2      /* Low batt during normal operation */
+#define VR4181_PMUINT_DEADMAN  0x4      /* Deadman's switch */
+#define VR4181_PMUINT_RESET    0x8      /* Reset switch */
+#define VR4181_PMUINT_RTCRESET 0x10     /* RTC Reset */
+#define VR4181_PMUINT_TIMEOUT  0x20     /* HAL Timer Reset */
+#define VR4181_PMUINT_BATTLOW  0x100    /* Battery low */
+#define VR4181_PMUINT_RTC      0x200    /* RTC Alarm */
+#define VR4181_PMUINT_DCD      0x400    /* DCD# */
+#define VR4181_PMUINT_GPIO0    0x1000   /* GPIO0 */
+#define VR4181_PMUINT_GPIO1    0x2000   /* GPIO1 */
+#define VR4181_PMUINT_GPIO2    0x4000   /* GPIO2 */
+#define VR4181_PMUINT_GPIO3    0x8000   /* GPIO3 */
+
+#define VR4181_PMUCNTREG        __preg16(KSEG1 + 0x0B0000A2)    /* PMU Control Register (R/W) */
+#define VR4181_PMUWAITREG       __preg16(KSEG1 + 0x0B0000A8)    /* PMU Wait Counter Register (R/W) */
+#define VR4181_PMUDIVREG        __preg16(KSEG1 + 0x0B0000AC)    /* PMU Divide Mode Register (R/W) */
+#define VR4181_DRAMHIBCTL       __preg16(KSEG1 + 0x0B0000B2)    /* DRAM Hibernate Control Register (R/W) */
+
+// Real Time Clock Unit (RTC)
+#define VR4181_ETIMELREG        __preg16(KSEG1 + 0x0B0000C0)    /* Elapsed Time L Register (R/W) */
+#define VR4181_ETIMEMREG        __preg16(KSEG1 + 0x0B0000C2)    /* Elapsed Time M Register (R/W) */
+#define VR4181_ETIMEHREG        __preg16(KSEG1 + 0x0B0000C4)    /* Elapsed Time H Register (R/W) */
+#define VR4181_ECMPLREG         __preg16(KSEG1 + 0x0B0000C8)    /* Elapsed Compare L Register (R/W) */
+#define VR4181_ECMPMREG         __preg16(KSEG1 + 0x0B0000CA)    /* Elapsed Compare M Register (R/W) */
+#define VR4181_ECMPHREG         __preg16(KSEG1 + 0x0B0000CC)    /* Elapsed Compare H Register (R/W) */
+#define VR4181_RTCL1LREG        __preg16(KSEG1 + 0x0B0000D0)    /* RTC Long 1 L Register (R/W) */
+#define VR4181_RTCL1HREG        __preg16(KSEG1 + 0x0B0000D2)    /* RTC Long 1 H Register (R/W) */
+#define VR4181_RTCL1CNTLREG     __preg16(KSEG1 + 0x0B0000D4)    /* RTC Long 1 Count L Register (R) */
+#define VR4181_RTCL1CNTHREG     __preg16(KSEG1 + 0x0B0000D6)    /* RTC Long 1 Count H Register (R) */
+#define VR4181_RTCL2LREG        __preg16(KSEG1 + 0x0B0000D8)    /* RTC Long 2 L Register (R/W) */
+#define VR4181_RTCL2HREG        __preg16(KSEG1 + 0x0B0000DA)    /* RTC Long 2 H Register (R/W) */
+#define VR4181_RTCL2CNTLREG     __preg16(KSEG1 + 0x0B0000DC)    /* RTC Long 2 Count L Register (R) */
+#define VR4181_RTCL2CNTHREG     __preg16(KSEG1 + 0x0B0000DE)    /* RTC Long 2 Count H Register (R) */
+#define VR4181_RTCINTREG        __preg16(KSEG1 + 0x0B0001DE)    /* RTC Interrupt Register (R/W) */
+
+// Deadman's Switch Unit (DSU)
+#define VR4181_DSUCNTREG        __preg16(KSEG1 + 0x0B0000E0)    /* DSU Control Register (R/W) */
+#define VR4181_DSUSETREG        __preg16(KSEG1 + 0x0B0000E2)    /* DSU Dead Time Set Register (R/W) */
+#define VR4181_DSUCLRREG        __preg16(KSEG1 + 0x0B0000E4)    /* DSU Clear Register (W) */
+#define VR4181_DSUTIMREG        __preg16(KSEG1 + 0x0B0000E6)    /* DSU Elapsed Time Register (R/W) */
+
+// General Purpose I/O Unit (GIU)
+#define VR4181_GPMD0REG         __preg16(KSEG1 + 0x0B000300)    /* GPIO Mode 0 Register (R/W) */
+#define VR4181_GPMD1REG         __preg16(KSEG1 + 0x0B000302)    /* GPIO Mode 1 Register (R/W) */
+#define VR4181_GPMD2REG         __preg16(KSEG1 + 0x0B000304)    /* GPIO Mode 2 Register (R/W) */
+#define VR4181_GPMD3REG         __preg16(KSEG1 + 0x0B000306)    /* GPIO Mode 3 Register (R/W) */
+#define VR4181_GPDATHREG        __preg16(KSEG1 + 0x0B000308)    /* GPIO Data High Register (R/W) */
+#define VR4181_GPDATHREG_GPIO16  0x0001
+#define VR4181_GPDATHREG_GPIO17  0x0002
+#define VR4181_GPDATHREG_GPIO18  0x0004
+#define VR4181_GPDATHREG_GPIO19  0x0008
+#define VR4181_GPDATHREG_GPIO20  0x0010
+#define VR4181_GPDATHREG_GPIO21  0x0020
+#define VR4181_GPDATHREG_GPIO22  0x0040
+#define VR4181_GPDATHREG_GPIO23  0x0080
+#define VR4181_GPDATHREG_GPIO24  0x0100
+#define VR4181_GPDATHREG_GPIO25  0x0200
+#define VR4181_GPDATHREG_GPIO26  0x0400
+#define VR4181_GPDATHREG_GPIO27  0x0800
+#define VR4181_GPDATHREG_GPIO28  0x1000
+#define VR4181_GPDATHREG_GPIO29  0x2000
+#define VR4181_GPDATHREG_GPIO30  0x4000
+#define VR4181_GPDATHREG_GPIO31  0x8000
+#define VR4181_GPDATLREG        __preg16(KSEG1 + 0x0B00030A)    /* GPIO Data Low Register (R/W) */
+#define VR4181_GPDATLREG_GPIO0   0x0001
+#define VR4181_GPDATLREG_GPIO1   0x0002
+#define VR4181_GPDATLREG_GPIO2   0x0004
+#define VR4181_GPDATLREG_GPIO3   0x0008
+#define VR4181_GPDATLREG_GPIO4   0x0010
+#define VR4181_GPDATLREG_GPIO5   0x0020
+#define VR4181_GPDATLREG_GPIO6   0x0040
+#define VR4181_GPDATLREG_GPIO7   0x0080
+#define VR4181_GPDATLREG_GPIO8   0x0100
+#define VR4181_GPDATLREG_GPIO9   0x0200
+#define VR4181_GPDATLREG_GPIO10  0x0400
+#define VR4181_GPDATLREG_GPIO11  0x0800
+#define VR4181_GPDATLREG_GPIO12  0x1000
+#define VR4181_GPDATLREG_GPIO13  0x2000
+#define VR4181_GPDATLREG_GPIO14  0x4000
+#define VR4181_GPDATLREG_GPIO15  0x8000
+#define VR4181_GPINTEN          __preg16(KSEG1 + 0x0B00030C)    /* GPIO Interrupt Enable Register (R/W) */
+#define VR4181_GPINTMSK         __preg16(KSEG1 + 0x0B00030E)    /* GPIO Interrupt Mask Register (R/W) */
+#define VR4181_GPINTTYPH        __preg16(KSEG1 + 0x0B000310)    /* GPIO Interrupt Type High Register (R/W) */
+#define VR4181_GPINTTYPL        __preg16(KSEG1 + 0x0B000312)    /* GPIO Interrupt Type Low Register (R/W) */
+#define VR4181_GPINTSTAT        __preg16(KSEG1 + 0x0B000314)    /* GPIO Interrupt Status Register (R/W) */
+#define VR4181_GPHIBSTH         __preg16(KSEG1 + 0x0B000316)    /* GPIO Hibernate Pin State High Register (R/W) */
+#define VR4181_GPHIBSTL         __preg16(KSEG1 + 0x0B000318)    /* GPIO Hibernate Pin State Low Register (R/W) */
+#define VR4181_GPSICTL          __preg16(KSEG1 + 0x0B00031A)    /* GPIO Serial Interface Control Register (R/W) */
+#define VR4181_KEYEN            __preg16(KSEG1 + 0x0B00031C)    /* Keyboard Scan Pin Enable Register (R/W) */
+#define VR4181_PCS0STRA         __preg16(KSEG1 + 0x0B000320)    /* Programmable Chip Select [0] Start Address Register (R/W) */
+#define VR4181_PCS0STPA         __preg16(KSEG1 + 0x0B000322)    /* Programmable Chip Select [0] Stop Address Register (R/W) */
+#define VR4181_PCS0HIA          __preg16(KSEG1 + 0x0B000324)    /* Programmable Chip Select [0] High Address Register (R/W) */
+#define VR4181_PCS1STRA         __preg16(KSEG1 + 0x0B000326)    /* Programmable Chip Select [1] Start Address Register (R/W) */
+#define VR4181_PCS1STPA         __preg16(KSEG1 + 0x0B000328)    /* Programmable Chip Select [1] Stop Address Register (R/W) */
+#define VR4181_PCS1HIA          __preg16(KSEG1 + 0x0B00032A)    /* Programmable Chip Select [1] High Address Register (R/W) */
+#define VR4181_PCSMODE          __preg16(KSEG1 + 0x0B00032C)    /* Programmable Chip Select Mode Register (R/W) */
+#define VR4181_LCDGPMODE        __preg16(KSEG1 + 0x0B00032E)    /* LCD General Purpose Mode Register (R/W) */
+#define VR4181_MISCREG0         __preg16(KSEG1 + 0x0B000330)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG1         __preg16(KSEG1 + 0x0B000332)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG2         __preg16(KSEG1 + 0x0B000334)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG3         __preg16(KSEG1 + 0x0B000336)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG4         __preg16(KSEG1 + 0x0B000338)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG5         __preg16(KSEG1 + 0x0B00033A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG6         __preg16(KSEG1 + 0x0B00033C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG7         __preg16(KSEG1 + 0x0B00033D)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG8         __preg16(KSEG1 + 0x0B000340)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG9         __preg16(KSEG1 + 0x0B000342)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG10        __preg16(KSEG1 + 0x0B000344)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG11        __preg16(KSEG1 + 0x0B000346)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG12        __preg16(KSEG1 + 0x0B000348)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG13        __preg16(KSEG1 + 0x0B00034A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG14        __preg16(KSEG1 + 0x0B00034C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_MISCREG15        __preg16(KSEG1 + 0x0B00034E)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
+#define VR4181_SECIRQMASKL      VR4181_GPINTEN
+// No SECIRQMASKH for VR4181
+
+// Touch Panel Interface Unit (PIU)
+#define VR4181_PIUCNTREG        __preg16(KSEG1 + 0x0B000122)    /* PIU Control register (R/W) */
+#define VR4181_PIUCNTREG_PIUSEQEN       0x0004
+#define VR4181_PIUCNTREG_PIUPWR         0x0002
+#define VR4181_PIUCNTREG_PADRST         0x0001
+
+#define VR4181_PIUINTREG        __preg16(KSEG1 + 0x0B000124)    /* PIU Interrupt cause register (R/W) */
+#define VR4181_PIUINTREG_OVP            0x8000
+#define VR4181_PIUINTREG_PADCMD         0x0040
+#define VR4181_PIUINTREG_PADADP         0x0020
+#define VR4181_PIUINTREG_PADPAGE1       0x0010
+#define VR4181_PIUINTREG_PADPAGE0       0x0008
+#define VR4181_PIUINTREG_PADDLOST       0x0004
+#define VR4181_PIUINTREG_PENCHG         0x0001
+
+#define VR4181_PIUSIVLREG       __preg16(KSEG1 + 0x0B000126)    /* PIU Data sampling interval register (R/W) */
+#define VR4181_PIUSTBLREG       __preg16(KSEG1 + 0x0B000128)    /* PIU A/D converter start delay register (R/W) */
+#define VR4181_PIUCMDREG        __preg16(KSEG1 + 0x0B00012A)    /* PIU A/D command register (R/W) */
+#define VR4181_PIUASCNREG       __preg16(KSEG1 + 0x0B000130)    /* PIU A/D port scan register (R/W) */
+#define VR4181_PIUAMSKREG       __preg16(KSEG1 + 0x0B000132)    /* PIU A/D scan mask register (R/W) */
+#define VR4181_PIUCIVLREG       __preg16(KSEG1 + 0x0B00013E)    /* PIU Check interval register (R) */
+#define VR4181_PIUPB00REG       __preg16(KSEG1 + 0x0B0002A0)    /* PIU Page 0 Buffer 0 register (R/W) */
+#define VR4181_PIUPB01REG       __preg16(KSEG1 + 0x0B0002A2)    /* PIU Page 0 Buffer 1 register (R/W) */
+#define VR4181_PIUPB02REG       __preg16(KSEG1 + 0x0B0002A4)    /* PIU Page 0 Buffer 2 register (R/W) */
+#define VR4181_PIUPB03REG       __preg16(KSEG1 + 0x0B0002A6)    /* PIU Page 0 Buffer 3 register (R/W) */
+#define VR4181_PIUPB10REG       __preg16(KSEG1 + 0x0B0002A8)    /* PIU Page 1 Buffer 0 register (R/W) */
+#define VR4181_PIUPB11REG       __preg16(KSEG1 + 0x0B0002AA)    /* PIU Page 1 Buffer 1 register (R/W) */
+#define VR4181_PIUPB12REG       __preg16(KSEG1 + 0x0B0002AC)    /* PIU Page 1 Buffer 2 register (R/W) */
+#define VR4181_PIUPB13REG       __preg16(KSEG1 + 0x0B0002AE)    /* PIU Page 1 Buffer 3 register (R/W) */
+#define VR4181_PIUAB0REG        __preg16(KSEG1 + 0x0B0002B0)    /* PIU A/D scan Buffer 0 register (R/W) */
+#define VR4181_PIUAB1REG        __preg16(KSEG1 + 0x0B0002B2)    /* PIU A/D scan Buffer 1 register (R/W) */
+#define VR4181_PIUAB2REG        __preg16(KSEG1 + 0x0B0002B4)    /* PIU A/D scan Buffer 2 register (R/W) */
+#define VR4181_PIUAB3REG        __preg16(KSEG1 + 0x0B0002B6)    /* PIU A/D scan Buffer 3 register (R/W) */
+#define VR4181_PIUPB04REG       __preg16(KSEG1 + 0x0B0002BC)    /* PIU Page 0 Buffer 4 register (R/W) */
+#define VR4181_PIUPB14REG       __preg16(KSEG1 + 0x0B0002BE)    /* PIU Page 1 Buffer 4 register (R/W) */
+
+// Audio Interface Unit (AIU)
+#define VR4181_SODATREG         __preg16(KSEG1 + 0x0B000166)    /* Speaker Output Data Register (R/W) */
+#define VR4181_SCNTREG          __preg16(KSEG1 + 0x0B000168)    /* Speaker Output Control Register (R/W) */
+#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Mike Input Data Register (R/W) */
+#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Mike Input Control Register (R/W) */
+#define VR4181_DVALIDREG        __preg16(KSEG1 + 0x0B000178)    /* Data Valid Register (R/W) */
+#define VR4181_SEQREG           __preg16(KSEG1 + 0x0B00017A)    /* Sequential Register (R/W) */
+#define VR4181_INTREG           __preg16(KSEG1 + 0x0B00017C)    /* Interrupt Register (R/W) */
+#define VR4181_SDMADATREG       __preg16(KSEG1 + 0x0B000160)    /* Speaker DMA Data Register (R/W) */
+#define VR4181_MDMADATREG       __preg16(KSEG1 + 0x0B000162)    /* Microphone DMA Data Register (R/W) */
+#define VR4181_DAVREF_SETUP     __preg16(KSEG1 + 0x0B000164)    /* DAC Vref setup register (R/W) */
+#define VR4181_SCNVC_END        __preg16(KSEG1 + 0x0B00016E)    /* Speaker sample rate control (R/W) */
+#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Microphone Input Data Register (R/W) */
+#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Microphone Input Control Register (R/W) */
+#define VR4181_MCNVC_END        __preg16(KSEG1 + 0x0B00017E)    /* Microphone sample rate control (R/W) */
+
+// Keyboard Interface Unit (KIU)
+#define VR4181_KIUDAT0          __preg16(KSEG1 + 0x0B000180)    /* KIU Data0 Register (R/W) */
+#define VR4181_KIUDAT1          __preg16(KSEG1 + 0x0B000182)    /* KIU Data1 Register (R/W) */
+#define VR4181_KIUDAT2          __preg16(KSEG1 + 0x0B000184)    /* KIU Data2 Register (R/W) */
+#define VR4181_KIUDAT3          __preg16(KSEG1 + 0x0B000186)    /* KIU Data3 Register (R/W) */
+#define VR4181_KIUDAT4          __preg16(KSEG1 + 0x0B000188)    /* KIU Data4 Register (R/W) */
+#define VR4181_KIUDAT5          __preg16(KSEG1 + 0x0B00018A)    /* KIU Data5 Register (R/W) */
+#define VR4181_KIUSCANREP       __preg16(KSEG1 + 0x0B000190)    /* KIU Scan/Repeat Register (R/W) */
+#define VR4181_KIUSCANREP_KEYEN      0x8000
+#define VR4181_KIUSCANREP_SCANSTP    0x0008
+#define VR4181_KIUSCANREP_SCANSTART  0x0004
+#define VR4181_KIUSCANREP_ATSTP      0x0002
+#define VR4181_KIUSCANREP_ATSCAN     0x0001
+#define VR4181_KIUSCANS         __preg16(KSEG1 + 0x0B000192)    /* KIU Scan Status Register (R) */
+#define VR4181_KIUWKS           __preg16(KSEG1 + 0x0B000194)    /* KIU Wait Keyscan Stable Register (R/W) */
+#define VR4181_KIUWKI           __preg16(KSEG1 + 0x0B000196)    /* KIU Wait Keyscan Interval Register (R/W) */
+#define VR4181_KIUINT           __preg16(KSEG1 + 0x0B000198)    /* KIU Interrupt Register (R/W) */
+#define VR4181_KIUINT_KDATLOST       0x0004
+#define VR4181_KIUINT_KDATRDY        0x0002
+#define VR4181_KIUINT_SCANINT        0x0001
+#define VR4181_KIUDAT6          __preg16(KSEG1 + 0x0B00018C)    /* Scan Line 6 Key Data Register (R) */
+#define VR4181_KIUDAT7          __preg16(KSEG1 + 0x0B00018E)    /* Scan Line 7 Key Data Register (R) */
+
+// CompactFlash Controller
+#define VR4181_PCCARDINDEX      __preg8(KSEG1 + 0x0B0008E0)     /* PC Card Controller Index Register */
+#define VR4181_PCCARDDATA       __preg8(KSEG1 + 0x0B0008E1)     /* PC Card Controller Data Register */
+#define VR4181_INTSTATREG       __preg16(KSEG1 + 0x0B0008F8)    /* Interrupt Status Register (R/W) */
+#define VR4181_INTMSKREG        __preg16(KSEG1 + 0x0B0008FA)    /* Interrupt Mask Register (R/W) */
+#define VR4181_CFG_REG_1        __preg16(KSEG1 + 0x0B0008FE)    /* Configuration Register 1 */
+
+// LED Control Unit (LED)
+#define VR4181_LEDHTSREG        __preg16(KSEG1 + 0x0B000240)    /* LED H Time Set register (R/W) */
+#define VR4181_LEDLTSREG        __preg16(KSEG1 + 0x0B000242)    /* LED L Time Set register (R/W) */
+#define VR4181_LEDCNTREG        __preg16(KSEG1 + 0x0B000248)    /* LED Control register (R/W) */
+#define VR4181_LEDASTCREG       __preg16(KSEG1 + 0x0B00024A)    /* LED Auto Stop Time Count register (R/W) */
+#define VR4181_LEDINTREG        __preg16(KSEG1 + 0x0B00024C)    /* LED Interrupt register (R/W) */
+
+// Serial Interface Unit (SIU / SIU1 and SIU2)
+#define VR4181_SIURB            __preg8(KSEG1 + 0x0C000010)     /* Receiver Buffer Register (Read) DLAB = 0 (R) */
+#define VR4181_SIUTH            __preg8(KSEG1 + 0x0C000010)     /* Transmitter Holding Register (Write) DLAB = 0 (W) */
+#define VR4181_SIUDLL           __preg8(KSEG1 + 0x0C000010)     /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
+#define VR4181_SIUIE            __preg8(KSEG1 + 0x0C000011)     /* Interrupt Enable DLAB = 0 (R/W) */
+#define VR4181_SIUDLM           __preg8(KSEG1 + 0x0C000011)     /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
+#define VR4181_SIUIID           __preg8(KSEG1 + 0x0C000012)     /* Interrupt Identification Register (Read) (R) */
+#define VR4181_SIUFC            __preg8(KSEG1 + 0x0C000012)     /* FIFO Control Register (Write) (W) */
+#define VR4181_SIULC            __preg8(KSEG1 + 0x0C000013)     /* Line Control Register (R/W) */
+#define VR4181_SIUMC            __preg8(KSEG1 + 0x0C000014)     /* MODEM Control Register (R/W) */
+#define VR4181_SIULS            __preg8(KSEG1 + 0x0C000015)     /* Line Status Register (R/W) */
+#define VR4181_SIUMS            __preg8(KSEG1 + 0x0C000016)     /* MODEM Status Register (R/W) */
+#define VR4181_SIUSC            __preg8(KSEG1 + 0x0C000017)     /* Scratch Register (R/W) */
+#define VR4181_SIURESET         __preg8(KSEG1 + 0x0C000019)     /* SIU Reset Register (R/W) */
+#define VR4181_SIUACTMSK        __preg8(KSEG1 + 0x0C00001C)     /* SIU Activity Mask (R/W) */
+#define VR4181_SIUACTTMR        __preg8(KSEG1 + 0x0C00001E)     /* SIU Activity Timer (R/W) */
+#define VR4181_SIURB_2          __preg8(KSEG1 + 0x0C000000)     /* Receive Buffer Register (Read) (R) */
+#define VR4181_SIUTH_2          __preg8(KSEG1 + 0x0C000000)     /* Transmitter Holding Register (Write) (W) */
+#define VR4181_SIUDLL_2         __preg8(KSEG1 + 0x0C000000)     /* Divisor Latch (Least Significant Byte) (R/W) */
+#define VR4181_SIUIE_2          __preg8(KSEG1 + 0x0C000001)     /* Interrupt Enable (DLAB = 0) (R/W) */
+#define VR4181_SIUDLM_2         __preg8(KSEG1 + 0x0C000001)     /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
+#define VR4181_SIUIID_2         __preg8(KSEG1 + 0x0C000002)     /* Interrupt Identification Register (Read) (R) */
+#define VR4181_SIUFC_2          __preg8(KSEG1 + 0x0C000002)     /* FIFO Control Register (Write) (W) */
+#define VR4181_SIULC_2          __preg8(KSEG1 + 0x0C000003)     /* Line Control Register (R/W) */
+#define VR4181_SIUMC_2          __preg8(KSEG1 + 0x0C000004)     /* Modem Control Register (R/W) */
+#define VR4181_SIULS_2          __preg8(KSEG1 + 0x0C000005)     /* Line Status Register (R/W) */
+#define VR4181_SIUMS_2          __preg8(KSEG1 + 0x0C000006)     /* Modem Status Register (R/W) */
+#define VR4181_SIUSC_2          __preg8(KSEG1 + 0x0C000007)     /* Scratch Register (R/W) */
+#define VR4181_SIUIRSEL_2       __preg8(KSEG1 + 0x0C000008)     /* SIU IrDA Selectot (R/W) */
+#define VR4181_SIURESET_2       __preg8(KSEG1 + 0x0C000009)     /* SIU Reset Register (R/W) */
+#define VR4181_SIUCSEL_2        __preg8(KSEG1 + 0x0C00000A)     /* IrDA Echo-back Control (R/W) */
+#define VR4181_SIUACTMSK_2      __preg8(KSEG1 + 0x0C00000C)     /* SIU Activity Mask Register (R/W) */
+#define VR4181_SIUACTTMR_2      __preg8(KSEG1 + 0x0C00000E)     /* SIU Activity Timer Register (R/W) */
+
+
+// USB Module
+#define VR4181_USBINFIFO        __preg16(KSEG1 + 0x0B000780)    /* USB Bulk Input FIFO (Bulk In End Point) (W) */
+#define VR4181_USBOUTFIFO       __preg16(KSEG1 + 0x0B000782)    /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
+#define VR4181_USBCTLFIFO       __preg16(KSEG1 + 0x0B000784)    /* USB Control FIFO (Control End Point) (W) */
+#define VR4181_USBSTAT          __preg16(KSEG1 + 0x0B000786)    /* Interrupt Status Register (R/W) */
+#define VR4181_USBINTMSK        __preg16(KSEG1 + 0x0B000788)    /* Interrupt Mask Register (R/W) */
+#define VR4181_USBCTLREG        __preg16(KSEG1 + 0x0B00078A)    /* Control Register (R/W) */
+#define VR4181_USBSTPREG        __preg16(KSEG1 + 0x0B00078C)    /* USB Transfer Stop Register (R/W) */
+
+// LCD Controller
+#define VR4181_HRTOTALREG       __preg16(KSEG1 + 0x0A000400)    /* Horizontal total Register (R/W) */
+#define VR4181_HRVISIBREG       __preg16(KSEG1 + 0x0A000402)    /* Horizontal Visible Register (R/W) */
+#define VR4181_LDCLKSTREG       __preg16(KSEG1 + 0x0A000404)    /* Load clock start Register (R/W) */
+#define VR4181_LDCLKNDREG       __preg16(KSEG1 + 0x0A000406)    /* Load clock end Register (R/W) */
+#define VR4181_VRTOTALREG       __preg16(KSEG1 + 0x0A000408)    /* Vertical Total Register (R/W) */
+#define VR4181_VRVISIBREG       __preg16(KSEG1 + 0x0A00040A)    /* Vertical Visible Register (R/W) */
+#define VR4181_FVSTARTREG       __preg16(KSEG1 + 0x0A00040C)    /* FLM vertical start Register (R/W) */
+#define VR4181_FVENDREG         __preg16(KSEG1 + 0x0A00040E)    /* FLM vertical end Register (R/W) */
+#define VR4181_LCDCTRLREG       __preg16(KSEG1 + 0x0A000410)    /* LCD control Register (R/W) */
+#define VR4181_LCDINRQREG       __preg16(KSEG1 + 0x0A000412)    /* LCD Interrupt request Register (R/W) */
+#define VR4181_LCDCFGREG0       __preg16(KSEG1 + 0x0A000414)    /* LCD Configuration Register 0 (R/W) */
+#define VR4181_LCDCFGREG1       __preg16(KSEG1 + 0x0A000416)    /* LCD Configuration Register 1 (R/W) */
+#define VR4181_FBSTAD1REG       __preg16(KSEG1 + 0x0A000418)    /* Frame Buffer Start Address 1 Register (R/W) */
+#define VR4181_FBSTAD2REG       __preg16(KSEG1 + 0x0A00041A)    /* Frame Buffer Start Address 2 Register (R/W) */
+#define VR4181_FBNDAD1REG       __preg16(KSEG1 + 0x0A000420)    /* Frame Buffer End Address 1 Register (R/W) */
+#define VR4181_FBNDAD2REG       __preg16(KSEG1 + 0x0A000422)    /* Frame Buffer End Address 2 register (R/W) */
+#define VR4181_FHSTARTREG       __preg16(KSEG1 + 0x0A000424)    /* FLM horizontal Start Register (R/W) */
+#define VR4181_FHENDREG         __preg16(KSEG1 + 0x0A000426)    /* FLM horizontal End Register (R/W) */
+#define VR4181_PWRCONREG1       __preg16(KSEG1 + 0x0A000430)    /* Power Control register 1 (R/W) */
+#define VR4181_PWRCONREG2       __preg16(KSEG1 + 0x0A000432)    /* Power Control register 2 (R/W) */
+#define VR4181_LCDIMSKREG       __preg16(KSEG1 + 0x0A000434)    /* LCD Interrupt Mask register (R/W) */
+#define VR4181_CPINDCTREG       __preg16(KSEG1 + 0x0A00047E)    /* Color palette Index and control Register (R/W) */
+#define VR4181_CPALDATREG       __preg32(KSEG1 + 0x0A000480)    /* Color palette data register (32bits Register) (R/W) */
+
+// physical address spaces
+#define VR4181_LCD             0x0a000000
+#define VR4181_INTERNAL_IO_2   0x0b000000
+#define VR4181_INTERNAL_IO_1   0x0c000000
+#define VR4181_ISA_MEM         0x10000000
+#define VR4181_ISA_IO          0x14000000
+#define VR4181_ROM             0x18000000
+
+// This is the base address for IO port decoding to which the 16 bit IO port address
+// is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
+// attempted, which can be handy for turning up parts of the kernel that make
+// incorrect architecture assumptions (by assuming that everything acts like a PC),
+// but we need it correctly defined to use the PCMCIA/CF controller:
+#define VR4181_PORT_BASE        (KSEG1 + VR4181_ISA_IO)
+#define VR4181_ISAMEM_BASE      (KSEG1 + VR4181_ISA_MEM)
+
+#endif /* __ASM_VR4181_VR4181_H */
diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h
new file mode 100644
index 000000000000..5b55083c5281
--- /dev/null
+++ b/include/asm-mips/vr41xx/capcella.h
@@ -0,0 +1,43 @@
+/*
+ *  capcella.h, Include file for ZAO Networks Capcella.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ZAO_CAPCELLA_H
+#define __ZAO_CAPCELLA_H
+
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define PC104PLUS_INTA_PIN              2
+#define PC104PLUS_INTB_PIN              3
+#define PC104PLUS_INTC_PIN              4
+#define PC104PLUS_INTD_PIN              5
+
+/*
+ * Interrupt Number
+ */
+#define RTL8139_1_IRQ                   GIU_IRQ(PC104PLUS_INTC_PIN)
+#define RTL8139_2_IRQ                   GIU_IRQ(PC104PLUS_INTD_PIN)
+#define PC104PLUS_INTA_IRQ              GIU_IRQ(PC104PLUS_INTA_PIN)
+#define PC104PLUS_INTB_IRQ              GIU_IRQ(PC104PLUS_INTB_PIN)
+#define PC104PLUS_INTC_IRQ              GIU_IRQ(PC104PLUS_INTC_PIN)
+#define PC104PLUS_INTD_IRQ              GIU_IRQ(PC104PLUS_INTD_PIN)
+
+#endif /* __ZAO_CAPCELLA_H */
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
new file mode 100644
index 000000000000..42af389019ea
--- /dev/null
+++ b/include/asm-mips/vr41xx/cmbvr4133.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-mips/vr41xx/cmbvr4133.h
+ *
+ * Include file for NEC CMB-VR4133.
+ *
+ * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
+ *         Jun Sun <jsun@mvista.com, or source@mvista.com> and
+ *         Alex Sapkov <asapkov@ru.mvista.com>
+ *
+ * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __NEC_CMBVR4133_H
+#define __NEC_CMBVR4133_H
+
+#include <asm/addrspace.h>
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define CMBVR41XX_INTA_PIN              1
+#define CMBVR41XX_INTB_PIN              1
+#define CMBVR41XX_INTC_PIN              3
+#define CMBVR41XX_INTD_PIN              1
+#define CMBVR41XX_INTE_PIN              1
+
+/*
+ * Interrupt Number
+ */
+#define CMBVR41XX_INTA_IRQ              GIU_IRQ(CMBVR41XX_INTA_PIN)
+#define CMBVR41XX_INTB_IRQ              GIU_IRQ(CMBVR41XX_INTB_PIN)
+#define CMBVR41XX_INTC_IRQ              GIU_IRQ(CMBVR41XX_INTC_PIN)
+#define CMBVR41XX_INTD_IRQ              GIU_IRQ(CMBVR41XX_INTD_PIN)
+#define CMBVR41XX_INTE_IRQ              GIU_IRQ(CMBVR41XX_INTE_PIN)
+
+#define I8259_IRQ_BASE                  72
+#define I8259_IRQ(x)                    (I8259_IRQ_BASE + (x))
+#define TIMER_IRQ                       I8259_IRQ(0)
+#define KEYBOARD_IRQ                    I8259_IRQ(1)
+#define I8259_SLAVE_IRQ                 I8259_IRQ(2)
+#define UART3_IRQ                       I8259_IRQ(3)
+#define UART1_IRQ                       I8259_IRQ(4)
+#define UART2_IRQ                       I8259_IRQ(5)
+#define FDC_IRQ                         I8259_IRQ(6)
+#define PARPORT_IRQ                     I8259_IRQ(7)
+#define RTC_IRQ                         I8259_IRQ(8)
+#define USB_IRQ                         I8259_IRQ(9)
+#define I8259_INTA_IRQ                  I8259_IRQ(10)
+#define AUDIO_IRQ                       I8259_IRQ(11)
+#define AUX_IRQ                         I8259_IRQ(12)
+#define IDE_PRIMARY_IRQ                 I8259_IRQ(14)
+#define IDE_SECONDARY_IRQ               I8259_IRQ(15)
+#define I8259_IRQ_LAST                  IDE_SECONDARY_IRQ
+
+#define RTC_PORT(x)     (0xaf000100 + (x))
+#define RTC_IO_EXTENT   0x140
+
+#endif /* __NEC_CMBVR4133_H */
diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h
new file mode 100644
index 000000000000..ea37b56fc66d
--- /dev/null
+++ b/include/asm-mips/vr41xx/e55.h
@@ -0,0 +1,43 @@
+/*
+ *  e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __CASIO_E55_H
+#define __CASIO_E55_H
+
+#include <asm/addrspace.h>
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * Board specific address mapping
+ */
+#define VR41XX_ISA_MEM_BASE             0x10000000
+#define VR41XX_ISA_MEM_SIZE             0x04000000
+
+/* VR41XX_ISA_IO_BASE includes offset from real base. */
+#define VR41XX_ISA_IO_BASE              0x1400c000
+#define VR41XX_ISA_IO_SIZE              0x03ff4000
+
+#define ISA_BUS_IO_BASE                 0
+#define ISA_BUS_IO_SIZE                 VR41XX_ISA_IO_SIZE
+
+#define IO_PORT_BASE                    KSEG1ADDR(VR41XX_ISA_IO_BASE)
+#define IO_PORT_RESOURCE_START          ISA_BUS_IO_BASE
+#define IO_PORT_RESOURCE_END            (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
+
+#endif /* __CASIO_E55_H */
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h
new file mode 100644
index 000000000000..e6ac3c8e8bae
--- /dev/null
+++ b/include/asm-mips/vr41xx/mpc30x.h
@@ -0,0 +1,37 @@
+/*
+ *  mpc30x.h, Include file for Victor MP-C303/304.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __VICTOR_MPC30X_H
+#define __VICTOR_MPC30X_H
+
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define VRC4173_PIN                     1
+#define MQ200_PIN                       4
+
+/*
+ * Interrupt Number
+ */
+#define VRC4173_CASCADE_IRQ             GIU_IRQ(VRC4173_PIN)
+#define MQ200_IRQ                       GIU_IRQ(MQ200_PIN)
+
+#endif /* __VICTOR_MPC30X_H */
diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h
new file mode 100644
index 000000000000..865cc07ddd7f
--- /dev/null
+++ b/include/asm-mips/vr41xx/siu.h
@@ -0,0 +1,50 @@
+/*
+ *  Include file for NEC VR4100 series Serial Interface Unit.
+ *
+ *  Copyright (C) 2005  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VR41XX_SIU_H
+#define __NEC_VR41XX_SIU_H
+
+typedef enum {
+        SIU_INTERFACE_RS232C,
+        SIU_INTERFACE_IRDA,
+} siu_interface_t;
+
+extern void vr41xx_select_siu_interface(siu_interface_t interface);
+
+typedef enum {
+        SIU_USE_IRDA,
+        FIR_USE_IRDA,
+} irda_use_t;
+
+extern void vr41xx_use_irda(irda_use_t use);
+
+typedef enum {
+        SHARP_IRDA,
+        TEMIC_IRDA,
+        HP_IRDA,
+} irda_module_t;
+
+typedef enum {
+        IRDA_TX_1_5MBPS,
+        IRDA_TX_4MBPS,
+} irda_speed_t;
+
+extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
+
+#endif /* __NEC_VR41XX_SIU_H */
diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h
new file mode 100644
index 000000000000..273c6392688f
--- /dev/null
+++ b/include/asm-mips/vr41xx/tb0219.h
@@ -0,0 +1,42 @@
+/*
+ *  tb0219.h, Include file for TANBAC TB0219.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  Modified for TANBAC TB0219:
+ *  Copyright (C) 2003 Megasolution Inc.  <matsu@megasolution.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TANBAC_TB0219_H
+#define __TANBAC_TB0219_H
+
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define TB0219_PCI_SLOT1_PIN            2
+#define TB0219_PCI_SLOT2_PIN            3
+#define TB0219_PCI_SLOT3_PIN            4
+
+/*
+ * Interrupt Number
+ */
+#define TB0219_PCI_SLOT1_IRQ            GIU_IRQ(TB0219_PCI_SLOT1_PIN)
+#define TB0219_PCI_SLOT2_IRQ            GIU_IRQ(TB0219_PCI_SLOT2_PIN)
+#define TB0219_PCI_SLOT3_IRQ            GIU_IRQ(TB0219_PCI_SLOT3_PIN)
+
+#endif /* __TANBAC_TB0219_H */
diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h
new file mode 100644
index 000000000000..0ff9a60ecacc
--- /dev/null
+++ b/include/asm-mips/vr41xx/tb0226.h
@@ -0,0 +1,43 @@
+/*
+ *  tb0226.h, Include file for TANBAC TB0226.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TANBAC_TB0226_H
+#define __TANBAC_TB0226_H
+
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define GD82559_1_PIN                   2
+#define GD82559_2_PIN                   3
+#define UPD720100_INTA_PIN              4
+#define UPD720100_INTB_PIN              8
+#define UPD720100_INTC_PIN              13
+
+/*
+ * Interrupt Number
+ */
+#define GD82559_1_IRQ                   GIU_IRQ(GD82559_1_PIN)
+#define GD82559_2_IRQ                   GIU_IRQ(GD82559_2_PIN)
+#define UPD720100_INTA_IRQ              GIU_IRQ(UPD720100_INTA_PIN)
+#define UPD720100_INTB_IRQ              GIU_IRQ(UPD720100_INTB_PIN)
+#define UPD720100_INTC_IRQ              GIU_IRQ(UPD720100_INTC_PIN)
+
+#endif /* __TANBAC_TB0226_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
new file mode 100644
index 000000000000..caacaced3213
--- /dev/null
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -0,0 +1,320 @@
+/*
+ * include/asm-mips/vr41xx/vr41xx.h
+ *
+ * Include file for NEC VR4100 series.
+ *
+ * Copyright (C) 1999 Michael Klar
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+ * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __NEC_VR41XX_H
+#define __NEC_VR41XX_H
+
+#include <linux/interrupt.h>
+
+/*
+ * CPU Revision
+ */
+/* VR4122 0x00000c70-0x00000c72 */
+#define PRID_VR4122_REV1_0      0x00000c70
+#define PRID_VR4122_REV2_0      0x00000c70
+#define PRID_VR4122_REV2_1      0x00000c70
+#define PRID_VR4122_REV3_0      0x00000c71
+#define PRID_VR4122_REV3_1      0x00000c72
+
+/* VR4181A 0x00000c73-0x00000c7f */
+#define PRID_VR4181A_REV1_0     0x00000c73
+#define PRID_VR4181A_REV1_1     0x00000c74
+
+/* VR4131 0x00000c80-0x00000c83 */
+#define PRID_VR4131_REV1_2      0x00000c80
+#define PRID_VR4131_REV2_0      0x00000c81
+#define PRID_VR4131_REV2_1      0x00000c82
+#define PRID_VR4131_REV2_2      0x00000c83
+
+/* VR4133 0x00000c84- */
+#define PRID_VR4133             0x00000c84
+
+/*
+ * Bus Control Uint
+ */
+extern unsigned long vr41xx_calculate_clock_frequency(void);
+extern unsigned long vr41xx_get_vtclock_frequency(void);
+extern unsigned long vr41xx_get_tclock_frequency(void);
+
+/*
+ * Clock Mask Unit
+ */
+typedef enum {
+        PIU_CLOCK,
+        SIU_CLOCK,
+        AIU_CLOCK,
+        KIU_CLOCK,
+        FIR_CLOCK,
+        DSIU_CLOCK,
+        CSI_CLOCK,
+        PCIU_CLOCK,
+        HSP_CLOCK,
+        PCI_CLOCK,
+        CEU_CLOCK,
+        ETHER0_CLOCK,
+        ETHER1_CLOCK
+} vr41xx_clock_t;
+
+extern void vr41xx_supply_clock(vr41xx_clock_t clock);
+extern void vr41xx_mask_clock(vr41xx_clock_t clock);
+
+/*
+ * Interrupt Control Unit
+ */
+/* CPU core Interrupt Numbers */
+#define MIPS_CPU_IRQ_BASE       0
+#define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
+#define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
+#define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
+#define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
+#define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
+#define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
+#define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
+#define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
+#define TIMER_IRQ               MIPS_CPU_IRQ(7)
+
+/* SYINT1 Interrupt Numbers */
+#define SYSINT1_IRQ_BASE        8
+#define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
+#define BATTRY_IRQ              SYSINT1_IRQ(0)
+#define POWER_IRQ               SYSINT1_IRQ(1)
+#define RTCLONG1_IRQ            SYSINT1_IRQ(2)
+#define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
+/* RFU */
+#define PIU_IRQ                 SYSINT1_IRQ(5)
+#define AIU_IRQ                 SYSINT1_IRQ(6)
+#define KIU_IRQ                 SYSINT1_IRQ(7)
+#define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
+#define SIU_IRQ                 SYSINT1_IRQ(9)
+#define BUSERR_IRQ              SYSINT1_IRQ(10)
+#define SOFTINT_IRQ             SYSINT1_IRQ(11)
+#define CLKRUN_IRQ              SYSINT1_IRQ(12)
+#define DOZEPIU_IRQ             SYSINT1_IRQ(13)
+#define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
+
+/* SYSINT2 Interrupt Numbers */
+#define SYSINT2_IRQ_BASE        24
+#define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
+#define RTCLONG2_IRQ            SYSINT2_IRQ(0)
+#define LED_IRQ                 SYSINT2_IRQ(1)
+#define HSP_IRQ                 SYSINT2_IRQ(2)
+#define TCLOCK_IRQ              SYSINT2_IRQ(3)
+#define FIR_IRQ                 SYSINT2_IRQ(4)
+#define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
+#define DSIU_IRQ                SYSINT2_IRQ(5)
+#define PCI_IRQ                 SYSINT2_IRQ(6)
+#define SCU_IRQ                 SYSINT2_IRQ(7)
+#define CSI_IRQ                 SYSINT2_IRQ(8)
+#define BCU_IRQ                 SYSINT2_IRQ(9)
+#define ETHERNET_IRQ            SYSINT2_IRQ(10)
+#define SYSINT2_IRQ_LAST        ETHERNET_IRQ
+
+/* GIU Interrupt Numbers */
+#define GIU_IRQ_BASE            40
+#define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
+#define GIU_IRQ_LAST            GIU_IRQ(31)
+#define GIU_IRQ_TO_PIN(x)       ((x) - GIU_IRQ_BASE)    /* Pin 0-31 */
+
+extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
+extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
+
+#define PIUINT_COMMAND          0x0040
+#define PIUINT_DATA             0x0020
+#define PIUINT_PAGE1            0x0010
+#define PIUINT_PAGE0            0x0008
+#define PIUINT_DATALOST         0x0004
+#define PIUINT_STATUSCHANGE     0x0001
+
+extern void vr41xx_enable_piuint(uint16_t mask);
+extern void vr41xx_disable_piuint(uint16_t mask);
+
+#define AIUINT_INPUT_DMAEND     0x0800
+#define AIUINT_INPUT_DMAHALT    0x0400
+#define AIUINT_INPUT_DATALOST   0x0200
+#define AIUINT_INPUT_DATA       0x0100
+#define AIUINT_OUTPUT_DMAEND    0x0008
+#define AIUINT_OUTPUT_DMAHALT   0x0004
+#define AIUINT_OUTPUT_NODATA    0x0002
+
+extern void vr41xx_enable_aiuint(uint16_t mask);
+extern void vr41xx_disable_aiuint(uint16_t mask);
+
+#define KIUINT_DATALOST         0x0004
+#define KIUINT_DATAREADY        0x0002
+#define KIUINT_SCAN             0x0001
+
+extern void vr41xx_enable_kiuint(uint16_t mask);
+extern void vr41xx_disable_kiuint(uint16_t mask);
+
+#define DSIUINT_CTS             0x0800
+#define DSIUINT_RXERR           0x0400
+#define DSIUINT_RX              0x0200
+#define DSIUINT_TX              0x0100
+#define DSIUINT_ALL             0x0f00
+
+extern void vr41xx_enable_dsiuint(uint16_t mask);
+extern void vr41xx_disable_dsiuint(uint16_t mask);
+
+#define FIRINT_UNIT             0x0010
+#define FIRINT_RX_DMAEND        0x0008
+#define FIRINT_RX_DMAHALT       0x0004
+#define FIRINT_TX_DMAEND        0x0002
+#define FIRINT_TX_DMAHALT       0x0001
+
+extern void vr41xx_enable_firint(uint16_t mask);
+extern void vr41xx_disable_firint(uint16_t mask);
+
+extern void vr41xx_enable_pciint(void);
+extern void vr41xx_disable_pciint(void);
+
+extern void vr41xx_enable_scuint(void);
+extern void vr41xx_disable_scuint(void);
+
+#define CSIINT_TX_DMAEND        0x0040
+#define CSIINT_TX_DMAHALT       0x0020
+#define CSIINT_TX_DATA          0x0010
+#define CSIINT_TX_FIFOEMPTY     0x0008
+#define CSIINT_RX_DMAEND        0x0004
+#define CSIINT_RX_DMAHALT       0x0002
+#define CSIINT_RX_FIFOEMPTY     0x0001
+
+extern void vr41xx_enable_csiint(uint16_t mask);
+extern void vr41xx_disable_csiint(uint16_t mask);
+
+extern void vr41xx_enable_bcuint(void);
+extern void vr41xx_disable_bcuint(void);
+
+/*
+ * Power Management Unit
+ */
+
+/*
+ * RTC
+ */
+extern void vr41xx_set_rtclong1_cycle(uint32_t cycles);
+extern uint32_t vr41xx_read_rtclong1_counter(void);
+
+extern void vr41xx_set_rtclong2_cycle(uint32_t cycles);
+extern uint32_t vr41xx_read_rtclong2_counter(void);
+
+extern void vr41xx_set_tclock_cycle(uint32_t cycles);
+extern uint32_t vr41xx_read_tclock_counter(void);
+
+/*
+ * General-Purpose I/O Unit
+ */
+enum {
+        TRIGGER_LEVEL,
+        TRIGGER_EDGE,
+        TRIGGER_EDGE_FALLING,
+        TRIGGER_EDGE_RISING
+};
+
+enum {
+        SIGNAL_THROUGH,
+        SIGNAL_HOLD
+};
+
+extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
+
+enum {
+        LEVEL_LOW,
+        LEVEL_HIGH
+};
+
+extern void vr41xx_set_irq_level(int pin, int level);
+
+enum {
+        PIO_INPUT,
+        PIO_OUTPUT
+};
+
+enum {
+        DATA_LOW,
+        DATA_HIGH
+};
+
+/*
+ * PCI Control Unit
+ */
+#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
+
+struct pci_master_address_conversion {
+        uint32_t bus_base_address;
+        uint32_t address_mask;
+        uint32_t pci_base_address;
+};
+
+struct pci_target_address_conversion {
+        uint32_t address_mask;
+        uint32_t bus_base_address;
+};
+
+typedef enum {
+        CANNOT_LOCK_FROM_DEVICE,
+        CAN_LOCK_FROM_DEVICE,
+} pci_exclusive_access_t;
+
+struct pci_mailbox_address {
+        uint32_t base_address;
+};
+
+struct pci_target_address_window {
+        uint32_t base_address;
+};
+
+typedef enum {
+        PCI_ARBITRATION_MODE_FAIR,
+        PCI_ARBITRATION_MODE_ALTERNATE_0,
+        PCI_ARBITRATION_MODE_ALTERNATE_B,
+} pci_arbiter_priority_control_t;
+
+typedef enum {
+        PCI_TAKE_AWAY_GNT_DISABLE,
+        PCI_TAKE_AWAY_GNT_ENABLE,
+} pci_take_away_gnt_mode_t;
+
+struct pci_controller_unit_setup {
+        struct pci_master_address_conversion *master_memory1;
+        struct pci_master_address_conversion *master_memory2;
+
+        struct pci_target_address_conversion *target_memory1;
+        struct pci_target_address_conversion *target_memory2;
+
+        struct pci_master_address_conversion *master_io;
+
+        pci_exclusive_access_t exclusive_access;
+
+        uint32_t pci_clock_max;
+        uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
+
+        struct pci_mailbox_address *mailbox;
+        struct pci_target_address_window *target_window1;
+        struct pci_target_address_window *target_window2;
+
+        uint8_t master_latency_timer;
+        uint8_t retry_limit;
+
+        pci_arbiter_priority_control_t arbiter_priority_control;
+        pci_take_away_gnt_mode_t take_away_gnt_mode;
+
+        struct resource *mem_resource;
+        struct resource *io_resource;
+};
+
+extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
+
+#endif /* __NEC_VR41XX_H */
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
new file mode 100644
index 000000000000..58e193c51b45
--- /dev/null
+++ b/include/asm-mips/vr41xx/vrc4173.h
@@ -0,0 +1,222 @@
+/*
+ *  vrc4173.h, Include file for NEC VRC4173.
+ *
+ *  Copyright (C) 2000  Michael R. McDonald
+ *  Copyright (C) 2001-2003 Montavista Software Inc.
+ *    Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
+ *  Copyright (C) 2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *  Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VRC4173_H 
+#define __NEC_VRC4173_H 
+
+#include <linux/config.h>
+#include <asm/io.h>
+
+/*
+ * Interrupt Number
+ */
+#define VRC4173_IRQ_BASE        72
+#define VRC4173_IRQ(x)          (VRC4173_IRQ_BASE + (x))
+#define VRC4173_USB_IRQ         VRC4173_IRQ(0)
+#define VRC4173_PCMCIA2_IRQ     VRC4173_IRQ(1)
+#define VRC4173_PCMCIA1_IRQ     VRC4173_IRQ(2)
+#define VRC4173_PS2CH2_IRQ      VRC4173_IRQ(3)
+#define VRC4173_PS2CH1_IRQ      VRC4173_IRQ(4)
+#define VRC4173_PIU_IRQ         VRC4173_IRQ(5)
+#define VRC4173_AIU_IRQ         VRC4173_IRQ(6)
+#define VRC4173_KIU_IRQ         VRC4173_IRQ(7)
+#define VRC4173_GIU_IRQ         VRC4173_IRQ(8)
+#define VRC4173_AC97_IRQ        VRC4173_IRQ(9)
+#define VRC4173_AC97INT1_IRQ    VRC4173_IRQ(10)
+/* RFU */
+#define VRC4173_DOZEPIU_IRQ     VRC4173_IRQ(13)
+#define VRC4173_IRQ_LAST        VRC4173_DOZEPIU_IRQ
+
+/*
+ * PCI I/O accesses
+ */
+#ifdef CONFIG_VRC4173
+
+extern unsigned long vrc4173_io_offset;
+
+#define set_vrc4173_io_offset(offset)   do { vrc4173_io_offset = (offset); } while (0)
+
+#define vrc4173_outb(val,port)          outb((val), vrc4173_io_offset+(port))
+#define vrc4173_outw(val,port)          outw((val), vrc4173_io_offset+(port))
+#define vrc4173_outl(val,port)          outl((val), vrc4173_io_offset+(port))
+#define vrc4173_outb_p(val,port)        outb_p((val), vrc4173_io_offset+(port))
+#define vrc4173_outw_p(val,port)        outw_p((val), vrc4173_io_offset+(port))
+#define vrc4173_outl_p(val,port)        outl_p((val), vrc4173_io_offset+(port))
+
+#define vrc4173_inb(port)               inb(vrc4173_io_offset+(port))
+#define vrc4173_inw(port)               inw(vrc4173_io_offset+(port))
+#define vrc4173_inl(port)               inl(vrc4173_io_offset+(port))
+#define vrc4173_inb_p(port)             inb_p(vrc4173_io_offset+(port))
+#define vrc4173_inw_p(port)             inw_p(vrc4173_io_offset+(port))
+#define vrc4173_inl_p(port)             inl_p(vrc4173_io_offset+(port))
+
+#define vrc4173_outsb(port,addr,count)  outsb(vrc4173_io_offset+(port),(addr),(count))
+#define vrc4173_outsw(port,addr,count)  outsw(vrc4173_io_offset+(port),(addr),(count))
+#define vrc4173_outsl(port,addr,count)  outsl(vrc4173_io_offset+(port),(addr),(count))
+
+#define vrc4173_insb(port,addr,count)   insb(vrc4173_io_offset+(port),(addr),(count))
+#define vrc4173_insw(port,addr,count)   insw(vrc4173_io_offset+(port),(addr),(count))
+#define vrc4173_insl(port,addr,count)   insl(vrc4173_io_offset+(port),(addr),(count))
+
+#else
+
+#define set_vrc4173_io_offset(offset)   do {} while (0)
+
+#define vrc4173_outb(val,port)          do {} while (0)
+#define vrc4173_outw(val,port)          do {} while (0)
+#define vrc4173_outl(val,port)          do {} while (0)
+#define vrc4173_outb_p(val,port)        do {} while (0)
+#define vrc4173_outw_p(val,port)        do {} while (0)
+#define vrc4173_outl_p(val,port)        do {} while (0)
+
+#define vrc4173_inb(port)               0
+#define vrc4173_inw(port)               0
+#define vrc4173_inl(port)               0
+#define vrc4173_inb_p(port)             0
+#define vrc4173_inw_p(port)             0
+#define vrc4173_inl_p(port)             0
+
+#define vrc4173_outsb(port,addr,count)  do {} while (0)
+#define vrc4173_outsw(port,addr,count)  do {} while (0)
+#define vrc4173_outsl(port,addr,count)  do {} while (0)
+
+#define vrc4173_insb(port,addr,count)   do {} while (0)
+#define vrc4173_insw(port,addr,count)   do {} while (0)
+#define vrc4173_insl(port,addr,count)   do {} while (0)
+
+#endif
+
+/*
+ * Clock Mask Unit
+ */
+typedef enum vrc4173_clock {
+        VRC4173_PIU_CLOCK,
+        VRC4173_KIU_CLOCK,
+        VRC4173_AIU_CLOCK,
+        VRC4173_PS2_CH1_CLOCK,
+        VRC4173_PS2_CH2_CLOCK,
+        VRC4173_USBU_PCI_CLOCK,
+        VRC4173_CARDU1_PCI_CLOCK,
+        VRC4173_CARDU2_PCI_CLOCK,
+        VRC4173_AC97U_PCI_CLOCK,
+        VRC4173_USBU_48MHz_CLOCK,
+        VRC4173_EXT_48MHz_CLOCK,
+        VRC4173_48MHz_CLOCK,
+} vrc4173_clock_t;
+
+#ifdef CONFIG_VRC4173
+
+extern void vrc4173_supply_clock(vrc4173_clock_t clock);
+extern void vrc4173_mask_clock(vrc4173_clock_t clock);
+
+#else
+
+static inline void vrc4173_supply_clock(vrc4173_clock_t clock) {}
+static inline void vrc4173_mask_clock(vrc4173_clock_t clock) {}
+
+#endif
+
+/*
+ * Interupt Control Unit
+ */
+
+#define VRC4173_PIUINT_COMMAND          0x0040
+#define VRC4173_PIUINT_DATA             0x0020
+#define VRC4173_PIUINT_PAGE1            0x0010
+#define VRC4173_PIUINT_PAGE0            0x0008
+#define VRC4173_PIUINT_DATALOST         0x0004
+#define VRC4173_PIUINT_STATUSCHANGE     0x0001
+
+#ifdef CONFIG_VRC4173
+
+extern void vrc4173_enable_piuint(uint16_t mask);
+extern void vrc4173_disable_piuint(uint16_t mask);
+
+#else
+
+static inline void vrc4173_enable_piuint(uint16_t mask) {}
+static inline void vrc4173_disable_piuint(uint16_t mask) {}
+
+#endif
+
+#define VRC4173_AIUINT_INPUT_DMAEND     0x0800
+#define VRC4173_AIUINT_INPUT_DMAHALT    0x0400
+#define VRC4173_AIUINT_INPUT_DATALOST   0x0200
+#define VRC4173_AIUINT_INPUT_DATA       0x0100
+#define VRC4173_AIUINT_OUTPUT_DMAEND    0x0008
+#define VRC4173_AIUINT_OUTPUT_DMAHALT   0x0004
+#define VRC4173_AIUINT_OUTPUT_NODATA    0x0002
+
+#ifdef CONFIG_VRC4173
+
+extern void vrc4173_enable_aiuint(uint16_t mask);
+extern void vrc4173_disable_aiuint(uint16_t mask);
+
+#else
+
+static inline void vrc4173_enable_aiuint(uint16_t mask) {}
+static inline void vrc4173_disable_aiuint(uint16_t mask) {}
+
+#endif
+
+#define VRC4173_KIUINT_DATALOST         0x0004
+#define VRC4173_KIUINT_DATAREADY        0x0002
+#define VRC4173_KIUINT_SCAN             0x0001
+
+#ifdef CONFIG_VRC4173
+
+extern void vrc4173_enable_kiuint(uint16_t mask);
+extern void vrc4173_disable_kiuint(uint16_t mask);
+
+#else
+
+static inline void vrc4173_enable_kiuint(uint16_t mask) {}
+static inline void vrc4173_disable_kiuint(uint16_t mask) {}
+
+#endif
+
+/*
+ * General-Purpose I/O Unit
+ */
+typedef enum vrc4173_function {
+        PS2_CHANNEL1,
+        PS2_CHANNEL2,
+        TOUCHPANEL,
+        KEYBOARD_8SCANLINES,
+        KEYBOARD_10SCANLINES,
+        KEYBOARD_12SCANLINES,
+        GPIO_0_15PINS,
+        GPIO_16_20PINS,
+} vrc4173_function_t;
+
+#ifdef CONFIG_VRC4173
+
+extern void vrc4173_select_function(vrc4173_function_t function);
+
+#else
+
+static inline void vrc4173_select_function(vrc4173_function_t function) {}
+
+#endif
+
+#endif /* __NEC_VRC4173_H */
diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h
new file mode 100644
index 000000000000..dfe01b43fb79
--- /dev/null
+++ b/include/asm-mips/vr41xx/workpad.h
@@ -0,0 +1,43 @@
+/*
+ *  workpad.h, Include file for IBM WorkPad z50.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __IBM_WORKPAD_H
+#define __IBM_WORKPAD_H
+
+#include <asm/addrspace.h>
+#include <asm/vr41xx/vr41xx.h>
+
+/*
+ * Board specific address mapping
+ */
+#define VR41XX_ISA_MEM_BASE             0x10000000
+#define VR41XX_ISA_MEM_SIZE             0x04000000
+
+/* VR41XX_ISA_IO_BASE includes offset from real base. */
+#define VR41XX_ISA_IO_BASE              0x15000000
+#define VR41XX_ISA_IO_SIZE              0x03000000
+
+#define ISA_BUS_IO_BASE                 0
+#define ISA_BUS_IO_SIZE                 VR41XX_ISA_IO_SIZE
+
+#define IO_PORT_BASE                    KSEG1ADDR(VR41XX_ISA_IO_BASE)
+#define IO_PORT_RESOURCE_START          ISA_BUS_IO_BASE
+#define IO_PORT_RESOURCE_END            (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
+
+#endif /* __IBM_WORKPAD_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
new file mode 100644
index 000000000000..c4a704121343
--- /dev/null
+++ b/include/asm-mips/war.h
@@ -0,0 +1,224 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004 by Ralf Baechle
+ */
+#ifndef _ASM_WAR_H
+#define _ASM_WAR_H
+
+#include <linux/config.h>
+
+/*
+ * Another R4600 erratum.  Due to the lack of errata information the exact
+ * technical details aren't known.  I've experimentally found that disabling
+ * interrupts during indexed I-cache flushes seems to be sufficient to deal
+ * with the issue.
+ *
+ * #define R4600_V1_INDEX_ICACHEOP_WAR 1
+ */
+
+/*
+ * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
+ *
+ *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
+ *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
+ *      executed if there is no other dcache activity. If the dcache is
+ *      accessed for another instruction immeidately preceding when these
+ *      cache instructions are executing, it is possible that the dcache
+ *      tag match outputs used by these cache instructions will be
+ *      incorrect. These cache instructions should be preceded by at least
+ *      four instructions that are not any kind of load or store
+ *      instruction.
+ *
+ *      This is not allowed:    lw
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              cache       Hit_Writeback_Invalidate_D
+ *
+ *      This is allowed:        lw
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              cache       Hit_Writeback_Invalidate_D
+ *
+ * #define R4600_V1_HIT_CACHEOP_WAR 1
+ */
+
+
+/*
+ * Writeback and invalidate the primary cache dcache before DMA.
+ *
+ * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
+ * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
+ * operate correctly if the internal data cache refill buffer is empty.  These
+ * CACHE instructions should be separated from any potential data cache miss
+ * by a load instruction to an uncached address to empty the response buffer."
+ * (Revision 2.0 device errata from IDT available on http://www.idt.com/
+ * in .pdf format.)
+ *
+ * #define R4600_V2_HIT_CACHEOP_WAR 1
+ */
+
+/*
+ * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
+ */
+#ifdef CONFIG_SGI_IP22
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     1
+#define R4600_V1_HIT_CACHEOP_WAR        1
+#define R4600_V2_HIT_CACHEOP_WAR        1
+
+#endif
+
+/*
+ * But the RM200C seems to have been shipped only with V2.0 R4600s
+ */
+#ifdef CONFIG_SNI_RM200_PCI
+
+#define R4600_V2_HIT_CACHEOP_WAR        1
+
+#endif
+
+#ifdef CONFIG_CPU_R5432
+
+/*
+ * When an interrupt happens on a CP0 register read instruction, CPU may
+ * lock up or read corrupted values of CP0 registers after it enters
+ * the exception handler.
+ *
+ * This workaround makes sure that we read a "safe" CP0 register as the
+ * first thing in the exception handler, which breaks one of the
+ * pre-conditions for this problem.
+ */
+#define R5432_CP0_INTERRUPT_WAR 1
+
+#endif
+
+#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
+    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
+
+/*
+ * Workaround for the Sibyte M3 errata the text of which can be found at
+ *
+ *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
+ *
+ * This will enable the use of a special TLB refill handler which does a
+ * consistency check on the information in c0_badvaddr and c0_entryhi and
+ * will just return and take the exception again if the information was
+ * found to be inconsistent.
+ */
+#define BCM1250_M3_WAR 1
+
+/* 
+ * This is a DUART workaround related to glitches around register accesses
+ */
+#define SIBYTE_1956_WAR 1
+
+#endif
+
+/*
+ * Fill buffers not flushed on CACHE instructions
+ * 
+ * Hit_Invalidate_I cacheops invalidate an icache line but the refill
+ * for that line can get stale data from the fill buffer instead of
+ * accessing memory if the previous icache miss was also to that line.
+ *
+ * Workaround: generate an icache refill from a different line
+ *
+ * Affects:
+ *  MIPS 4K             RTL revision <3.0, PRID revision <4
+ */
+#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
+    defined(CONFIG_MIPS_SEAD)
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#endif
+
+/*
+ * Missing implicit forced flush of evictions caused by CACHE
+ * instruction
+ *
+ * Evictions caused by a CACHE instructions are not forced on to the
+ * bus. The BIU gives higher priority to fetches than to the data from
+ * the eviction buffer and no collision detection is performed between
+ * fetches and pending data from the eviction buffer.
+ *
+ * Workaround: Execute a SYNC instruction after the cache instruction
+ *
+ * Affects:
+ *   MIPS 5Kc,5Kf       RTL revision <2.3, PRID revision <8
+ *   MIPS 20Kc          RTL revision <4.0, PRID revision <?
+ */
+#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
+    defined(CONFIG_MIPS_SEAD)
+#define MIPS_CACHE_SYNC_WAR 1
+#endif
+
+/*
+ * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
+ * the line which this instruction itself exists, the following
+ * operation is not guaranteed."
+ *
+ * Workaround: do two phase flushing for Index_Invalidate_I
+ */
+#ifdef CONFIG_CPU_TX49XX
+#define TX49XX_ICACHE_INDEX_INV_WAR 1
+#endif
+
+/*
+ * On the RM9000 there is a problem which makes the CreateDirtyExclusive
+ * cache operation unusable on SMP systems.
+ */
+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
+#define  RM9000_CDEX_SMP_WAR            1
+#endif
+
+/*
+ * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * may cause ll / sc and lld / scd sequences to execute non-atomically.
+ */
+#ifdef CONFIG_SGI_IP27
+#define R10000_LLSC_WAR 1
+#endif
+
+/*
+ * Workarounds default to off
+ */
+#ifndef R4600_V1_INDEX_ICACHEOP_WAR
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#endif
+#ifndef R4600_V1_HIT_CACHEOP_WAR
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#endif
+#ifndef R4600_V2_HIT_CACHEOP_WAR
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#endif
+#ifndef R5432_CP0_INTERRUPT_WAR
+#define R5432_CP0_INTERRUPT_WAR         0
+#endif
+#ifndef BCM1250_M3_WAR
+#define BCM1250_M3_WAR                  0
+#endif
+#ifndef SIBYTE_1956_WAR
+#define SIBYTE_1956_WAR                 0
+#endif
+#ifndef MIPS4K_ICACHE_REFILL_WAR
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#endif
+#ifndef MIPS_CACHE_SYNC_WAR
+#define MIPS_CACHE_SYNC_WAR             0
+#endif
+#ifndef TX49XX_ICACHE_INDEX_INV_WAR
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#endif
+#ifndef RM9000_CDEX_SMP_WAR
+#define RM9000_CDEX_SMP_WAR             0
+#endif
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR                 0
+#endif
+
+#endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
new file mode 100644
index 000000000000..6aa90cae1114
--- /dev/null
+++ b/include/asm-mips/watch.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle
+ */
+#ifndef _ASM_WATCH_H
+#define _ASM_WATCH_H
+
+#include <linux/linkage.h>
+
+/*
+ * Types of reference for watch_set()
+ */
+enum wref_type {
+        wr_save = 1,
+        wr_load = 2
+};
+
+extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref);
+extern asmlinkage void __watch_clear(void);
+extern asmlinkage void __watch_reenable(void);
+
+#define watch_set(addr, ref)                                    \
+        if (cpu_has_watch)                                      \
+                __watch_set(addr, ref)
+#define watch_clear()                                           \
+        if (cpu_has_watch)                                      \
+                __watch_clear()
+#define watch_reenable()                                        \
+        if (cpu_has_watch)                                      \
+                __watch_reenable()
+
+#endif /* _ASM_WATCH_H */
diff --git a/include/asm-mips/wbflush.h b/include/asm-mips/wbflush.h
new file mode 100644
index 000000000000..c3bef50f37a8
--- /dev/null
+++ b/include/asm-mips/wbflush.h
@@ -0,0 +1,35 @@
+/*
+ * Header file for using the wbflush routine
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef _ASM_WBFLUSH_H
+#define _ASM_WBFLUSH_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_CPU_HAS_WB
+
+extern void (*__wbflush)(void);
+extern void wbflush_setup(void);
+
+#define wbflush()                       \
+        do {                            \
+                __sync();               \
+                __wbflush();            \
+        } while (0)
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wbflush_setup() do { } while (0)
+
+#define wbflush() fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#endif /* _ASM_WBFLUSH_H */
diff --git a/include/asm-mips/xor.h b/include/asm-mips/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/include/asm-mips/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h
new file mode 100644
index 000000000000..4a60f27c8817
--- /dev/null
+++ b/include/asm-mips/xtalk/xtalk.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xtalk.h -- platform-independent crosstalk interface, derived from
+ * IRIX <sys/PCI/bridge.h>, revision 1.38.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XTALK_H
+#define _ASM_XTALK_XTALK_H
+
+#ifndef __ASSEMBLY__
+/*
+ * User-level device driver visible types
+ */
+typedef char            xwidgetnum_t;   /* xtalk widget number  (0..15) */
+
+#define XWIDGET_NONE            -1
+
+typedef int xwidget_part_num_t; /* xtalk widget part number */
+
+#define XWIDGET_PART_NUM_NONE   -1
+
+typedef int             xwidget_rev_num_t;      /* xtalk widget revision number */
+
+#define XWIDGET_REV_NUM_NONE    -1
+
+typedef int xwidget_mfg_num_t;  /* xtalk widget manufacturing ID */
+
+#define XWIDGET_MFG_NUM_NONE    -1
+
+typedef struct xtalk_piomap_s *xtalk_piomap_t;
+
+/* It is often convenient to fold the XIO target port
+ * number into the XIO address.
+ */
+#define XIO_NOWHERE     (0xFFFFFFFFFFFFFFFFull)
+#define XIO_ADDR_BITS   (0x0000FFFFFFFFFFFFull)
+#define XIO_PORT_BITS   (0xF000000000000000ull)
+#define XIO_PORT_SHIFT  (60)
+
+#define XIO_PACKED(x)   (((x)&XIO_PORT_BITS) != 0)
+#define XIO_ADDR(x)     ((x)&XIO_ADDR_BITS)
+#define XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
+#define XIO_PACK(p,o)   ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XTALK_H */
diff --git a/include/asm-mips/xtalk/xwidget.h b/include/asm-mips/xtalk/xwidget.h
new file mode 100644
index 000000000000..b4a13d7405ee
--- /dev/null
+++ b/include/asm-mips/xtalk/xwidget.h
@@ -0,0 +1,167 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xwidget.h - generic crosstalk widget header file, derived from IRIX
+ * <sys/xtalk/xtalkwidget.h>, revision 1.32.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XWIDGET_H
+#define _ASM_XTALK_XWIDGET_H
+
+#include <linux/types.h>
+#include <asm/xtalk/xtalk.h>
+
+#define WIDGET_ID                       0x04
+#define WIDGET_STATUS                   0x0c
+#define WIDGET_ERR_UPPER_ADDR           0x14
+#define WIDGET_ERR_LOWER_ADDR           0x1c
+#define WIDGET_CONTROL                  0x24
+#define WIDGET_REQ_TIMEOUT              0x2c
+#define WIDGET_INTDEST_UPPER_ADDR       0x34
+#define WIDGET_INTDEST_LOWER_ADDR       0x3c
+#define WIDGET_ERR_CMD_WORD             0x44
+#define WIDGET_LLP_CFG                  0x4c
+#define WIDGET_TFLUSH                   0x54
+
+/* WIDGET_ID */
+#define WIDGET_REV_NUM                  0xf0000000
+#define WIDGET_PART_NUM                 0x0ffff000
+#define WIDGET_MFG_NUM                  0x00000ffe
+#define WIDGET_REV_NUM_SHFT             28
+#define WIDGET_PART_NUM_SHFT            12
+#define WIDGET_MFG_NUM_SHFT             1
+
+#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
+#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
+#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
+
+/* WIDGET_STATUS */
+#define WIDGET_LLP_REC_CNT              0xff000000
+#define WIDGET_LLP_TX_CNT               0x00ff0000
+#define WIDGET_PENDING                  0x0000001f
+
+/* WIDGET_ERR_UPPER_ADDR */
+#define WIDGET_ERR_UPPER_ADDR_ONLY      0x0000ffff
+
+/* WIDGET_CONTROL */
+#define WIDGET_F_BAD_PKT                0x00010000
+#define WIDGET_LLP_XBAR_CRD             0x0000f000
+#define WIDGET_LLP_XBAR_CRD_SHFT        12
+#define WIDGET_CLR_RLLP_CNT             0x00000800
+#define WIDGET_CLR_TLLP_CNT             0x00000400
+#define WIDGET_SYS_END                  0x00000200
+#define WIDGET_MAX_TRANS                0x000001f0
+#define WIDGET_WIDGET_ID                0x0000000f
+
+/* WIDGET_INTDEST_UPPER_ADDR */
+#define WIDGET_INT_VECTOR               0xff000000
+#define WIDGET_INT_VECTOR_SHFT          24
+#define WIDGET_TARGET_ID                0x000f0000
+#define WIDGET_TARGET_ID_SHFT           16
+#define WIDGET_UPP_ADDR                 0x0000ffff
+
+/* WIDGET_ERR_CMD_WORD */
+#define WIDGET_DIDN                     0xf0000000
+#define WIDGET_SIDN                     0x0f000000
+#define WIDGET_PACTYP                   0x00f00000
+#define WIDGET_TNUM                     0x000f8000
+#define WIDGET_COHERENT                 0x00004000
+#define WIDGET_DS                       0x00003000
+#define WIDGET_GBR                      0x00000800
+#define WIDGET_VBPM                     0x00000400
+#define WIDGET_ERROR                    0x00000200
+#define WIDGET_BARRIER                  0x00000100
+
+/* WIDGET_LLP_CFG */
+#define WIDGET_LLP_MAXRETRY             0x03ff0000
+#define WIDGET_LLP_MAXRETRY_SHFT        16
+#define WIDGET_LLP_NULLTIMEOUT          0x0000fc00
+#define WIDGET_LLP_NULLTIMEOUT_SHFT     10
+#define WIDGET_LLP_MAXBURST             0x000003ff
+#define WIDGET_LLP_MAXBURST_SHFT        0
+
+/*
+ * according to the crosstalk spec, only 32-bits access to the widget
+ * configuration registers is allowed.  some widgets may allow 64-bits
+ * access but software should not depend on it.  registers beyond the
+ * widget target flush register are widget dependent thus will not be
+ * defined here
+ */
+#ifndef __ASSEMBLY__
+typedef u32 widgetreg_t;
+
+/* widget configuration registers */
+typedef volatile struct widget_cfg {
+        widgetreg_t             w_pad_0;                /* 0x00 */
+        widgetreg_t             w_id;                   /* 0x04 */
+        widgetreg_t             w_pad_1;                /* 0x08 */
+        widgetreg_t             w_status;               /* 0x0c */
+        widgetreg_t             w_pad_2;                /* 0x10 */
+        widgetreg_t             w_err_upper_addr;       /* 0x14 */
+        widgetreg_t             w_pad_3;                /* 0x18 */
+        widgetreg_t             w_err_lower_addr;       /* 0x1c */
+        widgetreg_t             w_pad_4;                /* 0x20 */
+        widgetreg_t             w_control;              /* 0x24 */
+        widgetreg_t             w_pad_5;                /* 0x28 */
+        widgetreg_t             w_req_timeout;          /* 0x2c */
+        widgetreg_t             w_pad_6;                /* 0x30 */
+        widgetreg_t             w_intdest_upper_addr;   /* 0x34 */
+        widgetreg_t             w_pad_7;                /* 0x38 */
+        widgetreg_t             w_intdest_lower_addr;   /* 0x3c */
+        widgetreg_t             w_pad_8;                /* 0x40 */
+        widgetreg_t             w_err_cmd_word;         /* 0x44 */
+        widgetreg_t             w_pad_9;                /* 0x48 */
+        widgetreg_t             w_llp_cfg;              /* 0x4c */
+        widgetreg_t             w_pad_10;               /* 0x50 */
+        widgetreg_t             w_tflush;               /* 0x54 */
+} widget_cfg_t;
+
+typedef struct {
+        unsigned        didn:4;
+        unsigned        sidn:4;
+        unsigned        pactyp:4;
+        unsigned        tnum:5;
+        unsigned        ct:1;
+        unsigned        ds:2;
+        unsigned        gbr:1;
+        unsigned        vbpm:1;
+        unsigned        error:1;
+        unsigned        bo:1;
+        unsigned        other:8;
+} w_err_cmd_word_f;
+
+typedef union {
+        widgetreg_t             r;
+        w_err_cmd_word_f        f;
+} w_err_cmd_word_u;
+
+typedef struct xwidget_info_s *xwidget_info_t;
+
+/*
+ * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
+ */
+typedef struct xwidget_hwid_s {
+        xwidget_part_num_t      part_num;
+        xwidget_rev_num_t       rev_num;
+        xwidget_mfg_num_t       mfg_num;
+} *xwidget_hwid_t;
+
+
+/*
+ * Returns 1 if a driver that handles devices described by hwid1 is able
+ * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
+ * numbers at all.
+ */
+#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
+        (((hwid1)->part_num == (hwid2)->part_num) && \
+        (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid1)->mfg_num == (hwid2)->mfg_num)))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XWIDGET_H */
diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h
new file mode 100644
index 000000000000..75c0ddfeca13
--- /dev/null
+++ b/include/asm-mips/xxs1500.h
@@ -0,0 +1,35 @@
+/*
+ * MyCable XXS1500 Referrence Board
+ *
+ * Copyright 2003 MontaVista Software Inc.
+ * Author: Pete Popov, MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * 
+ */
+#ifndef __ASM_XXS1500_H
+#define __ASM_XXS1500_H
+
+/* PCMCIA XXS1500 specific defines */
+#define PCMCIA_MAX_SOCK 0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+#define PCMCIA_IRQ AU1000_GPIO_4
+
+#endif /* __ASM_XXS1500_ */