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-rw-r--r--include/asm-mips/addrspace.h1
-rw-r--r--include/asm-mips/cpu.h6
-rw-r--r--include/asm-mips/delay.h22
-rw-r--r--include/asm-mips/futex.h141
-rw-r--r--include/asm-mips/inst.h33
-rw-r--r--include/asm-mips/mipsregs.h2
-rw-r--r--include/asm-mips/page.h2
-rw-r--r--include/asm-mips/pgtable-32.h61
-rw-r--r--include/asm-mips/pgtable-64.h13
-rw-r--r--include/asm-mips/pgtable.h103
-rw-r--r--include/asm-mips/sigcontext.h10
-rw-r--r--include/asm-mips/smp.h5
-rw-r--r--include/asm-mips/sparsemem.h14
13 files changed, 295 insertions, 118 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 42520cc84b0f..1386af1cb7d9 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -129,6 +129,7 @@
129#if defined (CONFIG_CPU_R4300) \ 129#if defined (CONFIG_CPU_R4300) \
130 || defined (CONFIG_CPU_R4X00) \ 130 || defined (CONFIG_CPU_R4X00) \
131 || defined (CONFIG_CPU_R5000) \ 131 || defined (CONFIG_CPU_R5000) \
132 || defined (CONFIG_CPU_RM7000) \
132 || defined (CONFIG_CPU_NEVADA) \ 133 || defined (CONFIG_CPU_NEVADA) \
133 || defined (CONFIG_CPU_TX49XX) \ 134 || defined (CONFIG_CPU_TX49XX) \
134 || defined (CONFIG_CPU_MIPS64) 135 || defined (CONFIG_CPU_MIPS64)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 818b9a97e214..dff2a0a52f8f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,6 +51,7 @@
51#define PRID_IMP_R4300 0x0b00 51#define PRID_IMP_R4300 0x0b00
52#define PRID_IMP_VR41XX 0x0c00 52#define PRID_IMP_VR41XX 0x0c00
53#define PRID_IMP_R12000 0x0e00 53#define PRID_IMP_R12000 0x0e00
54#define PRID_IMP_R14000 0x0f00
54#define PRID_IMP_R8000 0x1000 55#define PRID_IMP_R8000 0x1000
55#define PRID_IMP_PR4450 0x1200 56#define PRID_IMP_PR4450 0x1200
56#define PRID_IMP_R4600 0x2000 57#define PRID_IMP_R4600 0x2000
@@ -87,6 +88,7 @@
87#define PRID_IMP_24K 0x9300 88#define PRID_IMP_24K 0x9300
88#define PRID_IMP_34K 0x9500 89#define PRID_IMP_34K 0x9500
89#define PRID_IMP_24KE 0x9600 90#define PRID_IMP_24KE 0x9600
91#define PRID_IMP_74K 0x9700
90 92
91/* 93/*
92 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 94 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -196,7 +198,9 @@
196#define CPU_34K 60 198#define CPU_34K 60
197#define CPU_PR4450 61 199#define CPU_PR4450 61
198#define CPU_SB1A 62 200#define CPU_SB1A 62
199#define CPU_LAST 62 201#define CPU_74K 63
202#define CPU_R14000 64
203#define CPU_LAST 64
200 204
201/* 205/*
202 * ISA Level encodings 206 * ISA Level encodings
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index 64dd45150f64..928f30f8c45c 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -19,20 +19,22 @@ static inline void __delay(unsigned long loops)
19{ 19{
20 if (sizeof(long) == 4) 20 if (sizeof(long) == 4)
21 __asm__ __volatile__ ( 21 __asm__ __volatile__ (
22 ".set\tnoreorder\n" 22 " .set noreorder \n"
23 "1:\tbnez\t%0,1b\n\t" 23 " .align 3 \n"
24 "subu\t%0,1\n\t" 24 "1: bnez %0, 1b \n"
25 ".set\treorder" 25 " subu %0, 1 \n"
26 " .set reorder \n"
26 : "=r" (loops) 27 : "=r" (loops)
27 : "0" (loops)); 28 : "0" (loops));
28 else if (sizeof(long) == 8) 29 else if (sizeof(long) == 8)
29 __asm__ __volatile__ ( 30 __asm__ __volatile__ (
30 ".set\tnoreorder\n" 31 " .set noreorder \n"
31 "1:\tbnez\t%0,1b\n\t" 32 " .align 3 \n"
32 "dsubu\t%0,1\n\t" 33 "1: bnez %0, 1b \n"
33 ".set\treorder" 34 " dsubu %0, 1 \n"
34 :"=r" (loops) 35 " .set reorder \n"
35 :"0" (loops)); 36 : "=r" (loops)
37 : "0" (loops));
36} 38}
37 39
38 40
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index a554089991f2..12d118f1bc9c 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -7,6 +7,7 @@
7#include <linux/futex.h> 7#include <linux/futex.h>
8#include <asm/errno.h> 8#include <asm/errno.h>
9#include <asm/uaccess.h> 9#include <asm/uaccess.h>
10#include <asm/war.h>
10 11
11#ifdef CONFIG_SMP 12#ifdef CONFIG_SMP
12#define __FUTEX_SMP_SYNC " sync \n" 13#define __FUTEX_SMP_SYNC " sync \n"
@@ -16,30 +17,58 @@
16 17
17#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 18#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
18{ \ 19{ \
19 __asm__ __volatile__( \ 20 if (cpu_has_llsc && R10000_LLSC_WAR) { \
20 " .set push \n" \ 21 __asm__ __volatile__( \
21 " .set noat \n" \ 22 " .set push \n" \
22 " .set mips3 \n" \ 23 " .set noat \n" \
23 "1: ll %1, (%3) # __futex_atomic_op1 \n" \ 24 " .set mips3 \n" \
24 " .set mips0 \n" \ 25 "1: ll %1, (%3) # __futex_atomic_op \n" \
25 " " insn " \n" \ 26 " .set mips0 \n" \
26 " .set mips3 \n" \ 27 " " insn " \n" \
27 "2: sc $1, (%3) \n" \ 28 " .set mips3 \n" \
28 " beqzl $1, 1b \n" \ 29 "2: sc $1, (%3) \n" \
29 __FUTEX_SMP_SYNC \ 30 " beqzl $1, 1b \n" \
30 "3: \n" \ 31 __FUTEX_SMP_SYNC \
31 " .set pop \n" \ 32 "3: \n" \
32 " .set mips0 \n" \ 33 " .set pop \n" \
33 " .section .fixup,\"ax\" \n" \ 34 " .set mips0 \n" \
34 "4: li %0, %5 \n" \ 35 " .section .fixup,\"ax\" \n" \
35 " j 2b \n" \ 36 "4: li %0, %5 \n" \
36 " .previous \n" \ 37 " j 2b \n" \
37 " .section __ex_table,\"a\" \n" \ 38 " .previous \n" \
38 " "__UA_ADDR "\t1b, 4b \n" \ 39 " .section __ex_table,\"a\" \n" \
39 " "__UA_ADDR "\t2b, 4b \n" \ 40 " "__UA_ADDR "\t1b, 4b \n" \
40 " .previous \n" \ 41 " "__UA_ADDR "\t2b, 4b \n" \
41 : "=r" (ret), "=r" (oldval) \ 42 " .previous \n" \
42 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 43 : "=r" (ret), "=r" (oldval) \
44 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
45 } else if (cpu_has_llsc) { \
46 __asm__ __volatile__( \
47 " .set push \n" \
48 " .set noat \n" \
49 " .set mips3 \n" \
50 "1: ll %1, (%3) # __futex_atomic_op \n" \
51 " .set mips0 \n" \
52 " " insn " \n" \
53 " .set mips3 \n" \
54 "2: sc $1, (%3) \n" \
55 " beqz $1, 1b \n" \
56 __FUTEX_SMP_SYNC \
57 "3: \n" \
58 " .set pop \n" \
59 " .set mips0 \n" \
60 " .section .fixup,\"ax\" \n" \
61 "4: li %0, %5 \n" \
62 " j 2b \n" \
63 " .previous \n" \
64 " .section __ex_table,\"a\" \n" \
65 " "__UA_ADDR "\t1b, 4b \n" \
66 " "__UA_ADDR "\t2b, 4b \n" \
67 " .previous \n" \
68 : "=r" (ret), "=r" (oldval) \
69 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
70 } else \
71 ret = -ENOSYS; \
43} 72}
44 73
45static inline int 74static inline int
@@ -102,7 +131,69 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
102static inline int 131static inline int
103futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 132futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
104{ 133{
105 return -ENOSYS; 134 int retval;
135
136 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
137 return -EFAULT;
138
139 if (cpu_has_llsc && R10000_LLSC_WAR) {
140 __asm__ __volatile__(
141 "# futex_atomic_cmpxchg_inatomic \n"
142 " .set push \n"
143 " .set noat \n"
144 " .set mips3 \n"
145 "1: ll %0, %2 \n"
146 " bne %0, %z3, 3f \n"
147 " .set mips0 \n"
148 " move $1, %z4 \n"
149 " .set mips3 \n"
150 "2: sc $1, %1 \n"
151 " beqzl $1, 1b \n"
152 __FUTEX_SMP_SYNC
153 "3: \n"
154 " .set pop \n"
155 " .section .fixup,\"ax\" \n"
156 "4: li %0, %5 \n"
157 " j 3b \n"
158 " .previous \n"
159 " .section __ex_table,\"a\" \n"
160 " "__UA_ADDR "\t1b, 4b \n"
161 " "__UA_ADDR "\t2b, 4b \n"
162 " .previous \n"
163 : "=&r" (retval), "=R" (*uaddr)
164 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
165 : "memory");
166 } else if (cpu_has_llsc) {
167 __asm__ __volatile__(
168 "# futex_atomic_cmpxchg_inatomic \n"
169 " .set push \n"
170 " .set noat \n"
171 " .set mips3 \n"
172 "1: ll %0, %2 \n"
173 " bne %0, %z3, 3f \n"
174 " .set mips0 \n"
175 " move $1, %z4 \n"
176 " .set mips3 \n"
177 "2: sc $1, %1 \n"
178 " beqz $1, 1b \n"
179 __FUTEX_SMP_SYNC
180 "3: \n"
181 " .set pop \n"
182 " .section .fixup,\"ax\" \n"
183 "4: li %0, %5 \n"
184 " j 3b \n"
185 " .previous \n"
186 " .section __ex_table,\"a\" \n"
187 " "__UA_ADDR "\t1b, 4b \n"
188 " "__UA_ADDR "\t2b, 4b \n"
189 " .previous \n"
190 : "=&r" (retval), "=R" (*uaddr)
191 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
192 : "memory");
193 } else
194 return -ENOSYS;
195
196 return retval;
106} 197}
107 198
108#endif 199#endif
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index e0745f4ff624..1ed8d0f62577 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -6,6 +6,7 @@
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle 8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
9 */ 10 */
10#ifndef _ASM_INST_H 11#ifndef _ASM_INST_H
11#define _ASM_INST_H 12#define _ASM_INST_H
@@ -21,14 +22,14 @@ enum major_op {
21 cop0_op, cop1_op, cop2_op, cop1x_op, 22 cop0_op, cop1_op, cop2_op, cop1x_op,
22 beql_op, bnel_op, blezl_op, bgtzl_op, 23 beql_op, bnel_op, blezl_op, bgtzl_op,
23 daddi_op, daddiu_op, ldl_op, ldr_op, 24 daddi_op, daddiu_op, ldl_op, ldr_op,
24 major_1c_op, jalx_op, major_1e_op, major_1f_op, 25 spec2_op, jalx_op, mdmx_op, spec3_op,
25 lb_op, lh_op, lwl_op, lw_op, 26 lb_op, lh_op, lwl_op, lw_op,
26 lbu_op, lhu_op, lwr_op, lwu_op, 27 lbu_op, lhu_op, lwr_op, lwu_op,
27 sb_op, sh_op, swl_op, sw_op, 28 sb_op, sh_op, swl_op, sw_op,
28 sdl_op, sdr_op, swr_op, cache_op, 29 sdl_op, sdr_op, swr_op, cache_op,
29 ll_op, lwc1_op, lwc2_op, pref_op, 30 ll_op, lwc1_op, lwc2_op, pref_op,
30 lld_op, ldc1_op, ldc2_op, ld_op, 31 lld_op, ldc1_op, ldc2_op, ld_op,
31 sc_op, swc1_op, swc2_op, rdhwr_op, 32 sc_op, swc1_op, swc2_op, major_3b_op,
32 scd_op, sdc1_op, sdc2_op, sd_op 33 scd_op, sdc1_op, sdc2_op, sd_op
33}; 34};
34 35
@@ -37,7 +38,7 @@ enum major_op {
37 */ 38 */
38enum spec_op { 39enum spec_op {
39 sll_op, movc_op, srl_op, sra_op, 40 sll_op, movc_op, srl_op, sra_op,
40 sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ 41 sllv_op, pmon_op, srlv_op, srav_op,
41 jr_op, jalr_op, movz_op, movn_op, 42 jr_op, jalr_op, movz_op, movn_op,
42 syscall_op, break_op, spim_op, sync_op, 43 syscall_op, break_op, spim_op, sync_op,
43 mfhi_op, mthi_op, mflo_op, mtlo_op, 44 mfhi_op, mthi_op, mflo_op, mtlo_op,
@@ -55,6 +56,28 @@ enum spec_op {
55}; 56};
56 57
57/* 58/*
59 * func field of spec2 opcode.
60 */
61enum spec2_op {
62 madd_op, maddu_op, mul_op, spec2_3_unused_op,
63 msub_op, msubu_op, /* more unused ops */
64 clz_op = 0x20, clo_op,
65 dclz_op = 0x24, dclo_op,
66 sdbpp_op = 0x3f
67};
68
69/*
70 * func field of spec3 opcode.
71 */
72enum spec3_op {
73 ext_op, dextm_op, dextu_op, dext_op,
74 ins_op, dinsm_op, dinsu_op, dins_op,
75 bshfl_op = 0x20,
76 dbshfl_op = 0x24,
77 rdhwr_op = 0x3f
78};
79
80/*
58 * rt field of bcond opcodes. 81 * rt field of bcond opcodes.
59 */ 82 */
60enum rt_op { 83enum rt_op {
@@ -151,8 +174,8 @@ enum cop1x_func {
151 * func field for mad opcodes (MIPS IV). 174 * func field for mad opcodes (MIPS IV).
152 */ 175 */
153enum mad_func { 176enum mad_func {
154 madd_op = 0x08, msub_op = 0x0a, 177 madd_fp_op = 0x08, msub_fp_op = 0x0a,
155 nmadd_op = 0x0c, nmsub_op = 0x0e 178 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
156}; 179};
157 180
158/* 181/*
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index a2ef579f6b1a..5af7517fce8a 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -291,7 +291,7 @@
291#define ST0_DL (_ULCAST_(1) << 24) 291#define ST0_DL (_ULCAST_(1) << 24)
292 292
293/* 293/*
294 * Enable the MIPS DSP ASE 294 * Enable the MIPS MDMX and DSP ASEs
295 */ 295 */
296#define ST0_MX 0x01000000 296#define ST0_MX 0x01000000
297 297
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index a1eab136ff6c..4035ec79ecd4 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -139,9 +139,11 @@ typedef struct { unsigned long pgprot; } pgprot_t;
139 139
140#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 140#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
141 141
142#ifndef CONFIG_SPARSEMEM
142#ifndef CONFIG_NEED_MULTIPLE_NODES 143#ifndef CONFIG_NEED_MULTIPLE_NODES
143#define pfn_valid(pfn) ((pfn) < max_mapnr) 144#define pfn_valid(pfn) ((pfn) < max_mapnr)
144#endif 145#endif
146#endif
145 147
146#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 148#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
147#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 149#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4d6bc45df594..087c20769256 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -177,48 +177,67 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
177 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) 177 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
178 178
179/* 179/*
180 * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset 180 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
181 * into this range:
182 */ 181 */
183#define PTE_FILE_MAX_BITS 27 182#define PTE_FILE_MAX_BITS 28
184 183
185#define pte_to_pgoff(_pte) \ 184#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
186 ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) 185 (((_pte).pte >> 2 ) & 0x38) | \
186 (((_pte).pte >> 10) << 6 ))
187 187
188#define pgoff_to_pte(off) \ 188#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
189 ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) 189 (((off) & 0x38) << 2 ) | \
190 (((off) >> 6 ) << 10) | \
191 _PAGE_FILE })
190 192
191#else 193#else
192 194
193/* Swap entries must have VALID and GLOBAL bits cleared. */ 195/* Swap entries must have VALID and GLOBAL bits cleared. */
196#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
197#define __swp_type(x) (((x).val >> 2) & 0x1f)
198#define __swp_offset(x) ((x).val >> 7)
199#define __swp_entry(type,offset) \
200 ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
201#else
194#define __swp_type(x) (((x).val >> 8) & 0x1f) 202#define __swp_type(x) (((x).val >> 8) & 0x1f)
195#define __swp_offset(x) ((x).val >> 13) 203#define __swp_offset(x) ((x).val >> 13)
196#define __swp_entry(type,offset) \ 204#define __swp_entry(type,offset) \
197 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) 205 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
206#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
198 207
208#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
199/* 209/*
200 * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset 210 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
201 * into this range:
202 */ 211 */
203#define PTE_FILE_MAX_BITS 27 212#define PTE_FILE_MAX_BITS 30
204 213
205#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 214#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
206 /* fixme */ 215#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
207#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
208#define pgoff_to_pte(off) \
209 ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
210 216
211#else 217#else
212#define pte_to_pgoff(_pte) \ 218/*
213 ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) 219 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
220 */
221#define PTE_FILE_MAX_BITS 28
222
223#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
224 (((_pte).pte >> 2) & 0x8) | \
225 (((_pte).pte >> 8) << 4))
214 226
215#define pgoff_to_pte(off) \ 227#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
216 ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) 228 (((off) & 0x8) << 2) | \
229 (((off) >> 4) << 8) | \
230 _PAGE_FILE })
217#endif 231#endif
218 232
219#endif 233#endif
220 234
235#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
236#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
237#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
238#else
221#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 239#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
222#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 240#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
241#endif
223 242
224#endif /* _ASM_PGTABLE_32_H */ 243#endif /* _ASM_PGTABLE_32_H */
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 82166b254b27..2faf5c9ff127 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -224,15 +224,12 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
224#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 224#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
225 225
226/* 226/*
227 * Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset 227 * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
228 * into this range: 228 * make things easier, and only use the upper 56 bits for the page offset...
229 */ 229 */
230#define PTE_FILE_MAX_BITS 32 230#define PTE_FILE_MAX_BITS 56
231 231
232#define pte_to_pgoff(_pte) \ 232#define pte_to_pgoff(_pte) ((_pte).pte >> 8)
233 ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) 233#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) | _PAGE_FILE })
234
235#define pgoff_to_pte(off) \
236 ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
237 234
238#endif /* _ASM_PGTABLE_64_H */ 235#endif /* _ASM_PGTABLE_64_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 702a28fa7a34..d0af2a3b0152 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -70,7 +70,15 @@ extern unsigned long zero_page_mask;
70#define ZERO_PAGE(vaddr) \ 70#define ZERO_PAGE(vaddr) \
71 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) 71 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
72 72
73#define __HAVE_ARCH_MULTIPLE_ZERO_PAGE 73#define __HAVE_ARCH_MOVE_PTE
74#define move_pte(pte, prot, old_addr, new_addr) \
75({ \
76 pte_t newpte = (pte); \
77 if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \
78 pte_page(pte) == ZERO_PAGE(old_addr)) \
79 newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \
80 newpte; \
81})
74 82
75extern void paging_init(void); 83extern void paging_init(void);
76 84
@@ -82,10 +90,11 @@ extern void paging_init(void);
82#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 90#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
83#define pmd_page_kernel(pmd) pmd_val(pmd) 91#define pmd_page_kernel(pmd) pmd_val(pmd)
84 92
85#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
86#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
87
88#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 93#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
94
95#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
96#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
97
89static inline void set_pte(pte_t *ptep, pte_t pte) 98static inline void set_pte(pte_t *ptep, pte_t pte)
90{ 99{
91 ptep->pte_high = pte.pte_high; 100 ptep->pte_high = pte.pte_high;
@@ -93,27 +102,35 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
93 ptep->pte_low = pte.pte_low; 102 ptep->pte_low = pte.pte_low;
94 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); 103 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
95 104
96 if (pte_val(pte) & _PAGE_GLOBAL) { 105 if (pte.pte_low & _PAGE_GLOBAL) {
97 pte_t *buddy = ptep_buddy(ptep); 106 pte_t *buddy = ptep_buddy(ptep);
98 /* 107 /*
99 * Make sure the buddy is global too (if it's !none, 108 * Make sure the buddy is global too (if it's !none,
100 * it better already be global) 109 * it better already be global)
101 */ 110 */
102 if (pte_none(*buddy)) 111 if (pte_none(*buddy)) {
103 buddy->pte_low |= _PAGE_GLOBAL; 112 buddy->pte_low |= _PAGE_GLOBAL;
113 buddy->pte_high |= _PAGE_GLOBAL;
114 }
104 } 115 }
105} 116}
106#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 117#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
107 118
108static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 119static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
109{ 120{
121 pte_t null = __pte(0);
122
110 /* Preserve global status for the pair */ 123 /* Preserve global status for the pair */
111 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) 124 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
112 set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); 125 null.pte_low = null.pte_high = _PAGE_GLOBAL;
113 else 126
114 set_pte_at(mm, addr, ptep, __pte(0)); 127 set_pte_at(mm, addr, ptep, null);
115} 128}
116#else 129#else
130
131#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
132#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
133
117/* 134/*
118 * Certain architectures need to do special things when pte's 135 * Certain architectures need to do special things when pte's
119 * within a page table are directly modified. Thus, the following 136 * within a page table are directly modified. Thus, the following
@@ -174,75 +191,76 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
174 */ 191 */
175static inline int pte_user(pte_t pte) { BUG(); return 0; } 192static inline int pte_user(pte_t pte) { BUG(); return 0; }
176#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 193#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
177static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } 194static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; }
178static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } 195static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
179static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } 196static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
180static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } 197static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
181static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } 198static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; }
199
182static inline pte_t pte_wrprotect(pte_t pte) 200static inline pte_t pte_wrprotect(pte_t pte)
183{ 201{
184 (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 202 pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
185 (pte).pte_high &= ~_PAGE_SILENT_WRITE; 203 pte.pte_high &= ~_PAGE_SILENT_WRITE;
186 return pte; 204 return pte;
187} 205}
188 206
189static inline pte_t pte_rdprotect(pte_t pte) 207static inline pte_t pte_rdprotect(pte_t pte)
190{ 208{
191 (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); 209 pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
192 (pte).pte_high &= ~_PAGE_SILENT_READ; 210 pte.pte_high &= ~_PAGE_SILENT_READ;
193 return pte; 211 return pte;
194} 212}
195 213
196static inline pte_t pte_mkclean(pte_t pte) 214static inline pte_t pte_mkclean(pte_t pte)
197{ 215{
198 (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); 216 pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
199 (pte).pte_high &= ~_PAGE_SILENT_WRITE; 217 pte.pte_high &= ~_PAGE_SILENT_WRITE;
200 return pte; 218 return pte;
201} 219}
202 220
203static inline pte_t pte_mkold(pte_t pte) 221static inline pte_t pte_mkold(pte_t pte)
204{ 222{
205 (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); 223 pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
206 (pte).pte_high &= ~_PAGE_SILENT_READ; 224 pte.pte_high &= ~_PAGE_SILENT_READ;
207 return pte; 225 return pte;
208} 226}
209 227
210static inline pte_t pte_mkwrite(pte_t pte) 228static inline pte_t pte_mkwrite(pte_t pte)
211{ 229{
212 (pte).pte_low |= _PAGE_WRITE; 230 pte.pte_low |= _PAGE_WRITE;
213 if ((pte).pte_low & _PAGE_MODIFIED) { 231 if (pte.pte_low & _PAGE_MODIFIED) {
214 (pte).pte_low |= _PAGE_SILENT_WRITE; 232 pte.pte_low |= _PAGE_SILENT_WRITE;
215 (pte).pte_high |= _PAGE_SILENT_WRITE; 233 pte.pte_high |= _PAGE_SILENT_WRITE;
216 } 234 }
217 return pte; 235 return pte;
218} 236}
219 237
220static inline pte_t pte_mkread(pte_t pte) 238static inline pte_t pte_mkread(pte_t pte)
221{ 239{
222 (pte).pte_low |= _PAGE_READ; 240 pte.pte_low |= _PAGE_READ;
223 if ((pte).pte_low & _PAGE_ACCESSED) { 241 if (pte.pte_low & _PAGE_ACCESSED) {
224 (pte).pte_low |= _PAGE_SILENT_READ; 242 pte.pte_low |= _PAGE_SILENT_READ;
225 (pte).pte_high |= _PAGE_SILENT_READ; 243 pte.pte_high |= _PAGE_SILENT_READ;
226 } 244 }
227 return pte; 245 return pte;
228} 246}
229 247
230static inline pte_t pte_mkdirty(pte_t pte) 248static inline pte_t pte_mkdirty(pte_t pte)
231{ 249{
232 (pte).pte_low |= _PAGE_MODIFIED; 250 pte.pte_low |= _PAGE_MODIFIED;
233 if ((pte).pte_low & _PAGE_WRITE) { 251 if (pte.pte_low & _PAGE_WRITE) {
234 (pte).pte_low |= _PAGE_SILENT_WRITE; 252 pte.pte_low |= _PAGE_SILENT_WRITE;
235 (pte).pte_high |= _PAGE_SILENT_WRITE; 253 pte.pte_high |= _PAGE_SILENT_WRITE;
236 } 254 }
237 return pte; 255 return pte;
238} 256}
239 257
240static inline pte_t pte_mkyoung(pte_t pte) 258static inline pte_t pte_mkyoung(pte_t pte)
241{ 259{
242 (pte).pte_low |= _PAGE_ACCESSED; 260 pte.pte_low |= _PAGE_ACCESSED;
243 if ((pte).pte_low & _PAGE_READ) 261 if (pte.pte_low & _PAGE_READ)
244 (pte).pte_low |= _PAGE_SILENT_READ; 262 pte.pte_low |= _PAGE_SILENT_READ;
245 (pte).pte_high |= _PAGE_SILENT_READ; 263 pte.pte_high |= _PAGE_SILENT_READ;
246 return pte; 264 return pte;
247} 265}
248#else 266#else
@@ -335,8 +353,9 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
335#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 353#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
336static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 354static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
337{ 355{
338 pte.pte_low &= _PAGE_CHG_MASK; 356 pte.pte_low &= _PAGE_CHG_MASK;
339 pte.pte_low |= pgprot_val(newprot); 357 pte.pte_high &= ~0x3f;
358 pte.pte_low |= pgprot_val(newprot);
340 pte.pte_high |= pgprot_val(newprot) & 0x3f; 359 pte.pte_high |= pgprot_val(newprot) & 0x3f;
341 return pte; 360 return pte;
342} 361}
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index 8edabb0be23f..cefa657dd04a 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -55,8 +55,14 @@ struct sigcontext {
55struct sigcontext { 55struct sigcontext {
56 unsigned long sc_regs[32]; 56 unsigned long sc_regs[32];
57 unsigned long sc_fpregs[32]; 57 unsigned long sc_fpregs[32];
58 unsigned long sc_hi[4]; 58 unsigned long sc_mdhi;
59 unsigned long sc_lo[4]; 59 unsigned long sc_hi1;
60 unsigned long sc_hi2;
61 unsigned long sc_hi3;
62 unsigned long sc_mdlo;
63 unsigned long sc_lo1;
64 unsigned long sc_lo2;
65 unsigned long sc_lo3;
60 unsigned long sc_pc; 66 unsigned long sc_pc;
61 unsigned int sc_fpc_csr; 67 unsigned int sc_fpc_csr;
62 unsigned int sc_used_math; 68 unsigned int sc_used_math;
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 75c6fe7c2126..e14e4b69de21 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -48,7 +48,6 @@ extern struct call_data_struct *call_data;
48#define SMP_CALL_FUNCTION 0x2 48#define SMP_CALL_FUNCTION 0x2
49 49
50extern cpumask_t phys_cpu_present_map; 50extern cpumask_t phys_cpu_present_map;
51extern cpumask_t cpu_online_map;
52#define cpu_possible_map phys_cpu_present_map 51#define cpu_possible_map phys_cpu_present_map
53 52
54extern cpumask_t cpu_callout_map; 53extern cpumask_t cpu_callout_map;
@@ -86,9 +85,9 @@ extern void prom_init_secondary(void);
86extern void plat_smp_setup(void); 85extern void plat_smp_setup(void);
87 86
88/* 87/*
89 * Called after init_IRQ but before __cpu_up. 88 * Called in smp_prepare_cpus.
90 */ 89 */
91extern void prom_prepare_cpus(unsigned int max_cpus); 90extern void plat_prepare_cpus(unsigned int max_cpus);
92 91
93/* 92/*
94 * Last chance for the board code to finish SMP initialization before 93 * Last chance for the board code to finish SMP initialization before
diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h
new file mode 100644
index 000000000000..795ac6c23203
--- /dev/null
+++ b/include/asm-mips/sparsemem.h
@@ -0,0 +1,14 @@
1#ifndef _MIPS_SPARSEMEM_H
2#define _MIPS_SPARSEMEM_H
3#ifdef CONFIG_SPARSEMEM
4
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
8 */
9#define SECTION_SIZE_BITS 28
10#define MAX_PHYSMEM_BITS 35
11
12#endif /* CONFIG_SPARSEMEM */
13#endif /* _MIPS_SPARSEMEM_H */
14
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-02 14:32:49 -0500