diff options
Diffstat (limited to 'include/asm-mips')
100 files changed, 2599 insertions, 1781 deletions
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index ef33c3f13484..1ad60ba186d0 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h | |||
@@ -40,6 +40,7 @@ struct exec | |||
40 | #ifdef CONFIG_64BIT | 40 | #ifdef CONFIG_64BIT |
41 | #define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) | 41 | #define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) |
42 | #endif | 42 | #endif |
43 | #define STACK_TOP_MAX TASK_SIZE | ||
43 | 44 | ||
44 | #endif | 45 | #endif |
45 | 46 | ||
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index c6275088cf65..0b3ff9c48409 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h | |||
@@ -129,28 +129,12 @@ | |||
129 | #define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ | 129 | #define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ |
130 | ((cm)<<59) | (a)) | 130 | ((cm)<<59) | (a)) |
131 | 131 | ||
132 | #if defined (CONFIG_CPU_R4300) \ | 132 | /* |
133 | || defined (CONFIG_CPU_R4X00) \ | 133 | * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting |
134 | || defined (CONFIG_CPU_R5000) \ | 134 | * the region, 3 bits for the CCA mode. This leaves 59 bits of which the |
135 | || defined (CONFIG_CPU_RM7000) \ | 135 | * R8000 implements most with its 48-bit physical address space. |
136 | || defined (CONFIG_CPU_NEVADA) \ | 136 | */ |
137 | || defined (CONFIG_CPU_TX49XX) \ | 137 | #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ |
138 | || defined (CONFIG_CPU_MIPS64) | ||
139 | #define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */ | ||
140 | #endif | ||
141 | |||
142 | #if defined (CONFIG_CPU_R8000) | ||
143 | /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ | ||
144 | #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ | ||
145 | #endif | ||
146 | |||
147 | #if defined (CONFIG_CPU_R10000) | ||
148 | #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ | ||
149 | #endif | ||
150 | |||
151 | #if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) | ||
152 | #define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */ | ||
153 | #endif | ||
154 | 138 | ||
155 | #ifndef CONFIG_CPU_R8000 | 139 | #ifndef CONFIG_CPU_R8000 |
156 | 140 | ||
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 92e62ef711ed..c5f20df780e9 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h | |||
@@ -52,21 +52,6 @@ | |||
52 | .endm | 52 | .endm |
53 | #endif /* CONFIG_MIPS_MT_SMTC */ | 53 | #endif /* CONFIG_MIPS_MT_SMTC */ |
54 | 54 | ||
55 | #ifdef CONFIG_CPU_SB1 | ||
56 | .macro fpu_enable_hazard | ||
57 | .set push | ||
58 | .set noreorder | ||
59 | .set mips2 | ||
60 | SSNOP | ||
61 | bnezl $0, .+4 | ||
62 | SSNOP | ||
63 | .set pop | ||
64 | .endm | ||
65 | #else | ||
66 | .macro fpu_enable_hazard | ||
67 | .endm | ||
68 | #endif | ||
69 | |||
70 | /* | 55 | /* |
71 | * Temporary until all gas have MT ASE support | 56 | * Temporary until all gas have MT ASE support |
72 | */ | 57 | */ |
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 1b60624dab7e..7d8003769a44 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h | |||
@@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) | |||
138 | { | 138 | { |
139 | unsigned long result; | 139 | unsigned long result; |
140 | 140 | ||
141 | smp_mb(); | 141 | smp_llsc_mb(); |
142 | 142 | ||
143 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 143 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
144 | unsigned long temp; | 144 | unsigned long temp; |
@@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) | |||
181 | raw_local_irq_restore(flags); | 181 | raw_local_irq_restore(flags); |
182 | } | 182 | } |
183 | 183 | ||
184 | smp_mb(); | 184 | smp_llsc_mb(); |
185 | 185 | ||
186 | return result; | 186 | return result; |
187 | } | 187 | } |
@@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) | |||
190 | { | 190 | { |
191 | unsigned long result; | 191 | unsigned long result; |
192 | 192 | ||
193 | smp_mb(); | 193 | smp_llsc_mb(); |
194 | 194 | ||
195 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 195 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
196 | unsigned long temp; | 196 | unsigned long temp; |
@@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) | |||
233 | raw_local_irq_restore(flags); | 233 | raw_local_irq_restore(flags); |
234 | } | 234 | } |
235 | 235 | ||
236 | smp_mb(); | 236 | smp_llsc_mb(); |
237 | 237 | ||
238 | return result; | 238 | return result; |
239 | } | 239 | } |
@@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) | |||
250 | { | 250 | { |
251 | unsigned long result; | 251 | unsigned long result; |
252 | 252 | ||
253 | smp_mb(); | 253 | smp_llsc_mb(); |
254 | 254 | ||
255 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 255 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
256 | unsigned long temp; | 256 | unsigned long temp; |
@@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) | |||
302 | raw_local_irq_restore(flags); | 302 | raw_local_irq_restore(flags); |
303 | } | 303 | } |
304 | 304 | ||
305 | smp_mb(); | 305 | smp_llsc_mb(); |
306 | 306 | ||
307 | return result; | 307 | return result; |
308 | } | 308 | } |
@@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) | |||
519 | { | 519 | { |
520 | unsigned long result; | 520 | unsigned long result; |
521 | 521 | ||
522 | smp_mb(); | 522 | smp_llsc_mb(); |
523 | 523 | ||
524 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 524 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
525 | unsigned long temp; | 525 | unsigned long temp; |
@@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) | |||
562 | raw_local_irq_restore(flags); | 562 | raw_local_irq_restore(flags); |
563 | } | 563 | } |
564 | 564 | ||
565 | smp_mb(); | 565 | smp_llsc_mb(); |
566 | 566 | ||
567 | return result; | 567 | return result; |
568 | } | 568 | } |
@@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) | |||
571 | { | 571 | { |
572 | unsigned long result; | 572 | unsigned long result; |
573 | 573 | ||
574 | smp_mb(); | 574 | smp_llsc_mb(); |
575 | 575 | ||
576 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 576 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
577 | unsigned long temp; | 577 | unsigned long temp; |
@@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) | |||
614 | raw_local_irq_restore(flags); | 614 | raw_local_irq_restore(flags); |
615 | } | 615 | } |
616 | 616 | ||
617 | smp_mb(); | 617 | smp_llsc_mb(); |
618 | 618 | ||
619 | return result; | 619 | return result; |
620 | } | 620 | } |
@@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) | |||
631 | { | 631 | { |
632 | unsigned long result; | 632 | unsigned long result; |
633 | 633 | ||
634 | smp_mb(); | 634 | smp_llsc_mb(); |
635 | 635 | ||
636 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 636 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
637 | unsigned long temp; | 637 | unsigned long temp; |
@@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) | |||
683 | raw_local_irq_restore(flags); | 683 | raw_local_irq_restore(flags); |
684 | } | 684 | } |
685 | 685 | ||
686 | smp_mb(); | 686 | smp_llsc_mb(); |
687 | 687 | ||
688 | return result; | 688 | return result; |
689 | } | 689 | } |
@@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) | |||
791 | * atomic*_return operations are serializing but not the non-*_return | 791 | * atomic*_return operations are serializing but not the non-*_return |
792 | * versions. | 792 | * versions. |
793 | */ | 793 | */ |
794 | #define smp_mb__before_atomic_dec() smp_mb() | 794 | #define smp_mb__before_atomic_dec() smp_llsc_mb() |
795 | #define smp_mb__after_atomic_dec() smp_mb() | 795 | #define smp_mb__after_atomic_dec() smp_llsc_mb() |
796 | #define smp_mb__before_atomic_inc() smp_mb() | 796 | #define smp_mb__before_atomic_inc() smp_llsc_mb() |
797 | #define smp_mb__after_atomic_inc() smp_mb() | 797 | #define smp_mb__after_atomic_inc() smp_llsc_mb() |
798 | 798 | ||
799 | #include <asm-generic/atomic.h> | 799 | #include <asm-generic/atomic.h> |
800 | |||
800 | #endif /* _ASM_ATOMIC_H */ | 801 | #endif /* _ASM_ATOMIC_H */ |
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index ed82631b0017..9d8cfbb5e796 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h | |||
@@ -121,6 +121,11 @@ | |||
121 | #else | 121 | #else |
122 | #define __WEAK_ORDERING_MB " \n" | 122 | #define __WEAK_ORDERING_MB " \n" |
123 | #endif | 123 | #endif |
124 | #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) | ||
125 | #define __WEAK_LLSC_MB " sync \n" | ||
126 | #else | ||
127 | #define __WEAK_LLSC_MB " \n" | ||
128 | #endif | ||
124 | 129 | ||
125 | #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") | 130 | #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") |
126 | #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") | 131 | #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") |
@@ -129,4 +134,8 @@ | |||
129 | #define set_mb(var, value) \ | 134 | #define set_mb(var, value) \ |
130 | do { var = value; smp_mb(); } while (0) | 135 | do { var = value; smp_mb(); } while (0) |
131 | 136 | ||
137 | #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") | ||
138 | #define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") | ||
139 | #define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") | ||
140 | |||
132 | #endif /* __ASM_BARRIER_H */ | 141 | #endif /* __ASM_BARRIER_H */ |
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d995413e11fd..148bc79557f1 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h | |||
@@ -38,8 +38,8 @@ | |||
38 | /* | 38 | /* |
39 | * clear_bit() doesn't provide any barrier for the compiler. | 39 | * clear_bit() doesn't provide any barrier for the compiler. |
40 | */ | 40 | */ |
41 | #define smp_mb__before_clear_bit() smp_mb() | 41 | #define smp_mb__before_clear_bit() smp_llsc_mb() |
42 | #define smp_mb__after_clear_bit() smp_mb() | 42 | #define smp_mb__after_clear_bit() smp_llsc_mb() |
43 | 43 | ||
44 | /* | 44 | /* |
45 | * set_bit - Atomically set a bit in memory | 45 | * set_bit - Atomically set a bit in memory |
@@ -238,10 +238,11 @@ static inline int test_and_set_bit(unsigned long nr, | |||
238 | volatile unsigned long *addr) | 238 | volatile unsigned long *addr) |
239 | { | 239 | { |
240 | unsigned short bit = nr & SZLONG_MASK; | 240 | unsigned short bit = nr & SZLONG_MASK; |
241 | unsigned long res; | ||
241 | 242 | ||
242 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 243 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
243 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 244 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
244 | unsigned long temp, res; | 245 | unsigned long temp; |
245 | 246 | ||
246 | __asm__ __volatile__( | 247 | __asm__ __volatile__( |
247 | " .set mips3 \n" | 248 | " .set mips3 \n" |
@@ -254,11 +255,9 @@ static inline int test_and_set_bit(unsigned long nr, | |||
254 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 255 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
255 | : "r" (1UL << bit), "m" (*m) | 256 | : "r" (1UL << bit), "m" (*m) |
256 | : "memory"); | 257 | : "memory"); |
257 | |||
258 | return res != 0; | ||
259 | } else if (cpu_has_llsc) { | 258 | } else if (cpu_has_llsc) { |
260 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 259 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
261 | unsigned long temp, res; | 260 | unsigned long temp; |
262 | 261 | ||
263 | __asm__ __volatile__( | 262 | __asm__ __volatile__( |
264 | " .set push \n" | 263 | " .set push \n" |
@@ -277,25 +276,22 @@ static inline int test_and_set_bit(unsigned long nr, | |||
277 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 276 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
278 | : "r" (1UL << bit), "m" (*m) | 277 | : "r" (1UL << bit), "m" (*m) |
279 | : "memory"); | 278 | : "memory"); |
280 | |||
281 | return res != 0; | ||
282 | } else { | 279 | } else { |
283 | volatile unsigned long *a = addr; | 280 | volatile unsigned long *a = addr; |
284 | unsigned long mask; | 281 | unsigned long mask; |
285 | int retval; | ||
286 | unsigned long flags; | 282 | unsigned long flags; |
287 | 283 | ||
288 | a += nr >> SZLONG_LOG; | 284 | a += nr >> SZLONG_LOG; |
289 | mask = 1UL << bit; | 285 | mask = 1UL << bit; |
290 | raw_local_irq_save(flags); | 286 | raw_local_irq_save(flags); |
291 | retval = (mask & *a) != 0; | 287 | res = (mask & *a); |
292 | *a |= mask; | 288 | *a |= mask; |
293 | raw_local_irq_restore(flags); | 289 | raw_local_irq_restore(flags); |
294 | |||
295 | return retval; | ||
296 | } | 290 | } |
297 | 291 | ||
298 | smp_mb(); | 292 | smp_llsc_mb(); |
293 | |||
294 | return res != 0; | ||
299 | } | 295 | } |
300 | 296 | ||
301 | /* | 297 | /* |
@@ -310,10 +306,11 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
310 | volatile unsigned long *addr) | 306 | volatile unsigned long *addr) |
311 | { | 307 | { |
312 | unsigned short bit = nr & SZLONG_MASK; | 308 | unsigned short bit = nr & SZLONG_MASK; |
309 | unsigned long res; | ||
313 | 310 | ||
314 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 311 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
315 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 312 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
316 | unsigned long temp, res; | 313 | unsigned long temp; |
317 | 314 | ||
318 | __asm__ __volatile__( | 315 | __asm__ __volatile__( |
319 | " .set mips3 \n" | 316 | " .set mips3 \n" |
@@ -327,12 +324,10 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
327 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 324 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
328 | : "r" (1UL << bit), "m" (*m) | 325 | : "r" (1UL << bit), "m" (*m) |
329 | : "memory"); | 326 | : "memory"); |
330 | |||
331 | return res != 0; | ||
332 | #ifdef CONFIG_CPU_MIPSR2 | 327 | #ifdef CONFIG_CPU_MIPSR2 |
333 | } else if (__builtin_constant_p(nr)) { | 328 | } else if (__builtin_constant_p(nr)) { |
334 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 329 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
335 | unsigned long temp, res; | 330 | unsigned long temp; |
336 | 331 | ||
337 | __asm__ __volatile__( | 332 | __asm__ __volatile__( |
338 | "1: " __LL "%0, %1 # test_and_clear_bit \n" | 333 | "1: " __LL "%0, %1 # test_and_clear_bit \n" |
@@ -346,12 +341,10 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
346 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 341 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
347 | : "ri" (bit), "m" (*m) | 342 | : "ri" (bit), "m" (*m) |
348 | : "memory"); | 343 | : "memory"); |
349 | |||
350 | return res; | ||
351 | #endif | 344 | #endif |
352 | } else if (cpu_has_llsc) { | 345 | } else if (cpu_has_llsc) { |
353 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 346 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
354 | unsigned long temp, res; | 347 | unsigned long temp; |
355 | 348 | ||
356 | __asm__ __volatile__( | 349 | __asm__ __volatile__( |
357 | " .set push \n" | 350 | " .set push \n" |
@@ -371,25 +364,22 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
371 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 364 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
372 | : "r" (1UL << bit), "m" (*m) | 365 | : "r" (1UL << bit), "m" (*m) |
373 | : "memory"); | 366 | : "memory"); |
374 | |||
375 | return res != 0; | ||
376 | } else { | 367 | } else { |
377 | volatile unsigned long *a = addr; | 368 | volatile unsigned long *a = addr; |
378 | unsigned long mask; | 369 | unsigned long mask; |
379 | int retval; | ||
380 | unsigned long flags; | 370 | unsigned long flags; |
381 | 371 | ||
382 | a += nr >> SZLONG_LOG; | 372 | a += nr >> SZLONG_LOG; |
383 | mask = 1UL << bit; | 373 | mask = 1UL << bit; |
384 | raw_local_irq_save(flags); | 374 | raw_local_irq_save(flags); |
385 | retval = (mask & *a) != 0; | 375 | res = (mask & *a); |
386 | *a &= ~mask; | 376 | *a &= ~mask; |
387 | raw_local_irq_restore(flags); | 377 | raw_local_irq_restore(flags); |
388 | |||
389 | return retval; | ||
390 | } | 378 | } |
391 | 379 | ||
392 | smp_mb(); | 380 | smp_llsc_mb(); |
381 | |||
382 | return res != 0; | ||
393 | } | 383 | } |
394 | 384 | ||
395 | /* | 385 | /* |
@@ -404,10 +394,11 @@ static inline int test_and_change_bit(unsigned long nr, | |||
404 | volatile unsigned long *addr) | 394 | volatile unsigned long *addr) |
405 | { | 395 | { |
406 | unsigned short bit = nr & SZLONG_MASK; | 396 | unsigned short bit = nr & SZLONG_MASK; |
397 | unsigned long res; | ||
407 | 398 | ||
408 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 399 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
409 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 400 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
410 | unsigned long temp, res; | 401 | unsigned long temp; |
411 | 402 | ||
412 | __asm__ __volatile__( | 403 | __asm__ __volatile__( |
413 | " .set mips3 \n" | 404 | " .set mips3 \n" |
@@ -420,11 +411,9 @@ static inline int test_and_change_bit(unsigned long nr, | |||
420 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 411 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
421 | : "r" (1UL << bit), "m" (*m) | 412 | : "r" (1UL << bit), "m" (*m) |
422 | : "memory"); | 413 | : "memory"); |
423 | |||
424 | return res != 0; | ||
425 | } else if (cpu_has_llsc) { | 414 | } else if (cpu_has_llsc) { |
426 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 415 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
427 | unsigned long temp, res; | 416 | unsigned long temp; |
428 | 417 | ||
429 | __asm__ __volatile__( | 418 | __asm__ __volatile__( |
430 | " .set push \n" | 419 | " .set push \n" |
@@ -443,24 +432,22 @@ static inline int test_and_change_bit(unsigned long nr, | |||
443 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 432 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
444 | : "r" (1UL << bit), "m" (*m) | 433 | : "r" (1UL << bit), "m" (*m) |
445 | : "memory"); | 434 | : "memory"); |
446 | |||
447 | return res != 0; | ||
448 | } else { | 435 | } else { |
449 | volatile unsigned long *a = addr; | 436 | volatile unsigned long *a = addr; |
450 | unsigned long mask, retval; | 437 | unsigned long mask; |
451 | unsigned long flags; | 438 | unsigned long flags; |
452 | 439 | ||
453 | a += nr >> SZLONG_LOG; | 440 | a += nr >> SZLONG_LOG; |
454 | mask = 1UL << bit; | 441 | mask = 1UL << bit; |
455 | raw_local_irq_save(flags); | 442 | raw_local_irq_save(flags); |
456 | retval = (mask & *a) != 0; | 443 | res = (mask & *a); |
457 | *a ^= mask; | 444 | *a ^= mask; |
458 | raw_local_irq_restore(flags); | 445 | raw_local_irq_restore(flags); |
459 | |||
460 | return retval; | ||
461 | } | 446 | } |
462 | 447 | ||
463 | smp_mb(); | 448 | smp_llsc_mb(); |
449 | |||
450 | return res != 0; | ||
464 | } | 451 | } |
465 | 452 | ||
466 | #include <asm-generic/bitops/non-atomic.h> | 453 | #include <asm-generic/bitops/non-atomic.h> |
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index b0c329783ac5..087126a5faf9 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
@@ -109,18 +109,12 @@ | |||
109 | #define MACH_COSINE_ORION 0 | 109 | #define MACH_COSINE_ORION 0 |
110 | 110 | ||
111 | /* | 111 | /* |
112 | * Valid machtype for group GALILEO | ||
113 | */ | ||
114 | #define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ | ||
115 | #define MACH_EV64120A 0 /* EV64120A */ | ||
116 | |||
117 | /* | ||
118 | * Valid machtype for group MOMENCO | 112 | * Valid machtype for group MOMENCO |
119 | */ | 113 | */ |
120 | #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ | 114 | #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ |
121 | #define MACH_MOMENCO_OCELOT 0 | 115 | #define MACH_MOMENCO_OCELOT 0 |
122 | #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ | 116 | #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ |
123 | #define MACH_MOMENCO_OCELOT_C 2 | 117 | #define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ |
124 | #define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */ | 118 | #define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */ |
125 | #define MACH_MOMENCO_OCELOT_3 4 | 119 | #define MACH_MOMENCO_OCELOT_3 4 |
126 | 120 | ||
@@ -194,13 +188,6 @@ | |||
194 | #define MACH_HP_LASERJET 1 | 188 | #define MACH_HP_LASERJET 1 |
195 | 189 | ||
196 | /* | 190 | /* |
197 | * Valid machtype for group LASAT | ||
198 | */ | ||
199 | #define MACH_GROUP_LASAT 21 | ||
200 | #define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ | ||
201 | #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ | ||
202 | |||
203 | /* | ||
204 | * Valid machtype for group TITAN | 191 | * Valid machtype for group TITAN |
205 | */ | 192 | */ |
206 | #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ | 193 | #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ |
@@ -213,6 +200,27 @@ | |||
213 | #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ | 200 | #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ |
214 | #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ | 201 | #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ |
215 | 202 | ||
203 | /* | ||
204 | * Valid machtype for group LEMOTE | ||
205 | */ | ||
206 | #define MACH_GROUP_LEMOTE 27 | ||
207 | #define MACH_LEMOTE_FULONG 0 | ||
208 | |||
209 | /* | ||
210 | * Valid machtype for group PMC-MSP | ||
211 | */ | ||
212 | #define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ | ||
213 | #define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ | ||
214 | #define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ | ||
215 | #define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ | ||
216 | #define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ | ||
217 | #define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ | ||
218 | #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ | ||
219 | #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ | ||
220 | |||
221 | #define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ | ||
222 | #define MACH_WRPPMC 1 | ||
223 | |||
216 | #define CL_SIZE COMMAND_LINE_SIZE | 224 | #define CL_SIZE COMMAND_LINE_SIZE |
217 | 225 | ||
218 | const char *get_system_type(void); | 226 | const char *get_system_type(void); |
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index c4a1ec31ff6a..df7f2deb3b56 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h | |||
@@ -20,7 +20,11 @@ | |||
20 | #define Index_Load_Tag_D 0x05 | 20 | #define Index_Load_Tag_D 0x05 |
21 | #define Index_Store_Tag_I 0x08 | 21 | #define Index_Store_Tag_I 0x08 |
22 | #define Index_Store_Tag_D 0x09 | 22 | #define Index_Store_Tag_D 0x09 |
23 | #if defined(CONFIG_CPU_LOONGSON2) | ||
24 | #define Hit_Invalidate_I 0x00 | ||
25 | #else | ||
23 | #define Hit_Invalidate_I 0x10 | 26 | #define Hit_Invalidate_I 0x10 |
27 | #endif | ||
24 | #define Hit_Invalidate_D 0x11 | 28 | #define Hit_Invalidate_D 0x11 |
25 | #define Hit_Writeback_Inv_D 0x15 | 29 | #define Hit_Writeback_Inv_D 0x15 |
26 | 30 | ||
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h index 6599a901b63e..368a99e5c3e1 100644 --- a/include/asm-mips/compat-signal.h +++ b/include/asm-mips/compat-signal.h | |||
@@ -10,6 +10,68 @@ | |||
10 | 10 | ||
11 | #include <asm/uaccess.h> | 11 | #include <asm/uaccess.h> |
12 | 12 | ||
13 | #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) | ||
14 | |||
15 | typedef struct compat_siginfo { | ||
16 | int si_signo; | ||
17 | int si_code; | ||
18 | int si_errno; | ||
19 | |||
20 | union { | ||
21 | int _pad[SI_PAD_SIZE32]; | ||
22 | |||
23 | /* kill() */ | ||
24 | struct { | ||
25 | compat_pid_t _pid; /* sender's pid */ | ||
26 | compat_uid_t _uid; /* sender's uid */ | ||
27 | } _kill; | ||
28 | |||
29 | /* SIGCHLD */ | ||
30 | struct { | ||
31 | compat_pid_t _pid; /* which child */ | ||
32 | compat_uid_t _uid; /* sender's uid */ | ||
33 | int _status; /* exit code */ | ||
34 | compat_clock_t _utime; | ||
35 | compat_clock_t _stime; | ||
36 | } _sigchld; | ||
37 | |||
38 | /* IRIX SIGCHLD */ | ||
39 | struct { | ||
40 | compat_pid_t _pid; /* which child */ | ||
41 | compat_clock_t _utime; | ||
42 | int _status; /* exit code */ | ||
43 | compat_clock_t _stime; | ||
44 | } _irix_sigchld; | ||
45 | |||
46 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | ||
47 | struct { | ||
48 | s32 _addr; /* faulting insn/memory ref. */ | ||
49 | } _sigfault; | ||
50 | |||
51 | /* SIGPOLL, SIGXFSZ (To do ...) */ | ||
52 | struct { | ||
53 | int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ | ||
54 | int _fd; | ||
55 | } _sigpoll; | ||
56 | |||
57 | /* POSIX.1b timers */ | ||
58 | struct { | ||
59 | timer_t _tid; /* timer id */ | ||
60 | int _overrun; /* overrun count */ | ||
61 | compat_sigval_t _sigval;/* same as below */ | ||
62 | int _sys_private; /* not to be passed to user */ | ||
63 | } _timer; | ||
64 | |||
65 | /* POSIX.1b signals */ | ||
66 | struct { | ||
67 | compat_pid_t _pid; /* sender's pid */ | ||
68 | compat_uid_t _uid; /* sender's uid */ | ||
69 | compat_sigval_t _sigval; | ||
70 | } _rt; | ||
71 | |||
72 | } _sifields; | ||
73 | } compat_siginfo_t; | ||
74 | |||
13 | static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, | 75 | static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, |
14 | const sigset_t *s) | 76 | const sigset_t *s) |
15 | { | 77 | { |
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 432653d7ae09..568c76cdd900 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h | |||
@@ -37,8 +37,10 @@ typedef s32 compat_key_t; | |||
37 | 37 | ||
38 | typedef s32 compat_int_t; | 38 | typedef s32 compat_int_t; |
39 | typedef s32 compat_long_t; | 39 | typedef s32 compat_long_t; |
40 | typedef s64 compat_s64; | ||
40 | typedef u32 compat_uint_t; | 41 | typedef u32 compat_uint_t; |
41 | typedef u32 compat_ulong_t; | 42 | typedef u32 compat_ulong_t; |
43 | typedef u64 compat_u64; | ||
42 | 44 | ||
43 | struct compat_timespec { | 45 | struct compat_timespec { |
44 | compat_time_t tv_sec; | 46 | compat_time_t tv_sec; |
@@ -132,7 +134,8 @@ typedef u32 compat_uptr_t; | |||
132 | 134 | ||
133 | static inline void __user *compat_ptr(compat_uptr_t uptr) | 135 | static inline void __user *compat_ptr(compat_uptr_t uptr) |
134 | { | 136 | { |
135 | return (void __user *)(long)uptr; | 137 | /* cast to a __user pointer via "unsigned long" makes sparse happy */ |
138 | return (void __user *)(unsigned long)(long)uptr; | ||
136 | } | 139 | } |
137 | 140 | ||
138 | static inline compat_uptr_t ptr_to_compat(void __user *uptr) | 141 | static inline compat_uptr_t ptr_to_compat(void __user *uptr) |
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 5e4bed123b48..d95a83e3e1d7 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h | |||
@@ -150,6 +150,10 @@ | |||
150 | #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) | 150 | #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) |
151 | #endif | 151 | #endif |
152 | 152 | ||
153 | #ifndef cpu_has_userlocal | ||
154 | #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) | ||
155 | #endif | ||
156 | |||
153 | #ifdef CONFIG_32BIT | 157 | #ifdef CONFIG_32BIT |
154 | # ifndef cpu_has_nofpuex | 158 | # ifndef cpu_has_nofpuex |
155 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) | 159 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) |
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b2..3857358fb6de 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h | |||
@@ -89,6 +89,8 @@ | |||
89 | #define PRID_IMP_34K 0x9500 | 89 | #define PRID_IMP_34K 0x9500 |
90 | #define PRID_IMP_24KE 0x9600 | 90 | #define PRID_IMP_24KE 0x9600 |
91 | #define PRID_IMP_74K 0x9700 | 91 | #define PRID_IMP_74K 0x9700 |
92 | #define PRID_IMP_LOONGSON1 0x4200 | ||
93 | #define PRID_IMP_LOONGSON2 0x6300 | ||
92 | 94 | ||
93 | /* | 95 | /* |
94 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE | 96 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE |
@@ -107,6 +109,7 @@ | |||
107 | * Definitions for 7:0 on legacy processors | 109 | * Definitions for 7:0 on legacy processors |
108 | */ | 110 | */ |
109 | 111 | ||
112 | #define PRID_REV_MASK 0x00ff | ||
110 | 113 | ||
111 | #define PRID_REV_TX4927 0x0022 | 114 | #define PRID_REV_TX4927 0x0022 |
112 | #define PRID_REV_TX4937 0x0030 | 115 | #define PRID_REV_TX4937 0x0030 |
@@ -123,6 +126,18 @@ | |||
123 | #define PRID_REV_VR4122 0x0070 | 126 | #define PRID_REV_VR4122 0x0070 |
124 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ | 127 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ |
125 | #define PRID_REV_VR4130 0x0080 | 128 | #define PRID_REV_VR4130 0x0080 |
129 | #define PRID_REV_34K_V1_0_2 0x0022 | ||
130 | |||
131 | /* | ||
132 | * Older processors used to encode processor version and revision in two | ||
133 | * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores | ||
134 | * have switched to use the 8-bits as 3:3:2 bitfield with the last field as | ||
135 | * the patch number. *ARGH* | ||
136 | */ | ||
137 | #define PRID_REV_ENCODE_44(ver, rev) \ | ||
138 | ((ver) << 4 | (rev)) | ||
139 | #define PRID_REV_ENCODE_332(ver, rev, patch) \ | ||
140 | ((ver) << 5 | (rev) << 2 | (patch)) | ||
126 | 141 | ||
127 | /* | 142 | /* |
128 | * FPU implementation/revision register (CP1 control register 0). | 143 | * FPU implementation/revision register (CP1 control register 0). |
@@ -200,7 +215,10 @@ | |||
200 | #define CPU_SB1A 62 | 215 | #define CPU_SB1A 62 |
201 | #define CPU_74K 63 | 216 | #define CPU_74K 63 |
202 | #define CPU_R14000 64 | 217 | #define CPU_R14000 64 |
203 | #define CPU_LAST 64 | 218 | #define CPU_LOONGSON1 65 |
219 | #define CPU_LOONGSON2 66 | ||
220 | |||
221 | #define CPU_LAST 66 | ||
204 | 222 | ||
205 | /* | 223 | /* |
206 | * ISA Level encodings | 224 | * ISA Level encodings |
@@ -246,6 +264,7 @@ | |||
246 | #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ | 264 | #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ |
247 | #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ | 265 | #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ |
248 | #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ | 266 | #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ |
267 | #define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ | ||
249 | 268 | ||
250 | /* | 269 | /* |
251 | * CPU ASE encodings | 270 | * CPU ASE encodings |
diff --git a/include/asm-mips/dec/serial.h b/include/asm-mips/dec/serial.h deleted file mode 100644 index acad75890a05..000000000000 --- a/include/asm-mips/dec/serial.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-mips/dec/serial.h | ||
3 | * | ||
4 | * Definitions common to all DECstation serial devices. | ||
5 | * | ||
6 | * Copyright (C) 2004 Maciej W. Rozycki | ||
7 | * | ||
8 | * Based on bits extracted from drivers/tc/zs.h for which | ||
9 | * the following copyrights apply: | ||
10 | * | ||
11 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
12 | * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) | ||
13 | * Copyright (C) Harald Koerfgen | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version | ||
18 | * 2 of the License, or (at your option) any later version. | ||
19 | */ | ||
20 | #ifndef __ASM_MIPS_DEC_SERIAL_H | ||
21 | #define __ASM_MIPS_DEC_SERIAL_H | ||
22 | |||
23 | struct dec_serial_hook { | ||
24 | int (*init_channel)(void *handle); | ||
25 | void (*init_info)(void *handle); | ||
26 | void (*rx_char)(unsigned char ch, unsigned char fl); | ||
27 | int (*poll_rx_char)(void *handle); | ||
28 | int (*poll_tx_char)(void *handle, unsigned char ch); | ||
29 | unsigned int cflags; | ||
30 | }; | ||
31 | |||
32 | extern int register_dec_serial_hook(unsigned int channel, | ||
33 | struct dec_serial_hook *hook); | ||
34 | extern int unregister_dec_serial_hook(unsigned int channel); | ||
35 | |||
36 | #endif /* __ASM_MIPS_DEC_SERIAL_H */ | ||
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h index 66189f5f6399..716371bd0980 100644 --- a/include/asm-mips/div64.h +++ b/include/asm-mips/div64.h | |||
@@ -20,7 +20,7 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #define do_div64_32(res, high, low, base) ({ \ | 22 | #define do_div64_32(res, high, low, base) ({ \ |
23 | unsigned long __quot, __mod; \ | 23 | unsigned long __quot32, __mod32; \ |
24 | unsigned long __cf, __tmp, __tmp2, __i; \ | 24 | unsigned long __cf, __tmp, __tmp2, __i; \ |
25 | \ | 25 | \ |
26 | __asm__(".set push\n\t" \ | 26 | __asm__(".set push\n\t" \ |
@@ -48,12 +48,13 @@ | |||
48 | "bnez %4, 0b\n\t" \ | 48 | "bnez %4, 0b\n\t" \ |
49 | " srl %5, %1, 0x1f\n\t" \ | 49 | " srl %5, %1, 0x1f\n\t" \ |
50 | ".set pop" \ | 50 | ".set pop" \ |
51 | : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ | 51 | : "=&r" (__mod32), "=&r" (__tmp), \ |
52 | "=&r" (__quot32), "=&r" (__cf), \ | ||
52 | "=&r" (__i), "=&r" (__tmp2) \ | 53 | "=&r" (__i), "=&r" (__tmp2) \ |
53 | : "Jr" (base), "0" (high), "1" (low)); \ | 54 | : "Jr" (base), "0" (high), "1" (low)); \ |
54 | \ | 55 | \ |
55 | (res) = __quot; \ | 56 | (res) = __quot32; \ |
56 | __mod; }) | 57 | __mod32; }) |
57 | 58 | ||
58 | #define do_div(n, base) ({ \ | 59 | #define do_div(n, base) ({ \ |
59 | unsigned long long __quot; \ | 60 | unsigned long long __quot; \ |
diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h deleted file mode 100644 index 1ff8b73f7a6a..000000000000 --- a/include/asm-mips/ds1216.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | #ifndef _DS1216_H | ||
2 | #define _DS1216_H | ||
3 | |||
4 | extern volatile unsigned char *ds1216_base; | ||
5 | unsigned long ds1216_get_cmos_time(void); | ||
6 | int ds1216_set_rtc_mmss(unsigned long nowtime); | ||
7 | |||
8 | #define DS1216_SEC_BYTE 1 | ||
9 | #define DS1216_MIN_BYTE 2 | ||
10 | #define DS1216_HOUR_BYTE 3 | ||
11 | #define DS1216_HOUR_MASK (0x1f) | ||
12 | #define DS1216_AMPM_MASK (1<<5) | ||
13 | #define DS1216_1224_MASK (1<<7) | ||
14 | #define DS1216_DAY_BYTE 4 | ||
15 | #define DS1216_DAY_MASK (0x7) | ||
16 | #define DS1216_DATE_BYTE 5 | ||
17 | #define DS1216_DATE_MASK (0x3f) | ||
18 | #define DS1216_MONTH_BYTE 6 | ||
19 | #define DS1216_MONTH_MASK (0x1f) | ||
20 | #define DS1216_YEAR_BYTE 7 | ||
21 | |||
22 | #define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE]) | ||
23 | #define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE]) | ||
24 | #define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK) | ||
25 | #define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK) | ||
26 | #define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK) | ||
27 | #define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK) | ||
28 | #define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK) | ||
29 | #define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE]) | ||
30 | |||
31 | #endif | ||
diff --git a/include/asm-mips/fb.h b/include/asm-mips/fb.h new file mode 100644 index 000000000000..bd3f68c9ddfc --- /dev/null +++ b/include/asm-mips/fb.h | |||
@@ -0,0 +1,19 @@ | |||
1 | #ifndef _ASM_FB_H_ | ||
2 | #define _ASM_FB_H_ | ||
3 | |||
4 | #include <linux/fb.h> | ||
5 | #include <linux/fs.h> | ||
6 | #include <asm/page.h> | ||
7 | |||
8 | static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, | ||
9 | unsigned long off) | ||
10 | { | ||
11 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | ||
12 | } | ||
13 | |||
14 | static inline int fb_is_primary_device(struct fb_info *info) | ||
15 | { | ||
16 | return 0; | ||
17 | } | ||
18 | |||
19 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index 47e5679c2353..b623882bce19 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h | |||
@@ -29,7 +29,7 @@ | |||
29 | " .set mips3 \n" \ | 29 | " .set mips3 \n" \ |
30 | "2: sc $1, %2 \n" \ | 30 | "2: sc $1, %2 \n" \ |
31 | " beqzl $1, 1b \n" \ | 31 | " beqzl $1, 1b \n" \ |
32 | __WEAK_ORDERING_MB \ | 32 | __WEAK_LLSC_MB \ |
33 | "3: \n" \ | 33 | "3: \n" \ |
34 | " .set pop \n" \ | 34 | " .set pop \n" \ |
35 | " .set mips0 \n" \ | 35 | " .set mips0 \n" \ |
@@ -55,7 +55,7 @@ | |||
55 | " .set mips3 \n" \ | 55 | " .set mips3 \n" \ |
56 | "2: sc $1, %2 \n" \ | 56 | "2: sc $1, %2 \n" \ |
57 | " beqz $1, 1b \n" \ | 57 | " beqz $1, 1b \n" \ |
58 | __WEAK_ORDERING_MB \ | 58 | __WEAK_LLSC_MB \ |
59 | "3: \n" \ | 59 | "3: \n" \ |
60 | " .set pop \n" \ | 60 | " .set pop \n" \ |
61 | " .set mips0 \n" \ | 61 | " .set mips0 \n" \ |
@@ -152,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) | |||
152 | " .set mips3 \n" | 152 | " .set mips3 \n" |
153 | "2: sc $1, %1 \n" | 153 | "2: sc $1, %1 \n" |
154 | " beqzl $1, 1b \n" | 154 | " beqzl $1, 1b \n" |
155 | __WEAK_ORDERING_MB | 155 | __WEAK_LLSC_MB |
156 | "3: \n" | 156 | "3: \n" |
157 | " .set pop \n" | 157 | " .set pop \n" |
158 | " .section .fixup,\"ax\" \n" | 158 | " .section .fixup,\"ax\" \n" |
@@ -179,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) | |||
179 | " .set mips3 \n" | 179 | " .set mips3 \n" |
180 | "2: sc $1, %1 \n" | 180 | "2: sc $1, %1 \n" |
181 | " beqz $1, 1b \n" | 181 | " beqz $1, 1b \n" |
182 | __WEAK_ORDERING_MB | 182 | __WEAK_LLSC_MB |
183 | "3: \n" | 183 | "3: \n" |
184 | " .set pop \n" | 184 | " .set pop \n" |
185 | " .section .fixup,\"ax\" \n" | 185 | " .section .fixup,\"ax\" \n" |
diff --git a/include/asm-mips/gfx.h b/include/asm-mips/gfx.h deleted file mode 100644 index 37235e41a6fd..000000000000 --- a/include/asm-mips/gfx.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * This is the user-visible SGI GFX interface. | ||
7 | * | ||
8 | * This must be used verbatim into the GNU libc. It does not include | ||
9 | * any kernel-only bits on it. | ||
10 | * | ||
11 | * miguel@nuclecu.unam.mx | ||
12 | */ | ||
13 | #ifndef _ASM_GFX_H | ||
14 | #define _ASM_GFX_H | ||
15 | |||
16 | /* The iocls, yes, they do not make sense, but such is life */ | ||
17 | #define GFX_BASE 100 | ||
18 | #define GFX_GETNUM_BOARDS (GFX_BASE + 1) | ||
19 | #define GFX_GETBOARD_INFO (GFX_BASE + 2) | ||
20 | #define GFX_ATTACH_BOARD (GFX_BASE + 3) | ||
21 | #define GFX_DETACH_BOARD (GFX_BASE + 4) | ||
22 | #define GFX_IS_MANAGED (GFX_BASE + 5) | ||
23 | |||
24 | #define GFX_MAPALL (GFX_BASE + 10) | ||
25 | #define GFX_LABEL (GFX_BASE + 11) | ||
26 | |||
27 | #define GFX_INFO_NAME_SIZE 16 | ||
28 | #define GFX_INFO_LABEL_SIZE 16 | ||
29 | |||
30 | struct gfx_info { | ||
31 | char name [GFX_INFO_NAME_SIZE]; /* board name */ | ||
32 | char label [GFX_INFO_LABEL_SIZE]; /* label name */ | ||
33 | unsigned short int xpmax, ypmax; /* screen resolution */ | ||
34 | unsigned int lenght; /* size of a complete gfx_info for this board */ | ||
35 | }; | ||
36 | |||
37 | struct gfx_getboardinfo_args { | ||
38 | unsigned int board; /* board number. starting from zero */ | ||
39 | void *buf; /* pointer to gfx_info */ | ||
40 | unsigned int len; /* buffer size of buf */ | ||
41 | }; | ||
42 | |||
43 | struct gfx_attach_board_args { | ||
44 | unsigned int board; /* board number, starting from zero */ | ||
45 | void *vaddr; /* address where the board registers should be mapped */ | ||
46 | }; | ||
47 | |||
48 | #ifdef __KERNEL__ | ||
49 | /* umap.c */ | ||
50 | extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long); | ||
51 | extern void *vmalloc_uncached (unsigned long size); | ||
52 | extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr); | ||
53 | #endif | ||
54 | |||
55 | #endif /* _ASM_GFX_H */ | ||
diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h new file mode 100644 index 000000000000..06e46faf862d --- /dev/null +++ b/include/asm-mips/gpio.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __ASM_MIPS_GPIO_H | ||
2 | #define __ASM_MIPS_GPIO_H | ||
3 | |||
4 | #include <gpio.h> | ||
5 | |||
6 | #endif /* __ASM_MIPS_GPIO_H */ | ||
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 92ec2618560c..7ba92890ea13 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h | |||
@@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr); | |||
178 | static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, | 178 | static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, |
179 | unsigned long flags) | 179 | unsigned long flags) |
180 | { | 180 | { |
181 | void __iomem *addr = plat_ioremap(offset, size, flags); | ||
182 | |||
183 | if (addr) | ||
184 | return addr; | ||
185 | |||
181 | #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) | 186 | #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) |
182 | 187 | ||
183 | if (cpu_has_64bit_addresses) { | 188 | if (cpu_has_64bit_addresses) { |
@@ -207,7 +212,8 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, | |||
207 | */ | 212 | */ |
208 | if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && | 213 | if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && |
209 | flags == _CACHE_UNCACHED) | 214 | flags == _CACHE_UNCACHED) |
210 | return (void __iomem *)CKSEG1ADDR(phys_addr); | 215 | return (void __iomem *) |
216 | (unsigned long)CKSEG1ADDR(phys_addr); | ||
211 | } | 217 | } |
212 | 218 | ||
213 | return __ioremap(offset, size, flags); | 219 | return __ioremap(offset, size, flags); |
@@ -282,6 +288,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, | |||
282 | 288 | ||
283 | static inline void iounmap(const volatile void __iomem *addr) | 289 | static inline void iounmap(const volatile void __iomem *addr) |
284 | { | 290 | { |
291 | if (plat_iounmap(addr)) | ||
292 | return; | ||
293 | |||
285 | #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) | 294 | #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) |
286 | 295 | ||
287 | if (cpu_has_64bit_addresses || | 296 | if (cpu_has_64bit_addresses || |
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 91803ba30ff2..97102ebc54b1 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h | |||
@@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq) | |||
24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | 24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ |
25 | #endif | 25 | #endif |
26 | 26 | ||
27 | #ifdef CONFIG_MIPS_MT_SMTC | 27 | #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP |
28 | /* | 28 | /* |
29 | * Clear interrupt mask handling "backstop" if irq_hwmask | 29 | * Clear interrupt mask handling "backstop" if irq_hwmask |
30 | * entry so indicates. This implies that the ack() or end() | 30 | * entry so indicates. This implies that the ack() or end() |
@@ -72,4 +72,13 @@ extern int allocate_irqno(void); | |||
72 | extern void alloc_legacy_irqno(void); | 72 | extern void alloc_legacy_irqno(void); |
73 | extern void free_irqno(unsigned int irq); | 73 | extern void free_irqno(unsigned int irq); |
74 | 74 | ||
75 | /* | ||
76 | * Before R2 the timer and performance counter interrupts were both fixed to | ||
77 | * IE7. Since R2 their number has to be read from the c0_intctl register. | ||
78 | */ | ||
79 | #define CP0_LEGACY_COMPARE_IRQ 7 | ||
80 | |||
81 | extern int cp0_compare_irq; | ||
82 | extern int cp0_perfcount_irq; | ||
83 | |||
75 | #endif /* _ASM_IRQ_H */ | 84 | #endif /* _ASM_IRQ_H */ |
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h deleted file mode 100644 index edcd7544b358..000000000000 --- a/include/asm-mips/lasat/ds1603.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | #include <asm/addrspace.h> | ||
2 | |||
3 | /* Lasat 100 */ | ||
4 | #define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) | ||
5 | #define DS1603_RST_100 (1 << 2) | ||
6 | #define DS1603_CLK_100 (1 << 0) | ||
7 | #define DS1603_DATA_SHIFT_100 1 | ||
8 | #define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) | ||
9 | |||
10 | /* Lasat 200 */ | ||
11 | #define DS1603_REG_200 (KSEG1ADDR(0x11000000)) | ||
12 | #define DS1603_RST_200 (1 << 3) | ||
13 | #define DS1603_CLK_200 (1 << 4) | ||
14 | #define DS1603_DATA_200 (1 << 5) | ||
15 | |||
16 | #define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) | ||
17 | #define DS1603_DATA_READ_SHIFT_200 9 | ||
18 | #define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) | ||
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h deleted file mode 100644 index 7b53edd5cd5f..000000000000 --- a/include/asm-mips/lasat/eeprom.h +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | #include <asm/addrspace.h> | ||
2 | |||
3 | /* lasat 100 */ | ||
4 | #define AT93C_REG_100 KSEG1ADDR(0x1c810000) | ||
5 | #define AT93C_RDATA_REG_100 AT93C_REG_100 | ||
6 | #define AT93C_RDATA_SHIFT_100 4 | ||
7 | #define AT93C_WDATA_SHIFT_100 4 | ||
8 | #define AT93C_CS_M_100 ( 1 << 5 ) | ||
9 | #define AT93C_CLK_M_100 ( 1 << 3 ) | ||
10 | |||
11 | /* lasat 200 */ | ||
12 | #define AT93C_REG_200 KSEG1ADDR(0x11000000) | ||
13 | #define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) | ||
14 | #define AT93C_RDATA_SHIFT_200 8 | ||
15 | #define AT93C_WDATA_SHIFT_200 2 | ||
16 | #define AT93C_CS_M_200 ( 1 << 0 ) | ||
17 | #define AT93C_CLK_M_200 ( 1 << 1 ) | ||
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h deleted file mode 100644 index f5589f31a197..000000000000 --- a/include/asm-mips/lasat/head.h +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * Image header stuff | ||
3 | */ | ||
4 | #ifndef _HEAD_H | ||
5 | #define _HEAD_H | ||
6 | |||
7 | #define LASAT_K_MAGIC0_VAL 0xfedeabba | ||
8 | #define LASAT_K_MAGIC1_VAL 0x00bedead | ||
9 | |||
10 | #ifndef _LANGUAGE_ASSEMBLY | ||
11 | #include <linux/types.h> | ||
12 | struct bootloader_header { | ||
13 | u32 magic[2]; | ||
14 | u32 version; | ||
15 | u32 image_start; | ||
16 | u32 image_size; | ||
17 | u32 kernel_start; | ||
18 | u32 kernel_entry; | ||
19 | }; | ||
20 | #endif | ||
21 | |||
22 | #endif /* _HEAD_H */ | ||
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h deleted file mode 100644 index 42077e367a5b..000000000000 --- a/include/asm-mips/lasat/lasat.h +++ /dev/null | |||
@@ -1,253 +0,0 @@ | |||
1 | /* | ||
2 | * lasat.h | ||
3 | * | ||
4 | * Thomas Horsten <thh@lasat.com> | ||
5 | * Copyright (C) 2000 LASAT Networks A/S. | ||
6 | * | ||
7 | * This program is free software; you can distribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License (Version 2) as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
14 | * for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
19 | * | ||
20 | * Configuration for LASAT boards, loads the appropriate include files. | ||
21 | */ | ||
22 | #ifndef _LASAT_H | ||
23 | #define _LASAT_H | ||
24 | |||
25 | #ifndef _LANGUAGE_ASSEMBLY | ||
26 | |||
27 | extern struct lasat_misc { | ||
28 | volatile u32 *reset_reg; | ||
29 | volatile u32 *flash_wp_reg; | ||
30 | u32 flash_wp_bit; | ||
31 | } *lasat_misc; | ||
32 | |||
33 | enum lasat_mtdparts { | ||
34 | LASAT_MTD_BOOTLOADER, | ||
35 | LASAT_MTD_SERVICE, | ||
36 | LASAT_MTD_NORMAL, | ||
37 | LASAT_MTD_CONFIG, | ||
38 | LASAT_MTD_FS, | ||
39 | LASAT_MTD_LAST | ||
40 | }; | ||
41 | |||
42 | /* | ||
43 | * The format of the data record in the EEPROM. | ||
44 | * See Documentation/LASAT/eeprom.txt for a detailed description | ||
45 | * of the fields in this struct, and the LASAT Hardware Configuration | ||
46 | * field specification for a detailed description of the config | ||
47 | * field. | ||
48 | */ | ||
49 | #include <linux/types.h> | ||
50 | |||
51 | #define LASAT_EEPROM_VERSION 7 | ||
52 | struct lasat_eeprom_struct { | ||
53 | unsigned int version; | ||
54 | unsigned int cfg[3]; | ||
55 | unsigned char hwaddr[6]; | ||
56 | unsigned char print_partno[12]; | ||
57 | unsigned char term0; | ||
58 | unsigned char print_serial[14]; | ||
59 | unsigned char term1; | ||
60 | unsigned char prod_partno[12]; | ||
61 | unsigned char term2; | ||
62 | unsigned char prod_serial[14]; | ||
63 | unsigned char term3; | ||
64 | unsigned char passwd_hash[16]; | ||
65 | unsigned char pwdnull; | ||
66 | unsigned char vendid; | ||
67 | unsigned char ts_ref; | ||
68 | unsigned char ts_signoff; | ||
69 | unsigned char reserved[11]; | ||
70 | unsigned char debugaccess; | ||
71 | unsigned short prid; | ||
72 | unsigned int serviceflag; | ||
73 | unsigned int ipaddr; | ||
74 | unsigned int netmask; | ||
75 | unsigned int crc32; | ||
76 | }; | ||
77 | |||
78 | struct lasat_eeprom_struct_pre7 { | ||
79 | unsigned int version; | ||
80 | unsigned int flags[3]; | ||
81 | unsigned char hwaddr0[6]; | ||
82 | unsigned char hwaddr1[6]; | ||
83 | unsigned char print_partno[9]; | ||
84 | unsigned char term0; | ||
85 | unsigned char print_serial[14]; | ||
86 | unsigned char term1; | ||
87 | unsigned char prod_partno[9]; | ||
88 | unsigned char term2; | ||
89 | unsigned char prod_serial[14]; | ||
90 | unsigned char term3; | ||
91 | unsigned char passwd_hash[24]; | ||
92 | unsigned char pwdnull; | ||
93 | unsigned char vendor; | ||
94 | unsigned char ts_ref; | ||
95 | unsigned char ts_signoff; | ||
96 | unsigned char reserved[6]; | ||
97 | unsigned int writecount; | ||
98 | unsigned int ipaddr; | ||
99 | unsigned int netmask; | ||
100 | unsigned int crc32; | ||
101 | }; | ||
102 | |||
103 | /* Configuration descriptor encoding - see the doc for details */ | ||
104 | |||
105 | #define LASAT_W0_DSCTYPE(v) ( ( (v) ) & 0xf ) | ||
106 | #define LASAT_W0_BMID(v) ( ( (v) >> 0x04 ) & 0xf ) | ||
107 | #define LASAT_W0_CPUTYPE(v) ( ( (v) >> 0x08 ) & 0xf ) | ||
108 | #define LASAT_W0_BUSSPEED(v) ( ( (v) >> 0x0c ) & 0xf ) | ||
109 | #define LASAT_W0_CPUCLK(v) ( ( (v) >> 0x10 ) & 0xf ) | ||
110 | #define LASAT_W0_SDRAMBANKSZ(v) ( ( (v) >> 0x14 ) & 0xf ) | ||
111 | #define LASAT_W0_SDRAMBANKS(v) ( ( (v) >> 0x18 ) & 0xf ) | ||
112 | #define LASAT_W0_L2CACHE(v) ( ( (v) >> 0x1c ) & 0xf ) | ||
113 | |||
114 | #define LASAT_W1_EDHAC(v) ( ( (v) ) & 0xf ) | ||
115 | #define LASAT_W1_HIFN(v) ( ( (v) >> 0x04 ) & 0x1 ) | ||
116 | #define LASAT_W1_ISDN(v) ( ( (v) >> 0x05 ) & 0x1 ) | ||
117 | #define LASAT_W1_IDE(v) ( ( (v) >> 0x06 ) & 0x1 ) | ||
118 | #define LASAT_W1_HDLC(v) ( ( (v) >> 0x07 ) & 0x1 ) | ||
119 | #define LASAT_W1_USVERSION(v) ( ( (v) >> 0x08 ) & 0x1 ) | ||
120 | #define LASAT_W1_4MACS(v) ( ( (v) >> 0x09 ) & 0x1 ) | ||
121 | #define LASAT_W1_EXTSERIAL(v) ( ( (v) >> 0x0a ) & 0x1 ) | ||
122 | #define LASAT_W1_FLASHSIZE(v) ( ( (v) >> 0x0c ) & 0xf ) | ||
123 | #define LASAT_W1_PCISLOTS(v) ( ( (v) >> 0x10 ) & 0xf ) | ||
124 | #define LASAT_W1_PCI1OPT(v) ( ( (v) >> 0x14 ) & 0xf ) | ||
125 | #define LASAT_W1_PCI2OPT(v) ( ( (v) >> 0x18 ) & 0xf ) | ||
126 | #define LASAT_W1_PCI3OPT(v) ( ( (v) >> 0x1c ) & 0xf ) | ||
127 | |||
128 | /* Routines specific to LASAT boards */ | ||
129 | |||
130 | #define LASAT_BMID_MASQUERADE2 0 | ||
131 | #define LASAT_BMID_MASQUERADEPRO 1 | ||
132 | #define LASAT_BMID_SAFEPIPE25 2 | ||
133 | #define LASAT_BMID_SAFEPIPE50 3 | ||
134 | #define LASAT_BMID_SAFEPIPE100 4 | ||
135 | #define LASAT_BMID_SAFEPIPE5000 5 | ||
136 | #define LASAT_BMID_SAFEPIPE7000 6 | ||
137 | #define LASAT_BMID_SAFEPIPE1000 7 | ||
138 | //#define LASAT_BMID_SAFEPIPE30 7 | ||
139 | //#define LASAT_BMID_SAFEPIPE5100 8 | ||
140 | //#define LASAT_BMID_SAFEPIPE7100 9 | ||
141 | #define LASAT_BMID_UNKNOWN 0xf | ||
142 | #define LASAT_MAX_BMID_NAMES 9 // no larger than 15! | ||
143 | |||
144 | #define LASAT_HAS_EDHAC ( 1 << 0 ) | ||
145 | #define LASAT_EDHAC_FAST ( 1 << 1 ) | ||
146 | #define LASAT_HAS_EADI ( 1 << 2 ) | ||
147 | #define LASAT_HAS_HIFN ( 1 << 3 ) | ||
148 | #define LASAT_HAS_ISDN ( 1 << 4 ) | ||
149 | #define LASAT_HAS_LEASEDLINE_IF ( 1 << 5 ) | ||
150 | #define LASAT_HAS_HDC ( 1 << 6 ) | ||
151 | |||
152 | #define LASAT_PRID_MASQUERADE2 0 | ||
153 | #define LASAT_PRID_MASQUERADEPRO 1 | ||
154 | #define LASAT_PRID_SAFEPIPE25 2 | ||
155 | #define LASAT_PRID_SAFEPIPE50 3 | ||
156 | #define LASAT_PRID_SAFEPIPE100 4 | ||
157 | #define LASAT_PRID_SAFEPIPE5000 5 | ||
158 | #define LASAT_PRID_SAFEPIPE7000 6 | ||
159 | #define LASAT_PRID_SAFEPIPE30 7 | ||
160 | #define LASAT_PRID_SAFEPIPE5100 8 | ||
161 | #define LASAT_PRID_SAFEPIPE7100 9 | ||
162 | |||
163 | #define LASAT_PRID_SAFEPIPE1110 10 | ||
164 | #define LASAT_PRID_SAFEPIPE3020 11 | ||
165 | #define LASAT_PRID_SAFEPIPE3030 12 | ||
166 | #define LASAT_PRID_SAFEPIPE5020 13 | ||
167 | #define LASAT_PRID_SAFEPIPE5030 14 | ||
168 | #define LASAT_PRID_SAFEPIPE1120 15 | ||
169 | #define LASAT_PRID_SAFEPIPE1130 16 | ||
170 | #define LASAT_PRID_SAFEPIPE6010 17 | ||
171 | #define LASAT_PRID_SAFEPIPE6110 18 | ||
172 | #define LASAT_PRID_SAFEPIPE6210 19 | ||
173 | #define LASAT_PRID_SAFEPIPE1020 20 | ||
174 | #define LASAT_PRID_SAFEPIPE1040 21 | ||
175 | #define LASAT_PRID_SAFEPIPE1060 22 | ||
176 | |||
177 | struct lasat_info { | ||
178 | unsigned int li_cpu_hz; | ||
179 | unsigned int li_bus_hz; | ||
180 | unsigned int li_bmid; | ||
181 | unsigned int li_memsize; | ||
182 | unsigned int li_flash_size; | ||
183 | unsigned int li_prid; | ||
184 | unsigned char li_bmstr[16]; | ||
185 | unsigned char li_namestr[32]; | ||
186 | unsigned char li_typestr[16]; | ||
187 | /* Info on the Flash layout */ | ||
188 | unsigned int li_flash_base; | ||
189 | unsigned long li_flashpart_base[LASAT_MTD_LAST]; | ||
190 | unsigned long li_flashpart_size[LASAT_MTD_LAST]; | ||
191 | struct lasat_eeprom_struct li_eeprom_info; | ||
192 | unsigned int li_eeprom_upgrade_version; | ||
193 | unsigned int li_debugaccess; | ||
194 | }; | ||
195 | |||
196 | extern struct lasat_info lasat_board_info; | ||
197 | |||
198 | static inline unsigned long lasat_flash_partition_start(int partno) | ||
199 | { | ||
200 | if (partno < 0 || partno >= LASAT_MTD_LAST) | ||
201 | return 0; | ||
202 | |||
203 | return lasat_board_info.li_flashpart_base[partno]; | ||
204 | } | ||
205 | |||
206 | static inline unsigned long lasat_flash_partition_size(int partno) | ||
207 | { | ||
208 | if (partno < 0 || partno >= LASAT_MTD_LAST) | ||
209 | return 0; | ||
210 | |||
211 | return lasat_board_info.li_flashpart_size[partno]; | ||
212 | } | ||
213 | |||
214 | /* Called from setup() to initialize the global board_info struct */ | ||
215 | extern int lasat_init_board_info(void); | ||
216 | |||
217 | /* Write the modified EEPROM info struct */ | ||
218 | extern void lasat_write_eeprom_info(void); | ||
219 | |||
220 | #define N_MACHTYPES 2 | ||
221 | /* for calibration of delays */ | ||
222 | |||
223 | /* the lasat_ndelay function is necessary because it is used at an | ||
224 | * early stage of the boot process where ndelay is not calibrated. | ||
225 | * It is used for the bit-banging rtc and eeprom drivers */ | ||
226 | |||
227 | #include <asm/delay.h> | ||
228 | /* calculating with the slowest board with 100 MHz clock */ | ||
229 | #define LASAT_100_DIVIDER 20 | ||
230 | /* All 200's run at 250 MHz clock */ | ||
231 | #define LASAT_200_DIVIDER 8 | ||
232 | |||
233 | extern unsigned int lasat_ndelay_divider; | ||
234 | |||
235 | static inline void lasat_ndelay(unsigned int ns) | ||
236 | { | ||
237 | __delay(ns / lasat_ndelay_divider); | ||
238 | } | ||
239 | |||
240 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | ||
241 | |||
242 | #define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef | ||
243 | #define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba | ||
244 | |||
245 | /* Lasat 100 boards */ | ||
246 | #define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) | ||
247 | |||
248 | /* Lasat 200 boards */ | ||
249 | #define Vrc5074_PHYS_BASE 0x1fa00000 | ||
250 | #define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) | ||
251 | #define PCI_WINDOW1 0x1a000000 | ||
252 | |||
253 | #endif /* _LASAT_H */ | ||
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h deleted file mode 100644 index 065474feeccc..000000000000 --- a/include/asm-mips/lasat/lasatint.h +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | #define LASATINT_END 16 | ||
2 | |||
3 | /* lasat 100 */ | ||
4 | #define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) | ||
5 | #define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) | ||
6 | #define LASATINT_MASK_SHIFT_100 0 | ||
7 | |||
8 | /* lasat 200 */ | ||
9 | #define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) | ||
10 | #define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) | ||
11 | #define LASATINT_MASK_SHIFT_200 16 | ||
12 | |||
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h deleted file mode 100644 index 42a492edc40e..000000000000 --- a/include/asm-mips/lasat/picvue.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | /* Lasat 100 */ | ||
2 | #define PVC_REG_100 KSEG1ADDR(0x1c820000) | ||
3 | #define PVC_DATA_SHIFT_100 0 | ||
4 | #define PVC_DATA_M_100 0xFF | ||
5 | #define PVC_E_100 (1 << 8) | ||
6 | #define PVC_RW_100 (1 << 9) | ||
7 | #define PVC_RS_100 (1 << 10) | ||
8 | |||
9 | /* Lasat 200 */ | ||
10 | #define PVC_REG_200 KSEG1ADDR(0x11000000) | ||
11 | #define PVC_DATA_SHIFT_200 24 | ||
12 | #define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) | ||
13 | #define PVC_E_200 (1 << 16) | ||
14 | #define PVC_RW_200 (1 << 17) | ||
15 | #define PVC_RS_200 (1 << 18) | ||
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h deleted file mode 100644 index 9e88c7669c7a..000000000000 --- a/include/asm-mips/lasat/serial.h +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | #include <asm/lasat/lasat.h> | ||
2 | |||
3 | /* Lasat 100 boards serial configuration */ | ||
4 | #define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) | ||
5 | #define LASAT_UART_REGS_BASE_100 0x1c8b0000 | ||
6 | #define LASAT_UART_REGS_SHIFT_100 2 | ||
7 | #define LASATINT_UART_100 8 | ||
8 | |||
9 | /* * LASAT 200 boards serial configuration */ | ||
10 | #define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) | ||
11 | #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) | ||
12 | #define LASAT_UART_REGS_SHIFT_200 3 | ||
13 | #define LASATINT_UART_200 13 | ||
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h deleted file mode 100644 index 27911e054ffc..000000000000 --- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | #ifndef __AU1XXX_GPIO_H | ||
2 | #define __AU1XXX_GPIO_H | ||
3 | |||
4 | void au1xxx_gpio1_set_inputs(void); | ||
5 | void au1xxx_gpio_tristate(int signal); | ||
6 | void au1xxx_gpio_write(int signal, int value); | ||
7 | int au1xxx_gpio_read(int signal); | ||
8 | |||
9 | typedef volatile struct | ||
10 | { | ||
11 | u32 dir; | ||
12 | u32 reserved; | ||
13 | u32 output; | ||
14 | u32 pinstate; | ||
15 | u32 inten; | ||
16 | u32 enable; | ||
17 | |||
18 | } AU1X00_GPIO2; | ||
19 | |||
20 | #endif //__AU1XXX_GPIO_H | ||
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 8fcae21adbd5..4663e8b415c9 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h | |||
@@ -88,26 +88,26 @@ static const struct drive_list_entry dma_white_list [] = { | |||
88 | /* | 88 | /* |
89 | * Hitachi | 89 | * Hitachi |
90 | */ | 90 | */ |
91 | { "HITACHI_DK14FA-20" , "ALL" }, | 91 | { "HITACHI_DK14FA-20" , NULL }, |
92 | { "HTS726060M9AT00" , "ALL" }, | 92 | { "HTS726060M9AT00" , NULL }, |
93 | /* | 93 | /* |
94 | * Maxtor | 94 | * Maxtor |
95 | */ | 95 | */ |
96 | { "Maxtor 6E040L0" , "ALL" }, | 96 | { "Maxtor 6E040L0" , NULL }, |
97 | { "Maxtor 6Y080P0" , "ALL" }, | 97 | { "Maxtor 6Y080P0" , NULL }, |
98 | { "Maxtor 6Y160P0" , "ALL" }, | 98 | { "Maxtor 6Y160P0" , NULL }, |
99 | /* | 99 | /* |
100 | * Seagate | 100 | * Seagate |
101 | */ | 101 | */ |
102 | { "ST3120026A" , "ALL" }, | 102 | { "ST3120026A" , NULL }, |
103 | { "ST320014A" , "ALL" }, | 103 | { "ST320014A" , NULL }, |
104 | { "ST94011A" , "ALL" }, | 104 | { "ST94011A" , NULL }, |
105 | { "ST340016A" , "ALL" }, | 105 | { "ST340016A" , NULL }, |
106 | /* | 106 | /* |
107 | * Western Digital | 107 | * Western Digital |
108 | */ | 108 | */ |
109 | { "WDC WD400UE-00HCT0" , "ALL" }, | 109 | { "WDC WD400UE-00HCT0" , NULL }, |
110 | { "WDC WD400JB-00JJC0" , "ALL" }, | 110 | { "WDC WD400JB-00JJC0" , NULL }, |
111 | { NULL , NULL } | 111 | { NULL , NULL } |
112 | }; | 112 | }; |
113 | 113 | ||
@@ -116,9 +116,9 @@ static const struct drive_list_entry dma_black_list [] = { | |||
116 | /* | 116 | /* |
117 | * Western Digital | 117 | * Western Digital |
118 | */ | 118 | */ |
119 | { "WDC WD100EB-00CGH0" , "ALL" }, | 119 | { "WDC WD100EB-00CGH0" , NULL }, |
120 | { "WDC WD200BB-00AUA1" , "ALL" }, | 120 | { "WDC WD200BB-00AUA1" , NULL }, |
121 | { "WDC AC24300L" , "ALL" }, | 121 | { "WDC AC24300L" , NULL }, |
122 | { NULL , NULL } | 122 | { NULL , NULL } |
123 | }; | 123 | }; |
124 | #endif | 124 | #endif |
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h new file mode 100644 index 000000000000..2dc61e009a08 --- /dev/null +++ b/include/asm-mips/mach-au1x00/gpio.h | |||
@@ -0,0 +1,69 @@ | |||
1 | #ifndef _AU1XXX_GPIO_H_ | ||
2 | #define _AU1XXX_GPIO_H_ | ||
3 | |||
4 | #include <linux/types.h> | ||
5 | |||
6 | #define AU1XXX_GPIO_BASE 200 | ||
7 | |||
8 | struct au1x00_gpio2 { | ||
9 | u32 dir; | ||
10 | u32 reserved; | ||
11 | u32 output; | ||
12 | u32 pinstate; | ||
13 | u32 inten; | ||
14 | u32 enable; | ||
15 | }; | ||
16 | |||
17 | extern int au1xxx_gpio_get_value(unsigned gpio); | ||
18 | extern void au1xxx_gpio_set_value(unsigned gpio, int value); | ||
19 | extern int au1xxx_gpio_direction_input(unsigned gpio); | ||
20 | extern int au1xxx_gpio_direction_output(unsigned gpio, int value); | ||
21 | |||
22 | |||
23 | /* Wrappers for the arch-neutral GPIO API */ | ||
24 | |||
25 | static inline int gpio_request(unsigned gpio, const char *label) | ||
26 | { | ||
27 | /* Not yet implemented */ | ||
28 | return 0; | ||
29 | } | ||
30 | |||
31 | static inline void gpio_free(unsigned gpio) | ||
32 | { | ||
33 | /* Not yet implemented */ | ||
34 | } | ||
35 | |||
36 | static inline int gpio_direction_input(unsigned gpio) | ||
37 | { | ||
38 | return au1xxx_gpio_direction_input(gpio); | ||
39 | } | ||
40 | |||
41 | static inline int gpio_direction_output(unsigned gpio, int value) | ||
42 | { | ||
43 | return au1xxx_gpio_direction_output(gpio, value); | ||
44 | } | ||
45 | |||
46 | static inline int gpio_get_value(unsigned gpio) | ||
47 | { | ||
48 | return au1xxx_gpio_get_value(gpio); | ||
49 | } | ||
50 | |||
51 | static inline void gpio_set_value(unsigned gpio, int value) | ||
52 | { | ||
53 | au1xxx_gpio_set_value(gpio, value); | ||
54 | } | ||
55 | |||
56 | static inline int gpio_to_irq(unsigned gpio) | ||
57 | { | ||
58 | return gpio; | ||
59 | } | ||
60 | |||
61 | static inline int irq_to_gpio(unsigned irq) | ||
62 | { | ||
63 | return irq; | ||
64 | } | ||
65 | |||
66 | /* For cansleep */ | ||
67 | #include <asm-generic/gpio.h> | ||
68 | |||
69 | #endif /* _AU1XXX_GPIO_H_ */ | ||
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h index 098fca4289bb..364cea2dc71f 100644 --- a/include/asm-mips/mach-au1x00/ioremap.h +++ b/include/asm-mips/mach-au1x00/ioremap.h | |||
@@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) | |||
28 | return __fixup_bigphys_addr(phys_addr, size); | 28 | return __fixup_bigphys_addr(phys_addr, size); |
29 | } | 29 | } |
30 | 30 | ||
31 | static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, | ||
32 | unsigned long flags) | ||
33 | { | ||
34 | return NULL; | ||
35 | } | ||
36 | |||
37 | static inline int plat_iounmap(const volatile void __iomem *addr) | ||
38 | { | ||
39 | return 0; | ||
40 | } | ||
41 | |||
31 | #endif /* __ASM_MACH_AU1X00_IOREMAP_H */ | 42 | #endif /* __ASM_MACH_AU1X00_IOREMAP_H */ |
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 684a501c04cf..9c9d2b998ca4 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h | |||
@@ -30,7 +30,6 @@ | |||
30 | #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE | 30 | #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE |
31 | 31 | ||
32 | #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) | 32 | #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) |
33 | #define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ | ||
34 | #define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) | 33 | #define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) |
35 | #define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) | 34 | #define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) |
36 | #define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) | 35 | #define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) |
@@ -71,10 +70,6 @@ | |||
71 | 70 | ||
72 | extern int cobalt_board_id; | 71 | extern int cobalt_board_id; |
73 | 72 | ||
74 | #define PCI_CFG_SET(devfn,where) \ | ||
75 | GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \ | ||
76 | (PCI_FUNC (devfn) << 8) | (where))) | ||
77 | |||
78 | #define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) | 73 | #define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) |
79 | # define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ | 74 | # define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ |
80 | # define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ | 75 | # define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ |
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index c6dfa59d1986..d38f069d9e95 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | 6 | * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) |
7 | */ | 7 | */ |
8 | #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H |
@@ -46,6 +46,8 @@ | |||
46 | #define cpu_has_ic_fills_f_dc 0 | 46 | #define cpu_has_ic_fills_f_dc 0 |
47 | #define cpu_icache_snoops_remote_store 0 | 47 | #define cpu_icache_snoops_remote_store 0 |
48 | #define cpu_has_dsp 0 | 48 | #define cpu_has_dsp 0 |
49 | #define cpu_has_mipsmt 0 | ||
50 | #define cpu_has_userlocal 0 | ||
49 | 51 | ||
50 | #define cpu_has_mips32r1 0 | 52 | #define cpu_has_mips32r1 0 |
51 | #define cpu_has_mips32r2 0 | 53 | #define cpu_has_mips32r2 0 |
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h deleted file mode 100644 index 7e272ce57ea3..000000000000 --- a/include/asm-mips/mach-ev64120/mach-gt64120.h +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | /* | ||
2 | * This is a direct copy of the ev96100.h file, with a global | ||
3 | * search and replace. The numbers are the same. | ||
4 | * | ||
5 | * The reason I'm duplicating this is so that the 64120/96100 | ||
6 | * defines won't be confusing in the source code. | ||
7 | */ | ||
8 | #ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H | ||
9 | #define __ASM_GALILEO_BOARDS_MIPS_EV64120_H | ||
10 | |||
11 | /* | ||
12 | * GT64120 config space base address | ||
13 | */ | ||
14 | extern unsigned long gt64120_base; | ||
15 | |||
16 | #define GT64120_BASE (gt64120_base) | ||
17 | |||
18 | /* | ||
19 | * PCI Bus allocation | ||
20 | */ | ||
21 | #define GT_PCI_MEM_BASE 0x12000000UL | ||
22 | #define GT_PCI_MEM_SIZE 0x02000000UL | ||
23 | #define GT_PCI_IO_BASE 0x10000000UL | ||
24 | #define GT_PCI_IO_SIZE 0x02000000UL | ||
25 | #define GT_ISA_IO_BASE PCI_IO_BASE | ||
26 | |||
27 | /* | ||
28 | * Duart I/O ports. | ||
29 | */ | ||
30 | #define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) | ||
31 | #define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) | ||
32 | |||
33 | |||
34 | /* | ||
35 | * EV64120 interrupt controller register base. | ||
36 | */ | ||
37 | #define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) | ||
38 | |||
39 | /* | ||
40 | * EV64120 UART register base. | ||
41 | */ | ||
42 | #define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) | ||
43 | #define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) | ||
44 | #define EV64120_BASE_BAUD ( 3686400 / 16 ) | ||
45 | #define EV64120_UART_IRQ 6 | ||
46 | |||
47 | /* | ||
48 | * PCI interrupts will come in on either the INTA or INTD interrups lines, | ||
49 | * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our | ||
50 | * boards, they all either come in on IntD or they all come in on IntA, they | ||
51 | * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the | ||
52 | * "requested" interrupt numbers and go through the list whenever we get an | ||
53 | * IntA/D. | ||
54 | * | ||
55 | * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and | ||
56 | * INTD is 11. | ||
57 | */ | ||
58 | #define GT_TIMER 4 | ||
59 | #define GT_INTA 2 | ||
60 | #define GT_INTD 5 | ||
61 | |||
62 | #endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */ | ||
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 0d31854222f9..07f4322c235d 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h | |||
@@ -4,6 +4,7 @@ | |||
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> | 6 | * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> |
7 | * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) | ||
7 | */ | 8 | */ |
8 | #ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H | 9 | #ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H | 10 | #define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H |
@@ -27,6 +28,8 @@ | |||
27 | #define cpu_has_ic_fills_f_dc 0 | 28 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | 29 | #define cpu_has_dsp 0 |
29 | #define cpu_icache_snoops_remote_store 0 | 30 | #define cpu_icache_snoops_remote_store 0 |
31 | #define cpu_has_mipsmt 0 | ||
32 | #define cpu_has_userlocal 0 | ||
30 | 33 | ||
31 | #define cpu_has_nofpuex 0 | 34 | #define cpu_has_nofpuex 0 |
32 | #define cpu_has_64bits 1 | 35 | #define cpu_has_64bits 1 |
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h new file mode 100644 index 000000000000..6eaf5efedf3a --- /dev/null +++ b/include/asm-mips/mach-generic/gpio.h | |||
@@ -0,0 +1,15 @@ | |||
1 | #ifndef __ASM_MACH_GENERIC_GPIO_H | ||
2 | #define __ASM_MACH_GENERIC_GPIO_H | ||
3 | |||
4 | int gpio_request(unsigned gpio, const char *label); | ||
5 | void gpio_free(unsigned gpio); | ||
6 | int gpio_direction_input(unsigned gpio); | ||
7 | int gpio_direction_output(unsigned gpio, int value); | ||
8 | int gpio_get_value(unsigned gpio); | ||
9 | void gpio_set_value(unsigned gpio, int value); | ||
10 | int gpio_to_irq(unsigned gpio); | ||
11 | int irq_to_gpio(unsigned irq); | ||
12 | |||
13 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
14 | |||
15 | #endif /* __ASM_MACH_GENERIC_GPIO_H */ | ||
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h index 9b64ff6e485d..b379938d47f0 100644 --- a/include/asm-mips/mach-generic/ioremap.h +++ b/include/asm-mips/mach-generic/ioremap.h | |||
@@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) | |||
20 | return phys_addr; | 20 | return phys_addr; |
21 | } | 21 | } |
22 | 22 | ||
23 | static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, | ||
24 | unsigned long flags) | ||
25 | { | ||
26 | return NULL; | ||
27 | } | ||
28 | |||
29 | static inline int plat_iounmap(const volatile void __iomem *addr) | ||
30 | { | ||
31 | return 0; | ||
32 | } | ||
33 | |||
23 | #endif /* __ASM_MACH_GENERIC_IOREMAP_H */ | 34 | #endif /* __ASM_MACH_GENERIC_IOREMAP_H */ |
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 0ae9997bc9a8..c9fa4b14968d 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h | |||
@@ -10,38 +10,54 @@ | |||
10 | #ifndef _ASM_MACH_GENERIC_SPACES_H | 10 | #ifndef _ASM_MACH_GENERIC_SPACES_H |
11 | #define _ASM_MACH_GENERIC_SPACES_H | 11 | #define _ASM_MACH_GENERIC_SPACES_H |
12 | 12 | ||
13 | #include <linux/const.h> | ||
14 | |||
15 | /* | ||
16 | * This gives the physical RAM offset. | ||
17 | */ | ||
18 | #ifndef PHYS_OFFSET | ||
19 | #define PHYS_OFFSET _AC(0, UL) | ||
20 | #endif | ||
13 | 21 | ||
14 | #ifdef CONFIG_32BIT | 22 | #ifdef CONFIG_32BIT |
15 | 23 | ||
16 | #define CAC_BASE 0x80000000 | 24 | #define CAC_BASE _AC(0x80000000, UL) |
17 | #define IO_BASE 0xa0000000 | 25 | #define IO_BASE _AC(0xa0000000, UL) |
18 | #define UNCAC_BASE 0xa0000000 | 26 | #define UNCAC_BASE _AC(0xa0000000, UL) |
19 | #define MAP_BASE 0xc0000000 | ||
20 | 27 | ||
21 | /* | 28 | #ifndef MAP_BASE |
22 | * This handles the memory map. | 29 | #define MAP_BASE _AC(0xc0000000, UL) |
23 | * We handle pages at KSEG0 for kernels with 32 bit address space. | 30 | #endif |
24 | */ | ||
25 | #define PAGE_OFFSET 0x80000000UL | ||
26 | 31 | ||
27 | /* | 32 | /* |
28 | * Memory above this physical address will be considered highmem. | 33 | * Memory above this physical address will be considered highmem. |
29 | */ | 34 | */ |
30 | #ifndef HIGHMEM_START | 35 | #ifndef HIGHMEM_START |
31 | #define HIGHMEM_START 0x20000000UL | 36 | #define HIGHMEM_START _AC(0x20000000, UL) |
32 | #endif | 37 | #endif |
33 | 38 | ||
34 | #endif /* CONFIG_32BIT */ | 39 | #endif /* CONFIG_32BIT */ |
35 | 40 | ||
36 | #ifdef CONFIG_64BIT | 41 | #ifdef CONFIG_64BIT |
37 | 42 | ||
38 | /* | 43 | #ifndef CAC_BASE |
39 | * This handles the memory map. | ||
40 | */ | ||
41 | #ifdef CONFIG_DMA_NONCOHERENT | 44 | #ifdef CONFIG_DMA_NONCOHERENT |
42 | #define PAGE_OFFSET 0x9800000000000000UL | 45 | #define CAC_BASE _AC(0x9800000000000000, UL) |
43 | #else | 46 | #else |
44 | #define PAGE_OFFSET 0xa800000000000000UL | 47 | #define CAC_BASE _AC(0xa800000000000000, UL) |
48 | #endif | ||
49 | #endif | ||
50 | |||
51 | #ifndef IO_BASE | ||
52 | #define IO_BASE _AC(0x9000000000000000, UL) | ||
53 | #endif | ||
54 | |||
55 | #ifndef UNCAC_BASE | ||
56 | #define UNCAC_BASE _AC(0x9000000000000000, UL) | ||
57 | #endif | ||
58 | |||
59 | #ifndef MAP_BASE | ||
60 | #define MAP_BASE _AC(0xc000000000000000, UL) | ||
45 | #endif | 61 | #endif |
46 | 62 | ||
47 | /* | 63 | /* |
@@ -50,22 +66,20 @@ | |||
50 | * in the distant future. Nobody will care for a few years :-) | 66 | * in the distant future. Nobody will care for a few years :-) |
51 | */ | 67 | */ |
52 | #ifndef HIGHMEM_START | 68 | #ifndef HIGHMEM_START |
53 | #define HIGHMEM_START (1UL << 59UL) | 69 | #define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) |
54 | #endif | 70 | #endif |
55 | 71 | ||
56 | #ifdef CONFIG_DMA_NONCOHERENT | ||
57 | #define CAC_BASE 0x9800000000000000UL | ||
58 | #else | ||
59 | #define CAC_BASE 0xa800000000000000UL | ||
60 | #endif | ||
61 | #define IO_BASE 0x9000000000000000UL | ||
62 | #define UNCAC_BASE 0x9000000000000000UL | ||
63 | #define MAP_BASE 0xc000000000000000UL | ||
64 | |||
65 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | 72 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) |
66 | #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) | 73 | #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) |
67 | #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) | 74 | #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) |
68 | 75 | ||
69 | #endif /* CONFIG_64BIT */ | 76 | #endif /* CONFIG_64BIT */ |
70 | 77 | ||
78 | /* | ||
79 | * This handles the memory map. | ||
80 | */ | ||
81 | #ifndef PAGE_OFFSET | ||
82 | #define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) | ||
83 | #endif | ||
84 | |||
71 | #endif /* __ASM_MACH_GENERIC_SPACES_H */ | 85 | #endif /* __ASM_MACH_GENERIC_SPACES_H */ |
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index f7c5dc8a5336..9c8735158da1 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003 Ralf Baechle | 6 | * Copyright (C) 2003, 07 Ralf Baechle |
7 | */ | 7 | */ |
8 | #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H |
@@ -30,6 +30,8 @@ | |||
30 | #define cpu_has_ic_fills_f_dc 0 | 30 | #define cpu_has_ic_fills_f_dc 0 |
31 | 31 | ||
32 | #define cpu_has_dsp 0 | 32 | #define cpu_has_dsp 0 |
33 | #define cpu_has_mipsmt 0 | ||
34 | #define cpu_has_userlocal 0 | ||
33 | 35 | ||
34 | #define cpu_has_nofpuex 0 | 36 | #define cpu_has_nofpuex 0 |
35 | #define cpu_has_64bits 1 | 37 | #define cpu_has_64bits 1 |
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index ab20c026fd19..7f9fa6f66059 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h | |||
@@ -11,44 +11,17 @@ | |||
11 | #define _ASM_MACH_IP22_SPACES_H | 11 | #define _ASM_MACH_IP22_SPACES_H |
12 | 12 | ||
13 | 13 | ||
14 | #ifdef CONFIG_32BIT | ||
15 | |||
16 | #define CAC_BASE 0x80000000 | ||
17 | #define IO_BASE 0xa0000000 | ||
18 | #define UNCAC_BASE 0xa0000000 | ||
19 | #define MAP_BASE 0xc0000000 | ||
20 | |||
21 | /* | ||
22 | * This handles the memory map. | ||
23 | * We handle pages at KSEG0 for kernels with 32 bit address space. | ||
24 | */ | ||
25 | #define PAGE_OFFSET 0x80000000UL | ||
26 | |||
27 | /* | ||
28 | * Memory above this physical address will be considered highmem. | ||
29 | */ | ||
30 | #ifndef HIGHMEM_START | ||
31 | #define HIGHMEM_START 0x20000000UL | ||
32 | #endif | ||
33 | |||
34 | #endif /* CONFIG_32BIT */ | ||
35 | |||
36 | #ifdef CONFIG_64BIT | 14 | #ifdef CONFIG_64BIT |
37 | #define PAGE_OFFSET 0xffffffff80000000UL | ||
38 | 15 | ||
39 | #ifndef HIGHMEM_START | 16 | #define PAGE_OFFSET 0xffffffff80000000UL |
40 | #define HIGHMEM_START (1UL << 59UL) | ||
41 | #endif | ||
42 | 17 | ||
43 | #define CAC_BASE 0xffffffff80000000 | 18 | #define CAC_BASE 0xffffffff80000000 |
44 | #define IO_BASE 0xffffffffa0000000 | 19 | #define IO_BASE 0xffffffffa0000000 |
45 | #define UNCAC_BASE 0xffffffffa0000000 | 20 | #define UNCAC_BASE 0xffffffffa0000000 |
46 | #define MAP_BASE 0xc000000000000000 | 21 | #define MAP_BASE 0xc000000000000000 |
47 | 22 | ||
48 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | ||
49 | #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) | ||
50 | #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) | ||
51 | |||
52 | #endif /* CONFIG_64BIT */ | 23 | #endif /* CONFIG_64BIT */ |
53 | 24 | ||
25 | #include <asm/mach-generic/spaces.h> | ||
26 | |||
54 | #endif /* __ASM_MACH_IP22_SPACES_H */ | 27 | #endif /* __ASM_MACH_IP22_SPACES_H */ |
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index a071974b67bb..fe076380c189 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003 Ralf Baechle | 6 | * Copyright (C) 2003, 07 Ralf Baechle |
7 | */ | 7 | */ |
8 | #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H |
@@ -27,6 +27,8 @@ | |||
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | 28 | #define cpu_has_dsp 0 |
29 | #define cpu_icache_snoops_remote_store 1 | 29 | #define cpu_icache_snoops_remote_store 1 |
30 | #define cpu_has_mipsmt 0 | ||
31 | #define cpu_has_userlocal 0 | ||
30 | 32 | ||
31 | #define cpu_has_nofpuex 0 | 33 | #define cpu_has_nofpuex 0 |
32 | #define cpu_has_64bits 1 | 34 | #define cpu_has_64bits 1 |
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h index 45e61785ef42..b18802a0b17e 100644 --- a/include/asm-mips/mach-ip27/spaces.h +++ b/include/asm-mips/mach-ip27/spaces.h | |||
@@ -14,22 +14,17 @@ | |||
14 | * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects | 14 | * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects |
15 | * uncached memory addressing. | 15 | * uncached memory addressing. |
16 | */ | 16 | */ |
17 | #define CAC_BASE 0xa800000000000000 | ||
18 | 17 | ||
19 | #define HSPEC_BASE 0x9000000000000000 | 18 | #define HSPEC_BASE 0x9000000000000000 |
20 | #define IO_BASE 0x9200000000000000 | 19 | #define IO_BASE 0x9200000000000000 |
21 | #define MSPEC_BASE 0x9400000000000000 | 20 | #define MSPEC_BASE 0x9400000000000000 |
22 | #define UNCAC_BASE 0x9600000000000000 | 21 | #define UNCAC_BASE 0x9600000000000000 |
23 | #define MAP_BASE 0xc000000000000000 | ||
24 | 22 | ||
25 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | ||
26 | #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) | ||
27 | #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) | ||
28 | #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) | 23 | #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) |
29 | #define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) | 24 | #define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) |
30 | 25 | ||
31 | #define PAGE_OFFSET CAC_BASE | ||
32 | |||
33 | #define HIGHMEM_START (~0UL) | 26 | #define HIGHMEM_START (~0UL) |
34 | 27 | ||
28 | #include <asm/mach-generic/spaces.h> | ||
29 | |||
35 | #endif /* _ASM_MACH_IP27_SPACES_H */ | 30 | #endif /* _ASM_MACH_IP27_SPACES_H */ |
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 2a3de092bf13..6782fccebe8d 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h | |||
@@ -4,7 +4,7 @@ | |||
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2005 Ilya A. Volynets-Evenbakh | 6 | * Copyright (C) 2005 Ilya A. Volynets-Evenbakh |
7 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) | 7 | * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org) |
8 | */ | 8 | */ |
9 | #ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H | 9 | #ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H |
10 | #define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H | 10 | #define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H |
@@ -38,6 +38,8 @@ | |||
38 | #define cpu_has_ic_fills_f_dc 0 | 38 | #define cpu_has_ic_fills_f_dc 0 |
39 | #define cpu_has_dsp 0 | 39 | #define cpu_has_dsp 0 |
40 | #define cpu_has_4k_cache 1 | 40 | #define cpu_has_4k_cache 1 |
41 | #define cpu_has_mipsmt 0 | ||
42 | #define cpu_has_userlocal 0 | ||
41 | 43 | ||
42 | 44 | ||
43 | #define cpu_has_mips32r1 0 | 45 | #define cpu_has_mips32r1 0 |
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h index c3f9a6a20eb0..a5511ebb2d53 100644 --- a/include/asm-mips/mach-ip32/dma-coherence.h +++ b/include/asm-mips/mach-ip32/dma-coherence.h | |||
@@ -6,8 +6,8 @@ | |||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | 6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> |
7 | * | 7 | * |
8 | */ | 8 | */ |
9 | #ifndef __ASM_MACH_IP35_DMA_COHERENCE_H | 9 | #ifndef __ASM_MACH_IP32_DMA_COHERENCE_H |
10 | #define __ASM_MACH_IP35_DMA_COHERENCE_H | 10 | #define __ASM_MACH_IP32_DMA_COHERENCE_H |
11 | 11 | ||
12 | #include <asm/ip32/crime.h> | 12 | #include <asm/ip32/crime.h> |
13 | 13 | ||
@@ -69,4 +69,4 @@ static inline int plat_device_is_coherent(struct device *dev) | |||
69 | return 0; /* IP32 is non-cohernet */ | 69 | return 0; /* IP32 is non-cohernet */ |
70 | } | 70 | } |
71 | 71 | ||
72 | #endif /* __ASM_MACH_IP35_DMA_COHERENCE_H */ | 72 | #endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */ |
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h deleted file mode 100644 index 44abe5c02389..000000000000 --- a/include/asm-mips/mach-ip32/spaces.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org) | ||
7 | * Copyright (C) 2000, 2002 Maciej W. Rozycki | ||
8 | * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. | ||
9 | */ | ||
10 | #ifndef _ASM_MACH_IP32_SPACES_H | ||
11 | #define _ASM_MACH_IP32_SPACES_H | ||
12 | |||
13 | /* | ||
14 | * Memory above this physical address will be considered highmem. | ||
15 | * Fixme: 59 bits is a fictive number and makes assumptions about processors | ||
16 | * in the distant future. Nobody will care for a few years :-) | ||
17 | */ | ||
18 | #ifndef HIGHMEM_START | ||
19 | #define HIGHMEM_START (1UL << 59UL) | ||
20 | #endif | ||
21 | |||
22 | #define CAC_BASE 0x9800000000000000UL | ||
23 | #define IO_BASE 0x9000000000000000UL | ||
24 | #define UNCAC_BASE 0x9000000000000000UL | ||
25 | #define MAP_BASE 0xc000000000000000UL | ||
26 | |||
27 | #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) | ||
28 | #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) | ||
29 | #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) | ||
30 | |||
31 | /* | ||
32 | * This handles the memory map. | ||
33 | */ | ||
34 | #define PAGE_OFFSET CAC_BASE | ||
35 | |||
36 | #endif /* __ASM_MACH_IP32_SPACES_H */ | ||
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h new file mode 100644 index 000000000000..aa131ad7f717 --- /dev/null +++ b/include/asm-mips/mach-jmr3927/ioremap.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * include/asm-mips/mach-jmr3927/ioremap.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation; either version | ||
7 | * 2 of the License, or (at your option) any later version. | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_JMR3927_IOREMAP_H | ||
10 | #define __ASM_MACH_JMR3927_IOREMAP_H | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | |||
14 | /* | ||
15 | * Allow physical addresses to be fixed up to help peripherals located | ||
16 | * outside the low 32-bit range -- generic pass-through version. | ||
17 | */ | ||
18 | static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) | ||
19 | { | ||
20 | return phys_addr; | ||
21 | } | ||
22 | |||
23 | static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, | ||
24 | unsigned long flags) | ||
25 | { | ||
26 | #define TXX9_DIRECTMAP_BASE 0xff000000ul | ||
27 | if (offset >= TXX9_DIRECTMAP_BASE && | ||
28 | offset < TXX9_DIRECTMAP_BASE + 0xf0000) | ||
29 | return (void __iomem *)offset; | ||
30 | return NULL; | ||
31 | } | ||
32 | |||
33 | static inline int plat_iounmap(const volatile void __iomem *addr) | ||
34 | { | ||
35 | return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; | ||
36 | } | ||
37 | |||
38 | #endif /* __ASM_MACH_JMR3927_IOREMAP_H */ | ||
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h deleted file mode 100644 index 1a9ad45cc135..000000000000 --- a/include/asm-mips/mach-lasat/mach-gt64120.h +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | /* | ||
2 | * This is a direct copy of the ev96100.h file, with a global | ||
3 | * search and replace. The numbers are the same. | ||
4 | * | ||
5 | * The reason I'm duplicating this is so that the 64120/96100 | ||
6 | * defines won't be confusing in the source code. | ||
7 | */ | ||
8 | #ifndef _ASM_GT64120_LASAT_GT64120_DEP_H | ||
9 | #define _ASM_GT64120_LASAT_GT64120_DEP_H | ||
10 | |||
11 | /* | ||
12 | * GT64120 config space base address on Lasat 100 | ||
13 | */ | ||
14 | #define GT64120_BASE (KSEG1ADDR(0x14000000)) | ||
15 | |||
16 | /* | ||
17 | * PCI Bus allocation | ||
18 | * | ||
19 | * (Guessing ...) | ||
20 | */ | ||
21 | #define GT_PCI_MEM_BASE 0x12000000UL | ||
22 | #define GT_PCI_MEM_SIZE 0x02000000UL | ||
23 | #define GT_PCI_IO_BASE 0x10000000UL | ||
24 | #define GT_PCI_IO_SIZE 0x02000000UL | ||
25 | #define GT_ISA_IO_BASE PCI_IO_BASE | ||
26 | |||
27 | #endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ | ||
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h new file mode 100644 index 000000000000..7e914777ebc4 --- /dev/null +++ b/include/asm-mips/mach-lemote/dma-coherence.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org> | ||
7 | * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology | ||
8 | * Author: Fuxin Zhang, zhangfx@lemote.com | ||
9 | * | ||
10 | */ | ||
11 | #ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H | ||
12 | #define __ASM_MACH_LEMOTE_DMA_COHERENCE_H | ||
13 | |||
14 | struct device; | ||
15 | |||
16 | static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, | ||
17 | size_t size) | ||
18 | { | ||
19 | return virt_to_phys(addr) | 0x80000000; | ||
20 | } | ||
21 | |||
22 | static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, | ||
23 | struct page *page) | ||
24 | { | ||
25 | return page_to_phys(page) | 0x80000000; | ||
26 | } | ||
27 | |||
28 | static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
29 | { | ||
30 | return dma_addr & 0x7fffffff; | ||
31 | } | ||
32 | |||
33 | static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) | ||
34 | { | ||
35 | } | ||
36 | |||
37 | static inline int plat_device_is_coherent(struct device *dev) | ||
38 | { | ||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | #endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ | ||
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h new file mode 100644 index 000000000000..ed5147e11085 --- /dev/null +++ b/include/asm-mips/mach-lemote/mc146818rtc.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) | ||
7 | * | ||
8 | * RTC routines for PC style attached Dallas chip. | ||
9 | */ | ||
10 | #ifndef __ASM_MACH_LEMOTE_MC146818RTC_H | ||
11 | #define __ASM_MACH_LEMOTE_MC146818RTC_H | ||
12 | |||
13 | #include <linux/io.h> | ||
14 | |||
15 | #define RTC_PORT(x) (0x70 + (x)) | ||
16 | #define RTC_IRQ 8 | ||
17 | |||
18 | static inline unsigned char CMOS_READ(unsigned long addr) | ||
19 | { | ||
20 | outb_p(addr, RTC_PORT(0)); | ||
21 | return inb_p(RTC_PORT(1)); | ||
22 | } | ||
23 | |||
24 | static inline void CMOS_WRITE(unsigned char data, unsigned long addr) | ||
25 | { | ||
26 | outb_p(addr, RTC_PORT(0)); | ||
27 | outb_p(data, RTC_PORT(1)); | ||
28 | } | ||
29 | |||
30 | #define RTC_ALWAYS_BCD 0 | ||
31 | |||
32 | #ifndef mc146818_decode_year | ||
33 | #define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) | ||
34 | #endif | ||
35 | |||
36 | #endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ | ||
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h new file mode 100644 index 000000000000..0b793e7bf67e --- /dev/null +++ b/include/asm-mips/mach-mips/kernel-entry-init.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Chris Dearman (chris@mips.com) | ||
7 | * Copyright (C) 2007 Mips Technologies, Inc. | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H | ||
10 | #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H | ||
11 | |||
12 | .macro kernel_entry_setup | ||
13 | #ifdef CONFIG_MIPS_MT_SMTC | ||
14 | mfc0 t0, CP0_CONFIG | ||
15 | bgez t0, 9f | ||
16 | mfc0 t0, CP0_CONFIG, 1 | ||
17 | bgez t0, 9f | ||
18 | mfc0 t0, CP0_CONFIG, 2 | ||
19 | bgez t0, 9f | ||
20 | mfc0 t0, CP0_CONFIG, 3 | ||
21 | and t0, 1<<2 | ||
22 | bnez t0, 0f | ||
23 | 9: | ||
24 | /* Assume we came from YAMON... */ | ||
25 | PTR_LA v0, 0x9fc00534 /* YAMON print */ | ||
26 | lw v0, (v0) | ||
27 | move a0, zero | ||
28 | PTR_LA a1, nonmt_processor | ||
29 | jal v0 | ||
30 | |||
31 | PTR_LA v0, 0x9fc00520 /* YAMON exit */ | ||
32 | lw v0, (v0) | ||
33 | li a0, 1 | ||
34 | jal v0 | ||
35 | |||
36 | 1: b 1b | ||
37 | |||
38 | __INITDATA | ||
39 | nonmt_processor: | ||
40 | .asciz "SMTC kernel requires the MT ASE to run\n" | ||
41 | __FINIT | ||
42 | 0: | ||
43 | #endif | ||
44 | .endm | ||
45 | |||
46 | /* | ||
47 | * Do SMP slave processor setup necessary before we can safely execute C code. | ||
48 | */ | ||
49 | .macro smp_slave_setup | ||
50 | .endm | ||
51 | |||
52 | #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ | ||
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h index 779b02205737..779b02205737 100644 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h | |||
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h deleted file mode 100644 index 57a12ded0613..000000000000 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2004 MontaVista Software Inc. | ||
7 | * Author: Manish Lachwani, mlachwani@mvista.com | ||
8 | * Copyright (C) 2004 Ralf Baechle | ||
9 | */ | ||
10 | #ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H | ||
11 | #define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H | ||
12 | |||
13 | /* | ||
14 | * Momentum Ocelot-3 is based on Rm7900 processor which | ||
15 | * is based on the E9000 core. | ||
16 | */ | ||
17 | #define cpu_has_watch 1 | ||
18 | #define cpu_has_mips16 0 | ||
19 | #define cpu_has_divec 0 | ||
20 | #define cpu_has_vce 0 | ||
21 | #define cpu_has_cache_cdex_p 0 | ||
22 | #define cpu_has_cache_cdex_s 0 | ||
23 | #define cpu_has_prefetch 1 | ||
24 | #define cpu_has_mcheck 0 | ||
25 | #define cpu_has_ejtag 0 | ||
26 | |||
27 | #define cpu_has_llsc 1 | ||
28 | #define cpu_has_vtag_icache 0 | ||
29 | #define cpu_has_dc_aliases 0 | ||
30 | #define cpu_has_ic_fills_f_dc 0 | ||
31 | #define cpu_has_dsp 0 | ||
32 | #define cpu_icache_snoops_remote_store 0 | ||
33 | |||
34 | #define cpu_has_nofpuex 0 | ||
35 | #define cpu_has_64bits 1 | ||
36 | |||
37 | #define cpu_has_inclusive_pcaches 0 | ||
38 | |||
39 | #define cpu_dcache_line_size() 32 | ||
40 | #define cpu_icache_line_size() 32 | ||
41 | #define cpu_scache_line_size() 32 | ||
42 | |||
43 | #define cpu_has_mips32r1 0 | ||
44 | #define cpu_has_mips32r2 0 | ||
45 | #define cpu_has_mips64r1 0 | ||
46 | #define cpu_has_mips64r2 0 | ||
47 | |||
48 | #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ | ||
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h index 529445dacedb..d2daaed235d5 100644 --- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h +++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003 Ralf Baechle | 6 | * Copyright (C) 2003, 07 Ralf Baechle |
7 | */ | 7 | */ |
8 | #ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H |
@@ -24,6 +24,7 @@ | |||
24 | #define cpu_has_ic_fills_f_dc 0 | 24 | #define cpu_has_ic_fills_f_dc 0 |
25 | 25 | ||
26 | #define cpu_has_dsp 0 | 26 | #define cpu_has_dsp 0 |
27 | #define cpu_has_mipsmt 0 | ||
27 | 28 | ||
28 | #define cpu_has_nofpuex 0 | 29 | #define cpu_has_nofpuex 0 |
29 | #define cpu_has_64bits 0 | 30 | #define cpu_has_64bits 0 |
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h index 7e07283140a3..ccf543363537 100644 --- a/include/asm-mips/mach-rm/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003, 2004 Ralf Baechle | 6 | * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) |
7 | * | 7 | * |
8 | * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. | 8 | * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. |
9 | */ | 9 | */ |
@@ -32,6 +32,8 @@ | |||
32 | #define cpu_has_dsp 0 | 32 | #define cpu_has_dsp 0 |
33 | #define cpu_has_nofpuex 0 | 33 | #define cpu_has_nofpuex 0 |
34 | #define cpu_has_64bits 1 | 34 | #define cpu_has_64bits 1 |
35 | #define cpu_has_mipsmt 0 | ||
36 | #define cpu_has_userlocal 0 | ||
35 | 37 | ||
36 | #define cpu_has_mips32r1 0 | 38 | #define cpu_has_mips32r1 0 |
37 | #define cpu_has_mips32r2 0 | 39 | #define cpu_has_mips32r2 0 |
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index a25968f277a2..63d5bf649af1 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003, 2004 Ralf Baechle | 6 | * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) |
7 | */ | 7 | */ |
8 | #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H |
@@ -26,6 +26,8 @@ | |||
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | 28 | #define cpu_has_dsp 0 |
29 | #define cpu_has_mipsmt 0 | ||
30 | #define cpu_has_userlocal 0 | ||
29 | #define cpu_icache_snoops_remote_store 0 | 31 | #define cpu_icache_snoops_remote_store 0 |
30 | 32 | ||
31 | #define cpu_has_nofpuex 0 | 33 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h new file mode 100644 index 000000000000..1e7beae72229 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/ioremap.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * include/asm-mips/mach-tx49xx/ioremap.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation; either version | ||
7 | * 2 of the License, or (at your option) any later version. | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_TX49XX_IOREMAP_H | ||
10 | #define __ASM_MACH_TX49XX_IOREMAP_H | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | |||
14 | /* | ||
15 | * Allow physical addresses to be fixed up to help peripherals located | ||
16 | * outside the low 32-bit range -- generic pass-through version. | ||
17 | */ | ||
18 | static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) | ||
19 | { | ||
20 | return phys_addr; | ||
21 | } | ||
22 | |||
23 | static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, | ||
24 | unsigned long flags) | ||
25 | { | ||
26 | #ifdef CONFIG_64BIT | ||
27 | #define TXX9_DIRECTMAP_BASE 0xfff000000ul | ||
28 | #else | ||
29 | #define TXX9_DIRECTMAP_BASE 0xff000000ul | ||
30 | #endif | ||
31 | if (offset >= TXX9_DIRECTMAP_BASE && | ||
32 | offset < TXX9_DIRECTMAP_BASE + 0x400000) | ||
33 | return (void __iomem *)(unsigned long)(int)offset; | ||
34 | return NULL; | ||
35 | } | ||
36 | |||
37 | static inline int plat_iounmap(const volatile void __iomem *addr) | ||
38 | { | ||
39 | return (unsigned long)addr >= | ||
40 | (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff); | ||
41 | } | ||
42 | |||
43 | #endif /* __ASM_MACH_TX49XX_IOREMAP_H */ | ||
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 42cebb7ce7a6..470e5e9e10d6 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2003, 2004 Ralf Baechle | 6 | * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) |
7 | */ | 7 | */ |
8 | #ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H | 8 | #ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H |
9 | #define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H | 9 | #define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H |
@@ -26,6 +26,8 @@ | |||
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | 28 | #define cpu_has_dsp 0 |
29 | #define cpu_has_mipsmt 0 | ||
30 | #define cpu_has_userlocal 0 | ||
29 | #define cpu_icache_snoops_remote_store 0 | 31 | #define cpu_icache_snoops_remote_store 0 |
30 | 32 | ||
31 | #define cpu_has_nofpuex 0 | 33 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h index 76add42e486e..93ba1c1b2a4f 100644 --- a/include/asm-mips/mips-boards/atlasint.h +++ b/include/asm-mips/mips-boards/atlasint.h | |||
@@ -28,11 +28,6 @@ | |||
28 | 28 | ||
29 | #include <irq.h> | 29 | #include <irq.h> |
30 | 30 | ||
31 | /* | ||
32 | * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) | ||
33 | */ | ||
34 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE | ||
35 | |||
36 | /* CPU interrupt offsets */ | 31 | /* CPU interrupt offsets */ |
37 | #define MIPSCPU_INT_SW0 0 | 32 | #define MIPSCPU_INT_SW0 0 |
38 | #define MIPSCPU_INT_SW1 1 | 33 | #define MIPSCPU_INT_SW1 1 |
@@ -42,7 +37,6 @@ | |||
42 | #define MIPSCPU_INT_MB2 4 | 37 | #define MIPSCPU_INT_MB2 4 |
43 | #define MIPSCPU_INT_MB3 5 | 38 | #define MIPSCPU_INT_MB3 5 |
44 | #define MIPSCPU_INT_MB4 6 | 39 | #define MIPSCPU_INT_MB4 6 |
45 | #define MIPSCPU_INT_CPUCTR 7 | ||
46 | 40 | ||
47 | /* | 41 | /* |
48 | * Interrupts 8..39 are used for Atlas interrupt controller interrupts | 42 | * Interrupts 8..39 are used for Atlas interrupt controller interrupts |
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index cd7125610100..dc3fc32eedd8 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h | |||
@@ -26,7 +26,12 @@ | |||
26 | /* offsets from base register */ | 26 | /* offsets from base register */ |
27 | #define BONITO(x) (x) | 27 | #define BONITO(x) (x) |
28 | 28 | ||
29 | #else /* !__ASSEMBLY__ */ | 29 | #elif defined(CONFIG_LEMOTE_FULONG) |
30 | |||
31 | #define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) | ||
32 | #define BONITO_IRQ_BASE 32 | ||
33 | |||
34 | #else | ||
30 | 35 | ||
31 | /* | 36 | /* |
32 | * Algorithmics Bonito64 system controller register base. | 37 | * Algorithmics Bonito64 system controller register base. |
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index b98f1658cfd0..c8ebcc3e1267 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h | |||
@@ -73,12 +73,28 @@ | |||
73 | * CoreEMUL with Bonito System Controller is treated like a Core20K | 73 | * CoreEMUL with Bonito System Controller is treated like a Core20K |
74 | * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC | 74 | * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC |
75 | */ | 75 | */ |
76 | #define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 | 76 | #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 |
77 | #define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 | 77 | #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 |
78 | 78 | ||
79 | #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) | 79 | #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) |
80 | 80 | ||
81 | extern unsigned int mips_revision_corid; | 81 | extern int mips_revision_corid; |
82 | |||
83 | #define MIPS_REVISION_SCON_OTHER 0 | ||
84 | #define MIPS_REVISION_SCON_SOCITSC 1 | ||
85 | #define MIPS_REVISION_SCON_SOCITSCP 2 | ||
86 | |||
87 | /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ | ||
88 | #define MIPS_REVISION_SCON_UNKNOWN -1 | ||
89 | #define MIPS_REVISION_SCON_GT64120 -2 | ||
90 | #define MIPS_REVISION_SCON_BONITO -3 | ||
91 | #define MIPS_REVISION_SCON_BRTL -4 | ||
92 | #define MIPS_REVISION_SCON_SOCIT -5 | ||
93 | #define MIPS_REVISION_SCON_ROCIT -6 | ||
94 | |||
95 | #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) | ||
96 | |||
97 | extern int mips_revision_sconid; | ||
82 | 98 | ||
83 | #ifdef CONFIG_PCI | 99 | #ifdef CONFIG_PCI |
84 | extern void mips_pcibios_init(void); | 100 | extern void mips_pcibios_init(void); |
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 9180d6466113..7461318f1cd1 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h | |||
@@ -32,11 +32,6 @@ | |||
32 | */ | 32 | */ |
33 | #define MALTA_INT_BASE 0 | 33 | #define MALTA_INT_BASE 0 |
34 | 34 | ||
35 | /* | ||
36 | * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) | ||
37 | */ | ||
38 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE | ||
39 | |||
40 | /* CPU interrupt offsets */ | 35 | /* CPU interrupt offsets */ |
41 | #define MIPSCPU_INT_SW0 0 | 36 | #define MIPSCPU_INT_SW0 0 |
42 | #define MIPSCPU_INT_SW1 1 | 37 | #define MIPSCPU_INT_SW1 1 |
@@ -49,7 +44,6 @@ | |||
49 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 | 44 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 |
50 | #define MIPSCPU_INT_MB4 6 | 45 | #define MIPSCPU_INT_MB4 6 |
51 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 | 46 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 |
52 | #define MIPSCPU_INT_CPUCTR 7 | ||
53 | 47 | ||
54 | /* | 48 | /* |
55 | * Interrupts 64..127 are used for Soc-it Classic interrupts | 49 | * Interrupts 64..127 are used for Soc-it Classic interrupts |
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h index 8eaefb837b9d..e036b7dd6deb 100644 --- a/include/asm-mips/mips-boards/msc01_pci.h +++ b/include/asm-mips/mips-boards/msc01_pci.h | |||
@@ -208,6 +208,7 @@ | |||
208 | * latter, they should be moved elsewhere. | 208 | * latter, they should be moved elsewhere. |
209 | */ | 209 | */ |
210 | #define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 | 210 | #define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 |
211 | #define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 | ||
211 | 212 | ||
212 | extern unsigned long _pcictrl_msc; | 213 | extern unsigned long _pcictrl_msc; |
213 | 214 | ||
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h index daaf9f98fc63..a9db576a9768 100644 --- a/include/asm-mips/mips-boards/prom.h +++ b/include/asm-mips/mips-boards/prom.h | |||
@@ -33,6 +33,7 @@ extern void prom_meminit(void); | |||
33 | extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); | 33 | extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); |
34 | extern void mips_display_message(const char *str); | 34 | extern void mips_display_message(const char *str); |
35 | extern void mips_display_word(unsigned int num); | 35 | extern void mips_display_word(unsigned int num); |
36 | extern void mips_scroll_message(void); | ||
36 | extern int get_ethernet_addr(char *ethernet_addr); | 37 | extern int get_ethernet_addr(char *ethernet_addr); |
37 | 38 | ||
38 | /* Memory descriptor management. */ | 39 | /* Memory descriptor management. */ |
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h index 4f6a3933699d..e710bae07340 100644 --- a/include/asm-mips/mips-boards/seadint.h +++ b/include/asm-mips/mips-boards/seadint.h | |||
@@ -22,14 +22,7 @@ | |||
22 | 22 | ||
23 | #include <irq.h> | 23 | #include <irq.h> |
24 | 24 | ||
25 | /* | ||
26 | * Interrupts 0..7 are used for SEAD CPU interrupts | ||
27 | */ | ||
28 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE | ||
29 | |||
30 | #define MIPSCPU_INT_UART0 2 | 25 | #define MIPSCPU_INT_UART0 2 |
31 | #define MIPSCPU_INT_UART1 3 | 26 | #define MIPSCPU_INT_UART1 3 |
32 | 27 | ||
33 | #define MIPSCPU_INT_CPUCTR 7 | ||
34 | |||
35 | #endif /* !(_MIPS_SEADINT_H) */ | 28 | #endif /* !(_MIPS_SEADINT_H) */ |
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h index 54f2fe621d69..8ef6db76d5c1 100644 --- a/include/asm-mips/mips-boards/simint.h +++ b/include/asm-mips/mips-boards/simint.h | |||
@@ -21,15 +21,11 @@ | |||
21 | 21 | ||
22 | #define SIM_INT_BASE 0 | 22 | #define SIM_INT_BASE 0 |
23 | #define MIPSCPU_INT_MB0 2 | 23 | #define MIPSCPU_INT_MB0 2 |
24 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE | ||
25 | #define MIPS_CPU_TIMER_IRQ 7 | 24 | #define MIPS_CPU_TIMER_IRQ 7 |
26 | 25 | ||
27 | 26 | ||
28 | #define MIPSCPU_INT_CPUCTR 7 | ||
29 | |||
30 | #define MSC01E_INT_BASE 64 | 27 | #define MSC01E_INT_BASE 64 |
31 | 28 | ||
32 | #define MIPSCPU_INT_CPUCTR 7 | ||
33 | #define MSC01E_INT_CPUCTR 11 | 29 | #define MSC01E_INT_CPUCTR 11 |
34 | 30 | ||
35 | #endif | 31 | #endif |
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9985cb7c16e7..18f47f1e8cd5 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h | |||
@@ -7,7 +7,7 @@ | |||
7 | * Copyright (C) 2000 Silicon Graphics, Inc. | 7 | * Copyright (C) 2000 Silicon Graphics, Inc. |
8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | 8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. |
9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | 9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
10 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki | 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
12 | */ | 12 | */ |
13 | #ifndef _ASM_MIPSREGS_H | 13 | #ifndef _ASM_MIPSREGS_H |
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include <linux/linkage.h> | 16 | #include <linux/linkage.h> |
17 | #include <asm/hazards.h> | 17 | #include <asm/hazards.h> |
18 | #include <asm/war.h> | ||
18 | 19 | ||
19 | /* | 20 | /* |
20 | * The following macros are especially useful for __asm__ | 21 | * The following macros are especially useful for __asm__ |
@@ -533,6 +534,12 @@ | |||
533 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | 534 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) |
534 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | 535 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) |
535 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) | 536 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
537 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) | ||
538 | |||
539 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) | ||
540 | |||
541 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) | ||
542 | |||
536 | 543 | ||
537 | /* | 544 | /* |
538 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | 545 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. |
@@ -700,10 +707,10 @@ do { \ | |||
700 | */ | 707 | */ |
701 | #define __read_64bit_c0_split(source, sel) \ | 708 | #define __read_64bit_c0_split(source, sel) \ |
702 | ({ \ | 709 | ({ \ |
703 | unsigned long long val; \ | 710 | unsigned long long __val; \ |
704 | unsigned long flags; \ | 711 | unsigned long __flags; \ |
705 | \ | 712 | \ |
706 | local_irq_save(flags); \ | 713 | local_irq_save(__flags); \ |
707 | if (sel == 0) \ | 714 | if (sel == 0) \ |
708 | __asm__ __volatile__( \ | 715 | __asm__ __volatile__( \ |
709 | ".set\tmips64\n\t" \ | 716 | ".set\tmips64\n\t" \ |
@@ -712,7 +719,7 @@ do { \ | |||
712 | "dsrl\t%M0, %M0, 32\n\t" \ | 719 | "dsrl\t%M0, %M0, 32\n\t" \ |
713 | "dsrl\t%L0, %L0, 32\n\t" \ | 720 | "dsrl\t%L0, %L0, 32\n\t" \ |
714 | ".set\tmips0" \ | 721 | ".set\tmips0" \ |
715 | : "=r" (val)); \ | 722 | : "=r" (__val)); \ |
716 | else \ | 723 | else \ |
717 | __asm__ __volatile__( \ | 724 | __asm__ __volatile__( \ |
718 | ".set\tmips64\n\t" \ | 725 | ".set\tmips64\n\t" \ |
@@ -721,17 +728,17 @@ do { \ | |||
721 | "dsrl\t%M0, %M0, 32\n\t" \ | 728 | "dsrl\t%M0, %M0, 32\n\t" \ |
722 | "dsrl\t%L0, %L0, 32\n\t" \ | 729 | "dsrl\t%L0, %L0, 32\n\t" \ |
723 | ".set\tmips0" \ | 730 | ".set\tmips0" \ |
724 | : "=r" (val)); \ | 731 | : "=r" (__val)); \ |
725 | local_irq_restore(flags); \ | 732 | local_irq_restore(__flags); \ |
726 | \ | 733 | \ |
727 | val; \ | 734 | __val; \ |
728 | }) | 735 | }) |
729 | 736 | ||
730 | #define __write_64bit_c0_split(source, sel, val) \ | 737 | #define __write_64bit_c0_split(source, sel, val) \ |
731 | do { \ | 738 | do { \ |
732 | unsigned long flags; \ | 739 | unsigned long __flags; \ |
733 | \ | 740 | \ |
734 | local_irq_save(flags); \ | 741 | local_irq_save(__flags); \ |
735 | if (sel == 0) \ | 742 | if (sel == 0) \ |
736 | __asm__ __volatile__( \ | 743 | __asm__ __volatile__( \ |
737 | ".set\tmips64\n\t" \ | 744 | ".set\tmips64\n\t" \ |
@@ -752,7 +759,7 @@ do { \ | |||
752 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | 759 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ |
753 | ".set\tmips0" \ | 760 | ".set\tmips0" \ |
754 | : : "r" (val)); \ | 761 | : : "r" (val)); \ |
755 | local_irq_restore(flags); \ | 762 | local_irq_restore(__flags); \ |
756 | } while (0) | 763 | } while (0) |
757 | 764 | ||
758 | #define read_c0_index() __read_32bit_c0_register($0, 0) | 765 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
@@ -770,6 +777,9 @@ do { \ | |||
770 | #define read_c0_context() __read_ulong_c0_register($4, 0) | 777 | #define read_c0_context() __read_ulong_c0_register($4, 0) |
771 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | 778 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) |
772 | 779 | ||
780 | #define read_c0_userlocal() __read_ulong_c0_register($4, 2) | ||
781 | #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) | ||
782 | |||
773 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) | 783 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
774 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | 784 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) |
775 | 785 | ||
@@ -1292,10 +1302,39 @@ static inline void tlb_probe(void) | |||
1292 | 1302 | ||
1293 | static inline void tlb_read(void) | 1303 | static inline void tlb_read(void) |
1294 | { | 1304 | { |
1305 | #if MIPS34K_MISSED_ITLB_WAR | ||
1306 | int res = 0; | ||
1307 | |||
1308 | __asm__ __volatile__( | ||
1309 | " .set push \n" | ||
1310 | " .set noreorder \n" | ||
1311 | " .set noat \n" | ||
1312 | " .set mips32r2 \n" | ||
1313 | " .word 0x41610001 # dvpe $1 \n" | ||
1314 | " move %0, $1 \n" | ||
1315 | " ehb \n" | ||
1316 | " .set pop \n" | ||
1317 | : "=r" (res)); | ||
1318 | |||
1319 | instruction_hazard(); | ||
1320 | #endif | ||
1321 | |||
1295 | __asm__ __volatile__( | 1322 | __asm__ __volatile__( |
1296 | ".set noreorder\n\t" | 1323 | ".set noreorder\n\t" |
1297 | "tlbr\n\t" | 1324 | "tlbr\n\t" |
1298 | ".set reorder"); | 1325 | ".set reorder"); |
1326 | |||
1327 | #if MIPS34K_MISSED_ITLB_WAR | ||
1328 | if ((res & _ULCAST_(1))) | ||
1329 | __asm__ __volatile__( | ||
1330 | " .set push \n" | ||
1331 | " .set noreorder \n" | ||
1332 | " .set noat \n" | ||
1333 | " .set mips32r2 \n" | ||
1334 | " .word 0x41600021 # evpe \n" | ||
1335 | " ehb \n" | ||
1336 | " .set pop \n"); | ||
1337 | #endif | ||
1299 | } | 1338 | } |
1300 | 1339 | ||
1301 | static inline void tlb_write_indexed(void) | 1340 | static inline void tlb_write_indexed(void) |
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 399d03f1c4fc..de6d09ebbd80 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h | |||
@@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr) | |||
112 | #define MODULE_PROC_FAMILY "RM9000 " | 112 | #define MODULE_PROC_FAMILY "RM9000 " |
113 | #elif defined CONFIG_CPU_SB1 | 113 | #elif defined CONFIG_CPU_SB1 |
114 | #define MODULE_PROC_FAMILY "SB1 " | 114 | #define MODULE_PROC_FAMILY "SB1 " |
115 | #elif defined CONFIG_CPU_LOONGSON2 | ||
116 | #define MODULE_PROC_FAMILY "LOONGSON2 " | ||
115 | #else | 117 | #else |
116 | #error MODULE_PROC_FAMILY undefined for your processor configuration | 118 | #error MODULE_PROC_FAMILY undefined for your processor configuration |
117 | #endif | 119 | #endif |
@@ -122,6 +124,13 @@ search_module_dbetables(unsigned long addr) | |||
122 | #define MODULE_KERNEL_TYPE "64BIT " | 124 | #define MODULE_KERNEL_TYPE "64BIT " |
123 | #endif | 125 | #endif |
124 | 126 | ||
125 | #define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE | 127 | #ifdef CONFIG_MIPS_MT_SMTC |
128 | #define MODULE_KERNEL_SMTC "MT_SMTC " | ||
129 | #else | ||
130 | #define MODULE_KERNEL_SMTC "" | ||
131 | #endif | ||
132 | |||
133 | #define MODULE_ARCH_VERMAGIC \ | ||
134 | MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC | ||
126 | 135 | ||
127 | #endif /* _ASM_MODULE_H */ | 136 | #endif /* _ASM_MODULE_H */ |
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h deleted file mode 100644 index c3ca959aa4d9..000000000000 --- a/include/asm-mips/nile4.h +++ /dev/null | |||
@@ -1,310 +0,0 @@ | |||
1 | /* | ||
2 | * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | * | ||
7 | * This file is based on the following documentation: | ||
8 | * | ||
9 | * NEC Vrc 5074 System Controller Data Sheet, June 1998 | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_NILE4_H | ||
13 | #define _ASM_NILE4_H | ||
14 | |||
15 | #define NILE4_BASE 0xbfa00000 | ||
16 | #define NILE4_SIZE 0x00200000 /* 2 MB */ | ||
17 | |||
18 | |||
19 | /* | ||
20 | * Physical Device Address Registers (PDARs) | ||
21 | */ | ||
22 | |||
23 | #define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ | ||
24 | #define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ | ||
25 | #define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ | ||
26 | #define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ | ||
27 | #define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ | ||
28 | #define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ | ||
29 | #define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ | ||
30 | #define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ | ||
31 | #define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ | ||
32 | #define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ | ||
33 | #define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ | ||
34 | #define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ | ||
35 | /* [R/W] */ | ||
36 | #define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ | ||
37 | |||
38 | |||
39 | /* | ||
40 | * CPU Interface Registers | ||
41 | */ | ||
42 | |||
43 | #define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ | ||
44 | #define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ | ||
45 | #define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ | ||
46 | #define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ | ||
47 | /* Enable [R/W] */ | ||
48 | #define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ | ||
49 | #define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ | ||
50 | |||
51 | |||
52 | /* | ||
53 | * Memory-Interface Registers | ||
54 | */ | ||
55 | |||
56 | #define NILE4_MEMCTRL 0x00C0 /* Memory Control */ | ||
57 | #define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ | ||
58 | #define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ | ||
59 | |||
60 | |||
61 | /* | ||
62 | * PCI-Bus Registers | ||
63 | */ | ||
64 | |||
65 | #define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ | ||
66 | #define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ | ||
67 | #define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ | ||
68 | #define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ | ||
69 | #define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ | ||
70 | |||
71 | |||
72 | /* | ||
73 | * Local-Bus Registers | ||
74 | */ | ||
75 | |||
76 | #define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ | ||
77 | #define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ | ||
78 | #define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ | ||
79 | #define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ | ||
80 | #define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ | ||
81 | #define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ | ||
82 | #define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ | ||
83 | #define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ | ||
84 | #define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ | ||
85 | /* Enables [R/W] */ | ||
86 | #define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ | ||
87 | #define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ | ||
88 | |||
89 | |||
90 | /* | ||
91 | * DMA Registers | ||
92 | */ | ||
93 | |||
94 | #define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ | ||
95 | #define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ | ||
96 | #define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ | ||
97 | #define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ | ||
98 | #define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ | ||
99 | #define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ | ||
100 | |||
101 | |||
102 | /* | ||
103 | * Timer Registers | ||
104 | */ | ||
105 | |||
106 | #define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ | ||
107 | #define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ | ||
108 | #define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ | ||
109 | #define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ | ||
110 | #define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ | ||
111 | #define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ | ||
112 | #define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ | ||
113 | #define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ | ||
114 | |||
115 | |||
116 | /* | ||
117 | * PCI Configuration Space Registers | ||
118 | */ | ||
119 | |||
120 | #define NILE4_PCI_BASE 0x0200 | ||
121 | |||
122 | #define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ | ||
123 | #define NILE4_DID 0x0202 /* PCI Device ID [R] */ | ||
124 | #define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ | ||
125 | #define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ | ||
126 | #define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ | ||
127 | #define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ | ||
128 | #define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ | ||
129 | #define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ | ||
130 | #define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ | ||
131 | #define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ | ||
132 | #define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ | ||
133 | #define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ | ||
134 | #define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ | ||
135 | #define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ | ||
136 | /* (unimplemented) */ | ||
137 | #define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ | ||
138 | #define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ | ||
139 | #define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ | ||
140 | /* (unimplemented) */ | ||
141 | #define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ | ||
142 | #define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ | ||
143 | #define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ | ||
144 | #define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ | ||
145 | #define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ | ||
146 | #define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ | ||
147 | #define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ | ||
148 | #define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ | ||
149 | #define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ | ||
150 | #define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ | ||
151 | #define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ | ||
152 | #define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ | ||
153 | |||
154 | |||
155 | /* | ||
156 | * Serial-Port Registers | ||
157 | */ | ||
158 | |||
159 | #define NILE4_UART_BASE 0x0300 | ||
160 | |||
161 | #define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ | ||
162 | #define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ | ||
163 | #define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ | ||
164 | #define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ | ||
165 | #define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ | ||
166 | #define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ | ||
167 | #define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ | ||
168 | #define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ | ||
169 | #define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ | ||
170 | #define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ | ||
171 | #define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ | ||
172 | #define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ | ||
173 | |||
174 | #define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ | ||
175 | |||
176 | |||
177 | /* | ||
178 | * Interrupt Lines | ||
179 | */ | ||
180 | |||
181 | #define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ | ||
182 | #define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ | ||
183 | #define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ | ||
184 | #define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ | ||
185 | #define NILE4_INT_UART 4 /* UART Interrupt */ | ||
186 | #define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ | ||
187 | #define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ | ||
188 | #define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ | ||
189 | #define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ | ||
190 | #define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ | ||
191 | #define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ | ||
192 | #define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ | ||
193 | #define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ | ||
194 | #define NILE4_INT_RESV 13 /* Reserved */ | ||
195 | #define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ | ||
196 | #define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ | ||
197 | |||
198 | |||
199 | /* | ||
200 | * Nile 4 Register Access | ||
201 | */ | ||
202 | |||
203 | static inline void nile4_sync(void) | ||
204 | { | ||
205 | volatile u32 *p = (volatile u32 *)0xbfc00000; | ||
206 | (void)(*p); | ||
207 | } | ||
208 | |||
209 | static inline void nile4_out32(u32 offset, u32 val) | ||
210 | { | ||
211 | *(volatile u32 *)(NILE4_BASE+offset) = val; | ||
212 | nile4_sync(); | ||
213 | } | ||
214 | |||
215 | static inline u32 nile4_in32(u32 offset) | ||
216 | { | ||
217 | u32 val = *(volatile u32 *)(NILE4_BASE+offset); | ||
218 | nile4_sync(); | ||
219 | return val; | ||
220 | } | ||
221 | |||
222 | static inline void nile4_out16(u32 offset, u16 val) | ||
223 | { | ||
224 | *(volatile u16 *)(NILE4_BASE+offset) = val; | ||
225 | nile4_sync(); | ||
226 | } | ||
227 | |||
228 | static inline u16 nile4_in16(u32 offset) | ||
229 | { | ||
230 | u16 val = *(volatile u16 *)(NILE4_BASE+offset); | ||
231 | nile4_sync(); | ||
232 | return val; | ||
233 | } | ||
234 | |||
235 | static inline void nile4_out8(u32 offset, u8 val) | ||
236 | { | ||
237 | *(volatile u8 *)(NILE4_BASE+offset) = val; | ||
238 | nile4_sync(); | ||
239 | } | ||
240 | |||
241 | static inline u8 nile4_in8(u32 offset) | ||
242 | { | ||
243 | u8 val = *(volatile u8 *)(NILE4_BASE+offset); | ||
244 | nile4_sync(); | ||
245 | return val; | ||
246 | } | ||
247 | |||
248 | |||
249 | /* | ||
250 | * Physical Device Address Registers | ||
251 | */ | ||
252 | |||
253 | extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, | ||
254 | int on_memory_bus, int visible); | ||
255 | |||
256 | |||
257 | /* | ||
258 | * PCI Master Registers | ||
259 | */ | ||
260 | |||
261 | #define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ | ||
262 | #define NILE4_PCICMD_IO 1 /* PCI I/O Space */ | ||
263 | #define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ | ||
264 | #define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ | ||
265 | |||
266 | |||
267 | /* | ||
268 | * PCI Address Spaces | ||
269 | * | ||
270 | * Note that these are multiplexed using PCIINIT[01]! | ||
271 | */ | ||
272 | |||
273 | #define NILE4_PCI_IO_BASE 0xa6000000 | ||
274 | #define NILE4_PCI_MEM_BASE 0xa8000000 | ||
275 | #define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE | ||
276 | #define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE | ||
277 | |||
278 | |||
279 | extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); | ||
280 | |||
281 | |||
282 | /* | ||
283 | * Interrupt Programming | ||
284 | */ | ||
285 | |||
286 | #define NUM_I8259_INTERRUPTS 16 | ||
287 | #define NUM_NILE4_INTERRUPTS 16 | ||
288 | |||
289 | #define IRQ_I8259_CASCADE NILE4_INT_INTE | ||
290 | #define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) | ||
291 | #define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) | ||
292 | #define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) | ||
293 | |||
294 | extern void nile4_map_irq(int nile4_irq, int cpu_irq); | ||
295 | extern void nile4_map_irq_all(int cpu_irq); | ||
296 | extern void nile4_enable_irq(unsigned int nile4_irq); | ||
297 | extern void nile4_disable_irq(unsigned int nile4_irq); | ||
298 | extern void nile4_disable_irq_all(void); | ||
299 | extern u16 nile4_get_irq_stat(int cpu_irq); | ||
300 | extern void nile4_enable_irq_output(int cpu_irq); | ||
301 | extern void nile4_disable_irq_output(int cpu_irq); | ||
302 | extern void nile4_set_pci_irq_polarity(int pci_irq, int high); | ||
303 | extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); | ||
304 | extern void nile4_clear_irq(int nile4_irq); | ||
305 | extern void nile4_clear_irq_mask(u32 mask); | ||
306 | extern u8 nile4_i8259_iack(void); | ||
307 | extern void nile4_dump_irq_status(void); /* Debug */ | ||
308 | |||
309 | #endif | ||
310 | |||
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 5c3239dad0f2..b92dd8c760da 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h | |||
@@ -34,12 +34,8 @@ | |||
34 | 34 | ||
35 | #ifndef __ASSEMBLY__ | 35 | #ifndef __ASSEMBLY__ |
36 | 36 | ||
37 | /* | 37 | #include <linux/pfn.h> |
38 | * This gives the physical RAM offset. | 38 | #include <asm/io.h> |
39 | */ | ||
40 | #ifndef PHYS_OFFSET | ||
41 | #define PHYS_OFFSET 0UL | ||
42 | #endif | ||
43 | 39 | ||
44 | /* | 40 | /* |
45 | * It's normally defined only for FLATMEM config but it's | 41 | * It's normally defined only for FLATMEM config but it's |
@@ -48,9 +44,6 @@ | |||
48 | */ | 44 | */ |
49 | #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) | 45 | #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) |
50 | 46 | ||
51 | #include <linux/pfn.h> | ||
52 | #include <asm/io.h> | ||
53 | |||
54 | extern void clear_page(void * page); | 47 | extern void clear_page(void * page); |
55 | extern void copy_page(void * to, void * from); | 48 | extern void copy_page(void * to, void * from); |
56 | 49 | ||
@@ -150,11 +143,15 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
150 | * __pa()/__va() should be used only during mem init. | 143 | * __pa()/__va() should be used only during mem init. |
151 | */ | 144 | */ |
152 | #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) | 145 | #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) |
153 | #define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) | 146 | #define __pa(x) \ |
147 | ({ \ | ||
148 | unsigned long __x = (unsigned long)(x); \ | ||
149 | __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \ | ||
150 | }) | ||
154 | #else | 151 | #else |
155 | #define __pa_page_offset(x) PAGE_OFFSET | 152 | #define __pa(x) \ |
153 | ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) | ||
156 | #endif | 154 | #endif |
157 | #define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET) | ||
158 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) | 155 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) |
159 | #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) | 156 | #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) |
160 | 157 | ||
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 3eea3ba0fca5..4fcc185cb2d1 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h | |||
@@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose); | |||
56 | /* | 56 | /* |
57 | * board supplied pci irq fixup routine | 57 | * board supplied pci irq fixup routine |
58 | */ | 58 | */ |
59 | extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); | 59 | extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); |
60 | 60 | ||
61 | 61 | ||
62 | /* Can be used to override the logic in pci_scan_bus for skipping | 62 | /* Can be used to override the logic in pci_scan_bus for skipping |
@@ -121,20 +121,6 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; | |||
121 | 121 | ||
122 | #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ | 122 | #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ |
123 | 123 | ||
124 | /* This is always fine. */ | ||
125 | #define pci_dac_dma_supported(pci_dev, mask) (1) | ||
126 | |||
127 | extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, | ||
128 | struct page *page, unsigned long offset, int direction); | ||
129 | extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev, | ||
130 | dma64_addr_t dma_addr); | ||
131 | extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, | ||
132 | dma64_addr_t dma_addr); | ||
133 | extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, | ||
134 | dma64_addr_t dma_addr, size_t len, int direction); | ||
135 | extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, | ||
136 | dma64_addr_t dma_addr, size_t len, int direction); | ||
137 | |||
138 | #ifdef CONFIG_PCI | 124 | #ifdef CONFIG_PCI |
139 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | 125 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
140 | enum pci_dma_burst_strategy *strat, | 126 | enum pci_dma_burst_strategy *strat, |
@@ -181,10 +167,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) | |||
181 | /* implement the pci_ DMA API in terms of the generic device dma_ one */ | 167 | /* implement the pci_ DMA API in terms of the generic device dma_ one */ |
182 | #include <asm-generic/pci-dma-compat.h> | 168 | #include <asm-generic/pci-dma-compat.h> |
183 | 169 | ||
184 | static inline void pcibios_add_platform_entries(struct pci_dev *dev) | ||
185 | { | ||
186 | } | ||
187 | |||
188 | /* Do platform specific device initialization at pci_enable_device() time */ | 170 | /* Do platform specific device initialization at pci_enable_device() time */ |
189 | extern int pcibios_plat_dev_init(struct pci_dev *dev); | 171 | extern int pcibios_plat_dev_init(struct pci_dev *dev); |
190 | 172 | ||
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 27d77d981937..2e2d70d13ff6 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h | |||
@@ -178,9 +178,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |||
178 | * The following only work if pte_present() is true. | 178 | * The following only work if pte_present() is true. |
179 | * Undefined behaviour if not.. | 179 | * Undefined behaviour if not.. |
180 | */ | 180 | */ |
181 | static inline int pte_user(pte_t pte) { BUG(); return 0; } | ||
182 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) | 181 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) |
183 | static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; } | ||
184 | static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } | 182 | static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } |
185 | static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } | 183 | static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } |
186 | static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } | 184 | static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } |
@@ -193,13 +191,6 @@ static inline pte_t pte_wrprotect(pte_t pte) | |||
193 | return pte; | 191 | return pte; |
194 | } | 192 | } |
195 | 193 | ||
196 | static inline pte_t pte_rdprotect(pte_t pte) | ||
197 | { | ||
198 | pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); | ||
199 | pte.pte_high &= ~_PAGE_SILENT_READ; | ||
200 | return pte; | ||
201 | } | ||
202 | |||
203 | static inline pte_t pte_mkclean(pte_t pte) | 194 | static inline pte_t pte_mkclean(pte_t pte) |
204 | { | 195 | { |
205 | pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); | 196 | pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); |
@@ -224,16 +215,6 @@ static inline pte_t pte_mkwrite(pte_t pte) | |||
224 | return pte; | 215 | return pte; |
225 | } | 216 | } |
226 | 217 | ||
227 | static inline pte_t pte_mkread(pte_t pte) | ||
228 | { | ||
229 | pte.pte_low |= _PAGE_READ; | ||
230 | if (pte.pte_low & _PAGE_ACCESSED) { | ||
231 | pte.pte_low |= _PAGE_SILENT_READ; | ||
232 | pte.pte_high |= _PAGE_SILENT_READ; | ||
233 | } | ||
234 | return pte; | ||
235 | } | ||
236 | |||
237 | static inline pte_t pte_mkdirty(pte_t pte) | 218 | static inline pte_t pte_mkdirty(pte_t pte) |
238 | { | 219 | { |
239 | pte.pte_low |= _PAGE_MODIFIED; | 220 | pte.pte_low |= _PAGE_MODIFIED; |
@@ -253,7 +234,6 @@ static inline pte_t pte_mkyoung(pte_t pte) | |||
253 | return pte; | 234 | return pte; |
254 | } | 235 | } |
255 | #else | 236 | #else |
256 | static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } | ||
257 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } | 237 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } |
258 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } | 238 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } |
259 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | 239 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } |
@@ -265,12 +245,6 @@ static inline pte_t pte_wrprotect(pte_t pte) | |||
265 | return pte; | 245 | return pte; |
266 | } | 246 | } |
267 | 247 | ||
268 | static inline pte_t pte_rdprotect(pte_t pte) | ||
269 | { | ||
270 | pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); | ||
271 | return pte; | ||
272 | } | ||
273 | |||
274 | static inline pte_t pte_mkclean(pte_t pte) | 248 | static inline pte_t pte_mkclean(pte_t pte) |
275 | { | 249 | { |
276 | pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); | 250 | pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); |
@@ -291,14 +265,6 @@ static inline pte_t pte_mkwrite(pte_t pte) | |||
291 | return pte; | 265 | return pte; |
292 | } | 266 | } |
293 | 267 | ||
294 | static inline pte_t pte_mkread(pte_t pte) | ||
295 | { | ||
296 | pte_val(pte) |= _PAGE_READ; | ||
297 | if (pte_val(pte) & _PAGE_ACCESSED) | ||
298 | pte_val(pte) |= _PAGE_SILENT_READ; | ||
299 | return pte; | ||
300 | } | ||
301 | |||
302 | static inline pte_t pte_mkdirty(pte_t pte) | 268 | static inline pte_t pte_mkdirty(pte_t pte) |
303 | { | 269 | { |
304 | pte_val(pte) |= _PAGE_MODIFIED; | 270 | pte_val(pte) |= _PAGE_MODIFIED; |
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h new file mode 100644 index 000000000000..c84bcf9570b1 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h | |||
@@ -0,0 +1,151 @@ | |||
1 | /* | ||
2 | * Defines for the MSP interrupt controller. | ||
3 | * | ||
4 | * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. | ||
5 | * Author: Carsten Langgaard, carstenl@mips.com | ||
6 | * | ||
7 | * ######################################################################## | ||
8 | * | ||
9 | * This program is free software; you can distribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License (Version 2) as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
21 | * | ||
22 | * ######################################################################## | ||
23 | */ | ||
24 | |||
25 | #ifndef _MSP_CIC_INT_H | ||
26 | #define _MSP_CIC_INT_H | ||
27 | |||
28 | /* | ||
29 | * The PMC-Sierra CIC interrupts are all centrally managed by the | ||
30 | * CIC sub-system. | ||
31 | * We attempt to keep the interrupt numbers as consistent as possible | ||
32 | * across all of the MSP devices, but some differences will creep in ... | ||
33 | * The interrupts which are directly forwarded to the MIPS core interrupts | ||
34 | * are assigned interrupts in the range 0-7, interrupts cascaded through | ||
35 | * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4 | ||
36 | * (MSP_INT_CIC). Currently we don't really distinguish between VPE1 | ||
37 | * and VPE0 (or thread contexts for that matter). Will have to fix. | ||
38 | * The PER interrupts are assigned interrupts in the range 40-71. | ||
39 | */ | ||
40 | |||
41 | |||
42 | /* | ||
43 | * IRQs directly forwarded to the CPU | ||
44 | */ | ||
45 | #define MSP_MIPS_INTBASE 0 | ||
46 | #define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ | ||
47 | #define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ | ||
48 | #define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ | ||
49 | #define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ | ||
50 | #define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ | ||
51 | #define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ | ||
52 | #define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ | ||
53 | #define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ | ||
54 | |||
55 | /* | ||
56 | * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) | ||
57 | * These defines should be tied to the register definitions for the CIC | ||
58 | * interrupt routine. For now, just use hard-coded values. | ||
59 | */ | ||
60 | #define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) | ||
61 | #define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) | ||
62 | /* External interrupt 0 */ | ||
63 | #define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) | ||
64 | /* External interrupt 1 */ | ||
65 | #define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) | ||
66 | /* External interrupt 2 */ | ||
67 | #define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) | ||
68 | /* External interrupt 3 */ | ||
69 | #define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) | ||
70 | /* CPU interface interrupt */ | ||
71 | #define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) | ||
72 | /* External interrupt 4 */ | ||
73 | #define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) | ||
74 | /* Cascaded IRQ for USB */ | ||
75 | #define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) | ||
76 | /* Sec engine mailbox IRQ */ | ||
77 | #define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) | ||
78 | /* External interrupt 5 */ | ||
79 | #define MSP_INT_TDM (MSP_CIC_INTBASE + 9) | ||
80 | /* TDM interrupt */ | ||
81 | #define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) | ||
82 | /* Cascaded IRQ for MAC 0 */ | ||
83 | #define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) | ||
84 | /* Cascaded IRQ for MAC 1 */ | ||
85 | #define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) | ||
86 | /* Cascaded IRQ for sec engine */ | ||
87 | #define MSP_INT_PER (MSP_CIC_INTBASE + 13) | ||
88 | /* Peripheral interrupt */ | ||
89 | #define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) | ||
90 | /* SLP timer 0 */ | ||
91 | #define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) | ||
92 | /* SLP timer 1 */ | ||
93 | #define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) | ||
94 | /* SLP timer 2 */ | ||
95 | #define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) | ||
96 | /* VPE0 MIPS timer */ | ||
97 | #define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) | ||
98 | /* Block Copy */ | ||
99 | #define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) | ||
100 | /* UART 0 */ | ||
101 | #define MSP_INT_PCI (MSP_CIC_INTBASE + 20) | ||
102 | /* PCI subsystem */ | ||
103 | #define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) | ||
104 | /* External interrupt 5 */ | ||
105 | #define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) | ||
106 | /* PCI Message Signal */ | ||
107 | #define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) | ||
108 | /* Cascaded ADSL2+ SAR IRQ */ | ||
109 | #define MSP_INT_DSL (MSP_CIC_INTBASE + 24) | ||
110 | /* ADSL2+ IRQ */ | ||
111 | #define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) | ||
112 | /* SLP error condition */ | ||
113 | #define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) | ||
114 | /* VPE1 MIPS timer */ | ||
115 | #define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) | ||
116 | /* VPE0 Performance counter */ | ||
117 | #define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) | ||
118 | /* VPE1 Performance counter */ | ||
119 | #define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) | ||
120 | /* External interrupt 5 */ | ||
121 | #define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) | ||
122 | /* VPE0 Software interrupt */ | ||
123 | #define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) | ||
124 | /* VPE0 Software interrupt */ | ||
125 | |||
126 | /* | ||
127 | * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) | ||
128 | */ | ||
129 | #define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) | ||
130 | /* Reserved 0-1 */ | ||
131 | #define MSP_INT_UART1 (MSP_PER_INTBASE + 2) | ||
132 | /* UART 1 */ | ||
133 | /* Reserved 3-5 */ | ||
134 | #define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) | ||
135 | /* 2-wire */ | ||
136 | #define MSP_INT_TM0 (MSP_PER_INTBASE + 7) | ||
137 | /* Peripheral timer block out 0 */ | ||
138 | #define MSP_INT_TM1 (MSP_PER_INTBASE + 8) | ||
139 | /* Peripheral timer block out 1 */ | ||
140 | /* Reserved 9 */ | ||
141 | #define MSP_INT_SPRX (MSP_PER_INTBASE + 10) | ||
142 | /* SPI RX complete */ | ||
143 | #define MSP_INT_SPTX (MSP_PER_INTBASE + 11) | ||
144 | /* SPI TX complete */ | ||
145 | #define MSP_INT_GPIO (MSP_PER_INTBASE + 12) | ||
146 | /* GPIO */ | ||
147 | #define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) | ||
148 | /* Peripheral error */ | ||
149 | /* Reserved 14-31 */ | ||
150 | |||
151 | #endif /* !_MSP_CIC_INT_H */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h new file mode 100644 index 000000000000..1d9f05474820 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * Defines for the MSP interrupt handlers. | ||
3 | * | ||
4 | * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved. | ||
5 | * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com | ||
6 | * | ||
7 | * ######################################################################## | ||
8 | * | ||
9 | * This program is free software; you can distribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License (Version 2) as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
21 | * | ||
22 | * ######################################################################## | ||
23 | */ | ||
24 | |||
25 | #ifndef _MSP_INT_H | ||
26 | #define _MSP_INT_H | ||
27 | |||
28 | /* | ||
29 | * The PMC-Sierra MSP product line has at least two different interrupt | ||
30 | * controllers, the SLP register based scheme and the CIC interrupt | ||
31 | * controller block mechanism. This file distinguishes between them | ||
32 | * so that devices see a uniform interface. | ||
33 | */ | ||
34 | |||
35 | #if defined(CONFIG_IRQ_MSP_SLP) | ||
36 | #include "msp_slp_int.h" | ||
37 | #elif defined(CONFIG_IRQ_MSP_CIC) | ||
38 | #include "msp_cic_int.h" | ||
39 | #else | ||
40 | #error "What sort of interrupt controller does *your* MSP have?" | ||
41 | #endif | ||
42 | |||
43 | #endif /* !_MSP_INT_H */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h new file mode 100644 index 000000000000..415606903617 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h | |||
@@ -0,0 +1,205 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2000-2006 PMC-Sierra INC. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it | ||
5 | * and/or modify it under the terms of the GNU General | ||
6 | * Public License as published by the Free Software | ||
7 | * Foundation; either version 2 of the License, or (at your | ||
8 | * option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be | ||
11 | * useful, but WITHOUT ANY WARRANTY; without even the implied | ||
12 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | ||
13 | * PURPOSE. See the GNU General Public License for more | ||
14 | * details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public | ||
17 | * License along with this program; if not, write to the Free | ||
18 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA | ||
19 | * 02139, USA. | ||
20 | * | ||
21 | * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND | ||
22 | * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS | ||
23 | * SOFTWARE. | ||
24 | */ | ||
25 | |||
26 | #ifndef _MSP_PCI_H_ | ||
27 | #define _MSP_PCI_H_ | ||
28 | |||
29 | #define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) | ||
30 | |||
31 | /* | ||
32 | * It is convenient to program the OATRAN register so that | ||
33 | * Athena virtual address space and PCI address space are | ||
34 | * the same. This is not a requirement, just a convenience. | ||
35 | * | ||
36 | * The only hard restrictions on the value of OATRAN is that | ||
37 | * OATRAN must not be programmed to allow translated memory | ||
38 | * addresses to fall within the lowest 512MB of | ||
39 | * PCI address space. This region is hardcoded | ||
40 | * for use as Athena PCI Host Controller target | ||
41 | * access memory space to the Athena's SDRAM. | ||
42 | * | ||
43 | * Note that OATRAN applies only to memory accesses, not | ||
44 | * to I/O accesses. | ||
45 | * | ||
46 | * To program OATRAN to make Athena virtual address space | ||
47 | * and PCI address space have the same values, OATRAN | ||
48 | * is to be programmed to 0xB8000000. The top seven | ||
49 | * bits of the value mimic the seven bits clipped off | ||
50 | * by the PCI Host controller. | ||
51 | * | ||
52 | * With OATRAN at the said value, when the CPU does | ||
53 | * an access to its virtual address at, say 0xB900_5000, | ||
54 | * the address appearing on the PCI bus will be | ||
55 | * 0xB900_5000. | ||
56 | * - Michael Penner | ||
57 | */ | ||
58 | #define MSP_PCI_OATRAN 0xB8000000UL | ||
59 | |||
60 | #define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL) | ||
61 | #define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000) | ||
62 | #define MSP_PCI_SPACE_END \ | ||
63 | (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1) | ||
64 | #define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL) | ||
65 | #define MSP_PCI_IOSPACE_SIZE 0x1000 | ||
66 | #define MSP_PCI_IOSPACE_END \ | ||
67 | (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1) | ||
68 | |||
69 | /* IRQ for PCI status interrupts */ | ||
70 | #define PCI_STAT_IRQ 20 | ||
71 | |||
72 | #define QFLUSH_REG_1 0xB7F40000 | ||
73 | |||
74 | typedef volatile unsigned int pcireg; | ||
75 | typedef void * volatile ppcireg; | ||
76 | |||
77 | struct pci_block_copy | ||
78 | { | ||
79 | pcireg unused1; /* +0x00 */ | ||
80 | pcireg unused2; /* +0x04 */ | ||
81 | ppcireg unused3; /* +0x08 */ | ||
82 | ppcireg unused4; /* +0x0C */ | ||
83 | pcireg unused5; /* +0x10 */ | ||
84 | pcireg unused6; /* +0x14 */ | ||
85 | pcireg unused7; /* +0x18 */ | ||
86 | ppcireg unused8; /* +0x1C */ | ||
87 | ppcireg unused9; /* +0x20 */ | ||
88 | pcireg unusedA; /* +0x24 */ | ||
89 | ppcireg unusedB; /* +0x28 */ | ||
90 | ppcireg unusedC; /* +0x2C */ | ||
91 | }; | ||
92 | |||
93 | enum | ||
94 | { | ||
95 | config_device_vendor, /* 0 */ | ||
96 | config_status_command, /* 1 */ | ||
97 | config_class_revision, /* 2 */ | ||
98 | config_BIST_header_latency_cache, /* 3 */ | ||
99 | config_BAR0, /* 4 */ | ||
100 | config_BAR1, /* 5 */ | ||
101 | config_BAR2, /* 6 */ | ||
102 | config_not_used7, /* 7 */ | ||
103 | config_not_used8, /* 8 */ | ||
104 | config_not_used9, /* 9 */ | ||
105 | config_CIS, /* 10 */ | ||
106 | config_subsystem, /* 11 */ | ||
107 | config_not_used12, /* 12 */ | ||
108 | config_capabilities, /* 13 */ | ||
109 | config_not_used14, /* 14 */ | ||
110 | config_lat_grant_irq, /* 15 */ | ||
111 | config_message_control,/* 16 */ | ||
112 | config_message_addr, /* 17 */ | ||
113 | config_message_data, /* 18 */ | ||
114 | config_VPD_addr, /* 19 */ | ||
115 | config_VPD_data, /* 20 */ | ||
116 | config_maxregs /* 21 - number of registers */ | ||
117 | }; | ||
118 | |||
119 | struct msp_pci_regs | ||
120 | { | ||
121 | pcireg hop_unused_00; /* +0x00 */ | ||
122 | pcireg hop_unused_04; /* +0x04 */ | ||
123 | pcireg hop_unused_08; /* +0x08 */ | ||
124 | pcireg hop_unused_0C; /* +0x0C */ | ||
125 | pcireg hop_unused_10; /* +0x10 */ | ||
126 | pcireg hop_unused_14; /* +0x14 */ | ||
127 | pcireg hop_unused_18; /* +0x18 */ | ||
128 | pcireg hop_unused_1C; /* +0x1C */ | ||
129 | pcireg hop_unused_20; /* +0x20 */ | ||
130 | pcireg hop_unused_24; /* +0x24 */ | ||
131 | pcireg hop_unused_28; /* +0x28 */ | ||
132 | pcireg hop_unused_2C; /* +0x2C */ | ||
133 | pcireg hop_unused_30; /* +0x30 */ | ||
134 | pcireg hop_unused_34; /* +0x34 */ | ||
135 | pcireg if_control; /* +0x38 */ | ||
136 | pcireg oatran; /* +0x3C */ | ||
137 | pcireg reset_ctl; /* +0x40 */ | ||
138 | pcireg config_addr; /* +0x44 */ | ||
139 | pcireg hop_unused_48; /* +0x48 */ | ||
140 | pcireg msg_signaled_int_status; /* +0x4C */ | ||
141 | pcireg msg_signaled_int_mask; /* +0x50 */ | ||
142 | pcireg if_status; /* +0x54 */ | ||
143 | pcireg if_mask; /* +0x58 */ | ||
144 | pcireg hop_unused_5C; /* +0x5C */ | ||
145 | pcireg hop_unused_60; /* +0x60 */ | ||
146 | pcireg hop_unused_64; /* +0x64 */ | ||
147 | pcireg hop_unused_68; /* +0x68 */ | ||
148 | pcireg hop_unused_6C; /* +0x6C */ | ||
149 | pcireg hop_unused_70; /* +0x70 */ | ||
150 | |||
151 | struct pci_block_copy pci_bc[2] __attribute__((aligned(64))); | ||
152 | |||
153 | pcireg error_hdr1; /* +0xE0 */ | ||
154 | pcireg error_hdr2; /* +0xE4 */ | ||
155 | |||
156 | pcireg config[config_maxregs] __attribute__((aligned(256))); | ||
157 | |||
158 | }; | ||
159 | |||
160 | #define BPCI_CFGADDR_BUSNUM_SHF 16 | ||
161 | #define BPCI_CFGADDR_FUNCTNUM_SHF 8 | ||
162 | #define BPCI_CFGADDR_REGNUM_SHF 2 | ||
163 | #define BPCI_CFGADDR_ENABLE (1<<31) | ||
164 | |||
165 | #define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */ | ||
166 | #define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */ | ||
167 | #define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */ | ||
168 | #define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */ | ||
169 | #define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */ | ||
170 | #define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */ | ||
171 | #define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */ | ||
172 | |||
173 | #define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */ | ||
174 | #define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */ | ||
175 | #define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */ | ||
176 | #define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */ | ||
177 | #define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */ | ||
178 | #define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */ | ||
179 | #define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */ | ||
180 | #define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */ | ||
181 | #define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */ | ||
182 | #define BPCI_IFSTATUS_SER (1<<19) /* System error */ | ||
183 | #define BPCI_IFSTATUS_PER (1<<20) /* Parity error */ | ||
184 | #define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */ | ||
185 | #define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */ | ||
186 | #define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */ | ||
187 | #define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */ | ||
188 | #define BPCI_IFSTATUS_TA (1<<28) /* Target abort */ | ||
189 | #define BPCI_IFSTATUS_MA (1<<29) /* Master abort */ | ||
190 | #define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */ | ||
191 | #define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */ | ||
192 | |||
193 | #define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ | ||
194 | #define BPCI_RESETCTL_RT (1<<4) /* Release time */ | ||
195 | #define BPCI_RESETCTL_CT (1<<8) /* Config time */ | ||
196 | #define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */ | ||
197 | #define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */ | ||
198 | #define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */ | ||
199 | |||
200 | extern struct msp_pci_regs msp_pci_regs | ||
201 | __attribute__((section(".register"))); | ||
202 | extern unsigned long msp_pci_config_space | ||
203 | __attribute__((section(".register"))); | ||
204 | |||
205 | #endif /* !_MSP_PCI_H_ */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h new file mode 100644 index 000000000000..14ca7dc382a8 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h | |||
@@ -0,0 +1,176 @@ | |||
1 | /* | ||
2 | * MIPS boards bootprom interface for the Linux kernel. | ||
3 | * | ||
4 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | ||
5 | * Author: Carsten Langgaard, carstenl@mips.com | ||
6 | * | ||
7 | * ######################################################################## | ||
8 | * | ||
9 | * This program is free software; you can distribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License (Version 2) as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
21 | * | ||
22 | * ######################################################################## | ||
23 | */ | ||
24 | |||
25 | #ifndef _ASM_MSP_PROM_H | ||
26 | #define _ASM_MSP_PROM_H | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | |||
30 | #define DEVICEID "deviceid" | ||
31 | #define FEATURES "features" | ||
32 | #define PROM_ENV "prom_env" | ||
33 | #define PROM_ENV_FILE "/proc/"PROM_ENV | ||
34 | #define PROM_ENV_SIZE 256 | ||
35 | |||
36 | #define CPU_DEVID_FAMILY 0x0000ff00 | ||
37 | #define CPU_DEVID_REVISION 0x000000ff | ||
38 | |||
39 | #define FPGA_IS_POLO(revision) \ | ||
40 | (((revision >= 0xb0) && (revision < 0xd0))) | ||
41 | #define FPGA_IS_5000(revision) \ | ||
42 | ((revision >= 0x80) && (revision <= 0x90)) | ||
43 | #define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) | ||
44 | #define FPGA_IS_DUET(revision) \ | ||
45 | (((revision >= 0xa0) && (revision < 0xb0))) | ||
46 | #define FPGA_IS_MSP4200(revision) ((revision >= 0xd0)) | ||
47 | #define FPGA_IS_MSP7100(revision) ((revision >= 0xd0)) | ||
48 | |||
49 | #define MACHINE_TYPE_POLO "POLO" | ||
50 | #define MACHINE_TYPE_DUET "DUET" | ||
51 | #define MACHINE_TYPE_ZEUS "ZEUS" | ||
52 | #define MACHINE_TYPE_MSP2000REVB "MSP2000REVB" | ||
53 | #define MACHINE_TYPE_MSP5000 "MSP5000" | ||
54 | #define MACHINE_TYPE_MSP4200 "MSP4200" | ||
55 | #define MACHINE_TYPE_MSP7120 "MSP7120" | ||
56 | #define MACHINE_TYPE_MSP7130 "MSP7130" | ||
57 | #define MACHINE_TYPE_OTHER "OTHER" | ||
58 | |||
59 | #define MACHINE_TYPE_POLO_FPGA "POLO-FPGA" | ||
60 | #define MACHINE_TYPE_DUET_FPGA "DUET-FPGA" | ||
61 | #define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA" | ||
62 | #define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA" | ||
63 | #define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA" | ||
64 | #define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA" | ||
65 | #define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA" | ||
66 | #define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA" | ||
67 | |||
68 | /* Device Family definitions */ | ||
69 | #define FAMILY_FPGA 0x0000 | ||
70 | #define FAMILY_ZEUS 0x1000 | ||
71 | #define FAMILY_POLO 0x2000 | ||
72 | #define FAMILY_DUET 0x4000 | ||
73 | #define FAMILY_TRIAD 0x5000 | ||
74 | #define FAMILY_MSP4200 0x4200 | ||
75 | #define FAMILY_MSP4200_FPGA 0x4f00 | ||
76 | #define FAMILY_MSP7100 0x7100 | ||
77 | #define FAMILY_MSP7100_FPGA 0x7f00 | ||
78 | |||
79 | /* Device Type definitions */ | ||
80 | #define TYPE_MSP7120 0x7120 | ||
81 | #define TYPE_MSP7130 0x7130 | ||
82 | |||
83 | #define ENET_KEY 'E' | ||
84 | #define ENETTXD_KEY 'e' | ||
85 | #define PCI_KEY 'P' | ||
86 | #define PCIMUX_KEY 'p' | ||
87 | #define SEC_KEY 'S' | ||
88 | #define SPAD_KEY 'D' | ||
89 | #define TDM_KEY 'T' | ||
90 | #define ZSP_KEY 'Z' | ||
91 | |||
92 | #define FEATURE_NOEXIST '-' | ||
93 | #define FEATURE_EXIST '+' | ||
94 | |||
95 | #define ENET_MII 'M' | ||
96 | #define ENET_RMII 'R' | ||
97 | |||
98 | #define ENETTXD_FALLING 'F' | ||
99 | #define ENETTXD_RISING 'R' | ||
100 | |||
101 | #define PCI_HOST 'H' | ||
102 | #define PCI_PERIPHERAL 'P' | ||
103 | |||
104 | #define PCIMUX_FULL 'F' | ||
105 | #define PCIMUX_SINGLE 'S' | ||
106 | |||
107 | #define SEC_DUET 'D' | ||
108 | #define SEC_POLO 'P' | ||
109 | #define SEC_SLOW 'S' | ||
110 | #define SEC_TRIAD 'T' | ||
111 | |||
112 | #define SPAD_POLO 'P' | ||
113 | |||
114 | #define TDM_DUET 'D' /* DUET TDMs might exist */ | ||
115 | #define TDM_POLO 'P' /* POLO TDMs might exist */ | ||
116 | #define TDM_TRIAD 'T' /* TRIAD TDMs might exist */ | ||
117 | |||
118 | #define ZSP_DUET 'D' /* one DUET zsp engine */ | ||
119 | #define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ | ||
120 | |||
121 | extern char *prom_getcmdline(void); | ||
122 | extern char *prom_getenv(char *name); | ||
123 | extern void prom_init_cmdline(void); | ||
124 | extern void prom_meminit(void); | ||
125 | extern void prom_fixup_mem_map(unsigned long start_mem, | ||
126 | unsigned long end_mem); | ||
127 | |||
128 | #ifdef CONFIG_MTD_PMC_MSP_RAMROOT | ||
129 | extern bool get_ramroot(void **start, unsigned long *size); | ||
130 | #endif | ||
131 | |||
132 | extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr); | ||
133 | extern unsigned long get_deviceid(void); | ||
134 | extern char identify_enet(unsigned long interface_num); | ||
135 | extern char identify_enetTxD(unsigned long interface_num); | ||
136 | extern char identify_pci(void); | ||
137 | extern char identify_sec(void); | ||
138 | extern char identify_spad(void); | ||
139 | extern char identify_sec(void); | ||
140 | extern char identify_tdm(void); | ||
141 | extern char identify_zsp(void); | ||
142 | extern unsigned long identify_family(void); | ||
143 | extern unsigned long identify_revision(void); | ||
144 | |||
145 | /* | ||
146 | * The following macro calls prom_printf and puts the format string | ||
147 | * into an init section so it can be reclaimed. | ||
148 | */ | ||
149 | #define ppfinit(f, x...) \ | ||
150 | do { \ | ||
151 | static char _f[] __initdata = KERN_INFO f; \ | ||
152 | printk(_f, ## x); \ | ||
153 | } while (0) | ||
154 | |||
155 | /* Memory descriptor management. */ | ||
156 | #define PROM_MAX_PMEMBLOCKS 7 /* 6 used */ | ||
157 | |||
158 | enum yamon_memtypes { | ||
159 | yamon_dontuse, | ||
160 | yamon_prom, | ||
161 | yamon_free, | ||
162 | }; | ||
163 | |||
164 | struct prom_pmemblock { | ||
165 | unsigned long base; /* Within KSEG0. */ | ||
166 | unsigned int size; /* In bytes. */ | ||
167 | unsigned int type; /* free or prom memory */ | ||
168 | }; | ||
169 | |||
170 | extern int prom_argc; | ||
171 | extern char **prom_argv; | ||
172 | extern char **prom_envp; | ||
173 | extern int *prom_vec; | ||
174 | extern struct prom_pmemblock *prom_getmdesc(void); | ||
175 | |||
176 | #endif /* !_ASM_MSP_PROM_H */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h new file mode 100644 index 000000000000..60a5a38dd5b2 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h | |||
@@ -0,0 +1,236 @@ | |||
1 | /* | ||
2 | * SMP/VPE-safe functions to access "registers" (see note). | ||
3 | * | ||
4 | * NOTES: | ||
5 | * - These macros use ll/sc instructions, so it is your responsibility to | ||
6 | * ensure these are available on your platform before including this file. | ||
7 | * - The MIPS32 spec states that ll/sc results are undefined for uncached | ||
8 | * accesses. This means they can't be used on HW registers accessed | ||
9 | * through kseg1. Code which requires these macros for this purpose must | ||
10 | * front-end the registers with cached memory "registers" and have a single | ||
11 | * thread update the actual HW registers. | ||
12 | * - A maximum of 2k of code can be inserted between ll and sc. Every | ||
13 | * memory accesses between the instructions will increase the chance of | ||
14 | * sc failing and having to loop. | ||
15 | * - When using custom_read_reg32/custom_write_reg32 only perform the | ||
16 | * necessary logical operations on the register value in between these | ||
17 | * two calls. All other logic should be performed before the first call. | ||
18 | * - There is a bug on the R10000 chips which has a workaround. If you | ||
19 | * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR' | ||
20 | * to be non-zero. If you are using this header from within linux, you may | ||
21 | * include <asm/war.h> before including this file to have this defined | ||
22 | * appropriately for you. | ||
23 | * | ||
24 | * Copyright 2005-2007 PMC-Sierra, Inc. | ||
25 | * | ||
26 | * This program is free software; you can redistribute it and/or modify it | ||
27 | * under the terms of the GNU General Public License as published by the | ||
28 | * Free Software Foundation; either version 2 of the License, or (at your | ||
29 | * option) any later version. | ||
30 | * | ||
31 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
32 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
33 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO | ||
34 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
35 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
36 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
37 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
38 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
40 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
41 | * | ||
42 | * You should have received a copy of the GNU General Public License along | ||
43 | * with this program; if not, write to the Free Software Foundation, Inc., 675 | ||
44 | * Mass Ave, Cambridge, MA 02139, USA. | ||
45 | */ | ||
46 | |||
47 | #ifndef __ASM_REGOPS_H__ | ||
48 | #define __ASM_REGOPS_H__ | ||
49 | |||
50 | #include <linux/types.h> | ||
51 | |||
52 | #include <asm/war.h> | ||
53 | |||
54 | #ifndef R10000_LLSC_WAR | ||
55 | #define R10000_LLSC_WAR 0 | ||
56 | #endif | ||
57 | |||
58 | #if R10000_LLSC_WAR == 1 | ||
59 | #define __beqz "beqzl " | ||
60 | #else | ||
61 | #define __beqz "beqz " | ||
62 | #endif | ||
63 | |||
64 | #ifndef _LINUX_TYPES_H | ||
65 | typedef unsigned int u32; | ||
66 | #endif | ||
67 | |||
68 | /* | ||
69 | * Sets all the masked bits to the corresponding value bits | ||
70 | */ | ||
71 | static inline void set_value_reg32(volatile u32 *const addr, | ||
72 | u32 const mask, | ||
73 | u32 const value) | ||
74 | { | ||
75 | u32 temp; | ||
76 | |||
77 | __asm__ __volatile__( | ||
78 | " .set push \n" | ||
79 | " .set mips3 \n" | ||
80 | "1: ll %0, %1 # set_value_reg32 \n" | ||
81 | " and %0, %2 \n" | ||
82 | " or %0, %3 \n" | ||
83 | " sc %0, %1 \n" | ||
84 | " "__beqz"%0, 1b \n" | ||
85 | " nop \n" | ||
86 | " .set pop \n" | ||
87 | : "=&r" (temp), "=m" (*addr) | ||
88 | : "ir" (~mask), "ir" (value), "m" (*addr)); | ||
89 | } | ||
90 | |||
91 | /* | ||
92 | * Sets all the masked bits to '1' | ||
93 | */ | ||
94 | static inline void set_reg32(volatile u32 *const addr, | ||
95 | u32 const mask) | ||
96 | { | ||
97 | u32 temp; | ||
98 | |||
99 | __asm__ __volatile__( | ||
100 | " .set push \n" | ||
101 | " .set mips3 \n" | ||
102 | "1: ll %0, %1 # set_reg32 \n" | ||
103 | " or %0, %2 \n" | ||
104 | " sc %0, %1 \n" | ||
105 | " "__beqz"%0, 1b \n" | ||
106 | " nop \n" | ||
107 | " .set pop \n" | ||
108 | : "=&r" (temp), "=m" (*addr) | ||
109 | : "ir" (mask), "m" (*addr)); | ||
110 | } | ||
111 | |||
112 | /* | ||
113 | * Sets all the masked bits to '0' | ||
114 | */ | ||
115 | static inline void clear_reg32(volatile u32 *const addr, | ||
116 | u32 const mask) | ||
117 | { | ||
118 | u32 temp; | ||
119 | |||
120 | __asm__ __volatile__( | ||
121 | " .set push \n" | ||
122 | " .set mips3 \n" | ||
123 | "1: ll %0, %1 # clear_reg32 \n" | ||
124 | " and %0, %2 \n" | ||
125 | " sc %0, %1 \n" | ||
126 | " "__beqz"%0, 1b \n" | ||
127 | " nop \n" | ||
128 | " .set pop \n" | ||
129 | : "=&r" (temp), "=m" (*addr) | ||
130 | : "ir" (~mask), "m" (*addr)); | ||
131 | } | ||
132 | |||
133 | /* | ||
134 | * Toggles all masked bits from '0' to '1' and '1' to '0' | ||
135 | */ | ||
136 | static inline void toggle_reg32(volatile u32 *const addr, | ||
137 | u32 const mask) | ||
138 | { | ||
139 | u32 temp; | ||
140 | |||
141 | __asm__ __volatile__( | ||
142 | " .set push \n" | ||
143 | " .set mips3 \n" | ||
144 | "1: ll %0, %1 # toggle_reg32 \n" | ||
145 | " xor %0, %2 \n" | ||
146 | " sc %0, %1 \n" | ||
147 | " "__beqz"%0, 1b \n" | ||
148 | " nop \n" | ||
149 | " .set pop \n" | ||
150 | : "=&r" (temp), "=m" (*addr) | ||
151 | : "ir" (mask), "m" (*addr)); | ||
152 | } | ||
153 | |||
154 | /* | ||
155 | * Read all masked bits others are returned as '0' | ||
156 | */ | ||
157 | static inline u32 read_reg32(volatile u32 *const addr, | ||
158 | u32 const mask) | ||
159 | { | ||
160 | u32 temp; | ||
161 | |||
162 | __asm__ __volatile__( | ||
163 | " .set push \n" | ||
164 | " .set noreorder \n" | ||
165 | " lw %0, %1 # read \n" | ||
166 | " and %0, %2 # mask \n" | ||
167 | " .set pop \n" | ||
168 | : "=&r" (temp) | ||
169 | : "m" (*addr), "ir" (mask)); | ||
170 | |||
171 | return temp; | ||
172 | } | ||
173 | |||
174 | /* | ||
175 | * blocking_read_reg32 - Read address with blocking load | ||
176 | * | ||
177 | * Uncached writes need to be read back to ensure they reach RAM. | ||
178 | * The returned value must be 'used' to prevent from becoming a | ||
179 | * non-blocking load. | ||
180 | */ | ||
181 | static inline u32 blocking_read_reg32(volatile u32 *const addr) | ||
182 | { | ||
183 | u32 temp; | ||
184 | |||
185 | __asm__ __volatile__( | ||
186 | " .set push \n" | ||
187 | " .set noreorder \n" | ||
188 | " lw %0, %1 # read \n" | ||
189 | " move %0, %0 # block \n" | ||
190 | " .set pop \n" | ||
191 | : "=&r" (temp) | ||
192 | : "m" (*addr)); | ||
193 | |||
194 | return temp; | ||
195 | } | ||
196 | |||
197 | /* | ||
198 | * For special strange cases only: | ||
199 | * | ||
200 | * If you need custom processing within a ll/sc loop, use the following macros | ||
201 | * VERY CAREFULLY: | ||
202 | * | ||
203 | * u32 tmp; <-- Define a variable to hold the data | ||
204 | * | ||
205 | * custom_read_reg32(address, tmp); <-- Reads the address and put the value | ||
206 | * in the 'tmp' variable given | ||
207 | * | ||
208 | * From here on out, you are (basicly) atomic, so don't do anything too | ||
209 | * fancy! | ||
210 | * Also, this code may loop if the end of this block fails to write | ||
211 | * everything back safely due do the other CPU, so do NOT do anything | ||
212 | * with side-effects! | ||
213 | * | ||
214 | * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely. | ||
215 | */ | ||
216 | #define custom_read_reg32(address, tmp) \ | ||
217 | __asm__ __volatile__( \ | ||
218 | " .set push \n" \ | ||
219 | " .set mips3 \n" \ | ||
220 | "1: ll %0, %1 #custom_read_reg32 \n" \ | ||
221 | " .set pop \n" \ | ||
222 | : "=r" (tmp), "=m" (*address) \ | ||
223 | : "m" (*address)) | ||
224 | |||
225 | #define custom_write_reg32(address, tmp) \ | ||
226 | __asm__ __volatile__( \ | ||
227 | " .set push \n" \ | ||
228 | " .set mips3 \n" \ | ||
229 | " sc %0, %1 #custom_write_reg32 \n" \ | ||
230 | " "__beqz"%0, 1b \n" \ | ||
231 | " nop \n" \ | ||
232 | " .set pop \n" \ | ||
233 | : "=&r" (tmp), "=m" (*address) \ | ||
234 | : "0" (tmp), "m" (*address)) | ||
235 | |||
236 | #endif /* __ASM_REGOPS_H__ */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h new file mode 100644 index 000000000000..0b56f55206c6 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h | |||
@@ -0,0 +1,667 @@ | |||
1 | /* | ||
2 | * Defines for the address space, registers and register configuration | ||
3 | * (bit masks, access macros etc) for the PMC-Sierra line of MSP products. | ||
4 | * This file contains addess maps for all the devices in the line of | ||
5 | * products but only has register definitions and configuration masks for | ||
6 | * registers which aren't definitely associated with any device. Things | ||
7 | * like clock settings, reset access, the ELB etc. Individual device | ||
8 | * drivers will reference the appropriate XXX_BASE value defined here | ||
9 | * and have individual registers offset from that. | ||
10 | * | ||
11 | * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved. | ||
12 | * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com | ||
13 | * | ||
14 | * ######################################################################## | ||
15 | * | ||
16 | * This program is free software; you can distribute it and/or modify it | ||
17 | * under the terms of the GNU General Public License (Version 2) as | ||
18 | * published by the Free Software Foundation. | ||
19 | * | ||
20 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
21 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
22 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
23 | * for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License along | ||
26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
27 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
28 | * | ||
29 | * ######################################################################## | ||
30 | */ | ||
31 | |||
32 | #include <asm/addrspace.h> | ||
33 | #include <linux/types.h> | ||
34 | |||
35 | #ifndef _ASM_MSP_REGS_H | ||
36 | #define _ASM_MSP_REGS_H | ||
37 | |||
38 | /* | ||
39 | ######################################################################## | ||
40 | # Address space and device base definitions # | ||
41 | ######################################################################## | ||
42 | */ | ||
43 | |||
44 | /* | ||
45 | *************************************************************************** | ||
46 | * System Logic and Peripherals (ELB, UART0, etc) device address space * | ||
47 | *************************************************************************** | ||
48 | */ | ||
49 | #define MSP_SLP_BASE 0x1c000000 | ||
50 | /* System Logic and Peripherals */ | ||
51 | #define MSP_RST_BASE (MSP_SLP_BASE + 0x10) | ||
52 | /* System reset register base */ | ||
53 | #define MSP_RST_SIZE 0x0C /* System reset register space */ | ||
54 | |||
55 | #define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C) | ||
56 | /* watchdog timer base */ | ||
57 | #define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054) | ||
58 | /* internal timer base */ | ||
59 | #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100) | ||
60 | /* UART0 controller base */ | ||
61 | #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120) | ||
62 | /* Block Copy controller base */ | ||
63 | #define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160) | ||
64 | /* Block Copy descriptor base */ | ||
65 | |||
66 | /* | ||
67 | *************************************************************************** | ||
68 | * PCI address space * | ||
69 | *************************************************************************** | ||
70 | */ | ||
71 | #define MSP_PCI_BASE 0x19000000 | ||
72 | |||
73 | /* | ||
74 | *************************************************************************** | ||
75 | * MSbus device address space * | ||
76 | *************************************************************************** | ||
77 | */ | ||
78 | #define MSP_MSB_BASE 0x18000000 | ||
79 | /* MSbus address start */ | ||
80 | #define MSP_PER_BASE (MSP_MSB_BASE + 0x400000) | ||
81 | /* Peripheral device registers */ | ||
82 | #define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000) | ||
83 | /* MAC A device registers */ | ||
84 | #define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000) | ||
85 | /* MAC B device registers */ | ||
86 | #define MSP_MAC_SIZE 0xE0 /* MAC register space */ | ||
87 | |||
88 | #define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000) | ||
89 | /* Security Engine registers */ | ||
90 | #define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000) | ||
91 | /* MAC C device registers */ | ||
92 | #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) | ||
93 | /* ADSL2 device registers */ | ||
94 | #define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) | ||
95 | /* USB device registers */ | ||
96 | #define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) | ||
97 | /* USB device registers */ | ||
98 | #define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) | ||
99 | /* USB device registers */ | ||
100 | #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) | ||
101 | /* CPU interface registers */ | ||
102 | |||
103 | /* Devices within the MSbus peripheral block */ | ||
104 | #define MSP_UART1_BASE (MSP_PER_BASE + 0x030) | ||
105 | /* UART1 controller base */ | ||
106 | #define MSP_SPI_BASE (MSP_PER_BASE + 0x058) | ||
107 | /* SPI/MPI control registers */ | ||
108 | #define MSP_TWI_BASE (MSP_PER_BASE + 0x090) | ||
109 | /* Two-wire control registers */ | ||
110 | #define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0) | ||
111 | /* Programmable timer control */ | ||
112 | |||
113 | /* | ||
114 | *************************************************************************** | ||
115 | * Physical Memory configuration address space * | ||
116 | *************************************************************************** | ||
117 | */ | ||
118 | #define MSP_MEM_CFG_BASE 0x17f00000 | ||
119 | |||
120 | #define MSP_MEM_INDIRECT_CTL_10 0x10 | ||
121 | |||
122 | /* | ||
123 | * Notes: | ||
124 | * 1) The SPI registers are split into two blocks, one offset from the | ||
125 | * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by | ||
126 | * 0x68. The SPI driver definitions for the register must be aware | ||
127 | * of this. | ||
128 | * 2) The block copy engine register are divided into two regions, one | ||
129 | * for the control/configuration of the engine proper and one for the | ||
130 | * values of the descriptors used in the copy process. These have | ||
131 | * different base defines (CTRL_BASE vs DESC_BASE) | ||
132 | * 3) These constants are for physical addresses which means that they | ||
133 | * work correctly with "ioremap" and friends. This means that device | ||
134 | * drivers will need to remap these addresses using ioremap and perhaps | ||
135 | * the readw/writew macros. Or they could use the regptr() macro | ||
136 | * defined below, but the readw/writew calls are the correct thing. | ||
137 | * 4) The UARTs have an additional status register offset from the base | ||
138 | * address. This register isn't used in the standard 8250 driver but | ||
139 | * may be used in other software. Consult the hardware datasheet for | ||
140 | * offset details. | ||
141 | * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers | ||
142 | * start at an offset of 0x84 from the base address but the block of | ||
143 | * registers before this is reserved for the security engine. The | ||
144 | * driver will have to be aware of this but it makes the register | ||
145 | * definitions line up better with the documentation. | ||
146 | */ | ||
147 | |||
148 | /* | ||
149 | ######################################################################## | ||
150 | # System register definitions. Not associated with a specific device # | ||
151 | ######################################################################## | ||
152 | */ | ||
153 | |||
154 | /* | ||
155 | * This macro maps the physical register number into uncached space | ||
156 | * and (for C code) casts it into a u32 pointer so it can be dereferenced | ||
157 | * Normally these would be accessed with ioremap and readX/writeX, but | ||
158 | * these are convenient for a lot of internal kernel code. | ||
159 | */ | ||
160 | #ifdef __ASSEMBLER__ | ||
161 | #define regptr(addr) (KSEG1ADDR(addr)) | ||
162 | #else | ||
163 | #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr))) | ||
164 | #endif | ||
165 | |||
166 | /* | ||
167 | *************************************************************************** | ||
168 | * System Logic and Peripherals (RESET, ELB, etc) registers * | ||
169 | *************************************************************************** | ||
170 | */ | ||
171 | |||
172 | /* System Control register definitions */ | ||
173 | #define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) | ||
174 | /* Device-ID RO */ | ||
175 | #define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) | ||
176 | /* Firmware-ID Register RW */ | ||
177 | #define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) | ||
178 | /* System-ID Register-0 RW */ | ||
179 | #define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) | ||
180 | /* System-ID Register-1 RW */ | ||
181 | |||
182 | /* System Reset register definitions */ | ||
183 | #define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) | ||
184 | /* System Reset Status RO */ | ||
185 | #define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) | ||
186 | /* System Set Reset WO */ | ||
187 | #define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) | ||
188 | /* System Clear Reset WO */ | ||
189 | |||
190 | /* System Clock Registers */ | ||
191 | #define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C) | ||
192 | /* PCI clock generator RW */ | ||
193 | #define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20) | ||
194 | /* UART clock generator RW */ | ||
195 | /* reserved (MSP_SLP_BASE + 0x24) */ | ||
196 | /* reserved (MSP_SLP_BASE + 0x28) */ | ||
197 | #define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C) | ||
198 | /* PLL1 clock generator RW */ | ||
199 | #define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30) | ||
200 | /* PLL0 clock generator RW */ | ||
201 | #define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34) | ||
202 | /* MIPS clock generator RW */ | ||
203 | #define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) | ||
204 | /* Voice Eng clock generator RW */ | ||
205 | /* reserved (MSP_SLP_BASE + 0x3C) */ | ||
206 | #define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40) | ||
207 | /* MS-Bus clock generator RW */ | ||
208 | #define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44) | ||
209 | /* Sec & MAC clock generator RW */ | ||
210 | #define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48) | ||
211 | /* Per & TDM clock generator RW */ | ||
212 | |||
213 | /* Interrupt Controller Registers */ | ||
214 | #define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70) | ||
215 | /* Interrupt status register RW */ | ||
216 | #define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74) | ||
217 | /* Interrupt enable/mask RW */ | ||
218 | #define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78) | ||
219 | /* Security Engine mailbox RW */ | ||
220 | #define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C) | ||
221 | /* Voice Engine mailbox RW */ | ||
222 | |||
223 | /* ELB Controller Registers */ | ||
224 | #define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80) | ||
225 | /* ELB CS0 Configuration Reg */ | ||
226 | #define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84) | ||
227 | /* ELB CS0 Base Address Reg */ | ||
228 | #define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88) | ||
229 | /* ELB CS0 Mask Register */ | ||
230 | #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C) | ||
231 | /* ELB CS0 access register */ | ||
232 | |||
233 | #define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90) | ||
234 | /* ELB CS1 Configuration Reg */ | ||
235 | #define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94) | ||
236 | /* ELB CS1 Base Address Reg */ | ||
237 | #define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98) | ||
238 | /* ELB CS1 Mask Register */ | ||
239 | #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C) | ||
240 | /* ELB CS1 access register */ | ||
241 | |||
242 | #define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0) | ||
243 | /* ELB CS2 Configuration Reg */ | ||
244 | #define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4) | ||
245 | /* ELB CS2 Base Address Reg */ | ||
246 | #define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8) | ||
247 | /* ELB CS2 Mask Register */ | ||
248 | #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC) | ||
249 | /* ELB CS2 access register */ | ||
250 | |||
251 | #define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0) | ||
252 | /* ELB CS3 Configuration Reg */ | ||
253 | #define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4) | ||
254 | /* ELB CS3 Base Address Reg */ | ||
255 | #define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8) | ||
256 | /* ELB CS3 Mask Register */ | ||
257 | #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC) | ||
258 | /* ELB CS3 access register */ | ||
259 | |||
260 | #define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0) | ||
261 | /* ELB CS4 Configuration Reg */ | ||
262 | #define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4) | ||
263 | /* ELB CS4 Base Address Reg */ | ||
264 | #define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8) | ||
265 | /* ELB CS4 Mask Register */ | ||
266 | #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC) | ||
267 | /* ELB CS4 access register */ | ||
268 | |||
269 | #define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0) | ||
270 | /* ELB CS5 Configuration Reg */ | ||
271 | #define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4) | ||
272 | /* ELB CS5 Base Address Reg */ | ||
273 | #define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8) | ||
274 | /* ELB CS5 Mask Register */ | ||
275 | #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC) | ||
276 | /* ELB CS5 access register */ | ||
277 | |||
278 | /* reserved 0xE0 - 0xE8 */ | ||
279 | #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC) | ||
280 | /* ELB single PC card detect */ | ||
281 | |||
282 | /* reserved 0xF0 - 0xF8 */ | ||
283 | #define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) | ||
284 | /* SDRAM read/ELB timing Reg */ | ||
285 | |||
286 | /* Extended UART status registers */ | ||
287 | #define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0) | ||
288 | /* UART Status Register 0 */ | ||
289 | #define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170) | ||
290 | /* UART Status Register 1 */ | ||
291 | |||
292 | /* Performance monitoring registers */ | ||
293 | #define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140) | ||
294 | /* Performance monitor control */ | ||
295 | #define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144) | ||
296 | /* Performance monitor clear */ | ||
297 | #define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148) | ||
298 | /* Perf monitor counter high */ | ||
299 | #define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C) | ||
300 | /* Perf monitor counter low */ | ||
301 | |||
302 | /* System control registers */ | ||
303 | #define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150) | ||
304 | /* System control register */ | ||
305 | #define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154) | ||
306 | /* System Error status 1 */ | ||
307 | #define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158) | ||
308 | /* System Error status 2 */ | ||
309 | #define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C) | ||
310 | /* System Interrupt config */ | ||
311 | |||
312 | /* Voice Engine Memory configuration */ | ||
313 | #define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C) | ||
314 | /* Voice engine memory config */ | ||
315 | |||
316 | /* CPU/SLP Error Status registers */ | ||
317 | #define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180) | ||
318 | /* CPU/SLP Error status 1 */ | ||
319 | #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) | ||
320 | /* CPU/SLP Error status 1 */ | ||
321 | |||
322 | #define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) | ||
323 | /* Extended GPIO register */ | ||
324 | |||
325 | /* System Error registers */ | ||
326 | #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) | ||
327 | /* Int status for SLP errors */ | ||
328 | #define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194) | ||
329 | /* Int mask for SLP errors */ | ||
330 | #define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198) | ||
331 | /* External ELB reset */ | ||
332 | #define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C) | ||
333 | /* Boot Status */ | ||
334 | |||
335 | /* Extended ELB addressing */ | ||
336 | #define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0) | ||
337 | /* CS0 Extended address */ | ||
338 | #define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4) | ||
339 | /* CS1 Extended address */ | ||
340 | #define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8) | ||
341 | /* CS2 Extended address */ | ||
342 | #define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC) | ||
343 | /* CS3 Extended address */ | ||
344 | /* reserved 0x1B0 */ | ||
345 | #define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4) | ||
346 | /* CS5 Extended address */ | ||
347 | |||
348 | /* PLL Adjustment registers */ | ||
349 | #define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200) | ||
350 | /* PLL0 lock status */ | ||
351 | #define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204) | ||
352 | /* PLL Analog reset status */ | ||
353 | #define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208) | ||
354 | /* PLL0 Adjustment value */ | ||
355 | #define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C) | ||
356 | /* PLL1 Adjustment value */ | ||
357 | |||
358 | /* | ||
359 | *************************************************************************** | ||
360 | * Peripheral Register definitions * | ||
361 | *************************************************************************** | ||
362 | */ | ||
363 | |||
364 | /* Peripheral status */ | ||
365 | #define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50) | ||
366 | /* Peripheral control register */ | ||
367 | #define PER_STS_REG regptr(MSP_PER_BASE + 0x54) | ||
368 | /* Peripheral status register */ | ||
369 | |||
370 | /* SPI/MPI Registers */ | ||
371 | #define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58) | ||
372 | /* SPI/MPI Tx Size register */ | ||
373 | #define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C) | ||
374 | /* SPI/MPI Rx Size register */ | ||
375 | #define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60) | ||
376 | /* SPI/MPI Control register */ | ||
377 | #define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64) | ||
378 | /* SPI/MPI Chip Select reg */ | ||
379 | #define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0) | ||
380 | /* SPI/MPI Core Data reg */ | ||
381 | #define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4) | ||
382 | /* SPI/MPI Core Control reg */ | ||
383 | #define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8) | ||
384 | /* SPI/MPI Core Status reg */ | ||
385 | #define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC) | ||
386 | /* SPI/MPI Core Ssel reg */ | ||
387 | #define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0) | ||
388 | /* SPI/MPI Data FIFO reg */ | ||
389 | |||
390 | /* Peripheral Block Error Registers */ | ||
391 | #define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70) | ||
392 | /* Error Bit Status Register */ | ||
393 | #define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74) | ||
394 | /* Error Bit Mask Register */ | ||
395 | #define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78) | ||
396 | /* Error Header 1 Register */ | ||
397 | #define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C) | ||
398 | /* Error Header 2 Register */ | ||
399 | |||
400 | /* Peripheral Block Interrupt Registers */ | ||
401 | #define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80) | ||
402 | /* Interrupt status register */ | ||
403 | #define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84) | ||
404 | /* Interrupt Mask Register */ | ||
405 | #define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88) | ||
406 | /* GPIO interrupt status reg */ | ||
407 | #define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C) | ||
408 | /* GPIO interrupt MASK Reg */ | ||
409 | |||
410 | /* POLO GPIO registers */ | ||
411 | #define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0) | ||
412 | /* Polo GPIO[8:0] data reg */ | ||
413 | #define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4) | ||
414 | /* Polo GPIO[7:0] config reg */ | ||
415 | #define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8) | ||
416 | /* Polo GPIO[15:8] config reg */ | ||
417 | #define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC) | ||
418 | /* Polo GPIO[31:0] output drive */ | ||
419 | #define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170) | ||
420 | /* Polo GPIO[23:16] config reg */ | ||
421 | #define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174) | ||
422 | /* Polo GPIO[15:9] data reg */ | ||
423 | #define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178) | ||
424 | /* Polo GPIO[23:16] data reg */ | ||
425 | #define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C) | ||
426 | /* Polo GPIO[31:24] data reg */ | ||
427 | #define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180) | ||
428 | /* Polo GPIO[39:32] data reg */ | ||
429 | #define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184) | ||
430 | /* Polo GPIO[47:40] data reg */ | ||
431 | #define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188) | ||
432 | /* Polo GPIO[54:48] data reg */ | ||
433 | #define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) | ||
434 | /* Polo GPIO[31:24] config reg */ | ||
435 | #define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190) | ||
436 | /* Polo GPIO[39:32] config reg */ | ||
437 | #define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194) | ||
438 | /* Polo GPIO[47:40] config reg */ | ||
439 | #define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198) | ||
440 | /* Polo GPIO[54:48] config reg */ | ||
441 | #define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C) | ||
442 | /* Polo GPIO[54:32] output drive */ | ||
443 | |||
444 | /* Generic GPIO registers */ | ||
445 | #define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170) | ||
446 | /* GPIO[1:0] data register */ | ||
447 | #define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174) | ||
448 | /* GPIO[5:2] data register */ | ||
449 | #define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178) | ||
450 | /* GPIO[9:6] data register */ | ||
451 | #define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C) | ||
452 | /* GPIO[15:10] data register */ | ||
453 | #define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180) | ||
454 | /* GPIO[1:0] config register */ | ||
455 | #define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184) | ||
456 | /* GPIO[5:2] config register */ | ||
457 | #define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188) | ||
458 | /* GPIO[9:6] config register */ | ||
459 | #define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) | ||
460 | /* GPIO[15:10] config register */ | ||
461 | #define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190) | ||
462 | /* GPIO[15:0] output drive */ | ||
463 | |||
464 | /* | ||
465 | *************************************************************************** | ||
466 | * CPU Interface register definitions * | ||
467 | *************************************************************************** | ||
468 | */ | ||
469 | #define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00) | ||
470 | /* PCI-SDRAM queue flush trigger */ | ||
471 | #define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04) | ||
472 | /* OCP Error Attribute 1 */ | ||
473 | #define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08) | ||
474 | /* OCP Error Attribute 2 */ | ||
475 | #define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C) | ||
476 | /* OCP Error Status */ | ||
477 | #define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10) | ||
478 | /* CPU policy configuration */ | ||
479 | #define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10) | ||
480 | /* Misc configuration options */ | ||
481 | |||
482 | /* Central Interrupt Controller Registers */ | ||
483 | #define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000) | ||
484 | /* Central Interrupt registers */ | ||
485 | #define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00) | ||
486 | /* External interrupt config */ | ||
487 | #define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04) | ||
488 | /* CIC Interrupt Status */ | ||
489 | #define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08) | ||
490 | /* VPE0 Interrupt Mask */ | ||
491 | #define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C) | ||
492 | /* VPE1 Interrupt Mask */ | ||
493 | #define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10) | ||
494 | /* Thread Context 0 Int Mask */ | ||
495 | #define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14) | ||
496 | /* Thread Context 1 Int Mask */ | ||
497 | #define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18) | ||
498 | /* Thread Context 2 Int Mask */ | ||
499 | #define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18) | ||
500 | /* Thread Context 3 Int Mask */ | ||
501 | #define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18) | ||
502 | /* Thread Context 4 Int Mask */ | ||
503 | #define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18) | ||
504 | #define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18) | ||
505 | #define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18) | ||
506 | #define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08) | ||
507 | |||
508 | |||
509 | /* | ||
510 | *************************************************************************** | ||
511 | * Memory controller registers * | ||
512 | *************************************************************************** | ||
513 | */ | ||
514 | #define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00) | ||
515 | #define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00) | ||
516 | #define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04) | ||
517 | #define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08) | ||
518 | |||
519 | /* | ||
520 | *************************************************************************** | ||
521 | * PCI controller registers * | ||
522 | *************************************************************************** | ||
523 | */ | ||
524 | #define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00) | ||
525 | #define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800) | ||
526 | #define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c) | ||
527 | |||
528 | /* | ||
529 | ######################################################################## | ||
530 | # Register content & macro definitions # | ||
531 | ######################################################################## | ||
532 | */ | ||
533 | |||
534 | /* | ||
535 | *************************************************************************** | ||
536 | * DEV_ID defines * | ||
537 | *************************************************************************** | ||
538 | */ | ||
539 | #define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ | ||
540 | #define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ | ||
541 | #define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ | ||
542 | #define DEV_ID_FAMILY (0xff << 8) /* family ID code */ | ||
543 | #define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ | ||
544 | |||
545 | #define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ | ||
546 | #define MSP5000_ID (0x50 << 8) | ||
547 | #define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ | ||
548 | #define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ | ||
549 | #define MSP4200_ID (0x42 << 8) | ||
550 | #define MSP4000_ID (0x40 << 8) | ||
551 | #define MSP2XXX_ID (0x20 << 8) | ||
552 | #define MSPZEUS_ID (0x10 << 8) | ||
553 | |||
554 | #define MSP2004_SUB_ID (0x0 << 16) | ||
555 | #define MSP2005_SUB_ID (0x1 << 16) | ||
556 | #define MSP2006_SUB_ID (0x1 << 16) | ||
557 | #define MSP2007_SUB_ID (0x2 << 16) | ||
558 | #define MSP2010_SUB_ID (0x3 << 16) | ||
559 | #define MSP2015_SUB_ID (0x4 << 16) | ||
560 | #define MSP2020_SUB_ID (0x5 << 16) | ||
561 | #define MSP2100_SUB_ID (0x6 << 16) | ||
562 | |||
563 | /* | ||
564 | *************************************************************************** | ||
565 | * RESET defines * | ||
566 | *************************************************************************** | ||
567 | */ | ||
568 | #define MSP_GR_RST (0x01 << 0) /* Global reset bit */ | ||
569 | #define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ | ||
570 | #define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ | ||
571 | #define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ | ||
572 | /* reserved */ | ||
573 | #define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ | ||
574 | #define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ | ||
575 | #define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ | ||
576 | #define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ | ||
577 | #define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ | ||
578 | #define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ | ||
579 | #define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ | ||
580 | #define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ | ||
581 | #define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ | ||
582 | |||
583 | /* | ||
584 | *************************************************************************** | ||
585 | * UART defines * | ||
586 | *************************************************************************** | ||
587 | */ | ||
588 | #ifndef CONFIG_MSP_FPGA | ||
589 | #define MSP_BASE_BAUD 25000000 | ||
590 | #else | ||
591 | #define MSP_BASE_BAUD 6000000 | ||
592 | #endif | ||
593 | #define MSP_UART_REG_LEN 0x20 | ||
594 | |||
595 | /* | ||
596 | *************************************************************************** | ||
597 | * ELB defines * | ||
598 | *************************************************************************** | ||
599 | */ | ||
600 | #define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ | ||
601 | #define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ | ||
602 | |||
603 | /* | ||
604 | *************************************************************************** | ||
605 | * CIC defines * | ||
606 | *************************************************************************** | ||
607 | */ | ||
608 | |||
609 | /* CIC_EXT_CFG_REG */ | ||
610 | #define EXT_INT_POL(eirq) (1 << (eirq + 8)) | ||
611 | #define EXT_INT_EDGE(eirq) (1 << eirq) | ||
612 | |||
613 | #define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq)) | ||
614 | #define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq)) | ||
615 | #define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq)) | ||
616 | #define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq)) | ||
617 | #define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI | ||
618 | #define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO | ||
619 | |||
620 | #define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \ | ||
621 | ((reg & EXT_INT_EDGE(eirq)) == 0) | ||
622 | #define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq)) | ||
623 | #define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq)) | ||
624 | #define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \ | ||
625 | ((reg & EXT_INT_POL(eirq)) == 0) | ||
626 | #define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI | ||
627 | #define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO | ||
628 | |||
629 | /* | ||
630 | *************************************************************************** | ||
631 | * Memory Controller defines * | ||
632 | *************************************************************************** | ||
633 | */ | ||
634 | |||
635 | /* Indirect memory controller registers */ | ||
636 | #define DDRC_CFG(n) (n) | ||
637 | #define DDRC_DEBUG(n) (0x04 + n) | ||
638 | #define DDRC_CTL(n) (0x40 + n) | ||
639 | |||
640 | /* Macro to perform DDRC indirect write */ | ||
641 | #define DDRC_INDIRECT_WRITE(reg, mask, value) \ | ||
642 | ({ \ | ||
643 | *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ | ||
644 | *MEM_SS_DATA = (value); \ | ||
645 | *MEM_SS_WRITE = 1; \ | ||
646 | }) | ||
647 | |||
648 | /* | ||
649 | *************************************************************************** | ||
650 | * SPI/MPI Mode * | ||
651 | *************************************************************************** | ||
652 | */ | ||
653 | #define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */ | ||
654 | #define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ | ||
655 | #define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */ | ||
656 | #define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ | ||
657 | |||
658 | /* | ||
659 | *************************************************************************** | ||
660 | * SPI/MPI Control Register * | ||
661 | *************************************************************************** | ||
662 | */ | ||
663 | #define SPI_MPI_RX_START 0x00000004 /* Start receive command */ | ||
664 | #define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */ | ||
665 | #define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */ | ||
666 | |||
667 | #endif /* !_ASM_MSP_REGS_H */ | ||
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h new file mode 100644 index 000000000000..96d4c8ce8c83 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /* | ||
2 | * Defines for the MSP interrupt controller. | ||
3 | * | ||
4 | * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. | ||
5 | * Author: Carsten Langgaard, carstenl@mips.com | ||
6 | * | ||
7 | * ######################################################################## | ||
8 | * | ||
9 | * This program is free software; you can distribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License (Version 2) as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
21 | * | ||
22 | * ######################################################################## | ||
23 | */ | ||
24 | |||
25 | #ifndef _MSP_SLP_INT_H | ||
26 | #define _MSP_SLP_INT_H | ||
27 | |||
28 | /* | ||
29 | * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded | ||
30 | * hierarchical system. The first level are the direct MIPS interrupts | ||
31 | * and are assigned the interrupt range 0-7. The second level is the SLM | ||
32 | * interrupt controller and is assigned the range 8-39. The third level | ||
33 | * comprises the Peripherial block, the PCI block, the PCI MSI block and | ||
34 | * the SLP. The PCI interrupts and the SLP errors are handled by the | ||
35 | * relevant subsystems so the core interrupt code needs only concern | ||
36 | * itself with the Peripheral block. These are assigned interrupts in | ||
37 | * the range 40-71. | ||
38 | */ | ||
39 | |||
40 | /* | ||
41 | * IRQs directly connected to CPU | ||
42 | */ | ||
43 | #define MSP_MIPS_INTBASE 0 | ||
44 | #define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ | ||
45 | #define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ | ||
46 | #define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ | ||
47 | #define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ | ||
48 | #define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ | ||
49 | #define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */ | ||
50 | #define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */ | ||
51 | #define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */ | ||
52 | |||
53 | /* | ||
54 | * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) | ||
55 | * These defines should be tied to the register definition for the SLM | ||
56 | * interrupt routine. For now, just use hard-coded values. | ||
57 | */ | ||
58 | #define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8) | ||
59 | #define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0) | ||
60 | /* External interrupt 0 */ | ||
61 | #define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1) | ||
62 | /* External interrupt 1 */ | ||
63 | #define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2) | ||
64 | /* External interrupt 2 */ | ||
65 | #define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3) | ||
66 | /* External interrupt 3 */ | ||
67 | /* Reserved 4-7 */ | ||
68 | |||
69 | /* | ||
70 | ************************************************************************* | ||
71 | * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER * | ||
72 | * Some MSP produces have this interrupt labelled as Voice and some are * | ||
73 | * SEC mbox ... * | ||
74 | ************************************************************************* | ||
75 | */ | ||
76 | #define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8) | ||
77 | /* Cascaded IRQ for Voice Engine*/ | ||
78 | #define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9) | ||
79 | /* TDM interrupt */ | ||
80 | #define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10) | ||
81 | /* Cascaded IRQ for MAC 0 */ | ||
82 | #define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11) | ||
83 | /* Cascaded IRQ for MAC 1 */ | ||
84 | #define MSP_INT_SEC (MSP_SLP_INTBASE + 12) | ||
85 | /* IRQ for security engine */ | ||
86 | #define MSP_INT_PER (MSP_SLP_INTBASE + 13) | ||
87 | /* Peripheral interrupt */ | ||
88 | #define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) | ||
89 | /* SLP timer 0 */ | ||
90 | #define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) | ||
91 | /* SLP timer 1 */ | ||
92 | #define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) | ||
93 | /* SLP timer 2 */ | ||
94 | #define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) | ||
95 | /* Cascaded MIPS timer */ | ||
96 | #define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18) | ||
97 | /* Block Copy */ | ||
98 | #define MSP_INT_UART0 (MSP_SLP_INTBASE + 19) | ||
99 | /* UART 0 */ | ||
100 | #define MSP_INT_PCI (MSP_SLP_INTBASE + 20) | ||
101 | /* PCI subsystem */ | ||
102 | #define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21) | ||
103 | /* PCI doorbell */ | ||
104 | #define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22) | ||
105 | /* PCI Message Signal */ | ||
106 | #define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23) | ||
107 | /* PCI Block Copy 0 */ | ||
108 | #define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24) | ||
109 | /* PCI Block Copy 1 */ | ||
110 | #define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25) | ||
111 | /* SLP error condition */ | ||
112 | #define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26) | ||
113 | /* IRQ for MAC2 */ | ||
114 | /* Reserved 26-31 */ | ||
115 | |||
116 | /* | ||
117 | * IRQs cascaded on SLP PER interrupt (MSP_INT_PER) | ||
118 | */ | ||
119 | #define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32) | ||
120 | /* Reserved 0-1 */ | ||
121 | #define MSP_INT_UART1 (MSP_PER_INTBASE + 2) | ||
122 | /* UART 1 */ | ||
123 | /* Reserved 3-5 */ | ||
124 | #define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) | ||
125 | /* 2-wire */ | ||
126 | #define MSP_INT_TM0 (MSP_PER_INTBASE + 7) | ||
127 | /* Peripheral timer block out 0 */ | ||
128 | #define MSP_INT_TM1 (MSP_PER_INTBASE + 8) | ||
129 | /* Peripheral timer block out 1 */ | ||
130 | /* Reserved 9 */ | ||
131 | #define MSP_INT_SPRX (MSP_PER_INTBASE + 10) | ||
132 | /* SPI RX complete */ | ||
133 | #define MSP_INT_SPTX (MSP_PER_INTBASE + 11) | ||
134 | /* SPI TX complete */ | ||
135 | #define MSP_INT_GPIO (MSP_PER_INTBASE + 12) | ||
136 | /* GPIO */ | ||
137 | #define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) | ||
138 | /* Peripheral error */ | ||
139 | /* Reserved 14-31 */ | ||
140 | |||
141 | #endif /* !_MSP_SLP_INT_H */ | ||
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 5f80ba71ab92..1d8b9a8ae324 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h | |||
@@ -82,10 +82,6 @@ struct mips_fpu_struct { | |||
82 | unsigned int fcr31; | 82 | unsigned int fcr31; |
83 | }; | 83 | }; |
84 | 84 | ||
85 | #define INIT_FPU { \ | ||
86 | {0,} \ | ||
87 | } | ||
88 | |||
89 | #define NUM_DSP_REGS 6 | 85 | #define NUM_DSP_REGS 6 |
90 | 86 | ||
91 | typedef __u32 dspreg_t; | 87 | typedef __u32 dspreg_t; |
@@ -95,8 +91,6 @@ struct mips_dsp_state { | |||
95 | unsigned int dspcontrol; | 91 | unsigned int dspcontrol; |
96 | }; | 92 | }; |
97 | 93 | ||
98 | #define INIT_DSP {{0,},} | ||
99 | |||
100 | #define INIT_CPUMASK { \ | 94 | #define INIT_CPUMASK { \ |
101 | {0,} \ | 95 | {0,} \ |
102 | } | 96 | } |
@@ -155,41 +149,63 @@ struct thread_struct { | |||
155 | #define MF_N64 0 | 149 | #define MF_N64 0 |
156 | 150 | ||
157 | #ifdef CONFIG_MIPS_MT_FPAFF | 151 | #ifdef CONFIG_MIPS_MT_FPAFF |
158 | #define FPAFF_INIT 0, INIT_CPUMASK, | 152 | #define FPAFF_INIT \ |
153 | .emulated_fp = 0, \ | ||
154 | .user_cpus_allowed = INIT_CPUMASK, | ||
159 | #else | 155 | #else |
160 | #define FPAFF_INIT | 156 | #define FPAFF_INIT |
161 | #endif /* CONFIG_MIPS_MT_FPAFF */ | 157 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
162 | 158 | ||
163 | #define INIT_THREAD { \ | 159 | #define INIT_THREAD { \ |
164 | /* \ | 160 | /* \ |
165 | * saved main processor registers \ | 161 | * Saved main processor registers \ |
166 | */ \ | 162 | */ \ |
167 | 0, 0, 0, 0, 0, 0, 0, 0, \ | 163 | .reg16 = 0, \ |
168 | 0, 0, 0, \ | 164 | .reg17 = 0, \ |
169 | /* \ | 165 | .reg18 = 0, \ |
170 | * saved cp0 stuff \ | 166 | .reg19 = 0, \ |
171 | */ \ | 167 | .reg20 = 0, \ |
172 | 0, \ | 168 | .reg21 = 0, \ |
173 | /* \ | 169 | .reg22 = 0, \ |
174 | * saved fpu/fpu emulator stuff \ | 170 | .reg23 = 0, \ |
175 | */ \ | 171 | .reg29 = 0, \ |
176 | INIT_FPU, \ | 172 | .reg30 = 0, \ |
177 | /* \ | 173 | .reg31 = 0, \ |
178 | * fpu affinity state (null if not FPAFF) \ | 174 | /* \ |
179 | */ \ | 175 | * Saved cp0 stuff \ |
180 | FPAFF_INIT \ | 176 | */ \ |
181 | /* \ | 177 | .cp0_status = 0, \ |
182 | * saved dsp/dsp emulator stuff \ | 178 | /* \ |
183 | */ \ | 179 | * Saved FPU/FPU emulator stuff \ |
184 | INIT_DSP, \ | 180 | */ \ |
185 | /* \ | 181 | .fpu = { \ |
186 | * Other stuff associated with the process \ | 182 | .fpr = {0,}, \ |
187 | */ \ | 183 | .fcr31 = 0, \ |
188 | 0, 0, 0, 0, \ | 184 | }, \ |
189 | /* \ | 185 | /* \ |
190 | * For now the default is to fix address errors \ | 186 | * FPU affinity state (null if not FPAFF) \ |
191 | */ \ | 187 | */ \ |
192 | MF_FIXADE, 0, 0 \ | 188 | FPAFF_INIT \ |
189 | /* \ | ||
190 | * Saved DSP stuff \ | ||
191 | */ \ | ||
192 | .dsp = { \ | ||
193 | .dspr = {0, }, \ | ||
194 | .dspcontrol = 0, \ | ||
195 | }, \ | ||
196 | /* \ | ||
197 | * Other stuff associated with the process \ | ||
198 | */ \ | ||
199 | .cp0_badvaddr = 0, \ | ||
200 | .cp0_baduaddr = 0, \ | ||
201 | .error_code = 0, \ | ||
202 | .trap_no = 0, \ | ||
203 | /* \ | ||
204 | * For now the default is to fix address errors \ | ||
205 | */ \ | ||
206 | .mflags = MF_FIXADE, \ | ||
207 | .irix_trampoline = 0, \ | ||
208 | .irix_oldctx = 0, \ | ||
193 | } | 209 | } |
194 | 210 | ||
195 | struct task_struct; | 211 | struct task_struct; |
@@ -237,7 +253,7 @@ unsigned long get_wchan(struct task_struct *p); | |||
237 | 253 | ||
238 | #define ARCH_HAS_PREFETCH | 254 | #define ARCH_HAS_PREFETCH |
239 | 255 | ||
240 | extern inline void prefetch(const void *addr) | 256 | static inline void prefetch(const void *addr) |
241 | { | 257 | { |
242 | __asm__ __volatile__( | 258 | __asm__ __volatile__( |
243 | " .set mips4 \n" | 259 | " .set mips4 \n" |
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 1906938285c0..85b44366343a 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h | |||
@@ -86,7 +86,7 @@ struct pt_regs { | |||
86 | 86 | ||
87 | extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); | 87 | extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); |
88 | 88 | ||
89 | extern NORET_TYPE void die(const char *, struct pt_regs *); | 89 | extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET; |
90 | 90 | ||
91 | static inline void die_if_kernel(const char *str, struct pt_regs *regs) | 91 | static inline void die_if_kernel(const char *str, struct pt_regs *regs) |
92 | { | 92 | { |
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h deleted file mode 100644 index 82ad401c7dca..000000000000 --- a/include/asm-mips/rtc.h +++ /dev/null | |||
@@ -1,73 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-mips/rtc.h | ||
3 | * | ||
4 | * (Really an interface for drivers/char/genrtc.c) | ||
5 | * | ||
6 | * Copyright (C) 2004 MontaVista Software Inc. | ||
7 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
8 | * | ||
9 | * Please read the COPYING file for all license details. | ||
10 | */ | ||
11 | |||
12 | #ifndef _MIPS_RTC_H | ||
13 | #define _MIPS_RTC_H | ||
14 | |||
15 | #ifdef __KERNEL__ | ||
16 | |||
17 | #include <linux/rtc.h> | ||
18 | #include <asm/time.h> | ||
19 | |||
20 | #define RTC_PIE 0x40 /* periodic interrupt enable */ | ||
21 | #define RTC_AIE 0x20 /* alarm interrupt enable */ | ||
22 | #define RTC_UIE 0x10 /* update-finished interrupt enable */ | ||
23 | |||
24 | /* some dummy definitions */ | ||
25 | #define RTC_BATT_BAD 0x100 /* battery bad */ | ||
26 | #define RTC_SQWE 0x08 /* enable square-wave output */ | ||
27 | #define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ | ||
28 | #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ | ||
29 | #define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ | ||
30 | |||
31 | static inline unsigned int get_rtc_time(struct rtc_time *time) | ||
32 | { | ||
33 | unsigned long nowtime; | ||
34 | |||
35 | nowtime = rtc_mips_get_time(); | ||
36 | to_tm(nowtime, time); | ||
37 | time->tm_year -= 1900; | ||
38 | |||
39 | return RTC_24H; | ||
40 | } | ||
41 | |||
42 | static inline int set_rtc_time(struct rtc_time *time) | ||
43 | { | ||
44 | unsigned long nowtime; | ||
45 | int ret; | ||
46 | |||
47 | nowtime = mktime(time->tm_year+1900, time->tm_mon+1, | ||
48 | time->tm_mday, time->tm_hour, time->tm_min, | ||
49 | time->tm_sec); | ||
50 | ret = rtc_mips_set_time(nowtime); | ||
51 | |||
52 | return ret; | ||
53 | } | ||
54 | |||
55 | static inline unsigned int get_rtc_ss(void) | ||
56 | { | ||
57 | struct rtc_time h; | ||
58 | |||
59 | get_rtc_time(&h); | ||
60 | return h.tm_sec; | ||
61 | } | ||
62 | |||
63 | static inline int get_rtc_pll(struct rtc_pll_info *pll) | ||
64 | { | ||
65 | return -EINVAL; | ||
66 | } | ||
67 | |||
68 | static inline int set_rtc_pll(struct rtc_pll_info *pll) | ||
69 | { | ||
70 | return -EINVAL; | ||
71 | } | ||
72 | #endif | ||
73 | #endif | ||
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index ce51213d84f9..c07ebd8eb9e7 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h | |||
@@ -19,159 +19,4 @@ | |||
19 | */ | 19 | */ |
20 | #define BASE_BAUD (1843200 / 16) | 20 | #define BASE_BAUD (1843200 / 16) |
21 | 21 | ||
22 | /* Standard COM flags (except for COM4, because of the 8514 problem) */ | ||
23 | #ifdef CONFIG_SERIAL_DETECT_IRQ | ||
24 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) | ||
25 | #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) | ||
26 | #else | ||
27 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
28 | #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF | ||
29 | #endif | ||
30 | |||
31 | #ifdef CONFIG_MACH_JAZZ | ||
32 | #include <asm/jazz.h> | ||
33 | |||
34 | #ifndef CONFIG_OLIVETTI_M700 | ||
35 | /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know | ||
36 | exactly which ones ... XXX */ | ||
37 | #define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ | ||
38 | #else | ||
39 | /* but the M700 isn't such a strange beast */ | ||
40 | #define JAZZ_BASE_BAUD BASE_BAUD | ||
41 | #endif | ||
42 | |||
43 | #define _JAZZ_SERIAL_INIT(int, base) \ | ||
44 | { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ | ||
45 | .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \ | ||
46 | .io_type = SERIAL_IO_MEM } | ||
47 | #define JAZZ_SERIAL_PORT_DEFNS \ | ||
48 | _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \ | ||
49 | _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE), | ||
50 | #else | ||
51 | #define JAZZ_SERIAL_PORT_DEFNS | ||
52 | #endif | ||
53 | |||
54 | /* | ||
55 | * Galileo EV64120 evaluation board | ||
56 | */ | ||
57 | #ifdef CONFIG_MIPS_EV64120 | ||
58 | #include <mach-gt64120.h> | ||
59 | #define EV64120_SERIAL_PORT_DEFNS \ | ||
60 | { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ | ||
61 | .flags = STD_COM_FLAGS, \ | ||
62 | .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \ | ||
63 | .io_type = SERIAL_IO_MEM }, \ | ||
64 | { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ | ||
65 | .flags = STD_COM_FLAGS, \ | ||
66 | .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \ | ||
67 | .io_type = SERIAL_IO_MEM }, | ||
68 | #else | ||
69 | #define EV64120_SERIAL_PORT_DEFNS | ||
70 | #endif | ||
71 | |||
72 | #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT | ||
73 | #define STD_SERIAL_PORT_DEFNS \ | ||
74 | /* UART CLK PORT IRQ FLAGS */ \ | ||
75 | { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ | ||
76 | { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ | ||
77 | { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ | ||
78 | { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ | ||
79 | |||
80 | #else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ | ||
81 | #define STD_SERIAL_PORT_DEFNS | ||
82 | #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ | ||
83 | |||
84 | #ifdef CONFIG_MOMENCO_OCELOT_3 | ||
85 | #define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) | ||
86 | #define OCELOT_3_SERIAL_IRQ 6 | ||
87 | #define OCELOT_3_SERIAL_BASE (signed)0xfd000020 | ||
88 | |||
89 | #define _OCELOT_3_SERIAL_INIT(int, base) \ | ||
90 | { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \ | ||
91 | .flags = STD_COM_FLAGS, \ | ||
92 | .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ | ||
93 | io_type: SERIAL_IO_MEM } | ||
94 | |||
95 | #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ | ||
96 | _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) | ||
97 | #else | ||
98 | #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS | ||
99 | #endif | ||
100 | |||
101 | #ifdef CONFIG_MOMENCO_OCELOT | ||
102 | /* Ordinary NS16552 duart with a 20MHz crystal. */ | ||
103 | #define OCELOT_BASE_BAUD ( 20000000 / 16 ) | ||
104 | |||
105 | #define OCELOT_SERIAL1_IRQ 4 | ||
106 | #define OCELOT_SERIAL1_BASE 0xe0001020 | ||
107 | |||
108 | #define _OCELOT_SERIAL_INIT(int, base) \ | ||
109 | { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ | ||
110 | .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ | ||
111 | .io_type = SERIAL_IO_MEM } | ||
112 | #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ | ||
113 | _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE) | ||
114 | #else | ||
115 | #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS | ||
116 | #endif | ||
117 | |||
118 | #ifdef CONFIG_MOMENCO_OCELOT_C | ||
119 | /* Ordinary NS16552 duart with a 20MHz crystal. */ | ||
120 | #define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) | ||
121 | |||
122 | #define OCELOT_C_SERIAL1_IRQ 80 | ||
123 | #define OCELOT_C_SERIAL1_BASE 0xfd000020 | ||
124 | |||
125 | #define OCELOT_C_SERIAL2_IRQ 81 | ||
126 | #define OCELOT_C_SERIAL2_BASE 0xfd000000 | ||
127 | |||
128 | #define _OCELOT_C_SERIAL_INIT(int, base) \ | ||
129 | { .baud_base = OCELOT_C_BASE_BAUD, \ | ||
130 | .irq = (int), \ | ||
131 | .flags = STD_COM_FLAGS, \ | ||
132 | .iomem_base = (u8 *) base, \ | ||
133 | .iomem_reg_shift = 2, \ | ||
134 | .io_type = SERIAL_IO_MEM \ | ||
135 | } | ||
136 | #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ | ||
137 | _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ | ||
138 | _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) | ||
139 | #else | ||
140 | #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS | ||
141 | #endif | ||
142 | |||
143 | #ifdef CONFIG_DDB5477 | ||
144 | #include <asm/ddb5xxx/ddb5477.h> | ||
145 | #define DDB5477_SERIAL_PORT_DEFNS \ | ||
146 | { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \ | ||
147 | .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \ | ||
148 | .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \ | ||
149 | { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \ | ||
150 | .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \ | ||
151 | .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, | ||
152 | #else | ||
153 | #define DDB5477_SERIAL_PORT_DEFNS | ||
154 | #endif | ||
155 | |||
156 | #ifdef CONFIG_SGI_IP32 | ||
157 | /* | ||
158 | * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory | ||
159 | * They are initialized in ip32_setup | ||
160 | */ | ||
161 | #define IP32_SERIAL_PORT_DEFNS \ | ||
162 | {},{}, | ||
163 | #else | ||
164 | #define IP32_SERIAL_PORT_DEFNS | ||
165 | #endif /* CONFIG_SGI_IP32 */ | ||
166 | |||
167 | #define SERIAL_PORT_DFNS \ | ||
168 | DDB5477_SERIAL_PORT_DEFNS \ | ||
169 | EV64120_SERIAL_PORT_DEFNS \ | ||
170 | IP32_SERIAL_PORT_DEFNS \ | ||
171 | JAZZ_SERIAL_PORT_DEFNS \ | ||
172 | STD_SERIAL_PORT_DEFNS \ | ||
173 | MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ | ||
174 | MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ | ||
175 | MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS | ||
176 | |||
177 | #endif /* _ASM_SERIAL_H */ | 22 | #endif /* _ASM_SERIAL_H */ |
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index bda391d3af85..2738c1366f66 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h | |||
@@ -220,17 +220,25 @@ | |||
220 | #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) | 220 | #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) |
221 | 221 | ||
222 | #define BCM1480_DUART_CHANREG_SPACING 0x100 | 222 | #define BCM1480_DUART_CHANREG_SPACING 0x100 |
223 | #define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ | 223 | #define A_BCM1480_DUART_CHANREG(chan, reg) \ |
224 | + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ | 224 | (A_BCM1480_DUART(chan) + \ |
225 | + (reg)) | 225 | BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) |
226 | #define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) | 226 | #define A_BCM1480_DUART_CTRLREG(chan, reg) \ |
227 | 227 | (A_BCM1480_DUART(chan) + \ | |
228 | #define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) | 228 | BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) |
229 | #define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) | 229 | |
230 | 230 | #define R_BCM1480_DUART_IMRREG(chan) \ | |
231 | #define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) | 231 | (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) |
232 | #define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) | 232 | #define R_BCM1480_DUART_ISRREG(chan) \ |
233 | #define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT) | 233 | (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) |
234 | |||
235 | #define A_BCM1480_DUART_IMRREG(chan) \ | ||
236 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) | ||
237 | #define A_BCM1480_DUART_ISRREG(chan) \ | ||
238 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan))) | ||
239 | |||
240 | #define A_BCM1480_DUART_IN_PORT(chan) \ | ||
241 | (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT)) | ||
234 | 242 | ||
235 | /* | 243 | /* |
236 | * These constants are the absolute addresses. | 244 | * These constants are the absolute addresses. |
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index da7c188993c9..220b7e94f1bf 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h | |||
@@ -272,59 +272,69 @@ | |||
272 | ********************************************************************* */ | 272 | ********************************************************************* */ |
273 | 273 | ||
274 | 274 | ||
275 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | 275 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ |
276 | #define R_DUART_NUM_PORTS 2 | 276 | #define R_DUART_NUM_PORTS 2 |
277 | 277 | ||
278 | #define A_DUART 0x0010060000 | 278 | #define A_DUART 0x0010060000 |
279 | 279 | ||
280 | #define DUART_CHANREG_SPACING 0x100 | 280 | #define DUART_CHANREG_SPACING 0x100 |
281 | #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) | 281 | |
282 | #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) | 282 | #define A_DUART_CHANREG(chan, reg) \ |
283 | (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) | ||
283 | #endif /* 1250 & 112x */ | 284 | #endif /* 1250 & 112x */ |
284 | 285 | ||
285 | #define R_DUART_MODE_REG_1 0x100 | 286 | #define R_DUART_MODE_REG_1 0x000 |
286 | #define R_DUART_MODE_REG_2 0x110 | 287 | #define R_DUART_MODE_REG_2 0x010 |
287 | #define R_DUART_STATUS 0x120 | 288 | #define R_DUART_STATUS 0x020 |
288 | #define R_DUART_CLK_SEL 0x130 | 289 | #define R_DUART_CLK_SEL 0x030 |
289 | #define R_DUART_CMD 0x150 | 290 | #define R_DUART_CMD 0x050 |
290 | #define R_DUART_RX_HOLD 0x160 | 291 | #define R_DUART_RX_HOLD 0x060 |
291 | #define R_DUART_TX_HOLD 0x170 | 292 | #define R_DUART_TX_HOLD 0x070 |
292 | 293 | ||
293 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | 294 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
294 | #define R_DUART_FULL_CTL 0x140 | 295 | #define R_DUART_FULL_CTL 0x040 |
295 | #define R_DUART_OPCR_X 0x180 | 296 | #define R_DUART_OPCR_X 0x080 |
296 | #define R_DUART_AUXCTL_X 0x190 | 297 | #define R_DUART_AUXCTL_X 0x090 |
297 | #endif /* 1250 PASS2 || 112x PASS1 || 1480*/ | 298 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
298 | 299 | ||
299 | 300 | ||
300 | /* | 301 | /* |
301 | * The IMR and ISR can't be addressed with A_DUART_CHANREG, | 302 | * The IMR and ISR can't be addressed with A_DUART_CHANREG, |
302 | * so use this macro instead. | 303 | * so use these macros instead. |
303 | */ | 304 | */ |
304 | 305 | ||
305 | #define R_DUART_AUX_CTRL 0x310 | 306 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ |
306 | #define R_DUART_ISR_A 0x320 | 307 | #define DUART_IMRISR_SPACING 0x20 |
307 | #define R_DUART_IMR_A 0x330 | 308 | #define DUART_INCHNG_SPACING 0x10 |
308 | #define R_DUART_ISR_B 0x340 | ||
309 | #define R_DUART_IMR_B 0x350 | ||
310 | #define R_DUART_OUT_PORT 0x360 | ||
311 | #define R_DUART_OPCR 0x370 | ||
312 | #define R_DUART_IN_PORT 0x380 | ||
313 | 309 | ||
314 | #define R_DUART_SET_OPR 0x3B0 | 310 | #define A_DUART_CTRLREG(reg) \ |
315 | #define R_DUART_CLEAR_OPR 0x3C0 | 311 | (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) |
316 | 312 | ||
317 | #define DUART_IMRISR_SPACING 0x20 | 313 | #define R_DUART_IMRREG(chan) \ |
314 | (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) | ||
315 | #define R_DUART_ISRREG(chan) \ | ||
316 | (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) | ||
317 | #define R_DUART_INCHREG(chan) \ | ||
318 | (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) | ||
318 | 319 | ||
319 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | 320 | #define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) |
320 | #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) | 321 | #define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) |
321 | #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) | 322 | #define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) |
322 | |||
323 | #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) | ||
324 | #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) | ||
325 | #endif /* 1250 & 112x */ | 323 | #endif /* 1250 & 112x */ |
326 | 324 | ||
327 | 325 | #define R_DUART_AUX_CTRL 0x010 | |
326 | #define R_DUART_ISR_A 0x020 | ||
327 | #define R_DUART_IMR_A 0x030 | ||
328 | #define R_DUART_ISR_B 0x040 | ||
329 | #define R_DUART_IMR_B 0x050 | ||
330 | #define R_DUART_OUT_PORT 0x060 | ||
331 | #define R_DUART_OPCR 0x070 | ||
332 | #define R_DUART_IN_PORT 0x080 | ||
333 | |||
334 | #define R_DUART_SET_OPR 0x0B0 | ||
335 | #define R_DUART_CLEAR_OPR 0x0C0 | ||
336 | #define R_DUART_IN_CHNG_A 0x0D0 | ||
337 | #define R_DUART_IN_CHNG_B 0x0E0 | ||
328 | 338 | ||
329 | 339 | ||
330 | /* | 340 | /* |
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index e87045e62bf0..cf74fedcbef1 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h | |||
@@ -75,7 +75,8 @@ | |||
75 | #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) | 75 | #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) |
76 | #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) | 76 | #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) |
77 | 77 | ||
78 | #define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ | 78 | #define M_DUART_TX_IRQ_SEL_TXRDY 0 |
79 | #define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) | ||
79 | 80 | ||
80 | #define M_DUART_RX_IRQ_SEL_RXRDY 0 | 81 | #define M_DUART_RX_IRQ_SEL_RXRDY 0 |
81 | #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) | 82 | #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) |
@@ -246,10 +247,13 @@ | |||
246 | 247 | ||
247 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) | 248 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) |
248 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) | 249 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) |
250 | #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) | ||
251 | |||
249 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) | 252 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) |
250 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) | 253 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) |
251 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) | 254 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) |
252 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) | 255 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) |
256 | #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) | ||
253 | 257 | ||
254 | /* | 258 | /* |
255 | * DUART Channel A Interrupt Status Register (Table 10-17) | 259 | * DUART Channel A Interrupt Status Register (Table 10-17) |
@@ -262,6 +266,7 @@ | |||
262 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) | 266 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) |
263 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) | 267 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) |
264 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) | 268 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) |
269 | #define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) | ||
265 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) | 270 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) |
266 | 271 | ||
267 | /* | 272 | /* |
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 1608fd71d6f7..13aef6af422c 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h | |||
@@ -49,13 +49,6 @@ extern struct call_data_struct *call_data; | |||
49 | extern cpumask_t phys_cpu_present_map; | 49 | extern cpumask_t phys_cpu_present_map; |
50 | #define cpu_possible_map phys_cpu_present_map | 50 | #define cpu_possible_map phys_cpu_present_map |
51 | 51 | ||
52 | extern cpumask_t cpu_callout_map; | ||
53 | /* We don't mark CPUs online until __cpu_up(), so we need another measure */ | ||
54 | static inline int num_booting_cpus(void) | ||
55 | { | ||
56 | return cpus_weight(cpu_callout_map); | ||
57 | } | ||
58 | |||
59 | /* | 52 | /* |
60 | * These are defined by the board-specific code. | 53 | * These are defined by the board-specific code. |
61 | */ | 54 | */ |
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index f257509b914f..ddaf36a1e389 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h | |||
@@ -146,9 +146,6 @@ extern unsigned int sni_brd_type; | |||
146 | #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE | 146 | #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE |
147 | #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) | 147 | #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) |
148 | 148 | ||
149 | #define SNI_DS1216_A20R_BASE 0xbc081ffc | ||
150 | #define SNI_DS1216_RM200_BASE 0xbcd41ffc | ||
151 | |||
152 | #define SNI_PCIT_INT_REG 0xbfff000c | 149 | #define SNI_PCIT_INT_REG 0xbfff000c |
153 | 150 | ||
154 | #define SNI_PCIT_INT_START 24 | 151 | #define SNI_PCIT_INT_START 24 |
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 35e431cd796b..bb897016c491 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h | |||
@@ -67,7 +67,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) | |||
67 | : "memory"); | 67 | : "memory"); |
68 | } | 68 | } |
69 | 69 | ||
70 | smp_mb(); | 70 | smp_llsc_mb(); |
71 | } | 71 | } |
72 | 72 | ||
73 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | 73 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) |
@@ -118,7 +118,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) | |||
118 | : "memory"); | 118 | : "memory"); |
119 | } | 119 | } |
120 | 120 | ||
121 | smp_mb(); | 121 | smp_llsc_mb(); |
122 | 122 | ||
123 | return res == 0; | 123 | return res == 0; |
124 | } | 124 | } |
@@ -183,7 +183,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) | |||
183 | : "memory"); | 183 | : "memory"); |
184 | } | 184 | } |
185 | 185 | ||
186 | smp_mb(); | 186 | smp_llsc_mb(); |
187 | } | 187 | } |
188 | 188 | ||
189 | /* Note the use of sub, not subu which will make the kernel die with an | 189 | /* Note the use of sub, not subu which will make the kernel die with an |
@@ -193,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) | |||
193 | { | 193 | { |
194 | unsigned int tmp; | 194 | unsigned int tmp; |
195 | 195 | ||
196 | smp_mb(); | 196 | smp_llsc_mb(); |
197 | 197 | ||
198 | if (R10000_LLSC_WAR) { | 198 | if (R10000_LLSC_WAR) { |
199 | __asm__ __volatile__( | 199 | __asm__ __volatile__( |
@@ -262,7 +262,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) | |||
262 | : "memory"); | 262 | : "memory"); |
263 | } | 263 | } |
264 | 264 | ||
265 | smp_mb(); | 265 | smp_llsc_mb(); |
266 | } | 266 | } |
267 | 267 | ||
268 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | 268 | static inline void __raw_write_unlock(raw_rwlock_t *rw) |
@@ -293,7 +293,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) | |||
293 | " .set reorder \n" | 293 | " .set reorder \n" |
294 | " beqzl %1, 1b \n" | 294 | " beqzl %1, 1b \n" |
295 | " nop \n" | 295 | " nop \n" |
296 | __WEAK_ORDERING_MB | 296 | __WEAK_LLSC_MB |
297 | " li %2, 1 \n" | 297 | " li %2, 1 \n" |
298 | "2: \n" | 298 | "2: \n" |
299 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) | 299 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) |
@@ -310,7 +310,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) | |||
310 | " beqz %1, 1b \n" | 310 | " beqz %1, 1b \n" |
311 | " nop \n" | 311 | " nop \n" |
312 | " .set reorder \n" | 312 | " .set reorder \n" |
313 | __WEAK_ORDERING_MB | 313 | __WEAK_LLSC_MB |
314 | " li %2, 1 \n" | 314 | " li %2, 1 \n" |
315 | "2: \n" | 315 | "2: \n" |
316 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) | 316 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) |
@@ -336,7 +336,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) | |||
336 | " sc %1, %0 \n" | 336 | " sc %1, %0 \n" |
337 | " beqzl %1, 1b \n" | 337 | " beqzl %1, 1b \n" |
338 | " nop \n" | 338 | " nop \n" |
339 | __WEAK_ORDERING_MB | 339 | __WEAK_LLSC_MB |
340 | " li %2, 1 \n" | 340 | " li %2, 1 \n" |
341 | " .set reorder \n" | 341 | " .set reorder \n" |
342 | "2: \n" | 342 | "2: \n" |
@@ -354,7 +354,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) | |||
354 | " beqz %1, 3f \n" | 354 | " beqz %1, 3f \n" |
355 | " li %2, 1 \n" | 355 | " li %2, 1 \n" |
356 | "2: \n" | 356 | "2: \n" |
357 | __WEAK_ORDERING_MB | 357 | __WEAK_LLSC_MB |
358 | " .subsection 2 \n" | 358 | " .subsection 2 \n" |
359 | "3: b 1b \n" | 359 | "3: b 1b \n" |
360 | " li %2, 0 \n" | 360 | " li %2, 0 \n" |
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 7afa1fdf70ca..ed33366b85b8 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h | |||
@@ -17,6 +17,18 @@ | |||
17 | #include <asm/mipsregs.h> | 17 | #include <asm/mipsregs.h> |
18 | #include <asm/asm-offsets.h> | 18 | #include <asm/asm-offsets.h> |
19 | 19 | ||
20 | /* | ||
21 | * For SMTC kernel, global IE should be left set, and interrupts | ||
22 | * controlled exclusively via IXMT. | ||
23 | */ | ||
24 | #ifdef CONFIG_MIPS_MT_SMTC | ||
25 | #define STATMASK 0x1e | ||
26 | #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
27 | #define STATMASK 0x3f | ||
28 | #else | ||
29 | #define STATMASK 0x1f | ||
30 | #endif | ||
31 | |||
20 | #ifdef CONFIG_MIPS_MT_SMTC | 32 | #ifdef CONFIG_MIPS_MT_SMTC |
21 | #include <asm/mipsmtregs.h> | 33 | #include <asm/mipsmtregs.h> |
22 | #endif /* CONFIG_MIPS_MT_SMTC */ | 34 | #endif /* CONFIG_MIPS_MT_SMTC */ |
@@ -236,10 +248,10 @@ | |||
236 | .set reorder | 248 | .set reorder |
237 | .set noat | 249 | .set noat |
238 | mfc0 a0, CP0_STATUS | 250 | mfc0 a0, CP0_STATUS |
239 | ori a0, 0x1f | ||
240 | xori a0, 0x1f | ||
241 | mtc0 a0, CP0_STATUS | ||
242 | li v1, 0xff00 | 251 | li v1, 0xff00 |
252 | ori a0, STATMASK | ||
253 | xori a0, STATMASK | ||
254 | mtc0 a0, CP0_STATUS | ||
243 | and a0, v1 | 255 | and a0, v1 |
244 | LONG_L v0, PT_STATUS(sp) | 256 | LONG_L v0, PT_STATUS(sp) |
245 | nor v1, $0, v1 | 257 | nor v1, $0, v1 |
@@ -249,10 +261,6 @@ | |||
249 | LONG_L $31, PT_R31(sp) | 261 | LONG_L $31, PT_R31(sp) |
250 | LONG_L $28, PT_R28(sp) | 262 | LONG_L $28, PT_R28(sp) |
251 | LONG_L $25, PT_R25(sp) | 263 | LONG_L $25, PT_R25(sp) |
252 | #ifdef CONFIG_64BIT | ||
253 | LONG_L $8, PT_R8(sp) | ||
254 | LONG_L $9, PT_R9(sp) | ||
255 | #endif | ||
256 | LONG_L $7, PT_R7(sp) | 264 | LONG_L $7, PT_R7(sp) |
257 | LONG_L $6, PT_R6(sp) | 265 | LONG_L $6, PT_R6(sp) |
258 | LONG_L $5, PT_R5(sp) | 266 | LONG_L $5, PT_R5(sp) |
@@ -273,16 +281,6 @@ | |||
273 | .endm | 281 | .endm |
274 | 282 | ||
275 | #else | 283 | #else |
276 | /* | ||
277 | * For SMTC kernel, global IE should be left set, and interrupts | ||
278 | * controlled exclusively via IXMT. | ||
279 | */ | ||
280 | |||
281 | #ifdef CONFIG_MIPS_MT_SMTC | ||
282 | #define STATMASK 0x1e | ||
283 | #else | ||
284 | #define STATMASK 0x1f | ||
285 | #endif | ||
286 | .macro RESTORE_SOME | 284 | .macro RESTORE_SOME |
287 | .set push | 285 | .set push |
288 | .set reorder | 286 | .set reorder |
@@ -385,9 +383,9 @@ | |||
385 | .macro CLI | 383 | .macro CLI |
386 | #if !defined(CONFIG_MIPS_MT_SMTC) | 384 | #if !defined(CONFIG_MIPS_MT_SMTC) |
387 | mfc0 t0, CP0_STATUS | 385 | mfc0 t0, CP0_STATUS |
388 | li t1, ST0_CU0 | 0x1f | 386 | li t1, ST0_CU0 | STATMASK |
389 | or t0, t1 | 387 | or t0, t1 |
390 | xori t0, 0x1f | 388 | xori t0, STATMASK |
391 | mtc0 t0, CP0_STATUS | 389 | mtc0 t0, CP0_STATUS |
392 | #else /* CONFIG_MIPS_MT_SMTC */ | 390 | #else /* CONFIG_MIPS_MT_SMTC */ |
393 | /* | 391 | /* |
@@ -420,9 +418,9 @@ | |||
420 | .macro STI | 418 | .macro STI |
421 | #if !defined(CONFIG_MIPS_MT_SMTC) | 419 | #if !defined(CONFIG_MIPS_MT_SMTC) |
422 | mfc0 t0, CP0_STATUS | 420 | mfc0 t0, CP0_STATUS |
423 | li t1, ST0_CU0 | 0x1f | 421 | li t1, ST0_CU0 | STATMASK |
424 | or t0, t1 | 422 | or t0, t1 |
425 | xori t0, 0x1e | 423 | xori t0, STATMASK & ~1 |
426 | mtc0 t0, CP0_STATUS | 424 | mtc0 t0, CP0_STATUS |
427 | #else /* CONFIG_MIPS_MT_SMTC */ | 425 | #else /* CONFIG_MIPS_MT_SMTC */ |
428 | /* | 426 | /* |
@@ -451,7 +449,8 @@ | |||
451 | .endm | 449 | .endm |
452 | 450 | ||
453 | /* | 451 | /* |
454 | * Just move to kernel mode and leave interrupts as they are. | 452 | * Just move to kernel mode and leave interrupts as they are. Note |
453 | * for the R3000 this means copying the previous enable from IEp. | ||
455 | * Set cp0 enable bit as sign that we're running on the kernel stack | 454 | * Set cp0 enable bit as sign that we're running on the kernel stack |
456 | */ | 455 | */ |
457 | .macro KMODE | 456 | .macro KMODE |
@@ -482,9 +481,14 @@ | |||
482 | move ra, t0 | 481 | move ra, t0 |
483 | #endif /* CONFIG_MIPS_MT_SMTC */ | 482 | #endif /* CONFIG_MIPS_MT_SMTC */ |
484 | mfc0 t0, CP0_STATUS | 483 | mfc0 t0, CP0_STATUS |
485 | li t1, ST0_CU0 | 0x1e | 484 | li t1, ST0_CU0 | (STATMASK & ~1) |
485 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
486 | andi t2, t0, ST0_IEP | ||
487 | srl t2, 2 | ||
488 | or t0, t2 | ||
489 | #endif | ||
486 | or t0, t1 | 490 | or t0, t1 |
487 | xori t0, 0x1e | 491 | xori t0, STATMASK & ~1 |
488 | mtc0 t0, CP0_STATUS | 492 | mtc0 t0, CP0_STATUS |
489 | #ifdef CONFIG_MIPS_MT_SMTC | 493 | #ifdef CONFIG_MIPS_MT_SMTC |
490 | _ehb | 494 | _ehb |
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index bb0b289dbc9e..8d0b1cd4a45e 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h | |||
@@ -44,7 +44,7 @@ struct task_struct; | |||
44 | * different thread. | 44 | * different thread. |
45 | */ | 45 | */ |
46 | 46 | ||
47 | #define switch_to(prev,next,last) \ | 47 | #define __mips_mt_fpaff_switch_to(prev) \ |
48 | do { \ | 48 | do { \ |
49 | if (cpu_has_fpu && \ | 49 | if (cpu_has_fpu && \ |
50 | (prev->thread.mflags & MF_FPUBOUND) && \ | 50 | (prev->thread.mflags & MF_FPUBOUND) && \ |
@@ -52,34 +52,24 @@ do { \ | |||
52 | prev->thread.mflags &= ~MF_FPUBOUND; \ | 52 | prev->thread.mflags &= ~MF_FPUBOUND; \ |
53 | prev->cpus_allowed = prev->thread.user_cpus_allowed; \ | 53 | prev->cpus_allowed = prev->thread.user_cpus_allowed; \ |
54 | } \ | 54 | } \ |
55 | if (cpu_has_dsp) \ | ||
56 | __save_dsp(prev); \ | ||
57 | next->thread.emulated_fp = 0; \ | 55 | next->thread.emulated_fp = 0; \ |
58 | (last) = resume(prev, next, task_thread_info(next)); \ | ||
59 | if (cpu_has_dsp) \ | ||
60 | __restore_dsp(current); \ | ||
61 | } while(0) | 56 | } while(0) |
62 | 57 | ||
63 | #else | 58 | #else |
59 | #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) | ||
60 | #endif | ||
61 | |||
64 | #define switch_to(prev,next,last) \ | 62 | #define switch_to(prev,next,last) \ |
65 | do { \ | 63 | do { \ |
64 | __mips_mt_fpaff_switch_to(prev); \ | ||
66 | if (cpu_has_dsp) \ | 65 | if (cpu_has_dsp) \ |
67 | __save_dsp(prev); \ | 66 | __save_dsp(prev); \ |
68 | (last) = resume(prev, next, task_thread_info(next)); \ | 67 | (last) = resume(prev, next, task_thread_info(next)); \ |
69 | if (cpu_has_dsp) \ | 68 | if (cpu_has_dsp) \ |
70 | __restore_dsp(current); \ | 69 | __restore_dsp(current); \ |
70 | if (cpu_has_userlocal) \ | ||
71 | write_c0_userlocal(task_thread_info(current)->tp_value);\ | ||
71 | } while(0) | 72 | } while(0) |
72 | #endif | ||
73 | |||
74 | /* | ||
75 | * On SMP systems, when the scheduler does migration-cost autodetection, | ||
76 | * it needs a way to flush as much of the CPU's caches as possible. | ||
77 | * | ||
78 | * TODO: fill this in! | ||
79 | */ | ||
80 | static inline void sched_cacheflush(void) | ||
81 | { | ||
82 | } | ||
83 | 73 | ||
84 | static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) | 74 | static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) |
85 | { | 75 | { |
@@ -127,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) | |||
127 | raw_local_irq_restore(flags); /* implies memory barrier */ | 117 | raw_local_irq_restore(flags); /* implies memory barrier */ |
128 | } | 118 | } |
129 | 119 | ||
130 | smp_mb(); | 120 | smp_llsc_mb(); |
131 | 121 | ||
132 | return retval; | 122 | return retval; |
133 | } | 123 | } |
@@ -175,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) | |||
175 | raw_local_irq_restore(flags); /* implies memory barrier */ | 165 | raw_local_irq_restore(flags); /* implies memory barrier */ |
176 | } | 166 | } |
177 | 167 | ||
178 | smp_mb(); | 168 | smp_llsc_mb(); |
179 | 169 | ||
180 | return retval; | 170 | return retval; |
181 | } | 171 | } |
@@ -256,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, | |||
256 | raw_local_irq_restore(flags); /* implies memory barrier */ | 246 | raw_local_irq_restore(flags); /* implies memory barrier */ |
257 | } | 247 | } |
258 | 248 | ||
259 | smp_mb(); | 249 | smp_llsc_mb(); |
260 | 250 | ||
261 | return retval; | 251 | return retval; |
262 | } | 252 | } |
@@ -362,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, | |||
362 | raw_local_irq_restore(flags); /* implies memory barrier */ | 352 | raw_local_irq_restore(flags); /* implies memory barrier */ |
363 | } | 353 | } |
364 | 354 | ||
365 | smp_mb(); | 355 | smp_llsc_mb(); |
366 | 356 | ||
367 | return retval; | 357 | return retval; |
368 | } | 358 | } |
@@ -480,6 +470,6 @@ extern int stop_a_enabled; | |||
480 | */ | 470 | */ |
481 | #define __ARCH_WANT_UNLOCKED_CTXSW | 471 | #define __ARCH_WANT_UNLOCKED_CTXSW |
482 | 472 | ||
483 | #define arch_align_stack(x) (x) | 473 | extern unsigned long arch_align_stack(unsigned long sp); |
484 | 474 | ||
485 | #endif /* _ASM_SYSTEM_H */ | 475 | #endif /* _ASM_SYSTEM_H */ |
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 0bbe07b42a07..5bfdc3b64510 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h | |||
@@ -30,6 +30,17 @@ struct termios { | |||
30 | cc_t c_cc[NCCS]; /* control characters */ | 30 | cc_t c_cc[NCCS]; /* control characters */ |
31 | }; | 31 | }; |
32 | 32 | ||
33 | struct termios2 { | ||
34 | tcflag_t c_iflag; /* input mode flags */ | ||
35 | tcflag_t c_oflag; /* output mode flags */ | ||
36 | tcflag_t c_cflag; /* control mode flags */ | ||
37 | tcflag_t c_lflag; /* local mode flags */ | ||
38 | cc_t c_line; /* line discipline */ | ||
39 | cc_t c_cc[NCCS]; /* control characters */ | ||
40 | speed_t c_ispeed; /* input speed */ | ||
41 | speed_t c_ospeed; /* output speed */ | ||
42 | }; | ||
43 | |||
33 | struct ktermios { | 44 | struct ktermios { |
34 | tcflag_t c_iflag; /* input mode flags */ | 45 | tcflag_t c_iflag; /* input mode flags */ |
35 | tcflag_t c_oflag; /* output mode flags */ | 46 | tcflag_t c_oflag; /* output mode flags */ |
diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h index fff7a73e22d0..bb8f5c29c3d9 100644 --- a/include/asm-mips/tlbdebug.h +++ b/include/asm-mips/tlbdebug.h | |||
@@ -11,10 +11,6 @@ | |||
11 | /* | 11 | /* |
12 | * TLB debugging functions: | 12 | * TLB debugging functions: |
13 | */ | 13 | */ |
14 | extern void dump_tlb(int first, int last); | ||
15 | extern void dump_tlb_all(void); | 14 | extern void dump_tlb_all(void); |
16 | extern void dump_tlb_wired(void); | ||
17 | extern void dump_tlb_addr(unsigned long addr); | ||
18 | extern void dump_tlb_nonwired(void); | ||
19 | 15 | ||
20 | #endif /* __ASM_TLBDEBUG_H */ | 16 | #endif /* __ASM_TLBDEBUG_H */ |
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 0fbedafdcea8..74e7d8061e58 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h | |||
@@ -105,12 +105,6 @@ | |||
105 | #define rbtx4938_pcireset_ptr \ | 105 | #define rbtx4938_pcireset_ptr \ |
106 | ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) | 106 | ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) |
107 | 107 | ||
108 | /* SPI */ | ||
109 | #define RBTX4938_SEEPROM1_CHIPID 0 | ||
110 | #define RBTX4938_SEEPROM2_CHIPID 1 | ||
111 | #define RBTX4938_SEEPROM3_CHIPID 2 | ||
112 | #define RBTX4938_SRTC_CHIPID 3 | ||
113 | |||
114 | /* | 108 | /* |
115 | * IRQ mappings | 109 | * IRQ mappings |
116 | */ | 110 | */ |
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h index 0dbbab820a5a..6a60c83e152b 100644 --- a/include/asm-mips/tx4938/spi.h +++ b/include/asm-mips/tx4938/spi.h | |||
@@ -14,61 +14,7 @@ | |||
14 | #ifndef __ASM_TX_BOARDS_TX4938_SPI_H | 14 | #ifndef __ASM_TX_BOARDS_TX4938_SPI_H |
15 | #define __ASM_TX_BOARDS_TX4938_SPI_H | 15 | #define __ASM_TX_BOARDS_TX4938_SPI_H |
16 | 16 | ||
17 | /* SPI */ | 17 | extern int spi_eeprom_register(int chipid); |
18 | struct spi_dev_desc { | ||
19 | unsigned int baud; | ||
20 | unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ | ||
21 | unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ | ||
22 | unsigned int polarity:1; /* 0:High-Active */ | ||
23 | unsigned int phase:1; /* 0:Sample-Then-Shift */ | ||
24 | }; | ||
25 | |||
26 | extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; | ||
27 | extern void txx9_spi_irqinit(int irc_irq) __init; | ||
28 | extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, | ||
29 | unsigned char **inbufs, unsigned int *incounts, | ||
30 | unsigned char **outbufs, unsigned int *outcounts, | ||
31 | int cansleep); | ||
32 | extern int spi_eeprom_write_enable(int chipid, int enable); | ||
33 | extern int spi_eeprom_read_status(int chipid); | ||
34 | extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); | 18 | extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); |
35 | extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); | ||
36 | extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; | ||
37 | |||
38 | #define TXX9_IMCLK (txx9_gbus_clock / 2) | ||
39 | |||
40 | /* | ||
41 | * SPI | ||
42 | */ | ||
43 | |||
44 | /* SPMCR : SPI Master Control */ | ||
45 | #define TXx9_SPMCR_OPMODE 0xc0 | ||
46 | #define TXx9_SPMCR_CONFIG 0x40 | ||
47 | #define TXx9_SPMCR_ACTIVE 0x80 | ||
48 | #define TXx9_SPMCR_SPSTP 0x02 | ||
49 | #define TXx9_SPMCR_BCLR 0x01 | ||
50 | |||
51 | /* SPCR0 : SPI Status */ | ||
52 | #define TXx9_SPCR0_TXIFL_MASK 0xc000 | ||
53 | #define TXx9_SPCR0_RXIFL_MASK 0x3000 | ||
54 | #define TXx9_SPCR0_SIDIE 0x0800 | ||
55 | #define TXx9_SPCR0_SOEIE 0x0400 | ||
56 | #define TXx9_SPCR0_RBSIE 0x0200 | ||
57 | #define TXx9_SPCR0_TBSIE 0x0100 | ||
58 | #define TXx9_SPCR0_IFSPSE 0x0010 | ||
59 | #define TXx9_SPCR0_SBOS 0x0004 | ||
60 | #define TXx9_SPCR0_SPHA 0x0002 | ||
61 | #define TXx9_SPCR0_SPOL 0x0001 | ||
62 | |||
63 | /* SPSR : SPI Status */ | ||
64 | #define TXx9_SPSR_TBSI 0x8000 | ||
65 | #define TXx9_SPSR_RBSI 0x4000 | ||
66 | #define TXx9_SPSR_TBS_MASK 0x3800 | ||
67 | #define TXx9_SPSR_RBS_MASK 0x0700 | ||
68 | #define TXx9_SPSR_SPOE 0x0080 | ||
69 | #define TXx9_SPSR_IFSD 0x0008 | ||
70 | #define TXx9_SPSR_SIDLE 0x0004 | ||
71 | #define TXx9_SPSR_STRDY 0x0002 | ||
72 | #define TXx9_SPSR_SRRDY 0x0001 | ||
73 | 19 | ||
74 | #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ | 20 | #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ |
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 2f1087b3a202..ed16de0a6398 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h | |||
@@ -336,16 +336,20 @@ | |||
336 | #define __NR_epoll_pwait (__NR_Linux + 313) | 336 | #define __NR_epoll_pwait (__NR_Linux + 313) |
337 | #define __NR_ioprio_set (__NR_Linux + 314) | 337 | #define __NR_ioprio_set (__NR_Linux + 314) |
338 | #define __NR_ioprio_get (__NR_Linux + 315) | 338 | #define __NR_ioprio_get (__NR_Linux + 315) |
339 | #define __NR_utimensat (__NR_Linux + 316) | ||
340 | #define __NR_signalfd (__NR_Linux + 317) | ||
341 | #define __NR_timerfd (__NR_Linux + 318) | ||
342 | #define __NR_eventfd (__NR_Linux + 319) | ||
339 | 343 | ||
340 | /* | 344 | /* |
341 | * Offset of the last Linux o32 flavoured syscall | 345 | * Offset of the last Linux o32 flavoured syscall |
342 | */ | 346 | */ |
343 | #define __NR_Linux_syscalls 315 | 347 | #define __NR_Linux_syscalls 319 |
344 | 348 | ||
345 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ | 349 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
346 | 350 | ||
347 | #define __NR_O32_Linux 4000 | 351 | #define __NR_O32_Linux 4000 |
348 | #define __NR_O32_Linux_syscalls 315 | 352 | #define __NR_O32_Linux_syscalls 319 |
349 | 353 | ||
350 | #if _MIPS_SIM == _MIPS_SIM_ABI64 | 354 | #if _MIPS_SIM == _MIPS_SIM_ABI64 |
351 | 355 | ||
@@ -628,16 +632,20 @@ | |||
628 | #define __NR_epoll_pwait (__NR_Linux + 272) | 632 | #define __NR_epoll_pwait (__NR_Linux + 272) |
629 | #define __NR_ioprio_set (__NR_Linux + 273) | 633 | #define __NR_ioprio_set (__NR_Linux + 273) |
630 | #define __NR_ioprio_get (__NR_Linux + 274) | 634 | #define __NR_ioprio_get (__NR_Linux + 274) |
635 | #define __NR_utimensat (__NR_Linux + 275) | ||
636 | #define __NR_signalfd (__NR_Linux + 276) | ||
637 | #define __NR_timerfd (__NR_Linux + 277) | ||
638 | #define __NR_eventfd (__NR_Linux + 278) | ||
631 | 639 | ||
632 | /* | 640 | /* |
633 | * Offset of the last Linux 64-bit flavoured syscall | 641 | * Offset of the last Linux 64-bit flavoured syscall |
634 | */ | 642 | */ |
635 | #define __NR_Linux_syscalls 274 | 643 | #define __NR_Linux_syscalls 278 |
636 | 644 | ||
637 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ | 645 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ |
638 | 646 | ||
639 | #define __NR_64_Linux 5000 | 647 | #define __NR_64_Linux 5000 |
640 | #define __NR_64_Linux_syscalls 274 | 648 | #define __NR_64_Linux_syscalls 278 |
641 | 649 | ||
642 | #if _MIPS_SIM == _MIPS_SIM_NABI32 | 650 | #if _MIPS_SIM == _MIPS_SIM_NABI32 |
643 | 651 | ||
@@ -924,16 +932,20 @@ | |||
924 | #define __NR_epoll_pwait (__NR_Linux + 276) | 932 | #define __NR_epoll_pwait (__NR_Linux + 276) |
925 | #define __NR_ioprio_set (__NR_Linux + 277) | 933 | #define __NR_ioprio_set (__NR_Linux + 277) |
926 | #define __NR_ioprio_get (__NR_Linux + 278) | 934 | #define __NR_ioprio_get (__NR_Linux + 278) |
935 | #define __NR_utimensat (__NR_Linux + 279) | ||
936 | #define __NR_signalfd (__NR_Linux + 280) | ||
937 | #define __NR_timerfd (__NR_Linux + 281) | ||
938 | #define __NR_eventfd (__NR_Linux + 282) | ||
927 | 939 | ||
928 | /* | 940 | /* |
929 | * Offset of the last N32 flavoured syscall | 941 | * Offset of the last N32 flavoured syscall |
930 | */ | 942 | */ |
931 | #define __NR_Linux_syscalls 278 | 943 | #define __NR_Linux_syscalls 282 |
932 | 944 | ||
933 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ | 945 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ |
934 | 946 | ||
935 | #define __NR_N32_Linux 6000 | 947 | #define __NR_N32_Linux 6000 |
936 | #define __NR_N32_Linux_syscalls 278 | 948 | #define __NR_N32_Linux_syscalls 282 |
937 | 949 | ||
938 | #ifdef __KERNEL__ | 950 | #ifdef __KERNEL__ |
939 | 951 | ||
@@ -949,7 +961,6 @@ | |||
949 | #define __ARCH_WANT_SYS_UTIME | 961 | #define __ARCH_WANT_SYS_UTIME |
950 | #define __ARCH_WANT_SYS_WAITPID | 962 | #define __ARCH_WANT_SYS_WAITPID |
951 | #define __ARCH_WANT_SYS_SOCKETCALL | 963 | #define __ARCH_WANT_SYS_SOCKETCALL |
952 | #define __ARCH_WANT_SYS_FADVISE64 | ||
953 | #define __ARCH_WANT_SYS_GETPGRP | 964 | #define __ARCH_WANT_SYS_GETPGRP |
954 | #define __ARCH_WANT_SYS_LLSEEK | 965 | #define __ARCH_WANT_SYS_LLSEEK |
955 | #define __ARCH_WANT_SYS_NICE | 966 | #define __ARCH_WANT_SYS_NICE |
@@ -966,6 +977,22 @@ | |||
966 | # define __ARCH_WANT_COMPAT_SYS_TIME | 977 | # define __ARCH_WANT_COMPAT_SYS_TIME |
967 | # endif | 978 | # endif |
968 | 979 | ||
980 | /* whitelists for checksyscalls */ | ||
981 | #define __IGNORE_select | ||
982 | #define __IGNORE_vfork | ||
983 | #define __IGNORE_time | ||
984 | #define __IGNORE_uselib | ||
985 | #define __IGNORE_fadvise64_64 | ||
986 | #define __IGNORE_getdents64 | ||
987 | #if _MIPS_SIM == _MIPS_SIM_NABI32 | ||
988 | #define __IGNORE_truncate64 | ||
989 | #define __IGNORE_ftruncate64 | ||
990 | #define __IGNORE_stat64 | ||
991 | #define __IGNORE_lstat64 | ||
992 | #define __IGNORE_fstat64 | ||
993 | #define __IGNORE_fstatat64 | ||
994 | #endif | ||
995 | |||
969 | #endif /* !__ASSEMBLY__ */ | 996 | #endif /* !__ASSEMBLY__ */ |
970 | 997 | ||
971 | /* | 998 | /* |
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h index 8109cda557dc..0bcdd3a5c256 100644 --- a/include/asm-mips/vr41xx/giu.h +++ b/include/asm-mips/vr41xx/giu.h | |||
@@ -20,6 +20,15 @@ | |||
20 | #ifndef __NEC_VR41XX_GIU_H | 20 | #ifndef __NEC_VR41XX_GIU_H |
21 | #define __NEC_VR41XX_GIU_H | 21 | #define __NEC_VR41XX_GIU_H |
22 | 22 | ||
23 | /* | ||
24 | * NEC VR4100 series GIU platform device IDs. | ||
25 | */ | ||
26 | enum { | ||
27 | GPIO_50PINS_PULLUPDOWN, | ||
28 | GPIO_36PINS, | ||
29 | GPIO_48PINS_EDGE_SELECT, | ||
30 | }; | ||
31 | |||
23 | typedef enum { | 32 | typedef enum { |
24 | IRQ_TRIGGER_LEVEL, | 33 | IRQ_TRIGGER_LEVEL, |
25 | IRQ_TRIGGER_EDGE, | 34 | IRQ_TRIGGER_EDGE, |
diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h index 1fcf6e8082b4..98cdb4096485 100644 --- a/include/asm-mips/vr41xx/siu.h +++ b/include/asm-mips/vr41xx/siu.h | |||
@@ -20,6 +20,8 @@ | |||
20 | #ifndef __NEC_VR41XX_SIU_H | 20 | #ifndef __NEC_VR41XX_SIU_H |
21 | #define __NEC_VR41XX_SIU_H | 21 | #define __NEC_VR41XX_SIU_H |
22 | 22 | ||
23 | #define SIU_PORTS_MAX 2 | ||
24 | |||
23 | typedef enum { | 25 | typedef enum { |
24 | SIU_INTERFACE_RS232C, | 26 | SIU_INTERFACE_RS232C, |
25 | SIU_INTERFACE_IRDA, | 27 | SIU_INTERFACE_IRDA, |
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 13a3502eef44..9de52a5b0f3d 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -169,26 +169,28 @@ | |||
169 | 169 | ||
170 | /* | 170 | /* |
171 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive | 171 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive |
172 | * cache operation unusable on SMP systems. | 172 | * eache operation unusable on SMP systems. |
173 | */ | 173 | */ |
174 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ | 174 | #if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) |
175 | defined(CONFIG_BASLER_EXCITE) | ||
176 | #define RM9000_CDEX_SMP_WAR 1 | 175 | #define RM9000_CDEX_SMP_WAR 1 |
177 | #endif | 176 | #endif |
178 | 177 | ||
179 | /* | 178 | /* |
180 | * The RM9000 has a bug (though PMC-Sierra opposes it being called that) | 179 | * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra |
181 | * where invalid instructions in the same I-cache line worth of instructions | 180 | * opposes it being called that) where invalid instructions in the same |
182 | * being fetched may case spurious exceptions. | 181 | * I-cache line worth of instructions being fetched may case spurious |
182 | * exceptions. | ||
183 | */ | 183 | */ |
184 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ | 184 | #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ |
185 | defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) | 185 | defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \ |
186 | defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \ | ||
187 | defined(CONFIG_WR_PPMC) | ||
186 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | 188 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 |
187 | #endif | 189 | #endif |
188 | 190 | ||
189 | 191 | ||
190 | /* | 192 | /* |
191 | * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that | 193 | * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that |
192 | * may cause ll / sc and lld / scd sequences to execute non-atomically. | 194 | * may cause ll / sc and lld / scd sequences to execute non-atomically. |
193 | */ | 195 | */ |
194 | #ifdef CONFIG_SGI_IP27 | 196 | #ifdef CONFIG_SGI_IP27 |
@@ -196,6 +198,14 @@ | |||
196 | #endif | 198 | #endif |
197 | 199 | ||
198 | /* | 200 | /* |
201 | * 34K core erratum: "Problems Executing the TLBR Instruction" | ||
202 | */ | ||
203 | #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ | ||
204 | defined(CONFIG_PMC_MSP7120_FPGA) | ||
205 | #define MIPS34K_MISSED_ITLB_WAR 1 | ||
206 | #endif | ||
207 | |||
208 | /* | ||
199 | * Workarounds default to off | 209 | * Workarounds default to off |
200 | */ | 210 | */ |
201 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR | 211 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR |
@@ -234,5 +244,8 @@ | |||
234 | #ifndef R10000_LLSC_WAR | 244 | #ifndef R10000_LLSC_WAR |
235 | #define R10000_LLSC_WAR 0 | 245 | #define R10000_LLSC_WAR 0 |
236 | #endif | 246 | #endif |
247 | #ifndef MIPS34K_MISSED_ITLB_WAR | ||
248 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
249 | #endif | ||
237 | 250 | ||
238 | #endif /* _ASM_WAR_H */ | 251 | #endif /* _ASM_WAR_H */ |
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h deleted file mode 100644 index 6aa90cae1114..000000000000 --- a/include/asm-mips/watch.h +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle | ||
7 | */ | ||
8 | #ifndef _ASM_WATCH_H | ||
9 | #define _ASM_WATCH_H | ||
10 | |||
11 | #include <linux/linkage.h> | ||
12 | |||
13 | /* | ||
14 | * Types of reference for watch_set() | ||
15 | */ | ||
16 | enum wref_type { | ||
17 | wr_save = 1, | ||
18 | wr_load = 2 | ||
19 | }; | ||
20 | |||
21 | extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref); | ||
22 | extern asmlinkage void __watch_clear(void); | ||
23 | extern asmlinkage void __watch_reenable(void); | ||
24 | |||
25 | #define watch_set(addr, ref) \ | ||
26 | if (cpu_has_watch) \ | ||
27 | __watch_set(addr, ref) | ||
28 | #define watch_clear() \ | ||
29 | if (cpu_has_watch) \ | ||
30 | __watch_clear() | ||
31 | #define watch_reenable() \ | ||
32 | if (cpu_has_watch) \ | ||
33 | __watch_reenable() | ||
34 | |||
35 | #endif /* _ASM_WATCH_H */ | ||