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-rw-r--r--include/asm-mips/cmp.h18
-rw-r--r--include/asm-mips/cpu.h9
-rw-r--r--include/asm-mips/dec/ioasic.h2
-rw-r--r--include/asm-mips/ds1287.h27
-rw-r--r--include/asm-mips/gcmpregs.h117
-rw-r--r--include/asm-mips/gic.h487
-rw-r--r--include/asm-mips/io.h2
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h4
-rw-r--r--include/asm-mips/jmr3927/tx3927.h2
-rw-r--r--include/asm-mips/jmr3927/txx927.h12
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h26
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h18
-rw-r--r--include/asm-mips/mach-generic/gpio.h6
-rw-r--r--include/asm-mips/mach-ip27/topology.h2
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h18
-rw-r--r--include/asm-mips/mips-boards/generic.h1
-rw-r--r--include/asm-mips/mips-boards/launch.h35
-rw-r--r--include/asm-mips/mips-boards/malta.h23
-rw-r--r--include/asm-mips/mips-boards/maltaint.h27
-rw-r--r--include/asm-mips/mips-boards/maltasmp.h36
-rw-r--r--include/asm-mips/mipsmtregs.h8
-rw-r--r--include/asm-mips/pgtable-32.h4
-rw-r--r--include/asm-mips/pgtable-bits.h91
-rw-r--r--include/asm-mips/pgtable.h57
-rw-r--r--include/asm-mips/r4k-timer.h30
-rw-r--r--include/asm-mips/smp-ops.h1
-rw-r--r--include/asm-mips/smtc.h1
-rw-r--r--include/asm-mips/smvp.h19
-rw-r--r--include/asm-mips/traps.h2
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h58
-rw-r--r--include/asm-mips/tx4938/tx4938.h38
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h54
-rw-r--r--include/asm-mips/txx9pio.h29
33 files changed, 992 insertions, 272 deletions
diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h
new file mode 100644
index 000000000000..89a73fb93ae6
--- /dev/null
+++ b/include/asm-mips/cmp.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_CMP_H
2#define _ASM_CMP_H
3
4/*
5 * Definitions for CMP multitasking on MIPS cores
6 */
7struct task_struct;
8
9extern void cmp_smp_setup(void);
10extern void cmp_smp_finish(void);
11extern void cmp_boot_secondary(int cpu, struct task_struct *t);
12extern void cmp_init_secondary(void);
13extern void cmp_cpus_done(void);
14extern void cmp_prepare_cpus(unsigned int max_cpus);
15
16/* This is platform specific */
17extern void cmp_send_ipi(int cpu, unsigned int action);
18#endif /* _ASM_CMP_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index bf5bbc78a9f7..1c35cac6f35b 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -29,7 +29,7 @@
29#define PRID_COMP_ALCHEMY 0x030000 29#define PRID_COMP_ALCHEMY 0x030000
30#define PRID_COMP_SIBYTE 0x040000 30#define PRID_COMP_SIBYTE 0x040000
31#define PRID_COMP_SANDCRAFT 0x050000 31#define PRID_COMP_SANDCRAFT 0x050000
32#define PRID_COMP_PHILIPS 0x060000 32#define PRID_COMP_NXP 0x060000
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
@@ -89,6 +89,7 @@
89#define PRID_IMP_34K 0x9500 89#define PRID_IMP_34K 0x9500
90#define PRID_IMP_24KE 0x9600 90#define PRID_IMP_24KE 0x9600
91#define PRID_IMP_74K 0x9700 91#define PRID_IMP_74K 0x9700
92#define PRID_IMP_1004K 0x9900
92#define PRID_IMP_LOONGSON1 0x4200 93#define PRID_IMP_LOONGSON1 0x4200
93#define PRID_IMP_LOONGSON2 0x6300 94#define PRID_IMP_LOONGSON2 0x6300
94 95
@@ -194,9 +195,9 @@ enum cpu_type_enum {
194 /* 195 /*
195 * MIPS32 class processors 196 * MIPS32 class processors
196 */ 197 */
197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, 198 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
198 CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550, 199 CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
199 CPU_PR4450, CPU_BCM3302, CPU_BCM4710, 200 CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
200 201
201 /* 202 /*
202 * MIPS64 class processors 203 * MIPS64 class processors
diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h
index 486a5b0a1302..98badd6bf22d 100644
--- a/include/asm-mips/dec/ioasic.h
+++ b/include/asm-mips/dec/ioasic.h
@@ -33,4 +33,6 @@ static inline u32 ioasic_read(unsigned int reg)
33 33
34extern void init_ioasic_irqs(int base); 34extern void init_ioasic_irqs(int base);
35 35
36extern void dec_ioasic_clocksource_init(void);
37
36#endif /* __ASM_DEC_IOASIC_H */ 38#endif /* __ASM_DEC_IOASIC_H */
diff --git a/include/asm-mips/ds1287.h b/include/asm-mips/ds1287.h
new file mode 100644
index 000000000000..ba1702e86931
--- /dev/null
+++ b/include/asm-mips/ds1287.h
@@ -0,0 +1,27 @@
1/*
2 * DS1287 timer functions.
3 *
4 * Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#ifndef __ASM_DS1287_H
21#define __ASM_DS1287_H
22
23extern int ds1287_timer_state(void);
24extern void ds1287_set_base_clock(unsigned int clock);
25extern int ds1287_clockevent_init(int irq);
26
27#endif
diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h
new file mode 100644
index 000000000000..d74a8a4ca861
--- /dev/null
+++ b/include/asm-mips/gcmpregs.h
@@ -0,0 +1,117 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * Multiprocessor Subsystem Register Definitions
9 *
10 */
11#ifndef _ASM_GCMPREGS_H
12#define _ASM_GCMPREGS_H
13
14
15/* Offsets to major blocks within GCMP from GCMP base */
16#define GCMP_GCB_OFS 0x0000 /* Global Control Block */
17#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */
18#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */
19#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
20
21/* Offsets to individual GCMP registers from GCMP base */
22#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
23
24#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
25#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
26#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
27#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
28
29/* GCMP register access */
30#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
31#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
32#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
33#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
34
35/* Mask generation */
36#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF)
37#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits)
38#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits)
39#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits)
40
41/* GCB registers */
42#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */
43#define GCMP_GCB_GC_NUMIOCU_SHF 8
44#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4)
45#define GCMP_GCB_GC_NUMCORES_SHF 0
46#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8)
47#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */
48#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15
49#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
50#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
51#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
52#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0
53#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1
54#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
55#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
56#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
57#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
58#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
59#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8)
60#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */
61#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */
62#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */
63#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27
64#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
65#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0
66#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27)
67#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */
68#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */
69#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0
70#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5)
71#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */
72#define GCMP_GCB_GICBA_BASE_SHF 17
73#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15)
74#define GCMP_GCB_GICBA_EN_SHF 0
75#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1)
76
77/* GCB Regions */
78#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */
79#define GCMP_GCB_CMxBASE_BASE_SHF 16
80#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16)
81#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */
82#define GCMP_GCB_CMxMASK_MASK_SHF 16
83#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16)
84#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0
85#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
86#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0
87#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1
88#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
89#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
90
91
92/* Core local/Core other control block registers */
93#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */
94#define GCMP_CCB_RESETR_INRESET_SHF 0
95#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16)
96#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */
97#define GCMP_CCB_COHCTL_DOMAIN_SHF 0
98#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8)
99#define GCMP_CCB_CFG_OFS 0x0010 /* Config */
100#define GCMP_CCB_CFG_IOCUTYPE_SHF 10
101#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2)
102#define GCMP_CCB_CFG_IOCUTYPE_CPU 0
103#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1
104#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2
105#define GCMP_CCB_CFG_NUMVPE_SHF 0
106#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10)
107#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */
108#define GCMP_CCB_OTHER_CORENUM_SHF 16
109#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16)
110#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */
111#define GCMP_CCB_RESETBASE_BEV_SHF 12
112#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20)
113#define GCMP_CCB_ID_OFS 0x0028 /* Identification */
114#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */
115#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
116
117#endif /* _ASM_GCMPREGS_H */
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
new file mode 100644
index 000000000000..01b2f92dc33d
--- /dev/null
+++ b/include/asm-mips/gic.h
@@ -0,0 +1,487 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * GIC Register Definitions
9 *
10 */
11#ifndef _ASM_GICREGS_H
12#define _ASM_GICREGS_H
13
14#undef GICISBYTELITTLEENDIAN
15#define GICISWORDLITTLEENDIAN
16
17/* Constants */
18#define GIC_POL_POS 1
19#define GIC_POL_NEG 0
20#define GIC_TRIG_EDGE 1
21#define GIC_TRIG_LEVEL 0
22
23#define GIC_NUM_INTRS 32
24
25#define MSK(n) ((1 << (n)) - 1)
26#define REG32(addr) (*(volatile unsigned int *) (addr))
27#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS)
28#define REGP(base, phys) REG32((unsigned int)(base) + (phys))
29
30/* Accessors */
31#define GIC_REG(segment, offset) \
32 REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
33#define GIC_REG_ADDR(segment, offset) \
34 REG32(_gic_base + segment##_##SECTION_OFS + offset)
35
36#define GIC_ABS_REG(segment, offset) \
37 (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
38#define GIC_REG_ABS_ADDR(segment, offset) \
39 (_gic_base + segment##_##SECTION_OFS + offset)
40
41#ifdef GICISBYTELITTLEENDIAN
42#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
43#define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
44#define GICBIS(reg, bits) \
45 ({unsigned int data; \
46 GICREAD(reg, data); \
47 data |= bits; \
48 GICWRITE(reg, data); \
49 })
50
51#else
52#define GICREAD(reg, data) (data) = (reg)
53#define GICWRITE(reg, data) (reg) = (data)
54#define GICBIS(reg, bits) (reg) |= (bits)
55#endif
56
57
58/* GIC Address Space */
59#define SHARED_SECTION_OFS 0x0000
60#define SHARED_SECTION_SIZE 0x8000
61#define VPE_LOCAL_SECTION_OFS 0x8000
62#define VPE_LOCAL_SECTION_SIZE 0x4000
63#define VPE_OTHER_SECTION_OFS 0xc000
64#define VPE_OTHER_SECTION_SIZE 0x4000
65#define USM_VISIBLE_SECTION_OFS 0x10000
66#define USM_VISIBLE_SECTION_SIZE 0x10000
67
68/* Register Map for Shared Section */
69#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
70
71#define GIC_SH_CONFIG_OFS 0x0000
72
73/* Shared Global Counter */
74#define GIC_SH_COUNTER_31_00_OFS 0x0010
75#define GIC_SH_COUNTER_63_32_OFS 0x0014
76
77/* Interrupt Polarity */
78#define GIC_SH_POL_31_0_OFS 0x0100
79#define GIC_SH_POL_63_32_OFS 0x0104
80#define GIC_SH_POL_95_64_OFS 0x0108
81#define GIC_SH_POL_127_96_OFS 0x010c
82#define GIC_SH_POL_159_128_OFS 0x0110
83#define GIC_SH_POL_191_160_OFS 0x0114
84#define GIC_SH_POL_223_192_OFS 0x0118
85#define GIC_SH_POL_255_224_OFS 0x011c
86
87/* Edge/Level Triggering */
88#define GIC_SH_TRIG_31_0_OFS 0x0180
89#define GIC_SH_TRIG_63_32_OFS 0x0184
90#define GIC_SH_TRIG_95_64_OFS 0x0188
91#define GIC_SH_TRIG_127_96_OFS 0x018c
92#define GIC_SH_TRIG_159_128_OFS 0x0190
93#define GIC_SH_TRIG_191_160_OFS 0x0194
94#define GIC_SH_TRIG_223_192_OFS 0x0198
95#define GIC_SH_TRIG_255_224_OFS 0x019c
96
97/* Dual Edge Triggering */
98#define GIC_SH_DUAL_31_0_OFS 0x0200
99#define GIC_SH_DUAL_63_32_OFS 0x0204
100#define GIC_SH_DUAL_95_64_OFS 0x0208
101#define GIC_SH_DUAL_127_96_OFS 0x020c
102#define GIC_SH_DUAL_159_128_OFS 0x0210
103#define GIC_SH_DUAL_191_160_OFS 0x0214
104#define GIC_SH_DUAL_223_192_OFS 0x0218
105#define GIC_SH_DUAL_255_224_OFS 0x021c
106
107/* Set/Clear corresponding bit in Edge Detect Register */
108#define GIC_SH_WEDGE_OFS 0x0280
109
110/* Reset Mask - Disables Interrupt */
111#define GIC_SH_RMASK_31_0_OFS 0x0300
112#define GIC_SH_RMASK_63_32_OFS 0x0304
113#define GIC_SH_RMASK_95_64_OFS 0x0308
114#define GIC_SH_RMASK_127_96_OFS 0x030c
115#define GIC_SH_RMASK_159_128_OFS 0x0310
116#define GIC_SH_RMASK_191_160_OFS 0x0314
117#define GIC_SH_RMASK_223_192_OFS 0x0318
118#define GIC_SH_RMASK_255_224_OFS 0x031c
119
120/* Set Mask (WO) - Enables Interrupt */
121#define GIC_SH_SMASK_31_0_OFS 0x0380
122#define GIC_SH_SMASK_63_32_OFS 0x0384
123#define GIC_SH_SMASK_95_64_OFS 0x0388
124#define GIC_SH_SMASK_127_96_OFS 0x038c
125#define GIC_SH_SMASK_159_128_OFS 0x0390
126#define GIC_SH_SMASK_191_160_OFS 0x0394
127#define GIC_SH_SMASK_223_192_OFS 0x0398
128#define GIC_SH_SMASK_255_224_OFS 0x039c
129
130/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
131#define GIC_SH_MASK_31_0_OFS 0x0400
132#define GIC_SH_MASK_63_32_OFS 0x0404
133#define GIC_SH_MASK_95_64_OFS 0x0408
134#define GIC_SH_MASK_127_96_OFS 0x040c
135#define GIC_SH_MASK_159_128_OFS 0x0410
136#define GIC_SH_MASK_191_160_OFS 0x0414
137#define GIC_SH_MASK_223_192_OFS 0x0418
138#define GIC_SH_MASK_255_224_OFS 0x041c
139
140/* Pending Global Interrupts (RO) */
141#define GIC_SH_PEND_31_0_OFS 0x0480
142#define GIC_SH_PEND_63_32_OFS 0x0484
143#define GIC_SH_PEND_95_64_OFS 0x0488
144#define GIC_SH_PEND_127_96_OFS 0x048c
145#define GIC_SH_PEND_159_128_OFS 0x0490
146#define GIC_SH_PEND_191_160_OFS 0x0494
147#define GIC_SH_PEND_223_192_OFS 0x0498
148#define GIC_SH_PEND_255_224_OFS 0x049c
149
150#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
151
152/* Maps Interrupt X to a Pin */
153#define GIC_SH_MAP_TO_PIN(intr) \
154 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
155
156#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
157
158/* Maps Interrupt X to a VPE */
159#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
160 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
161#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
162
163/* Polarity : Reset Value is always 0 */
164#define GIC_SH_SET_POLARITY_OFS 0x0100
165#define GIC_SET_POLARITY(intr, pol) \
166 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
167
168/* Triggering : Reset Value is always 0 */
169#define GIC_SH_SET_TRIGGER_OFS 0x0180
170#define GIC_SET_TRIGGER(intr, trig) \
171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
172
173/* Mask manipulation */
174#define GIC_SH_SMASK_OFS 0x0380
175#define GIC_SET_INTR_MASK(intr, val) \
176 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
177
178#define GIC_SH_RMASK_OFS 0x0300
179#define GIC_CLR_INTR_MASK(intr, val) \
180 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
181
182/* Register Map for Local Section */
183#define GIC_VPE_CTL_OFS 0x0000
184#define GIC_VPE_PEND_OFS 0x0004
185#define GIC_VPE_MASK_OFS 0x0008
186#define GIC_VPE_RMASK_OFS 0x000c
187#define GIC_VPE_SMASK_OFS 0x0010
188#define GIC_VPE_WD_MAP_OFS 0x0040
189#define GIC_VPE_COMPARE_MAP_OFS 0x0044
190#define GIC_VPE_TIMER_MAP_OFS 0x0048
191#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
192#define GIC_VPE_SWINT0_MAP_OFS 0x0054
193#define GIC_VPE_SWINT1_MAP_OFS 0x0058
194#define GIC_VPE_OTHER_ADDR_OFS 0x0080
195#define GIC_VPE_WD_CONFIG0_OFS 0x0090
196#define GIC_VPE_WD_COUNT0_OFS 0x0094
197#define GIC_VPE_WD_INITIAL0_OFS 0x0098
198#define GIC_VPE_COMPARE_LO_OFS 0x00a0
199#define GIC_VPE_COMPARE_HI 0x00a4
200
201#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
202#define GIC_VPE_EIC_SS(intr) \
203 (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
204
205#define GIC_VPE_EIC_VEC_BASE 0x0800
206#define GIC_VPE_EIC_VEC(intr) \
207 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
208
209#define GIC_VPE_TENABLE_NMI_OFS 0x1000
210#define GIC_VPE_TENABLE_YQ_OFS 0x1004
211#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
212#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
213
214/* User Mode Visible Section Register Map */
215#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
216#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
217
218#else /* CONFIG_CPU_BIG_ENDIAN */
219
220#define GIC_SH_CONFIG_OFS 0x0000
221
222/* Shared Global Counter */
223#define GIC_SH_COUNTER_31_00_OFS 0x0014
224#define GIC_SH_COUNTER_63_32_OFS 0x0010
225
226/* Interrupt Polarity */
227#define GIC_SH_POL_31_0_OFS 0x0104
228#define GIC_SH_POL_63_32_OFS 0x0100
229#define GIC_SH_POL_95_64_OFS 0x010c
230#define GIC_SH_POL_127_96_OFS 0x0108
231#define GIC_SH_POL_159_128_OFS 0x0114
232#define GIC_SH_POL_191_160_OFS 0x0110
233#define GIC_SH_POL_223_192_OFS 0x011c
234#define GIC_SH_POL_255_224_OFS 0x0118
235
236/* Edge/Level Triggering */
237#define GIC_SH_TRIG_31_0_OFS 0x0184
238#define GIC_SH_TRIG_63_32_OFS 0x0180
239#define GIC_SH_TRIG_95_64_OFS 0x018c
240#define GIC_SH_TRIG_127_96_OFS 0x0188
241#define GIC_SH_TRIG_159_128_OFS 0x0194
242#define GIC_SH_TRIG_191_160_OFS 0x0190
243#define GIC_SH_TRIG_223_192_OFS 0x019c
244#define GIC_SH_TRIG_255_224_OFS 0x0198
245
246/* Dual Edge Triggering */
247#define GIC_SH_DUAL_31_0_OFS 0x0204
248#define GIC_SH_DUAL_63_32_OFS 0x0200
249#define GIC_SH_DUAL_95_64_OFS 0x020c
250#define GIC_SH_DUAL_127_96_OFS 0x0208
251#define GIC_SH_DUAL_159_128_OFS 0x0214
252#define GIC_SH_DUAL_191_160_OFS 0x0210
253#define GIC_SH_DUAL_223_192_OFS 0x021c
254#define GIC_SH_DUAL_255_224_OFS 0x0218
255
256/* Set/Clear corresponding bit in Edge Detect Register */
257#define GIC_SH_WEDGE_OFS 0x0280
258
259/* Reset Mask - Disables Interrupt */
260#define GIC_SH_RMASK_31_0_OFS 0x0304
261#define GIC_SH_RMASK_63_32_OFS 0x0300
262#define GIC_SH_RMASK_95_64_OFS 0x030c
263#define GIC_SH_RMASK_127_96_OFS 0x0308
264#define GIC_SH_RMASK_159_128_OFS 0x0314
265#define GIC_SH_RMASK_191_160_OFS 0x0310
266#define GIC_SH_RMASK_223_192_OFS 0x031c
267#define GIC_SH_RMASK_255_224_OFS 0x0318
268
269/* Set Mask (WO) - Enables Interrupt */
270#define GIC_SH_SMASK_31_0_OFS 0x0384
271#define GIC_SH_SMASK_63_32_OFS 0x0380
272#define GIC_SH_SMASK_95_64_OFS 0x038c
273#define GIC_SH_SMASK_127_96_OFS 0x0388
274#define GIC_SH_SMASK_159_128_OFS 0x0394
275#define GIC_SH_SMASK_191_160_OFS 0x0390
276#define GIC_SH_SMASK_223_192_OFS 0x039c
277#define GIC_SH_SMASK_255_224_OFS 0x0398
278
279/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
280#define GIC_SH_MASK_31_0_OFS 0x0404
281#define GIC_SH_MASK_63_32_OFS 0x0400
282#define GIC_SH_MASK_95_64_OFS 0x040c
283#define GIC_SH_MASK_127_96_OFS 0x0408
284#define GIC_SH_MASK_159_128_OFS 0x0414
285#define GIC_SH_MASK_191_160_OFS 0x0410
286#define GIC_SH_MASK_223_192_OFS 0x041c
287#define GIC_SH_MASK_255_224_OFS 0x0418
288
289/* Pending Global Interrupts (RO) */
290#define GIC_SH_PEND_31_0_OFS 0x0484
291#define GIC_SH_PEND_63_32_OFS 0x0480
292#define GIC_SH_PEND_95_64_OFS 0x048c
293#define GIC_SH_PEND_127_96_OFS 0x0488
294#define GIC_SH_PEND_159_128_OFS 0x0494
295#define GIC_SH_PEND_191_160_OFS 0x0490
296#define GIC_SH_PEND_223_192_OFS 0x049c
297#define GIC_SH_PEND_255_224_OFS 0x0498
298
299#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
300
301/* Maps Interrupt X to a Pin */
302#define GIC_SH_MAP_TO_PIN(intr) \
303 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
304
305#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
306
307/*
308 * Maps Interrupt X to a VPE. This is more complex than the LE case, as
309 * odd and even registers need to be transposed. It does work - trust me!
310 */
311#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
312 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
313 (((((vpe) / 32) ^ 1) - 1) * 4))
314#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
315
316/* Polarity */
317#define GIC_SH_SET_POLARITY_OFS 0x0100
318#define GIC_SET_POLARITY(intr, pol) \
319 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
320
321/* Triggering */
322#define GIC_SH_SET_TRIGGER_OFS 0x0180
323#define GIC_SET_TRIGGER(intr, trig) \
324 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
325
326/* Mask manipulation */
327#define GIC_SH_SMASK_OFS 0x0380
328#define GIC_SET_INTR_MASK(intr, val) \
329 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
330
331#define GIC_SH_RMASK_OFS 0x0300
332#define GIC_CLR_INTR_MASK(intr, val) \
333 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))
334
335/* Register Map for Local Section */
336#define GIC_VPE_CTL_OFS 0x0000
337#define GIC_VPE_PEND_OFS 0x0004
338#define GIC_VPE_MASK_OFS 0x0008
339#define GIC_VPE_RMASK_OFS 0x000c
340#define GIC_VPE_SMASK_OFS 0x0010
341#define GIC_VPE_WD_MAP_OFS 0x0040
342#define GIC_VPE_COMPARE_MAP_OFS 0x0044
343#define GIC_VPE_TIMER_MAP_OFS 0x0048
344#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
345#define GIC_VPE_SWINT0_MAP_OFS 0x0054
346#define GIC_VPE_SWINT1_MAP_OFS 0x0058
347#define GIC_VPE_OTHER_ADDR_OFS 0x0080
348#define GIC_VPE_WD_CONFIG0_OFS 0x0090
349#define GIC_VPE_WD_COUNT0_OFS 0x0094
350#define GIC_VPE_WD_INITIAL0_OFS 0x0098
351#define GIC_VPE_COMPARE_LO_OFS 0x00a4
352#define GIC_VPE_COMPARE_HI_OFS 0x00a0
353
354#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
355#define GIC_VPE_EIC_SS(intr) \
356 (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
357
358#define GIC_VPE_EIC_VEC_BASE 0x0800
359#define GIC_VPE_EIC_VEC(intr) \
360 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
361
362#define GIC_VPE_TENABLE_NMI_OFS 0x1000
363#define GIC_VPE_TENABLE_YQ_OFS 0x1004
364#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
365#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
366
367/* User Mode Visible Section Register Map */
368#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
369#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
370
371#endif /* !LE */
372
373/* Masks */
374#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
375#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
376
377#define GIC_SH_CONFIG_COUNTBITS_SHF 24
378#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
379
380#define GIC_SH_CONFIG_NUMINTRS_SHF 16
381#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
382
383#define GIC_SH_CONFIG_NUMVPES_SHF 0
384#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
385
386#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
387#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
388
389#define GIC_MAP_TO_PIN_SHF 31
390#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
391#define GIC_MAP_TO_NMI_SHF 30
392#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
393#define GIC_MAP_TO_YQ_SHF 29
394#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
395#define GIC_MAP_SHF 0
396#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
397
398/* GIC_VPE_CTL Masks */
399#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
400#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
401#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
402#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
403#define GIC_VPE_CTL_EIC_MODE_SHF 0
404#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
405
406/* GIC_VPE_PEND Masks */
407#define GIC_VPE_PEND_WD_SHF 0
408#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
409#define GIC_VPE_PEND_CMP_SHF 1
410#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
411#define GIC_VPE_PEND_TIMER_SHF 2
412#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
413#define GIC_VPE_PEND_PERFCOUNT_SHF 3
414#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
415#define GIC_VPE_PEND_SWINT0_SHF 4
416#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
417#define GIC_VPE_PEND_SWINT1_SHF 5
418#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
419
420/* GIC_VPE_RMASK Masks */
421#define GIC_VPE_RMASK_WD_SHF 0
422#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
423#define GIC_VPE_RMASK_CMP_SHF 1
424#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
425#define GIC_VPE_RMASK_TIMER_SHF 2
426#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
427#define GIC_VPE_RMASK_PERFCNT_SHF 3
428#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
429#define GIC_VPE_RMASK_SWINT0_SHF 4
430#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
431#define GIC_VPE_RMASK_SWINT1_SHF 5
432#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
433
434/* GIC_VPE_SMASK Masks */
435#define GIC_VPE_SMASK_WD_SHF 0
436#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
437#define GIC_VPE_SMASK_CMP_SHF 1
438#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
439#define GIC_VPE_SMASK_TIMER_SHF 2
440#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
441#define GIC_VPE_SMASK_PERFCNT_SHF 3
442#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
443#define GIC_VPE_SMASK_SWINT0_SHF 4
444#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
445#define GIC_VPE_SMASK_SWINT1_SHF 5
446#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
447
448/*
449 * Set the Mapping of Interrupt X to a VPE.
450 */
451#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
452 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
453 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
454
455struct gic_pcpu_mask {
456 DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
457};
458
459struct gic_pending_regs {
460 DECLARE_BITMAP(pending, GIC_NUM_INTRS);
461};
462
463struct gic_intrmask_regs {
464 DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
465};
466
467/*
468 * Interrupt Meta-data specification. The ipiflag helps
469 * in building ipi_map.
470 */
471struct gic_intr_map {
472 unsigned int intrnum; /* Ext Intr Num */
473 unsigned int cpunum; /* Directed to this CPU */
474 unsigned int pin; /* Directed to this Pin */
475 unsigned int polarity; /* Polarity : +/- */
476 unsigned int trigtype; /* Trigger : Edge/Levl */
477 unsigned int ipiflag; /* Is used for IPI ? */
478};
479
480extern void gic_init(unsigned long gic_base_addr,
481 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
482 unsigned int intrmap_size, unsigned int irqbase);
483
484extern unsigned int gic_get_int(void);
485extern void gic_send_ipi(unsigned int intr);
486
487#endif /* _ASM_GICREGS_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index e62058b0d28c..f18d2816cbec 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -273,7 +273,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
273 * memory-like regions on I/O busses. 273 * memory-like regions on I/O busses.
274 */ 274 */
275#define ioremap_cachable(offset, size) \ 275#define ioremap_cachable(offset, size) \
276 __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) 276 __ioremap_mode((offset), (size), _page_cachable_default)
277 277
278/* 278/*
279 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 279 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 81602c8047eb..a162268f17df 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -99,8 +99,8 @@
99#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) 99#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
100 100
101/* DIPSW4 macro */ 101/* DIPSW4 macro */
102#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0) 102#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
103#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) 103#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
104#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) 104#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
105#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) 105#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
106 106
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 338f99882a39..fb580333c102 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -314,6 +314,6 @@ struct tx3927_ccfg_reg {
314#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 314#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
315#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) 315#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
317#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) 317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
318 318
319#endif /* __ASM_TX3927_H */ 319#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 0474fe8dac3f..25dcf2feb095 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -22,18 +22,6 @@ struct txx927_sio_reg {
22 volatile unsigned long rfifo; 22 volatile unsigned long rfifo;
23}; 23};
24 24
25struct txx927_pio_reg {
26 volatile unsigned long dout;
27 volatile unsigned long din;
28 volatile unsigned long dir;
29 volatile unsigned long od;
30 volatile unsigned long flag[2];
31 volatile unsigned long pol;
32 volatile unsigned long intc;
33 volatile unsigned long maskcpu;
34 volatile unsigned long maskext;
35};
36
37/* 25/*
38 * SIO 26 * SIO
39 */ 27 */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 5bb57bf2b9d7..a05555165d05 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -3,9 +3,8 @@
3 * BRIEF MODULE DESCRIPTION 3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU. 4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 * 5 *
6 * Copyright 2000,2001 MontaVista Software Inc. 6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * ppopov@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
117 116
118#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 117#endif /* !defined (_LANGUAGE_ASSEMBLY) */
119 118
120#ifdef CONFIG_PM
121/* no CP0 timer irq */
122#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
123#else
124#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
125#endif
126
127/* 119/*
128 * SDRAM Register Offsets 120 * SDRAM Register Offsets
129 */ 121 */
@@ -1693,20 +1685,6 @@ enum soc_au1200_ints {
1693#define IOMEM_RESOURCE_START 0x10000000 1685#define IOMEM_RESOURCE_START 0x10000000
1694#define IOMEM_RESOURCE_END 0xffffffff 1686#define IOMEM_RESOURCE_END 0xffffffff
1695 1687
1696 /*
1697 * Borrowed from the PPC arch:
1698 * The following macro is used to lookup irqs in a standard table
1699 * format for those PPC systems that do not already have PCI
1700 * interrupts properly routed.
1701 */
1702 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1703#define PCI_IRQ_TABLE_LOOKUP \
1704 ({ long _ctl_ = -1; \
1705 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1706 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1707 _ctl_; })
1708
1709
1710#else /* Au1000 and Au1100 and Au1200 */ 1688#else /* Au1000 and Au1100 and Au1200 */
1711 1689
1712/* don't allow any legacy ports probing */ 1690/* don't allow any legacy ports probing */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index d2e28e64932e..eedd048a7261 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -169,15 +169,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
169#define BCSR_INT_SD0INSERT 0x1000 169#define BCSR_INT_SD0INSERT 0x1000
170#define BCSR_INT_SD0EJECT 0x2000 170#define BCSR_INT_SD0EJECT 0x2000
171 171
172#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) 172#define SMC91C111_PHYS_ADDR 0x19000300
173#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT 173#define SMC91C111_INT DB1200_ETH_INT
174 174
175#define AU1XXX_ATA_PHYS_ADDR (0x18800000) 175#define IDE_PHYS_ADDR 0x18800000
176#define AU1XXX_ATA_REG_OFFSET (5) 176#define IDE_REG_SHIFT 5
177#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET) 177#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
178#define AU1XXX_ATA_INT DB1200_IDE_INT 178#define IDE_INT DB1200_IDE_INT
179#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; 179#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
180#define AU1XXX_ATA_RQSIZE 128 180#define IDE_RQSIZE 128
181 181
182#define NAND_PHYS_ADDR 0x20000000 182#define NAND_PHYS_ADDR 0x20000000
183 183
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
index 6eaf5efedf3a..e6b376bd9d06 100644
--- a/include/asm-mips/mach-generic/gpio.h
+++ b/include/asm-mips/mach-generic/gpio.h
@@ -1,12 +1,18 @@
1#ifndef __ASM_MACH_GENERIC_GPIO_H 1#ifndef __ASM_MACH_GENERIC_GPIO_H
2#define __ASM_MACH_GENERIC_GPIO_H 2#define __ASM_MACH_GENERIC_GPIO_H
3 3
4#ifdef CONFIG_HAVE_GPIO_LIB
5#define gpio_get_value __gpio_get_value
6#define gpio_set_value __gpio_set_value
7#define gpio_cansleep __gpio_cansleep
8#else
4int gpio_request(unsigned gpio, const char *label); 9int gpio_request(unsigned gpio, const char *label);
5void gpio_free(unsigned gpio); 10void gpio_free(unsigned gpio);
6int gpio_direction_input(unsigned gpio); 11int gpio_direction_input(unsigned gpio);
7int gpio_direction_output(unsigned gpio, int value); 12int gpio_direction_output(unsigned gpio, int value);
8int gpio_get_value(unsigned gpio); 13int gpio_get_value(unsigned gpio);
9void gpio_set_value(unsigned gpio, int value); 14void gpio_set_value(unsigned gpio, int value);
15#endif
10int gpio_to_irq(unsigned gpio); 16int gpio_to_irq(unsigned gpio);
11int irq_to_gpio(unsigned irq); 17int irq_to_gpio(unsigned irq);
12 18
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index 372291f53fb9..7785bec732f2 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -54,4 +54,6 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
54 .nr_balance_failed = 0, \ 54 .nr_balance_failed = 0, \
55} 55}
56 56
57#include <asm-generic/topology.h>
58
57#endif /* _ASM_MACH_TOPOLOGY_H */ 59#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index edaa489b58f1..e2c6bcac3b42 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -182,15 +182,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
182#define SET_VCC_VPP(VCC, VPP, SLOT)\ 182#define SET_VCC_VPP(VCC, VPP, SLOT)\
183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
184 184
185#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300) 185#define SMC91C111_PHYS_ADDR 0x0D000300
186#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT 186#define SMC91C111_INT PB1200_ETH_INT
187 187
188#define AU1XXX_ATA_PHYS_ADDR (0x0C800000) 188#define IDE_PHYS_ADDR 0x0C800000
189#define AU1XXX_ATA_REG_OFFSET (5) 189#define IDE_REG_SHIFT 5
190#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET) 190#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
191#define AU1XXX_ATA_INT PB1200_IDE_INT 191#define IDE_INT PB1200_IDE_INT
192#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; 192#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
193#define AU1XXX_ATA_RQSIZE 128 193#define IDE_RQSIZE 128
194 194
195#define NAND_PHYS_ADDR 0x1C000000 195#define NAND_PHYS_ADDR 0x1C000000
196 196
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 1c39d339521e..33407bee4e73 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -68,6 +68,7 @@
68#define MIPS_REVISION_CORID_CORE_FPGA3 9 68#define MIPS_REVISION_CORID_CORE_FPGA3 9
69#define MIPS_REVISION_CORID_CORE_24K 10 69#define MIPS_REVISION_CORID_CORE_24K 10
70#define MIPS_REVISION_CORID_CORE_FPGA4 11 70#define MIPS_REVISION_CORID_CORE_FPGA4 11
71#define MIPS_REVISION_CORID_CORE_FPGA5 12
71 72
72/**** Artificial corid defines ****/ 73/**** Artificial corid defines ****/
73/* 74/*
diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h
new file mode 100644
index 000000000000..d8ae7f95a522
--- /dev/null
+++ b/include/asm-mips/mips-boards/launch.h
@@ -0,0 +1,35 @@
1/*
2 *
3 */
4
5#ifndef _ASSEMBLER_
6
7struct cpulaunch {
8 unsigned long pc;
9 unsigned long gp;
10 unsigned long sp;
11 unsigned long a0;
12 unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */
13 unsigned long flags;
14};
15
16#else
17
18#define LOG2CPULAUNCH 5
19#define LAUNCH_PC 0
20#define LAUNCH_GP 4
21#define LAUNCH_SP 8
22#define LAUNCH_A0 12
23#define LAUNCH_FLAGS 28
24
25#endif
26
27#define LAUNCH_FREADY 1
28#define LAUNCH_FGO 2
29#define LAUNCH_FGONE 4
30
31#define CPULAUNCH 0x00000f00
32#define NCPULAUNCH 8
33
34/* Polling period in count cycles for secondary CPU's */
35#define LAUNCHPERIOD 10000
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index 93bf4e51b8a4..c1891578fa65 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -52,6 +52,29 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
52} 52}
53 53
54/* 54/*
55 * GCMP Specific definitions
56 */
57#define GCMP_BASE_ADDR 0x1fbf8000
58#define GCMP_ADDRSPACE_SZ (256 * 1024)
59
60/*
61 * GIC Specific definitions
62 */
63#define GIC_BASE_ADDR 0x1bdc0000
64#define GIC_ADDRSPACE_SZ (128 * 1024)
65
66/*
67 * MSC01 BIU Specific definitions
68 * FIXME : These should be elsewhere ?
69 */
70#define MSC01_BIU_REG_BASE 0x1bc80000
71#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
72#define MSC01_SC_CFG_OFS 0x0110
73#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
74#define MSC01_SC_CFG_GICPRES_SHF 2
75#define MSC01_SC_CFG_GICENA_SHF 3
76
77/*
55 * Malta RTC-device indirect register access. 78 * Malta RTC-device indirect register access.
56 */ 79 */
57#define MALTA_RTC_ADR_REG 0x70 80#define MALTA_RTC_ADR_REG 0x70
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 7461318f1cd1..cea872fc6f5c 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -39,7 +39,9 @@
39#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 39#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
40#define MIPSCPU_INT_MB1 3 40#define MIPSCPU_INT_MB1 3
41#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 41#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
42#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
42#define MIPSCPU_INT_MB2 4 43#define MIPSCPU_INT_MB2 4
44#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
43#define MIPSCPU_INT_MB3 5 45#define MIPSCPU_INT_MB3 5
44#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 46#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
45#define MIPSCPU_INT_MB4 6 47#define MIPSCPU_INT_MB4 6
@@ -76,6 +78,31 @@
76#define MSC01E_INT_PERFCTR 10 78#define MSC01E_INT_PERFCTR 10
77#define MSC01E_INT_CPUCTR 11 79#define MSC01E_INT_CPUCTR 11
78 80
81/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
82#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
83#define GIC_CPU_INT1 1 /* . */
84#define GIC_CPU_INT2 2 /* . */
85#define GIC_CPU_INT3 3 /* . */
86#define GIC_CPU_INT4 4 /* . */
87#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
88
89#define GIC_EXT_INTR(x) x
90
91/* Dummy data */
92#define X 0xdead
93
94/* External Interrupts used for IPI */
95#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
96#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
97#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
98#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
99#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
100#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
101#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
102#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
103
104#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
105
79#ifndef __ASSEMBLY__ 106#ifndef __ASSEMBLY__
80extern void maltaint_init(void); 107extern void maltaint_init(void);
81#endif 108#endif
diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h
new file mode 100644
index 000000000000..8d7e955d506e
--- /dev/null
+++ b/include/asm-mips/mips-boards/maltasmp.h
@@ -0,0 +1,36 @@
1/*
2 * There are several SMP models supported
3 * SMTC is mutually exclusive to other options (atm)
4 */
5#if defined(CONFIG_MIPS_MT_SMTC)
6#define malta_smtc 1
7#define malta_cmp 0
8#define malta_smvp 0
9#else
10#define malta_smtc 0
11#if defined(CONFIG_MIPS_CMP)
12extern int gcmp_present;
13#define malta_cmp gcmp_present
14#else
15#define malta_cmp 0
16#endif
17/* FIXME: should become COMFIG_MIPS_MT_SMVP */
18#if defined(CONFIG_MIPS_MT_SMP)
19#define malta_smvp 1
20#else
21#define malta_smvp 0
22#endif
23#endif
24
25#include <asm/mipsregs.h>
26#include <asm/mipsmtregs.h>
27
28/* malta_smtc */
29#include <asm/smtc.h>
30#include <asm/smtc_ipi.h>
31
32/* malta_cmp */
33#include <asm/cmp.h>
34
35/* malta_smvp */
36#include <asm/smvp.h>
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
index 5a2f8a3a6a1f..c9420aa97e32 100644
--- a/include/asm-mips/mipsmtregs.h
+++ b/include/asm-mips/mipsmtregs.h
@@ -197,8 +197,8 @@ static inline void __raw_evpe(void)
197 " .set pop \n"); 197 " .set pop \n");
198} 198}
199 199
200/* Enable multiMT if previous suggested it should be. 200/* Enable virtual processor execution if previous suggested it should be.
201 EMT_ENABLE to force */ 201 EVPE_ENABLE to force */
202 202
203#define EVPE_ENABLE MVPCONTROL_EVP 203#define EVPE_ENABLE MVPCONTROL_EVP
204 204
@@ -238,8 +238,8 @@ static inline void __raw_emt(void)
238 " .set reorder"); 238 " .set reorder");
239} 239}
240 240
241/* enable multiVPE if previous suggested it should be. 241/* enable multi-threaded execution if previous suggested it should be.
242 EVPE_ENABLE to force */ 242 EMT_ENABLE to force */
243 243
244#define EMT_ENABLE VPECONTROL_TE 244#define EMT_ENABLE VPECONTROL_TE
245 245
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index ceefe027c761..4396e9ffd418 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp)
107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
108} 108}
109 109
110#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 110#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
111#define pte_page(x) pfn_to_page(pte_pfn(x)) 111#define pte_page(x) pfn_to_page(pte_pfn(x))
112#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 112#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
113static inline pte_t 113static inline pte_t
@@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
132#endif 132#endif
133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ 133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
134 134
135#define __pgd_offset(address) pgd_index(address) 135#define __pgd_offset(address) pgd_index(address)
136#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 136#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 7494ba91112a..60e2f9338fcd 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -32,14 +32,14 @@
32 * unpredictable things. The code (when it is written) to deal with 32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k. 33 * this problem will be in the update_mmu_cache() code for the r4k.
34 */ 34 */
35#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
36 36
37#define _PAGE_PRESENT (1<<6) /* implemented in software */ 37#define _PAGE_PRESENT (1<<6) /* implemented in software */
38#define _PAGE_READ (1<<7) /* implemented in software */ 38#define _PAGE_READ (1<<7) /* implemented in software */
39#define _PAGE_WRITE (1<<8) /* implemented in software */ 39#define _PAGE_WRITE (1<<8) /* implemented in software */
40#define _PAGE_ACCESSED (1<<9) /* implemented in software */ 40#define _PAGE_ACCESSED (1<<9) /* implemented in software */
41#define _PAGE_MODIFIED (1<<10) /* implemented in software */ 41#define _PAGE_MODIFIED (1<<10) /* implemented in software */
42#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ 42#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
43 43
44#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ 44#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
45#define _PAGE_GLOBAL (1<<0) 45#define _PAGE_GLOBAL (1<<0)
@@ -47,15 +47,9 @@
47#define _PAGE_SILENT_READ (1<<1) /* synonym */ 47#define _PAGE_SILENT_READ (1<<1) /* synonym */
48#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ 48#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
49#define _PAGE_SILENT_WRITE (1<<2) 49#define _PAGE_SILENT_WRITE (1<<2)
50#define _CACHE_SHIFT 3
50#define _CACHE_MASK (7<<3) 51#define _CACHE_MASK (7<<3)
51 52
52/* MIPS32 defines only values 2 and 3. The rest are implementation
53 * dependent.
54 */
55#define _CACHE_UNCACHED (2<<3)
56#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
57#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
58
59#else 53#else
60 54
61#define _PAGE_PRESENT (1<<0) /* implemented in software */ 55#define _PAGE_PRESENT (1<<0) /* implemented in software */
@@ -74,75 +68,72 @@
74#define _PAGE_SILENT_WRITE (1<<10) 68#define _PAGE_SILENT_WRITE (1<<10)
75#define _CACHE_UNCACHED (1<<11) 69#define _CACHE_UNCACHED (1<<11)
76#define _CACHE_MASK (1<<11) 70#define _CACHE_MASK (1<<11)
77#define _CACHE_CACHABLE_NONCOHERENT 0
78 71
79#else 72#else
73
80#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
81#define _PAGE_GLOBAL (1<<6) 75#define _PAGE_GLOBAL (1<<6)
82#define _PAGE_VALID (1<<7) 76#define _PAGE_VALID (1<<7)
83#define _PAGE_SILENT_READ (1<<7) /* synonym */ 77#define _PAGE_SILENT_READ (1<<7) /* synonym */
84#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 78#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
85#define _PAGE_SILENT_WRITE (1<<8) 79#define _PAGE_SILENT_WRITE (1<<8)
80#define _CACHE_SHIFT 9
86#define _CACHE_MASK (7<<9) 81#define _CACHE_MASK (7<<9)
87 82
88#ifdef CONFIG_CPU_SB1 83#endif
84#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
85
86
87/*
88 * Cache attributes
89 */
90#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
91
92#define _CACHE_CACHABLE_NONCOHERENT 0
93
94#elif defined(CONFIG_CPU_SB1)
89 95
90/* No penalty for being coherent on the SB1, so just 96/* No penalty for being coherent on the SB1, so just
91 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 97 use it for "noncoherent" spaces, too. Shouldn't hurt. */
92 98
93#define _CACHE_UNCACHED (2<<9) 99#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
94#define _CACHE_CACHABLE_COW (5<<9) 100#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
95#define _CACHE_CACHABLE_NONCOHERENT (5<<9) 101#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
96#define _CACHE_UNCACHED_ACCELERATED (7<<9) 102#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
97 103
98#elif defined(CONFIG_CPU_RM9000) 104#elif defined(CONFIG_CPU_RM9000)
99 105
100#define _CACHE_WT (0 << 9) 106#define _CACHE_WT (0<<_CACHE_SHIFT)
101#define _CACHE_WTWA (1 << 9) 107#define _CACHE_WTWA (1<<_CACHE_SHIFT)
102#define _CACHE_UC_B (2 << 9) 108#define _CACHE_UC_B (2<<_CACHE_SHIFT)
103#define _CACHE_WB (3 << 9) 109#define _CACHE_WB (3<<_CACHE_SHIFT)
104#define _CACHE_CWBEA (4 << 9) 110#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
105#define _CACHE_CWB (5 << 9) 111#define _CACHE_CWB (5<<_CACHE_SHIFT)
106#define _CACHE_UCNB (6 << 9) 112#define _CACHE_UCNB (6<<_CACHE_SHIFT)
107#define _CACHE_FPC (7 << 9) 113#define _CACHE_FPC (7<<_CACHE_SHIFT)
108 114
109#define _CACHE_UNCACHED _CACHE_UC_B 115#define _CACHE_UNCACHED _CACHE_UC_B
110#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB 116#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
111 117
112#else 118#else
113 119
114#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ 120#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
115#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ 121#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
116#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ 122#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
117#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ 123#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
118#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ 124#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
119#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ 125#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
120#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ 126#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
121#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ 127#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
128#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
122 129
123#endif 130#endif
124#endif
125#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
126 131
127#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 132#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
128#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 133#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
129 134
130#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 135#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
131 136
132#ifdef CONFIG_MIPS_UNCACHED 137#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
133#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
134#elif defined(CONFIG_DMA_NONCOHERENT)
135#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
136#elif defined(CONFIG_CPU_RM9000)
137#define PAGE_CACHABLE_DEFAULT _CACHE_CWB
138#else
139#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
140#endif
141
142#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
143#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
144#else
145#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
146#endif
147 138
148#endif /* _ASM_PGTABLE_BITS_H */ 139#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 782221e57c0a..2f597eea4448 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -23,15 +23,15 @@ struct vm_area_struct;
23 23
24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
26 PAGE_CACHABLE_DEFAULT) 26 _page_cachable_default)
27#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 27#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
28 PAGE_CACHABLE_DEFAULT) 28 _page_cachable_default)
29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
30 PAGE_CACHABLE_DEFAULT) 30 _page_cachable_default)
31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
32 _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) 32 _PAGE_GLOBAL | _page_cachable_default)
33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
34 PAGE_CACHABLE_DEFAULT) 34 _page_cachable_default)
35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) 36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
37 37
@@ -40,23 +40,30 @@ struct vm_area_struct;
40 * read. Also, write permissions imply read permissions. This is the closest 40 * read. Also, write permissions imply read permissions. This is the closest
41 * we can get by reasonable means.. 41 * we can get by reasonable means..
42 */ 42 */
43#define __P000 PAGE_NONE 43
44#define __P001 PAGE_READONLY 44/*
45#define __P010 PAGE_COPY 45 * Dummy values to fill the table in mmap.c
46#define __P011 PAGE_COPY 46 * The real values will be generated at runtime
47#define __P100 PAGE_READONLY 47 */
48#define __P101 PAGE_READONLY 48#define __P000 __pgprot(0)
49#define __P110 PAGE_COPY 49#define __P001 __pgprot(0)
50#define __P111 PAGE_COPY 50#define __P010 __pgprot(0)
51 51#define __P011 __pgprot(0)
52#define __S000 PAGE_NONE 52#define __P100 __pgprot(0)
53#define __S001 PAGE_READONLY 53#define __P101 __pgprot(0)
54#define __S010 PAGE_SHARED 54#define __P110 __pgprot(0)
55#define __S011 PAGE_SHARED 55#define __P111 __pgprot(0)
56#define __S100 PAGE_READONLY 56
57#define __S101 PAGE_READONLY 57#define __S000 __pgprot(0)
58#define __S110 PAGE_SHARED 58#define __S001 __pgprot(0)
59#define __S111 PAGE_SHARED 59#define __S010 __pgprot(0)
60#define __S011 __pgprot(0)
61#define __S100 __pgprot(0)
62#define __S101 __pgprot(0)
63#define __S110 __pgprot(0)
64#define __S111 __pgprot(0)
65
66extern unsigned long _page_cachable_default;
60 67
61/* 68/*
62 * ZERO_PAGE is a global shared page that is always zero; used 69 * ZERO_PAGE is a global shared page that is always zero; used
@@ -79,7 +86,7 @@ extern void paging_init(void);
79#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 86#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
80#define pmd_page_vaddr(pmd) pmd_val(pmd) 87#define pmd_page_vaddr(pmd) pmd_val(pmd)
81 88
82#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 89#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
83 90
84#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 91#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
85#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 92#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
@@ -182,7 +189,7 @@ extern pgd_t swapper_pg_dir[];
182 * The following only work if pte_present() is true. 189 * The following only work if pte_present() is true.
183 * Undefined behaviour if not.. 190 * Undefined behaviour if not..
184 */ 191 */
185#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 192#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
186static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 193static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
187static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 194static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
188static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } 195static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
@@ -311,7 +318,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
311 */ 318 */
312#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 319#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
313 320
314#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 321#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
315static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 322static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
316{ 323{
317 pte.pte_low &= _PAGE_CHG_MASK; 324 pte.pte_low &= _PAGE_CHG_MASK;
diff --git a/include/asm-mips/r4k-timer.h b/include/asm-mips/r4k-timer.h
new file mode 100644
index 000000000000..a37d12b3b61c
--- /dev/null
+++ b/include/asm-mips/r4k-timer.h
@@ -0,0 +1,30 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_R4K_TYPES_H
9#define __ASM_R4K_TYPES_H
10
11#include <linux/compiler.h>
12
13#ifdef CONFIG_SYNC_R4K
14
15extern void synchronise_count_master(void);
16extern void synchronise_count_slave(void);
17
18#else
19
20static inline void synchronise_count_master(void)
21{
22}
23
24static inline void synchronise_count_slave(void)
25{
26}
27
28#endif
29
30#endif /* __ASM_R4K_TYPES_H */
diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h
index b17fdfb5d818..43c207e72a63 100644
--- a/include/asm-mips/smp-ops.h
+++ b/include/asm-mips/smp-ops.h
@@ -51,6 +51,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops)
51#endif /* !CONFIG_SMP */ 51#endif /* !CONFIG_SMP */
52 52
53extern struct plat_smp_ops up_smp_ops; 53extern struct plat_smp_ops up_smp_ops;
54extern struct plat_smp_ops cmp_smp_ops;
54extern struct plat_smp_ops vsmp_smp_ops; 55extern struct plat_smp_ops vsmp_smp_ops;
55 56
56#endif /* __ASM_SMP_OPS_H */ 57#endif /* __ASM_SMP_OPS_H */
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index ff3e8936b493..3639b28f80db 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -44,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot);
44extern void mipsmt_prepare_cpus(void); 44extern void mipsmt_prepare_cpus(void);
45extern void smtc_smp_finish(void); 45extern void smtc_smp_finish(void);
46extern void smtc_boot_secondary(int cpu, struct task_struct *t); 46extern void smtc_boot_secondary(int cpu, struct task_struct *t);
47extern void smtc_cpus_done(void);
47 48
48/* 49/*
49 * Sharing the TLB between multiple VPEs means that the 50 * Sharing the TLB between multiple VPEs means that the
diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h
new file mode 100644
index 000000000000..0d0e80a39e8a
--- /dev/null
+++ b/include/asm-mips/smvp.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_SMVP_H
2#define _ASM_SMVP_H
3
4/*
5 * Definitions for SMVP multitasking on MIPS MT cores
6 */
7struct task_struct;
8
9extern void smvp_smp_setup(void);
10extern void smvp_smp_finish(void);
11extern void smvp_boot_secondary(int cpu, struct task_struct *t);
12extern void smvp_init_secondary(void);
13extern void smvp_smp_finish(void);
14extern void smvp_cpus_done(void);
15extern void smvp_prepare_cpus(unsigned int max_cpus);
16
17/* This is platform specific */
18extern void smvp_send_ipi(int cpu, unsigned int action);
19#endif /* _ASM_SMVP_H */
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index d02e019b0127..e5dbde625ec2 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -23,5 +23,7 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
23 23
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_watchpoint_handler)(struct pt_regs *regs);
26 28
27#endif /* _ASM_TRAPS_H */ 29#endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index b180488dcdc4..dfed7beb533f 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -67,44 +67,26 @@
67#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) 67#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
68#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) 68#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
69 69
70#define rbtx4938_fpga_rev_ptr \ 70#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
71 ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR) 71#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
72#define rbtx4938_led_ptr \ 72#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
73 ((volatile unsigned char *)RBTX4938_LED_ADDR) 73#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
74#define rbtx4938_dipsw_ptr \ 74#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
75 ((volatile unsigned char *)RBTX4938_DIPSW_ADDR) 75#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
76#define rbtx4938_bdipsw_ptr \ 76#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
77 ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR) 77#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
78#define rbtx4938_imask_ptr \ 78#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
79 ((volatile unsigned char *)RBTX4938_IMASK_ADDR) 79#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
80#define rbtx4938_imask2_ptr \ 80#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
81 ((volatile unsigned char *)RBTX4938_IMASK2_ADDR) 81#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
82#define rbtx4938_intpol_ptr \ 82#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
83 ((volatile unsigned char *)RBTX4938_INTPOL_ADDR) 83#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
84#define rbtx4938_istat_ptr \ 84#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
85 ((volatile unsigned char *)RBTX4938_ISTAT_ADDR) 85#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
86#define rbtx4938_istat2_ptr \ 86#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
87 ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR) 87#define rbtx4938_softresetlock_addr \
88#define rbtx4938_imstat_ptr \ 88 ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
89 ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR) 89#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
90#define rbtx4938_imstat2_ptr \
91 ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
92#define rbtx4938_softint_ptr \
93 ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
94#define rbtx4938_piosel_ptr \
95 ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
96#define rbtx4938_spics_ptr \
97 ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
98#define rbtx4938_sfpwr_ptr \
99 ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
100#define rbtx4938_sfvol_ptr \
101 ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
102#define rbtx4938_softreset_ptr \
103 ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
104#define rbtx4938_softresetlock_ptr \
105 ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
106#define rbtx4938_pcireset_ptr \
107 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
108 90
109/* 91/*
110 * IRQ mappings 92 * IRQ mappings
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index f7c448b90578..e8807f5c61e9 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -13,8 +13,6 @@
13#ifndef __ASM_TX_BOARDS_TX4938_H 13#ifndef __ASM_TX_BOARDS_TX4938_H
14#define __ASM_TX_BOARDS_TX4938_H 14#define __ASM_TX_BOARDS_TX4938_H
15 15
16#include <asm/tx4938/tx4938_mips.h>
17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 16#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 17#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
20 18
@@ -54,28 +52,6 @@
54#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 52#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
55#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 53#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
56 54
57#ifndef _LANGUAGE_ASSEMBLY
58#include <asm/byteorder.h>
59
60#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
61
62#define TX4938_RD08( reg ) (*(vu08*)(reg))
63#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))
64
65#define TX4938_RD16( reg ) (*(vu16*)(reg))
66#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))
67
68#define TX4938_RD32( reg ) (*(vu32*)(reg))
69#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))
70
71#define TX4938_RD64( reg ) (*(vu64*)(reg))
72#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))
73
74#define TX4938_RD( reg ) TX4938_RD32( reg )
75#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
76
77#endif /* !__ASSEMBLY__ */
78
79#ifdef __ASSEMBLY__ 55#ifdef __ASSEMBLY__
80#define _CONST64(c) c 56#define _CONST64(c) c
81#else 57#else
@@ -261,18 +237,6 @@ struct tx4938_sio_reg {
261 volatile unsigned long rfifo; 237 volatile unsigned long rfifo;
262}; 238};
263 239
264struct tx4938_pio_reg {
265 volatile unsigned long dout;
266 volatile unsigned long din;
267 volatile unsigned long dir;
268 volatile unsigned long od;
269 volatile unsigned long flag[2];
270 volatile unsigned long pol;
271 volatile unsigned long intc;
272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext;
274};
275
276struct tx4938_ndfmc_reg { 240struct tx4938_ndfmc_reg {
277 endian_def_l2(unused0, dtr); 241 endian_def_l2(unused0, dtr);
278 endian_def_l2(unused1, mcr); 242 endian_def_l2(unused1, mcr);
@@ -642,7 +606,7 @@ struct tx4938_ccfg_reg {
642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 606#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 607#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
644#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 608#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
645#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) 609#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
646#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 610#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
647#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) 611#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
648#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) 612#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
deleted file mode 100644
index f346ff58b947..000000000000
--- a/include/asm-mips/tx4938/tx4938_mips.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * linux/include/asm-mips/tx4938/tx4938_mips.h
3 * Generic bitmask definitions
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12
13#ifndef TX4938_TX4938_MIPS_H
14#define TX4938_TX4938_MIPS_H
15#ifndef __ASSEMBLY__
16
17#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
18#define reg_rd16(r) ((u16)(*((vu16*)(r))))
19#define reg_rd32(r) ((u32)(*((vu32*)(r))))
20#define reg_rd64(r) ((u64)(*((vu64*)(r))))
21
22#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v)))
23#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v)))
24#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v)))
25#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v)))
26
27typedef volatile __signed char vs8;
28typedef volatile unsigned char vu8;
29
30typedef volatile __signed short vs16;
31typedef volatile unsigned short vu16;
32
33typedef volatile __signed int vs32;
34typedef volatile unsigned int vu32;
35
36typedef s8 s08;
37typedef vs8 vs08;
38
39typedef u8 u08;
40typedef vu8 vu08;
41
42#if (_MIPS_SZLONG == 64)
43
44typedef volatile __signed__ long vs64;
45typedef volatile unsigned long vu64;
46
47#else
48
49typedef volatile __signed__ long long vs64;
50typedef volatile unsigned long long vu64;
51
52#endif
53#endif
54#endif
diff --git a/include/asm-mips/txx9pio.h b/include/asm-mips/txx9pio.h
new file mode 100644
index 000000000000..3d6fa9f8d513
--- /dev/null
+++ b/include/asm-mips/txx9pio.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-mips/txx9pio.h
3 * TX39/TX49 PIO controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9PIO_H
10#define __ASM_TXX9PIO_H
11
12#include <linux/types.h>
13
14struct txx9_pio_reg {
15 __u32 dout;
16 __u32 din;
17 __u32 dir;
18 __u32 od;
19 __u32 flag[2];
20 __u32 pol;
21 __u32 intc;
22 __u32 maskcpu;
23 __u32 maskext;
24};
25
26int txx9_gpio_init(unsigned long baseaddr,
27 unsigned int base, unsigned int num);
28
29#endif /* __ASM_TXX9PIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 12:53:54 -0500