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-rw-r--r--include/asm-mips/cacheflush.h2
-rw-r--r--include/asm-mips/galileo-boards/ev96100.h55
-rw-r--r--include/asm-mips/galileo-boards/ev96100int.h12
-rw-r--r--include/asm-mips/irqflags.h25
-rw-r--r--include/asm-mips/mach-ev64120/mach-gt64120.h1
-rw-r--r--include/asm-mips/serial.h17
-rw-r--r--include/asm-mips/stacktrace.h44
7 files changed, 78 insertions, 78 deletions
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 36416fdfcf68..9ab59e2bb233 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -46,8 +46,6 @@ static inline void flush_dcache_page(struct page *page)
46#define flush_dcache_mmap_lock(mapping) do { } while (0) 46#define flush_dcache_mmap_lock(mapping) do { } while (0)
47#define flush_dcache_mmap_unlock(mapping) do { } while (0) 47#define flush_dcache_mmap_unlock(mapping) do { } while (0)
48 48
49extern void (*__flush_icache_page)(struct vm_area_struct *vma,
50 struct page *page);
51static inline void flush_icache_page(struct vm_area_struct *vma, 49static inline void flush_icache_page(struct vm_area_struct *vma,
52 struct page *page) 50 struct page *page)
53{ 51{
diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h
deleted file mode 100644
index 070dfd84a8e8..000000000000
--- a/include/asm-mips/galileo-boards/ev96100.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 *
3 */
4#ifndef _MIPS_EV96100_H
5#define _MIPS_EV96100_H
6
7#include <asm/addrspace.h>
8
9/*
10 * GT64120 config space base address
11 */
12#define GT64120_BASE (KSEG1ADDR(0x14000000))
13#define MIPS_GT_BASE GT64120_BASE
14
15/*
16 * PCI Bus allocation
17 */
18#define GT_PCI_MEM_BASE 0x12000000UL
19#define GT_PCI_MEM_SIZE 0x02000000UL
20#define GT_PCI_IO_BASE 0x10000000UL
21#define GT_PCI_IO_SIZE 0x02000000UL
22#define GT_ISA_IO_BASE PCI_IO_BASE
23
24/*
25 * Duart I/O ports.
26 */
27#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
28#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
29
30
31/*
32 * EV96100 interrupt controller register base.
33 */
34#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
35
36/*
37 * EV96100 UART register base.
38 */
39#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
40#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
41#define EV96100_BASE_BAUD ( 3686400 / 16 )
42
43
44/*
45 * Because of an error/peculiarity in the Galileo chip, we need to swap the
46 * bytes when running bigendian.
47 */
48#define __GT_READ(ofs) \
49 (*(volatile u32 *)(GT64120_BASE+(ofs)))
50#define __GT_WRITE(ofs, data) \
51 do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
52#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
53#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
54
55#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/ev96100int.h b/include/asm-mips/galileo-boards/ev96100int.h
deleted file mode 100644
index c58b16d06d6e..000000000000
--- a/include/asm-mips/galileo-boards/ev96100int.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 *
3 */
4#ifndef _MIPS_EV96100INT_H
5#define _MIPS_EV96100INT_H
6
7#define EV96100INT_UART_0 6 /* IP 6 */
8#define EV96100INT_TIMER 7 /* IP 7 */
9
10extern void ev96100int_init(void);
11
12#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index 43ca09a3a3d0..46bf5de5ac72 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -213,12 +213,37 @@ static inline int raw_irqs_disabled_flags(unsigned long flags)
213 * Do the CPU's IRQ-state tracing from assembly code. 213 * Do the CPU's IRQ-state tracing from assembly code.
214 */ 214 */
215#ifdef CONFIG_TRACE_IRQFLAGS 215#ifdef CONFIG_TRACE_IRQFLAGS
216/* Reload some registers clobbered by trace_hardirqs_on */
217#ifdef CONFIG_64BIT
218# define TRACE_IRQS_RELOAD_REGS \
219 LONG_L $11, PT_R11(sp); \
220 LONG_L $10, PT_R10(sp); \
221 LONG_L $9, PT_R9(sp); \
222 LONG_L $8, PT_R8(sp); \
223 LONG_L $7, PT_R7(sp); \
224 LONG_L $6, PT_R6(sp); \
225 LONG_L $5, PT_R5(sp); \
226 LONG_L $4, PT_R4(sp); \
227 LONG_L $2, PT_R2(sp)
228#else
229# define TRACE_IRQS_RELOAD_REGS \
230 LONG_L $7, PT_R7(sp); \
231 LONG_L $6, PT_R6(sp); \
232 LONG_L $5, PT_R5(sp); \
233 LONG_L $4, PT_R4(sp); \
234 LONG_L $2, PT_R2(sp)
235#endif
216# define TRACE_IRQS_ON \ 236# define TRACE_IRQS_ON \
237 CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
217 jal trace_hardirqs_on 238 jal trace_hardirqs_on
239# define TRACE_IRQS_ON_RELOAD \
240 TRACE_IRQS_ON; \
241 TRACE_IRQS_RELOAD_REGS
218# define TRACE_IRQS_OFF \ 242# define TRACE_IRQS_OFF \
219 jal trace_hardirqs_off 243 jal trace_hardirqs_off
220#else 244#else
221# define TRACE_IRQS_ON 245# define TRACE_IRQS_ON
246# define TRACE_IRQS_ON_RELOAD
222# define TRACE_IRQS_OFF 247# define TRACE_IRQS_OFF
223#endif 248#endif
224 249
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
index 13b1443a7a65..7e272ce57ea3 100644
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ b/include/asm-mips/mach-ev64120/mach-gt64120.h
@@ -42,6 +42,7 @@ extern unsigned long gt64120_base;
42#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) 42#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
43#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) 43#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
44#define EV64120_BASE_BAUD ( 3686400 / 16 ) 44#define EV64120_BASE_BAUD ( 3686400 / 16 )
45#define EV64120_UART_IRQ 6
45 46
46/* 47/*
47 * PCI interrupts will come in on either the INTA or INTD interrups lines, 48 * PCI interrupts will come in on either the INTA or INTD interrups lines,
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 035637c67e7c..c882e04e1497 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -55,19 +55,18 @@
55 * Galileo EV64120 evaluation board 55 * Galileo EV64120 evaluation board
56 */ 56 */
57#ifdef CONFIG_MIPS_EV64120 57#ifdef CONFIG_MIPS_EV64120
58#include <asm/galileo-boards/ev96100.h> 58#include <mach-gt64120.h>
59#include <asm/galileo-boards/ev96100int.h> 59#define EV64120_SERIAL_PORT_DEFNS \
60#define EV96100_SERIAL_PORT_DEFNS \ 60 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
61 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
62 .flags = STD_COM_FLAGS, \ 61 .flags = STD_COM_FLAGS, \
63 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \ 62 .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
64 .io_type = SERIAL_IO_MEM }, \ 63 .io_type = SERIAL_IO_MEM }, \
65 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ 64 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
66 .flags = STD_COM_FLAGS, \ 65 .flags = STD_COM_FLAGS, \
67 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \ 66 .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
68 .io_type = SERIAL_IO_MEM }, 67 .io_type = SERIAL_IO_MEM },
69#else 68#else
70#define EV96100_SERIAL_PORT_DEFNS 69#define EV64120_SERIAL_PORT_DEFNS
71#endif 70#endif
72 71
73#ifdef CONFIG_MIPS_ITE8172 72#ifdef CONFIG_MIPS_ITE8172
@@ -239,7 +238,7 @@
239 238
240#define SERIAL_PORT_DFNS \ 239#define SERIAL_PORT_DFNS \
241 DDB5477_SERIAL_PORT_DEFNS \ 240 DDB5477_SERIAL_PORT_DEFNS \
242 EV96100_SERIAL_PORT_DEFNS \ 241 EV64120_SERIAL_PORT_DEFNS \
243 IP32_SERIAL_PORT_DEFNS \ 242 IP32_SERIAL_PORT_DEFNS \
244 ITE_SERIAL_PORT_DEFNS \ 243 ITE_SERIAL_PORT_DEFNS \
245 IVR_SERIAL_PORT_DEFNS \ 244 IVR_SERIAL_PORT_DEFNS \
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
new file mode 100644
index 000000000000..07f873351a86
--- /dev/null
+++ b/include/asm-mips/stacktrace.h
@@ -0,0 +1,44 @@
1#ifndef _ASM_STACKTRACE_H
2#define _ASM_STACKTRACE_H
3
4#include <asm/ptrace.h>
5
6#ifdef CONFIG_KALLSYMS
7extern int raw_show_trace;
8extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
9 unsigned long pc, unsigned long *ra);
10#else
11#define raw_show_trace 1
12#define unwind_stack(task, sp, pc, ra) 0
13#endif
14
15static __always_inline void prepare_frametrace(struct pt_regs *regs)
16{
17#ifndef CONFIG_KALLSYMS
18 /*
19 * Remove any garbage that may be in regs (specially func
20 * addresses) to avoid show_raw_backtrace() to report them
21 */
22 memset(regs, 0, sizeof(*regs));
23#endif
24 __asm__ __volatile__(
25 ".set push\n\t"
26 ".set noat\n\t"
27#ifdef CONFIG_64BIT
28 "1: dla $1, 1b\n\t"
29 "sd $1, %0\n\t"
30 "sd $29, %1\n\t"
31 "sd $31, %2\n\t"
32#else
33 "1: la $1, 1b\n\t"
34 "sw $1, %0\n\t"
35 "sw $29, %1\n\t"
36 "sw $31, %2\n\t"
37#endif
38 ".set pop\n\t"
39 : "=m" (regs->cp0_epc),
40 "=m" (regs->regs[29]), "=m" (regs->regs[31])
41 : : "memory");
42}
43
44#endif /* _ASM_STACKTRACE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 09:13:05 -0500