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-rw-r--r--include/asm-mips/Kbuild2
-rw-r--r--include/asm-mips/bootinfo.h3
-rw-r--r--include/asm-mips/cacheflush.h12
-rw-r--r--include/asm-mips/fcntl.h2
-rw-r--r--include/asm-mips/galileo-boards/gt96100.h427
-rw-r--r--include/asm-mips/hazards.h360
-rw-r--r--include/asm-mips/irq.h4
-rw-r--r--include/asm-mips/mach-atlas/mc146818rtc.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h6
-rw-r--r--include/asm-mips/mach-ev96100/mach-gt64120.h46
-rw-r--r--include/asm-mips/mach-excite/excite.h2
-rw-r--r--include/asm-mips/mach-excite/excite_fpga.h80
-rw-r--r--include/asm-mips/mach-qemu/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mips-boards/atlasint.h124
-rw-r--r--include/asm-mips/mmu_context.h8
-rw-r--r--include/asm-mips/page.h11
-rw-r--r--include/asm-mips/pgtable-32.h4
-rw-r--r--include/asm-mips/pgtable-64.h16
-rw-r--r--include/asm-mips/pgtable.h2
-rw-r--r--include/asm-mips/ptrace.h3
-rw-r--r--include/asm-mips/serial.h4
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h6
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h2
-rw-r--r--include/asm-mips/signal.h11
-rw-r--r--include/asm-mips/spinlock.h47
-rw-r--r--include/asm-mips/timex.h4
-rw-r--r--include/asm-mips/unistd.h24
-rw-r--r--include/asm-mips/user.h4
28 files changed, 413 insertions, 807 deletions
diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild
index c68e1680da01..7897f05e3165 100644
--- a/include/asm-mips/Kbuild
+++ b/include/asm-mips/Kbuild
@@ -1 +1,3 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2
3header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 3b745e76f429..78c35ec46362 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -112,8 +112,7 @@
112 * Valid machtype for group GALILEO 112 * Valid machtype for group GALILEO
113 */ 113 */
114#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ 114#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */
115#define MACH_EV96100 0 /* EV96100 */ 115#define MACH_EV64120A 0 /* EV64120A */
116#define MACH_EV64120A 1 /* EV64120A */
117 116
118/* 117/*
119 * Valid machtype for group MOMENCO 118 * Valid machtype for group MOMENCO
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 47bc8f6c20d2..36416fdfcf68 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -21,7 +21,6 @@
21 * - flush_cache_range(vma, start, end) flushes a range of pages 21 * - flush_cache_range(vma, start, end) flushes a range of pages
22 * - flush_icache_range(start, end) flush a range of instructions 22 * - flush_icache_range(start, end) flush a range of instructions
23 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache 23 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 * 24 *
26 * MIPS specific flush operations: 25 * MIPS specific flush operations:
27 * 26 *
@@ -39,7 +38,7 @@ extern void __flush_dcache_page(struct page *page);
39 38
40static inline void flush_dcache_page(struct page *page) 39static inline void flush_dcache_page(struct page *page)
41{ 40{
42 if (cpu_has_dc_aliases) 41 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
43 __flush_dcache_page(page); 42 __flush_dcache_page(page);
44 43
45} 44}
@@ -47,8 +46,13 @@ static inline void flush_dcache_page(struct page *page)
47#define flush_dcache_mmap_lock(mapping) do { } while (0) 46#define flush_dcache_mmap_lock(mapping) do { } while (0)
48#define flush_dcache_mmap_unlock(mapping) do { } while (0) 47#define flush_dcache_mmap_unlock(mapping) do { } while (0)
49 48
50extern void (*flush_icache_page)(struct vm_area_struct *vma, 49extern void (*__flush_icache_page)(struct vm_area_struct *vma,
51 struct page *page); 50 struct page *page);
51static inline void flush_icache_page(struct vm_area_struct *vma,
52 struct page *page)
53{
54}
55
52extern void (*flush_icache_range)(unsigned long start, unsigned long end); 56extern void (*flush_icache_range)(unsigned long start, unsigned long end);
53#define flush_cache_vmap(start, end) flush_cache_all() 57#define flush_cache_vmap(start, end) flush_cache_all()
54#define flush_cache_vunmap(start, end) flush_cache_all() 58#define flush_cache_vunmap(start, end) flush_cache_all()
@@ -60,7 +64,7 @@ static inline void copy_to_user_page(struct vm_area_struct *vma,
60 if (cpu_has_dc_aliases) 64 if (cpu_has_dc_aliases)
61 flush_cache_page(vma, vaddr, page_to_pfn(page)); 65 flush_cache_page(vma, vaddr, page_to_pfn(page));
62 memcpy(dst, src, len); 66 memcpy(dst, src, len);
63 flush_icache_page(vma, page); 67 __flush_icache_page(vma, page);
64} 68}
65 69
66static inline void copy_from_user_page(struct vm_area_struct *vma, 70static inline void copy_from_user_page(struct vm_area_struct *vma,
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 787220e6c1fc..00a50ec1c19f 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -25,8 +25,6 @@
25 25
26#define F_SETOWN 24 /* for sockets. */ 26#define F_SETOWN 24 /* for sockets. */
27#define F_GETOWN 23 /* for sockets. */ 27#define F_GETOWN 23 /* for sockets. */
28#define F_SETSIG 10 /* for sockets. */
29#define F_GETSIG 11 /* for sockets. */
30 28
31#ifndef __mips64 29#ifndef __mips64
32#define F_GETLK64 33 /* using 'struct flock64' */ 30#define F_GETLK64 33 /* using 'struct flock64' */
diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h
deleted file mode 100644
index aabd1b629c19..000000000000
--- a/include/asm-mips/galileo-boards/gt96100.h
+++ /dev/null
@@ -1,427 +0,0 @@
1/*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Register offsets of the MIPS GT96100 Advanced Communication Controller.
20 */
21#ifndef _GT96100_H
22#define _GT96100_H
23
24/*
25 * Galileo GT96100 internal register base.
26 */
27#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
28
29#define GT96100_WRITE(ofs, data) \
30 *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
31#define GT96100_READ(ofs) \
32 le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
33
34#define GT96100_ETH_IO_SIZE 0x4000
35
36/************************************************************************
37 * Register offset addresses follow
38 ************************************************************************/
39
40/* CPU Interface Control Registers */
41#define GT96100_CPU_INTERF_CONFIG 0x000000
42
43/* Ethernet Ports */
44#define GT96100_ETH_PHY_ADDR_REG 0x080800
45#define GT96100_ETH_SMI_REG 0x080810
46/*
47 These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
48 get offsets to port 1 registers.
49*/
50#define GT96100_ETH_PORT_CONFIG 0x084800
51#define GT96100_ETH_PORT_CONFIG_EXT 0x084808
52#define GT96100_ETH_PORT_COMM 0x084810
53#define GT96100_ETH_PORT_STATUS 0x084818
54#define GT96100_ETH_SER_PARAM 0x084820
55#define GT96100_ETH_HASH_TBL_PTR 0x084828
56#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830
57#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838
58#define GT96100_ETH_SDMA_CONFIG 0x084840
59#define GT96100_ETH_SDMA_COMM 0x084848
60#define GT96100_ETH_INT_CAUSE 0x084850
61#define GT96100_ETH_INT_MASK 0x084858
62#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880
63#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884
64#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888
65#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C
66#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0
67#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4
68#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8
69#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC
70#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0
71#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4
72#define GT96100_ETH_MIB_COUNT_BASE 0x085800
73
74/* SDMAs */
75#define GT96100_SDMA_GROUP_CONFIG 0x101AF0
76/* SDMA Group 0 */
77#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900
78#define GT96100_SDMA_G0_CHAN0_COMM 0x000908
79#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900
80#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910
81#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900
82#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910
83#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914
84#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900
85#define GT96100_SDMA_G0_CHAN1_COMM 0x010908
86#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900
87#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910
88#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900
89#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910
90#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914
91#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900
92#define GT96100_SDMA_G0_CHAN2_COMM 0x020908
93#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900
94#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910
95#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900
96#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910
97#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914
98#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900
99#define GT96100_SDMA_G0_CHAN3_COMM 0x030908
100#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900
101#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910
102#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900
103#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910
104#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914
105#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900
106#define GT96100_SDMA_G0_CHAN4_COMM 0x040908
107#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900
108#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910
109#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900
110#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910
111#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914
112#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900
113#define GT96100_SDMA_G0_CHAN5_COMM 0x050908
114#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900
115#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910
116#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900
117#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910
118#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914
119#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900
120#define GT96100_SDMA_G0_CHAN6_COMM 0x060908
121#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900
122#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910
123#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900
124#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910
125#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914
126#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900
127#define GT96100_SDMA_G0_CHAN7_COMM 0x070908
128#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900
129#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910
130#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900
131#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910
132#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914
133/* SDMA Group 1 */
134#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900
135#define GT96100_SDMA_G1_CHAN0_COMM 0x100908
136#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900
137#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910
138#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900
139#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910
140#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914
141#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900
142#define GT96100_SDMA_G1_CHAN1_COMM 0x110908
143#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900
144#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910
145#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900
146#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910
147#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914
148#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900
149#define GT96100_SDMA_G1_CHAN2_COMM 0x120908
150#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900
151#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910
152#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900
153#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910
154#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914
155#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900
156#define GT96100_SDMA_G1_CHAN3_COMM 0x130908
157#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900
158#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910
159#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900
160#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910
161#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914
162#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900
163#define GT96100_SDMA_G1_CHAN4_COMM 0x140908
164#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900
165#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910
166#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900
167#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910
168#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914
169#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900
170#define GT96100_SDMA_G1_CHAN5_COMM 0x150908
171#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900
172#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910
173#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900
174#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910
175#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914
176#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900
177#define GT96100_SDMA_G1_CHAN6_COMM 0x160908
178#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900
179#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910
180#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900
181#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910
182#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914
183#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900
184#define GT96100_SDMA_G1_CHAN7_COMM 0x170908
185#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900
186#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910
187#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900
188#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910
189#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914
190/* MPSCs */
191#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00
192#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04
193#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08
194#define GT96100_MPSC_CHAN0_REG1 0x000A0C
195#define GT96100_MPSC_CHAN0_REG2 0x000A10
196#define GT96100_MPSC_CHAN0_REG3 0x000A14
197#define GT96100_MPSC_CHAN0_REG4 0x000A18
198#define GT96100_MPSC_CHAN0_REG5 0x000A1C
199#define GT96100_MPSC_CHAN0_REG6 0x000A20
200#define GT96100_MPSC_CHAN0_REG7 0x000A24
201#define GT96100_MPSC_CHAN0_REG8 0x000A28
202#define GT96100_MPSC_CHAN0_REG9 0x000A2C
203#define GT96100_MPSC_CHAN0_REG10 0x000A30
204#define GT96100_MPSC_CHAN0_REG11 0x000A34
205#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00
206#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04
207#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08
208#define GT96100_MPSC_CHAN1_REG1 0x008A0C
209#define GT96100_MPSC_CHAN1_REG2 0x008A10
210#define GT96100_MPSC_CHAN1_REG3 0x008A14
211#define GT96100_MPSC_CHAN1_REG4 0x008A18
212#define GT96100_MPSC_CHAN1_REG5 0x008A1C
213#define GT96100_MPSC_CHAN1_REG6 0x008A20
214#define GT96100_MPSC_CHAN1_REG7 0x008A24
215#define GT96100_MPSC_CHAN1_REG8 0x008A28
216#define GT96100_MPSC_CHAN1_REG9 0x008A2C
217#define GT96100_MPSC_CHAN1_REG10 0x008A30
218#define GT96100_MPSC_CHAN1_REG11 0x008A34
219#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00
220#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04
221#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08
222#define GT96100_MPSC_CHAN2_REG1 0x010A0C
223#define GT96100_MPSC_CHAN2_REG2 0x010A10
224#define GT96100_MPSC_CHAN2_REG3 0x010A14
225#define GT96100_MPSC_CHAN2_REG4 0x010A18
226#define GT96100_MPSC_CHAN2_REG5 0x010A1C
227#define GT96100_MPSC_CHAN2_REG6 0x010A20
228#define GT96100_MPSC_CHAN2_REG7 0x010A24
229#define GT96100_MPSC_CHAN2_REG8 0x010A28
230#define GT96100_MPSC_CHAN2_REG9 0x010A2C
231#define GT96100_MPSC_CHAN2_REG10 0x010A30
232#define GT96100_MPSC_CHAN2_REG11 0x010A34
233#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00
234#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04
235#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08
236#define GT96100_MPSC_CHAN3_REG1 0x018A0C
237#define GT96100_MPSC_CHAN3_REG2 0x018A10
238#define GT96100_MPSC_CHAN3_REG3 0x018A14
239#define GT96100_MPSC_CHAN3_REG4 0x018A18
240#define GT96100_MPSC_CHAN3_REG5 0x018A1C
241#define GT96100_MPSC_CHAN3_REG6 0x018A20
242#define GT96100_MPSC_CHAN3_REG7 0x018A24
243#define GT96100_MPSC_CHAN3_REG8 0x018A28
244#define GT96100_MPSC_CHAN3_REG9 0x018A2C
245#define GT96100_MPSC_CHAN3_REG10 0x018A30
246#define GT96100_MPSC_CHAN3_REG11 0x018A34
247#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00
248#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04
249#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08
250#define GT96100_MPSC_CHAN4_REG1 0x020A0C
251#define GT96100_MPSC_CHAN4_REG2 0x020A10
252#define GT96100_MPSC_CHAN4_REG3 0x020A14
253#define GT96100_MPSC_CHAN4_REG4 0x020A18
254#define GT96100_MPSC_CHAN4_REG5 0x020A1C
255#define GT96100_MPSC_CHAN4_REG6 0x020A20
256#define GT96100_MPSC_CHAN4_REG7 0x020A24
257#define GT96100_MPSC_CHAN4_REG8 0x020A28
258#define GT96100_MPSC_CHAN4_REG9 0x020A2C
259#define GT96100_MPSC_CHAN4_REG10 0x020A30
260#define GT96100_MPSC_CHAN4_REG11 0x020A34
261#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00
262#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04
263#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08
264#define GT96100_MPSC_CHAN5_REG1 0x028A0C
265#define GT96100_MPSC_CHAN5_REG2 0x028A10
266#define GT96100_MPSC_CHAN5_REG3 0x028A14
267#define GT96100_MPSC_CHAN5_REG4 0x028A18
268#define GT96100_MPSC_CHAN5_REG5 0x028A1C
269#define GT96100_MPSC_CHAN5_REG6 0x028A20
270#define GT96100_MPSC_CHAN5_REG7 0x028A24
271#define GT96100_MPSC_CHAN5_REG8 0x028A28
272#define GT96100_MPSC_CHAN5_REG9 0x028A2C
273#define GT96100_MPSC_CHAN5_REG10 0x028A30
274#define GT96100_MPSC_CHAN5_REG11 0x028A34
275#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00
276#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04
277#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08
278#define GT96100_MPSC_CHAN6_REG1 0x030A0C
279#define GT96100_MPSC_CHAN6_REG2 0x030A10
280#define GT96100_MPSC_CHAN6_REG3 0x030A14
281#define GT96100_MPSC_CHAN6_REG4 0x030A18
282#define GT96100_MPSC_CHAN6_REG5 0x030A1C
283#define GT96100_MPSC_CHAN6_REG6 0x030A20
284#define GT96100_MPSC_CHAN6_REG7 0x030A24
285#define GT96100_MPSC_CHAN6_REG8 0x030A28
286#define GT96100_MPSC_CHAN6_REG9 0x030A2C
287#define GT96100_MPSC_CHAN6_REG10 0x030A30
288#define GT96100_MPSC_CHAN6_REG11 0x030A34
289#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00
290#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04
291#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08
292#define GT96100_MPSC_CHAN7_REG1 0x038A0C
293#define GT96100_MPSC_CHAN7_REG2 0x038A10
294#define GT96100_MPSC_CHAN7_REG3 0x038A14
295#define GT96100_MPSC_CHAN7_REG4 0x038A18
296#define GT96100_MPSC_CHAN7_REG5 0x038A1C
297#define GT96100_MPSC_CHAN7_REG6 0x038A20
298#define GT96100_MPSC_CHAN7_REG7 0x038A24
299#define GT96100_MPSC_CHAN7_REG8 0x038A28
300#define GT96100_MPSC_CHAN7_REG9 0x038A2C
301#define GT96100_MPSC_CHAN7_REG10 0x038A30
302#define GT96100_MPSC_CHAN7_REG11 0x038A34
303/* FlexTDMs */
304/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
305#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00
306#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00
307#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00
308#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00
309/* RDPR0 - Receive Dual Port RAM. block size 0xff */
310#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00
311#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00
312#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00
313#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00
314#define GT96100_FXTDM0_TX_READ_PTR 0x008B00
315#define GT96100_FXTDM0_RX_READ_PTR 0x008B04
316#define GT96100_FXTDM0_CONFIG 0x008B08
317#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
318#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
319#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
320#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
321#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00
322#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00
323#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00
324#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00
325#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00
326#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00
327#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00
328#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00
329#define GT96100_FXTDM1_TX_READ_PTR 0x018B00
330#define GT96100_FXTDM1_RX_READ_PTR 0x018B04
331#define GT96100_FXTDM1_CONFIG 0x018B08
332#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
333#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
334#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
335#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
336#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00
337#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00
338#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00
339#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00
340#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00
341#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00
342#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00
343#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00
344#define GT96100_FLTDM2_TX_READ_PTR 0x028B00
345#define GT96100_FLTDM2_RX_READ_PTR 0x028B04
346#define GT96100_FLTDM2_CONFIG 0x028B08
347#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
348#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
349#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
350#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
351#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00
352#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00
353#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00
354#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00
355#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00
356#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00
357#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00
358#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00
359#define GT96100_FXTDM3_TX_READ_PTR 0x038B00
360#define GT96100_FXTDM3_RX_READ_PTR 0x038B04
361#define GT96100_FXTDM3_CONFIG 0x038B08
362#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
363#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
364#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
365#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
366/* Baud Rate Generators */
367#define GT96100_BRG0_CONFIG 0x102A00
368#define GT96100_BRG0_BAUD_TUNE 0x102A04
369#define GT96100_BRG1_CONFIG 0x102A08
370#define GT96100_BRG1_BAUD_TUNE 0x102A0C
371#define GT96100_BRG2_CONFIG 0x102A10
372#define GT96100_BRG2_BAUD_TUNE 0x102A14
373#define GT96100_BRG3_CONFIG 0x102A18
374#define GT96100_BRG3_BAUD_TUNE 0x102A1C
375#define GT96100_BRG4_CONFIG 0x102A20
376#define GT96100_BRG4_BAUD_TUNE 0x102A24
377#define GT96100_BRG5_CONFIG 0x102A28
378#define GT96100_BRG5_BAUD_TUNE 0x102A2C
379#define GT96100_BRG6_CONFIG 0x102A30
380#define GT96100_BRG6_BAUD_TUNE 0x102A34
381#define GT96100_BRG7_CONFIG 0x102A38
382#define GT96100_BRG7_BAUD_TUNE 0x102A3C
383/* Routing Registers */
384#define GT96100_ROUTE_MAIN 0x101A00
385#define GT96100_ROUTE_RX_CLOCK 0x101A10
386#define GT96100_ROUTE_TX_CLOCK 0x101A20
387/* General Purpose Ports */
388#define GT96100_GPP_CONFIG0 0x100A00
389#define GT96100_GPP_CONFIG1 0x100A04
390#define GT96100_GPP_CONFIG2 0x100A08
391#define GT96100_GPP_CONFIG3 0x100A0C
392#define GT96100_GPP_IO0 0x100A20
393#define GT96100_GPP_IO1 0x100A24
394#define GT96100_GPP_IO2 0x100A28
395#define GT96100_GPP_IO3 0x100A2C
396#define GT96100_GPP_DATA0 0x100A40
397#define GT96100_GPP_DATA1 0x100A44
398#define GT96100_GPP_DATA2 0x100A48
399#define GT96100_GPP_DATA3 0x100A4C
400#define GT96100_GPP_LEVEL0 0x100A60
401#define GT96100_GPP_LEVEL1 0x100A64
402#define GT96100_GPP_LEVEL2 0x100A68
403#define GT96100_GPP_LEVEL3 0x100A6C
404/* Watchdog */
405#define GT96100_WD_CONFIG 0x101A80
406#define GT96100_WD_VALUE 0x101A84
407/* Communication Unit Arbiter */
408#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
409/* PCI Arbiters */
410#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
411#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
412/* CIU Arbiter */
413#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
414/* Interrupt Controller */
415#define GT96100_MAIN_CAUSE 0x000C18
416#define GT96100_INT0_MAIN_MASK 0x000C1C
417#define GT96100_INT1_MAIN_MASK 0x000C24
418#define GT96100_HIGH_CAUSE 0x000C98
419#define GT96100_INT0_HIGH_MASK 0x000C9C
420#define GT96100_INT1_HIGH_MASK 0x000CA4
421#define GT96100_INT0_SELECT 0x000C70
422#define GT96100_INT1_SELECT 0x000C74
423#define GT96100_SERIAL_CAUSE 0x103A00
424#define GT96100_SERINT0_MASK 0x103A80
425#define GT96100_SERINT1_MASK 0x103A88
426
427#endif /* _GT96100_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 25f5e8a4177d..0fe02945feba 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -12,102 +12,95 @@
12 12
13 13
14#ifdef __ASSEMBLY__ 14#ifdef __ASSEMBLY__
15 15#define ASMMACRO(name, code...) .macro name; code; .endm
16 .macro _ssnop
17 sll $0, $0, 1
18 .endm
19
20 .macro _ehb
21 sll $0, $0, 3
22 .endm
23
24/*
25 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
26 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
27 * for data translations should not occur for 3 cpu cycles.
28 */
29#ifdef CONFIG_CPU_RM9000
30
31 .macro mtc0_tlbw_hazard
32 .set push
33 .set mips32
34 _ssnop; _ssnop; _ssnop; _ssnop
35 .set pop
36 .endm
37
38 .macro tlbw_eret_hazard
39 .set push
40 .set mips32
41 _ssnop; _ssnop; _ssnop; _ssnop
42 .set pop
43 .endm
44
45#else 16#else
46 17
47/* 18#define ASMMACRO(name, code...) \
48 * The taken branch will result in a two cycle penalty for the two killed 19__asm__(".macro " #name "; " #code "; .endm"); \
49 * instructions on R4000 / R4400. Other processors only have a single cycle 20 \
50 * hazard so this is nice trick to have an optimal code for a range of 21static inline void name(void) \
51 * processors. 22{ \
52 */ 23 __asm__ __volatile__ (#name); \
53 .macro mtc0_tlbw_hazard 24}
54 b . + 8
55 .endm
56 25
57 .macro tlbw_eret_hazard
58 .endm
59#endif 26#endif
60 27
28ASMMACRO(_ssnop,
29 sll $0, $0, 1
30 )
31
32ASMMACRO(_ehb,
33 sll $0, $0, 3
34 )
35
61/* 36/*
62 * mtc0->mfc0 hazard 37 * TLB hazards
63 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
64 * It is a MIPS32R2 processor so ehb will clear the hazard.
65 */ 38 */
39#if defined(CONFIG_CPU_MIPSR2)
66 40
67#ifdef CONFIG_CPU_MIPSR2
68/* 41/*
69 * Use a macro for ehb unless explicit support for MIPSR2 is enabled 42 * MIPSR2 defines ehb for hazard avoidance
70 */ 43 */
71 44
72#define irq_enable_hazard \ 45ASMMACRO(mtc0_tlbw_hazard,
46 _ehb
47 )
48ASMMACRO(tlbw_use_hazard,
49 _ehb
50 )
51ASMMACRO(tlb_probe_hazard,
52 _ehb
53 )
54ASMMACRO(irq_enable_hazard,
55 )
56ASMMACRO(irq_disable_hazard,
73 _ehb 57 _ehb
74 58 )
75#define irq_disable_hazard \ 59ASMMACRO(back_to_back_c0_hazard,
76 _ehb 60 _ehb
77 61 )
78#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
79
80/* 62/*
81 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 63 * gcc has a tradition of misscompiling the previous construct using the
64 * address of a label as argument to inline assembler. Gas otoh has the
65 * annoying difference between la and dla which are only usable for 32-bit
66 * rsp. 64-bit code, so can't be used without conditional compilation.
67 * The alterantive is switching the assembler to 64-bit code which happens
68 * to work right even for 32-bit code ...
82 */ 69 */
70#define instruction_hazard() \
71do { \
72 unsigned long tmp; \
73 \
74 __asm__ __volatile__( \
75 " .set mips64r2 \n" \
76 " dla %0, 1f \n" \
77 " jr.hb %0 \n" \
78 " .set mips0 \n" \
79 "1: \n" \
80 : "=r" (tmp)); \
81} while (0)
83 82
84#define irq_enable_hazard 83#elif defined(CONFIG_CPU_R10000)
85
86#define irq_disable_hazard
87
88#else
89 84
90/* 85/*
91 * Classic MIPS needs 1 - 3 nops or ssnops 86 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
92 */ 87 */
93#define irq_enable_hazard
94#define irq_disable_hazard \
95 _ssnop; _ssnop; _ssnop
96 88
97#endif 89ASMMACRO(mtc0_tlbw_hazard,
98 90 )
99#else /* __ASSEMBLY__ */ 91ASMMACRO(tlbw_use_hazard,
100 92 )
101__asm__( 93ASMMACRO(tlb_probe_hazard,
102 " .macro _ssnop \n" 94 )
103 " sll $0, $0, 1 \n" 95ASMMACRO(irq_enable_hazard,
104 " .endm \n" 96 )
105 " \n" 97ASMMACRO(irq_disable_hazard,
106 " .macro _ehb \n" 98 )
107 " sll $0, $0, 3 \n" 99ASMMACRO(back_to_back_c0_hazard,
108 " .endm \n"); 100 )
101#define instruction_hazard() do { } while (0)
109 102
110#ifdef CONFIG_CPU_RM9000 103#elif defined(CONFIG_CPU_RM9000)
111 104
112/* 105/*
113 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent 106 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
@@ -115,176 +108,73 @@ __asm__(
115 * for data translations should not occur for 3 cpu cycles. 108 * for data translations should not occur for 3 cpu cycles.
116 */ 109 */
117 110
118#define mtc0_tlbw_hazard() \ 111ASMMACRO(mtc0_tlbw_hazard,
119 __asm__ __volatile__( \ 112 _ssnop; _ssnop; _ssnop; _ssnop
120 " .set mips32 \n" \ 113 )
121 " _ssnop \n" \ 114ASMMACRO(tlbw_use_hazard,
122 " _ssnop \n" \ 115 _ssnop; _ssnop; _ssnop; _ssnop
123 " _ssnop \n" \ 116 )
124 " _ssnop \n" \ 117ASMMACRO(tlb_probe_hazard,
125 " .set mips0 \n") 118 _ssnop; _ssnop; _ssnop; _ssnop
126 119 )
127#define tlbw_use_hazard() \ 120ASMMACRO(irq_enable_hazard,
128 __asm__ __volatile__( \ 121 )
129 " .set mips32 \n" \ 122ASMMACRO(irq_disable_hazard,
130 " _ssnop \n" \ 123 )
131 " _ssnop \n" \ 124ASMMACRO(back_to_back_c0_hazard,
132 " _ssnop \n" \ 125 )
133 " _ssnop \n" \ 126#define instruction_hazard() do { } while (0)
134 " .set mips0 \n")
135
136#else
137
138/*
139 * Overkill warning ...
140 */
141#define mtc0_tlbw_hazard() \
142 __asm__ __volatile__( \
143 " .set noreorder \n" \
144 " nop \n" \
145 " nop \n" \
146 " nop \n" \
147 " nop \n" \
148 " nop \n" \
149 " nop \n" \
150 " .set reorder \n")
151
152#define tlbw_use_hazard() \
153 __asm__ __volatile__( \
154 " .set noreorder \n" \
155 " nop \n" \
156 " nop \n" \
157 " nop \n" \
158 " nop \n" \
159 " nop \n" \
160 " nop \n" \
161 " .set reorder \n")
162
163#endif
164
165/*
166 * Interrupt enable/disable hazards
167 * Some processors have hazards when modifying
168 * the status register to change the interrupt state
169 */
170
171#ifdef CONFIG_CPU_MIPSR2
172
173__asm__(" .macro irq_enable_hazard \n"
174 " _ehb \n"
175 " .endm \n"
176 " \n"
177 " .macro irq_disable_hazard \n"
178 " _ehb \n"
179 " .endm \n");
180 127
181#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) 128#elif defined(CONFIG_CPU_SB1)
182 129
183/* 130/*
184 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 131 * Mostly like R4000 for historic reasons
185 */ 132 */
186 133ASMMACRO(mtc0_tlbw_hazard,
187__asm__( 134 )
188 " .macro irq_enable_hazard \n" 135ASMMACRO(tlbw_use_hazard,
189 " .endm \n" 136 )
190 " \n" 137ASMMACRO(tlb_probe_hazard,
191 " .macro irq_disable_hazard \n" 138 )
192 " .endm \n"); 139ASMMACRO(irq_enable_hazard,
140 )
141ASMMACRO(irq_disable_hazard,
142 _ssnop; _ssnop; _ssnop
143 )
144ASMMACRO(back_to_back_c0_hazard,
145 )
146#define instruction_hazard() do { } while (0)
193 147
194#else 148#else
195 149
196/* 150/*
197 * Default for classic MIPS processors. Assume worst case hazards but don't 151 * Finally the catchall case for all other processors including R4000, R4400,
198 * care about the irq_enable_hazard - sooner or later the hardware will 152 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
199 * enable it and we don't care when exactly.
200 */
201
202__asm__(
203 " # \n"
204 " # There is a hazard but we do not care \n"
205 " # \n"
206 " .macro\tirq_enable_hazard \n"
207 " .endm \n"
208 " \n"
209 " .macro\tirq_disable_hazard \n"
210 " _ssnop \n"
211 " _ssnop \n"
212 " _ssnop \n"
213 " .endm \n");
214
215#endif
216
217#define irq_enable_hazard() \
218 __asm__ __volatile__("irq_enable_hazard")
219#define irq_disable_hazard() \
220 __asm__ __volatile__("irq_disable_hazard")
221
222
223/*
224 * Back-to-back hazards -
225 * 153 *
226 * What is needed to separate a move to cp0 from a subsequent read from the 154 * The taken branch will result in a two cycle penalty for the two killed
227 * same cp0 register? 155 * instructions on R4000 / R4400. Other processors only have a single cycle
228 */ 156 * hazard so this is nice trick to have an optimal code for a range of
229#ifdef CONFIG_CPU_MIPSR2 157 * processors.
230
231__asm__(" .macro back_to_back_c0_hazard \n"
232 " _ehb \n"
233 " .endm \n");
234
235#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
236 defined(CONFIG_CPU_SB1)
237
238__asm__(" .macro back_to_back_c0_hazard \n"
239 " .endm \n");
240
241#else
242
243__asm__(" .macro back_to_back_c0_hazard \n"
244 " .set noreorder \n"
245 " _ssnop \n"
246 " _ssnop \n"
247 " _ssnop \n"
248 " .set reorder \n"
249 " .endm");
250
251#endif
252
253#define back_to_back_c0_hazard() \
254 __asm__ __volatile__("back_to_back_c0_hazard")
255
256
257/*
258 * Instruction execution hazard
259 */
260#ifdef CONFIG_CPU_MIPSR2
261/*
262 * gcc has a tradition of misscompiling the previous construct using the
263 * address of a label as argument to inline assembler. Gas otoh has the
264 * annoying difference between la and dla which are only usable for 32-bit
265 * rsp. 64-bit code, so can't be used without conditional compilation.
266 * The alterantive is switching the assembler to 64-bit code which happens
267 * to work right even for 32-bit code ...
268 */ 158 */
269#define instruction_hazard() \ 159ASMMACRO(mtc0_tlbw_hazard,
270do { \ 160 nop
271 unsigned long tmp; \ 161 )
272 \ 162ASMMACRO(tlbw_use_hazard,
273 __asm__ __volatile__( \ 163 nop; nop; nop
274 " .set mips64r2 \n" \ 164 )
275 " dla %0, 1f \n" \ 165ASMMACRO(tlb_probe_hazard,
276 " jr.hb %0 \n" \ 166 nop; nop; nop
277 " .set mips0 \n" \ 167 )
278 "1: \n" \ 168ASMMACRO(irq_enable_hazard,
279 : "=r" (tmp)); \ 169 )
280} while (0) 170ASMMACRO(irq_disable_hazard,
281 171 nop; nop; nop
282#else 172 )
173ASMMACRO(back_to_back_c0_hazard,
174 _ssnop; _ssnop; _ssnop;
175 )
283#define instruction_hazard() do { } while (0) 176#define instruction_hazard() do { } while (0)
284#endif
285
286extern void mips_ihb(void);
287 177
288#endif /* __ASSEMBLY__ */ 178#endif
289 179
290#endif /* _ASM_HAZARDS_H */ 180#endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 896550bad322..d35c61776a02 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -76,8 +76,4 @@ extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
76 unsigned long hwmask); 76 unsigned long hwmask);
77#endif /* CONFIG_MIPS_MT_SMTC */ 77#endif /* CONFIG_MIPS_MT_SMTC */
78 78
79#ifdef CONFIG_SMP
80#define ARCH_HAS_IRQ_PER_CPU
81#endif
82
83#endif /* _ASM_IRQ_H */ 79#endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
index 397522ea5565..a73a5698420c 100644
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ b/include/asm-mips/mach-atlas/mc146818rtc.h
@@ -28,10 +28,12 @@
28#include <asm/mips-boards/atlas.h> 28#include <asm/mips-boards/atlas.h>
29#include <asm/mips-boards/atlasint.h> 29#include <asm/mips-boards/atlasint.h>
30 30
31#define ARCH_RTC_LOCATION
32
31#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8) 33#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8)
32#define RTC_IO_EXTENT 0x100 34#define RTC_IO_EXTENT 0x100
33#define RTC_IOMAPPED 0 35#define RTC_IOMAPPED 0
34#define RTC_IRQ ATLASINT_RTC 36#define RTC_IRQ ATLAS_INT_RTC
35 37
36static inline unsigned char CMOS_READ(unsigned long addr) 38static inline unsigned char CMOS_READ(unsigned long addr)
37{ 39{
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5b38a247e5a..eeb0c3115b6a 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -316,7 +316,7 @@ typedef struct dbdma_chan_config {
316 au1x_ddma_desc_t *chan_desc_base; 316 au1x_ddma_desc_t *chan_desc_base;
317 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; 317 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
318 void *chan_callparam; 318 void *chan_callparam;
319 void (*chan_callback)(int, void *, struct pt_regs *); 319 void (*chan_callback)(int, void *);
320} chan_tab_t; 320} chan_tab_t;
321 321
322#define DEV_FLAGS_INUSE (1 << 0) 322#define DEV_FLAGS_INUSE (1 << 0)
@@ -334,8 +334,8 @@ typedef struct dbdma_chan_config {
334 * meaningful name. The 'callback' is called during dma completion 334 * meaningful name. The 'callback' is called during dma completion
335 * interrupt. 335 * interrupt.
336 */ 336 */
337u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 337extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
338 void (*callback)(int, void *, struct pt_regs *), void *callparam); 338 void (*callback)(int, void *), void *callparam);
339 339
340#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 340#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
341 341
diff --git a/include/asm-mips/mach-ev96100/mach-gt64120.h b/include/asm-mips/mach-ev96100/mach-gt64120.h
deleted file mode 100644
index 0ef1e6c25acf..000000000000
--- a/include/asm-mips/mach-ev96100/mach-gt64120.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H
9#define _ASM_GT64120_EV96100_GT64120_DEP_H
10
11/*
12 * GT96100 config space base address
13 */
14#define GT64120_BASE (KSEG1ADDR(0x14000000))
15
16/*
17 * PCI Bus allocation
18 *
19 * (Guessing ...)
20 */
21#define GT_PCI_MEM_BASE 0x12000000UL
22#define GT_PCI_MEM_SIZE 0x02000000UL
23#define GT_PCI_IO_BASE 0x10000000UL
24#define GT_PCI_IO_SIZE 0x02000000UL
25#define GT_ISA_IO_BASE PCI_IO_BASE
26
27/*
28 * Duart I/O ports.
29 */
30#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
31#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
32
33
34/*
35 * EV96100 interrupt controller register base.
36 */
37#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
38
39/*
40 * EV96100 UART register base.
41 */
42#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
43#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
44#define EV96100_BASE_BAUD ( 3686400 / 16 )
45
46#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
index 130bd4b8edce..4c29ba44992c 100644
--- a/include/asm-mips/mach-excite/excite.h
+++ b/include/asm-mips/mach-excite/excite.h
@@ -7,7 +7,7 @@
7 7
8#define EXCITE_CPU_EXT_CLOCK 100000000 8#define EXCITE_CPU_EXT_CLOCK 100000000
9 9
10#if !defined(__ASSEMBLER__) 10#if !defined(__ASSEMBLY__)
11void __init excite_kgdb_init(void); 11void __init excite_kgdb_init(void);
12void excite_procfs_init(void); 12void excite_procfs_init(void);
13extern unsigned long memsize; 13extern unsigned long memsize;
diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h
new file mode 100644
index 000000000000..38fcda703a0b
--- /dev/null
+++ b/include/asm-mips/mach-excite/excite_fpga.h
@@ -0,0 +1,80 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Adress alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
index f4e370e27168..529445dacedb 100644
--- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
@@ -20,7 +20,7 @@
20 20
21#define cpu_has_llsc 1 21#define cpu_has_llsc 1
22#define cpu_has_vtag_icache 0 22#define cpu_has_vtag_icache 0
23#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) 23#define cpu_has_dc_aliases 0
24#define cpu_has_ic_fills_f_dc 0 24#define cpu_has_ic_fills_f_dc 0
25 25
26#define cpu_has_dsp 0 26#define cpu_has_dsp 0
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index fd7ebc54fa90..b15e4ea0b091 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved.
3 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. 3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
4 * 5 *
5 * ######################################################################## 6 * ########################################################################
6 * 7 *
@@ -25,41 +26,88 @@
25#ifndef _MIPS_ATLASINT_H 26#ifndef _MIPS_ATLASINT_H
26#define _MIPS_ATLASINT_H 27#define _MIPS_ATLASINT_H
27 28
28#define ATLASINT_BASE 1 29/*
29#define ATLASINT_UART (ATLASINT_BASE+0) 30 * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
30#define ATLASINT_TIM0 (ATLASINT_BASE+1) 31 */
31#define ATLASINT_RES2 (ATLASINT_BASE+2) 32#define MIPSCPU_INT_BASE 0
32#define ATLASINT_RES3 (ATLASINT_BASE+3) 33
33#define ATLASINT_RTC (ATLASINT_BASE+4) 34/* CPU interrupt offsets */
34#define ATLASINT_COREHI (ATLASINT_BASE+5) 35#define MIPSCPU_INT_SW0 0
35#define ATLASINT_CORELO (ATLASINT_BASE+6) 36#define MIPSCPU_INT_SW1 1
36#define ATLASINT_RES7 (ATLASINT_BASE+7) 37#define MIPSCPU_INT_MB0 2
37#define ATLASINT_PCIA (ATLASINT_BASE+8) 38#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0
38#define ATLASINT_PCIB (ATLASINT_BASE+9) 39#define MIPSCPU_INT_MB1 3
39#define ATLASINT_PCIC (ATLASINT_BASE+10) 40#define MIPSCPU_INT_MB2 4
40#define ATLASINT_PCID (ATLASINT_BASE+11) 41#define MIPSCPU_INT_MB3 5
41#define ATLASINT_ENUM (ATLASINT_BASE+12) 42#define MIPSCPU_INT_MB4 6
42#define ATLASINT_DEG (ATLASINT_BASE+13) 43#define MIPSCPU_INT_CPUCTR 7
43#define ATLASINT_ATXFAIL (ATLASINT_BASE+14) 44
44#define ATLASINT_INTA (ATLASINT_BASE+15) 45/*
45#define ATLASINT_INTB (ATLASINT_BASE+16) 46 * Interrupts 8..39 are used for Atlas interrupt controller interrupts
46#define ATLASINT_ETH ATLASINT_INTB 47 */
47#define ATLASINT_INTC (ATLASINT_BASE+17) 48#define ATLAS_INT_BASE 8
48#define ATLASINT_SCSI ATLASINT_INTC 49#define ATLAS_INT_UART (ATLAS_INT_BASE + 0)
49#define ATLASINT_INTD (ATLASINT_BASE+18) 50#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1)
50#define ATLASINT_SERR (ATLASINT_BASE+19) 51#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2)
51#define ATLASINT_RES20 (ATLASINT_BASE+20) 52#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3)
52#define ATLASINT_RES21 (ATLASINT_BASE+21) 53#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4)
53#define ATLASINT_RES22 (ATLASINT_BASE+22) 54#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5)
54#define ATLASINT_RES23 (ATLASINT_BASE+23) 55#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6)
55#define ATLASINT_RES24 (ATLASINT_BASE+24) 56#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7)
56#define ATLASINT_RES25 (ATLASINT_BASE+25) 57#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8)
57#define ATLASINT_RES26 (ATLASINT_BASE+26) 58#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9)
58#define ATLASINT_RES27 (ATLASINT_BASE+27) 59#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10)
59#define ATLASINT_RES28 (ATLASINT_BASE+28) 60#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11)
60#define ATLASINT_RES29 (ATLASINT_BASE+29) 61#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12)
61#define ATLASINT_RES30 (ATLASINT_BASE+30) 62#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13)
62#define ATLASINT_RES31 (ATLASINT_BASE+31) 63#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14)
63#define ATLASINT_END (ATLASINT_BASE+31) 64#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15)
65#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16)
66#define ATLAS_INT_ETH ATLAS_INT_INTB
67#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17)
68#define ATLAS_INT_SCSI ATLAS_INT_INTC
69#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18)
70#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19)
71#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20)
72#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21)
73#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22)
74#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23)
75#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24)
76#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25)
77#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26)
78#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27)
79#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28)
80#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29)
81#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30)
82#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31)
83#define ATLAS_INT_END (ATLAS_INT_BASE + 31)
84
85/*
86 * Interrupts 64..127 are used for Soc-it Classic interrupts
87 */
88#define MSC01C_INT_BASE 64
89
90/* SOC-it Classic interrupt offsets */
91#define MSC01C_INT_TMR 0
92#define MSC01C_INT_PCI 1
93
94/*
95 * Interrupts 64..127 are used for Soc-it EIC interrupts
96 */
97#define MSC01E_INT_BASE 64
98
99/* SOC-it EIC interrupt offsets */
100#define MSC01E_INT_SW0 1
101#define MSC01E_INT_SW1 2
102#define MSC01E_INT_MB0 3
103#define MSC01E_INT_ATLAS MSC01E_INT_MB0
104#define MSC01E_INT_MB1 4
105#define MSC01E_INT_MB2 5
106#define MSC01E_INT_MB3 6
107#define MSC01E_INT_MB4 7
108#define MSC01E_INT_TMR 8
109#define MSC01E_INT_PCI 9
110#define MSC01E_INT_PERFCTR 10
111#define MSC01E_INT_CPUCTR 11
64 112
65#endif /* !(_MIPS_ATLASINT_H) */ 113#endif /* !(_MIPS_ATLASINT_H) */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 18b69de87daa..fe065d6070ca 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -262,10 +262,10 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
262 /* See comments for similar code above */ 262 /* See comments for similar code above */
263 prevvpe = dvpe(); 263 prevvpe = dvpe();
264 oldasid = (read_c0_entryhi() & ASID_MASK); 264 oldasid = (read_c0_entryhi() & ASID_MASK);
265 if(smtc_live_asid[mytlb][oldasid]) { 265 if (smtc_live_asid[mytlb][oldasid]) {
266 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 266 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
267 if(smtc_live_asid[mytlb][oldasid] == 0) 267 if(smtc_live_asid[mytlb][oldasid] == 0)
268 smtc_flush_tlb_asid(oldasid); 268 smtc_flush_tlb_asid(oldasid);
269 } 269 }
270 /* See comments for similar code above */ 270 /* See comments for similar code above */
271 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 271 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 219d359861f3..85b258ee7090 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,6 +34,8 @@
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37#include <asm/cpu-features.h>
38
37extern void clear_page(void * page); 39extern void clear_page(void * page);
38extern void copy_page(void * to, void * from); 40extern void copy_page(void * to, void * from);
39 41
@@ -53,7 +55,7 @@ static inline void clear_user_page(void *addr, unsigned long vaddr,
53 extern void (*flush_data_cache_page)(unsigned long addr); 55 extern void (*flush_data_cache_page)(unsigned long addr);
54 56
55 clear_page(addr); 57 clear_page(addr);
56 if (pages_do_alias((unsigned long) addr, vaddr)) 58 if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
57 flush_data_cache_page((unsigned long)addr); 59 flush_data_cache_page((unsigned long)addr);
58} 60}
59 61
@@ -63,7 +65,8 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
63 extern void (*flush_data_cache_page)(unsigned long addr); 65 extern void (*flush_data_cache_page)(unsigned long addr);
64 66
65 copy_page(vto, vfrom); 67 copy_page(vto, vfrom);
66 if (pages_do_alias((unsigned long)vto, vaddr)) 68 if (!cpu_has_ic_fills_f_dc ||
69 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
67 flush_data_cache_page((unsigned long)vto); 70 flush_data_cache_page((unsigned long)vto);
68} 71}
69 72
@@ -74,15 +77,17 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
74 #ifdef CONFIG_CPU_MIPS32 77 #ifdef CONFIG_CPU_MIPS32
75 typedef struct { unsigned long pte_low, pte_high; } pte_t; 78 typedef struct { unsigned long pte_low, pte_high; } pte_t;
76 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) 79 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
80 #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
77 #else 81 #else
78 typedef struct { unsigned long long pte; } pte_t; 82 typedef struct { unsigned long long pte; } pte_t;
79 #define pte_val(x) ((x).pte) 83 #define pte_val(x) ((x).pte)
84 #define __pte(x) ((pte_t) { (x) } )
80 #endif 85 #endif
81#else 86#else
82typedef struct { unsigned long pte; } pte_t; 87typedef struct { unsigned long pte; } pte_t;
83#define pte_val(x) ((x).pte) 88#define pte_val(x) ((x).pte)
84#endif
85#define __pte(x) ((pte_t) { (x) } ) 89#define __pte(x) ((pte_t) { (x) } )
90#endif
86 91
87/* 92/*
88 * For 3-level pagetables we defines these ourselves, for 2-level the 93 * For 3-level pagetables we defines these ourselves, for 2-level the
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4b26d8528133..d20f2e9b28be 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -156,9 +156,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
156#define __pte_offset(address) \ 156#define __pte_offset(address) \
157 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 157 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
158#define pte_offset(dir, address) \ 158#define pte_offset(dir, address) \
159 ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) 159 ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
160#define pte_offset_kernel(dir, address) \ 160#define pte_offset_kernel(dir, address) \
161 ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) 161 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
162 162
163#define pte_offset_map(dir, address) \ 163#define pte_offset_map(dir, address) \
164 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) 164 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index e3db93212eab..d05fb6f38aa7 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -93,8 +93,12 @@
93#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) 93#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
94#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 94#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
95 95
96#if PGDIR_SIZE >= TASK_SIZE
97#define USER_PTRS_PER_PGD (1)
98#else
96#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 99#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
97#define FIRST_USER_ADDRESS 0 100#endif
101#define FIRST_USER_ADDRESS 0UL
98 102
99#define VMALLOC_START MAP_BASE 103#define VMALLOC_START MAP_BASE
100#define VMALLOC_END \ 104#define VMALLOC_END \
@@ -178,24 +182,26 @@ static inline void pud_clear(pud_t *pudp)
178/* to find an entry in a page-table-directory */ 182/* to find an entry in a page-table-directory */
179#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 183#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
180 184
181static inline unsigned long pud_page(pud_t pud) 185static inline unsigned long pud_page_vaddr(pud_t pud)
182{ 186{
183 return pud_val(pud); 187 return pud_val(pud);
184} 188}
189#define pud_phys(pud) (pud_val(pud) - PAGE_OFFSET)
190#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
185 191
186/* Find an entry in the second-level page table.. */ 192/* Find an entry in the second-level page table.. */
187static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address) 193static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
188{ 194{
189 return (pmd_t *) pud_page(*pud) + pmd_index(address); 195 return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
190} 196}
191 197
192/* Find an entry in the third-level page table.. */ 198/* Find an entry in the third-level page table.. */
193#define __pte_offset(address) \ 199#define __pte_offset(address) \
194 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 200 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
195#define pte_offset(dir, address) \ 201#define pte_offset(dir, address) \
196 ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) 202 ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
197#define pte_offset_kernel(dir, address) \ 203#define pte_offset_kernel(dir, address) \
198 ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) 204 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
199#define pte_offset_map(dir, address) \ 205#define pte_offset_map(dir, address) \
200 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) 206 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
201#define pte_offset_map_nested(dir, address) \ 207#define pte_offset_map_nested(dir, address) \
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index a36ca1be17f2..1ca4d1e185c7 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -87,7 +87,7 @@ extern void paging_init(void);
87 */ 87 */
88#define pmd_phys(pmd) (pmd_val(pmd) - PAGE_OFFSET) 88#define pmd_phys(pmd) (pmd_val(pmd) - PAGE_OFFSET)
89#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 89#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
90#define pmd_page_kernel(pmd) pmd_val(pmd) 90#define pmd_page_vaddr(pmd) pmd_val(pmd)
91 91
92#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 92#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
93 93
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 4113316ee0da..4fb0fc43ffd7 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -10,8 +10,6 @@
10#define _ASM_PTRACE_H 10#define _ASM_PTRACE_H
11 11
12 12
13#include <asm/isadep.h>
14
15/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ 13/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
16#define FPR_BASE 32 14#define FPR_BASE 32
17#define PC 64 15#define PC 64
@@ -73,6 +71,7 @@ struct pt_regs {
73#ifdef __KERNEL__ 71#ifdef __KERNEL__
74 72
75#include <linux/linkage.h> 73#include <linux/linkage.h>
74#include <asm/isadep.h>
76 75
77/* 76/*
78 * Does the process account for user or for system time? 77 * Does the process account for user or for system time?
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 584bd9c0ab2e..035637c67e7c 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -52,9 +52,9 @@
52#endif 52#endif
53 53
54/* 54/*
55 * Both Galileo boards have the same UART mappings. 55 * Galileo EV64120 evaluation board
56 */ 56 */
57#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120) 57#ifdef CONFIG_MIPS_EV64120
58#include <asm/galileo-boards/ev96100.h> 58#include <asm/galileo-boards/ev96100.h>
59#include <asm/galileo-boards/ev96100int.h> 59#include <asm/galileo-boards/ev96100int.h>
60#define EV96100_SERIAL_PORT_DEFNS \ 60#define EV96100_SERIAL_PORT_DEFNS \
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 335dbaf1d831..a885491217c1 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -212,7 +212,7 @@
212 * Note: you'll need to define uint32_t and uint64_t in your headers. 212 * Note: you'll need to define uint32_t and uint64_t in your headers.
213 */ 213 */
214 214
215#if !defined(__ASSEMBLER__) 215#if !defined(__ASSEMBLY__)
216#define _SB_MAKE64(x) ((uint64_t)(x)) 216#define _SB_MAKE64(x) ((uint64_t)(x))
217#define _SB_MAKE32(x) ((uint32_t)(x)) 217#define _SB_MAKE32(x) ((uint32_t)(x))
218#else 218#else
@@ -251,9 +251,9 @@
251 */ 251 */
252 252
253 253
254#if defined(__mips64) && !defined(__ASSEMBLER__) 254#if defined(__mips64) && !defined(__ASSEMBLY__)
255#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) 255#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) 256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
257#endif /* __ASSEMBLER__ */ 257#endif /* __ASSEMBLY__ */
258 258
259#endif 259#endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index f4178bdcfcb0..7ed0bb611e56 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -149,7 +149,7 @@
149 * (For the assembler version, sysrev and dest may be the same register. 149 * (For the assembler version, sysrev and dest may be the same register.
150 * Also, it clobbers AT.) 150 * Also, it clobbers AT.)
151 */ 151 */
152#ifdef __ASSEMBLER__ 152#ifdef __ASSEMBLY__
153#define SYS_SOC_TYPE(dest, sysrev) \ 153#define SYS_SOC_TYPE(dest, sysrev) \
154 .set push ; \ 154 .set push ; \
155 .set reorder ; \ 155 .set reorder ; \
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 87a1dff95199..8b391a2f0814 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -108,17 +108,8 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
108#define SIG_BLOCK 1 /* for blocking signals */ 108#define SIG_BLOCK 1 /* for blocking signals */
109#define SIG_UNBLOCK 2 /* for unblocking signals */ 109#define SIG_UNBLOCK 2 /* for unblocking signals */
110#define SIG_SETMASK 3 /* for setting the signal mask */ 110#define SIG_SETMASK 3 /* for setting the signal mask */
111#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility:
112 set only the low 32 bit of the sigset. */
113 111
114/* Type of a signal handler. */ 112#include <asm-generic/signal.h>
115typedef void __signalfn_t(int);
116typedef __signalfn_t __user *__sighandler_t;
117
118/* Fake signal functions */
119#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
120#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
121#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
122 113
123struct sigaction { 114struct sigaction {
124 unsigned int sa_flags; 115 unsigned int sa_flags;
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 669b8e349ff2..4c1a1b53aeaf 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -239,7 +239,51 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
239 : "memory"); 239 : "memory");
240} 240}
241 241
242#define __raw_read_trylock(lock) generic__raw_read_trylock(lock) 242static inline int __raw_read_trylock(raw_rwlock_t *rw)
243{
244 unsigned int tmp;
245 int ret;
246
247 if (R10000_LLSC_WAR) {
248 __asm__ __volatile__(
249 " .set noreorder # __raw_read_trylock \n"
250 " li %2, 0 \n"
251 "1: ll %1, %3 \n"
252 " bnez %1, 2f \n"
253 " addu %1, 1 \n"
254 " sc %1, %0 \n"
255 " beqzl %1, 1b \n"
256 " .set reorder \n"
257#ifdef CONFIG_SMP
258 " sync \n"
259#endif
260 " li %2, 1 \n"
261 "2: \n"
262 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
263 : "m" (rw->lock)
264 : "memory");
265 } else {
266 __asm__ __volatile__(
267 " .set noreorder # __raw_read_trylock \n"
268 " li %2, 0 \n"
269 "1: ll %1, %3 \n"
270 " bnez %1, 2f \n"
271 " addu %1, 1 \n"
272 " sc %1, %0 \n"
273 " beqz %1, 1b \n"
274 " .set reorder \n"
275#ifdef CONFIG_SMP
276 " sync \n"
277#endif
278 " li %2, 1 \n"
279 "2: \n"
280 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
281 : "m" (rw->lock)
282 : "memory");
283 }
284
285 return ret;
286}
243 287
244static inline int __raw_write_trylock(raw_rwlock_t *rw) 288static inline int __raw_write_trylock(raw_rwlock_t *rw)
245{ 289{
@@ -283,4 +327,5 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
283 return ret; 327 return ret;
284} 328}
285 329
330
286#endif /* _ASM_SPINLOCK_H */ 331#endif /* _ASM_SPINLOCK_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index 98aa737b34aa..b80de8e0fbbd 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -8,6 +8,8 @@
8#ifndef _ASM_TIMEX_H 8#ifndef _ASM_TIMEX_H
9#define _ASM_TIMEX_H 9#define _ASM_TIMEX_H
10 10
11#ifdef __KERNEL__
12
11#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
12 14
13/* 15/*
@@ -51,4 +53,6 @@ static inline cycles_t get_cycles (void)
51 return read_c0_count(); 53 return read_c0_count();
52} 54}
53 55
56#endif /* __KERNEL__ */
57
54#endif /* _ASM_TIMEX_H */ 58#endif /* _ASM_TIMEX_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 610ccb8a50b3..c39142920fe6 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -313,7 +313,7 @@
313#define __NR_mknodat (__NR_Linux + 290) 313#define __NR_mknodat (__NR_Linux + 290)
314#define __NR_fchownat (__NR_Linux + 291) 314#define __NR_fchownat (__NR_Linux + 291)
315#define __NR_futimesat (__NR_Linux + 292) 315#define __NR_futimesat (__NR_Linux + 292)
316#define __NR_fstatat (__NR_Linux + 293) 316#define __NR_fstatat64 (__NR_Linux + 293)
317#define __NR_unlinkat (__NR_Linux + 294) 317#define __NR_unlinkat (__NR_Linux + 294)
318#define __NR_renameat (__NR_Linux + 295) 318#define __NR_renameat (__NR_Linux + 295)
319#define __NR_linkat (__NR_Linux + 296) 319#define __NR_linkat (__NR_Linux + 296)
@@ -329,16 +329,18 @@
329#define __NR_tee (__NR_Linux + 306) 329#define __NR_tee (__NR_Linux + 306)
330#define __NR_vmsplice (__NR_Linux + 307) 330#define __NR_vmsplice (__NR_Linux + 307)
331#define __NR_move_pages (__NR_Linux + 308) 331#define __NR_move_pages (__NR_Linux + 308)
332#define __NR_set_robust_list (__NR_Linux + 309)
333#define __NR_get_robust_list (__NR_Linux + 310)
332 334
333/* 335/*
334 * Offset of the last Linux o32 flavoured syscall 336 * Offset of the last Linux o32 flavoured syscall
335 */ 337 */
336#define __NR_Linux_syscalls 308 338#define __NR_Linux_syscalls 310
337 339
338#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 340#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
339 341
340#define __NR_O32_Linux 4000 342#define __NR_O32_Linux 4000
341#define __NR_O32_Linux_syscalls 308 343#define __NR_O32_Linux_syscalls 310
342 344
343#if _MIPS_SIM == _MIPS_SIM_ABI64 345#if _MIPS_SIM == _MIPS_SIM_ABI64
344 346
@@ -598,7 +600,7 @@
598#define __NR_mknodat (__NR_Linux + 249) 600#define __NR_mknodat (__NR_Linux + 249)
599#define __NR_fchownat (__NR_Linux + 250) 601#define __NR_fchownat (__NR_Linux + 250)
600#define __NR_futimesat (__NR_Linux + 251) 602#define __NR_futimesat (__NR_Linux + 251)
601#define __NR_fstatat (__NR_Linux + 252) 603#define __NR_newfstatat (__NR_Linux + 252)
602#define __NR_unlinkat (__NR_Linux + 253) 604#define __NR_unlinkat (__NR_Linux + 253)
603#define __NR_renameat (__NR_Linux + 254) 605#define __NR_renameat (__NR_Linux + 254)
604#define __NR_linkat (__NR_Linux + 255) 606#define __NR_linkat (__NR_Linux + 255)
@@ -614,16 +616,18 @@
614#define __NR_tee (__NR_Linux + 265) 616#define __NR_tee (__NR_Linux + 265)
615#define __NR_vmsplice (__NR_Linux + 266) 617#define __NR_vmsplice (__NR_Linux + 266)
616#define __NR_move_pages (__NR_Linux + 267) 618#define __NR_move_pages (__NR_Linux + 267)
619#define __NR_set_robust_list (__NR_Linux + 268)
620#define __NR_get_robust_list (__NR_Linux + 269)
617 621
618/* 622/*
619 * Offset of the last Linux 64-bit flavoured syscall 623 * Offset of the last Linux 64-bit flavoured syscall
620 */ 624 */
621#define __NR_Linux_syscalls 267 625#define __NR_Linux_syscalls 269
622 626
623#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 627#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
624 628
625#define __NR_64_Linux 5000 629#define __NR_64_Linux 5000
626#define __NR_64_Linux_syscalls 267 630#define __NR_64_Linux_syscalls 269
627 631
628#if _MIPS_SIM == _MIPS_SIM_NABI32 632#if _MIPS_SIM == _MIPS_SIM_NABI32
629 633
@@ -887,7 +891,7 @@
887#define __NR_mknodat (__NR_Linux + 253) 891#define __NR_mknodat (__NR_Linux + 253)
888#define __NR_fchownat (__NR_Linux + 254) 892#define __NR_fchownat (__NR_Linux + 254)
889#define __NR_futimesat (__NR_Linux + 255) 893#define __NR_futimesat (__NR_Linux + 255)
890#define __NR_fstatat (__NR_Linux + 256) 894#define __NR_newfstatat (__NR_Linux + 256)
891#define __NR_unlinkat (__NR_Linux + 257) 895#define __NR_unlinkat (__NR_Linux + 257)
892#define __NR_renameat (__NR_Linux + 258) 896#define __NR_renameat (__NR_Linux + 258)
893#define __NR_linkat (__NR_Linux + 259) 897#define __NR_linkat (__NR_Linux + 259)
@@ -903,16 +907,18 @@
903#define __NR_tee (__NR_Linux + 269) 907#define __NR_tee (__NR_Linux + 269)
904#define __NR_vmsplice (__NR_Linux + 270) 908#define __NR_vmsplice (__NR_Linux + 270)
905#define __NR_move_pages (__NR_Linux + 271) 909#define __NR_move_pages (__NR_Linux + 271)
910#define __NR_set_robust_list (__NR_Linux + 272)
911#define __NR_get_robust_list (__NR_Linux + 273)
906 912
907/* 913/*
908 * Offset of the last N32 flavoured syscall 914 * Offset of the last N32 flavoured syscall
909 */ 915 */
910#define __NR_Linux_syscalls 271 916#define __NR_Linux_syscalls 273
911 917
912#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 918#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
913 919
914#define __NR_N32_Linux 6000 920#define __NR_N32_Linux 6000
915#define __NR_N32_Linux_syscalls 271 921#define __NR_N32_Linux_syscalls 273
916 922
917#ifdef __KERNEL__ 923#ifdef __KERNEL__
918 924
diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h
index 89bf8b4cab3c..61f2a093b91b 100644
--- a/include/asm-mips/user.h
+++ b/include/asm-mips/user.h
@@ -8,6 +8,8 @@
8#ifndef _ASM_USER_H 8#ifndef _ASM_USER_H
9#define _ASM_USER_H 9#define _ASM_USER_H
10 10
11#ifdef __KERNEL__
12
11#include <asm/page.h> 13#include <asm/page.h>
12#include <asm/reg.h> 14#include <asm/reg.h>
13 15
@@ -55,4 +57,6 @@ struct user {
55#define HOST_DATA_START_ADDR (u.start_data) 57#define HOST_DATA_START_ADDR (u.start_data)
56#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) 58#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
57 59
60#endif /* __KERNEL__ */
61
58#endif /* _ASM_USER_H */ 62#endif /* _ASM_USER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 01:26:01 -0500