aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/gdb-stub.h215
-rw-r--r--include/asm-mips/kdebug.h14
-rw-r--r--include/asm-mips/kgdb.h44
-rw-r--r--include/asm-mips/pci.h2
-rw-r--r--include/asm-mips/txx9/generic.h14
-rw-r--r--include/asm-mips/txx9/jmr3927.h2
-rw-r--r--include/asm-mips/txx9/pci.h3
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h2
-rw-r--r--include/asm-mips/txx9/tx3927.h25
-rw-r--r--include/asm-mips/txx9/tx4927.h5
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h8
-rw-r--r--include/asm-mips/txx9/tx4938.h7
-rw-r--r--include/asm-mips/txx9/txx927.h121
-rw-r--r--include/asm-mips/txx9irq.h4
14 files changed, 115 insertions, 351 deletions
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
deleted file mode 100644
index 22f67d4a71ab..000000000000
--- a/include/asm-mips/gdb-stub.h
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 Andreas Busse
7 * Copyright (C) 2003 Ralf Baechle
8 */
9#ifndef _ASM_GDB_STUB_H
10#define _ASM_GDB_STUB_H
11
12
13/*
14 * important register numbers
15 */
16
17#define REG_EPC 37
18#define REG_FP 72
19#define REG_SP 29
20
21/*
22 * Stack layout for the GDB exception handler
23 * Derived from the stack layout described in asm-mips/stackframe.h
24 *
25 * The first PTRSIZE*6 bytes are argument save space for C subroutines.
26 */
27#define NUMREGS 90
28
29#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
30#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
31#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
32#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
33#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
34#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
35#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
36#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
37#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
38#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
39#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
40#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
41#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
42#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
43#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
44#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
45#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
46#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
47#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
48#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
49#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
50#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
51#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
52#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
53#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
54#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
55#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
56#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
57#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
58#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
59#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
60#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
61
62/*
63 * Saved special registers
64 */
65#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
66#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
67#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
68#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
69#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
70#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
71
72/*
73 * Saved floating point registers
74 */
75#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
76#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
77#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
78#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
79#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
80#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
81#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
82#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
83#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
84#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
85#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
86#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
87#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
88#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
89#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
90#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
91#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
92#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
93#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
94#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
95#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
96#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
97#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
98#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
99#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
100#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
101#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
102#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
103#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
104#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
105#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
106#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
107
108#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
109#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
110#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
111
112#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
113
114/*
115 * Again, CP0 registers
116 */
117#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
118#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
119#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
120#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
121#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
122#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
123#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
124#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
125#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
126#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
127#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
128#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
129#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
130#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
131#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
132#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
133
134#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
135
136#ifndef __ASSEMBLY__
137
138/*
139 * This is the same as above, but for the high-level
140 * part of the GDB stub.
141 */
142
143struct gdb_regs {
144 /*
145 * Pad bytes for argument save space on the stack
146 * 24/48 Bytes for 32/64 bit code
147 */
148 unsigned long pad0[6];
149
150 /*
151 * saved main processor registers
152 */
153 long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
154 long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15;
155 long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
156 long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
157
158 /*
159 * Saved special registers
160 */
161 long cp0_status;
162 long lo;
163 long hi;
164 long cp0_badvaddr;
165 long cp0_cause;
166 long cp0_epc;
167
168 /*
169 * Saved floating point registers
170 */
171 long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
172 long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
173 long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
174 long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
175
176 long cp1_fsr;
177 long cp1_fir;
178
179 /*
180 * Frame pointer
181 */
182 long frame_ptr;
183 long dummy; /* unused */
184
185 /*
186 * saved cp0 registers
187 */
188 long cp0_index;
189 long cp0_random;
190 long cp0_entrylo0;
191 long cp0_entrylo1;
192 long cp0_context;
193 long cp0_pagemask;
194 long cp0_wired;
195 long cp0_reg7;
196 long cp0_reg8;
197 long cp0_reg9;
198 long cp0_entryhi;
199 long cp0_reg11;
200 long cp0_reg12;
201 long cp0_reg13;
202 long cp0_reg14;
203 long cp0_prid;
204};
205
206/*
207 * Prototypes
208 */
209
210extern int kgdb_enabled;
211void set_debug_traps(void);
212void set_async_breakpoint(unsigned long *epc);
213
214#endif /* !__ASSEMBLY__ */
215#endif /* _ASM_GDB_STUB_H */
diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h
index 6ece1b037665..5bf62aafc890 100644
--- a/include/asm-mips/kdebug.h
+++ b/include/asm-mips/kdebug.h
@@ -1 +1,13 @@
1#include <asm-generic/kdebug.h> 1#ifndef _ASM_MIPS_KDEBUG_H
2#define _ASM_MIPS_KDEBUG_H
3
4#include <linux/notifier.h>
5
6enum die_val {
7 DIE_OOPS = 1,
8 DIE_FP,
9 DIE_TRAP,
10 DIE_RI,
11};
12
13#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/include/asm-mips/kgdb.h b/include/asm-mips/kgdb.h
new file mode 100644
index 000000000000..48223b09396c
--- /dev/null
+++ b/include/asm-mips/kgdb.h
@@ -0,0 +1,44 @@
1#ifndef __ASM_KGDB_H_
2#define __ASM_KGDB_H_
3
4#ifdef __KERNEL__
5
6#include <asm/sgidefs.h>
7
8#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
9 (_MIPS_ISA == _MIPS_ISA_MIPS32)
10
11#define KGDB_GDB_REG_SIZE 32
12
13#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
14 (_MIPS_ISA == _MIPS_ISA_MIPS64)
15
16#ifdef CONFIG_32BIT
17#define KGDB_GDB_REG_SIZE 32
18#else /* CONFIG_CPU_32BIT */
19#define KGDB_GDB_REG_SIZE 64
20#endif
21#else
22#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
23#endif /* _MIPS_ISA */
24
25#define BUFMAX 2048
26#if (KGDB_GDB_REG_SIZE == 32)
27#define NUMREGBYTES (90*sizeof(u32))
28#define NUMCRITREGBYTES (12*sizeof(u32))
29#else
30#define NUMREGBYTES (90*sizeof(u64))
31#define NUMCRITREGBYTES (12*sizeof(u64))
32#endif
33#define BREAK_INSTR_SIZE 4
34#define CACHE_FLUSH_IS_SAFE 0
35
36extern void arch_kgdb_breakpoint(void);
37extern int kgdb_early_setup;
38extern void *saved_vectors[32];
39extern void handle_exception(struct pt_regs *regs);
40extern void breakinst(void);
41
42#endif /* __KERNEL__ */
43
44#endif /* __ASM_KGDB_H_ */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c205875d7f31..5510c53b7feb 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -174,4 +174,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
174 174
175extern int pci_probe_only; 175extern int pci_probe_only;
176 176
177extern char * (*pcibios_plat_setup)(char *str);
178
177#endif /* _ASM_PCI_H */ 179#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index cbae37ec3d88..5b1ccf901c62 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -44,5 +44,19 @@ extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45void prom_init_cmdline(void); 45void prom_init_cmdline(void);
46char *prom_getcmdline(void); 46char *prom_getcmdline(void);
47void txx9_wdt_init(unsigned long base);
48void txx9_spi_init(int busid, unsigned long base, int irq);
49void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
50void txx9_sio_init(unsigned long baseaddr, int irq,
51 unsigned int line, unsigned int sclk, int nocts);
52void prom_putchar(char c);
53#ifdef CONFIG_EARLY_PRINTK
54extern void (*txx9_prom_putchar)(char c);
55void txx9_sio_putchar_init(unsigned long baseaddr);
56#else
57static inline void txx9_sio_putchar_init(unsigned long baseaddr)
58{
59}
60#endif
47 61
48#endif /* __ASM_TXX9_GENERIC_H */ 62#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index d6eb1b6a54eb..a409c446bf18 100644
--- a/include/asm-mips/txx9/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -149,8 +149,6 @@
149 149
150/* Clocks */ 150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
154 152
155/* 153/*
156 * TX3927 Pin Configuration: 154 * TX3927 Pin Configuration:
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
index d89a45091e24..3d32529060aa 100644
--- a/include/asm-mips/txx9/pci.h
+++ b/include/asm-mips/txx9/pci.h
@@ -33,4 +33,7 @@ enum txx9_pci_err_action {
33}; 33};
34extern enum txx9_pci_err_action txx9_pci_err_action; 34extern enum txx9_pci_err_action txx9_pci_err_action;
35 35
36extern char * (*txx9_board_pcibios_setup)(char *str);
37char *txx9_pcibios_setup(char *str);
38
36#endif /* __ASM_TXX9_PCI_H */ 39#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 9375e4fc2289..02e161d0755d 100644
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -56,7 +56,7 @@
56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa 56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
57#define SMSC_FDC37M81X_CHIP_ID 0x4d 57#define SMSC_FDC37M81X_CHIP_ID 0x4d
58 58
59unsigned long __init smsc_fdc37m81x_init(unsigned long port); 59unsigned long smsc_fdc37m81x_init(unsigned long port);
60 60
61void smsc_fdc37m81x_config_beg(void); 61void smsc_fdc37m81x_config_beg(void);
62 62
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index ea79e1b16e71..587deb9592d2 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -8,9 +8,8 @@
8#ifndef __ASM_TXX9_TX3927_H 8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H 9#define __ASM_TXX9_TX3927_H
10 10
11#include <asm/txx9/txx927.h>
12
13#define TX3927_REG_BASE 0xfffe0000UL 11#define TX3927_REG_BASE 0xfffe0000UL
12#define TX3927_REG_SIZE 0x00010000
14#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) 13#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) 14#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) 15#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
@@ -236,11 +235,17 @@ struct tx3927_ccfg_reg {
236/* see PCI_STATUS_XXX in linux/pci.h */ 235/* see PCI_STATUS_XXX in linux/pci.h */
237#define PCI_STATUS_NEW_CAP 0x0010 236#define PCI_STATUS_NEW_CAP 0x0010
238 237
238/* bits for ISTAT/IIM */
239#define TX3927_PCIC_IIM_ALL 0x00001600
240
239/* bits for TC */ 241/* bits for TC */
240#define TX3927_PCIC_TC_OF16E 0x00000020 242#define TX3927_PCIC_TC_OF16E 0x00000020
241#define TX3927_PCIC_TC_IF8E 0x00000010 243#define TX3927_PCIC_TC_IF8E 0x00000010
242#define TX3927_PCIC_TC_OF8E 0x00000008 244#define TX3927_PCIC_TC_OF8E 0x00000008
243 245
246/* bits for TSTAT/TIM */
247#define TX3927_PCIC_TIM_ALL 0x0003ffff
248
244/* bits for IOBA/MBA */ 249/* bits for IOBA/MBA */
245/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ 250/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
246 251
@@ -313,12 +318,22 @@ struct tx3927_ccfg_reg {
313#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 318#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
314#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 319#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
315#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 320#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
316#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
317#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 321#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
318#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) 322#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
319 323
324#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326#define TX3927_ROMC_SIZE(ch) \
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328
329void tx3927_wdt_init(void);
330void tx3927_setup(void);
331void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
332void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
320struct pci_controller; 333struct pci_controller;
321void __init tx3927_pcic_setup(struct pci_controller *channel, 334void tx3927_pcic_setup(struct pci_controller *channel,
322 unsigned long sdram_size, int extarb); 335 unsigned long sdram_size, int extarb);
336void tx3927_setup_pcierr_irq(void);
337void tx3927_irq_init(void);
323 338
324#endif /* __ASM_TXX9_TX3927_H */ 339#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index ceb4b79ff4e3..195f6515db9a 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -243,12 +243,13 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
243} 243}
244 244
245unsigned int tx4927_get_mem_size(void); 245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void); 246void tx4927_wdt_init(void);
247void tx4927_setup(void); 247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr); 248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void); 249void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
250int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
251int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
252void tx4927_setup_pcierr_irq(void);
252void tx4927_irq_init(void); 253void tx4927_irq_init(void);
253 254
254#endif /* __ASM_TXX9_TX4927_H */ 255#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
index d61c3d09c4a2..c470b8a5fe57 100644
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -10,6 +10,7 @@
10#define __ASM_TXX9_TX4927PCIC_H 10#define __ASM_TXX9_TX4927PCIC_H
11 11
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/irqreturn.h>
13 14
14struct tx4927_pcic_reg { 15struct tx4927_pcic_reg {
15 u32 pciid; 16 u32 pciid;
@@ -192,8 +193,11 @@ struct tx4927_pcic_reg {
192 193
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 194struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel); 195 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 196void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb); 197 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void); 198void tx4927_report_pcic_status(void);
199char *tx4927_pcibios_setup(char *str);
200void tx4927_dump_pcic_settings(void);
201irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
198 202
199#endif /* __ASM_TXX9_TX4927PCIC_H */ 203#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 1ed969d381d6..8175d4ccbc39 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -276,15 +276,18 @@ struct tx4938_ccfg_reg {
276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
277 277
278#define tx4938_get_mem_size() tx4927_get_mem_size() 278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void); 279void tx4938_wdt_init(void);
280void tx4938_setup(void); 280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr); 281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void); 282void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
283void tx4938_spi_init(int busid);
284void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
283int tx4938_report_pciclk(void); 285int tx4938_report_pciclk(void);
284void tx4938_report_pci1clk(void); 286void tx4938_report_pci1clk(void);
285int tx4938_pciclk66_setup(void); 287int tx4938_pciclk66_setup(void);
286struct pci_dev; 288struct pci_dev;
287int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); 289int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
290void tx4938_setup_pcierr_irq(void);
288void tx4938_irq_init(void); 291void tx4938_irq_init(void);
289 292
290#endif 293#endif
diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h
deleted file mode 100644
index 97dd7ad1a890..000000000000
--- a/include/asm-mips/txx9/txx927.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_TXX927_H
11#define __ASM_TXX9_TXX927_H
12
13struct txx927_sio_reg {
14 volatile unsigned long lcr;
15 volatile unsigned long dicr;
16 volatile unsigned long disr;
17 volatile unsigned long cisr;
18 volatile unsigned long fcr;
19 volatile unsigned long flcr;
20 volatile unsigned long bgr;
21 volatile unsigned long tfifo;
22 volatile unsigned long rfifo;
23};
24
25/*
26 * SIO
27 */
28/* SILCR : Line Control */
29#define TXx927_SILCR_SCS_MASK 0x00000060
30#define TXx927_SILCR_SCS_IMCLK 0x00000000
31#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
32#define TXx927_SILCR_SCS_SCLK 0x00000040
33#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
34#define TXx927_SILCR_UEPS 0x00000010
35#define TXx927_SILCR_UPEN 0x00000008
36#define TXx927_SILCR_USBL_MASK 0x00000004
37#define TXx927_SILCR_USBL_1BIT 0x00000004
38#define TXx927_SILCR_USBL_2BIT 0x00000000
39#define TXx927_SILCR_UMODE_MASK 0x00000003
40#define TXx927_SILCR_UMODE_8BIT 0x00000000
41#define TXx927_SILCR_UMODE_7BIT 0x00000001
42
43/* SIDICR : DMA/Int. Control */
44#define TXx927_SIDICR_TDE 0x00008000
45#define TXx927_SIDICR_RDE 0x00004000
46#define TXx927_SIDICR_TIE 0x00002000
47#define TXx927_SIDICR_RIE 0x00001000
48#define TXx927_SIDICR_SPIE 0x00000800
49#define TXx927_SIDICR_CTSAC 0x00000600
50#define TXx927_SIDICR_STIE_MASK 0x0000003f
51#define TXx927_SIDICR_STIE_OERS 0x00000020
52#define TXx927_SIDICR_STIE_CTSS 0x00000010
53#define TXx927_SIDICR_STIE_RBRKD 0x00000008
54#define TXx927_SIDICR_STIE_TRDY 0x00000004
55#define TXx927_SIDICR_STIE_TXALS 0x00000002
56#define TXx927_SIDICR_STIE_UBRKD 0x00000001
57
58/* SIDISR : DMA/Int. Status */
59#define TXx927_SIDISR_UBRK 0x00008000
60#define TXx927_SIDISR_UVALID 0x00004000
61#define TXx927_SIDISR_UFER 0x00002000
62#define TXx927_SIDISR_UPER 0x00001000
63#define TXx927_SIDISR_UOER 0x00000800
64#define TXx927_SIDISR_ERI 0x00000400
65#define TXx927_SIDISR_TOUT 0x00000200
66#define TXx927_SIDISR_TDIS 0x00000100
67#define TXx927_SIDISR_RDIS 0x00000080
68#define TXx927_SIDISR_STIS 0x00000040
69#define TXx927_SIDISR_RFDN_MASK 0x0000001f
70
71/* SICISR : Change Int. Status */
72#define TXx927_SICISR_OERS 0x00000020
73#define TXx927_SICISR_CTSS 0x00000010
74#define TXx927_SICISR_RBRKD 0x00000008
75#define TXx927_SICISR_TRDY 0x00000004
76#define TXx927_SICISR_TXALS 0x00000002
77#define TXx927_SICISR_UBRKD 0x00000001
78
79/* SIFCR : FIFO Control */
80#define TXx927_SIFCR_SWRST 0x00008000
81#define TXx927_SIFCR_RDIL_MASK 0x00000180
82#define TXx927_SIFCR_RDIL_1 0x00000000
83#define TXx927_SIFCR_RDIL_4 0x00000080
84#define TXx927_SIFCR_RDIL_8 0x00000100
85#define TXx927_SIFCR_RDIL_12 0x00000180
86#define TXx927_SIFCR_RDIL_MAX 0x00000180
87#define TXx927_SIFCR_TDIL_MASK 0x00000018
88#define TXx927_SIFCR_TDIL_MASK 0x00000018
89#define TXx927_SIFCR_TDIL_1 0x00000000
90#define TXx927_SIFCR_TDIL_4 0x00000001
91#define TXx927_SIFCR_TDIL_8 0x00000010
92#define TXx927_SIFCR_TDIL_MAX 0x00000010
93#define TXx927_SIFCR_TFRST 0x00000004
94#define TXx927_SIFCR_RFRST 0x00000002
95#define TXx927_SIFCR_FRSTE 0x00000001
96#define TXx927_SIO_TX_FIFO 8
97#define TXx927_SIO_RX_FIFO 16
98
99/* SIFLCR : Flow Control */
100#define TXx927_SIFLCR_RCS 0x00001000
101#define TXx927_SIFLCR_TES 0x00000800
102#define TXx927_SIFLCR_RTSSC 0x00000200
103#define TXx927_SIFLCR_RSDE 0x00000100
104#define TXx927_SIFLCR_TSDE 0x00000080
105#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
106#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
107#define TXx927_SIFLCR_TBRK 0x00000001
108
109/* SIBGR : Baudrate Control */
110#define TXx927_SIBGR_BCLK_MASK 0x00000300
111#define TXx927_SIBGR_BCLK_T0 0x00000000
112#define TXx927_SIBGR_BCLK_T2 0x00000100
113#define TXx927_SIBGR_BCLK_T4 0x00000200
114#define TXx927_SIBGR_BCLK_T6 0x00000300
115#define TXx927_SIBGR_BRD_MASK 0x000000ff
116
117/*
118 * PIO
119 */
120
121#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
index 1c439e51b875..5620879be37f 100644
--- a/include/asm-mips/txx9irq.h
+++ b/include/asm-mips/txx9irq.h
@@ -14,8 +14,12 @@
14#ifdef CONFIG_IRQ_CPU 14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else 16#else
17#ifdef CONFIG_I8259
18#define TXX9_IRQ_BASE (I8259A_IRQ_BASE + 16)
19#else
17#define TXX9_IRQ_BASE 0 20#define TXX9_IRQ_BASE 0
18#endif 21#endif
22#endif
19 23
20#ifdef CONFIG_CPU_TX39XX 24#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16 25#define TXx9_MAX_IR 16
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 13:05:57 -0500