aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/asmmacro.h12
-rw-r--r--include/asm-mips/bitops.h12
-rw-r--r--include/asm-mips/byteorder.h4
-rw-r--r--include/asm-mips/elf.h2
-rw-r--r--include/asm-mips/fixmap.h4
-rw-r--r--include/asm-mips/futex.h2
-rw-r--r--include/asm-mips/inventory.h4
-rw-r--r--include/asm-mips/irqflags.h10
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h622
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h2
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h2
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h56
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h60
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h24
-rw-r--r--include/asm-mips/parport.h6
-rw-r--r--include/asm-mips/prctl.h2
-rw-r--r--include/asm-mips/semaphore.h6
-rw-r--r--include/asm-mips/sim.h4
-rw-r--r--include/asm-mips/sn/addrs.h44
-rw-r--r--include/asm-mips/sn/io.h2
-rw-r--r--include/asm-mips/sn/kldir.h2
-rw-r--r--include/asm-mips/sn/sn0/addrs.h8
-rw-r--r--include/asm-mips/sni.h18
-rw-r--r--include/asm-mips/system.h6
-rw-r--r--include/asm-mips/timex.h2
-rw-r--r--include/asm-mips/uaccess.h18
26 files changed, 467 insertions, 467 deletions
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index c5f20df780e9..7a881755800f 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -56,27 +56,27 @@
56 * Temporary until all gas have MT ASE support 56 * Temporary until all gas have MT ASE support
57 */ 57 */
58 .macro DMT reg=0 58 .macro DMT reg=0
59 .word (0x41600bc1 | (\reg << 16)) 59 .word 0x41600bc1 | (\reg << 16)
60 .endm 60 .endm
61 61
62 .macro EMT reg=0 62 .macro EMT reg=0
63 .word (0x41600be1 | (\reg << 16)) 63 .word 0x41600be1 | (\reg << 16)
64 .endm 64 .endm
65 65
66 .macro DVPE reg=0 66 .macro DVPE reg=0
67 .word (0x41600001 | (\reg << 16)) 67 .word 0x41600001 | (\reg << 16)
68 .endm 68 .endm
69 69
70 .macro EVPE reg=0 70 .macro EVPE reg=0
71 .word (0x41600021 | (\reg << 16)) 71 .word 0x41600021 | (\reg << 16)
72 .endm 72 .endm
73 73
74 .macro MFTR rt=0, rd=0, u=0, sel=0 74 .macro MFTR rt=0, rd=0, u=0, sel=0
75 .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 75 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
76 .endm 76 .endm
77 77
78 .macro MTTR rt=0, rd=0, u=0, sel=0 78 .macro MTTR rt=0, rd=0, u=0, sel=0
79 .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 79 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
80 .endm 80 .endm
81 81
82#endif /* _ASM_ASMMACRO_H */ 82#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 148bc79557f1..899357a72ac4 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -19,14 +19,14 @@
19#include <asm/sgidefs.h> 19#include <asm/sgidefs.h>
20#include <asm/war.h> 20#include <asm/war.h>
21 21
22#if (_MIPS_SZLONG == 32) 22#if _MIPS_SZLONG == 32
23#define SZLONG_LOG 5 23#define SZLONG_LOG 5
24#define SZLONG_MASK 31UL 24#define SZLONG_MASK 31UL
25#define __LL "ll " 25#define __LL "ll "
26#define __SC "sc " 26#define __SC "sc "
27#define __INS "ins " 27#define __INS "ins "
28#define __EXT "ext " 28#define __EXT "ext "
29#elif (_MIPS_SZLONG == 64) 29#elif _MIPS_SZLONG == 64
30#define SZLONG_LOG 6 30#define SZLONG_LOG 6
31#define SZLONG_MASK 63UL 31#define SZLONG_MASK 63UL
32#define __LL "lld " 32#define __LL "lld "
@@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x)
461 int lz; 461 int lz;
462 462
463 if (sizeof(x) == 4) { 463 if (sizeof(x) == 4) {
464 __asm__ ( 464 __asm__(
465 " .set push \n" 465 " .set push \n"
466 " .set mips32 \n" 466 " .set mips32 \n"
467 " clz %0, %1 \n" 467 " clz %0, %1 \n"
@@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x)
474 474
475 BUG_ON(sizeof(x) != 8); 475 BUG_ON(sizeof(x) != 8);
476 476
477 __asm__ ( 477 __asm__(
478 " .set push \n" 478 " .set push \n"
479 " .set mips64 \n" 479 " .set mips64 \n"
480 " dclz %0, %1 \n" 480 " dclz %0, %1 \n"
@@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word)
508 */ 508 */
509static inline int fls(int word) 509static inline int fls(int word)
510{ 510{
511 __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); 511 __asm__("clz %0, %1" : "=r" (word) : "r" (word));
512 512
513 return 32 - word; 513 return 32 - word;
514} 514}
@@ -516,7 +516,7 @@ static inline int fls(int word)
516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
517static inline int fls64(__u64 word) 517static inline int fls64(__u64 word)
518{ 518{
519 __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); 519 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
520 520
521 return 64 - word; 521 return 64 - word;
522} 522}
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index eee83cbdf2b0..fe7dc2d59b69 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
65 65
66#endif /* __GNUC__ */ 66#endif /* __GNUC__ */
67 67
68#if defined (__MIPSEB__) 68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h> 69# include <linux/byteorder/big_endian.h>
70#elif defined (__MIPSEL__) 70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h> 71# include <linux/byteorder/little_endian.h>
72#else 72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" 73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e7d95d48177d..766f91ad5cd3 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -319,7 +319,7 @@ do { \
319struct task_struct; 319struct task_struct;
320 320
321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); 321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
322extern int dump_task_regs (struct task_struct *, elf_gregset_t *); 322extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
324 324
325#define ELF_CORE_COPY_REGS(elf_regs, regs) \ 325#define ELF_CORE_COPY_REGS(elf_regs, regs) \
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 02c8a13fc894..f27b96cfac2e 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -60,8 +60,8 @@ enum fixed_addresses {
60 __end_of_fixed_addresses 60 __end_of_fixed_addresses
61}; 61};
62 62
63extern void __set_fixmap (enum fixed_addresses idx, 63extern void __set_fixmap(enum fixed_addresses idx,
64 unsigned long phys, pgprot_t flags); 64 unsigned long phys, pgprot_t flags);
65 65
66#define set_fixmap(idx, phys) \ 66#define set_fixmap(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL) 67 __set_fixmap(idx, phys, PAGE_KERNEL)
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index b623882bce19..3e7e30d4f418 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -75,7 +75,7 @@
75} 75}
76 76
77static inline int 77static inline int
78futex_atomic_op_inuser (int encoded_op, int __user *uaddr) 78futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
79{ 79{
80 int op = (encoded_op >> 28) & 7; 80 int op = (encoded_op >> 28) & 7;
81 int cmp = (encoded_op >> 24) & 15; 81 int cmp = (encoded_op >> 24) & 15;
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 92d90f75a636..cc88aed23f0f 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -17,8 +17,8 @@ typedef struct inventory_s {
17 17
18extern int inventory_items; 18extern int inventory_items;
19 19
20extern void add_to_inventory (int class, int type, int controller, int unit, int state); 20extern void add_to_inventory(int class, int type, int controller, int unit, int state);
21extern int dump_inventory_to_user (void __user *userbuf, int size); 21extern int dump_inventory_to_user(void __user *userbuf, int size);
22extern int __init init_inventory(void); 22extern int __init init_inventory(void);
23 23
24#endif /* __ASM_INVENTORY_H */ 24#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index e459fa05db83..881e8866501d 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -16,7 +16,7 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18 18
19__asm__ ( 19__asm__(
20 " .macro raw_local_irq_enable \n" 20 " .macro raw_local_irq_enable \n"
21 " .set push \n" 21 " .set push \n"
22 " .set reorder \n" 22 " .set reorder \n"
@@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void)
65 * 65 *
66 * Workaround: mask EXL bit of the result or place a nop before mfc0. 66 * Workaround: mask EXL bit of the result or place a nop before mfc0.
67 */ 67 */
68__asm__ ( 68__asm__(
69 " .macro raw_local_irq_disable\n" 69 " .macro raw_local_irq_disable\n"
70 " .set push \n" 70 " .set push \n"
71 " .set noat \n" 71 " .set noat \n"
@@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void)
96 : "memory"); 96 : "memory");
97} 97}
98 98
99__asm__ ( 99__asm__(
100 " .macro raw_local_save_flags flags \n" 100 " .macro raw_local_save_flags flags \n"
101 " .set push \n" 101 " .set push \n"
102 " .set reorder \n" 102 " .set reorder \n"
@@ -113,7 +113,7 @@ __asm__ __volatile__( \
113 "raw_local_save_flags %0" \ 113 "raw_local_save_flags %0" \
114 : "=r" (x)) 114 : "=r" (x))
115 115
116__asm__ ( 116__asm__(
117 " .macro raw_local_irq_save result \n" 117 " .macro raw_local_irq_save result \n"
118 " .set push \n" 118 " .set push \n"
119 " .set reorder \n" 119 " .set reorder \n"
@@ -145,7 +145,7 @@ __asm__ __volatile__( \
145 : /* no inputs */ \ 145 : /* no inputs */ \
146 : "memory") 146 : "memory")
147 147
148__asm__ ( 148__asm__(
149 " .macro raw_local_irq_restore flags \n" 149 " .macro raw_local_irq_restore flags \n"
150 " .set push \n" 150 " .set push \n"
151 " .set noreorder \n" 151 " .set noreorder \n"
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 58fca8a5a9a6..10f613f23c33 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
951/* Programmable Counters 0 and 1 */ 951/* Programmable Counters 0 and 1 */
952#define SYS_BASE 0xB1900000 952#define SYS_BASE 0xB1900000
953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954 #define SYS_CNTRL_E1S (1<<23) 954# define SYS_CNTRL_E1S (1<<23)
955 #define SYS_CNTRL_T1S (1<<20) 955# define SYS_CNTRL_T1S (1<<20)
956 #define SYS_CNTRL_M21 (1<<19) 956# define SYS_CNTRL_M21 (1<<19)
957 #define SYS_CNTRL_M11 (1<<18) 957# define SYS_CNTRL_M11 (1<<18)
958 #define SYS_CNTRL_M01 (1<<17) 958# define SYS_CNTRL_M01 (1<<17)
959 #define SYS_CNTRL_C1S (1<<16) 959# define SYS_CNTRL_C1S (1<<16)
960 #define SYS_CNTRL_BP (1<<14) 960# define SYS_CNTRL_BP (1<<14)
961 #define SYS_CNTRL_EN1 (1<<13) 961# define SYS_CNTRL_EN1 (1<<13)
962 #define SYS_CNTRL_BT1 (1<<12) 962# define SYS_CNTRL_BT1 (1<<12)
963 #define SYS_CNTRL_EN0 (1<<11) 963# define SYS_CNTRL_EN0 (1<<11)
964 #define SYS_CNTRL_BT0 (1<<10) 964# define SYS_CNTRL_BT0 (1<<10)
965 #define SYS_CNTRL_E0 (1<<8) 965# define SYS_CNTRL_E0 (1<<8)
966 #define SYS_CNTRL_E0S (1<<7) 966# define SYS_CNTRL_E0S (1<<7)
967 #define SYS_CNTRL_32S (1<<5) 967# define SYS_CNTRL_32S (1<<5)
968 #define SYS_CNTRL_T0S (1<<4) 968# define SYS_CNTRL_T0S (1<<4)
969 #define SYS_CNTRL_M20 (1<<3) 969# define SYS_CNTRL_M20 (1<<3)
970 #define SYS_CNTRL_M10 (1<<2) 970# define SYS_CNTRL_M10 (1<<2)
971 #define SYS_CNTRL_M00 (1<<1) 971# define SYS_CNTRL_M00 (1<<1)
972 #define SYS_CNTRL_C0S (1<<0) 972# define SYS_CNTRL_C0S (1<<0)
973 973
974/* Programmable Counter 0 Registers */ 974/* Programmable Counter 0 Registers */
975#define SYS_TOYTRIM (SYS_BASE + 0) 975#define SYS_TOYTRIM (SYS_BASE + 0)
@@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
989 989
990/* I2S Controller */ 990/* I2S Controller */
991#define I2S_DATA 0xB1000000 991#define I2S_DATA 0xB1000000
992 #define I2S_DATA_MASK (0xffffff) 992# define I2S_DATA_MASK (0xffffff)
993#define I2S_CONFIG 0xB1000004 993#define I2S_CONFIG 0xB1000004
994 #define I2S_CONFIG_XU (1<<25) 994# define I2S_CONFIG_XU (1<<25)
995 #define I2S_CONFIG_XO (1<<24) 995# define I2S_CONFIG_XO (1<<24)
996 #define I2S_CONFIG_RU (1<<23) 996# define I2S_CONFIG_RU (1<<23)
997 #define I2S_CONFIG_RO (1<<22) 997# define I2S_CONFIG_RO (1<<22)
998 #define I2S_CONFIG_TR (1<<21) 998# define I2S_CONFIG_TR (1<<21)
999 #define I2S_CONFIG_TE (1<<20) 999# define I2S_CONFIG_TE (1<<20)
1000 #define I2S_CONFIG_TF (1<<19) 1000# define I2S_CONFIG_TF (1<<19)
1001 #define I2S_CONFIG_RR (1<<18) 1001# define I2S_CONFIG_RR (1<<18)
1002 #define I2S_CONFIG_RE (1<<17) 1002# define I2S_CONFIG_RE (1<<17)
1003 #define I2S_CONFIG_RF (1<<16) 1003# define I2S_CONFIG_RF (1<<16)
1004 #define I2S_CONFIG_PD (1<<11) 1004# define I2S_CONFIG_PD (1<<11)
1005 #define I2S_CONFIG_LB (1<<10) 1005# define I2S_CONFIG_LB (1<<10)
1006 #define I2S_CONFIG_IC (1<<9) 1006# define I2S_CONFIG_IC (1<<9)
1007 #define I2S_CONFIG_FM_BIT 7 1007# define I2S_CONFIG_FM_BIT 7
1008 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012 #define I2S_CONFIG_TN (1<<6) 1012# define I2S_CONFIG_TN (1<<6)
1013 #define I2S_CONFIG_RN (1<<5) 1013# define I2S_CONFIG_RN (1<<5)
1014 #define I2S_CONFIG_SZ_BIT 0 1014# define I2S_CONFIG_SZ_BIT 0
1015 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1016 1016
1017#define I2S_CONTROL 0xB1000008 1017#define I2S_CONTROL 0xB1000008
1018 #define I2S_CONTROL_D (1<<1) 1018# define I2S_CONTROL_D (1<<1)
1019 #define I2S_CONTROL_CE (1<<0) 1019# define I2S_CONTROL_CE (1<<0)
1020 1020
1021/* USB Host Controller */ 1021/* USB Host Controller */
1022#ifndef USB_OHCI_LEN 1022#ifndef USB_OHCI_LEN
@@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1034#define USBD_EP5RD 0xB0200014 1034#define USBD_EP5RD 0xB0200014
1035#define USBD_INTEN 0xB0200018 1035#define USBD_INTEN 0xB0200018
1036#define USBD_INTSTAT 0xB020001C 1036#define USBD_INTSTAT 0xB020001C
1037 #define USBDEV_INT_SOF (1<<12) 1037# define USBDEV_INT_SOF (1<<12)
1038 #define USBDEV_INT_HF_BIT 6 1038# define USBDEV_INT_HF_BIT 6
1039 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1039# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1040 #define USBDEV_INT_CMPLT_BIT 0 1040# define USBDEV_INT_CMPLT_BIT 0
1041 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042#define USBD_CONFIG 0xB0200020 1042#define USBD_CONFIG 0xB0200020
1043#define USBD_EP0CS 0xB0200024 1043#define USBD_EP0CS 0xB0200024
1044#define USBD_EP2CS 0xB0200028 1044#define USBD_EP2CS 0xB0200028
1045#define USBD_EP3CS 0xB020002C 1045#define USBD_EP3CS 0xB020002C
1046#define USBD_EP4CS 0xB0200030 1046#define USBD_EP4CS 0xB0200030
1047#define USBD_EP5CS 0xB0200034 1047#define USBD_EP5CS 0xB0200034
1048 #define USBDEV_CS_SU (1<<14) 1048# define USBDEV_CS_SU (1<<14)
1049 #define USBDEV_CS_NAK (1<<13) 1049# define USBDEV_CS_NAK (1<<13)
1050 #define USBDEV_CS_ACK (1<<12) 1050# define USBDEV_CS_ACK (1<<12)
1051 #define USBDEV_CS_BUSY (1<<11) 1051# define USBDEV_CS_BUSY (1<<11)
1052 #define USBDEV_CS_TSIZE_BIT 1 1052# define USBDEV_CS_TSIZE_BIT 1
1053 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054 #define USBDEV_CS_STALL (1<<0) 1054# define USBDEV_CS_STALL (1<<0)
1055#define USBD_EP0RDSTAT 0xB0200040 1055#define USBD_EP0RDSTAT 0xB0200040
1056#define USBD_EP0WRSTAT 0xB0200044 1056#define USBD_EP0WRSTAT 0xB0200044
1057#define USBD_EP2WRSTAT 0xB0200048 1057#define USBD_EP2WRSTAT 0xB0200048
1058#define USBD_EP3WRSTAT 0xB020004C 1058#define USBD_EP3WRSTAT 0xB020004C
1059#define USBD_EP4RDSTAT 0xB0200050 1059#define USBD_EP4RDSTAT 0xB0200050
1060#define USBD_EP5RDSTAT 0xB0200054 1060#define USBD_EP5RDSTAT 0xB0200054
1061 #define USBDEV_FSTAT_FLUSH (1<<6) 1061# define USBDEV_FSTAT_FLUSH (1<<6)
1062 #define USBDEV_FSTAT_UF (1<<5) 1062# define USBDEV_FSTAT_UF (1<<5)
1063 #define USBDEV_FSTAT_OF (1<<4) 1063# define USBDEV_FSTAT_OF (1<<4)
1064 #define USBDEV_FSTAT_FCNT_BIT 0 1064# define USBDEV_FSTAT_FCNT_BIT 0
1065 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066#define USBD_ENABLE 0xB0200058 1066#define USBD_ENABLE 0xB0200058
1067 #define USBDEV_ENABLE (1<<1) 1067# define USBDEV_ENABLE (1<<1)
1068 #define USBDEV_CE (1<<0) 1068# define USBDEV_CE (1<<0)
1069 1069
1070#endif /* !CONFIG_SOC_AU1200 */ 1070#endif /* !CONFIG_SOC_AU1200 */
1071 1071
@@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1073 1073
1074/* 4 byte offsets from AU1000_ETH_BASE */ 1074/* 4 byte offsets from AU1000_ETH_BASE */
1075#define MAC_CONTROL 0x0 1075#define MAC_CONTROL 0x0
1076 #define MAC_RX_ENABLE (1<<2) 1076# define MAC_RX_ENABLE (1<<2)
1077 #define MAC_TX_ENABLE (1<<3) 1077# define MAC_TX_ENABLE (1<<3)
1078 #define MAC_DEF_CHECK (1<<5) 1078# define MAC_DEF_CHECK (1<<5)
1079 #define MAC_SET_BL(X) (((X)&0x3)<<6) 1079# define MAC_SET_BL(X) (((X)&0x3)<<6)
1080 #define MAC_AUTO_PAD (1<<8) 1080# define MAC_AUTO_PAD (1<<8)
1081 #define MAC_DISABLE_RETRY (1<<10) 1081# define MAC_DISABLE_RETRY (1<<10)
1082 #define MAC_DISABLE_BCAST (1<<11) 1082# define MAC_DISABLE_BCAST (1<<11)
1083 #define MAC_LATE_COL (1<<12) 1083# define MAC_LATE_COL (1<<12)
1084 #define MAC_HASH_MODE (1<<13) 1084# define MAC_HASH_MODE (1<<13)
1085 #define MAC_HASH_ONLY (1<<15) 1085# define MAC_HASH_ONLY (1<<15)
1086 #define MAC_PASS_ALL (1<<16) 1086# define MAC_PASS_ALL (1<<16)
1087 #define MAC_INVERSE_FILTER (1<<17) 1087# define MAC_INVERSE_FILTER (1<<17)
1088 #define MAC_PROMISCUOUS (1<<18) 1088# define MAC_PROMISCUOUS (1<<18)
1089 #define MAC_PASS_ALL_MULTI (1<<19) 1089# define MAC_PASS_ALL_MULTI (1<<19)
1090 #define MAC_FULL_DUPLEX (1<<20) 1090# define MAC_FULL_DUPLEX (1<<20)
1091 #define MAC_NORMAL_MODE 0 1091# define MAC_NORMAL_MODE 0
1092 #define MAC_INT_LOOPBACK (1<<21) 1092# define MAC_INT_LOOPBACK (1<<21)
1093 #define MAC_EXT_LOOPBACK (1<<22) 1093# define MAC_EXT_LOOPBACK (1<<22)
1094 #define MAC_DISABLE_RX_OWN (1<<23) 1094# define MAC_DISABLE_RX_OWN (1<<23)
1095 #define MAC_BIG_ENDIAN (1<<30) 1095# define MAC_BIG_ENDIAN (1<<30)
1096 #define MAC_RX_ALL (1<<31) 1096# define MAC_RX_ALL (1<<31)
1097#define MAC_ADDRESS_HIGH 0x4 1097#define MAC_ADDRESS_HIGH 0x4
1098#define MAC_ADDRESS_LOW 0x8 1098#define MAC_ADDRESS_LOW 0x8
1099#define MAC_MCAST_HIGH 0xC 1099#define MAC_MCAST_HIGH 0xC
1100#define MAC_MCAST_LOW 0x10 1100#define MAC_MCAST_LOW 0x10
1101#define MAC_MII_CNTRL 0x14 1101#define MAC_MII_CNTRL 0x14
1102 #define MAC_MII_BUSY (1<<0) 1102# define MAC_MII_BUSY (1<<0)
1103 #define MAC_MII_READ 0 1103# define MAC_MII_READ 0
1104 #define MAC_MII_WRITE (1<<1) 1104# define MAC_MII_WRITE (1<<1)
1105 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1105# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1106 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1106# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1107#define MAC_MII_DATA 0x18 1107#define MAC_MII_DATA 0x18
1108#define MAC_FLOW_CNTRL 0x1C 1108#define MAC_FLOW_CNTRL 0x1C
1109 #define MAC_FLOW_CNTRL_BUSY (1<<0) 1109# define MAC_FLOW_CNTRL_BUSY (1<<0)
1110 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 1110# define MAC_FLOW_CNTRL_ENABLE (1<<1)
1111 #define MAC_PASS_CONTROL (1<<2) 1111# define MAC_PASS_CONTROL (1<<2)
1112 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1112# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1113#define MAC_VLAN1_TAG 0x20 1113#define MAC_VLAN1_TAG 0x20
1114#define MAC_VLAN2_TAG 0x24 1114#define MAC_VLAN2_TAG 0x24
1115 1115
1116/* Ethernet Controller Enable */ 1116/* Ethernet Controller Enable */
1117 1117
1118 #define MAC_EN_CLOCK_ENABLE (1<<0) 1118# define MAC_EN_CLOCK_ENABLE (1<<0)
1119 #define MAC_EN_RESET0 (1<<1) 1119# define MAC_EN_RESET0 (1<<1)
1120 #define MAC_EN_TOSS (0<<2) 1120# define MAC_EN_TOSS (0<<2)
1121 #define MAC_EN_CACHEABLE (1<<3) 1121# define MAC_EN_CACHEABLE (1<<3)
1122 #define MAC_EN_RESET1 (1<<4) 1122# define MAC_EN_RESET1 (1<<4)
1123 #define MAC_EN_RESET2 (1<<5) 1123# define MAC_EN_RESET2 (1<<5)
1124 #define MAC_DMA_RESET (1<<6) 1124# define MAC_DMA_RESET (1<<6)
1125 1125
1126/* Ethernet Controller DMA Channels */ 1126/* Ethernet Controller DMA Channels */
1127 1127
@@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1129#define MAC1_TX_DMA_ADDR 0xB4004200 1129#define MAC1_TX_DMA_ADDR 0xB4004200
1130/* offsets from MAC_TX_RING_ADDR address */ 1130/* offsets from MAC_TX_RING_ADDR address */
1131#define MAC_TX_BUFF0_STATUS 0x0 1131#define MAC_TX_BUFF0_STATUS 0x0
1132 #define TX_FRAME_ABORTED (1<<0) 1132# define TX_FRAME_ABORTED (1<<0)
1133 #define TX_JAB_TIMEOUT (1<<1) 1133# define TX_JAB_TIMEOUT (1<<1)
1134 #define TX_NO_CARRIER (1<<2) 1134# define TX_NO_CARRIER (1<<2)
1135 #define TX_LOSS_CARRIER (1<<3) 1135# define TX_LOSS_CARRIER (1<<3)
1136 #define TX_EXC_DEF (1<<4) 1136# define TX_EXC_DEF (1<<4)
1137 #define TX_LATE_COLL_ABORT (1<<5) 1137# define TX_LATE_COLL_ABORT (1<<5)
1138 #define TX_EXC_COLL (1<<6) 1138# define TX_EXC_COLL (1<<6)
1139 #define TX_UNDERRUN (1<<7) 1139# define TX_UNDERRUN (1<<7)
1140 #define TX_DEFERRED (1<<8) 1140# define TX_DEFERRED (1<<8)
1141 #define TX_LATE_COLL (1<<9) 1141# define TX_LATE_COLL (1<<9)
1142 #define TX_COLL_CNT_MASK (0xF<<10) 1142# define TX_COLL_CNT_MASK (0xF<<10)
1143 #define TX_PKT_RETRY (1<<31) 1143# define TX_PKT_RETRY (1<<31)
1144#define MAC_TX_BUFF0_ADDR 0x4 1144#define MAC_TX_BUFF0_ADDR 0x4
1145 #define TX_DMA_ENABLE (1<<0) 1145# define TX_DMA_ENABLE (1<<0)
1146 #define TX_T_DONE (1<<1) 1146# define TX_T_DONE (1<<1)
1147 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1147# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1148#define MAC_TX_BUFF0_LEN 0x8 1148#define MAC_TX_BUFF0_LEN 0x8
1149#define MAC_TX_BUFF1_STATUS 0x10 1149#define MAC_TX_BUFF1_STATUS 0x10
1150#define MAC_TX_BUFF1_ADDR 0x14 1150#define MAC_TX_BUFF1_ADDR 0x14
@@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1160#define MAC1_RX_DMA_ADDR 0xB4004300 1160#define MAC1_RX_DMA_ADDR 0xB4004300
1161/* offsets from MAC_RX_RING_ADDR */ 1161/* offsets from MAC_RX_RING_ADDR */
1162#define MAC_RX_BUFF0_STATUS 0x0 1162#define MAC_RX_BUFF0_STATUS 0x0
1163 #define RX_FRAME_LEN_MASK 0x3fff 1163# define RX_FRAME_LEN_MASK 0x3fff
1164 #define RX_WDOG_TIMER (1<<14) 1164# define RX_WDOG_TIMER (1<<14)
1165 #define RX_RUNT (1<<15) 1165# define RX_RUNT (1<<15)
1166 #define RX_OVERLEN (1<<16) 1166# define RX_OVERLEN (1<<16)
1167 #define RX_COLL (1<<17) 1167# define RX_COLL (1<<17)
1168 #define RX_ETHER (1<<18) 1168# define RX_ETHER (1<<18)
1169 #define RX_MII_ERROR (1<<19) 1169# define RX_MII_ERROR (1<<19)
1170 #define RX_DRIBBLING (1<<20) 1170# define RX_DRIBBLING (1<<20)
1171 #define RX_CRC_ERROR (1<<21) 1171# define RX_CRC_ERROR (1<<21)
1172 #define RX_VLAN1 (1<<22) 1172# define RX_VLAN1 (1<<22)
1173 #define RX_VLAN2 (1<<23) 1173# define RX_VLAN2 (1<<23)
1174 #define RX_LEN_ERROR (1<<24) 1174# define RX_LEN_ERROR (1<<24)
1175 #define RX_CNTRL_FRAME (1<<25) 1175# define RX_CNTRL_FRAME (1<<25)
1176 #define RX_U_CNTRL_FRAME (1<<26) 1176# define RX_U_CNTRL_FRAME (1<<26)
1177 #define RX_MCAST_FRAME (1<<27) 1177# define RX_MCAST_FRAME (1<<27)
1178 #define RX_BCAST_FRAME (1<<28) 1178# define RX_BCAST_FRAME (1<<28)
1179 #define RX_FILTER_FAIL (1<<29) 1179# define RX_FILTER_FAIL (1<<29)
1180 #define RX_PACKET_FILTER (1<<30) 1180# define RX_PACKET_FILTER (1<<30)
1181 #define RX_MISSED_FRAME (1<<31) 1181# define RX_MISSED_FRAME (1<<31)
1182 1182
1183 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186#define MAC_RX_BUFF0_ADDR 0x4 1186#define MAC_RX_BUFF0_ADDR 0x4
1187 #define RX_DMA_ENABLE (1<<0) 1187# define RX_DMA_ENABLE (1<<0)
1188 #define RX_T_DONE (1<<1) 1188# define RX_T_DONE (1<<1)
1189 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1189# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1190 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1190# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1191#define MAC_RX_BUFF1_STATUS 0x10 1191#define MAC_RX_BUFF1_STATUS 0x10
1192#define MAC_RX_BUFF1_ADDR 0x14 1192#define MAC_RX_BUFF1_ADDR 0x14
1193#define MAC_RX_BUFF2_STATUS 0x20 1193#define MAC_RX_BUFF2_STATUS 0x20
@@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1298 1298
1299/* SSIO */ 1299/* SSIO */
1300#define SSI0_STATUS 0xB1600000 1300#define SSI0_STATUS 0xB1600000
1301 #define SSI_STATUS_BF (1<<4) 1301# define SSI_STATUS_BF (1<<4)
1302 #define SSI_STATUS_OF (1<<3) 1302# define SSI_STATUS_OF (1<<3)
1303 #define SSI_STATUS_UF (1<<2) 1303# define SSI_STATUS_UF (1<<2)
1304 #define SSI_STATUS_D (1<<1) 1304# define SSI_STATUS_D (1<<1)
1305 #define SSI_STATUS_B (1<<0) 1305# define SSI_STATUS_B (1<<0)
1306#define SSI0_INT 0xB1600004 1306#define SSI0_INT 0xB1600004
1307 #define SSI_INT_OI (1<<3) 1307# define SSI_INT_OI (1<<3)
1308 #define SSI_INT_UI (1<<2) 1308# define SSI_INT_UI (1<<2)
1309 #define SSI_INT_DI (1<<1) 1309# define SSI_INT_DI (1<<1)
1310#define SSI0_INT_ENABLE 0xB1600008 1310#define SSI0_INT_ENABLE 0xB1600008
1311 #define SSI_INTE_OIE (1<<3) 1311# define SSI_INTE_OIE (1<<3)
1312 #define SSI_INTE_UIE (1<<2) 1312# define SSI_INTE_UIE (1<<2)
1313 #define SSI_INTE_DIE (1<<1) 1313# define SSI_INTE_DIE (1<<1)
1314#define SSI0_CONFIG 0xB1600020 1314#define SSI0_CONFIG 0xB1600020
1315 #define SSI_CONFIG_AO (1<<24) 1315# define SSI_CONFIG_AO (1<<24)
1316 #define SSI_CONFIG_DO (1<<23) 1316# define SSI_CONFIG_DO (1<<23)
1317 #define SSI_CONFIG_ALEN_BIT 20 1317# define SSI_CONFIG_ALEN_BIT 20
1318 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 1318# define SSI_CONFIG_ALEN_MASK (0x7<<20)
1319 #define SSI_CONFIG_DLEN_BIT 16 1319# define SSI_CONFIG_DLEN_BIT 16
1320 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 1320# define SSI_CONFIG_DLEN_MASK (0x7<<16)
1321 #define SSI_CONFIG_DD (1<<11) 1321# define SSI_CONFIG_DD (1<<11)
1322 #define SSI_CONFIG_AD (1<<10) 1322# define SSI_CONFIG_AD (1<<10)
1323 #define SSI_CONFIG_BM_BIT 8 1323# define SSI_CONFIG_BM_BIT 8
1324 #define SSI_CONFIG_BM_MASK (0x3<<8) 1324# define SSI_CONFIG_BM_MASK (0x3<<8)
1325 #define SSI_CONFIG_CE (1<<7) 1325# define SSI_CONFIG_CE (1<<7)
1326 #define SSI_CONFIG_DP (1<<6) 1326# define SSI_CONFIG_DP (1<<6)
1327 #define SSI_CONFIG_DL (1<<5) 1327# define SSI_CONFIG_DL (1<<5)
1328 #define SSI_CONFIG_EP (1<<4) 1328# define SSI_CONFIG_EP (1<<4)
1329#define SSI0_ADATA 0xB1600024 1329#define SSI0_ADATA 0xB1600024
1330 #define SSI_AD_D (1<<24) 1330# define SSI_AD_D (1<<24)
1331 #define SSI_AD_ADDR_BIT 16 1331# define SSI_AD_ADDR_BIT 16
1332 #define SSI_AD_ADDR_MASK (0xff<<16) 1332# define SSI_AD_ADDR_MASK (0xff<<16)
1333 #define SSI_AD_DATA_BIT 0 1333# define SSI_AD_DATA_BIT 0
1334 #define SSI_AD_DATA_MASK (0xfff<<0) 1334# define SSI_AD_DATA_MASK (0xfff<<0)
1335#define SSI0_CLKDIV 0xB1600028 1335#define SSI0_CLKDIV 0xB1600028
1336#define SSI0_CONTROL 0xB1600100 1336#define SSI0_CONTROL 0xB1600100
1337 #define SSI_CONTROL_CD (1<<1) 1337# define SSI_CONTROL_CD (1<<1)
1338 #define SSI_CONTROL_E (1<<0) 1338# define SSI_CONTROL_E (1<<0)
1339 1339
1340/* SSI1 */ 1340/* SSI1 */
1341#define SSI1_STATUS 0xB1680000 1341#define SSI1_STATUS 0xB1680000
@@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1402#define IR_INT_CLEAR (IRDA_BASE+0x18) 1402#define IR_INT_CLEAR (IRDA_BASE+0x18)
1403#define IR_CONFIG_1 (IRDA_BASE+0x20) 1403#define IR_CONFIG_1 (IRDA_BASE+0x20)
1404 #define IR_RX_INVERT_LED (1<<0) 1404# define IR_RX_INVERT_LED (1<<0)
1405 #define IR_TX_INVERT_LED (1<<1) 1405# define IR_TX_INVERT_LED (1<<1)
1406 #define IR_ST (1<<2) 1406# define IR_ST (1<<2)
1407 #define IR_SF (1<<3) 1407# define IR_SF (1<<3)
1408 #define IR_SIR (1<<4) 1408# define IR_SIR (1<<4)
1409 #define IR_MIR (1<<5) 1409# define IR_MIR (1<<5)
1410 #define IR_FIR (1<<6) 1410# define IR_FIR (1<<6)
1411 #define IR_16CRC (1<<7) 1411# define IR_16CRC (1<<7)
1412 #define IR_TD (1<<8) 1412# define IR_TD (1<<8)
1413 #define IR_RX_ALL (1<<9) 1413# define IR_RX_ALL (1<<9)
1414 #define IR_DMA_ENABLE (1<<10) 1414# define IR_DMA_ENABLE (1<<10)
1415 #define IR_RX_ENABLE (1<<11) 1415# define IR_RX_ENABLE (1<<11)
1416 #define IR_TX_ENABLE (1<<12) 1416# define IR_TX_ENABLE (1<<12)
1417 #define IR_LOOPBACK (1<<14) 1417# define IR_LOOPBACK (1<<14)
1418 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1418# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1420#define IR_SIR_FLAGS (IRDA_BASE+0x24)
1421#define IR_ENABLE (IRDA_BASE+0x28) 1421#define IR_ENABLE (IRDA_BASE+0x28)
1422 #define IR_RX_STATUS (1<<9) 1422# define IR_RX_STATUS (1<<9)
1423 #define IR_TX_STATUS (1<<10) 1423# define IR_TX_STATUS (1<<10)
1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1428#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1428#define IR_CONFIG_2 (IRDA_BASE+0x3C)
1429 #define IR_MODE_INV (1<<0) 1429# define IR_MODE_INV (1<<0)
1430 #define IR_ONE_PIN (1<<1) 1430# define IR_ONE_PIN (1<<1)
1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1432 1432
1433/* GPIO */ 1433/* GPIO */
1434#define SYS_PINFUNC 0xB190002C 1434#define SYS_PINFUNC 0xB190002C
1435 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1435# define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1436 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1436# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1437 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1437# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1438 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1438# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1439 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1439# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1440 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1440# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1441 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1441# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1442 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1442# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1443 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1443# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1444 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1444# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1445 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1445# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1446 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1446# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1447 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1447# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1448 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1448# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1449 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1449# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1450 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1450# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1451 1451
1452/* Au1100 Only */ 1452/* Au1100 Only */
1453 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1453# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1454 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1454# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1455 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1455# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1456 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1456# define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1457 1457
1458/* Au1550 Only. Redefines lots of pins */ 1458/* Au1550 Only. Redefines lots of pins */
1459 #define SYS_PF_PSC2_MASK (7 << 17) 1459# define SYS_PF_PSC2_MASK (7 << 17)
1460 #define SYS_PF_PSC2_AC97 (0) 1460# define SYS_PF_PSC2_AC97 (0)
1461 #define SYS_PF_PSC2_SPI (0) 1461# define SYS_PF_PSC2_SPI (0)
1462 #define SYS_PF_PSC2_I2S (1 << 17) 1462# define SYS_PF_PSC2_I2S (1 << 17)
1463 #define SYS_PF_PSC2_SMBUS (3 << 17) 1463# define SYS_PF_PSC2_SMBUS (3 << 17)
1464 #define SYS_PF_PSC2_GPIO (7 << 17) 1464# define SYS_PF_PSC2_GPIO (7 << 17)
1465 #define SYS_PF_PSC3_MASK (7 << 20) 1465# define SYS_PF_PSC3_MASK (7 << 20)
1466 #define SYS_PF_PSC3_AC97 (0) 1466# define SYS_PF_PSC3_AC97 (0)
1467 #define SYS_PF_PSC3_SPI (0) 1467# define SYS_PF_PSC3_SPI (0)
1468 #define SYS_PF_PSC3_I2S (1 << 20) 1468# define SYS_PF_PSC3_I2S (1 << 20)
1469 #define SYS_PF_PSC3_SMBUS (3 << 20) 1469# define SYS_PF_PSC3_SMBUS (3 << 20)
1470 #define SYS_PF_PSC3_GPIO (7 << 20) 1470# define SYS_PF_PSC3_GPIO (7 << 20)
1471 #define SYS_PF_PSC1_S1 (1 << 1) 1471# define SYS_PF_PSC1_S1 (1 << 1)
1472 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1472# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1473 1473
1474/* Au1200 Only */ 1474/* Au1200 Only */
1475#ifdef CONFIG_SOC_AU1200 1475#ifdef CONFIG_SOC_AU1200
@@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1530 1530
1531/* Clock Controller */ 1531/* Clock Controller */
1532#define SYS_FREQCTRL0 0xB1900020 1532#define SYS_FREQCTRL0 0xB1900020
1533 #define SYS_FC_FRDIV2_BIT 22 1533# define SYS_FC_FRDIV2_BIT 22
1534 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1534# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535 #define SYS_FC_FE2 (1<<21) 1535# define SYS_FC_FE2 (1<<21)
1536 #define SYS_FC_FS2 (1<<20) 1536# define SYS_FC_FS2 (1<<20)
1537 #define SYS_FC_FRDIV1_BIT 12 1537# define SYS_FC_FRDIV1_BIT 12
1538 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1538# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539 #define SYS_FC_FE1 (1<<11) 1539# define SYS_FC_FE1 (1<<11)
1540 #define SYS_FC_FS1 (1<<10) 1540# define SYS_FC_FS1 (1<<10)
1541 #define SYS_FC_FRDIV0_BIT 2 1541# define SYS_FC_FRDIV0_BIT 2
1542 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1542# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543 #define SYS_FC_FE0 (1<<1) 1543# define SYS_FC_FE0 (1<<1)
1544 #define SYS_FC_FS0 (1<<0) 1544# define SYS_FC_FS0 (1<<0)
1545#define SYS_FREQCTRL1 0xB1900024 1545#define SYS_FREQCTRL1 0xB1900024
1546 #define SYS_FC_FRDIV5_BIT 22 1546# define SYS_FC_FRDIV5_BIT 22
1547 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1547# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548 #define SYS_FC_FE5 (1<<21) 1548# define SYS_FC_FE5 (1<<21)
1549 #define SYS_FC_FS5 (1<<20) 1549# define SYS_FC_FS5 (1<<20)
1550 #define SYS_FC_FRDIV4_BIT 12 1550# define SYS_FC_FRDIV4_BIT 12
1551 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1551# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552 #define SYS_FC_FE4 (1<<11) 1552# define SYS_FC_FE4 (1<<11)
1553 #define SYS_FC_FS4 (1<<10) 1553# define SYS_FC_FS4 (1<<10)
1554 #define SYS_FC_FRDIV3_BIT 2 1554# define SYS_FC_FRDIV3_BIT 2
1555 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1555# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556 #define SYS_FC_FE3 (1<<1) 1556# define SYS_FC_FE3 (1<<1)
1557 #define SYS_FC_FS3 (1<<0) 1557# define SYS_FC_FS3 (1<<0)
1558#define SYS_CLKSRC 0xB1900028 1558#define SYS_CLKSRC 0xB1900028
1559 #define SYS_CS_ME1_BIT 27 1559# define SYS_CS_ME1_BIT 27
1560 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1560# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1561 #define SYS_CS_DE1 (1<<26) 1561# define SYS_CS_DE1 (1<<26)
1562 #define SYS_CS_CE1 (1<<25) 1562# define SYS_CS_CE1 (1<<25)
1563 #define SYS_CS_ME0_BIT 22 1563# define SYS_CS_ME0_BIT 22
1564 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1564# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1565 #define SYS_CS_DE0 (1<<21) 1565# define SYS_CS_DE0 (1<<21)
1566 #define SYS_CS_CE0 (1<<20) 1566# define SYS_CS_CE0 (1<<20)
1567 #define SYS_CS_MI2_BIT 17 1567# define SYS_CS_MI2_BIT 17
1568 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1568# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1569 #define SYS_CS_DI2 (1<<16) 1569# define SYS_CS_DI2 (1<<16)
1570 #define SYS_CS_CI2 (1<<15) 1570# define SYS_CS_CI2 (1<<15)
1571#ifdef CONFIG_SOC_AU1100 1571#ifdef CONFIG_SOC_AU1100
1572 #define SYS_CS_ML_BIT 7 1572# define SYS_CS_ML_BIT 7
1573 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1573# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1574 #define SYS_CS_DL (1<<6) 1574# define SYS_CS_DL (1<<6)
1575 #define SYS_CS_CL (1<<5) 1575# define SYS_CS_CL (1<<5)
1576#else 1576#else
1577 #define SYS_CS_MUH_BIT 12 1577# define SYS_CS_MUH_BIT 12
1578 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1578# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1579 #define SYS_CS_DUH (1<<11) 1579# define SYS_CS_DUH (1<<11)
1580 #define SYS_CS_CUH (1<<10) 1580# define SYS_CS_CUH (1<<10)
1581 #define SYS_CS_MUD_BIT 7 1581# define SYS_CS_MUD_BIT 7
1582 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1582# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1583 #define SYS_CS_DUD (1<<6) 1583# define SYS_CS_DUD (1<<6)
1584 #define SYS_CS_CUD (1<<5) 1584# define SYS_CS_CUD (1<<5)
1585#endif 1585#endif
1586 #define SYS_CS_MIR_BIT 2 1586# define SYS_CS_MIR_BIT 2
1587 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1587# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1588 #define SYS_CS_DIR (1<<1) 1588# define SYS_CS_DIR (1<<1)
1589 #define SYS_CS_CIR (1<<0) 1589# define SYS_CS_CIR (1<<0)
1590 1590
1591 #define SYS_CS_MUX_AUX 0x1 1591# define SYS_CS_MUX_AUX 0x1
1592 #define SYS_CS_MUX_FQ0 0x2 1592# define SYS_CS_MUX_FQ0 0x2
1593 #define SYS_CS_MUX_FQ1 0x3 1593# define SYS_CS_MUX_FQ1 0x3
1594 #define SYS_CS_MUX_FQ2 0x4 1594# define SYS_CS_MUX_FQ2 0x4
1595 #define SYS_CS_MUX_FQ3 0x5 1595# define SYS_CS_MUX_FQ3 0x5
1596 #define SYS_CS_MUX_FQ4 0x6 1596# define SYS_CS_MUX_FQ4 0x6
1597 #define SYS_CS_MUX_FQ5 0x7 1597# define SYS_CS_MUX_FQ5 0x7
1598#define SYS_CPUPLL 0xB1900060 1598#define SYS_CPUPLL 0xB1900060
1599#define SYS_AUXPLL 0xB1900064 1599#define SYS_AUXPLL 0xB1900064
1600 1600
1601/* AC97 Controller */ 1601/* AC97 Controller */
1602#define AC97C_CONFIG 0xB0000000 1602#define AC97C_CONFIG 0xB0000000
1603 #define AC97C_RECV_SLOTS_BIT 13 1603# define AC97C_RECV_SLOTS_BIT 13
1604 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1604# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605 #define AC97C_XMIT_SLOTS_BIT 3 1605# define AC97C_XMIT_SLOTS_BIT 3
1606 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1606# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607 #define AC97C_SG (1<<2) 1607# define AC97C_SG (1<<2)
1608 #define AC97C_SYNC (1<<1) 1608# define AC97C_SYNC (1<<1)
1609 #define AC97C_RESET (1<<0) 1609# define AC97C_RESET (1<<0)
1610#define AC97C_STATUS 0xB0000004 1610#define AC97C_STATUS 0xB0000004
1611 #define AC97C_XU (1<<11) 1611# define AC97C_XU (1<<11)
1612 #define AC97C_XO (1<<10) 1612# define AC97C_XO (1<<10)
1613 #define AC97C_RU (1<<9) 1613# define AC97C_RU (1<<9)
1614 #define AC97C_RO (1<<8) 1614# define AC97C_RO (1<<8)
1615 #define AC97C_READY (1<<7) 1615# define AC97C_READY (1<<7)
1616 #define AC97C_CP (1<<6) 1616# define AC97C_CP (1<<6)
1617 #define AC97C_TR (1<<5) 1617# define AC97C_TR (1<<5)
1618 #define AC97C_TE (1<<4) 1618# define AC97C_TE (1<<4)
1619 #define AC97C_TF (1<<3) 1619# define AC97C_TF (1<<3)
1620 #define AC97C_RR (1<<2) 1620# define AC97C_RR (1<<2)
1621 #define AC97C_RE (1<<1) 1621# define AC97C_RE (1<<1)
1622 #define AC97C_RF (1<<0) 1622# define AC97C_RF (1<<0)
1623#define AC97C_DATA 0xB0000008 1623#define AC97C_DATA 0xB0000008
1624#define AC97C_CMD 0xB000000C 1624#define AC97C_CMD 0xB000000C
1625 #define AC97C_WD_BIT 16 1625# define AC97C_WD_BIT 16
1626 #define AC97C_READ (1<<7) 1626# define AC97C_READ (1<<7)
1627 #define AC97C_INDEX_MASK 0x7f 1627# define AC97C_INDEX_MASK 0x7f
1628#define AC97C_CNTRL 0xB0000010 1628#define AC97C_CNTRL 0xB0000010
1629 #define AC97C_RS (1<<1) 1629# define AC97C_RS (1<<1)
1630 #define AC97C_CE (1<<0) 1630# define AC97C_CE (1<<0)
1631 1631
1632 1632
1633/* Secure Digital (SD) Controller */ 1633/* Secure Digital (SD) Controller */
@@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1636#define SD1_XMIT_FIFO 0xB0680000 1636#define SD1_XMIT_FIFO 0xB0680000
1637#define SD1_RECV_FIFO 0xB0680004 1637#define SD1_RECV_FIFO 0xB0680004
1638 1638
1639#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1639#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640/* Au1500 PCI Controller */ 1640/* Au1500 PCI Controller */
1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1644# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index 4663e8b415c9..aef0edbfe4c6 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port);
136void auide_outsw(unsigned long port, void *addr, u32 count); 136void auide_outsw(unsigned long port, void *addr, u32 count);
137void auide_outsl(unsigned long port, void *addr, u32 count); 137void auide_outsl(unsigned long port, void *addr, u32 count);
138static void auide_tune_drive(ide_drive_t *drive, byte pio); 138static void auide_tune_drive(ide_drive_t *drive, byte pio);
139static int auide_tune_chipset (ide_drive_t *drive, u8 speed); 139static int auide_tune_chipset(ide_drive_t *drive, u8 speed);
140static int auide_ddma_init( _auide_hwif *auide ); 140static int auide_ddma_init( _auide_hwif *auide );
141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); 141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
142int __init auide_probe(void); 142int __init auide_probe(void);
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
index f6198a21fba1..b1e0be60f720 100644
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -2,7 +2,7 @@
2#define __ASM_MACH_IP32_KMALLOC_H 2#define __ASM_MACH_IP32_KMALLOC_H
3 3
4 4
5#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) 5#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
6#define ARCH_KMALLOC_MINALIGN 32 6#define ARCH_KMALLOC_MINALIGN 32
7#else 7#else
8#define ARCH_KMALLOC_MINALIGN 128 8#define ARCH_KMALLOC_MINALIGN 128
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index 50c1e413a688..b52e0e7ee3fb 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -32,38 +32,38 @@
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
33 33
34#define PB1000_PCR 0xBE000000 34#define PB1000_PCR 0xBE000000
35 #define PCR_SLOT_0_VPP0 (1<<0) 35# define PCR_SLOT_0_VPP0 (1<<0)
36 #define PCR_SLOT_0_VPP1 (1<<1) 36# define PCR_SLOT_0_VPP1 (1<<1)
37 #define PCR_SLOT_0_VCC0 (1<<2) 37# define PCR_SLOT_0_VCC0 (1<<2)
38 #define PCR_SLOT_0_VCC1 (1<<3) 38# define PCR_SLOT_0_VCC1 (1<<3)
39 #define PCR_SLOT_0_RST (1<<4) 39# define PCR_SLOT_0_RST (1<<4)
40 40
41 #define PCR_SLOT_1_VPP0 (1<<8) 41# define PCR_SLOT_1_VPP0 (1<<8)
42 #define PCR_SLOT_1_VPP1 (1<<9) 42# define PCR_SLOT_1_VPP1 (1<<9)
43 #define PCR_SLOT_1_VCC0 (1<<10) 43# define PCR_SLOT_1_VCC0 (1<<10)
44 #define PCR_SLOT_1_VCC1 (1<<11) 44# define PCR_SLOT_1_VCC1 (1<<11)
45 #define PCR_SLOT_1_RST (1<<12) 45# define PCR_SLOT_1_RST (1<<12)
46 46
47#define PB1000_MDR 0xBE000004 47#define PB1000_MDR 0xBE000004
48 #define MDR_PI (1<<5) /* pcmcia int latch */ 48# define MDR_PI (1<<5) /* pcmcia int latch */
49 #define MDR_EPI (1<<14) /* enable pcmcia int */ 49# define MDR_EPI (1<<14) /* enable pcmcia int */
50 #define MDR_CPI (1<<15) /* clear pcmcia int */ 50# define MDR_CPI (1<<15) /* clear pcmcia int */
51 51
52#define PB1000_ACR1 0xBE000008 52#define PB1000_ACR1 0xBE000008
53 #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 53# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
54 #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 54# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
55 #define ACR1_SLOT_0_READY (1<<2) /* ready */ 55# define ACR1_SLOT_0_READY (1<<2) /* ready */
56 #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 56# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
57 #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 57# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
58 #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 58# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
59 #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 59# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
60 #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 60# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
61 #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 61# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
62 #define ACR1_SLOT_1_READY (1<<10) /* ready */ 62# define ACR1_SLOT_1_READY (1<<10) /* ready */
63 #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 63# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
64 #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 64# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
65 #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 65# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
66 #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 66# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
67 67
68#define CPLD_AUX0 0xBE00000C 68#define CPLD_AUX0 0xBE00000C
69#define CPLD_AUX1 0xBE000010 69#define CPLD_AUX1 0xBE000010
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 4c5a1cd01841..63aa3926b297 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -29,44 +29,44 @@
29 29
30#define PB1100_IDENT 0xAE000000 30#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 31#define BOARD_STATUS_REG 0xAE000004
32 #define PB1100_ROM_SEL (1<<15) 32# define PB1100_ROM_SEL (1<<15)
33 #define PB1100_ROM_SIZ (1<<14) 33# define PB1100_ROM_SIZ (1<<14)
34 #define PB1100_SWAP_BOOT (1<<13) 34# define PB1100_SWAP_BOOT (1<<13)
35 #define PB1100_FLASH_WP (1<<12) 35# define PB1100_FLASH_WP (1<<12)
36 #define PB1100_ROM_H_STS (1<<11) 36# define PB1100_ROM_H_STS (1<<11)
37 #define PB1100_ROM_L_STS (1<<10) 37# define PB1100_ROM_L_STS (1<<10)
38 #define PB1100_FLASH_H_STS (1<<9) 38# define PB1100_FLASH_H_STS (1<<9)
39 #define PB1100_FLASH_L_STS (1<<8) 39# define PB1100_FLASH_L_STS (1<<8)
40 #define PB1100_SRAM_SIZ (1<<7) 40# define PB1100_SRAM_SIZ (1<<7)
41 #define PB1100_TSC_BUSY (1<<6) 41# define PB1100_TSC_BUSY (1<<6)
42 #define PB1100_PCMCIA_VS_MASK (3<<4) 42# define PB1100_PCMCIA_VS_MASK (3<<4)
43 #define PB1100_RS232_CD (1<<3) 43# define PB1100_RS232_CD (1<<3)
44 #define PB1100_RS232_CTS (1<<2) 44# define PB1100_RS232_CTS (1<<2)
45 #define PB1100_RS232_DSR (1<<1) 45# define PB1100_RS232_DSR (1<<1)
46 #define PB1100_RS232_RI (1<<0) 46# define PB1100_RS232_RI (1<<0)
47 47
48#define PB1100_IRDA_RS232 0xAE00000C 48#define PB1100_IRDA_RS232 0xAE00000C
49 #define PB1100_IRDA_FULL (0<<14) /* full power */ 49# define PB1100_IRDA_FULL (0<<14) /* full power */
50 #define PB1100_IRDA_SHUTDOWN (1<<14) 50# define PB1100_IRDA_SHUTDOWN (1<<14)
51 #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
52 #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
53 #define PB1100_IRDA_FIR (1<<13) 53# define PB1100_IRDA_FIR (1<<13)
54 54
55#define PCMCIA_BOARD_REG 0xAE000010 55#define PCMCIA_BOARD_REG 0xAE000010
56 #define PB1100_SD_WP1_RO (1<<15) /* read only */ 56# define PB1100_SD_WP1_RO (1<<15) /* read only */
57 #define PB1100_SD_WP0_RO (1<<14) /* read only */ 57# define PB1100_SD_WP0_RO (1<<14) /* read only */
58 #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
59 #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
60 #define PB1100_SEL_SD_CONN1 (1<<9) 60# define PB1100_SEL_SD_CONN1 (1<<9)
61 #define PB1100_SEL_SD_CONN0 (1<<8) 61# define PB1100_SEL_SD_CONN0 (1<<8)
62 #define PC_DEASSERT_RST (1<<7) 62# define PC_DEASSERT_RST (1<<7)
63 #define PC_DRV_EN (1<<4) 63# define PC_DRV_EN (1<<4)
64 64
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 66
67#define PB1100_RST_VDDI 0xAE00001C 67#define PB1100_RST_VDDI 0xAE00001C
68 #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
69 #define PB1100_VDDI_MASK (0x1F) 69# define PB1100_VDDI_MASK (0x1F)
70 70
71#define PB1100_LEDS 0xAE000018 71#define PB1100_LEDS 0xAE000018
72 72
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
index 57102fa9da51..982079f410b5 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
200 200
201 icache_invd_loop: 201 icache_invd_loop:
202 /* 9 == register t1 */ 202 /* 9 == register t1 */
203 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 203 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ 204 (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
205 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 205 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ 206 (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
207 207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ 208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ 209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
235 235
236 dcache_wbinvd_loop: 236 dcache_wbinvd_loop:
237 /* 9 == register t1 */ 237 /* 9 == register t1 */
238 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ 239 (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
240 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ 241 (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
242 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ 243 (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
244 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ 245 (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
246 246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ 247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ 248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h
index a742e04e82de..f52656826cce 100644
--- a/include/asm-mips/parport.h
+++ b/include/asm-mips/parport.h
@@ -6,10 +6,10 @@
6#ifndef _ASM_PARPORT_H 6#ifndef _ASM_PARPORT_H
7#define _ASM_PARPORT_H 7#define _ASM_PARPORT_H
8 8
9static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); 9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) 10static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
11{ 11{
12 return parport_pc_find_isa_ports (autoirq, autodma); 12 return parport_pc_find_isa_ports(autoirq, autodma);
13} 13}
14 14
15#endif /* _ASM_PARPORT_H */ 15#endif /* _ASM_PARPORT_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
index 4aaaff670361..8121a9a75bfd 100644
--- a/include/asm-mips/prctl.h
+++ b/include/asm-mips/prctl.h
@@ -36,6 +36,6 @@ struct prda {
36 36
37#define t_sys prda_sys 37#define t_sys prda_sys
38 38
39ptrdiff_t prctl (int op, int v1, int v2); 39ptrdiff_t prctl(int op, int v1, int v2);
40 40
41#endif 41#endif
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index 3d6aa7c7ea81..ea2413c58e78 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -51,18 +51,18 @@ struct semaphore {
51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) 51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) 52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
53 53
54static inline void sema_init (struct semaphore *sem, int val) 54static inline void sema_init(struct semaphore *sem, int val)
55{ 55{
56 atomic_set(&sem->count, val); 56 atomic_set(&sem->count, val);
57 init_waitqueue_head(&sem->wait); 57 init_waitqueue_head(&sem->wait);
58} 58}
59 59
60static inline void init_MUTEX (struct semaphore *sem) 60static inline void init_MUTEX(struct semaphore *sem)
61{ 61{
62 sema_init(sem, 1); 62 sema_init(sem, 1);
63} 63}
64 64
65static inline void init_MUTEX_LOCKED (struct semaphore *sem) 65static inline void init_MUTEX_LOCKED(struct semaphore *sem)
66{ 66{
67 sema_init(sem, 0); 67 sema_init(sem, 0);
68} 68}
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 67c4fe52bb42..0cd719fabb51 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -18,7 +18,7 @@
18#ifdef CONFIG_32BIT 18#ifdef CONFIG_32BIT
19 19
20#define save_static_function(symbol) \ 20#define save_static_function(symbol) \
21__asm__ ( \ 21__asm__( \
22 ".text\n\t" \ 22 ".text\n\t" \
23 ".globl\t" #symbol "\n\t" \ 23 ".globl\t" #symbol "\n\t" \
24 ".align\t2\n\t" \ 24 ".align\t2\n\t" \
@@ -46,7 +46,7 @@ __asm__ ( \
46#ifdef CONFIG_64BIT 46#ifdef CONFIG_64BIT
47 47
48#define save_static_function(symbol) \ 48#define save_static_function(symbol) \
49__asm__ ( \ 49__asm__( \
50 ".text\n\t" \ 50 ".text\n\t" \
51 ".globl\t" #symbol "\n\t" \ 51 ".globl\t" #symbol "\n\t" \
52 ".align\t2\n\t" \ 52 ".align\t2\n\t" \
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
index 8fa0af6b68d2..6aa086868249 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/include/asm-mips/sn/addrs.h
@@ -50,7 +50,7 @@
50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) 50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
51 51
52#define CHANGE_ADDR_NASID(_pa, _nasid) \ 52#define CHANGE_ADDR_NASID(_pa, _nasid) \
53 ((UINT64_CAST (_pa) & ~NASID_MASK) | \ 53 ((UINT64_CAST(_pa) & ~NASID_MASK) | \
54 (UINT64_CAST(_nasid) << NASID_SHFT)) 54 (UINT64_CAST(_nasid) << NASID_SHFT))
55 55
56 56
@@ -75,7 +75,7 @@
75 75
76 76
77#define RAW_NODE_SWIN_BASE(nasid, widget) \ 77#define RAW_NODE_SWIN_BASE(nasid, widget) \
78 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 78 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
79 79
80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) 80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
81 81
@@ -192,21 +192,21 @@
192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ 192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
193 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 193 NODE_ADDRSPACE_SIZE * 3 / 4 + \
194 0x200) | \ 194 0x200) | \
195 UINT64_CAST (_pa) & NASID_MASK | \ 195 UINT64_CAST(_pa) & NASID_MASK | \
196 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 196 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
197 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 197 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
198 198
199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ 199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
200 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 200 NODE_ADDRSPACE_SIZE * 3 / 4 + \
201 0x208) | \ 201 0x208) | \
202 UINT64_CAST (_pa) & NASID_MASK | \ 202 UINT64_CAST(_pa) & NASID_MASK | \
203 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 203 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
204 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 204 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
205 205
206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ 206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
207 NODE_ADDRSPACE_SIZE * 3 / 4) | \ 207 NODE_ADDRSPACE_SIZE * 3 / 4) | \
208 UINT64_CAST (_pa) & NASID_MASK | \ 208 UINT64_CAST(_pa) & NASID_MASK | \
209 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
210 (_rgn) << 3) 210 (_rgn) << 3)
211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) 211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) 212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
@@ -214,9 +214,9 @@
214 214
215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ 215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
216 NODE_ADDRSPACE_SIZE / 2) | \ 216 NODE_ADDRSPACE_SIZE / 2) | \
217 UINT64_CAST (_pa) & NASID_MASK | \ 217 UINT64_CAST(_pa) & NASID_MASK | \
218 UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ 218 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
219 UINT64_CAST (_pa) >> 3 & 3) 219 UINT64_CAST(_pa) >> 3 & 3)
220 220
221/* 221/*
222 * Macro to convert a back door directory or protection address into the 222 * Macro to convert a back door directory or protection address into the
@@ -225,16 +225,16 @@
225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) 225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) 226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
227 227
228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
229 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ 229 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
230 (UINT64_CAST (_ba) & 0x1f << 4) << 3) 230 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
231 231
232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
233 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) 233 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
234 234
235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
236 (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ 236 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
237 (UINT64_CAST (_ba) & 3) << 3) 237 (UINT64_CAST(_ba) & 3) << 3)
238#endif /* CONFIG_SGI_IP27 */ 238#endif /* CONFIG_SGI_IP27 */
239 239
240 240
@@ -282,7 +282,7 @@
282 * the base of the register space. 282 * the base of the register space.
283 */ 283 */
284#define HUB_REG_PTR(_base, _off) \ 284#define HUB_REG_PTR(_base, _off) \
285 (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 285 (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
286 286
287#define HUB_REG_PTR_L(_base, _off) \ 287#define HUB_REG_PTR_L(_base, _off) \
288 HUB_L(HUB_REG_PTR((_base), (_off))) 288 HUB_L(HUB_REG_PTR((_base), (_off)))
diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h
index ab2fa8cd2627..24c6775fbb0f 100644
--- a/include/asm-mips/sn/io.h
+++ b/include/asm-mips/sn/io.h
@@ -9,7 +9,7 @@
9#ifndef _ASM_SN_IO_H 9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H 10#define _ASM_SN_IO_H
11 11
12#if defined (CONFIG_SGI_IP27) 12#if defined(CONFIG_SGI_IP27)
13#include <asm/sn/sn0/hubio.h> 13#include <asm/sn/sn0/hubio.h>
14#endif 14#endif
15 15
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
index 0573cbffc104..1327e12e9645 100644
--- a/include/asm-mips/sn/kldir.h
+++ b/include/asm-mips/sn/kldir.h
@@ -140,7 +140,7 @@
140 */ 140 */
141#define SYMMON_STACK_SIZE 0x8000 141#define SYMMON_STACK_SIZE 0x8000
142 142
143#if defined (PROM) 143#if defined(PROM)
144 144
145/* 145/*
146 * These defines are prom version dependent. No code other than the IP27 146 * These defines are prom version dependent. No code other than the IP27
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
index 9e8cc52910f6..b06190093bbc 100644
--- a/include/asm-mips/sn/sn0/addrs.h
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -91,7 +91,7 @@
91 : RAW_NODE_SWIN_BASE(nasid, widget)) 91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ */ 92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \ 93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ */ 95#endif /* __ASSEMBLY__ */
96 96
97/* 97/*
@@ -106,7 +106,7 @@
106#define BWIN_WIDGET_MASK 0x7 106#define BWIN_WIDGET_MASK 0x7
107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
109 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
110 110
111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
@@ -259,7 +259,7 @@
259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
260 * the stack could start at CACHE_ERR_SP_PTR 260 * the stack could start at CACHE_ERR_SP_PTR
261 */ 261 */
262#if defined (HUB_ERR_STS_WAR) 262#if defined(HUB_ERR_STS_WAR)
263#define CACHE_ERR_EFRAME 0x480 263#define CACHE_ERR_EFRAME 0x480
264#else /* HUB_ERR_STS_WAR */ 264#else /* HUB_ERR_STS_WAR */
265#define CACHE_ERR_EFRAME 0x400 265#define CACHE_ERR_EFRAME 0x400
@@ -275,7 +275,7 @@
275 275
276#define _ARCSPROM 276#define _ARCSPROM
277 277
278#if defined (HUB_ERR_STS_WAR) 278#if defined(HUB_ERR_STS_WAR)
279 279
280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR 280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) 281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index ddaf36a1e389..4d43dbb7f8b8 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -194,17 +194,17 @@ extern unsigned int sni_brd_type;
194#define PCIMT_INT_ACKNOWLEDGE 0xba000000 194#define PCIMT_INT_ACKNOWLEDGE 0xba000000
195 195
196/* board specific init functions */ 196/* board specific init functions */
197extern void sni_a20r_init (void); 197extern void sni_a20r_init(void);
198extern void sni_pcit_init (void); 198extern void sni_pcit_init(void);
199extern void sni_rm200_init (void); 199extern void sni_rm200_init(void);
200extern void sni_pcimt_init (void); 200extern void sni_pcimt_init(void);
201 201
202/* board specific irq init functions */ 202/* board specific irq init functions */
203extern void sni_a20r_irq_init (void); 203extern void sni_a20r_irq_init(void);
204extern void sni_pcit_irq_init (void); 204extern void sni_pcit_irq_init(void);
205extern void sni_pcit_cplus_irq_init (void); 205extern void sni_pcit_cplus_irq_init(void);
206extern void sni_rm200_irq_init (void); 206extern void sni_rm200_irq_init(void);
207extern void sni_pcimt_irq_init (void); 207extern void sni_pcimt_irq_init(void);
208 208
209/* timer inits */ 209/* timer inits */
210extern void sni_cpu_time_init(void); 210extern void sni_cpu_time_init(void);
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 480b574e2483..862f161e88b6 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -195,11 +195,11 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
195 195
196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
197 197
198extern void set_handler (unsigned long offset, void *addr, unsigned long len); 198extern void set_handler(unsigned long offset, void *addr, unsigned long len);
199extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); 199extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
200 200
201typedef void (*vi_handler_t)(void); 201typedef void (*vi_handler_t)(void);
202extern void *set_vi_handler (int n, vi_handler_t addr); 202extern void *set_vi_handler(int n, vi_handler_t addr);
203 203
204extern void *set_except_vector(int n, void *addr); 204extern void *set_except_vector(int n, void *addr);
205extern unsigned long ebase; 205extern unsigned long ebase;
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index b80de8e0fbbd..87c68ae76ff8 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -48,7 +48,7 @@
48 48
49typedef unsigned int cycles_t; 49typedef unsigned int cycles_t;
50 50
51static inline cycles_t get_cycles (void) 51static inline cycles_t get_cycles(void)
52{ 52{
53 return read_c0_count(); 53 return read_c0_count();
54} 54}
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index b25511787ee0..017dfb0d75c3 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -391,9 +391,9 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 391
392#define __invoke_copy_to_user(to,from,n) \ 392#define __invoke_copy_to_user(to,from,n) \
393({ \ 393({ \
394 register void __user *__cu_to_r __asm__ ("$4"); \ 394 register void __user *__cu_to_r __asm__("$4"); \
395 register const void *__cu_from_r __asm__ ("$5"); \ 395 register const void *__cu_from_r __asm__("$5"); \
396 register long __cu_len_r __asm__ ("$6"); \ 396 register long __cu_len_r __asm__("$6"); \
397 \ 397 \
398 __cu_to_r = (to); \ 398 __cu_to_r = (to); \
399 __cu_from_r = (from); \ 399 __cu_from_r = (from); \
@@ -495,9 +495,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
495 495
496#define __invoke_copy_from_user(to,from,n) \ 496#define __invoke_copy_from_user(to,from,n) \
497({ \ 497({ \
498 register void *__cu_to_r __asm__ ("$4"); \ 498 register void *__cu_to_r __asm__("$4"); \
499 register const void __user *__cu_from_r __asm__ ("$5"); \ 499 register const void __user *__cu_from_r __asm__("$5"); \
500 register long __cu_len_r __asm__ ("$6"); \ 500 register long __cu_len_r __asm__("$6"); \
501 \ 501 \
502 __cu_to_r = (to); \ 502 __cu_to_r = (to); \
503 __cu_from_r = (from); \ 503 __cu_from_r = (from); \
@@ -518,9 +518,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
518 518
519#define __invoke_copy_from_user_inatomic(to,from,n) \ 519#define __invoke_copy_from_user_inatomic(to,from,n) \
520({ \ 520({ \
521 register void *__cu_to_r __asm__ ("$4"); \ 521 register void *__cu_to_r __asm__("$4"); \
522 register const void __user *__cu_from_r __asm__ ("$5"); \ 522 register const void __user *__cu_from_r __asm__("$5"); \
523 register long __cu_len_r __asm__ ("$6"); \ 523 register long __cu_len_r __asm__("$6"); \
524 \ 524 \
525 __cu_to_r = (to); \ 525 __cu_to_r = (to); \
526 __cu_from_r = (from); \ 526 __cu_from_r = (from); \
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 04:33:49 -0400