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-rw-r--r--include/asm-mips/atomic.h43
-rw-r--r--include/asm-mips/cpu-features.h21
-rw-r--r--include/asm-mips/cpu.h20
-rw-r--r--include/asm-mips/delay.h6
-rw-r--r--include/asm-mips/dsp.h4
-rw-r--r--include/asm-mips/elf.h4
-rw-r--r--include/asm-mips/hazards.h20
-rw-r--r--include/asm-mips/interrupt.h1
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h7
-rw-r--r--include/asm-mips/mach-ip22/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ja/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-rm200/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-yosemite/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mipsregs.h2
-rw-r--r--include/asm-mips/processor.h1
-rw-r--r--include/asm-mips/vr41xx/capcella.h2
-rw-r--r--include/asm-mips/vr41xx/e55.h2
-rw-r--r--include/asm-mips/vr41xx/giu.h2
-rw-r--r--include/asm-mips/vr41xx/mpc30x.h2
-rw-r--r--include/asm-mips/vr41xx/pci.h2
-rw-r--r--include/asm-mips/vr41xx/siu.h2
-rw-r--r--include/asm-mips/vr41xx/tb0219.h2
-rw-r--r--include/asm-mips/vr41xx/tb0226.h2
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h2
-rw-r--r--include/asm-mips/vr41xx/vrc4173.h2
-rw-r--r--include/asm-mips/vr41xx/workpad.h2
29 files changed, 128 insertions, 58 deletions
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 94a95872d727..654b97d3e13a 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -24,10 +24,9 @@
24#define _ASM_ATOMIC_H 24#define _ASM_ATOMIC_H
25 25
26#include <asm/cpu-features.h> 26#include <asm/cpu-features.h>
27#include <asm/interrupt.h>
27#include <asm/war.h> 28#include <asm/war.h>
28 29
29extern spinlock_t atomic_lock;
30
31typedef struct { volatile int counter; } atomic_t; 30typedef struct { volatile int counter; } atomic_t;
32 31
33#define ATOMIC_INIT(i) { (i) } 32#define ATOMIC_INIT(i) { (i) }
@@ -85,9 +84,9 @@ static __inline__ void atomic_add(int i, atomic_t * v)
85 } else { 84 } else {
86 unsigned long flags; 85 unsigned long flags;
87 86
88 spin_lock_irqsave(&atomic_lock, flags); 87 local_irq_save(flags);
89 v->counter += i; 88 v->counter += i;
90 spin_unlock_irqrestore(&atomic_lock, flags); 89 local_irq_restore(flags);
91 } 90 }
92} 91}
93 92
@@ -127,9 +126,9 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
127 } else { 126 } else {
128 unsigned long flags; 127 unsigned long flags;
129 128
130 spin_lock_irqsave(&atomic_lock, flags); 129 local_irq_save(flags);
131 v->counter -= i; 130 v->counter -= i;
132 spin_unlock_irqrestore(&atomic_lock, flags); 131 local_irq_restore(flags);
133 } 132 }
134} 133}
135 134
@@ -173,11 +172,11 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
173 } else { 172 } else {
174 unsigned long flags; 173 unsigned long flags;
175 174
176 spin_lock_irqsave(&atomic_lock, flags); 175 local_irq_save(flags);
177 result = v->counter; 176 result = v->counter;
178 result += i; 177 result += i;
179 v->counter = result; 178 v->counter = result;
180 spin_unlock_irqrestore(&atomic_lock, flags); 179 local_irq_restore(flags);
181 } 180 }
182 181
183 return result; 182 return result;
@@ -220,11 +219,11 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
220 } else { 219 } else {
221 unsigned long flags; 220 unsigned long flags;
222 221
223 spin_lock_irqsave(&atomic_lock, flags); 222 local_irq_save(flags);
224 result = v->counter; 223 result = v->counter;
225 result -= i; 224 result -= i;
226 v->counter = result; 225 v->counter = result;
227 spin_unlock_irqrestore(&atomic_lock, flags); 226 local_irq_restore(flags);
228 } 227 }
229 228
230 return result; 229 return result;
@@ -277,12 +276,12 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
277 } else { 276 } else {
278 unsigned long flags; 277 unsigned long flags;
279 278
280 spin_lock_irqsave(&atomic_lock, flags); 279 local_irq_save(flags);
281 result = v->counter; 280 result = v->counter;
282 result -= i; 281 result -= i;
283 if (result >= 0) 282 if (result >= 0)
284 v->counter = result; 283 v->counter = result;
285 spin_unlock_irqrestore(&atomic_lock, flags); 284 local_irq_restore(flags);
286 } 285 }
287 286
288 return result; 287 return result;
@@ -433,9 +432,9 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
433 } else { 432 } else {
434 unsigned long flags; 433 unsigned long flags;
435 434
436 spin_lock_irqsave(&atomic_lock, flags); 435 local_irq_save(flags);
437 v->counter += i; 436 v->counter += i;
438 spin_unlock_irqrestore(&atomic_lock, flags); 437 local_irq_restore(flags);
439 } 438 }
440} 439}
441 440
@@ -475,9 +474,9 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
475 } else { 474 } else {
476 unsigned long flags; 475 unsigned long flags;
477 476
478 spin_lock_irqsave(&atomic_lock, flags); 477 local_irq_save(flags);
479 v->counter -= i; 478 v->counter -= i;
480 spin_unlock_irqrestore(&atomic_lock, flags); 479 local_irq_restore(flags);
481 } 480 }
482} 481}
483 482
@@ -521,11 +520,11 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
521 } else { 520 } else {
522 unsigned long flags; 521 unsigned long flags;
523 522
524 spin_lock_irqsave(&atomic_lock, flags); 523 local_irq_save(flags);
525 result = v->counter; 524 result = v->counter;
526 result += i; 525 result += i;
527 v->counter = result; 526 v->counter = result;
528 spin_unlock_irqrestore(&atomic_lock, flags); 527 local_irq_restore(flags);
529 } 528 }
530 529
531 return result; 530 return result;
@@ -568,11 +567,11 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
568 } else { 567 } else {
569 unsigned long flags; 568 unsigned long flags;
570 569
571 spin_lock_irqsave(&atomic_lock, flags); 570 local_irq_save(flags);
572 result = v->counter; 571 result = v->counter;
573 result -= i; 572 result -= i;
574 v->counter = result; 573 v->counter = result;
575 spin_unlock_irqrestore(&atomic_lock, flags); 574 local_irq_restore(flags);
576 } 575 }
577 576
578 return result; 577 return result;
@@ -625,12 +624,12 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
625 } else { 624 } else {
626 unsigned long flags; 625 unsigned long flags;
627 626
628 spin_lock_irqsave(&atomic_lock, flags); 627 local_irq_save(flags);
629 result = v->counter; 628 result = v->counter;
630 result -= i; 629 result -= i;
631 if (result >= 0) 630 if (result >= 0)
632 v->counter = result; 631 v->counter = result;
633 spin_unlock_irqrestore(&atomic_lock, flags); 632 local_irq_restore(flags);
634 } 633 }
635 634
636 return result; 635 return result;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 03627cfb3e45..78c9cc2735d5 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -116,6 +116,27 @@
116#endif 116#endif
117#endif 117#endif
118 118
119# ifndef cpu_has_mips32r1
120# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
121# endif
122# ifndef cpu_has_mips32r2
123# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
124# endif
125# ifndef cpu_has_mips64r1
126# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
127# endif
128# ifndef cpu_has_mips64r2
129# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
130# endif
131
132/*
133 * Shortcuts ...
134 */
135#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
136#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
137#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
138#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
139
119#ifndef cpu_has_dsp 140#ifndef cpu_has_dsp
120#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 141#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
121#endif 142#endif
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 48eac296060f..934e063e79f1 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -204,16 +204,18 @@
204 */ 204 */
205#define MIPS_CPU_ISA_I 0x00000001 205#define MIPS_CPU_ISA_I 0x00000001
206#define MIPS_CPU_ISA_II 0x00000002 206#define MIPS_CPU_ISA_II 0x00000002
207#define MIPS_CPU_ISA_III 0x00008003 207#define MIPS_CPU_ISA_III 0x00000003
208#define MIPS_CPU_ISA_IV 0x00008004 208#define MIPS_CPU_ISA_IV 0x00000004
209#define MIPS_CPU_ISA_V 0x00008005 209#define MIPS_CPU_ISA_V 0x00000005
210#define MIPS_CPU_ISA_M32 0x00000020 210#define MIPS_CPU_ISA_M32R1 0x00000020
211#define MIPS_CPU_ISA_M64 0x00008040 211#define MIPS_CPU_ISA_M32R2 0x00000040
212#define MIPS_CPU_ISA_M64R1 0x00000080
213#define MIPS_CPU_ISA_M64R2 0x00000100
212 214
213/* 215#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
214 * Bit 15 encodes if an ISA level supports 64-bit operations. 216 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
215 */ 217#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
216#define MIPS_CPU_ISA_64BIT 0x00008000 218 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
217 219
218/* 220/*
219 * CPU Option encodings 221 * CPU Option encodings
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index 48d00cccdafa..64dd45150f64 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -52,13 +52,11 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
52 unsigned long lo; 52 unsigned long lo;
53 53
54 /* 54 /*
55 * The common rates of 1000 and 128 are rounded wrongly by the 55 * The rates of 128 is rounded wrongly by the catchall case
56 * catchall case for 64-bit. Excessive precission? Probably ... 56 * for 64-bit. Excessive precission? Probably ...
57 */ 57 */
58#if defined(CONFIG_64BIT) && (HZ == 128) 58#if defined(CONFIG_64BIT) && (HZ == 128)
59 usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ 59 usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
60#elif defined(CONFIG_64BIT) && (HZ == 1000)
61 usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */
62#elif defined(CONFIG_64BIT) 60#elif defined(CONFIG_64BIT)
63 usecs *= (0x8000000000000000UL / (500000 / HZ)); 61 usecs *= (0x8000000000000000UL / (500000 / HZ));
64#else /* 32-bit junk follows here */ 62#else /* 32-bit junk follows here */
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
index 50f556bb4978..e9bfc0813c72 100644
--- a/include/asm-mips/dsp.h
+++ b/include/asm-mips/dsp.h
@@ -16,7 +16,7 @@
16#include <asm/mipsregs.h> 16#include <asm/mipsregs.h>
17 17
18#define DSP_DEFAULT 0x00000000 18#define DSP_DEFAULT 0x00000000
19#define DSP_MASK 0x1f 19#define DSP_MASK 0x3ff
20 20
21#define __enable_dsp_hazard() \ 21#define __enable_dsp_hazard() \
22do { \ 22do { \
@@ -48,6 +48,7 @@ do { \
48 tsk->thread.dsp.dspr[3] = mflo2(); \ 48 tsk->thread.dsp.dspr[3] = mflo2(); \
49 tsk->thread.dsp.dspr[4] = mfhi3(); \ 49 tsk->thread.dsp.dspr[4] = mfhi3(); \
50 tsk->thread.dsp.dspr[5] = mflo3(); \ 50 tsk->thread.dsp.dspr[5] = mflo3(); \
51 tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
51} while (0) 52} while (0)
52 53
53#define save_dsp(tsk) \ 54#define save_dsp(tsk) \
@@ -64,6 +65,7 @@ do { \
64 mtlo2(tsk->thread.dsp.dspr[3]); \ 65 mtlo2(tsk->thread.dsp.dspr[3]); \
65 mthi3(tsk->thread.dsp.dspr[4]); \ 66 mthi3(tsk->thread.dsp.dspr[4]); \
66 mtlo3(tsk->thread.dsp.dspr[5]); \ 67 mtlo3(tsk->thread.dsp.dspr[5]); \
68 wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
67} while (0) 69} while (0)
68 70
69#define restore_dsp(tsk) \ 71#define restore_dsp(tsk) \
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index d2c9a25f8459..851f013adad3 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -277,12 +277,12 @@ do { \
277 277
278struct task_struct; 278struct task_struct;
279 279
280extern void dump_regs(elf_greg_t *, struct pt_regs *regs); 280extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
281extern int dump_task_regs (struct task_struct *, elf_gregset_t *); 281extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
282extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 282extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
283 283
284#define ELF_CORE_COPY_REGS(elf_regs, regs) \ 284#define ELF_CORE_COPY_REGS(elf_regs, regs) \
285 dump_regs((elf_greg_t *)&(elf_regs), regs); 285 elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
286#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) 286#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
287#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 287#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
288 dump_task_fpu(tsk, elf_fpregs) 288 dump_task_fpu(tsk, elf_fpregs)
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 7517189e469f..2fc90632f88c 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -233,15 +233,25 @@ __asm__(
233#endif 233#endif
234 234
235#ifdef CONFIG_CPU_MIPSR2 235#ifdef CONFIG_CPU_MIPSR2
236/*
237 * gcc has a tradition of misscompiling the previous construct using the
238 * address of a label as argument to inline assembler. Gas otoh has the
239 * annoying difference between la and dla which are only usable for 32-bit
240 * rsp. 64-bit code, so can't be used without conditional compilation.
241 * The alterantive is switching the assembler to 64-bit code which happens
242 * to work right even for 32-bit code ...
243 */
236#define instruction_hazard() \ 244#define instruction_hazard() \
237do { \ 245do { \
238__label__ __next; \ 246 unsigned long tmp; \
247 \
239 __asm__ __volatile__( \ 248 __asm__ __volatile__( \
249 " .set mips64r2 \n" \
250 " dla %0, 1f \n" \
240 " jr.hb %0 \n" \ 251 " jr.hb %0 \n" \
241 : \ 252 " .set mips0 \n" \
242 : "r" (&&__next)); \ 253 "1: \n" \
243__next: \ 254 : "=r" (tmp)); \
244 ; \
245} while (0) 255} while (0)
246 256
247#else 257#else
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
index a5735761f5e5..abdf54ee64cf 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/interrupt.h
@@ -93,6 +93,7 @@ __asm__ (
93 " .set noat \n" 93 " .set noat \n"
94#ifdef CONFIG_CPU_MIPSR2 94#ifdef CONFIG_CPU_MIPSR2
95 " di \\result \n" 95 " di \\result \n"
96 " andi \\result, 1 \n"
96#else 97#else
97 " mfc0 \\result, $12 \n" 98 " mfc0 \\result, $12 \n"
98 " ori $1, \\result, 1 \n" 99 " ori $1, \\result, 1 \n"
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 8327ec341c18..8e1d7ed7d8e3 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -838,6 +838,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
838#define UART3_ADDR 0xB1400000 838#define UART3_ADDR 0xB1400000
839 839
840#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 840#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
841#define USB_OHCI_LEN 0x00060000
841#define USB_HOST_CONFIG 0xB4027ffc 842#define USB_HOST_CONFIG 0xB4027ffc
842 843
843#define AU1550_ETH0_BASE 0xB0500000 844#define AU1550_ETH0_BASE 0xB0500000
@@ -1017,10 +1018,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1017 #define I2S_CONTROL_D (1<<1) 1018 #define I2S_CONTROL_D (1<<1)
1018 #define I2S_CONTROL_CE (1<<0) 1019 #define I2S_CONTROL_CE (1<<0)
1019 1020
1020#ifndef CONFIG_SOC_AU1200
1021
1022/* USB Host Controller */ 1021/* USB Host Controller */
1022#ifndef USB_OHCI_LEN
1023#define USB_OHCI_LEN 0x00100000 1023#define USB_OHCI_LEN 0x00100000
1024#endif
1025
1026#ifndef CONFIG_SOC_AU1200
1024 1027
1025/* USB Device Controller */ 1028/* USB Device Controller */
1026#define USBD_EP0RD 0xB0200000 1029#define USBD_EP0RD 0xB0200000
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index ab9714668177..2a37bedb4053 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -34,4 +34,9 @@
34#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 35#define cpu_has_64bits 1
36 36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
37#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */ 42#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index 4c8a90051fd0..2d2f5b91e47f 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 64 37#define cpu_icache_line_size() 64
38#define cpu_scache_line_size() 128 38#define cpu_scache_line_size() 128
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index ab37fc1842ba..b80c30725cf6 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -39,4 +39,9 @@
39#define cpu_has_ic_fills_f_dc 0 39#define cpu_has_ic_fills_f_dc 0
40#define cpu_has_dsp 0 40#define cpu_has_dsp 0
41 41
42#define cpu_has_mips32r1 0
43#define cpu_has_mips32r2 0
44#define cpu_has_mips64r1 0
45#define cpu_has_mips64r2 0
46
42#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ 47#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index a0fde405d4c4..90ff087083b9 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 825c5f674dfc..782b986241dd 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -40,4 +40,9 @@
40#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 32 41#define cpu_scache_line_size() 32
42 42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
43#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 48#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index 79f9b064c864..91e7cf5f2bfe 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -40,4 +40,9 @@
40#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ 41#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
42 42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
43#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */ 48#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 463d051f4683..3073542c93c7 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 80370e0a5589..035ba0a9b0df 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -1059,7 +1059,7 @@ do { \
1059 " .set noat \n" \ 1059 " .set noat \n" \
1060 " move $1, %0 \n" \ 1060 " move $1, %0 \n" \
1061 " # wrdsp $1, %x1 \n" \ 1061 " # wrdsp $1, %x1 \n" \
1062 " .word 0x7c2004f8 | (%x1 << 15) \n" \ 1062 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1063 " .set pop \n" \ 1063 " .set pop \n" \
1064 : \ 1064 : \
1065 : "r" (val), "i" (mask)); \ 1065 : "r" (val), "i" (mask)); \
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index f1980c6c3bcc..de53055a62ae 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -103,7 +103,6 @@ typedef __u32 dspreg_t;
103struct mips_dsp_state { 103struct mips_dsp_state {
104 dspreg_t dspr[NUM_DSP_REGS]; 104 dspreg_t dspr[NUM_DSP_REGS];
105 unsigned int dspcontrol; 105 unsigned int dspcontrol;
106 unsigned short used_dsp;
107}; 106};
108 107
109#define INIT_DSP {{0,},} 108#define INIT_DSP {{0,},}
diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h
index 5b55083c5281..d10ffda50de7 100644
--- a/include/asm-mips/vr41xx/capcella.h
+++ b/include/asm-mips/vr41xx/capcella.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * capcella.h, Include file for ZAO Networks Capcella. 2 * capcella.h, Include file for ZAO Networks Capcella.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h
index ea37b56fc66d..558f2269bf37 100644
--- a/include/asm-mips/vr41xx/e55.h
+++ b/include/asm-mips/vr41xx/e55.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65. 2 * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h
index 8590885a7638..8109cda557dc 100644
--- a/include/asm-mips/vr41xx/giu.h
+++ b/include/asm-mips/vr41xx/giu.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Include file for NEC VR4100 series General-purpose I/O Unit. 2 * Include file for NEC VR4100 series General-purpose I/O Unit.
3 * 3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h
index e6ac3c8e8bae..a6cbe4da6667 100644
--- a/include/asm-mips/vr41xx/mpc30x.h
+++ b/include/asm-mips/vr41xx/mpc30x.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * mpc30x.h, Include file for Victor MP-C303/304. 2 * mpc30x.h, Include file for Victor MP-C303/304.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/pci.h b/include/asm-mips/vr41xx/pci.h
index c473aa78d1d4..6fc01ce19777 100644
--- a/include/asm-mips/vr41xx/pci.h
+++ b/include/asm-mips/vr41xx/pci.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Include file for NEC VR4100 series PCI Control Unit. 2 * Include file for NEC VR4100 series PCI Control Unit.
3 * 3 *
4 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h
index 865cc07ddd7f..1fcf6e8082b4 100644
--- a/include/asm-mips/vr41xx/siu.h
+++ b/include/asm-mips/vr41xx/siu.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Include file for NEC VR4100 series Serial Interface Unit. 2 * Include file for NEC VR4100 series Serial Interface Unit.
3 * 3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h
index 273c6392688f..b318b9612a83 100644
--- a/include/asm-mips/vr41xx/tb0219.h
+++ b/include/asm-mips/vr41xx/tb0219.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * tb0219.h, Include file for TANBAC TB0219. 2 * tb0219.h, Include file for TANBAC TB0219.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * Modified for TANBAC TB0219: 6 * Modified for TANBAC TB0219:
7 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> 7 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h
index 0ff9a60ecacc..2513f450e2d6 100644
--- a/include/asm-mips/vr41xx/tb0226.h
+++ b/include/asm-mips/vr41xx/tb0226.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * tb0226.h, Include file for TANBAC TB0226. 2 * tb0226.h, Include file for TANBAC TB0226.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index bd2723c30901..70828d5fae9c 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -7,7 +7,7 @@
7 * Copyright (C) 2001, 2002 Paul Mundt 7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc. 8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp. 9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 10 * Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
index bb7a85c186e4..4d41a9c091d4 100644
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ b/include/asm-mips/vr41xx/vrc4173.h
@@ -4,7 +4,7 @@
4 * Copyright (C) 2000 Michael R. McDonald 4 * Copyright (C) 2000 Michael R. McDonald
5 * Copyright (C) 2001-2003 Montavista Software Inc. 5 * Copyright (C) 2001-2003 Montavista Software Inc.
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> 6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
7 * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 7 * Copyright (C) 2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
8 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h
index dfe01b43fb79..6bfa9c009a9b 100644
--- a/include/asm-mips/vr41xx/workpad.h
+++ b/include/asm-mips/vr41xx/workpad.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * workpad.h, Include file for IBM WorkPad z50. 2 * workpad.h, Include file for IBM WorkPad z50.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 05:07:28 -0500