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-rw-r--r--include/asm-mips/bootinfo.h7
-rw-r--r--include/asm-mips/lasat/ds1603.h18
-rw-r--r--include/asm-mips/lasat/eeprom.h17
-rw-r--r--include/asm-mips/lasat/head.h22
-rw-r--r--include/asm-mips/lasat/lasat.h253
-rw-r--r--include/asm-mips/lasat/lasatint.h12
-rw-r--r--include/asm-mips/lasat/picvue.h15
-rw-r--r--include/asm-mips/lasat/serial.h13
-rw-r--r--include/asm-mips/mach-lasat/mach-gt64120.h27
-rw-r--r--include/asm-mips/nile4.h310
10 files changed, 0 insertions, 694 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 94fc9be1aab6..075a4d3de326 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -188,13 +188,6 @@
188#define MACH_HP_LASERJET 1 188#define MACH_HP_LASERJET 1
189 189
190/* 190/*
191 * Valid machtype for group LASAT
192 */
193#define MACH_GROUP_LASAT 21
194#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
195#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
196
197/*
198 * Valid machtype for group TITAN 191 * Valid machtype for group TITAN
199 */ 192 */
200#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ 193#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
deleted file mode 100644
index edcd7544b358..000000000000
--- a/include/asm-mips/lasat/ds1603.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#include <asm/addrspace.h>
2
3/* Lasat 100 */
4#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
5#define DS1603_RST_100 (1 << 2)
6#define DS1603_CLK_100 (1 << 0)
7#define DS1603_DATA_SHIFT_100 1
8#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
9
10/* Lasat 200 */
11#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
12#define DS1603_RST_200 (1 << 3)
13#define DS1603_CLK_200 (1 << 4)
14#define DS1603_DATA_200 (1 << 5)
15
16#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
17#define DS1603_DATA_READ_SHIFT_200 9
18#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
deleted file mode 100644
index 7b53edd5cd5f..000000000000
--- a/include/asm-mips/lasat/eeprom.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#include <asm/addrspace.h>
2
3/* lasat 100 */
4#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
5#define AT93C_RDATA_REG_100 AT93C_REG_100
6#define AT93C_RDATA_SHIFT_100 4
7#define AT93C_WDATA_SHIFT_100 4
8#define AT93C_CS_M_100 ( 1 << 5 )
9#define AT93C_CLK_M_100 ( 1 << 3 )
10
11/* lasat 200 */
12#define AT93C_REG_200 KSEG1ADDR(0x11000000)
13#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
14#define AT93C_RDATA_SHIFT_200 8
15#define AT93C_WDATA_SHIFT_200 2
16#define AT93C_CS_M_200 ( 1 << 0 )
17#define AT93C_CLK_M_200 ( 1 << 1 )
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
deleted file mode 100644
index f5589f31a197..000000000000
--- a/include/asm-mips/lasat/head.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Image header stuff
3 */
4#ifndef _HEAD_H
5#define _HEAD_H
6
7#define LASAT_K_MAGIC0_VAL 0xfedeabba
8#define LASAT_K_MAGIC1_VAL 0x00bedead
9
10#ifndef _LANGUAGE_ASSEMBLY
11#include <linux/types.h>
12struct bootloader_header {
13 u32 magic[2];
14 u32 version;
15 u32 image_start;
16 u32 image_size;
17 u32 kernel_start;
18 u32 kernel_entry;
19};
20#endif
21
22#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
deleted file mode 100644
index 42077e367a5b..000000000000
--- a/include/asm-mips/lasat/lasat.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * lasat.h
3 *
4 * Thomas Horsten <thh@lasat.com>
5 * Copyright (C) 2000 LASAT Networks A/S.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Configuration for LASAT boards, loads the appropriate include files.
21 */
22#ifndef _LASAT_H
23#define _LASAT_H
24
25#ifndef _LANGUAGE_ASSEMBLY
26
27extern struct lasat_misc {
28 volatile u32 *reset_reg;
29 volatile u32 *flash_wp_reg;
30 u32 flash_wp_bit;
31} *lasat_misc;
32
33enum lasat_mtdparts {
34 LASAT_MTD_BOOTLOADER,
35 LASAT_MTD_SERVICE,
36 LASAT_MTD_NORMAL,
37 LASAT_MTD_CONFIG,
38 LASAT_MTD_FS,
39 LASAT_MTD_LAST
40};
41
42/*
43 * The format of the data record in the EEPROM.
44 * See Documentation/LASAT/eeprom.txt for a detailed description
45 * of the fields in this struct, and the LASAT Hardware Configuration
46 * field specification for a detailed description of the config
47 * field.
48 */
49#include <linux/types.h>
50
51#define LASAT_EEPROM_VERSION 7
52struct lasat_eeprom_struct {
53 unsigned int version;
54 unsigned int cfg[3];
55 unsigned char hwaddr[6];
56 unsigned char print_partno[12];
57 unsigned char term0;
58 unsigned char print_serial[14];
59 unsigned char term1;
60 unsigned char prod_partno[12];
61 unsigned char term2;
62 unsigned char prod_serial[14];
63 unsigned char term3;
64 unsigned char passwd_hash[16];
65 unsigned char pwdnull;
66 unsigned char vendid;
67 unsigned char ts_ref;
68 unsigned char ts_signoff;
69 unsigned char reserved[11];
70 unsigned char debugaccess;
71 unsigned short prid;
72 unsigned int serviceflag;
73 unsigned int ipaddr;
74 unsigned int netmask;
75 unsigned int crc32;
76};
77
78struct lasat_eeprom_struct_pre7 {
79 unsigned int version;
80 unsigned int flags[3];
81 unsigned char hwaddr0[6];
82 unsigned char hwaddr1[6];
83 unsigned char print_partno[9];
84 unsigned char term0;
85 unsigned char print_serial[14];
86 unsigned char term1;
87 unsigned char prod_partno[9];
88 unsigned char term2;
89 unsigned char prod_serial[14];
90 unsigned char term3;
91 unsigned char passwd_hash[24];
92 unsigned char pwdnull;
93 unsigned char vendor;
94 unsigned char ts_ref;
95 unsigned char ts_signoff;
96 unsigned char reserved[6];
97 unsigned int writecount;
98 unsigned int ipaddr;
99 unsigned int netmask;
100 unsigned int crc32;
101};
102
103/* Configuration descriptor encoding - see the doc for details */
104
105#define LASAT_W0_DSCTYPE(v) ( ( (v) ) & 0xf )
106#define LASAT_W0_BMID(v) ( ( (v) >> 0x04 ) & 0xf )
107#define LASAT_W0_CPUTYPE(v) ( ( (v) >> 0x08 ) & 0xf )
108#define LASAT_W0_BUSSPEED(v) ( ( (v) >> 0x0c ) & 0xf )
109#define LASAT_W0_CPUCLK(v) ( ( (v) >> 0x10 ) & 0xf )
110#define LASAT_W0_SDRAMBANKSZ(v) ( ( (v) >> 0x14 ) & 0xf )
111#define LASAT_W0_SDRAMBANKS(v) ( ( (v) >> 0x18 ) & 0xf )
112#define LASAT_W0_L2CACHE(v) ( ( (v) >> 0x1c ) & 0xf )
113
114#define LASAT_W1_EDHAC(v) ( ( (v) ) & 0xf )
115#define LASAT_W1_HIFN(v) ( ( (v) >> 0x04 ) & 0x1 )
116#define LASAT_W1_ISDN(v) ( ( (v) >> 0x05 ) & 0x1 )
117#define LASAT_W1_IDE(v) ( ( (v) >> 0x06 ) & 0x1 )
118#define LASAT_W1_HDLC(v) ( ( (v) >> 0x07 ) & 0x1 )
119#define LASAT_W1_USVERSION(v) ( ( (v) >> 0x08 ) & 0x1 )
120#define LASAT_W1_4MACS(v) ( ( (v) >> 0x09 ) & 0x1 )
121#define LASAT_W1_EXTSERIAL(v) ( ( (v) >> 0x0a ) & 0x1 )
122#define LASAT_W1_FLASHSIZE(v) ( ( (v) >> 0x0c ) & 0xf )
123#define LASAT_W1_PCISLOTS(v) ( ( (v) >> 0x10 ) & 0xf )
124#define LASAT_W1_PCI1OPT(v) ( ( (v) >> 0x14 ) & 0xf )
125#define LASAT_W1_PCI2OPT(v) ( ( (v) >> 0x18 ) & 0xf )
126#define LASAT_W1_PCI3OPT(v) ( ( (v) >> 0x1c ) & 0xf )
127
128/* Routines specific to LASAT boards */
129
130#define LASAT_BMID_MASQUERADE2 0
131#define LASAT_BMID_MASQUERADEPRO 1
132#define LASAT_BMID_SAFEPIPE25 2
133#define LASAT_BMID_SAFEPIPE50 3
134#define LASAT_BMID_SAFEPIPE100 4
135#define LASAT_BMID_SAFEPIPE5000 5
136#define LASAT_BMID_SAFEPIPE7000 6
137#define LASAT_BMID_SAFEPIPE1000 7
138//#define LASAT_BMID_SAFEPIPE30 7
139//#define LASAT_BMID_SAFEPIPE5100 8
140//#define LASAT_BMID_SAFEPIPE7100 9
141#define LASAT_BMID_UNKNOWN 0xf
142#define LASAT_MAX_BMID_NAMES 9 // no larger than 15!
143
144#define LASAT_HAS_EDHAC ( 1 << 0 )
145#define LASAT_EDHAC_FAST ( 1 << 1 )
146#define LASAT_HAS_EADI ( 1 << 2 )
147#define LASAT_HAS_HIFN ( 1 << 3 )
148#define LASAT_HAS_ISDN ( 1 << 4 )
149#define LASAT_HAS_LEASEDLINE_IF ( 1 << 5 )
150#define LASAT_HAS_HDC ( 1 << 6 )
151
152#define LASAT_PRID_MASQUERADE2 0
153#define LASAT_PRID_MASQUERADEPRO 1
154#define LASAT_PRID_SAFEPIPE25 2
155#define LASAT_PRID_SAFEPIPE50 3
156#define LASAT_PRID_SAFEPIPE100 4
157#define LASAT_PRID_SAFEPIPE5000 5
158#define LASAT_PRID_SAFEPIPE7000 6
159#define LASAT_PRID_SAFEPIPE30 7
160#define LASAT_PRID_SAFEPIPE5100 8
161#define LASAT_PRID_SAFEPIPE7100 9
162
163#define LASAT_PRID_SAFEPIPE1110 10
164#define LASAT_PRID_SAFEPIPE3020 11
165#define LASAT_PRID_SAFEPIPE3030 12
166#define LASAT_PRID_SAFEPIPE5020 13
167#define LASAT_PRID_SAFEPIPE5030 14
168#define LASAT_PRID_SAFEPIPE1120 15
169#define LASAT_PRID_SAFEPIPE1130 16
170#define LASAT_PRID_SAFEPIPE6010 17
171#define LASAT_PRID_SAFEPIPE6110 18
172#define LASAT_PRID_SAFEPIPE6210 19
173#define LASAT_PRID_SAFEPIPE1020 20
174#define LASAT_PRID_SAFEPIPE1040 21
175#define LASAT_PRID_SAFEPIPE1060 22
176
177struct lasat_info {
178 unsigned int li_cpu_hz;
179 unsigned int li_bus_hz;
180 unsigned int li_bmid;
181 unsigned int li_memsize;
182 unsigned int li_flash_size;
183 unsigned int li_prid;
184 unsigned char li_bmstr[16];
185 unsigned char li_namestr[32];
186 unsigned char li_typestr[16];
187 /* Info on the Flash layout */
188 unsigned int li_flash_base;
189 unsigned long li_flashpart_base[LASAT_MTD_LAST];
190 unsigned long li_flashpart_size[LASAT_MTD_LAST];
191 struct lasat_eeprom_struct li_eeprom_info;
192 unsigned int li_eeprom_upgrade_version;
193 unsigned int li_debugaccess;
194};
195
196extern struct lasat_info lasat_board_info;
197
198static inline unsigned long lasat_flash_partition_start(int partno)
199{
200 if (partno < 0 || partno >= LASAT_MTD_LAST)
201 return 0;
202
203 return lasat_board_info.li_flashpart_base[partno];
204}
205
206static inline unsigned long lasat_flash_partition_size(int partno)
207{
208 if (partno < 0 || partno >= LASAT_MTD_LAST)
209 return 0;
210
211 return lasat_board_info.li_flashpart_size[partno];
212}
213
214/* Called from setup() to initialize the global board_info struct */
215extern int lasat_init_board_info(void);
216
217/* Write the modified EEPROM info struct */
218extern void lasat_write_eeprom_info(void);
219
220#define N_MACHTYPES 2
221/* for calibration of delays */
222
223/* the lasat_ndelay function is necessary because it is used at an
224 * early stage of the boot process where ndelay is not calibrated.
225 * It is used for the bit-banging rtc and eeprom drivers */
226
227#include <asm/delay.h>
228/* calculating with the slowest board with 100 MHz clock */
229#define LASAT_100_DIVIDER 20
230/* All 200's run at 250 MHz clock */
231#define LASAT_200_DIVIDER 8
232
233extern unsigned int lasat_ndelay_divider;
234
235static inline void lasat_ndelay(unsigned int ns)
236{
237 __delay(ns / lasat_ndelay_divider);
238}
239
240#endif /* !defined (_LANGUAGE_ASSEMBLY) */
241
242#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
243#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
244
245/* Lasat 100 boards */
246#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
247
248/* Lasat 200 boards */
249#define Vrc5074_PHYS_BASE 0x1fa00000
250#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
251#define PCI_WINDOW1 0x1a000000
252
253#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
deleted file mode 100644
index 065474feeccc..000000000000
--- a/include/asm-mips/lasat/lasatint.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#define LASATINT_END 16
2
3/* lasat 100 */
4#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
5#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
6#define LASATINT_MASK_SHIFT_100 0
7
8/* lasat 200 */
9#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
10#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
11#define LASATINT_MASK_SHIFT_200 16
12
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
deleted file mode 100644
index 42a492edc40e..000000000000
--- a/include/asm-mips/lasat/picvue.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* Lasat 100 */
2#define PVC_REG_100 KSEG1ADDR(0x1c820000)
3#define PVC_DATA_SHIFT_100 0
4#define PVC_DATA_M_100 0xFF
5#define PVC_E_100 (1 << 8)
6#define PVC_RW_100 (1 << 9)
7#define PVC_RS_100 (1 << 10)
8
9/* Lasat 200 */
10#define PVC_REG_200 KSEG1ADDR(0x11000000)
11#define PVC_DATA_SHIFT_200 24
12#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
13#define PVC_E_200 (1 << 16)
14#define PVC_RW_200 (1 << 17)
15#define PVC_RS_200 (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
deleted file mode 100644
index 9e88c7669c7a..000000000000
--- a/include/asm-mips/lasat/serial.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#include <asm/lasat/lasat.h>
2
3/* Lasat 100 boards serial configuration */
4#define LASAT_BASE_BAUD_100 ( 7372800 / 16 )
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8
8
9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
deleted file mode 100644
index 1a9ad45cc135..000000000000
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
9#define _ASM_GT64120_LASAT_GT64120_DEP_H
10
11/*
12 * GT64120 config space base address on Lasat 100
13 */
14#define GT64120_BASE (KSEG1ADDR(0x14000000))
15
16/*
17 * PCI Bus allocation
18 *
19 * (Guessing ...)
20 */
21#define GT_PCI_MEM_BASE 0x12000000UL
22#define GT_PCI_MEM_SIZE 0x02000000UL
23#define GT_PCI_IO_BASE 0x10000000UL
24#define GT_PCI_IO_SIZE 0x02000000UL
25#define GT_ISA_IO_BASE PCI_IO_BASE
26
27#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
deleted file mode 100644
index c3ca959aa4d9..000000000000
--- a/include/asm-mips/nile4.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*
2 * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * This file is based on the following documentation:
8 *
9 * NEC Vrc 5074 System Controller Data Sheet, June 1998
10 */
11
12#ifndef _ASM_NILE4_H
13#define _ASM_NILE4_H
14
15#define NILE4_BASE 0xbfa00000
16#define NILE4_SIZE 0x00200000 /* 2 MB */
17
18
19 /*
20 * Physical Device Address Registers (PDARs)
21 */
22
23#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
24#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
25#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
26#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
27#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
28#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
29#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
30#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
31#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
32#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
33#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
34#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
35 /* [R/W] */
36#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
37
38
39 /*
40 * CPU Interface Registers
41 */
42
43#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
44#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
45#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
46#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
47 /* Enable [R/W] */
48#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
49#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
50
51
52 /*
53 * Memory-Interface Registers
54 */
55
56#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
57#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
58#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
59
60
61 /*
62 * PCI-Bus Registers
63 */
64
65#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
66#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
67#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
68#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
69#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
70
71
72 /*
73 * Local-Bus Registers
74 */
75
76#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
77#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
78#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
79#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
80#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
81#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
82#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
83#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
84#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
85 /* Enables [R/W] */
86#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
87#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
88
89
90 /*
91 * DMA Registers
92 */
93
94#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
95#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
96#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
97#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
98#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
99#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
100
101
102 /*
103 * Timer Registers
104 */
105
106#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
107#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
108#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
109#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
110#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
111#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
112#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
113#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
114
115
116 /*
117 * PCI Configuration Space Registers
118 */
119
120#define NILE4_PCI_BASE 0x0200
121
122#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
123#define NILE4_DID 0x0202 /* PCI Device ID [R] */
124#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
125#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
126#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
127#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
128#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
129#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
130#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
131#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
132#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
133#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
134#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
135#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
136 /* (unimplemented) */
137#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
138#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
139#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
140 /* (unimplemented) */
141#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
142#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
143#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
144#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
145#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
146#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
147#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
148#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
149#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
150#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
151#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
152#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
153
154
155 /*
156 * Serial-Port Registers
157 */
158
159#define NILE4_UART_BASE 0x0300
160
161#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
162#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
163#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
164#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
165#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
166#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
167#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
168#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
169#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
170#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
171#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
172#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
173
174#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
175
176
177 /*
178 * Interrupt Lines
179 */
180
181#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
182#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
183#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
184#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
185#define NILE4_INT_UART 4 /* UART Interrupt */
186#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
187#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
188#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
189#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
190#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
191#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
192#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
193#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
194#define NILE4_INT_RESV 13 /* Reserved */
195#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
196#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
197
198
199 /*
200 * Nile 4 Register Access
201 */
202
203static inline void nile4_sync(void)
204{
205 volatile u32 *p = (volatile u32 *)0xbfc00000;
206 (void)(*p);
207}
208
209static inline void nile4_out32(u32 offset, u32 val)
210{
211 *(volatile u32 *)(NILE4_BASE+offset) = val;
212 nile4_sync();
213}
214
215static inline u32 nile4_in32(u32 offset)
216{
217 u32 val = *(volatile u32 *)(NILE4_BASE+offset);
218 nile4_sync();
219 return val;
220}
221
222static inline void nile4_out16(u32 offset, u16 val)
223{
224 *(volatile u16 *)(NILE4_BASE+offset) = val;
225 nile4_sync();
226}
227
228static inline u16 nile4_in16(u32 offset)
229{
230 u16 val = *(volatile u16 *)(NILE4_BASE+offset);
231 nile4_sync();
232 return val;
233}
234
235static inline void nile4_out8(u32 offset, u8 val)
236{
237 *(volatile u8 *)(NILE4_BASE+offset) = val;
238 nile4_sync();
239}
240
241static inline u8 nile4_in8(u32 offset)
242{
243 u8 val = *(volatile u8 *)(NILE4_BASE+offset);
244 nile4_sync();
245 return val;
246}
247
248
249 /*
250 * Physical Device Address Registers
251 */
252
253extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
254 int on_memory_bus, int visible);
255
256
257 /*
258 * PCI Master Registers
259 */
260
261#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
262#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
263#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
264#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
265
266
267 /*
268 * PCI Address Spaces
269 *
270 * Note that these are multiplexed using PCIINIT[01]!
271 */
272
273#define NILE4_PCI_IO_BASE 0xa6000000
274#define NILE4_PCI_MEM_BASE 0xa8000000
275#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
276#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
277
278
279extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
280
281
282 /*
283 * Interrupt Programming
284 */
285
286#define NUM_I8259_INTERRUPTS 16
287#define NUM_NILE4_INTERRUPTS 16
288
289#define IRQ_I8259_CASCADE NILE4_INT_INTE
290#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
291#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
292#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
293
294extern void nile4_map_irq(int nile4_irq, int cpu_irq);
295extern void nile4_map_irq_all(int cpu_irq);
296extern void nile4_enable_irq(unsigned int nile4_irq);
297extern void nile4_disable_irq(unsigned int nile4_irq);
298extern void nile4_disable_irq_all(void);
299extern u16 nile4_get_irq_stat(int cpu_irq);
300extern void nile4_enable_irq_output(int cpu_irq);
301extern void nile4_disable_irq_output(int cpu_irq);
302extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
303extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
304extern void nile4_clear_irq(int nile4_irq);
305extern void nile4_clear_irq_mask(u32 mask);
306extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void); /* Debug */
308
309#endif
310
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