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-rw-r--r--include/asm-mips/apm.h1
-rw-r--r--include/asm-mips/atomic.h2
-rw-r--r--include/asm-mips/bitops.h2
-rw-r--r--include/asm-mips/cpu-features.h10
-rw-r--r--include/asm-mips/cpu.h2
-rw-r--r--include/asm-mips/inst.h2
-rw-r--r--include/asm-mips/irqflags.h (renamed from include/asm-mips/interrupt.h)70
-rw-r--r--include/asm-mips/mach-cobalt/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-dec/mc146818rtc.h2
-rw-r--r--include/asm-mips/mach-excite/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-excite/excite.h1
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-ja/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-mips/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-sibyte/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-sim/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/mach-yosemite/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mipsregs.h4
-rw-r--r--include/asm-mips/page.h12
-rw-r--r--include/asm-mips/system.h5
-rw-r--r--include/asm-mips/time.h4
-rw-r--r--include/asm-mips/unistd.h18
-rw-r--r--include/asm-mips/vr41xx/capcella.h2
-rw-r--r--include/asm-mips/vr41xx/cmbvr4133.h6
-rw-r--r--include/asm-mips/vr41xx/e55.h43
-rw-r--r--include/asm-mips/vr41xx/irq.h101
-rw-r--r--include/asm-mips/vr41xx/mpc30x.h2
-rw-r--r--include/asm-mips/vr41xx/tb0219.h2
-rw-r--r--include/asm-mips/vr41xx/tb0226.h2
-rw-r--r--include/asm-mips/vr41xx/tb0287.h2
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h53
-rw-r--r--include/asm-mips/vr41xx/vrc4173.h221
-rw-r--r--include/asm-mips/vr41xx/workpad.h43
34 files changed, 186 insertions, 448 deletions
diff --git a/include/asm-mips/apm.h b/include/asm-mips/apm.h
index e8c69208f63a..4b99ffc11529 100644
--- a/include/asm-mips/apm.h
+++ b/include/asm-mips/apm.h
@@ -13,7 +13,6 @@
13#ifndef MIPS_ASM_SA1100_APM_H 13#ifndef MIPS_ASM_SA1100_APM_H
14#define MIPS_ASM_SA1100_APM_H 14#define MIPS_ASM_SA1100_APM_H
15 15
16#include <linux/config.h>
17#include <linux/apm_bios.h> 16#include <linux/apm_bios.h>
18 17
19/* 18/*
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 13d44e14025a..e64abc0d8221 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -22,8 +22,8 @@
22#ifndef _ASM_ATOMIC_H 22#ifndef _ASM_ATOMIC_H
23#define _ASM_ATOMIC_H 23#define _ASM_ATOMIC_H
24 24
25#include <linux/irqflags.h>
25#include <asm/cpu-features.h> 26#include <asm/cpu-features.h>
26#include <asm/interrupt.h>
27#include <asm/war.h> 27#include <asm/war.h>
28 28
29typedef struct { volatile int counter; } atomic_t; 29typedef struct { volatile int counter; } atomic_t;
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 098cec263681..1bb89c5a10ee 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -31,7 +31,7 @@
31 31
32#ifdef __KERNEL__ 32#ifdef __KERNEL__
33 33
34#include <asm/interrupt.h> 34#include <linux/irqflags.h>
35#include <asm/sgidefs.h> 35#include <asm/sgidefs.h>
36#include <asm/war.h> 36#include <asm/war.h>
37 37
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 44285a9d5520..eadca266f159 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -143,12 +143,8 @@
143#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 143#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
144#endif 144#endif
145 145
146#ifdef CONFIG_MIPS_MT
147#ifndef cpu_has_mipsmt 146#ifndef cpu_has_mipsmt
148# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 147#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
149#endif
150#else
151# define cpu_has_mipsmt 0
152#endif 148#endif
153 149
154#ifdef CONFIG_32BIT 150#ifdef CONFIG_32BIT
@@ -199,8 +195,8 @@
199# define cpu_has_veic 0 195# define cpu_has_veic 0
200#endif 196#endif
201 197
202#ifndef cpu_has_subset_pcaches 198#ifndef cpu_has_inclusive_pcaches
203#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) 199#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
204#endif 200#endif
205 201
206#ifndef cpu_dcache_line_size 202#ifndef cpu_dcache_line_size
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dff2a0a52f8f..d38fdbf845b2 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -242,7 +242,7 @@
242#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ 242#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
243#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ 243#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
244#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ 244#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
245#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ 245#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */
246#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 246#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
247#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 247#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
248#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 248#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index 1ed8d0f62577..6489f00731ca 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -74,7 +74,7 @@ enum spec3_op {
74 ins_op, dinsm_op, dinsu_op, dins_op, 74 ins_op, dinsm_op, dinsu_op, dins_op,
75 bshfl_op = 0x20, 75 bshfl_op = 0x20,
76 dbshfl_op = 0x24, 76 dbshfl_op = 0x24,
77 rdhwr_op = 0x3f 77 rdhwr_op = 0x3b
78}; 78};
79 79
80/* 80/*
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/irqflags.h
index a99d6867510f..43ca09a3a3d0 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/irqflags.h
@@ -8,13 +8,15 @@
8 * Copyright (C) 1999 Silicon Graphics 8 * Copyright (C) 1999 Silicon Graphics
9 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */ 10 */
11#ifndef _ASM_INTERRUPT_H 11#ifndef _ASM_IRQFLAGS_H
12#define _ASM_INTERRUPT_H 12#define _ASM_IRQFLAGS_H
13
14#ifndef __ASSEMBLY__
13 15
14#include <asm/hazards.h> 16#include <asm/hazards.h>
15 17
16__asm__ ( 18__asm__ (
17 " .macro local_irq_enable \n" 19 " .macro raw_local_irq_enable \n"
18 " .set push \n" 20 " .set push \n"
19 " .set reorder \n" 21 " .set reorder \n"
20 " .set noat \n" 22 " .set noat \n"
@@ -35,10 +37,10 @@ __asm__ (
35 " .set pop \n" 37 " .set pop \n"
36 " .endm"); 38 " .endm");
37 39
38static inline void local_irq_enable(void) 40static inline void raw_local_irq_enable(void)
39{ 41{
40 __asm__ __volatile__( 42 __asm__ __volatile__(
41 "local_irq_enable" 43 "raw_local_irq_enable"
42 : /* no outputs */ 44 : /* no outputs */
43 : /* no inputs */ 45 : /* no inputs */
44 : "memory"); 46 : "memory");
@@ -63,7 +65,7 @@ static inline void local_irq_enable(void)
63 * Workaround: mask EXL bit of the result or place a nop before mfc0. 65 * Workaround: mask EXL bit of the result or place a nop before mfc0.
64 */ 66 */
65__asm__ ( 67__asm__ (
66 " .macro local_irq_disable\n" 68 " .macro raw_local_irq_disable\n"
67 " .set push \n" 69 " .set push \n"
68 " .set noat \n" 70 " .set noat \n"
69#ifdef CONFIG_MIPS_MT_SMTC 71#ifdef CONFIG_MIPS_MT_SMTC
@@ -84,17 +86,17 @@ __asm__ (
84 " .set pop \n" 86 " .set pop \n"
85 " .endm \n"); 87 " .endm \n");
86 88
87static inline void local_irq_disable(void) 89static inline void raw_local_irq_disable(void)
88{ 90{
89 __asm__ __volatile__( 91 __asm__ __volatile__(
90 "local_irq_disable" 92 "raw_local_irq_disable"
91 : /* no outputs */ 93 : /* no outputs */
92 : /* no inputs */ 94 : /* no inputs */
93 : "memory"); 95 : "memory");
94} 96}
95 97
96__asm__ ( 98__asm__ (
97 " .macro local_save_flags flags \n" 99 " .macro raw_local_save_flags flags \n"
98 " .set push \n" 100 " .set push \n"
99 " .set reorder \n" 101 " .set reorder \n"
100#ifdef CONFIG_MIPS_MT_SMTC 102#ifdef CONFIG_MIPS_MT_SMTC
@@ -105,13 +107,13 @@ __asm__ (
105 " .set pop \n" 107 " .set pop \n"
106 " .endm \n"); 108 " .endm \n");
107 109
108#define local_save_flags(x) \ 110#define raw_local_save_flags(x) \
109__asm__ __volatile__( \ 111__asm__ __volatile__( \
110 "local_save_flags %0" \ 112 "raw_local_save_flags %0" \
111 : "=r" (x)) 113 : "=r" (x))
112 114
113__asm__ ( 115__asm__ (
114 " .macro local_irq_save result \n" 116 " .macro raw_local_irq_save result \n"
115 " .set push \n" 117 " .set push \n"
116 " .set reorder \n" 118 " .set reorder \n"
117 " .set noat \n" 119 " .set noat \n"
@@ -135,15 +137,15 @@ __asm__ (
135 " .set pop \n" 137 " .set pop \n"
136 " .endm \n"); 138 " .endm \n");
137 139
138#define local_irq_save(x) \ 140#define raw_local_irq_save(x) \
139__asm__ __volatile__( \ 141__asm__ __volatile__( \
140 "local_irq_save\t%0" \ 142 "raw_local_irq_save\t%0" \
141 : "=r" (x) \ 143 : "=r" (x) \
142 : /* no inputs */ \ 144 : /* no inputs */ \
143 : "memory") 145 : "memory")
144 146
145__asm__ ( 147__asm__ (
146 " .macro local_irq_restore flags \n" 148 " .macro raw_local_irq_restore flags \n"
147 " .set push \n" 149 " .set push \n"
148 " .set noreorder \n" 150 " .set noreorder \n"
149 " .set noat \n" 151 " .set noat \n"
@@ -182,40 +184,42 @@ __asm__ (
182 " .set pop \n" 184 " .set pop \n"
183 " .endm \n"); 185 " .endm \n");
184 186
185#define local_irq_restore(flags) \ 187#define raw_local_irq_restore(flags) \
186do { \ 188do { \
187 unsigned long __tmp1; \ 189 unsigned long __tmp1; \
188 \ 190 \
189 __asm__ __volatile__( \ 191 __asm__ __volatile__( \
190 "local_irq_restore\t%0" \ 192 "raw_local_irq_restore\t%0" \
191 : "=r" (__tmp1) \ 193 : "=r" (__tmp1) \
192 : "0" (flags) \ 194 : "0" (flags) \
193 : "memory"); \ 195 : "memory"); \
194} while(0) 196} while(0)
195 197
196static inline int irqs_disabled(void) 198static inline int raw_irqs_disabled_flags(unsigned long flags)
197{ 199{
198#ifdef CONFIG_MIPS_MT_SMTC 200#ifdef CONFIG_MIPS_MT_SMTC
199 /* 201 /*
200 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU 202 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
201 */ 203 */
202 unsigned long __result; 204 return flags & 0x400;
203
204 __asm__ __volatile__(
205 " .set noreorder \n"
206 " mfc0 %0, $2, 1 \n"
207 " andi %0, 0x400 \n"
208 " slt %0, $0, %0 \n"
209 " .set reorder \n"
210 : "=r" (__result));
211
212 return __result;
213#else 205#else
214 unsigned long flags;
215 local_save_flags(flags);
216
217 return !(flags & 1); 206 return !(flags & 1);
218#endif 207#endif
219} 208}
220 209
221#endif /* _ASM_INTERRUPT_H */ 210#endif
211
212/*
213 * Do the CPU's IRQ-state tracing from assembly code.
214 */
215#ifdef CONFIG_TRACE_IRQFLAGS
216# define TRACE_IRQS_ON \
217 jal trace_hardirqs_on
218# define TRACE_IRQS_OFF \
219 jal trace_hardirqs_off
220#else
221# define TRACE_IRQS_ON
222# define TRACE_IRQS_OFF
223#endif
224
225#endif /* _ASM_IRQFLAGS_H */
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
index e0e08fc5d7f7..c6dfa59d1986 100644
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
@@ -27,7 +27,7 @@
27#define cpu_has_mcheck 0 27#define cpu_has_mcheck 0
28#define cpu_has_ejtag 0 28#define cpu_has_ejtag 0
29 29
30#define cpu_has_subset_pcaches 0 30#define cpu_has_inclusive_pcaches 0
31#define cpu_dcache_line_size() 32 31#define cpu_dcache_line_size() 32
32#define cpu_icache_line_size() 32 32#define cpu_icache_line_size() 32
33#define cpu_scache_line_size() 0 33#define cpu_scache_line_size() 0
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
index 6d37a5675803..6724e99e43e1 100644
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ b/include/asm-mips/mach-dec/mc146818rtc.h
@@ -19,6 +19,8 @@
19 19
20extern volatile u8 *dec_rtc_base; 20extern volatile u8 *dec_rtc_base;
21 21
22#define ARCH_RTC_LOCATION
23
22#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base) 24#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
23#define RTC_IO_EXTENT dec_kn_slot_size 25#define RTC_IO_EXTENT dec_kn_slot_size
24#define RTC_IOMAPPED 0 26#define RTC_IOMAPPED 0
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h
index abb76b2fd865..0d31854222f9 100644
--- a/include/asm-mips/mach-excite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h
@@ -31,7 +31,7 @@
31#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1 32#define cpu_has_64bits 1
33 33
34#define cpu_has_subset_pcaches 0 34#define cpu_has_inclusive_pcaches 0
35 35
36#define cpu_dcache_line_size() 32 36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
index c52610de2b3a..130bd4b8edce 100644
--- a/include/asm-mips/mach-excite/excite.h
+++ b/include/asm-mips/mach-excite/excite.h
@@ -1,7 +1,6 @@
1#ifndef __EXCITE_H__ 1#ifndef __EXCITE_H__
2#define __EXCITE_H__ 2#define __EXCITE_H__
3 3
4#include <linux/config.h>
5#include <linux/init.h> 4#include <linux/init.h>
6#include <asm/addrspace.h> 5#include <asm/addrspace.h>
7#include <asm/types.h> 6#include <asm/types.h>
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index 19c2d135985b..a071974b67bb 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -34,7 +34,7 @@
34#define cpu_has_4kex 1 34#define cpu_has_4kex 1
35#define cpu_has_4k_cache 1 35#define cpu_has_4k_cache 1
36 36
37#define cpu_has_subset_pcaches 1 37#define cpu_has_inclusive_pcaches 1
38 38
39#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 64 40#define cpu_icache_line_size() 64
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index 90ff087083b9..84b6dead0e8a 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -31,7 +31,7 @@
31#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1 32#define cpu_has_64bits 1
33 33
34#define cpu_has_subset_pcaches 0 34#define cpu_has_inclusive_pcaches 0
35 35
36#define cpu_dcache_line_size() 32 36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index e960679f54ba..7f3e3f9bd23a 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -39,7 +39,7 @@
39#define cpu_has_nofpuex 0 39#define cpu_has_nofpuex 0
40/* #define cpu_has_64bits ? */ 40/* #define cpu_has_64bits ? */
41/* #define cpu_has_64bit_zero_reg ? */ 41/* #define cpu_has_64bit_zero_reg ? */
42/* #define cpu_has_subset_pcaches ? */ 42/* #define cpu_has_inclusive_pcaches ? */
43#define cpu_icache_snoops_remote_store 1 43#define cpu_icache_snoops_remote_store 1
44#endif 44#endif
45 45
@@ -65,7 +65,7 @@
65#define cpu_has_nofpuex 0 65#define cpu_has_nofpuex 0
66/* #define cpu_has_64bits ? */ 66/* #define cpu_has_64bits ? */
67/* #define cpu_has_64bit_zero_reg ? */ 67/* #define cpu_has_64bit_zero_reg ? */
68/* #define cpu_has_subset_pcaches ? */ 68/* #define cpu_has_inclusive_pcaches ? */
69#define cpu_icache_snoops_remote_store 1 69#define cpu_icache_snoops_remote_store 1
70#endif 70#endif
71 71
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 782b986241dd..57a12ded0613 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -34,7 +34,7 @@
34#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 35#define cpu_has_64bits 1
36 36
37#define cpu_has_subset_pcaches 0 37#define cpu_has_inclusive_pcaches 0
38 38
39#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
index 193a666cd131..a25968f277a2 100644
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -31,7 +31,7 @@
31#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1 32#define cpu_has_64bits 1
33 33
34#define cpu_has_subset_pcaches 0 34#define cpu_has_inclusive_pcaches 0
35 35
36#define cpu_dcache_line_size() 32 36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h
index d736bdadb6df..779b02205737 100644
--- a/include/asm-mips/mach-sim/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -34,7 +34,7 @@
34#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
35/* #define cpu_has_64bits ? */ 35/* #define cpu_has_64bits ? */
36/* #define cpu_has_64bit_zero_reg ? */ 36/* #define cpu_has_64bit_zero_reg ? */
37/* #define cpu_has_subset_pcaches ? */ 37/* #define cpu_has_inclusive_pcaches ? */
38#endif 38#endif
39 39
40#ifdef CONFIG_CPU_MIPS64 40#ifdef CONFIG_CPU_MIPS64
@@ -59,7 +59,7 @@
59#define cpu_has_nofpuex 0 59#define cpu_has_nofpuex 0
60/* #define cpu_has_64bits ? */ 60/* #define cpu_has_64bits ? */
61/* #define cpu_has_64bit_zero_reg ? */ 61/* #define cpu_has_64bit_zero_reg ? */
62/* #define cpu_has_subset_pcaches ? */ 62/* #define cpu_has_inclusive_pcaches ? */
63#endif 63#endif
64 64
65#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ 65#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 3073542c93c7..42cebb7ce7a6 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -31,7 +31,7 @@
31#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1 32#define cpu_has_64bits 1
33 33
34#define cpu_has_subset_pcaches 0 34#define cpu_has_inclusive_pcaches 0
35 35
36#define cpu_dcache_line_size() 32 36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9192d76c133d..1f318d707998 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -470,6 +470,8 @@
470 470
471/* Bits specific to the VR41xx. */ 471/* Bits specific to the VR41xx. */
472#define VR41_CONF_CS (_ULCAST_(1) << 12) 472#define VR41_CONF_CS (_ULCAST_(1) << 12)
473#define VR41_CONF_P4K (_ULCAST_(1) << 13)
474#define VR41_CONF_BP (_ULCAST_(1) << 16)
473#define VR41_CONF_M16 (_ULCAST_(1) << 20) 475#define VR41_CONF_M16 (_ULCAST_(1) << 20)
474#define VR41_CONF_AD (_ULCAST_(1) << 23) 476#define VR41_CONF_AD (_ULCAST_(1) << 23)
475 477
@@ -1416,7 +1418,7 @@ change_c0_##name(unsigned int change, unsigned int new) \
1416 1418
1417#else /* SMTC versions that manage MT scheduling */ 1419#else /* SMTC versions that manage MT scheduling */
1418 1420
1419#include <asm/interrupt.h> 1421#include <linux/irqflags.h>
1420 1422
1421/* 1423/*
1422 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1424 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 6b97744f00cd..6ed1151a05a3 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -138,16 +138,14 @@ typedef struct { unsigned long pgprot; } pgprot_t;
138 138
139#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 139#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
140 140
141#ifndef CONFIG_SPARSEMEM
142#ifndef CONFIG_NEED_MULTIPLE_NODES
143#define pfn_valid(pfn) ((pfn) < max_mapnr)
144#endif
145#endif
146
147#ifdef CONFIG_FLATMEM 141#ifdef CONFIG_FLATMEM
148 142
149#define pfn_valid(pfn) ((pfn) < max_mapnr) 143#define pfn_valid(pfn) ((pfn) < max_mapnr)
150 144
145#elif defined(CONFIG_SPARSEMEM)
146
147/* pfn_valid is defined in linux/mmzone.h */
148
151#elif defined(CONFIG_NEED_MULTIPLE_NODES) 149#elif defined(CONFIG_NEED_MULTIPLE_NODES)
152 150
153#define pfn_valid(pfn) \ 151#define pfn_valid(pfn) \
@@ -159,8 +157,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
159 : 0); \ 157 : 0); \
160}) 158})
161 159
162#else
163#error Provide a definition of pfn_valid
164#endif 160#endif
165 161
166#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 162#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 130333d7c4ee..dcb4701d5728 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -13,13 +13,13 @@
13#define _ASM_SYSTEM_H 13#define _ASM_SYSTEM_H
14 14
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/irqflags.h>
16 17
17#include <asm/addrspace.h> 18#include <asm/addrspace.h>
18#include <asm/cpu-features.h> 19#include <asm/cpu-features.h>
19#include <asm/dsp.h> 20#include <asm/dsp.h>
20#include <asm/ptrace.h> 21#include <asm/ptrace.h>
21#include <asm/war.h> 22#include <asm/war.h>
22#include <asm/interrupt.h>
23 23
24/* 24/*
25 * read_barrier_depends - Flush all pending reads that subsequents reads 25 * read_barrier_depends - Flush all pending reads that subsequents reads
@@ -143,9 +143,6 @@
143#define set_mb(var, value) \ 143#define set_mb(var, value) \
144do { var = value; mb(); } while (0) 144do { var = value; mb(); } while (0)
145 145
146#define set_wmb(var, value) \
147do { var = value; wmb(); } while (0)
148
149/* 146/*
150 * switch_to(n) should switch tasks to task nr n, first 147 * switch_to(n) should switch tasks to task nr n, first
151 * checking that n isn't the current task, in which case it does nothing. 148 * checking that n isn't the current task, in which case it does nothing.
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index d897c8bb554d..2d543735668b 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -83,11 +83,11 @@ extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
83/* 83/*
84 * board specific routines required by time_init(). 84 * board specific routines required by time_init().
85 * board_time_init is defaulted to NULL and can remain so. 85 * board_time_init is defaulted to NULL and can remain so.
86 * board_timer_setup must be setup properly in machine setup routine. 86 * plat_timer_setup must be setup properly in machine setup routine.
87 */ 87 */
88struct irqaction; 88struct irqaction;
89extern void (*board_time_init)(void); 89extern void (*board_time_init)(void);
90extern void (*board_timer_setup)(struct irqaction *irq); 90extern void plat_timer_setup(struct irqaction *irq);
91 91
92/* 92/*
93 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 93 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 809f9f55bacb..610ccb8a50b3 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -327,16 +327,18 @@
327#define __NR_splice (__NR_Linux + 304) 327#define __NR_splice (__NR_Linux + 304)
328#define __NR_sync_file_range (__NR_Linux + 305) 328#define __NR_sync_file_range (__NR_Linux + 305)
329#define __NR_tee (__NR_Linux + 306) 329#define __NR_tee (__NR_Linux + 306)
330#define __NR_vmsplice (__NR_Linux + 307)
331#define __NR_move_pages (__NR_Linux + 308)
330 332
331/* 333/*
332 * Offset of the last Linux o32 flavoured syscall 334 * Offset of the last Linux o32 flavoured syscall
333 */ 335 */
334#define __NR_Linux_syscalls 306 336#define __NR_Linux_syscalls 308
335 337
336#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 338#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
337 339
338#define __NR_O32_Linux 4000 340#define __NR_O32_Linux 4000
339#define __NR_O32_Linux_syscalls 306 341#define __NR_O32_Linux_syscalls 308
340 342
341#if _MIPS_SIM == _MIPS_SIM_ABI64 343#if _MIPS_SIM == _MIPS_SIM_ABI64
342 344
@@ -610,16 +612,18 @@
610#define __NR_splice (__NR_Linux + 263) 612#define __NR_splice (__NR_Linux + 263)
611#define __NR_sync_file_range (__NR_Linux + 264) 613#define __NR_sync_file_range (__NR_Linux + 264)
612#define __NR_tee (__NR_Linux + 265) 614#define __NR_tee (__NR_Linux + 265)
615#define __NR_vmsplice (__NR_Linux + 266)
616#define __NR_move_pages (__NR_Linux + 267)
613 617
614/* 618/*
615 * Offset of the last Linux 64-bit flavoured syscall 619 * Offset of the last Linux 64-bit flavoured syscall
616 */ 620 */
617#define __NR_Linux_syscalls 265 621#define __NR_Linux_syscalls 267
618 622
619#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 623#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
620 624
621#define __NR_64_Linux 5000 625#define __NR_64_Linux 5000
622#define __NR_64_Linux_syscalls 265 626#define __NR_64_Linux_syscalls 267
623 627
624#if _MIPS_SIM == _MIPS_SIM_NABI32 628#if _MIPS_SIM == _MIPS_SIM_NABI32
625 629
@@ -897,16 +901,18 @@
897#define __NR_splice (__NR_Linux + 267) 901#define __NR_splice (__NR_Linux + 267)
898#define __NR_sync_file_range (__NR_Linux + 268) 902#define __NR_sync_file_range (__NR_Linux + 268)
899#define __NR_tee (__NR_Linux + 269) 903#define __NR_tee (__NR_Linux + 269)
904#define __NR_vmsplice (__NR_Linux + 270)
905#define __NR_move_pages (__NR_Linux + 271)
900 906
901/* 907/*
902 * Offset of the last N32 flavoured syscall 908 * Offset of the last N32 flavoured syscall
903 */ 909 */
904#define __NR_Linux_syscalls 269 910#define __NR_Linux_syscalls 271
905 911
906#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 912#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
907 913
908#define __NR_N32_Linux 6000 914#define __NR_N32_Linux 6000
909#define __NR_N32_Linux_syscalls 269 915#define __NR_N32_Linux_syscalls 271
910 916
911#ifdef __KERNEL__ 917#ifdef __KERNEL__
912 918
diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h
index d10ffda50de7..e0ee05a3dfcc 100644
--- a/include/asm-mips/vr41xx/capcella.h
+++ b/include/asm-mips/vr41xx/capcella.h
@@ -20,7 +20,7 @@
20#ifndef __ZAO_CAPCELLA_H 20#ifndef __ZAO_CAPCELLA_H
21#define __ZAO_CAPCELLA_H 21#define __ZAO_CAPCELLA_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
index 42af389019ea..9490ade58b46 100644
--- a/include/asm-mips/vr41xx/cmbvr4133.h
+++ b/include/asm-mips/vr41xx/cmbvr4133.h
@@ -15,8 +15,7 @@
15#ifndef __NEC_CMBVR4133_H 15#ifndef __NEC_CMBVR4133_H
16#define __NEC_CMBVR4133_H 16#define __NEC_CMBVR4133_H
17 17
18#include <asm/addrspace.h> 18#include <asm/vr41xx/irq.h>
19#include <asm/vr41xx/vr41xx.h>
20 19
21/* 20/*
22 * General-Purpose I/O Pin Number 21 * General-Purpose I/O Pin Number
@@ -55,7 +54,4 @@
55#define IDE_SECONDARY_IRQ I8259_IRQ(15) 54#define IDE_SECONDARY_IRQ I8259_IRQ(15)
56#define I8259_IRQ_LAST IDE_SECONDARY_IRQ 55#define I8259_IRQ_LAST IDE_SECONDARY_IRQ
57 56
58#define RTC_PORT(x) (0xaf000100 + (x))
59#define RTC_IO_EXTENT 0x140
60
61#endif /* __NEC_CMBVR4133_H */ 57#endif /* __NEC_CMBVR4133_H */
diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h
deleted file mode 100644
index 558f2269bf37..000000000000
--- a/include/asm-mips/vr41xx/e55.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65.
3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __CASIO_E55_H
21#define __CASIO_E55_H
22
23#include <asm/addrspace.h>
24#include <asm/vr41xx/vr41xx.h>
25
26/*
27 * Board specific address mapping
28 */
29#define VR41XX_ISA_MEM_BASE 0x10000000
30#define VR41XX_ISA_MEM_SIZE 0x04000000
31
32/* VR41XX_ISA_IO_BASE includes offset from real base. */
33#define VR41XX_ISA_IO_BASE 0x1400c000
34#define VR41XX_ISA_IO_SIZE 0x03ff4000
35
36#define ISA_BUS_IO_BASE 0
37#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE
38
39#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
40#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE
41#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
42
43#endif /* __CASIO_E55_H */
diff --git a/include/asm-mips/vr41xx/irq.h b/include/asm-mips/vr41xx/irq.h
new file mode 100644
index 000000000000..d315dfbc08f2
--- /dev/null
+++ b/include/asm-mips/vr41xx/irq.h
@@ -0,0 +1,101 @@
1/*
2 * include/asm-mips/vr41xx/irq.h
3 *
4 * Interrupt numbers for NEC VR4100 series.
5 *
6 * Copyright (C) 1999 Michael Klar
7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef __NEC_VR41XX_IRQ_H
18#define __NEC_VR41XX_IRQ_H
19
20/*
21 * CPU core Interrupt Numbers
22 */
23#define MIPS_CPU_IRQ_BASE 0
24#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
25#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
26#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
27#define INT0_IRQ MIPS_CPU_IRQ(2)
28#define INT1_IRQ MIPS_CPU_IRQ(3)
29#define INT2_IRQ MIPS_CPU_IRQ(4)
30#define INT3_IRQ MIPS_CPU_IRQ(5)
31#define INT4_IRQ MIPS_CPU_IRQ(6)
32#define TIMER_IRQ MIPS_CPU_IRQ(7)
33
34/*
35 * SYINT1 Interrupt Numbers
36 */
37#define SYSINT1_IRQ_BASE 8
38#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
39#define BATTRY_IRQ SYSINT1_IRQ(0)
40#define POWER_IRQ SYSINT1_IRQ(1)
41#define RTCLONG1_IRQ SYSINT1_IRQ(2)
42#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
43/* RFU */
44#define PIU_IRQ SYSINT1_IRQ(5)
45#define AIU_IRQ SYSINT1_IRQ(6)
46#define KIU_IRQ SYSINT1_IRQ(7)
47#define GIUINT_IRQ SYSINT1_IRQ(8)
48#define SIU_IRQ SYSINT1_IRQ(9)
49#define BUSERR_IRQ SYSINT1_IRQ(10)
50#define SOFTINT_IRQ SYSINT1_IRQ(11)
51#define CLKRUN_IRQ SYSINT1_IRQ(12)
52#define DOZEPIU_IRQ SYSINT1_IRQ(13)
53#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
54
55/*
56 * SYSINT2 Interrupt Numbers
57 */
58#define SYSINT2_IRQ_BASE 24
59#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
60#define RTCLONG2_IRQ SYSINT2_IRQ(0)
61#define LED_IRQ SYSINT2_IRQ(1)
62#define HSP_IRQ SYSINT2_IRQ(2)
63#define TCLOCK_IRQ SYSINT2_IRQ(3)
64#define FIR_IRQ SYSINT2_IRQ(4)
65#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
66#define DSIU_IRQ SYSINT2_IRQ(5)
67#define PCI_IRQ SYSINT2_IRQ(6)
68#define SCU_IRQ SYSINT2_IRQ(7)
69#define CSI_IRQ SYSINT2_IRQ(8)
70#define BCU_IRQ SYSINT2_IRQ(9)
71#define ETHERNET_IRQ SYSINT2_IRQ(10)
72#define SYSINT2_IRQ_LAST ETHERNET_IRQ
73
74/*
75 * GIU Interrupt Numbers
76 */
77#define GIU_IRQ_BASE 40
78#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
79#define GIU_IRQ_LAST GIU_IRQ(31)
80
81/*
82 * VRC4173 Interrupt Numbers
83 */
84#define VRC4173_IRQ_BASE 72
85#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
86#define VRC4173_USB_IRQ VRC4173_IRQ(0)
87#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
88#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
89#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
90#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
91#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
92#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
93#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
94#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
95#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
96#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
97/* RFU */
98#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
99#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
100
101#endif /* __NEC_VR41XX_IRQ_H */
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h
index a6cbe4da6667..1d67df843dc3 100644
--- a/include/asm-mips/vr41xx/mpc30x.h
+++ b/include/asm-mips/vr41xx/mpc30x.h
@@ -20,7 +20,7 @@
20#ifndef __VICTOR_MPC30X_H 20#ifndef __VICTOR_MPC30X_H
21#define __VICTOR_MPC30X_H 21#define __VICTOR_MPC30X_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h
index b318b9612a83..dc981b4be0a4 100644
--- a/include/asm-mips/vr41xx/tb0219.h
+++ b/include/asm-mips/vr41xx/tb0219.h
@@ -23,7 +23,7 @@
23#ifndef __TANBAC_TB0219_H 23#ifndef __TANBAC_TB0219_H
24#define __TANBAC_TB0219_H 24#define __TANBAC_TB0219_H
25 25
26#include <asm/vr41xx/vr41xx.h> 26#include <asm/vr41xx/irq.h>
27 27
28/* 28/*
29 * General-Purpose I/O Pin Number 29 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h
index 2513f450e2d6..de527dcfa5f3 100644
--- a/include/asm-mips/vr41xx/tb0226.h
+++ b/include/asm-mips/vr41xx/tb0226.h
@@ -20,7 +20,7 @@
20#ifndef __TANBAC_TB0226_H 20#ifndef __TANBAC_TB0226_H
21#define __TANBAC_TB0226_H 21#define __TANBAC_TB0226_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0287.h b/include/asm-mips/vr41xx/tb0287.h
index dd9832313afe..61bead68abf0 100644
--- a/include/asm-mips/vr41xx/tb0287.h
+++ b/include/asm-mips/vr41xx/tb0287.h
@@ -22,7 +22,7 @@
22#ifndef __TANBAC_TB0287_H 22#ifndef __TANBAC_TB0287_H
23#define __TANBAC_TB0287_H 23#define __TANBAC_TB0287_H
24 24
25#include <asm/vr41xx/vr41xx.h> 25#include <asm/vr41xx/irq.h>
26 26
27/* 27/*
28 * General-Purpose I/O Pin Number 28 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 70828d5fae9c..dd3eb3dc5886 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -74,59 +74,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
74/* 74/*
75 * Interrupt Control Unit 75 * Interrupt Control Unit
76 */ 76 */
77/* CPU core Interrupt Numbers */
78#define MIPS_CPU_IRQ_BASE 0
79#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
80#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
81#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
82#define INT0_IRQ MIPS_CPU_IRQ(2)
83#define INT1_IRQ MIPS_CPU_IRQ(3)
84#define INT2_IRQ MIPS_CPU_IRQ(4)
85#define INT3_IRQ MIPS_CPU_IRQ(5)
86#define INT4_IRQ MIPS_CPU_IRQ(6)
87#define TIMER_IRQ MIPS_CPU_IRQ(7)
88
89/* SYINT1 Interrupt Numbers */
90#define SYSINT1_IRQ_BASE 8
91#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
92#define BATTRY_IRQ SYSINT1_IRQ(0)
93#define POWER_IRQ SYSINT1_IRQ(1)
94#define RTCLONG1_IRQ SYSINT1_IRQ(2)
95#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
96/* RFU */
97#define PIU_IRQ SYSINT1_IRQ(5)
98#define AIU_IRQ SYSINT1_IRQ(6)
99#define KIU_IRQ SYSINT1_IRQ(7)
100#define GIUINT_IRQ SYSINT1_IRQ(8)
101#define SIU_IRQ SYSINT1_IRQ(9)
102#define BUSERR_IRQ SYSINT1_IRQ(10)
103#define SOFTINT_IRQ SYSINT1_IRQ(11)
104#define CLKRUN_IRQ SYSINT1_IRQ(12)
105#define DOZEPIU_IRQ SYSINT1_IRQ(13)
106#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
107
108/* SYSINT2 Interrupt Numbers */
109#define SYSINT2_IRQ_BASE 24
110#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
111#define RTCLONG2_IRQ SYSINT2_IRQ(0)
112#define LED_IRQ SYSINT2_IRQ(1)
113#define HSP_IRQ SYSINT2_IRQ(2)
114#define TCLOCK_IRQ SYSINT2_IRQ(3)
115#define FIR_IRQ SYSINT2_IRQ(4)
116#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
117#define DSIU_IRQ SYSINT2_IRQ(5)
118#define PCI_IRQ SYSINT2_IRQ(6)
119#define SCU_IRQ SYSINT2_IRQ(7)
120#define CSI_IRQ SYSINT2_IRQ(8)
121#define BCU_IRQ SYSINT2_IRQ(9)
122#define ETHERNET_IRQ SYSINT2_IRQ(10)
123#define SYSINT2_IRQ_LAST ETHERNET_IRQ
124
125/* GIU Interrupt Numbers */
126#define GIU_IRQ_BASE 40
127#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
128#define GIU_IRQ_LAST GIU_IRQ(31)
129
130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); 77extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
131extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); 78extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
132 79
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
deleted file mode 100644
index 96fdcd54cec7..000000000000
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * vrc4173.h, Include file for NEC VRC4173.
3 *
4 * Copyright (C) 2000 Michael R. McDonald
5 * Copyright (C) 2001-2003 Montavista Software Inc.
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
7 * Copyright (C) 2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
8 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __NEC_VRC4173_H
25#define __NEC_VRC4173_H
26
27#include <asm/io.h>
28
29/*
30 * Interrupt Number
31 */
32#define VRC4173_IRQ_BASE 72
33#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
34#define VRC4173_USB_IRQ VRC4173_IRQ(0)
35#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
36#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
37#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
38#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
39#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
40#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
41#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
42#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
43#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
44#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
45/* RFU */
46#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
47#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
48
49/*
50 * PCI I/O accesses
51 */
52#ifdef CONFIG_VRC4173
53
54extern unsigned long vrc4173_io_offset;
55
56#define set_vrc4173_io_offset(offset) do { vrc4173_io_offset = (offset); } while (0)
57
58#define vrc4173_outb(val,port) outb((val), vrc4173_io_offset+(port))
59#define vrc4173_outw(val,port) outw((val), vrc4173_io_offset+(port))
60#define vrc4173_outl(val,port) outl((val), vrc4173_io_offset+(port))
61#define vrc4173_outb_p(val,port) outb_p((val), vrc4173_io_offset+(port))
62#define vrc4173_outw_p(val,port) outw_p((val), vrc4173_io_offset+(port))
63#define vrc4173_outl_p(val,port) outl_p((val), vrc4173_io_offset+(port))
64
65#define vrc4173_inb(port) inb(vrc4173_io_offset+(port))
66#define vrc4173_inw(port) inw(vrc4173_io_offset+(port))
67#define vrc4173_inl(port) inl(vrc4173_io_offset+(port))
68#define vrc4173_inb_p(port) inb_p(vrc4173_io_offset+(port))
69#define vrc4173_inw_p(port) inw_p(vrc4173_io_offset+(port))
70#define vrc4173_inl_p(port) inl_p(vrc4173_io_offset+(port))
71
72#define vrc4173_outsb(port,addr,count) outsb(vrc4173_io_offset+(port),(addr),(count))
73#define vrc4173_outsw(port,addr,count) outsw(vrc4173_io_offset+(port),(addr),(count))
74#define vrc4173_outsl(port,addr,count) outsl(vrc4173_io_offset+(port),(addr),(count))
75
76#define vrc4173_insb(port,addr,count) insb(vrc4173_io_offset+(port),(addr),(count))
77#define vrc4173_insw(port,addr,count) insw(vrc4173_io_offset+(port),(addr),(count))
78#define vrc4173_insl(port,addr,count) insl(vrc4173_io_offset+(port),(addr),(count))
79
80#else
81
82#define set_vrc4173_io_offset(offset) do {} while (0)
83
84#define vrc4173_outb(val,port) do {} while (0)
85#define vrc4173_outw(val,port) do {} while (0)
86#define vrc4173_outl(val,port) do {} while (0)
87#define vrc4173_outb_p(val,port) do {} while (0)
88#define vrc4173_outw_p(val,port) do {} while (0)
89#define vrc4173_outl_p(val,port) do {} while (0)
90
91#define vrc4173_inb(port) 0
92#define vrc4173_inw(port) 0
93#define vrc4173_inl(port) 0
94#define vrc4173_inb_p(port) 0
95#define vrc4173_inw_p(port) 0
96#define vrc4173_inl_p(port) 0
97
98#define vrc4173_outsb(port,addr,count) do {} while (0)
99#define vrc4173_outsw(port,addr,count) do {} while (0)
100#define vrc4173_outsl(port,addr,count) do {} while (0)
101
102#define vrc4173_insb(port,addr,count) do {} while (0)
103#define vrc4173_insw(port,addr,count) do {} while (0)
104#define vrc4173_insl(port,addr,count) do {} while (0)
105
106#endif
107
108/*
109 * Clock Mask Unit
110 */
111typedef enum vrc4173_clock {
112 VRC4173_PIU_CLOCK,
113 VRC4173_KIU_CLOCK,
114 VRC4173_AIU_CLOCK,
115 VRC4173_PS2_CH1_CLOCK,
116 VRC4173_PS2_CH2_CLOCK,
117 VRC4173_USBU_PCI_CLOCK,
118 VRC4173_CARDU1_PCI_CLOCK,
119 VRC4173_CARDU2_PCI_CLOCK,
120 VRC4173_AC97U_PCI_CLOCK,
121 VRC4173_USBU_48MHz_CLOCK,
122 VRC4173_EXT_48MHz_CLOCK,
123 VRC4173_48MHz_CLOCK,
124} vrc4173_clock_t;
125
126#ifdef CONFIG_VRC4173
127
128extern void vrc4173_supply_clock(vrc4173_clock_t clock);
129extern void vrc4173_mask_clock(vrc4173_clock_t clock);
130
131#else
132
133static inline void vrc4173_supply_clock(vrc4173_clock_t clock) {}
134static inline void vrc4173_mask_clock(vrc4173_clock_t clock) {}
135
136#endif
137
138/*
139 * Interupt Control Unit
140 */
141
142#define VRC4173_PIUINT_COMMAND 0x0040
143#define VRC4173_PIUINT_DATA 0x0020
144#define VRC4173_PIUINT_PAGE1 0x0010
145#define VRC4173_PIUINT_PAGE0 0x0008
146#define VRC4173_PIUINT_DATALOST 0x0004
147#define VRC4173_PIUINT_STATUSCHANGE 0x0001
148
149#ifdef CONFIG_VRC4173
150
151extern void vrc4173_enable_piuint(uint16_t mask);
152extern void vrc4173_disable_piuint(uint16_t mask);
153
154#else
155
156static inline void vrc4173_enable_piuint(uint16_t mask) {}
157static inline void vrc4173_disable_piuint(uint16_t mask) {}
158
159#endif
160
161#define VRC4173_AIUINT_INPUT_DMAEND 0x0800
162#define VRC4173_AIUINT_INPUT_DMAHALT 0x0400
163#define VRC4173_AIUINT_INPUT_DATALOST 0x0200
164#define VRC4173_AIUINT_INPUT_DATA 0x0100
165#define VRC4173_AIUINT_OUTPUT_DMAEND 0x0008
166#define VRC4173_AIUINT_OUTPUT_DMAHALT 0x0004
167#define VRC4173_AIUINT_OUTPUT_NODATA 0x0002
168
169#ifdef CONFIG_VRC4173
170
171extern void vrc4173_enable_aiuint(uint16_t mask);
172extern void vrc4173_disable_aiuint(uint16_t mask);
173
174#else
175
176static inline void vrc4173_enable_aiuint(uint16_t mask) {}
177static inline void vrc4173_disable_aiuint(uint16_t mask) {}
178
179#endif
180
181#define VRC4173_KIUINT_DATALOST 0x0004
182#define VRC4173_KIUINT_DATAREADY 0x0002
183#define VRC4173_KIUINT_SCAN 0x0001
184
185#ifdef CONFIG_VRC4173
186
187extern void vrc4173_enable_kiuint(uint16_t mask);
188extern void vrc4173_disable_kiuint(uint16_t mask);
189
190#else
191
192static inline void vrc4173_enable_kiuint(uint16_t mask) {}
193static inline void vrc4173_disable_kiuint(uint16_t mask) {}
194
195#endif
196
197/*
198 * General-Purpose I/O Unit
199 */
200typedef enum vrc4173_function {
201 PS2_CHANNEL1,
202 PS2_CHANNEL2,
203 TOUCHPANEL,
204 KEYBOARD_8SCANLINES,
205 KEYBOARD_10SCANLINES,
206 KEYBOARD_12SCANLINES,
207 GPIO_0_15PINS,
208 GPIO_16_20PINS,
209} vrc4173_function_t;
210
211#ifdef CONFIG_VRC4173
212
213extern void vrc4173_select_function(vrc4173_function_t function);
214
215#else
216
217static inline void vrc4173_select_function(vrc4173_function_t function) {}
218
219#endif
220
221#endif /* __NEC_VRC4173_H */
diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h
deleted file mode 100644
index 6bfa9c009a9b..000000000000
--- a/include/asm-mips/vr41xx/workpad.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * workpad.h, Include file for IBM WorkPad z50.
3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __IBM_WORKPAD_H
21#define __IBM_WORKPAD_H
22
23#include <asm/addrspace.h>
24#include <asm/vr41xx/vr41xx.h>
25
26/*
27 * Board specific address mapping
28 */
29#define VR41XX_ISA_MEM_BASE 0x10000000
30#define VR41XX_ISA_MEM_SIZE 0x04000000
31
32/* VR41XX_ISA_IO_BASE includes offset from real base. */
33#define VR41XX_ISA_IO_BASE 0x15000000
34#define VR41XX_ISA_IO_SIZE 0x03000000
35
36#define ISA_BUS_IO_BASE 0
37#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE
38
39#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
40#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE
41#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
42
43#endif /* __IBM_WORKPAD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 05:23:01 -0500