diff options
Diffstat (limited to 'include/asm-mips')
-rw-r--r-- | include/asm-mips/bootinfo.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/cpu-feature-overrides.h | 40 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/excite.h | 155 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/excite_nandflash.h | 7 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/rm9k_eth.h | 23 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/rm9k_wdt.h | 12 | ||||
-rw-r--r-- | include/asm-mips/mach-excite/rm9k_xicap.h | 16 | ||||
-rw-r--r-- | include/asm-mips/rm9k-ocd.h | 56 | ||||
-rw-r--r-- | include/asm-mips/war.h | 5 |
9 files changed, 313 insertions, 2 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 72fa6dc45523..3b745e76f429 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
@@ -217,6 +217,7 @@ | |||
217 | */ | 217 | */ |
218 | #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ | 218 | #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ |
219 | #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ | 219 | #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ |
220 | #define MACH_TITAN_EXCITE 2 /* Basler eXcite */ | ||
220 | 221 | ||
221 | /* | 222 | /* |
222 | * Valid machtype for group NEC EMMA2RH | 223 | * Valid machtype for group NEC EMMA2RH |
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h new file mode 100644 index 000000000000..abb76b2fd865 --- /dev/null +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> | ||
7 | */ | ||
8 | #ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H | ||
9 | #define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H | ||
10 | |||
11 | /* | ||
12 | * Basler eXcite has an RM9122 processor. | ||
13 | */ | ||
14 | #define cpu_has_watch 1 | ||
15 | #define cpu_has_mips16 0 | ||
16 | #define cpu_has_divec 0 | ||
17 | #define cpu_has_vce 0 | ||
18 | #define cpu_has_cache_cdex_p 0 | ||
19 | #define cpu_has_cache_cdex_s 0 | ||
20 | #define cpu_has_prefetch 1 | ||
21 | #define cpu_has_mcheck 0 | ||
22 | #define cpu_has_ejtag 0 | ||
23 | |||
24 | #define cpu_has_llsc 1 | ||
25 | #define cpu_has_vtag_icache 0 | ||
26 | #define cpu_has_dc_aliases 0 | ||
27 | #define cpu_has_ic_fills_f_dc 0 | ||
28 | #define cpu_has_dsp 0 | ||
29 | #define cpu_icache_snoops_remote_store 0 | ||
30 | |||
31 | #define cpu_has_nofpuex 0 | ||
32 | #define cpu_has_64bits 1 | ||
33 | |||
34 | #define cpu_has_subset_pcaches 0 | ||
35 | |||
36 | #define cpu_dcache_line_size() 32 | ||
37 | #define cpu_icache_line_size() 32 | ||
38 | #define cpu_scache_line_size() 32 | ||
39 | |||
40 | #endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */ | ||
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h new file mode 100644 index 000000000000..c52610de2b3a --- /dev/null +++ b/include/asm-mips/mach-excite/excite.h | |||
@@ -0,0 +1,155 @@ | |||
1 | #ifndef __EXCITE_H__ | ||
2 | #define __EXCITE_H__ | ||
3 | |||
4 | #include <linux/config.h> | ||
5 | #include <linux/init.h> | ||
6 | #include <asm/addrspace.h> | ||
7 | #include <asm/types.h> | ||
8 | |||
9 | #define EXCITE_CPU_EXT_CLOCK 100000000 | ||
10 | |||
11 | #if !defined(__ASSEMBLER__) | ||
12 | void __init excite_kgdb_init(void); | ||
13 | void excite_procfs_init(void); | ||
14 | extern unsigned long memsize; | ||
15 | extern char modetty[]; | ||
16 | extern u32 unit_id; | ||
17 | #endif | ||
18 | |||
19 | /* Base name for XICAP devices */ | ||
20 | #define XICAP_NAME "xicap_gpi" | ||
21 | |||
22 | /* OCD register offsets */ | ||
23 | #define LKB0 0x0038 | ||
24 | #define LKB5 0x0128 | ||
25 | #define LKM5 0x012C | ||
26 | #define LKB7 0x0138 | ||
27 | #define LKM7 0x013c | ||
28 | #define LKB8 0x0140 | ||
29 | #define LKM8 0x0144 | ||
30 | #define LKB9 0x0148 | ||
31 | #define LKM9 0x014c | ||
32 | #define LKB10 0x0150 | ||
33 | #define LKM10 0x0154 | ||
34 | #define LKB11 0x0158 | ||
35 | #define LKM11 0x015c | ||
36 | #define LKB12 0x0160 | ||
37 | #define LKM12 0x0164 | ||
38 | #define LKB13 0x0168 | ||
39 | #define LKM13 0x016c | ||
40 | #define LDP0 0x0200 | ||
41 | #define LDP1 0x0210 | ||
42 | #define LDP2 0x0220 | ||
43 | #define LDP3 0x0230 | ||
44 | #define INTPIN0 0x0A40 | ||
45 | #define INTPIN1 0x0A44 | ||
46 | #define INTPIN2 0x0A48 | ||
47 | #define INTPIN3 0x0A4C | ||
48 | #define INTPIN4 0x0A50 | ||
49 | #define INTPIN5 0x0A54 | ||
50 | #define INTPIN6 0x0A58 | ||
51 | #define INTPIN7 0x0A5C | ||
52 | |||
53 | |||
54 | |||
55 | |||
56 | /* TITAN register offsets */ | ||
57 | #define CPRR 0x0004 | ||
58 | #define CPDSR 0x0008 | ||
59 | #define CPTC0R 0x000c | ||
60 | #define CPTC1R 0x0010 | ||
61 | #define CPCFG0 0x0020 | ||
62 | #define CPCFG1 0x0024 | ||
63 | #define CPDST0A 0x0028 | ||
64 | #define CPDST0B 0x002c | ||
65 | #define CPDST1A 0x0030 | ||
66 | #define CPDST1B 0x0034 | ||
67 | #define CPXDSTA 0x0038 | ||
68 | #define CPXDSTB 0x003c | ||
69 | #define CPXCISRA 0x0048 | ||
70 | #define CPXCISRB 0x004c | ||
71 | #define CPGIG0ER 0x0050 | ||
72 | #define CPGIG1ER 0x0054 | ||
73 | #define CPGRWL 0x0068 | ||
74 | #define CPURSLMT 0x00f8 | ||
75 | #define UACFG 0x0200 | ||
76 | #define UAINTS 0x0204 | ||
77 | #define SDRXFCIE 0x4828 | ||
78 | #define SDTXFCIE 0x4928 | ||
79 | #define INTP0Status0 0x1B00 | ||
80 | #define INTP0Mask0 0x1B04 | ||
81 | #define INTP0Set0 0x1B08 | ||
82 | #define INTP0Clear0 0x1B0C | ||
83 | #define GXCFG 0x5000 | ||
84 | #define GXDMADRPFX 0x5018 | ||
85 | #define GXDMA_DESCADR 0x501c | ||
86 | #define GXCH0TDESSTRT 0x5054 | ||
87 | |||
88 | /* IRQ definitions */ | ||
89 | #define NMICONFIG 0xac0 | ||
90 | #define TITAN_MSGINT 0xc4 | ||
91 | #define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) | ||
92 | #define FPGA0_MSGINT 0x5a | ||
93 | #define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) | ||
94 | #define FPGA1_MSGINT 0x7b | ||
95 | #define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) | ||
96 | #define PHY_MSGINT 0x9c | ||
97 | #define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) | ||
98 | |||
99 | #if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) | ||
100 | /* Pre-release units used interrupt pin #9 */ | ||
101 | #define USB_IRQ 11 | ||
102 | #else | ||
103 | /* Re-designed units use interrupt pin #1 */ | ||
104 | #define USB_MSGINT 0x39 | ||
105 | #define USB_IRQ ((USB_MSGINT / 0x20) + 2) | ||
106 | #endif | ||
107 | #define TIMER_IRQ 12 | ||
108 | |||
109 | |||
110 | /* Device address ranges */ | ||
111 | #define EXCITE_OFFS_OCD 0x1fffc000 | ||
112 | #define EXCITE_SIZE_OCD (16 * 1024) | ||
113 | #define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) | ||
114 | #define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) | ||
115 | |||
116 | #define EXCITE_OFFS_SCRAM 0x1fffa000 | ||
117 | #define EXCITE_SIZE_SCRAM (8 << 10) | ||
118 | #define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) | ||
119 | #define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) | ||
120 | |||
121 | #define EXCITE_OFFS_PCI_IO 0x1fff8000 | ||
122 | #define EXCITE_SIZE_PCI_IO (8 << 10) | ||
123 | #define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) | ||
124 | #define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) | ||
125 | |||
126 | #define EXCITE_OFFS_TITAN 0x1fff0000 | ||
127 | #define EXCITE_SIZE_TITAN (32 << 10) | ||
128 | #define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) | ||
129 | #define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) | ||
130 | |||
131 | #define EXCITE_OFFS_PCI_MEM 0x1ffe0000 | ||
132 | #define EXCITE_SIZE_PCI_MEM (64 << 10) | ||
133 | #define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) | ||
134 | #define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) | ||
135 | |||
136 | #define EXCITE_OFFS_FPGA 0x1ffdc000 | ||
137 | #define EXCITE_SIZE_FPGA (16 << 10) | ||
138 | #define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) | ||
139 | #define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) | ||
140 | |||
141 | #define EXCITE_OFFS_NAND 0x1ffd8000 | ||
142 | #define EXCITE_SIZE_NAND (16 << 10) | ||
143 | #define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) | ||
144 | #define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) | ||
145 | |||
146 | #define EXCITE_OFFS_BOOTROM 0x1f000000 | ||
147 | #define EXCITE_SIZE_BOOTROM (8 << 20) | ||
148 | #define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) | ||
149 | #define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) | ||
150 | |||
151 | /* FPGA address offsets */ | ||
152 | #define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ | ||
153 | #define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ | ||
154 | |||
155 | #endif /* __EXCITE_H__ */ | ||
diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h new file mode 100644 index 000000000000..c4cf6140622e --- /dev/null +++ b/include/asm-mips/mach-excite/excite_nandflash.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __EXCITE_NANDFLASH_H__ | ||
2 | #define __EXCITE_NANDFLASH_H__ | ||
3 | |||
4 | /* Resource names */ | ||
5 | #define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs" | ||
6 | |||
7 | #endif /* __EXCITE_NANDFLASH_H__ */ | ||
diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h new file mode 100644 index 000000000000..94705a46f72e --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_eth.h | |||
@@ -0,0 +1,23 @@ | |||
1 | #if !defined(__RM9K_ETH_H__) | ||
2 | #define __RM9K_ETH_H__ | ||
3 | |||
4 | #define RM9K_GE_NAME "rm9k_ge" | ||
5 | |||
6 | /* Resource names */ | ||
7 | #define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac" | ||
8 | #define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat" | ||
9 | #define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc" | ||
10 | #define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma" | ||
11 | #define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx" | ||
12 | #define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx" | ||
13 | #define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx" | ||
14 | #define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx" | ||
15 | #define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy" | ||
16 | #define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx" | ||
17 | #define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx" | ||
18 | #define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main" | ||
19 | #define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy" | ||
20 | #define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice" | ||
21 | #define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel" | ||
22 | |||
23 | #endif /* !defined(__RM9K_ETH_H__) */ | ||
diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h new file mode 100644 index 000000000000..3fa3c08d2da7 --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_wdt.h | |||
@@ -0,0 +1,12 @@ | |||
1 | #ifndef __RM9K_WDT_H__ | ||
2 | #define __RM9K_WDT_H__ | ||
3 | |||
4 | /* Device name */ | ||
5 | #define WDT_NAME "wdt_gpi" | ||
6 | |||
7 | /* Resource names */ | ||
8 | #define WDT_RESOURCE_REGS "excite_watchdog_regs" | ||
9 | #define WDT_RESOURCE_IRQ "excite_watchdog_irq" | ||
10 | #define WDT_RESOURCE_COUNTER "excite_watchdog_counter" | ||
11 | |||
12 | #endif /* __RM9K_WDT_H__ */ | ||
diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h new file mode 100644 index 000000000000..009577734a8d --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_xicap.h | |||
@@ -0,0 +1,16 @@ | |||
1 | #ifndef __EXCITE_XICAP_H__ | ||
2 | #define __EXCITE_XICAP_H__ | ||
3 | |||
4 | |||
5 | /* Resource names */ | ||
6 | #define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx" | ||
7 | #define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx" | ||
8 | #define XICAP_RESOURCE_XDMA "xicap_xdma" | ||
9 | #define XICAP_RESOURCE_DMADESC "xicap_dmadesc" | ||
10 | #define XICAP_RESOURCE_PKTPROC "xicap_pktproc" | ||
11 | #define XICAP_RESOURCE_IRQ "xicap_irq" | ||
12 | #define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice" | ||
13 | #define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks" | ||
14 | #define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream" | ||
15 | |||
16 | #endif /* __EXCITE_XICAP_H__ */ | ||
diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h new file mode 100644 index 000000000000..b0b80d9ecf96 --- /dev/null +++ b/include/asm-mips/rm9k-ocd.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2004 by Basler Vision Technologies AG | ||
3 | * Author: Thomas Koeller <thomas.koeller@baslerweb.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | |||
20 | #if !defined(_ASM_RM9K_OCD_H) | ||
21 | #define _ASM_RM9K_OCD_H | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | #include <linux/spinlock.h> | ||
25 | #include <asm/io.h> | ||
26 | |||
27 | extern volatile void __iomem * const ocd_base; | ||
28 | extern volatile void __iomem * const titan_base; | ||
29 | |||
30 | #define ocd_addr(__x__) (ocd_base + (__x__)) | ||
31 | #define titan_addr(__x__) (titan_base + (__x__)) | ||
32 | #define scram_addr(__x__) (scram_base + (__x__)) | ||
33 | |||
34 | /* OCD register access */ | ||
35 | #define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__)) | ||
36 | #define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__)) | ||
37 | #define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__)) | ||
38 | #define ocd_writel(__val__, __offs__) \ | ||
39 | __raw_writel((__val__), ocd_addr(__offs__)) | ||
40 | #define ocd_writew(__val__, __offs__) \ | ||
41 | __raw_writew((__val__), ocd_addr(__offs__)) | ||
42 | #define ocd_writeb(__val__, __offs__) \ | ||
43 | __raw_writeb((__val__), ocd_addr(__offs__)) | ||
44 | |||
45 | /* TITAN register access - 32 bit-wide only */ | ||
46 | #define titan_readl(__offs__) __raw_readl(titan_addr(__offs__)) | ||
47 | #define titan_writel(__val__, __offs__) \ | ||
48 | __raw_writel((__val__), titan_addr(__offs__)) | ||
49 | |||
50 | /* Protect access to shared TITAN registers */ | ||
51 | extern spinlock_t titan_lock; | ||
52 | extern int titan_irqflags; | ||
53 | #define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags) | ||
54 | #define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags) | ||
55 | |||
56 | #endif /* !defined(_ASM_RM9K_OCD_H) */ | ||
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index ad374bd3f130..70636b41832c 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -172,7 +172,8 @@ | |||
172 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive | 172 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive |
173 | * cache operation unusable on SMP systems. | 173 | * cache operation unusable on SMP systems. |
174 | */ | 174 | */ |
175 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) | 175 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ |
176 | defined(CONFIG_BASLER_EXCITE) | ||
176 | #define RM9000_CDEX_SMP_WAR 1 | 177 | #define RM9000_CDEX_SMP_WAR 1 |
177 | #endif | 178 | #endif |
178 | 179 | ||
@@ -182,7 +183,7 @@ | |||
182 | * being fetched may case spurious exceptions. | 183 | * being fetched may case spurious exceptions. |
183 | */ | 184 | */ |
184 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ | 185 | #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ |
185 | defined(CONFIG_PMC_YOSEMITE) | 186 | defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) |
186 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | 187 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 |
187 | #endif | 188 | #endif |
188 | 189 | ||