diff options
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_int.h | 310 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_l2c.h | 176 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_mc.h | 962 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_regs.h | 869 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_scd.h | 436 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250.h | 11 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_defs.h | 31 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_dma.h | 65 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_genbus.h | 225 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_int.h | 6 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_l2c.h | 9 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_mac.h | 33 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_mc.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_regs.h | 33 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_scd.h | 100 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_smbus.h | 53 | ||||
| -rw-r--r-- | include/asm-mips/sibyte/sb1250_uart.h | 11 |
17 files changed, 3236 insertions, 98 deletions
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h new file mode 100644 index 000000000000..42d4cf00efd3 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_int.h | |||
| @@ -0,0 +1,310 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Interrupt Mapper definitions File: bcm1480_int.h | ||
| 5 | * | ||
| 6 | * This module contains constants for manipulating the | ||
| 7 | * BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and | ||
| 8 | * definitions for the interrupt sources. | ||
| 9 | * | ||
| 10 | * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) | ||
| 11 | * | ||
| 12 | ********************************************************************* | ||
| 13 | * | ||
| 14 | * Copyright 2000,2001,2002,2003 | ||
| 15 | * Broadcom Corporation. All rights reserved. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or | ||
| 18 | * modify it under the terms of the GNU General Public License as | ||
| 19 | * published by the Free Software Foundation; either version 2 of | ||
| 20 | * the License, or (at your option) any later version. | ||
| 21 | * | ||
| 22 | * This program is distributed in the hope that it will be useful, | ||
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 25 | * GNU General Public License for more details. | ||
| 26 | * | ||
| 27 | * You should have received a copy of the GNU General Public License | ||
| 28 | * along with this program; if not, write to the Free Software | ||
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 30 | * MA 02111-1307 USA | ||
| 31 | ********************************************************************* */ | ||
| 32 | |||
| 33 | |||
| 34 | #ifndef _BCM1480_INT_H | ||
| 35 | #define _BCM1480_INT_H | ||
| 36 | |||
| 37 | #include "sb1250_defs.h" | ||
| 38 | |||
| 39 | /* ********************************************************************* | ||
| 40 | * Interrupt Mapper Constants | ||
| 41 | ********************************************************************* */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * The interrupt mapper deals with 128-bit logical registers that are | ||
| 45 | * implemented as pairs of 64-bit registers, with the "low" 64 bits in | ||
| 46 | * a register that has an address 0x1000 higher(!) than the | ||
| 47 | * corresponding "high" register. | ||
| 48 | * | ||
| 49 | * For appropriate registers, bit 0 of the "high" register is a | ||
| 50 | * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low" | ||
| 51 | * register. | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * This entire file uses _BCM1480_ in all the symbols because it is | ||
| 56 | * entirely BCM1480 specific. | ||
| 57 | */ | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Interrupt sources (Table 22) | ||
| 61 | */ | ||
| 62 | |||
| 63 | #define K_BCM1480_INT_SOURCES 128 | ||
| 64 | |||
| 65 | #define _BCM1480_INT_HIGH(k) (k) | ||
| 66 | #define _BCM1480_INT_LOW(k) ((k)+64) | ||
| 67 | |||
| 68 | #define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) | ||
| 69 | #define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) | ||
| 70 | #define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) | ||
| 71 | #define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) | ||
| 72 | #define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) | ||
| 73 | #define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) | ||
| 74 | #define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) | ||
| 75 | #define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) | ||
| 76 | #define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) | ||
| 77 | #define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) | ||
| 78 | #define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) | ||
| 79 | #define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) | ||
| 80 | #define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) | ||
| 81 | #define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) | ||
| 82 | #define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) | ||
| 83 | #define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) | ||
| 84 | #define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) | ||
| 85 | #define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) | ||
| 86 | #define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) | ||
| 87 | #define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) | ||
| 88 | #define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) | ||
| 89 | #define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) | ||
| 90 | #define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) | ||
| 91 | #define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) | ||
| 92 | #define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) | ||
| 93 | #define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) | ||
| 94 | #define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) | ||
| 95 | #define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) | ||
| 96 | #define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) | ||
| 97 | #define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) | ||
| 98 | #define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) | ||
| 99 | #define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) | ||
| 100 | #define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) | ||
| 101 | #define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) | ||
| 102 | #define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) | ||
| 103 | #define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) | ||
| 104 | #define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) | ||
| 105 | #define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) | ||
| 106 | #define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) | ||
| 107 | #define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) | ||
| 108 | #define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) | ||
| 109 | |||
| 110 | #define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) | ||
| 111 | #define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) | ||
| 112 | #define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) | ||
| 113 | #define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) | ||
| 114 | #define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) | ||
| 115 | #define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) | ||
| 116 | #define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) | ||
| 117 | #define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) | ||
| 118 | #define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) | ||
| 119 | #define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) | ||
| 120 | #define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) | ||
| 121 | #define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) | ||
| 122 | #define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) | ||
| 123 | #define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) | ||
| 124 | #define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) | ||
| 125 | #define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) | ||
| 126 | #define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) | ||
| 127 | #define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) | ||
| 128 | #define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) | ||
| 129 | #define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) | ||
| 130 | #define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) | ||
| 131 | #define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) | ||
| 132 | #define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) | ||
| 133 | #define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) | ||
| 134 | #define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) | ||
| 135 | #define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) | ||
| 136 | #define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) | ||
| 137 | #define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) | ||
| 138 | #define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) | ||
| 139 | #define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) | ||
| 140 | #define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) | ||
| 141 | #define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) | ||
| 142 | #define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) | ||
| 143 | #define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) | ||
| 144 | #define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) | ||
| 145 | #define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) | ||
| 146 | #define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) | ||
| 147 | #define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) | ||
| 148 | #define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) | ||
| 149 | #define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) | ||
| 150 | #define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) | ||
| 151 | #define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) | ||
| 152 | #define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) | ||
| 153 | #define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) | ||
| 154 | #define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Mask values for each interrupt | ||
| 158 | */ | ||
| 159 | |||
| 160 | #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) | ||
| 161 | #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) | ||
| 162 | |||
| 163 | #define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) | ||
| 164 | |||
| 165 | #define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) | ||
| 166 | #define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) | ||
| 167 | #define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) | ||
| 168 | #define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) | ||
| 169 | #define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) | ||
| 170 | #define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) | ||
| 171 | #define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) | ||
| 172 | #define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) | ||
| 173 | #define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) | ||
| 174 | #define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) | ||
| 175 | #define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) | ||
| 176 | #define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) | ||
| 177 | #define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) | ||
| 178 | #define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) | ||
| 179 | #define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) | ||
| 180 | #define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) | ||
| 181 | #define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) | ||
| 182 | #define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) | ||
| 183 | #define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) | ||
| 184 | #define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) | ||
| 185 | #define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) | ||
| 186 | #define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) | ||
| 187 | #define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) | ||
| 188 | #define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) | ||
| 189 | #define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) | ||
| 190 | #define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) | ||
| 191 | #define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) | ||
| 192 | #define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) | ||
| 193 | #define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) | ||
| 194 | #define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) | ||
| 195 | #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) | ||
| 196 | #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) | ||
| 197 | #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) | ||
| 198 | #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) | ||
| 199 | #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) | ||
| 200 | #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) | ||
| 201 | #define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) | ||
| 202 | #define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) | ||
| 203 | #define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) | ||
| 204 | #define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) | ||
| 205 | #define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) | ||
| 206 | #define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) | ||
| 207 | #define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) | ||
| 208 | #define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) | ||
| 209 | #define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) | ||
| 210 | #define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) | ||
| 211 | #define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) | ||
| 212 | #define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) | ||
| 213 | #define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) | ||
| 214 | #define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) | ||
| 215 | #define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) | ||
| 216 | #define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) | ||
| 217 | #define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) | ||
| 218 | #define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) | ||
| 219 | #define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) | ||
| 220 | #define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) | ||
| 221 | #define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) | ||
| 222 | #define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) | ||
| 223 | #define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) | ||
| 224 | #define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) | ||
| 225 | #define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) | ||
| 226 | #define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) | ||
| 227 | #define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) | ||
| 228 | #define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) | ||
| 229 | #define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) | ||
| 230 | #define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) | ||
| 231 | #define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) | ||
| 232 | #define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) | ||
| 233 | #define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) | ||
| 234 | #define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) | ||
| 235 | #define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) | ||
| 236 | #define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) | ||
| 237 | #define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) | ||
| 238 | #define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) | ||
| 239 | #define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) | ||
| 240 | #define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) | ||
| 241 | #define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) | ||
| 242 | #define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) | ||
| 243 | #define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) | ||
| 244 | #define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) | ||
| 245 | #define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) | ||
| 246 | #define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) | ||
| 247 | #define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) | ||
| 248 | #define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) | ||
| 249 | #define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) | ||
| 250 | #define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) | ||
| 251 | |||
| 252 | /* | ||
| 253 | * Interrupt mappings (Table 18) | ||
| 254 | */ | ||
| 255 | |||
| 256 | #define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ | ||
| 257 | #define K_BCM1480_INT_MAP_I1 1 | ||
| 258 | #define K_BCM1480_INT_MAP_I2 2 | ||
| 259 | #define K_BCM1480_INT_MAP_I3 3 | ||
| 260 | #define K_BCM1480_INT_MAP_I4 4 | ||
| 261 | #define K_BCM1480_INT_MAP_I5 5 | ||
| 262 | #define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ | ||
| 263 | #define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ | ||
| 264 | |||
| 265 | /* | ||
| 266 | * Interrupt LDT Set Register (Table 19) | ||
| 267 | */ | ||
| 268 | |||
| 269 | #define S_BCM1480_INT_HT_INTMSG 0 | ||
| 270 | #define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) | ||
| 271 | #define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) | ||
| 272 | #define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) | ||
| 273 | |||
| 274 | #define K_BCM1480_INT_HT_INTMSG_FIXED 0 | ||
| 275 | #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 | ||
| 276 | #define K_BCM1480_INT_HT_INTMSG_SMI 2 | ||
| 277 | #define K_BCM1480_INT_HT_INTMSG_NMI 3 | ||
| 278 | #define K_BCM1480_INT_HT_INTMSG_INIT 4 | ||
| 279 | #define K_BCM1480_INT_HT_INTMSG_STARTUP 5 | ||
| 280 | #define K_BCM1480_INT_HT_INTMSG_EXTINT 6 | ||
| 281 | #define K_BCM1480_INT_HT_INTMSG_RESERVED 7 | ||
| 282 | |||
| 283 | #define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) | ||
| 284 | #define V_BCM1480_INT_HT_EDGETRIGGER 0 | ||
| 285 | #define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE | ||
| 286 | |||
| 287 | #define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) | ||
| 288 | #define V_BCM1480_INT_HT_PHYSICALDEST 0 | ||
| 289 | #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE | ||
| 290 | |||
| 291 | #define S_BCM1480_INT_HT_INTDEST 5 | ||
| 292 | #define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) | ||
| 293 | #define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) | ||
| 294 | #define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) | ||
| 295 | |||
| 296 | #define S_BCM1480_INT_HT_VECTOR 13 | ||
| 297 | #define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) | ||
| 298 | #define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) | ||
| 299 | #define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) | ||
| 300 | |||
| 301 | /* | ||
| 302 | * Vector prefix (Table 4-7) | ||
| 303 | */ | ||
| 304 | |||
| 305 | #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 | ||
| 306 | #define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 | ||
| 307 | #define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 | ||
| 308 | #define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 | ||
| 309 | |||
| 310 | #endif /* _BCM1480_INT_H */ | ||
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h new file mode 100644 index 000000000000..886b099565e6 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_l2c.h | |||
| @@ -0,0 +1,176 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * L2 Cache constants and macros File: bcm1480_l2c.h | ||
| 5 | * | ||
| 6 | * This module contains constants useful for manipulating the | ||
| 7 | * level 2 cache. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1280-UM100-D2 (11/14/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _BCM1480_L2C_H | ||
| 34 | #define _BCM1480_L2C_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Format of level 2 cache management address (Table 55) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_BCM1480_L2C_MGMT_INDEX 5 | ||
| 43 | #define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) | ||
| 44 | #define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) | ||
| 45 | #define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) | ||
| 46 | |||
| 47 | #define S_BCM1480_L2C_MGMT_WAY 17 | ||
| 48 | #define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) | ||
| 49 | #define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) | ||
| 50 | #define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) | ||
| 51 | |||
| 52 | #define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) | ||
| 53 | #define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) | ||
| 54 | |||
| 55 | #define S_BCM1480_L2C_MGMT_ECC_DIAG 22 | ||
| 56 | #define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 57 | #define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 58 | #define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 59 | |||
| 60 | #define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 | ||
| 61 | |||
| 62 | #define BCM1480_L2C_ENTRIES_PER_WAY 4096 | ||
| 63 | #define BCM1480_L2C_NUM_WAYS 8 | ||
| 64 | |||
| 65 | |||
| 66 | /* | ||
| 67 | * Level 2 Cache Tag register (Table 59) | ||
| 68 | */ | ||
| 69 | |||
| 70 | #define S_BCM1480_L2C_TAG_MBZ 0 | ||
| 71 | #define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) | ||
| 72 | |||
| 73 | #define S_BCM1480_L2C_TAG_INDEX 5 | ||
| 74 | #define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) | ||
| 75 | #define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) | ||
| 76 | #define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) | ||
| 77 | |||
| 78 | /* Note that index bit 16 is also tag bit 40 */ | ||
| 79 | #define S_BCM1480_L2C_TAG_TAG 17 | ||
| 80 | #define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) | ||
| 81 | #define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) | ||
| 82 | #define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) | ||
| 83 | |||
| 84 | #define S_BCM1480_L2C_TAG_ECC 40 | ||
| 85 | #define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) | ||
| 86 | #define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) | ||
| 87 | #define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) | ||
| 88 | |||
| 89 | #define S_BCM1480_L2C_TAG_WAY 46 | ||
| 90 | #define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) | ||
| 91 | #define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) | ||
| 92 | #define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) | ||
| 93 | |||
| 94 | #define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) | ||
| 95 | #define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) | ||
| 96 | |||
| 97 | #define S_BCM1480_L2C_DATA_ECC 51 | ||
| 98 | #define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) | ||
| 99 | #define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) | ||
| 100 | #define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * L2 Misc0 Value Register (Table 60) | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 | ||
| 108 | #define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) | ||
| 109 | #define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) | ||
| 110 | |||
| 111 | #define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 | ||
| 112 | #define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) | ||
| 113 | #define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) | ||
| 114 | |||
| 115 | #define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 | ||
| 116 | #define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) | ||
| 117 | #define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) | ||
| 118 | |||
| 119 | #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 | ||
| 120 | #define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) | ||
| 121 | #define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) | ||
| 122 | |||
| 123 | #define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 | ||
| 124 | #define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) | ||
| 125 | #define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) | ||
| 126 | |||
| 127 | #define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 | ||
| 128 | #define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) | ||
| 129 | |||
| 130 | #define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 | ||
| 131 | #define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) | ||
| 132 | |||
| 133 | |||
| 134 | /* | ||
| 135 | * L2 Misc1 Value Register (Table 60) | ||
| 136 | */ | ||
| 137 | |||
| 138 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 | ||
| 139 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) | ||
| 140 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) | ||
| 141 | |||
| 142 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 | ||
| 143 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) | ||
| 144 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) | ||
| 145 | |||
| 146 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 | ||
| 147 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) | ||
| 148 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) | ||
| 149 | |||
| 150 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 | ||
| 151 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) | ||
| 152 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) | ||
| 153 | |||
| 154 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 | ||
| 155 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) | ||
| 156 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) | ||
| 157 | |||
| 158 | |||
| 159 | /* | ||
| 160 | * L2 Misc2 Value Register (Table 60) | ||
| 161 | */ | ||
| 162 | |||
| 163 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 | ||
| 164 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) | ||
| 165 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) | ||
| 166 | |||
| 167 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 | ||
| 168 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) | ||
| 169 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) | ||
| 170 | |||
| 171 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 | ||
| 172 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) | ||
| 173 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) | ||
| 174 | |||
| 175 | |||
| 176 | #endif /* _BCM1480_L2C_H */ | ||
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h new file mode 100644 index 000000000000..6bdc941afc91 --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_mc.h | |||
| @@ -0,0 +1,962 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Memory Controller constants File: bcm1480_mc.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * programming the memory controller. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _BCM1480_MC_H | ||
| 34 | #define _BCM1480_MC_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Memory Channel Configuration Register (Table 81) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_BCM1480_MC_INTLV0 0 | ||
| 43 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) | ||
| 44 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) | ||
| 45 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) | ||
| 46 | #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) | ||
| 47 | |||
| 48 | #define S_BCM1480_MC_INTLV1 8 | ||
| 49 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) | ||
| 50 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) | ||
| 51 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) | ||
| 52 | #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) | ||
| 53 | |||
| 54 | #define S_BCM1480_MC_INTLV2 16 | ||
| 55 | #define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) | ||
| 56 | #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) | ||
| 57 | #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) | ||
| 58 | #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) | ||
| 59 | |||
| 60 | #define S_BCM1480_MC_CS_MODE 32 | ||
| 61 | #define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) | ||
| 62 | #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) | ||
| 63 | #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) | ||
| 64 | #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) | ||
| 65 | |||
| 66 | #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ | ||
| 67 | V_BCM1480_MC_INTLV1_DEFAULT | \ | ||
| 68 | V_BCM1480_MC_INTLV2_DEFAULT | \ | ||
| 69 | V_BCM1480_MC_CS_MODE_DEFAULT) | ||
| 70 | |||
| 71 | #define K_BCM1480_MC_CS01_MODE 0x03 | ||
| 72 | #define K_BCM1480_MC_CS02_MODE 0x05 | ||
| 73 | #define K_BCM1480_MC_CS0123_MODE 0x0F | ||
| 74 | #define K_BCM1480_MC_CS0246_MODE 0x55 | ||
| 75 | #define K_BCM1480_MC_CS0145_MODE 0x33 | ||
| 76 | #define K_BCM1480_MC_CS0167_MODE 0xC3 | ||
| 77 | #define K_BCM1480_MC_CSFULL_MODE 0xFF | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Chip Select Start Address Register (Table 82) | ||
| 81 | */ | ||
| 82 | |||
| 83 | #define S_BCM1480_MC_CS0_START 0 | ||
| 84 | #define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) | ||
| 85 | #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) | ||
| 86 | #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) | ||
| 87 | |||
| 88 | #define S_BCM1480_MC_CS1_START 16 | ||
| 89 | #define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) | ||
| 90 | #define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) | ||
| 91 | #define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) | ||
| 92 | |||
| 93 | #define S_BCM1480_MC_CS2_START 32 | ||
| 94 | #define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) | ||
| 95 | #define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) | ||
| 96 | #define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) | ||
| 97 | |||
| 98 | #define S_BCM1480_MC_CS3_START 48 | ||
| 99 | #define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) | ||
| 100 | #define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) | ||
| 101 | #define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Chip Select End Address Register (Table 83) | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define S_BCM1480_MC_CS0_END 0 | ||
| 108 | #define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) | ||
| 109 | #define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) | ||
| 110 | #define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) | ||
| 111 | |||
| 112 | #define S_BCM1480_MC_CS1_END 16 | ||
| 113 | #define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) | ||
| 114 | #define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) | ||
| 115 | #define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) | ||
| 116 | |||
| 117 | #define S_BCM1480_MC_CS2_END 32 | ||
| 118 | #define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) | ||
| 119 | #define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) | ||
| 120 | #define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) | ||
| 121 | |||
| 122 | #define S_BCM1480_MC_CS3_END 48 | ||
| 123 | #define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) | ||
| 124 | #define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) | ||
| 125 | #define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) | ||
| 126 | |||
| 127 | /* | ||
| 128 | * Row Address Bit Select Register 0 (Table 84) | ||
| 129 | */ | ||
| 130 | |||
| 131 | #define S_BCM1480_MC_ROW00 0 | ||
| 132 | #define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) | ||
| 133 | #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) | ||
| 134 | #define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) | ||
| 135 | |||
| 136 | #define S_BCM1480_MC_ROW01 8 | ||
| 137 | #define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) | ||
| 138 | #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) | ||
| 139 | #define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) | ||
| 140 | |||
| 141 | #define S_BCM1480_MC_ROW02 16 | ||
| 142 | #define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) | ||
| 143 | #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) | ||
| 144 | #define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) | ||
| 145 | |||
| 146 | #define S_BCM1480_MC_ROW03 24 | ||
| 147 | #define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) | ||
| 148 | #define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) | ||
| 149 | #define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) | ||
| 150 | |||
| 151 | #define S_BCM1480_MC_ROW04 32 | ||
| 152 | #define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) | ||
| 153 | #define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) | ||
| 154 | #define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) | ||
| 155 | |||
| 156 | #define S_BCM1480_MC_ROW05 40 | ||
| 157 | #define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) | ||
| 158 | #define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) | ||
| 159 | #define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) | ||
| 160 | |||
| 161 | #define S_BCM1480_MC_ROW06 48 | ||
| 162 | #define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) | ||
| 163 | #define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) | ||
| 164 | #define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) | ||
| 165 | |||
| 166 | #define S_BCM1480_MC_ROW07 56 | ||
| 167 | #define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) | ||
| 168 | #define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) | ||
| 169 | #define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Row Address Bit Select Register 1 (Table 85) | ||
| 173 | */ | ||
| 174 | |||
| 175 | #define S_BCM1480_MC_ROW08 0 | ||
| 176 | #define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) | ||
| 177 | #define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) | ||
| 178 | #define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) | ||
| 179 | |||
| 180 | #define S_BCM1480_MC_ROW09 8 | ||
| 181 | #define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) | ||
| 182 | #define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) | ||
| 183 | #define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) | ||
| 184 | |||
| 185 | #define S_BCM1480_MC_ROW10 16 | ||
| 186 | #define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) | ||
| 187 | #define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) | ||
| 188 | #define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) | ||
| 189 | |||
| 190 | #define S_BCM1480_MC_ROW11 24 | ||
| 191 | #define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) | ||
| 192 | #define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) | ||
| 193 | #define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) | ||
| 194 | |||
| 195 | #define S_BCM1480_MC_ROW12 32 | ||
| 196 | #define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) | ||
| 197 | #define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) | ||
| 198 | #define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) | ||
| 199 | |||
| 200 | #define S_BCM1480_MC_ROW13 40 | ||
| 201 | #define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) | ||
| 202 | #define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) | ||
| 203 | #define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) | ||
| 204 | |||
| 205 | #define S_BCM1480_MC_ROW14 48 | ||
| 206 | #define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) | ||
| 207 | #define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) | ||
| 208 | #define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) | ||
| 209 | |||
| 210 | #define K_BCM1480_MC_ROWX_BIT_SPACING 8 | ||
| 211 | |||
| 212 | /* | ||
| 213 | * Column Address Bit Select Register 0 (Table 86) | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define S_BCM1480_MC_COL00 0 | ||
| 217 | #define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) | ||
| 218 | #define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) | ||
| 219 | #define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) | ||
| 220 | |||
| 221 | #define S_BCM1480_MC_COL01 8 | ||
| 222 | #define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) | ||
| 223 | #define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) | ||
| 224 | #define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) | ||
| 225 | |||
| 226 | #define S_BCM1480_MC_COL02 16 | ||
| 227 | #define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) | ||
| 228 | #define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) | ||
| 229 | #define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) | ||
| 230 | |||
| 231 | #define S_BCM1480_MC_COL03 24 | ||
| 232 | #define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) | ||
| 233 | #define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) | ||
| 234 | #define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) | ||
| 235 | |||
| 236 | #define S_BCM1480_MC_COL04 32 | ||
| 237 | #define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) | ||
| 238 | #define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) | ||
| 239 | #define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) | ||
| 240 | |||
| 241 | #define S_BCM1480_MC_COL05 40 | ||
| 242 | #define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) | ||
| 243 | #define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) | ||
| 244 | #define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) | ||
| 245 | |||
| 246 | #define S_BCM1480_MC_COL06 48 | ||
| 247 | #define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) | ||
| 248 | #define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) | ||
| 249 | #define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) | ||
| 250 | |||
| 251 | #define S_BCM1480_MC_COL07 56 | ||
| 252 | #define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) | ||
| 253 | #define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) | ||
| 254 | #define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) | ||
| 255 | |||
| 256 | /* | ||
| 257 | * Column Address Bit Select Register 1 (Table 87) | ||
| 258 | */ | ||
| 259 | |||
| 260 | #define S_BCM1480_MC_COL08 0 | ||
| 261 | #define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) | ||
| 262 | #define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) | ||
| 263 | #define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) | ||
| 264 | |||
| 265 | #define S_BCM1480_MC_COL09 8 | ||
| 266 | #define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) | ||
| 267 | #define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) | ||
| 268 | #define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) | ||
| 269 | |||
| 270 | #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ | ||
| 271 | |||
| 272 | #define S_BCM1480_MC_COL11 24 | ||
| 273 | #define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) | ||
| 274 | #define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) | ||
| 275 | #define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) | ||
| 276 | |||
| 277 | #define S_BCM1480_MC_COL12 32 | ||
| 278 | #define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) | ||
| 279 | #define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) | ||
| 280 | #define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) | ||
| 281 | |||
| 282 | #define S_BCM1480_MC_COL13 40 | ||
| 283 | #define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) | ||
| 284 | #define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) | ||
| 285 | #define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) | ||
| 286 | |||
| 287 | #define S_BCM1480_MC_COL14 48 | ||
| 288 | #define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) | ||
| 289 | #define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) | ||
| 290 | #define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) | ||
| 291 | |||
| 292 | #define K_BCM1480_MC_COLX_BIT_SPACING 8 | ||
| 293 | |||
| 294 | /* | ||
| 295 | * CS0 and CS1 Bank Address Bit Select Register (Table 88) | ||
| 296 | */ | ||
| 297 | |||
| 298 | #define S_BCM1480_MC_CS01_BANK0 0 | ||
| 299 | #define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) | ||
| 300 | #define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) | ||
| 301 | #define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) | ||
| 302 | |||
| 303 | #define S_BCM1480_MC_CS01_BANK1 8 | ||
| 304 | #define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) | ||
| 305 | #define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) | ||
| 306 | #define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) | ||
| 307 | |||
| 308 | #define S_BCM1480_MC_CS01_BANK2 16 | ||
| 309 | #define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) | ||
| 310 | #define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) | ||
| 311 | #define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) | ||
| 312 | |||
| 313 | /* | ||
| 314 | * CS2 and CS3 Bank Address Bit Select Register (Table 89) | ||
| 315 | */ | ||
| 316 | |||
| 317 | #define S_BCM1480_MC_CS23_BANK0 0 | ||
| 318 | #define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) | ||
| 319 | #define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) | ||
| 320 | #define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) | ||
| 321 | |||
| 322 | #define S_BCM1480_MC_CS23_BANK1 8 | ||
| 323 | #define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) | ||
| 324 | #define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) | ||
| 325 | #define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) | ||
| 326 | |||
| 327 | #define S_BCM1480_MC_CS23_BANK2 16 | ||
| 328 | #define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) | ||
| 329 | #define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) | ||
| 330 | #define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) | ||
| 331 | |||
| 332 | #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 | ||
| 333 | |||
| 334 | /* | ||
| 335 | * DRAM Command Register (Table 90) | ||
| 336 | */ | ||
| 337 | |||
| 338 | #define S_BCM1480_MC_COMMAND 0 | ||
| 339 | #define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) | ||
| 340 | #define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) | ||
| 341 | #define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) | ||
| 342 | |||
| 343 | #define K_BCM1480_MC_COMMAND_EMRS 0 | ||
| 344 | #define K_BCM1480_MC_COMMAND_MRS 1 | ||
| 345 | #define K_BCM1480_MC_COMMAND_PRE 2 | ||
| 346 | #define K_BCM1480_MC_COMMAND_AR 3 | ||
| 347 | #define K_BCM1480_MC_COMMAND_SETRFSH 4 | ||
| 348 | #define K_BCM1480_MC_COMMAND_CLRRFSH 5 | ||
| 349 | #define K_BCM1480_MC_COMMAND_SETPWRDN 6 | ||
| 350 | #define K_BCM1480_MC_COMMAND_CLRPWRDN 7 | ||
| 351 | |||
| 352 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 353 | #define K_BCM1480_MC_COMMAND_EMRS2 8 | ||
| 354 | #define K_BCM1480_MC_COMMAND_EMRS3 9 | ||
| 355 | #define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 | ||
| 356 | #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 | ||
| 357 | #endif | ||
| 358 | |||
| 359 | #define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) | ||
| 360 | #define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) | ||
| 361 | #define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) | ||
| 362 | #define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) | ||
| 363 | #define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) | ||
| 364 | #define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) | ||
| 365 | #define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) | ||
| 366 | #define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) | ||
| 367 | |||
| 368 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 369 | #define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) | ||
| 370 | #define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) | ||
| 371 | #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) | ||
| 372 | #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) | ||
| 373 | #endif | ||
| 374 | |||
| 375 | #define S_BCM1480_MC_CS0 4 | ||
| 376 | #define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) | ||
| 377 | #define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) | ||
| 378 | #define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) | ||
| 379 | #define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) | ||
| 380 | #define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) | ||
| 381 | #define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) | ||
| 382 | #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) | ||
| 383 | #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) | ||
| 384 | |||
| 385 | #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) | ||
| 386 | |||
| 387 | /* | ||
| 388 | * DRAM Mode Register (Table 91) | ||
| 389 | */ | ||
| 390 | |||
| 391 | #define S_BCM1480_MC_EMODE 0 | ||
| 392 | #define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) | ||
| 393 | #define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) | ||
| 394 | #define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) | ||
| 395 | #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) | ||
| 396 | |||
| 397 | #define S_BCM1480_MC_MODE 16 | ||
| 398 | #define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) | ||
| 399 | #define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) | ||
| 400 | #define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) | ||
| 401 | #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) | ||
| 402 | |||
| 403 | #define S_BCM1480_MC_DRAM_TYPE 32 | ||
| 404 | #define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) | ||
| 405 | #define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) | ||
| 406 | #define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) | ||
| 407 | |||
| 408 | #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 | ||
| 409 | #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 | ||
| 410 | |||
| 411 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 412 | #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 | ||
| 413 | #endif | ||
| 414 | |||
| 415 | #define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) | ||
| 416 | #define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) | ||
| 417 | |||
| 418 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 419 | #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) | ||
| 420 | #endif | ||
| 421 | |||
| 422 | #define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) | ||
| 423 | #define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) | ||
| 424 | #define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) | ||
| 425 | #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) | ||
| 426 | |||
| 427 | #define S_BCM1480_MC_PG_POLICY 40 | ||
| 428 | #define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) | ||
| 429 | #define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) | ||
| 430 | #define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) | ||
| 431 | |||
| 432 | #define K_BCM1480_MC_PG_POLICY_CLOSED 0 | ||
| 433 | #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 | ||
| 434 | |||
| 435 | #define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) | ||
| 436 | #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) | ||
| 437 | |||
| 438 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 439 | #define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) | ||
| 440 | #define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) | ||
| 441 | #endif | ||
| 442 | |||
| 443 | #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ | ||
| 444 | V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) | ||
| 445 | |||
| 446 | /* | ||
| 447 | * Memory Clock Configuration Register (Table 92) | ||
| 448 | */ | ||
| 449 | |||
| 450 | #define S_BCM1480_MC_CLK_RATIO 0 | ||
| 451 | #define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) | ||
| 452 | #define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) | ||
| 453 | #define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) | ||
| 454 | |||
| 455 | #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) | ||
| 456 | |||
| 457 | #define S_BCM1480_MC_REF_RATE 8 | ||
| 458 | #define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) | ||
| 459 | #define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) | ||
| 460 | #define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) | ||
| 461 | |||
| 462 | #define K_BCM1480_MC_REF_RATE_100MHz 0x31 | ||
| 463 | #define K_BCM1480_MC_REF_RATE_200MHz 0x62 | ||
| 464 | #define K_BCM1480_MC_REF_RATE_400MHz 0xC4 | ||
| 465 | |||
| 466 | #define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) | ||
| 467 | #define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) | ||
| 468 | #define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) | ||
| 469 | #define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz | ||
| 470 | |||
| 471 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 472 | #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) | ||
| 473 | #endif | ||
| 474 | |||
| 475 | /* | ||
| 476 | * ODT Register (Table 99) | ||
| 477 | */ | ||
| 478 | |||
| 479 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 480 | #define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) | ||
| 481 | #define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) | ||
| 482 | #define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) | ||
| 483 | #define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) | ||
| 484 | #define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) | ||
| 485 | #define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) | ||
| 486 | #define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) | ||
| 487 | #define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) | ||
| 488 | #define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) | ||
| 489 | #define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) | ||
| 490 | #define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) | ||
| 491 | #define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) | ||
| 492 | #define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) | ||
| 493 | #define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) | ||
| 494 | #define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) | ||
| 495 | #define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) | ||
| 496 | #define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) | ||
| 497 | #define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) | ||
| 498 | #define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) | ||
| 499 | #define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) | ||
| 500 | #define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) | ||
| 501 | #define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) | ||
| 502 | #define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) | ||
| 503 | #define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) | ||
| 504 | #define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) | ||
| 505 | #define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) | ||
| 506 | #define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) | ||
| 507 | #define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) | ||
| 508 | #define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) | ||
| 509 | #define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) | ||
| 510 | #define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) | ||
| 511 | #define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) | ||
| 512 | |||
| 513 | #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) | ||
| 514 | #endif | ||
| 515 | |||
| 516 | /* | ||
| 517 | * Memory DLL Configuration Register (Table 93) | ||
| 518 | */ | ||
| 519 | |||
| 520 | #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 | ||
| 521 | #define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 522 | #define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 523 | #define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 524 | #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) | ||
| 525 | |||
| 526 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 527 | #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 | ||
| 528 | #define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 529 | #define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 530 | #define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 531 | #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) | ||
| 532 | #endif | ||
| 533 | |||
| 534 | #define S_BCM1480_MC_ADDR_FINE_ADJ 8 | ||
| 535 | #define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 536 | #define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 537 | #define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 538 | #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) | ||
| 539 | |||
| 540 | #define S_BCM1480_MC_DQI_COARSE_ADJ 16 | ||
| 541 | #define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 542 | #define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 543 | #define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 544 | #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) | ||
| 545 | |||
| 546 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 547 | #define S_BCM1480_MC_DQI_FREQ_RANGE 24 | ||
| 548 | #define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 549 | #define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 550 | #define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 551 | #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) | ||
| 552 | #endif | ||
| 553 | |||
| 554 | #define S_BCM1480_MC_DQI_FINE_ADJ 24 | ||
| 555 | #define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) | ||
| 556 | #define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) | ||
| 557 | #define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) | ||
| 558 | #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) | ||
| 559 | |||
| 560 | #define S_BCM1480_MC_DQO_COARSE_ADJ 32 | ||
| 561 | #define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 562 | #define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 563 | #define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 564 | #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) | ||
| 565 | |||
| 566 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 567 | #define S_BCM1480_MC_DQO_FREQ_RANGE 40 | ||
| 568 | #define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 569 | #define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 570 | #define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 571 | #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) | ||
| 572 | #endif | ||
| 573 | |||
| 574 | #define S_BCM1480_MC_DQO_FINE_ADJ 40 | ||
| 575 | #define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) | ||
| 576 | #define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) | ||
| 577 | #define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) | ||
| 578 | #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) | ||
| 579 | |||
| 580 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 581 | #define S_BCM1480_MC_DLL_PDSEL 44 | ||
| 582 | #define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) | ||
| 583 | #define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) | ||
| 584 | #define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) | ||
| 585 | #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) | ||
| 586 | |||
| 587 | #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) | ||
| 588 | #define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) | ||
| 589 | #endif | ||
| 590 | |||
| 591 | #define S_BCM1480_MC_DLL_DEFAULT 48 | ||
| 592 | #define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) | ||
| 593 | #define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) | ||
| 594 | #define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) | ||
| 595 | #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) | ||
| 596 | |||
| 597 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 598 | #define S_BCM1480_MC_DLL_REGCTRL 54 | ||
| 599 | #define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) | ||
| 600 | #define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) | ||
| 601 | #define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) | ||
| 602 | #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) | ||
| 603 | #endif | ||
| 604 | |||
| 605 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 606 | #define S_BCM1480_MC_DLL_FREQ_RANGE 56 | ||
| 607 | #define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 608 | #define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 609 | #define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 610 | #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) | ||
| 611 | #endif | ||
| 612 | |||
| 613 | #define S_BCM1480_MC_DLL_STEP_SIZE 56 | ||
| 614 | #define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) | ||
| 615 | #define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) | ||
| 616 | #define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) | ||
| 617 | #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) | ||
| 618 | |||
| 619 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 620 | #define S_BCM1480_MC_DLL_BGCTRL 60 | ||
| 621 | #define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) | ||
| 622 | #define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) | ||
| 623 | #define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) | ||
| 624 | #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) | ||
| 625 | #endif | ||
| 626 | |||
| 627 | #define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) | ||
| 628 | |||
| 629 | /* | ||
| 630 | * Memory Drive Configuration Register (Table 94) | ||
| 631 | */ | ||
| 632 | |||
| 633 | #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 | ||
| 634 | #define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 635 | #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 636 | #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 637 | |||
| 638 | #define S_BCM1480_MC_RTT_BYP_PULLUP 6 | ||
| 639 | #define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 640 | #define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 641 | #define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 642 | |||
| 643 | #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) | ||
| 644 | #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) | ||
| 645 | |||
| 646 | #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 | ||
| 647 | #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 648 | #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 649 | #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 650 | |||
| 651 | #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 | ||
| 652 | #define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 653 | #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 654 | #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 655 | |||
| 656 | #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 | ||
| 657 | #define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 658 | #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 659 | #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 660 | |||
| 661 | #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 | ||
| 662 | #define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 663 | #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 664 | #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 665 | |||
| 666 | #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) | ||
| 667 | #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) | ||
| 668 | |||
| 669 | #define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) | ||
| 670 | #define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) | ||
| 671 | #define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) | ||
| 672 | |||
| 673 | #define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) | ||
| 674 | #define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) | ||
| 675 | #define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) | ||
| 676 | #define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) | ||
| 677 | #define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) | ||
| 678 | |||
| 679 | /* | ||
| 680 | * ECC Test Data Register (Table 95) | ||
| 681 | */ | ||
| 682 | |||
| 683 | #define S_BCM1480_MC_DATA_INVERT 0 | ||
| 684 | #define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) | ||
| 685 | |||
| 686 | /* | ||
| 687 | * ECC Test ECC Register (Table 96) | ||
| 688 | */ | ||
| 689 | |||
| 690 | #define S_BCM1480_MC_ECC_INVERT 0 | ||
| 691 | #define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) | ||
| 692 | |||
| 693 | /* | ||
| 694 | * SDRAM Timing Register (Table 97) | ||
| 695 | */ | ||
| 696 | |||
| 697 | #define S_BCM1480_MC_tRCD 0 | ||
| 698 | #define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) | ||
| 699 | #define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) | ||
| 700 | #define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) | ||
| 701 | #define K_BCM1480_MC_tRCD_DEFAULT 3 | ||
| 702 | #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) | ||
| 703 | |||
| 704 | #define S_BCM1480_MC_tCL 4 | ||
| 705 | #define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) | ||
| 706 | #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) | ||
| 707 | #define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) | ||
| 708 | #define K_BCM1480_MC_tCL_DEFAULT 2 | ||
| 709 | #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) | ||
| 710 | |||
| 711 | #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) | ||
| 712 | |||
| 713 | #define S_BCM1480_MC_tWR 9 | ||
| 714 | #define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) | ||
| 715 | #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) | ||
| 716 | #define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) | ||
| 717 | #define K_BCM1480_MC_tWR_DEFAULT 2 | ||
| 718 | #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) | ||
| 719 | |||
| 720 | #define S_BCM1480_MC_tCwD 12 | ||
| 721 | #define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) | ||
| 722 | #define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) | ||
| 723 | #define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) | ||
| 724 | #define K_BCM1480_MC_tCwD_DEFAULT 1 | ||
| 725 | #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) | ||
| 726 | |||
| 727 | #define S_BCM1480_MC_tRP 16 | ||
| 728 | #define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) | ||
| 729 | #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) | ||
| 730 | #define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) | ||
| 731 | #define K_BCM1480_MC_tRP_DEFAULT 4 | ||
| 732 | #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) | ||
| 733 | |||
| 734 | #define S_BCM1480_MC_tRRD 20 | ||
| 735 | #define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) | ||
| 736 | #define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) | ||
| 737 | #define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) | ||
| 738 | #define K_BCM1480_MC_tRRD_DEFAULT 2 | ||
| 739 | #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) | ||
| 740 | |||
| 741 | #define S_BCM1480_MC_tRCw 24 | ||
| 742 | #define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) | ||
| 743 | #define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) | ||
| 744 | #define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) | ||
| 745 | #define K_BCM1480_MC_tRCw_DEFAULT 10 | ||
| 746 | #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) | ||
| 747 | |||
| 748 | #define S_BCM1480_MC_tRCr 32 | ||
| 749 | #define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) | ||
| 750 | #define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) | ||
| 751 | #define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) | ||
| 752 | #define K_BCM1480_MC_tRCr_DEFAULT 9 | ||
| 753 | #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) | ||
| 754 | |||
| 755 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 756 | #define S_BCM1480_MC_tFAW 40 | ||
| 757 | #define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) | ||
| 758 | #define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) | ||
| 759 | #define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) | ||
| 760 | #define K_BCM1480_MC_tFAW_DEFAULT 0 | ||
| 761 | #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) | ||
| 762 | #endif | ||
| 763 | |||
| 764 | #define S_BCM1480_MC_tRFC 48 | ||
| 765 | #define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) | ||
| 766 | #define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) | ||
| 767 | #define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) | ||
| 768 | #define K_BCM1480_MC_tRFC_DEFAULT 12 | ||
| 769 | #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) | ||
| 770 | |||
| 771 | #define S_BCM1480_MC_tFIFO 56 | ||
| 772 | #define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) | ||
| 773 | #define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) | ||
| 774 | #define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) | ||
| 775 | #define K_BCM1480_MC_tFIFO_DEFAULT 0 | ||
| 776 | #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) | ||
| 777 | |||
| 778 | #define S_BCM1480_MC_tW2R 58 | ||
| 779 | #define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) | ||
| 780 | #define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) | ||
| 781 | #define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) | ||
| 782 | #define K_BCM1480_MC_tW2R_DEFAULT 1 | ||
| 783 | #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) | ||
| 784 | |||
| 785 | #define S_BCM1480_MC_tR2W 60 | ||
| 786 | #define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) | ||
| 787 | #define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) | ||
| 788 | #define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) | ||
| 789 | #define K_BCM1480_MC_tR2W_DEFAULT 0 | ||
| 790 | #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) | ||
| 791 | |||
| 792 | #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) | ||
| 793 | |||
| 794 | #define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ | ||
| 795 | V_BCM1480_MC_tFIFO_DEFAULT | \ | ||
| 796 | V_BCM1480_MC_tR2W_DEFAULT | \ | ||
| 797 | V_BCM1480_MC_tW2R_DEFAULT | \ | ||
| 798 | V_BCM1480_MC_tRFC_DEFAULT | \ | ||
| 799 | V_BCM1480_MC_tRCr_DEFAULT | \ | ||
| 800 | V_BCM1480_MC_tRCw_DEFAULT | \ | ||
| 801 | V_BCM1480_MC_tRRD_DEFAULT | \ | ||
| 802 | V_BCM1480_MC_tRP_DEFAULT | \ | ||
| 803 | V_BCM1480_MC_tCwD_DEFAULT | \ | ||
| 804 | V_BCM1480_MC_tWR_DEFAULT | \ | ||
| 805 | M_BCM1480_MC_tCrDh | \ | ||
| 806 | V_BCM1480_MC_tCL_DEFAULT | \ | ||
| 807 | V_BCM1480_MC_tRCD_DEFAULT) | ||
| 808 | |||
| 809 | /* | ||
| 810 | * SDRAM Timing Register 2 | ||
| 811 | */ | ||
| 812 | |||
| 813 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 814 | |||
| 815 | #define S_BCM1480_MC_tAL 0 | ||
| 816 | #define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) | ||
| 817 | #define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) | ||
| 818 | #define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) | ||
| 819 | #define K_BCM1480_MC_tAL_DEFAULT 0 | ||
| 820 | #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) | ||
| 821 | |||
| 822 | #define S_BCM1480_MC_tRTP 4 | ||
| 823 | #define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) | ||
| 824 | #define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) | ||
| 825 | #define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) | ||
| 826 | #define K_BCM1480_MC_tRTP_DEFAULT 2 | ||
| 827 | #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) | ||
| 828 | |||
| 829 | #define S_BCM1480_MC_tW2W 8 | ||
| 830 | #define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) | ||
| 831 | #define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) | ||
| 832 | #define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) | ||
| 833 | #define K_BCM1480_MC_tW2W_DEFAULT 0 | ||
| 834 | #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) | ||
| 835 | |||
| 836 | #define S_BCM1480_MC_tRAP 12 | ||
| 837 | #define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) | ||
| 838 | #define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) | ||
| 839 | #define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) | ||
| 840 | #define K_BCM1480_MC_tRAP_DEFAULT 0 | ||
| 841 | #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) | ||
| 842 | |||
| 843 | #endif | ||
| 844 | |||
| 845 | |||
| 846 | |||
| 847 | /* | ||
| 848 | * Global Registers: single instances per BCM1480 | ||
| 849 | */ | ||
| 850 | |||
| 851 | /* | ||
| 852 | * Global Configuration Register (Table 99) | ||
| 853 | */ | ||
| 854 | |||
| 855 | #define S_BCM1480_MC_BLK_SET_MARK 8 | ||
| 856 | #define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) | ||
| 857 | #define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) | ||
| 858 | #define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) | ||
| 859 | |||
| 860 | #define S_BCM1480_MC_BLK_CLR_MARK 12 | ||
| 861 | #define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) | ||
| 862 | #define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) | ||
| 863 | #define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) | ||
| 864 | |||
| 865 | #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) | ||
| 866 | |||
| 867 | #define S_BCM1480_MC_MAX_AGE 20 | ||
| 868 | #define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) | ||
| 869 | #define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) | ||
| 870 | #define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) | ||
| 871 | |||
| 872 | #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) | ||
| 873 | #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) | ||
| 874 | #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) | ||
| 875 | |||
| 876 | #define S_BCM1480_MC_SLEW 33 | ||
| 877 | #define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) | ||
| 878 | #define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) | ||
| 879 | #define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) | ||
| 880 | |||
| 881 | #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) | ||
| 882 | |||
| 883 | /* | ||
| 884 | * Global Channel Interleave Register (Table 100) | ||
| 885 | */ | ||
| 886 | |||
| 887 | #define S_BCM1480_MC_INTLV0 0 | ||
| 888 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) | ||
| 889 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) | ||
| 890 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) | ||
| 891 | |||
| 892 | #define S_BCM1480_MC_INTLV1 8 | ||
| 893 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) | ||
| 894 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) | ||
| 895 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) | ||
| 896 | |||
| 897 | #define S_BCM1480_MC_INTLV_MODE 16 | ||
| 898 | #define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) | ||
| 899 | #define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) | ||
| 900 | #define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) | ||
| 901 | |||
| 902 | #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 | ||
| 903 | #define K_BCM1480_MC_INTLV_MODE_01 0x1 | ||
| 904 | #define K_BCM1480_MC_INTLV_MODE_23 0x2 | ||
| 905 | #define K_BCM1480_MC_INTLV_MODE_01_23 0x3 | ||
| 906 | #define K_BCM1480_MC_INTLV_MODE_0123 0x4 | ||
| 907 | |||
| 908 | #define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) | ||
| 909 | #define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) | ||
| 910 | #define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) | ||
| 911 | #define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) | ||
| 912 | #define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) | ||
| 913 | |||
| 914 | /* | ||
| 915 | * ECC Status Register | ||
| 916 | */ | ||
| 917 | |||
| 918 | #define S_BCM1480_MC_ECC_ERR_ADDR 0 | ||
| 919 | #define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) | ||
| 920 | #define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) | ||
| 921 | #define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) | ||
| 922 | |||
| 923 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 924 | #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) | ||
| 925 | #endif | ||
| 926 | |||
| 927 | #define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) | ||
| 928 | #define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) | ||
| 929 | #define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) | ||
| 930 | |||
| 931 | /* | ||
| 932 | * Global ECC Address Register (Table 102) | ||
| 933 | */ | ||
| 934 | |||
| 935 | #define S_BCM1480_MC_ECC_CORR_ADDR 0 | ||
| 936 | #define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) | ||
| 937 | #define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) | ||
| 938 | #define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) | ||
| 939 | |||
| 940 | /* | ||
| 941 | * Global ECC Correction Register (Table 103) | ||
| 942 | */ | ||
| 943 | |||
| 944 | #define S_BCM1480_MC_ECC_CORRECT 0 | ||
| 945 | #define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) | ||
| 946 | #define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) | ||
| 947 | #define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) | ||
| 948 | |||
| 949 | /* | ||
| 950 | * Global ECC Performance Counters Control Register (Table 104) | ||
| 951 | */ | ||
| 952 | |||
| 953 | #define S_BCM1480_MC_CHANNEL_SELECT 0 | ||
| 954 | #define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) | ||
| 955 | #define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) | ||
| 956 | #define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) | ||
| 957 | #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 | ||
| 958 | #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 | ||
| 959 | #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 | ||
| 960 | #define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 | ||
| 961 | |||
| 962 | #endif /* _BCM1480_MC_H */ | ||
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h new file mode 100644 index 000000000000..c2dd2fe3047c --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_regs.h | |||
| @@ -0,0 +1,869 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Register Definitions File: bcm1480_regs.h | ||
| 5 | * | ||
| 6 | * This module contains the addresses of the on-chip peripherals | ||
| 7 | * on the BCM1280 and BCM1480. | ||
| 8 | * | ||
| 9 | * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _BCM1480_REGS_H | ||
| 33 | #define _BCM1480_REGS_H | ||
| 34 | |||
| 35 | #include "sb1250_defs.h" | ||
| 36 | |||
| 37 | /* ********************************************************************* | ||
| 38 | * Pull in the BCM1250's registers since a great deal of the 1480's | ||
| 39 | * functions are the same as the BCM1250. | ||
| 40 | ********************************************************************* */ | ||
| 41 | |||
| 42 | #include "sb1250_regs.h" | ||
| 43 | |||
| 44 | |||
| 45 | /* ********************************************************************* | ||
| 46 | * Some general notes: | ||
| 47 | * | ||
| 48 | * Register addresses are grouped by function and follow the order | ||
| 49 | * of the User Manual. | ||
| 50 | * | ||
| 51 | * For the most part, when there is more than one peripheral | ||
| 52 | * of the same type on the SOC, the constants below will be | ||
| 53 | * offsets from the base of each peripheral. For example, | ||
| 54 | * the MAC registers are described as offsets from the first | ||
| 55 | * MAC register, and there will be a MAC_REGISTER() macro | ||
| 56 | * to calculate the base address of a given MAC. | ||
| 57 | * | ||
| 58 | * The information in this file is based on the BCM1X55/BCM1X80 | ||
| 59 | * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. | ||
| 60 | * | ||
| 61 | * This file is basically a "what's new" header file. Since the | ||
| 62 | * BCM1250 and the new BCM1480 (and derivatives) share many common | ||
| 63 | * features, this file contains only what's new or changed from | ||
| 64 | * the 1250. (above, you can see that we include the 1250 symbols | ||
| 65 | * to get the base functionality). | ||
| 66 | * | ||
| 67 | * In software, be sure to use the correct symbols, particularly | ||
| 68 | * for blocks that are different between the two chip families. | ||
| 69 | * All BCM1480-specific symbols have _BCM1480_ in their names, | ||
| 70 | * and all BCM1250-specific and "base" functions that are common in | ||
| 71 | * both chips have no special names (this is for compatibility with | ||
| 72 | * older include files). Therefore, if you're working with the | ||
| 73 | * SCD, which is very different on each chip, A_SCD_xxx implies | ||
| 74 | * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 | ||
| 75 | * version. | ||
| 76 | ********************************************************************* */ | ||
| 77 | |||
| 78 | |||
| 79 | /* ********************************************************************* | ||
| 80 | * Memory Controller Registers (Section 6) | ||
| 81 | ********************************************************************* */ | ||
| 82 | |||
| 83 | #define A_BCM1480_MC_BASE_0 0x0010050000 | ||
| 84 | #define A_BCM1480_MC_BASE_1 0x0010051000 | ||
| 85 | #define A_BCM1480_MC_BASE_2 0x0010052000 | ||
| 86 | #define A_BCM1480_MC_BASE_3 0x0010053000 | ||
| 87 | #define BCM1480_MC_REGISTER_SPACING 0x1000 | ||
| 88 | |||
| 89 | #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) | ||
| 90 | #define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) | ||
| 91 | |||
| 92 | #define R_BCM1480_MC_CONFIG 0x0000000100 | ||
| 93 | #define R_BCM1480_MC_CS_START 0x0000000120 | ||
| 94 | #define R_BCM1480_MC_CS_END 0x0000000140 | ||
| 95 | #define S_BCM1480_MC_CS_STARTEND 24 | ||
| 96 | |||
| 97 | #define R_BCM1480_MC_CS01_ROW0 0x0000000180 | ||
| 98 | #define R_BCM1480_MC_CS01_ROW1 0x00000001A0 | ||
| 99 | #define R_BCM1480_MC_CS23_ROW0 0x0000000200 | ||
| 100 | #define R_BCM1480_MC_CS23_ROW1 0x0000000220 | ||
| 101 | #define R_BCM1480_MC_CS01_COL0 0x0000000280 | ||
| 102 | #define R_BCM1480_MC_CS01_COL1 0x00000002A0 | ||
| 103 | #define R_BCM1480_MC_CS23_COL0 0x0000000300 | ||
| 104 | #define R_BCM1480_MC_CS23_COL1 0x0000000320 | ||
| 105 | |||
| 106 | #define R_BCM1480_MC_CSX_BASE 0x0000000180 | ||
| 107 | #define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ | ||
| 108 | #define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ | ||
| 109 | #define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ | ||
| 110 | #define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ | ||
| 111 | #define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ | ||
| 112 | |||
| 113 | #define R_BCM1480_MC_CS01_BA 0x0000000380 | ||
| 114 | #define R_BCM1480_MC_CS23_BA 0x00000003A0 | ||
| 115 | #define R_BCM1480_MC_DRAMCMD 0x0000000400 | ||
| 116 | #define R_BCM1480_MC_DRAMMODE 0x0000000420 | ||
| 117 | #define R_BCM1480_MC_CLOCK_CFG 0x0000000440 | ||
| 118 | #define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG | ||
| 119 | #define R_BCM1480_MC_TEST_DATA 0x0000000480 | ||
| 120 | #define R_BCM1480_MC_TEST_ECC 0x00000004A0 | ||
| 121 | #define R_BCM1480_MC_TIMING1 0x00000004C0 | ||
| 122 | #define R_BCM1480_MC_TIMING2 0x00000004E0 | ||
| 123 | #define R_BCM1480_MC_DLL_CFG 0x0000000500 | ||
| 124 | #define R_BCM1480_MC_DRIVE_CFG 0x0000000520 | ||
| 125 | |||
| 126 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 127 | #define R_BCM1480_MC_ODT 0x0000000460 | ||
| 128 | #define R_BCM1480_MC_ECC_STATUS 0x0000000540 | ||
| 129 | #endif | ||
| 130 | |||
| 131 | /* Global registers (single instance) */ | ||
| 132 | #define A_BCM1480_MC_GLB_CONFIG 0x0010054100 | ||
| 133 | #define A_BCM1480_MC_GLB_INTLV 0x0010054120 | ||
| 134 | #define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 | ||
| 135 | #define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 | ||
| 136 | #define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 | ||
| 137 | #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 | ||
| 138 | |||
| 139 | /* ********************************************************************* | ||
| 140 | * L2 Cache Control Registers (Section 5) | ||
| 141 | ********************************************************************* */ | ||
| 142 | |||
| 143 | #define A_BCM1480_L2_BASE 0x0010040000 | ||
| 144 | |||
| 145 | #define A_BCM1480_L2_READ_TAG 0x0010040018 | ||
| 146 | #define A_BCM1480_L2_ECC_TAG 0x0010040038 | ||
| 147 | #define A_BCM1480_L2_MISC0_VALUE 0x0010040058 | ||
| 148 | #define A_BCM1480_L2_MISC1_VALUE 0x0010040078 | ||
| 149 | #define A_BCM1480_L2_MISC2_VALUE 0x0010040098 | ||
| 150 | #define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ | ||
| 151 | #define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ | ||
| 152 | #define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) | ||
| 153 | #define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ | ||
| 154 | #define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ | ||
| 155 | #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) | ||
| 156 | #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) | ||
| 157 | #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) | ||
| 158 | #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) | ||
| 159 | #define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ | ||
| 160 | #define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ | ||
| 161 | #define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ | ||
| 162 | #define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ | ||
| 163 | #define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ | ||
| 164 | #define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ | ||
| 165 | #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) | ||
| 166 | #define A_BCM1480_L2_BANK_BASE 0x00D0300000 | ||
| 167 | #define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) | ||
| 168 | #define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 | ||
| 169 | |||
| 170 | |||
| 171 | /* ********************************************************************* | ||
| 172 | * PCI-X Interface Registers (Section 7) | ||
| 173 | ********************************************************************* */ | ||
| 174 | |||
| 175 | #define A_BCM1480_PCI_BASE 0x0010061400 | ||
| 176 | |||
| 177 | #define A_BCM1480_PCI_RESET 0x0010061400 | ||
| 178 | #define A_BCM1480_PCI_DLL 0x0010061500 | ||
| 179 | |||
| 180 | #define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 | ||
| 181 | |||
| 182 | /* ********************************************************************* | ||
| 183 | * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) | ||
| 184 | ********************************************************************* */ | ||
| 185 | |||
| 186 | /* No register changes with Rev.C BCM1250, but one additional MAC */ | ||
| 187 | |||
| 188 | #define A_BCM1480_MAC_BASE_2 0x0010066000 | ||
| 189 | |||
| 190 | #ifndef A_MAC_BASE_2 | ||
| 191 | #define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 | ||
| 192 | #endif | ||
| 193 | |||
| 194 | #define A_BCM1480_MAC_BASE_3 0x0010067000 | ||
| 195 | #define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 | ||
| 196 | |||
| 197 | #define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 | ||
| 198 | |||
| 199 | #ifndef R_MAC_DMA_OODPKTLOST | ||
| 200 | #define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST | ||
| 201 | #endif | ||
| 202 | |||
| 203 | |||
| 204 | /* ********************************************************************* | ||
| 205 | * DUART Registers (Section 14) | ||
| 206 | ********************************************************************* */ | ||
| 207 | |||
| 208 | /* No significant differences from BCM1250, two DUARTs */ | ||
| 209 | |||
| 210 | /* Conventions, per user manual: | ||
| 211 | * DUART generic, channels A,B,C,D | ||
| 212 | * DUART0 implementing channels A,B | ||
| 213 | * DUART1 inplementing channels C,D | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define BCM1480_DUART_NUM_PORTS 4 | ||
| 217 | |||
| 218 | #define A_BCM1480_DUART0 0x0010060000 | ||
| 219 | #define A_BCM1480_DUART1 0x0010060400 | ||
| 220 | #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) | ||
| 221 | |||
| 222 | #define BCM1480_DUART_CHANREG_SPACING 0x100 | ||
| 223 | #define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ | ||
| 224 | + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ | ||
| 225 | + (reg)) | ||
| 226 | #define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) | ||
| 227 | |||
| 228 | #define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) | ||
| 229 | #define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) | ||
| 230 | |||
| 231 | #define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) | ||
| 232 | #define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) | ||
| 233 | |||
| 234 | /* | ||
| 235 | * These constants are the absolute addresses. | ||
| 236 | */ | ||
| 237 | |||
| 238 | #define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 | ||
| 239 | #define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 | ||
| 240 | #define A_BCM1480_DUART_STATUS_C 0x0010060420 | ||
| 241 | #define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 | ||
| 242 | #define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 | ||
| 243 | #define A_BCM1480_DUART_CMD_C 0x0010060450 | ||
| 244 | #define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 | ||
| 245 | #define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 | ||
| 246 | #define A_BCM1480_DUART_OPCR_C 0x0010060480 | ||
| 247 | #define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 | ||
| 248 | |||
| 249 | #define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 | ||
| 250 | #define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 | ||
| 251 | #define A_BCM1480_DUART_STATUS_D 0x0010060520 | ||
| 252 | #define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 | ||
| 253 | #define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 | ||
| 254 | #define A_BCM1480_DUART_CMD_D 0x0010060550 | ||
| 255 | #define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 | ||
| 256 | #define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 | ||
| 257 | #define A_BCM1480_DUART_OPCR_D 0x0010060580 | ||
| 258 | #define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 | ||
| 259 | |||
| 260 | #define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 | ||
| 261 | #define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 | ||
| 262 | #define A_BCM1480_DUART_ISR_C 0x0010060620 | ||
| 263 | #define A_BCM1480_DUART_IMR_C 0x0010060630 | ||
| 264 | #define A_BCM1480_DUART_ISR_D 0x0010060640 | ||
| 265 | #define A_BCM1480_DUART_IMR_D 0x0010060650 | ||
| 266 | #define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 | ||
| 267 | #define A_BCM1480_DUART_OPCR_CD 0x0010060670 | ||
| 268 | #define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 | ||
| 269 | #define A_BCM1480_DUART_ISR_CD 0x0010060690 | ||
| 270 | #define A_BCM1480_DUART_IMR_CD 0x00100606A0 | ||
| 271 | #define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 | ||
| 272 | #define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 | ||
| 273 | #define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 | ||
| 274 | #define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 | ||
| 275 | |||
| 276 | |||
| 277 | /* ********************************************************************* | ||
| 278 | * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) | ||
| 279 | ********************************************************************* */ | ||
| 280 | |||
| 281 | #define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 | ||
| 282 | #define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 | ||
| 283 | |||
| 284 | /* ********************************************************************* | ||
| 285 | * GPIO Registers (Section 17) | ||
| 286 | ********************************************************************* */ | ||
| 287 | |||
| 288 | /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ | ||
| 289 | |||
| 290 | #define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 | ||
| 291 | #define R_BCM1480_GPIO_INT_ADD_TYPE (-8) | ||
| 292 | |||
| 293 | #define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE | ||
| 294 | #define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE | ||
| 295 | |||
| 296 | /* ********************************************************************* | ||
| 297 | * SMBus Registers (Section 18) | ||
| 298 | ********************************************************************* */ | ||
| 299 | |||
| 300 | /* No changes from BCM1250 */ | ||
| 301 | |||
| 302 | /* ********************************************************************* | ||
| 303 | * Timer Registers (Sections 4.6) | ||
| 304 | ********************************************************************* */ | ||
| 305 | |||
| 306 | /* BCM1480 has two additional watchdogs */ | ||
| 307 | |||
| 308 | /* Watchdog timers */ | ||
| 309 | |||
| 310 | #define A_BCM1480_SCD_WDOG_2 0x0010022050 | ||
| 311 | #define A_BCM1480_SCD_WDOG_3 0x0010022150 | ||
| 312 | |||
| 313 | #define BCM1480_SCD_NUM_WDOGS 4 | ||
| 314 | |||
| 315 | #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) | ||
| 316 | #define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) | ||
| 317 | |||
| 318 | #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 | ||
| 319 | #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 | ||
| 320 | #define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 | ||
| 321 | |||
| 322 | #define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 | ||
| 323 | #define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 | ||
| 324 | #define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 | ||
| 325 | |||
| 326 | /* BCM1480 has two additional compare registers */ | ||
| 327 | |||
| 328 | #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT | ||
| 329 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 | ||
| 330 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 | ||
| 331 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 | ||
| 332 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 | ||
| 333 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 | ||
| 334 | |||
| 335 | /* ********************************************************************* | ||
| 336 | * System Control Registers (Section 4.2) | ||
| 337 | ********************************************************************* */ | ||
| 338 | |||
| 339 | /* Scratch register in different place */ | ||
| 340 | |||
| 341 | #define A_BCM1480_SCD_SCRATCH 0x100200A0 | ||
| 342 | |||
| 343 | /* ********************************************************************* | ||
| 344 | * System Address Trap Registers (Section 4.9) | ||
| 345 | ********************************************************************* */ | ||
| 346 | |||
| 347 | /* No changes from BCM1250 */ | ||
| 348 | |||
| 349 | /* ********************************************************************* | ||
| 350 | * System Interrupt Mapper Registers (Sections 4.3-4.5) | ||
| 351 | ********************************************************************* */ | ||
| 352 | |||
| 353 | #define A_BCM1480_IMR_CPU0_BASE 0x0010020000 | ||
| 354 | #define A_BCM1480_IMR_CPU1_BASE 0x0010022000 | ||
| 355 | #define A_BCM1480_IMR_CPU2_BASE 0x0010024000 | ||
| 356 | #define A_BCM1480_IMR_CPU3_BASE 0x0010026000 | ||
| 357 | #define BCM1480_IMR_REGISTER_SPACING 0x2000 | ||
| 358 | #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 | ||
| 359 | |||
| 360 | #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) | ||
| 361 | #define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) | ||
| 362 | |||
| 363 | /* Most IMR registers are 128 bits, implemented as non-contiguous | ||
| 364 | 64-bit registers high (_H) and low (_L) */ | ||
| 365 | #define BCM1480_IMR_HL_SPACING 0x1000 | ||
| 366 | |||
| 367 | #define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 | ||
| 368 | #define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 | ||
| 369 | #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 | ||
| 370 | #define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 | ||
| 371 | #define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 | ||
| 372 | #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 | ||
| 373 | #define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 | ||
| 374 | #define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 | ||
| 375 | #define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 | ||
| 376 | #define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 | ||
| 377 | #define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 | ||
| 378 | #define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 | ||
| 379 | #define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 | ||
| 380 | #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 | ||
| 381 | #define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 | ||
| 382 | #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 | ||
| 383 | #define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 | ||
| 384 | |||
| 385 | #define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 | ||
| 386 | #define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 | ||
| 387 | #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 | ||
| 388 | #define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 | ||
| 389 | #define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 | ||
| 390 | #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 | ||
| 391 | #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 | ||
| 392 | #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 | ||
| 393 | |||
| 394 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 | ||
| 395 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 | ||
| 396 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 | ||
| 397 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 | ||
| 398 | #define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 | ||
| 399 | |||
| 400 | #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ | ||
| 401 | (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) | ||
| 402 | #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) | ||
| 403 | |||
| 404 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ | ||
| 405 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ | ||
| 406 | |||
| 407 | /* ********************************************************************* | ||
| 408 | * System Performance Counter Registers (Section 4.7) | ||
| 409 | ********************************************************************* */ | ||
| 410 | |||
| 411 | /* BCM1480 has four more performance counter registers, and two control | ||
| 412 | registers. */ | ||
| 413 | |||
| 414 | #define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 | ||
| 415 | |||
| 416 | #define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 | ||
| 417 | #define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 | ||
| 418 | #define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 | ||
| 419 | #define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 | ||
| 420 | |||
| 421 | #define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 | ||
| 422 | #define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 | ||
| 423 | #define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 | ||
| 424 | #define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 | ||
| 425 | |||
| 426 | #define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 | ||
| 427 | #define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 | ||
| 428 | #define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 | ||
| 429 | #define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 | ||
| 430 | |||
| 431 | /* ********************************************************************* | ||
| 432 | * System Bus Watcher Registers (Section 4.8) | ||
| 433 | ********************************************************************* */ | ||
| 434 | |||
| 435 | |||
| 436 | /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ | ||
| 437 | |||
| 438 | #define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 | ||
| 439 | |||
| 440 | /* ********************************************************************* | ||
| 441 | * System Debug Controller Registers (Section 19) | ||
| 442 | ********************************************************************* */ | ||
| 443 | |||
| 444 | /* Same as 1250 */ | ||
| 445 | |||
| 446 | /* ********************************************************************* | ||
| 447 | * System Trace Unit Registers (Sections 4.10) | ||
| 448 | ********************************************************************* */ | ||
| 449 | |||
| 450 | /* Same as 1250 */ | ||
| 451 | |||
| 452 | /* ********************************************************************* | ||
| 453 | * Data Mover DMA Registers (Section 10.7) | ||
| 454 | ********************************************************************* */ | ||
| 455 | |||
| 456 | /* Same as 1250 */ | ||
| 457 | |||
| 458 | |||
| 459 | /* ********************************************************************* | ||
| 460 | * HyperTransport Interface Registers (Section 8) | ||
| 461 | ********************************************************************* */ | ||
| 462 | |||
| 463 | #define BCM1480_HT_NUM_PORTS 3 | ||
| 464 | #define BCM1480_HT_PORT_SPACING 0x800 | ||
| 465 | #define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) | ||
| 466 | |||
| 467 | #define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 | ||
| 468 | #define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 | ||
| 469 | #define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 | ||
| 470 | #define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 | ||
| 471 | |||
| 472 | |||
| 473 | /* ********************************************************************* | ||
| 474 | * Node Controller Registers (Section 9) | ||
| 475 | ********************************************************************* */ | ||
| 476 | |||
| 477 | #define A_BCM1480_NC_BASE 0x00DFBD0000 | ||
| 478 | |||
| 479 | #define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 | ||
| 480 | #define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 | ||
| 481 | #define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 | ||
| 482 | #define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 | ||
| 483 | #define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 | ||
| 484 | #define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 | ||
| 485 | #define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 | ||
| 486 | |||
| 487 | #define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 | ||
| 488 | #define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 | ||
| 489 | #define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 | ||
| 490 | #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 | ||
| 491 | |||
| 492 | #define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 | ||
| 493 | #define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 | ||
| 494 | #define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 | ||
| 495 | #define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 | ||
| 496 | #define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 | ||
| 497 | #define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 | ||
| 498 | #define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 | ||
| 499 | #define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 | ||
| 500 | #define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 | ||
| 501 | #define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 | ||
| 502 | #define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 | ||
| 503 | #define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 | ||
| 504 | #define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 | ||
| 505 | |||
| 506 | #define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 | ||
| 507 | #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 | ||
| 508 | |||
| 509 | |||
| 510 | /* ********************************************************************* | ||
| 511 | * H&R Block Configuration Registers (Section 12.4) | ||
| 512 | ********************************************************************* */ | ||
| 513 | |||
| 514 | #define A_BCM1480_HR_BASE_0 0x00DF820000 | ||
| 515 | #define A_BCM1480_HR_BASE_1 0x00DF8A0000 | ||
| 516 | #define A_BCM1480_HR_BASE_2 0x00DF920000 | ||
| 517 | #define BCM1480_HR_REGISTER_SPACING 0x80000 | ||
| 518 | |||
| 519 | #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) | ||
| 520 | #define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) | ||
| 521 | |||
| 522 | #define R_BCM1480_HR_CFG 0x0000000000 | ||
| 523 | |||
| 524 | #define R_BCM1480_HR_MAPPING 0x0000010010 | ||
| 525 | |||
| 526 | #define BCM1480_HR_RULE_SPACING 0x0000000010 | ||
| 527 | #define BCM1480_HR_NUM_RULES 16 | ||
| 528 | #define BCM1480_HR_OP_OFFSET 0x0000000100 | ||
| 529 | #define BCM1480_HR_TYPE_OFFSET 0x0000000108 | ||
| 530 | #define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) | ||
| 531 | #define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) | ||
| 532 | |||
| 533 | #define BCM1480_HR_LEAF_SPACING 0x0000000010 | ||
| 534 | #define BCM1480_HR_NUM_LEAVES 10 | ||
| 535 | #define BCM1480_HR_LEAF_OFFSET 0x0000000300 | ||
| 536 | #define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) | ||
| 537 | |||
| 538 | #define R_BCM1480_HR_EX_LEAF0 0x00000003A0 | ||
| 539 | |||
| 540 | #define BCM1480_HR_PATH_SPACING 0x0000000010 | ||
| 541 | #define BCM1480_HR_NUM_PATHS 16 | ||
| 542 | #define BCM1480_HR_PATH_OFFSET 0x0000000600 | ||
| 543 | #define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) | ||
| 544 | |||
| 545 | #define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 | ||
| 546 | |||
| 547 | #define BCM1480_HR_ROUTE_SPACING 8 | ||
| 548 | #define BCM1480_HR_NUM_ROUTES 512 | ||
| 549 | #define BCM1480_HR_ROUTE_OFFSET 0x0000001000 | ||
| 550 | #define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) | ||
| 551 | |||
| 552 | |||
| 553 | /* checked to here - ehs */ | ||
| 554 | /* ********************************************************************* | ||
| 555 | * Packet Manager DMA Registers (Section 12.5) | ||
| 556 | ********************************************************************* */ | ||
| 557 | |||
| 558 | #define A_BCM1480_PM_BASE 0x0010056000 | ||
| 559 | |||
| 560 | #define A_BCM1480_PMI_LCL_0 0x0010058000 | ||
| 561 | #define A_BCM1480_PMO_LCL_0 0x001005C000 | ||
| 562 | #define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) | ||
| 563 | #define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) | ||
| 564 | |||
| 565 | #define BCM1480_PM_LCL_REGISTER_SPACING 0x100 | ||
| 566 | #define BCM1480_PM_NUM_CHANNELS 32 | ||
| 567 | |||
| 568 | #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | ||
| 569 | #define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) | ||
| 570 | #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | ||
| 571 | #define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) | ||
| 572 | |||
| 573 | #define BCM1480_PM_INT_PACKING 8 | ||
| 574 | #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 | ||
| 575 | #define BCM1480_PM_INT_NUM_FUNCTIONS 3 | ||
| 576 | |||
| 577 | /* | ||
| 578 | * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) | ||
| 579 | */ | ||
| 580 | |||
| 581 | #define R_BCM1480_PM_BASE_SIZE 0x0000000000 | ||
| 582 | #define R_BCM1480_PM_CNT 0x0000000008 | ||
| 583 | #define R_BCM1480_PM_PFCNT 0x0000000010 | ||
| 584 | #define R_BCM1480_PM_LAST 0x0000000018 | ||
| 585 | #define R_BCM1480_PM_PFINDX 0x0000000020 | ||
| 586 | #define R_BCM1480_PM_INT_WMK 0x0000000028 | ||
| 587 | #define R_BCM1480_PM_CONFIG0 0x0000000030 | ||
| 588 | #define R_BCM1480_PM_LOCALDEBUG 0x0000000078 | ||
| 589 | #define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ | ||
| 590 | #define R_BCM1480_PM_INT_CNFG 0x0000000088 | ||
| 591 | #define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 | ||
| 592 | #define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ | ||
| 593 | #define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ | ||
| 594 | |||
| 595 | /* | ||
| 596 | * Global Registers (Not Channelized) | ||
| 597 | */ | ||
| 598 | |||
| 599 | #define A_BCM1480_PMI_GLB_0 0x0010056000 | ||
| 600 | #define A_BCM1480_PMO_GLB_0 0x0010057000 | ||
| 601 | |||
| 602 | /* | ||
| 603 | * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 | ||
| 604 | */ | ||
| 605 | |||
| 606 | #define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ | ||
| 607 | |||
| 608 | #define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) | ||
| 609 | |||
| 610 | /* | ||
| 611 | * Interrupt mapping registers | ||
| 612 | */ | ||
| 613 | |||
| 614 | |||
| 615 | #define A_BCM1480_PMI_INT_0 0x0010056800 | ||
| 616 | #define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) | ||
| 617 | #define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) | ||
| 618 | #define A_BCM1480_PMO_INT_0 0x0010057800 | ||
| 619 | #define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) | ||
| 620 | #define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) | ||
| 621 | |||
| 622 | /* | ||
| 623 | * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 | ||
| 624 | */ | ||
| 625 | |||
| 626 | #define R_BCM1480_PM_INT_ST 0x0000000000 | ||
| 627 | #define R_BCM1480_PM_INT_MSK 0x0000000040 | ||
| 628 | #define R_BCM1480_PM_INT_CLR 0x0000000080 | ||
| 629 | #define R_BCM1480_PM_MRGD_INT 0x00000000C0 | ||
| 630 | |||
| 631 | /* | ||
| 632 | * Debug registers (global) | ||
| 633 | */ | ||
| 634 | |||
| 635 | #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 | ||
| 636 | #define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 | ||
| 637 | #define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 | ||
| 638 | #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 | ||
| 639 | #define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 | ||
| 640 | #define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 | ||
| 641 | |||
| 642 | /* ********************************************************************* | ||
| 643 | * Switch performance counters | ||
| 644 | ********************************************************************* */ | ||
| 645 | |||
| 646 | #define A_BCM1480_SWPERF_CFG 0xdfb91800 | ||
| 647 | #define A_BCM1480_SWPERF_CNT0 0xdfb91880 | ||
| 648 | #define A_BCM1480_SWPERF_CNT1 0xdfb91888 | ||
| 649 | #define A_BCM1480_SWPERF_CNT2 0xdfb91890 | ||
| 650 | #define A_BCM1480_SWPERF_CNT3 0xdfb91898 | ||
| 651 | |||
| 652 | |||
| 653 | /* ********************************************************************* | ||
| 654 | * Switch Trace Unit | ||
| 655 | ********************************************************************* */ | ||
| 656 | |||
| 657 | #define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 | ||
| 658 | #define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 | ||
| 659 | #define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 | ||
| 660 | #define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 | ||
| 661 | #define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 | ||
| 662 | #define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 | ||
| 663 | #define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 | ||
| 664 | |||
| 665 | #define A_BCM1480_SWTRC_CFG 0xDFB91500 | ||
| 666 | #define A_BCM1480_SWTRC_READ 0xDFB91508 | ||
| 667 | |||
| 668 | #define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 | ||
| 669 | |||
| 670 | #define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) | ||
| 671 | #define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) | ||
| 672 | #define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) | ||
| 673 | |||
| 674 | #define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) | ||
| 675 | #define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) | ||
| 676 | #define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) | ||
| 677 | #define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) | ||
| 678 | |||
| 679 | |||
| 680 | |||
| 681 | /* ********************************************************************* | ||
| 682 | * High-Speed Port Registers (Section 13) | ||
| 683 | ********************************************************************* */ | ||
| 684 | |||
| 685 | #define A_BCM1480_HSP_BASE_0 0x00DF810000 | ||
| 686 | #define A_BCM1480_HSP_BASE_1 0x00DF890000 | ||
| 687 | #define A_BCM1480_HSP_BASE_2 0x00DF910000 | ||
| 688 | #define BCM1480_HSP_REGISTER_SPACING 0x80000 | ||
| 689 | |||
| 690 | #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) | ||
| 691 | #define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) | ||
| 692 | |||
| 693 | #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 | ||
| 694 | #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 | ||
| 695 | #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 | ||
| 696 | #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 | ||
| 697 | #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 | ||
| 698 | #define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 | ||
| 699 | |||
| 700 | #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 | ||
| 701 | #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 | ||
| 702 | |||
| 703 | #define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 | ||
| 704 | #define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 | ||
| 705 | #define R_BCM1480_HSP_RX_TEST 0x0000000810 | ||
| 706 | #define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 | ||
| 707 | #define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 | ||
| 708 | #define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 | ||
| 709 | #define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 | ||
| 710 | #define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 | ||
| 711 | |||
| 712 | #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 | ||
| 713 | |||
| 714 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 | ||
| 715 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 | ||
| 716 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 | ||
| 717 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 | ||
| 718 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 | ||
| 719 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 | ||
| 720 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 | ||
| 721 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 | ||
| 722 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) | ||
| 723 | |||
| 724 | /* XXX Following registers were shuffled. Renamed/renumbered per errata. */ | ||
| 725 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 | ||
| 726 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 | ||
| 727 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 | ||
| 728 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 | ||
| 729 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 | ||
| 730 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 | ||
| 731 | |||
| 732 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 | ||
| 733 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 | ||
| 734 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 | ||
| 735 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 | ||
| 736 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 | ||
| 737 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 | ||
| 738 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 | ||
| 739 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 | ||
| 740 | #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) | ||
| 741 | |||
| 742 | #define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 | ||
| 743 | #define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 | ||
| 744 | #define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 | ||
| 745 | #define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 | ||
| 746 | #define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 | ||
| 747 | #define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 | ||
| 748 | #define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 | ||
| 749 | |||
| 750 | #define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 | ||
| 751 | #define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 | ||
| 752 | #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 | ||
| 753 | |||
| 754 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 | ||
| 755 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 | ||
| 756 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 | ||
| 757 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 | ||
| 758 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 | ||
| 759 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 | ||
| 760 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 | ||
| 761 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 | ||
| 762 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) | ||
| 763 | #define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 | ||
| 764 | #define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 | ||
| 765 | #define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 | ||
| 766 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 | ||
| 767 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 | ||
| 768 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 | ||
| 769 | |||
| 770 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 | ||
| 771 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 | ||
| 772 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 | ||
| 773 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 | ||
| 774 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) | ||
| 775 | #define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 | ||
| 776 | #define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 | ||
| 777 | |||
| 778 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 | ||
| 779 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 | ||
| 780 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 | ||
| 781 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 | ||
| 782 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) | ||
| 783 | #define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 | ||
| 784 | #define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 | ||
| 785 | |||
| 786 | #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 | ||
| 787 | #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 | ||
| 788 | |||
| 789 | #define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 | ||
| 790 | #define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 | ||
| 791 | #define R_BCM1480_HSP_TX_TEST 0x0000040810 | ||
| 792 | |||
| 793 | #define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 | ||
| 794 | #define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 | ||
| 795 | #define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 | ||
| 796 | #define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 | ||
| 797 | #define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 | ||
| 798 | #define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 | ||
| 799 | #define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 | ||
| 800 | |||
| 801 | #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 | ||
| 802 | #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 | ||
| 803 | |||
| 804 | #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 | ||
| 805 | #define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) | ||
| 806 | |||
| 807 | |||
| 808 | |||
| 809 | /* ********************************************************************* | ||
| 810 | * Physical Address Map (Table 10 and Figure 7) | ||
| 811 | ********************************************************************* */ | ||
| 812 | |||
| 813 | #define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) | ||
| 814 | #define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) | ||
| 815 | #define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) | ||
| 816 | #define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) | ||
| 817 | #define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) | ||
| 818 | #define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) | ||
| 819 | #define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) | ||
| 820 | #define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) | ||
| 821 | #define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) | ||
| 822 | #define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) | ||
| 823 | #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) | ||
| 824 | #define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) | ||
| 825 | #define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) | ||
| 826 | #define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) | ||
| 827 | #define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) | ||
| 828 | #define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) | ||
| 829 | #define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) | ||
| 830 | #define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) | ||
| 831 | #define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) | ||
| 832 | #define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) | ||
| 833 | #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) | ||
| 834 | #define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) | ||
| 835 | #define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) | ||
| 836 | #define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) | ||
| 837 | #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) | ||
| 838 | #define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) | ||
| 839 | #define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) | ||
| 840 | #define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) | ||
| 841 | #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) | ||
| 842 | #define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) | ||
| 843 | #define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) | ||
| 844 | #define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) | ||
| 845 | #define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) | ||
| 846 | #define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) | ||
| 847 | #define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) | ||
| 848 | #define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) | ||
| 849 | #define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) | ||
| 850 | #define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) | ||
| 851 | |||
| 852 | |||
| 853 | /* ********************************************************************* | ||
| 854 | * L2 Cache as RAM (Table 54) | ||
| 855 | ********************************************************************* */ | ||
| 856 | |||
| 857 | #define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) | ||
| 858 | #define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 | ||
| 859 | #define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) | ||
| 860 | #define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) | ||
| 861 | #define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) | ||
| 862 | #define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) | ||
| 863 | #define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) | ||
| 864 | #define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) | ||
| 865 | #define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) | ||
| 866 | #define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) | ||
| 867 | #define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) | ||
| 868 | |||
| 869 | #endif /* _BCM1480_REGS_H */ | ||
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h new file mode 100644 index 000000000000..648bed96780f --- /dev/null +++ b/include/asm-mips/sibyte/bcm1480_scd.h | |||
| @@ -0,0 +1,436 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1400 Board Support Package | ||
| 3 | * | ||
| 4 | * SCD Constants and Macros File: bcm1480_scd.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the System Control and Debug module. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _BCM1480_SCD_H | ||
| 33 | #define _BCM1480_SCD_H | ||
| 34 | |||
| 35 | #include "sb1250_defs.h" | ||
| 36 | |||
| 37 | /* ********************************************************************* | ||
| 38 | * Pull in the BCM1250's SCD since lots of stuff is the same. | ||
| 39 | ********************************************************************* */ | ||
| 40 | |||
| 41 | #include "sb1250_scd.h" | ||
| 42 | |||
| 43 | /* ********************************************************************* | ||
| 44 | * Some general notes: | ||
| 45 | * | ||
| 46 | * This file is basically a "what's new" header file. Since the | ||
| 47 | * BCM1250 and the new BCM1480 (and derivatives) share many common | ||
| 48 | * features, this file contains only what's new or changed from | ||
| 49 | * the 1250. (above, you can see that we include the 1250 symbols | ||
| 50 | * to get the base functionality). | ||
| 51 | * | ||
| 52 | * In software, be sure to use the correct symbols, particularly | ||
| 53 | * for blocks that are different between the two chip families. | ||
| 54 | * All BCM1480-specific symbols have _BCM1480_ in their names, | ||
| 55 | * and all BCM1250-specific and "base" functions that are common in | ||
| 56 | * both chips have no special names (this is for compatibility with | ||
| 57 | * older include files). Therefore, if you're working with the | ||
| 58 | * SCD, which is very different on each chip, A_SCD_xxx implies | ||
| 59 | * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 | ||
| 60 | * version. | ||
| 61 | ********************************************************************* */ | ||
| 62 | |||
| 63 | /* ********************************************************************* | ||
| 64 | * System control/debug registers | ||
| 65 | ********************************************************************* */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * System Identification and Revision Register (Table 12) | ||
| 69 | * Register: SCD_SYSTEM_REVISION | ||
| 70 | * This register is field compatible with the 1250. | ||
| 71 | */ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * New part definitions | ||
| 75 | */ | ||
| 76 | |||
| 77 | #define K_SYS_PART_BCM1480 0x1406 | ||
| 78 | #define K_SYS_PART_BCM1280 0x1206 | ||
| 79 | #define K_SYS_PART_BCM1455 0x1407 | ||
| 80 | #define K_SYS_PART_BCM1255 0x1257 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Manufacturing Information Register (Table 14) | ||
| 84 | * Register: SCD_SYSTEM_MANUF | ||
| 85 | */ | ||
| 86 | |||
| 87 | /* | ||
| 88 | * System Configuration Register (Table 15) | ||
| 89 | * Register: SCD_SYSTEM_CFG | ||
| 90 | * Entire register is different from 1250, all new constants below | ||
| 91 | */ | ||
| 92 | |||
| 93 | #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) | ||
| 94 | #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) | ||
| 95 | #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) | ||
| 96 | #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) | ||
| 97 | #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) | ||
| 98 | #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) | ||
| 99 | |||
| 100 | #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) | ||
| 101 | #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) | ||
| 102 | #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) | ||
| 103 | #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) | ||
| 104 | |||
| 105 | #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) | ||
| 106 | #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) | ||
| 107 | #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) | ||
| 108 | #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) | ||
| 109 | |||
| 110 | #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | ||
| 111 | #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) | ||
| 112 | |||
| 113 | #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) | ||
| 114 | #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) | ||
| 115 | #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) | ||
| 116 | #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) | ||
| 117 | #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 | ||
| 118 | #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 | ||
| 119 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 | ||
| 120 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 | ||
| 121 | #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) | ||
| 122 | |||
| 123 | #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) | ||
| 124 | #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) | ||
| 125 | #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | ||
| 126 | #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) | ||
| 127 | #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) | ||
| 128 | #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) | ||
| 129 | |||
| 130 | #define S_BCM1480_SYS_CONFIG 26 | ||
| 131 | #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) | ||
| 132 | #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) | ||
| 133 | #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) | ||
| 134 | |||
| 135 | #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) | ||
| 136 | |||
| 137 | #define S_BCM1480_SYS_NODEID 47 | ||
| 138 | #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) | ||
| 139 | #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) | ||
| 140 | #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) | ||
| 141 | |||
| 142 | #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) | ||
| 143 | #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) | ||
| 144 | #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) | ||
| 145 | #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) | ||
| 146 | #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) | ||
| 147 | #define S_BCM1480_SYS_DISABLECPU0 56 | ||
| 148 | #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) | ||
| 149 | #define S_BCM1480_SYS_DISABLECPU1 57 | ||
| 150 | #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) | ||
| 151 | #define S_BCM1480_SYS_DISABLECPU2 58 | ||
| 152 | #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) | ||
| 153 | #define S_BCM1480_SYS_DISABLECPU3 59 | ||
| 154 | #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) | ||
| 155 | |||
| 156 | #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) | ||
| 157 | #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) | ||
| 158 | #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) | ||
| 159 | #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) | ||
| 160 | |||
| 161 | /* | ||
| 162 | * Scratch Register (Table 16) | ||
| 163 | * Register: SCD_SYSTEM_SCRATCH | ||
| 164 | * Same as BCM1250 | ||
| 165 | */ | ||
| 166 | |||
| 167 | |||
| 168 | /* | ||
| 169 | * Mailbox Registers (Table 17) | ||
| 170 | * Registers: SCD_MBOX_{0,1}_CPU_x | ||
| 171 | * Same as BCM1250 | ||
| 172 | */ | ||
| 173 | |||
| 174 | |||
| 175 | /* | ||
| 176 | * See bcm1480_int.h for interrupt mapper registers. | ||
| 177 | */ | ||
| 178 | |||
| 179 | |||
| 180 | /* | ||
| 181 | * Watchdog Timer Initial Count Registers (Table 23) | ||
| 182 | * Registers: SCD_WDOG_INIT_CNT_x | ||
| 183 | * | ||
| 184 | * The watchdogs are almost the same as the 1250, except | ||
| 185 | * the configuration register has more bits to control the | ||
| 186 | * other CPUs. | ||
| 187 | */ | ||
| 188 | |||
| 189 | |||
| 190 | /* | ||
| 191 | * Watchdog Timer Configuration Registers (Table 25) | ||
| 192 | * Registers: SCD_WDOG_CFG_x | ||
| 193 | */ | ||
| 194 | |||
| 195 | #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) | ||
| 196 | |||
| 197 | #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 | ||
| 198 | #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 199 | #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 200 | #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 201 | |||
| 202 | #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | ||
| 203 | #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 | ||
| 204 | #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 | ||
| 205 | #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 | ||
| 206 | #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 | ||
| 207 | #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 | ||
| 208 | #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 | ||
| 209 | |||
| 210 | |||
| 211 | #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) | ||
| 212 | |||
| 213 | /* | ||
| 214 | * General Timer Initial Count Registers (Table 26) | ||
| 215 | * Registers: SCD_TIMER_INIT_x | ||
| 216 | * | ||
| 217 | * The timer registers are the same as the BCM1250 | ||
| 218 | */ | ||
| 219 | |||
| 220 | |||
| 221 | /* | ||
| 222 | * ZBbus Count Register (Table 29) | ||
| 223 | * Register: ZBBUS_CYCLE_COUNT | ||
| 224 | * | ||
| 225 | * Same as BCM1250 | ||
| 226 | */ | ||
| 227 | |||
| 228 | /* | ||
| 229 | * ZBbus Compare Registers (Table 30) | ||
| 230 | * Registers: ZBBUS_CYCLE_CPx | ||
| 231 | * | ||
| 232 | * Same as BCM1250 | ||
| 233 | */ | ||
| 234 | |||
| 235 | |||
| 236 | /* | ||
| 237 | * System Performance Counter Configuration Register (Table 31) | ||
| 238 | * Register: PERF_CNT_CFG_0 | ||
| 239 | * | ||
| 240 | * Since the clear/enable bits are moved compared to the | ||
| 241 | * 1250 and there are more fields, this register will be BCM1480 specific. | ||
| 242 | */ | ||
| 243 | |||
| 244 | #define S_BCM1480_SPC_CFG_SRC0 0 | ||
| 245 | #define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0) | ||
| 246 | #define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0) | ||
| 247 | #define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0) | ||
| 248 | |||
| 249 | #define S_BCM1480_SPC_CFG_SRC1 8 | ||
| 250 | #define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1) | ||
| 251 | #define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1) | ||
| 252 | #define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1) | ||
| 253 | |||
| 254 | #define S_BCM1480_SPC_CFG_SRC2 16 | ||
| 255 | #define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2) | ||
| 256 | #define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2) | ||
| 257 | #define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2) | ||
| 258 | |||
| 259 | #define S_BCM1480_SPC_CFG_SRC3 24 | ||
| 260 | #define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3) | ||
| 261 | #define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3) | ||
| 262 | #define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3) | ||
| 263 | |||
| 264 | #define S_BCM1480_SPC_CFG_SRC4 32 | ||
| 265 | #define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4) | ||
| 266 | #define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4) | ||
| 267 | #define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4) | ||
| 268 | |||
| 269 | #define S_BCM1480_SPC_CFG_SRC5 40 | ||
| 270 | #define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5) | ||
| 271 | #define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5) | ||
| 272 | #define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5) | ||
| 273 | |||
| 274 | #define S_BCM1480_SPC_CFG_SRC6 48 | ||
| 275 | #define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6) | ||
| 276 | #define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6) | ||
| 277 | #define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6) | ||
| 278 | |||
| 279 | #define S_BCM1480_SPC_CFG_SRC7 56 | ||
| 280 | #define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7) | ||
| 281 | #define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7) | ||
| 282 | #define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7) | ||
| 283 | |||
| 284 | /* | ||
| 285 | * System Performance Counter Control Register (Table 32) | ||
| 286 | * Register: PERF_CNT_CFG_1 | ||
| 287 | * BCM1480 specific | ||
| 288 | */ | ||
| 289 | |||
| 290 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) | ||
| 291 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) | ||
| 292 | |||
| 293 | /* | ||
| 294 | * System Performance Counters (Table 33) | ||
| 295 | * Registers: PERF_CNT_x | ||
| 296 | */ | ||
| 297 | |||
| 298 | #define S_BCM1480_SPC_CNT_COUNT 0 | ||
| 299 | #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) | ||
| 300 | #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) | ||
| 301 | #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) | ||
| 302 | |||
| 303 | #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) | ||
| 304 | |||
| 305 | |||
| 306 | /* | ||
| 307 | * Bus Watcher Error Status Register (Tables 36, 37) | ||
| 308 | * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG | ||
| 309 | * Same as BCM1250. | ||
| 310 | */ | ||
| 311 | |||
| 312 | /* | ||
| 313 | * Bus Watcher Error Data Registers (Table 38) | ||
| 314 | * Registers: BUS_ERR_DATA_x | ||
| 315 | * Same as BCM1250. | ||
| 316 | */ | ||
| 317 | |||
| 318 | /* | ||
| 319 | * Bus Watcher L2 ECC Counter Register (Table 39) | ||
| 320 | * Register: BUS_L2_ERRORS | ||
| 321 | * Same as BCM1250. | ||
| 322 | */ | ||
| 323 | |||
| 324 | |||
| 325 | /* | ||
| 326 | * Bus Watcher Memory and I/O Error Counter Register (Table 40) | ||
| 327 | * Register: BUS_MEM_IO_ERRORS | ||
| 328 | * Same as BCM1250. | ||
| 329 | */ | ||
| 330 | |||
| 331 | |||
| 332 | /* | ||
| 333 | * Address Trap Registers | ||
| 334 | * | ||
| 335 | * Register layout same as BCM1250, almost. The bus agents | ||
| 336 | * are different, and the address trap configuration bits are | ||
| 337 | * slightly different. | ||
| 338 | */ | ||
| 339 | |||
| 340 | #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) | ||
| 341 | #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) | ||
| 342 | |||
| 343 | #define S_BCM1480_ATRAP_CFG_CNT 0 | ||
| 344 | #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) | ||
| 345 | #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) | ||
| 346 | #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) | ||
| 347 | |||
| 348 | #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | ||
| 349 | #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | ||
| 350 | #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) | ||
| 351 | #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | ||
| 352 | #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | ||
| 353 | |||
| 354 | #define S_BCM1480_ATRAP_CFG_AGENTID 8 | ||
| 355 | #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) | ||
| 356 | #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) | ||
| 357 | #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) | ||
| 358 | |||
| 359 | |||
| 360 | #define K_BCM1480_BUS_AGENT_CPU0 0 | ||
| 361 | #define K_BCM1480_BUS_AGENT_CPU1 1 | ||
| 362 | #define K_BCM1480_BUS_AGENT_NC 2 | ||
| 363 | #define K_BCM1480_BUS_AGENT_IOB 3 | ||
| 364 | #define K_BCM1480_BUS_AGENT_SCD 4 | ||
| 365 | #define K_BCM1480_BUS_AGENT_L2C 6 | ||
| 366 | #define K_BCM1480_BUS_AGENT_MC 7 | ||
| 367 | #define K_BCM1480_BUS_AGENT_CPU2 8 | ||
| 368 | #define K_BCM1480_BUS_AGENT_CPU3 9 | ||
| 369 | #define K_BCM1480_BUS_AGENT_PM 10 | ||
| 370 | |||
| 371 | #define S_BCM1480_ATRAP_CFG_CATTR 12 | ||
| 372 | #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) | ||
| 373 | #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) | ||
| 374 | #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) | ||
| 375 | |||
| 376 | #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 | ||
| 377 | #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 | ||
| 378 | #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 | ||
| 379 | #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 | ||
| 380 | |||
| 381 | #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) | ||
| 382 | |||
| 383 | |||
| 384 | /* | ||
| 385 | * Trace Event Registers (Table 47) | ||
| 386 | * Same as BCM1250. | ||
| 387 | */ | ||
| 388 | |||
| 389 | /* | ||
| 390 | * Trace Sequence Control Registers (Table 48) | ||
| 391 | * Registers: TRACE_SEQUENCE_x | ||
| 392 | * | ||
| 393 | * Same as BCM1250 except for two new fields. | ||
| 394 | */ | ||
| 395 | |||
| 396 | |||
| 397 | #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) | ||
| 398 | |||
| 399 | #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 | ||
| 400 | #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 401 | #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 402 | #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 403 | |||
| 404 | /* | ||
| 405 | * Trace Control Register (Table 49) | ||
| 406 | * Register: TRACE_CFG | ||
| 407 | * | ||
| 408 | * Bits 0..8 are the same as the BCM1250, rest are different. | ||
| 409 | * Entire register is redefined below. | ||
| 410 | */ | ||
| 411 | |||
| 412 | #define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | ||
| 413 | #define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | ||
| 414 | #define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | ||
| 415 | #define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) | ||
| 416 | #define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) | ||
| 417 | #define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) | ||
| 418 | #define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) | ||
| 419 | #define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) | ||
| 420 | #define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8) | ||
| 421 | |||
| 422 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 | ||
| 423 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 424 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 425 | #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 426 | |||
| 427 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 | ||
| 428 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 | ||
| 429 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 | ||
| 430 | |||
| 431 | #define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24 | ||
| 432 | #define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
| 433 | #define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
| 434 | #define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
| 435 | |||
| 436 | #endif /* _BCM1480_SCD_H */ | ||
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h index 3cc341ac87c7..a474c29cd701 100644 --- a/include/asm-mips/sibyte/sb1250.h +++ b/include/asm-mips/sibyte/sb1250.h | |||
| @@ -27,6 +27,9 @@ | |||
| 27 | 27 | ||
| 28 | #define SB1250_NR_IRQS 64 | 28 | #define SB1250_NR_IRQS 64 |
| 29 | 29 | ||
| 30 | #define BCM1480_NR_IRQS 128 | ||
| 31 | #define BCM1480_NR_IRQS_HALF 64 | ||
| 32 | |||
| 30 | #define SB1250_DUART_MINOR_BASE 64 | 33 | #define SB1250_DUART_MINOR_BASE 64 |
| 31 | 34 | ||
| 32 | #ifndef __ASSEMBLY__ | 35 | #ifndef __ASSEMBLY__ |
| @@ -35,6 +38,7 @@ | |||
| 35 | 38 | ||
| 36 | /* For revision/pass information */ | 39 | /* For revision/pass information */ |
| 37 | #include <asm/sibyte/sb1250_scd.h> | 40 | #include <asm/sibyte/sb1250_scd.h> |
| 41 | #include <asm/sibyte/bcm1480_scd.h> | ||
| 38 | extern unsigned int sb1_pass; | 42 | extern unsigned int sb1_pass; |
| 39 | extern unsigned int soc_pass; | 43 | extern unsigned int soc_pass; |
| 40 | extern unsigned int soc_type; | 44 | extern unsigned int soc_type; |
| @@ -46,6 +50,13 @@ extern unsigned long sb1250_gettimeoffset(void); | |||
| 46 | extern void sb1250_mask_irq(int cpu, int irq); | 50 | extern void sb1250_mask_irq(int cpu, int irq); |
| 47 | extern void sb1250_unmask_irq(int cpu, int irq); | 51 | extern void sb1250_unmask_irq(int cpu, int irq); |
| 48 | extern void sb1250_smp_finish(void); | 52 | extern void sb1250_smp_finish(void); |
| 53 | |||
| 54 | extern void bcm1480_time_init(void); | ||
| 55 | extern unsigned long bcm1480_gettimeoffset(void); | ||
| 56 | extern void bcm1480_mask_irq(int cpu, int irq); | ||
| 57 | extern void bcm1480_unmask_irq(int cpu, int irq); | ||
| 58 | extern void bcm1480_smp_finish(void); | ||
| 59 | |||
| 49 | extern void prom_printf(char *fmt, ...); | 60 | extern void prom_printf(char *fmt, ...); |
| 50 | 61 | ||
| 51 | #define AT_spin \ | 62 | #define AT_spin \ |
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index 40ef97c76c8b..f67f5a3381a3 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h | |||
| @@ -97,13 +97,17 @@ | |||
| 97 | * ordering, so be careful when adding support for new minor revs. | 97 | * ordering, so be careful when adding support for new minor revs. |
| 98 | ********************************************************************* */ | 98 | ********************************************************************* */ |
| 99 | 99 | ||
| 100 | #define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff | 100 | #define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff |
| 101 | #define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001 | 101 | #define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 |
| 102 | #define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002 | 102 | #define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 |
| 103 | #define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004 | 103 | #define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 |
| 104 | 104 | ||
| 105 | #define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 | 105 | #define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 |
| 106 | #define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 | 106 | #define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 |
| 107 | |||
| 108 | #define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 | ||
| 109 | #define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 | ||
| 110 | #define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000 | ||
| 107 | 111 | ||
| 108 | /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ | 112 | /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ |
| 109 | #define SIBYTE_HDR_FMASK(chip, pass) \ | 113 | #define SIBYTE_HDR_FMASK(chip, pass) \ |
| @@ -111,8 +115,17 @@ | |||
| 111 | #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ | 115 | #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ |
| 112 | (SIBYTE_HDR_FMASK_ ## chip ## _ALL) | 116 | (SIBYTE_HDR_FMASK_ ## chip ## _ALL) |
| 113 | 117 | ||
| 118 | /* Default constant value for all chips, all revisions */ | ||
| 114 | #define SIBYTE_HDR_FMASK_ALL \ | 119 | #define SIBYTE_HDR_FMASK_ALL \ |
| 120 | (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ | ||
| 121 | | SIBYTE_HDR_FMASK_1480_ALL) | ||
| 122 | |||
| 123 | /* This one is used for the "original" BCM1250/BCM112x chips. We use this | ||
| 124 | to weed out constants and macros that do not exist on later chips like | ||
| 125 | the BCM1480 */ | ||
| 126 | #define SIBYTE_HDR_FMASK_1250_112x_ALL \ | ||
| 115 | (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) | 127 | (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) |
| 128 | #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL | ||
| 116 | 129 | ||
| 117 | #ifndef SIBYTE_HDR_FEATURES | 130 | #ifndef SIBYTE_HDR_FEATURES |
| 118 | #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL | 131 | #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL |
| @@ -133,6 +146,12 @@ | |||
| 133 | #define SIBYTE_HDR_FEATURE_CHIP(chip) \ | 146 | #define SIBYTE_HDR_FEATURE_CHIP(chip) \ |
| 134 | (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) | 147 | (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) |
| 135 | 148 | ||
| 149 | /* True for all versions of the BCM1250 and BCM1125, but not true for | ||
| 150 | anything else */ | ||
| 151 | #define SIBYTE_HDR_FEATURE_1250_112x \ | ||
| 152 | (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) | ||
| 153 | /* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */ | ||
| 154 | |||
| 136 | /* True if header features enabled for that rev or later, inclusive. */ | 155 | /* True if header features enabled for that rev or later, inclusive. */ |
| 137 | #define SIBYTE_HDR_FEATURE(chip, pass) \ | 156 | #define SIBYTE_HDR_FEATURE(chip, pass) \ |
| 138 | (!! ((SIBYTE_HDR_FMASK(chip, pass) \ | 157 | (!! ((SIBYTE_HDR_FMASK(chip, pass) \ |
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index 3cdb48f50ed0..4b092b9dfe0f 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h | |||
| @@ -58,17 +58,17 @@ | |||
| 58 | #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) | 58 | #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) |
| 59 | 59 | ||
| 60 | #define S_DMA_DESC_TYPE _SB_MAKE64(1) | 60 | #define S_DMA_DESC_TYPE _SB_MAKE64(1) |
| 61 | #define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) | 61 | #define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) |
| 62 | #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) | 62 | #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) |
| 63 | #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) | 63 | #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) |
| 64 | 64 | ||
| 65 | #define K_DMA_DESC_TYPE_RING_AL 0 | 65 | #define K_DMA_DESC_TYPE_RING_AL 0 |
| 66 | #define K_DMA_DESC_TYPE_CHAIN_AL 1 | 66 | #define K_DMA_DESC_TYPE_CHAIN_AL 1 |
| 67 | 67 | ||
| 68 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 68 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 69 | #define K_DMA_DESC_TYPE_RING_UAL_WI 2 | 69 | #define K_DMA_DESC_TYPE_RING_UAL_WI 2 |
| 70 | #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 | 70 | #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 |
| 71 | #endif /* 1250 PASS3 || 112x PASS1 */ | 71 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 72 | 72 | ||
| 73 | #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) | 73 | #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) |
| 74 | #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) | 74 | #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) |
| @@ -111,11 +111,11 @@ | |||
| 111 | #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) | 111 | #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) |
| 112 | #define M_DMA_L2CA _SB_MAKEMASK1(5) | 112 | #define M_DMA_L2CA _SB_MAKEMASK1(5) |
| 113 | 113 | ||
| 114 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 114 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 115 | #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) | 115 | #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) |
| 116 | #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) | 116 | #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) |
| 117 | #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) | 117 | #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) |
| 118 | #endif /* 1250 PASS3 || 112x PASS1 */ | 118 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 119 | 119 | ||
| 120 | #define M_DMA_MBZ1 _SB_MAKEMASK(6,15) | 120 | #define M_DMA_MBZ1 _SB_MAKEMASK(6,15) |
| 121 | 121 | ||
| @@ -165,14 +165,14 @@ | |||
| 165 | #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) | 165 | #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) |
| 166 | #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) | 166 | #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) |
| 167 | 167 | ||
| 168 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 168 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 169 | #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) | 169 | #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) |
| 170 | #endif /* 1250 PASS3 || 112x PASS1 */ | 170 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 171 | 171 | ||
| 172 | /* | 172 | /* |
| 173 | * Receive Packet Drop Registers | 173 | * Receive Packet Drop Registers |
| 174 | */ | 174 | */ |
| 175 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 175 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 176 | #define S_DMA_OODLOST_RX _SB_MAKE64(0) | 176 | #define S_DMA_OODLOST_RX _SB_MAKE64(0) |
| 177 | #define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) | 177 | #define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) |
| 178 | #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) | 178 | #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) |
| @@ -180,7 +180,7 @@ | |||
| 180 | #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) | 180 | #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) |
| 181 | #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) | 181 | #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) |
| 182 | #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) | 182 | #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) |
| 183 | #endif /* 1250 PASS3 || 112x PASS1 */ | 183 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 184 | 184 | ||
| 185 | /* ********************************************************************* | 185 | /* ********************************************************************* |
| 186 | * DMA Descriptors | 186 | * DMA Descriptors |
| @@ -201,21 +201,21 @@ | |||
| 201 | 201 | ||
| 202 | #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) | 202 | #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) |
| 203 | 203 | ||
| 204 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 204 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 205 | #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) | 205 | #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) |
| 206 | #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) | 206 | #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) |
| 207 | #endif /* 1250 PASS3 || 112x PASS1 */ | 207 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 208 | 208 | ||
| 209 | #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) | 209 | #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) |
| 210 | #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) | 210 | #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) |
| 211 | #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) | 211 | #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) |
| 212 | #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) | 212 | #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) |
| 213 | 213 | ||
| 214 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 214 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 215 | #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) | 215 | #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) |
| 216 | #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) | 216 | #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) |
| 217 | #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) | 217 | #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) |
| 218 | #endif /* 1250 PASS3 || 112x PASS1 */ | 218 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 219 | 219 | ||
| 220 | #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) | 220 | #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) |
| 221 | #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) | 221 | #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) |
| @@ -235,12 +235,12 @@ | |||
| 235 | #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) | 235 | #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) |
| 236 | #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) | 236 | #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) |
| 237 | 237 | ||
| 238 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 238 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 239 | #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) | 239 | #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) |
| 240 | #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) | 240 | #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) |
| 241 | #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) | 241 | #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) |
| 242 | #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) | 242 | #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) |
| 243 | #endif /* 1250 PASS3 || 112x PASS1 */ | 243 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 244 | 244 | ||
| 245 | #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) | 245 | #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) |
| 246 | 246 | ||
| @@ -255,12 +255,12 @@ | |||
| 255 | 255 | ||
| 256 | #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) | 256 | #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) |
| 257 | 257 | ||
| 258 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 258 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 259 | #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) | 259 | #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) |
| 260 | #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) | 260 | #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) |
| 261 | #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) | 261 | #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) |
| 262 | #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) | 262 | #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) |
| 263 | #endif /* 1250 PASS3 || 112x PASS1 */ | 263 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 264 | 264 | ||
| 265 | #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) | 265 | #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) |
| 266 | #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) | 266 | #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) |
| @@ -282,15 +282,16 @@ | |||
| 282 | #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) | 282 | #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) |
| 283 | #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) | 283 | #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) |
| 284 | 284 | ||
| 285 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 285 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 286 | /* Note: BADTCPCS is actually in DSCR_B options field */ | 286 | /* Note: This bit is in the DSCR_B options field */ |
| 287 | #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) | 287 | #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) |
| 288 | #endif /* 1250 PASS2 || 112x PASS1 */ | 288 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 289 | 289 | ||
| 290 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 290 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 291 | /* Note: These bits are in the DSCR_B options field */ | ||
| 291 | #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) | 292 | #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) |
| 292 | #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) | 293 | #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) |
| 293 | #endif /* 1250 PASS3 || 112x PASS1 */ | 294 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 294 | 295 | ||
| 295 | #define S_DMA_ETHRX_RXCH 53 | 296 | #define S_DMA_ETHRX_RXCH 53 |
| 296 | #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) | 297 | #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) |
| @@ -438,7 +439,7 @@ | |||
| 438 | M_DM_CUR_DSCR_DSCR_COUNT) | 439 | M_DM_CUR_DSCR_DSCR_COUNT) |
| 439 | 440 | ||
| 440 | 441 | ||
| 441 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 442 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 442 | /* | 443 | /* |
| 443 | * Data Mover Channel Partial Result Registers | 444 | * Data Mover Channel Partial Result Registers |
| 444 | * Register: DM_PARTIAL_0 | 445 | * Register: DM_PARTIAL_0 |
| @@ -459,10 +460,10 @@ | |||
| 459 | M_DM_PARTIAL_TCPCS_PARTIAL) | 460 | M_DM_PARTIAL_TCPCS_PARTIAL) |
| 460 | 461 | ||
| 461 | #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) | 462 | #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) |
| 462 | #endif /* 1250 PASS3 || 112x PASS1 */ | 463 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 463 | 464 | ||
| 464 | 465 | ||
| 465 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 466 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 466 | /* | 467 | /* |
| 467 | * Data Mover CRC Definition Registers | 468 | * Data Mover CRC Definition Registers |
| 468 | * Register: CRC_DEF_0 | 469 | * Register: CRC_DEF_0 |
| @@ -479,10 +480,10 @@ | |||
| 479 | #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) | 480 | #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) |
| 480 | #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ | 481 | #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ |
| 481 | M_CRC_DEF_CRC_POLY) | 482 | M_CRC_DEF_CRC_POLY) |
| 482 | #endif /* 1250 PASS3 || 112x PASS1 */ | 483 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 483 | 484 | ||
| 484 | 485 | ||
| 485 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 486 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 486 | /* | 487 | /* |
| 487 | * Data Mover CRC/Checksum Definition Registers | 488 | * Data Mover CRC/Checksum Definition Registers |
| 488 | * Register: CTCP_DEF_0 | 489 | * Register: CTCP_DEF_0 |
| @@ -511,7 +512,7 @@ | |||
| 511 | #define K_CTCP_DEF_CRC_WIDTH_1 2 | 512 | #define K_CTCP_DEF_CRC_WIDTH_1 2 |
| 512 | 513 | ||
| 513 | #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) | 514 | #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) |
| 514 | #endif /* 1250 PASS3 || 112x PASS1 */ | 515 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 515 | 516 | ||
| 516 | 517 | ||
| 517 | /* | 518 | /* |
| @@ -560,12 +561,12 @@ | |||
| 560 | #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) | 561 | #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) |
| 561 | #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) | 562 | #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) |
| 562 | 563 | ||
| 563 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 564 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 564 | #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) | 565 | #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) |
| 565 | #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) | 566 | #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) |
| 566 | #endif /* 1250 PASS2 || 112x PASS1 */ | 567 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 567 | 568 | ||
| 568 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 569 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 569 | #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) | 570 | #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) |
| 570 | #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) | 571 | #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) |
| 571 | #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) | 572 | #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) |
| @@ -574,7 +575,7 @@ | |||
| 574 | #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) | 575 | #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) |
| 575 | #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) | 576 | #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) |
| 576 | #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) | 577 | #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) |
| 577 | #endif /* 1250 PASS3 || 112x PASS1 */ | 578 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 578 | 579 | ||
| 579 | #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) | 580 | #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) |
| 580 | 581 | ||
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index f1f509f295c4..0ce9957e8a7e 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h | |||
| @@ -51,19 +51,21 @@ | |||
| 51 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) | 51 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) |
| 52 | #define K_IO_WIDTH_SEL_1 0 | 52 | #define K_IO_WIDTH_SEL_1 0 |
| 53 | #define K_IO_WIDTH_SEL_2 1 | 53 | #define K_IO_WIDTH_SEL_2 1 |
| 54 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 54 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 55 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 55 | #define K_IO_WIDTH_SEL_1L 2 | 56 | #define K_IO_WIDTH_SEL_1L 2 |
| 56 | #endif /* 1250 PASS2 || 112x PASS1 */ | 57 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 57 | #define K_IO_WIDTH_SEL_4 3 | 58 | #define K_IO_WIDTH_SEL_4 3 |
| 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) | 59 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) |
| 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) | 60 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) |
| 60 | 61 | ||
| 61 | #define S_IO_PARITY_ENA 4 | 62 | #define S_IO_PARITY_ENA 4 |
| 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) | 63 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) |
| 63 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 64 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 65 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 64 | #define S_IO_BURST_EN 5 | 66 | #define S_IO_BURST_EN 5 |
| 65 | #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) | 67 | #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) |
| 66 | #endif /* 1250 PASS2 || 112x PASS1 */ | 68 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 67 | #define S_IO_PARITY_ODD 6 | 69 | #define S_IO_PARITY_ODD 6 |
| 68 | #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) | 70 | #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) |
| 69 | #define S_IO_NONMUX 7 | 71 | #define S_IO_NONMUX 7 |
| @@ -96,8 +98,11 @@ | |||
| 96 | 98 | ||
| 97 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ | 99 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ |
| 98 | 100 | ||
| 101 | #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) | ||
| 102 | |||
| 103 | |||
| 99 | /* | 104 | /* |
| 100 | * Generic Bus Region 0 Timing Registers (Table 11-7) | 105 | * Generic Bus Timing 0 Registers (Table 11-7) |
| 101 | */ | 106 | */ |
| 102 | 107 | ||
| 103 | #define S_IO_ALE_WIDTH 0 | 108 | #define S_IO_ALE_WIDTH 0 |
| @@ -105,21 +110,23 @@ | |||
| 105 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) | 110 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) |
| 106 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) | 111 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) |
| 107 | 112 | ||
| 108 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 113 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 114 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 109 | #define M_IO_EARLY_CS _SB_MAKEMASK1(3) | 115 | #define M_IO_EARLY_CS _SB_MAKEMASK1(3) |
| 110 | #endif /* 1250 PASS2 || 112x PASS1 */ | 116 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 111 | 117 | ||
| 112 | #define S_IO_ALE_TO_CS 4 | 118 | #define S_IO_ALE_TO_CS 4 |
| 113 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) | 119 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) |
| 114 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) | 120 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) |
| 115 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) | 121 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) |
| 116 | 122 | ||
| 117 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 123 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 124 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 118 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) | 125 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) |
| 119 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) | 126 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) |
| 120 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) | 127 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) |
| 121 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) | 128 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) |
| 122 | #endif /* 1250 PASS2 || 112x PASS1 */ | 129 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 123 | 130 | ||
| 124 | #define S_IO_CS_WIDTH 8 | 131 | #define S_IO_CS_WIDTH 8 |
| 125 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) | 132 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) |
| @@ -141,9 +148,10 @@ | |||
| 141 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) | 148 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) |
| 142 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) | 149 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) |
| 143 | 150 | ||
| 144 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 151 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ |
| 152 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 145 | #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) | 153 | #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) |
| 146 | #endif /* 1250 PASS2 || 112x PASS1 */ | 154 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 147 | 155 | ||
| 148 | #define S_IO_WRITE_WIDTH 4 | 156 | #define S_IO_WRITE_WIDTH 4 |
| 149 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) | 157 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) |
| @@ -183,9 +191,127 @@ | |||
| 183 | #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) | 191 | #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) |
| 184 | #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) | 192 | #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) |
| 185 | #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) | 193 | #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) |
| 186 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 194 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 187 | #define M_IO_COH_ERR _SB_MAKEMASK1(14) | 195 | #define M_IO_COH_ERR _SB_MAKEMASK1(14) |
| 188 | #endif /* 1250 PASS2 || 112x PASS1 */ | 196 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 197 | |||
| 198 | |||
| 199 | /* | ||
| 200 | * Generic Bus Output Drive Control Register 0 (Table 14-18) | ||
| 201 | */ | ||
| 202 | |||
| 203 | #define S_IO_SLEW0 0 | ||
| 204 | #define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) | ||
| 205 | #define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) | ||
| 206 | #define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) | ||
| 207 | |||
| 208 | #define S_IO_DRV_A 2 | ||
| 209 | #define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) | ||
| 210 | #define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) | ||
| 211 | #define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) | ||
| 212 | |||
| 213 | #define S_IO_DRV_B 6 | ||
| 214 | #define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) | ||
| 215 | #define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) | ||
| 216 | #define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) | ||
| 217 | |||
| 218 | #define S_IO_DRV_C 10 | ||
| 219 | #define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) | ||
| 220 | #define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) | ||
| 221 | #define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) | ||
| 222 | |||
| 223 | #define S_IO_DRV_D 14 | ||
| 224 | #define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) | ||
| 225 | #define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) | ||
| 226 | #define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) | ||
| 227 | |||
| 228 | /* | ||
| 229 | * Generic Bus Output Drive Control Register 1 (Table 14-19) | ||
| 230 | */ | ||
| 231 | |||
| 232 | #define S_IO_DRV_E 2 | ||
| 233 | #define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) | ||
| 234 | #define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) | ||
| 235 | #define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) | ||
| 236 | |||
| 237 | #define S_IO_DRV_F 6 | ||
| 238 | #define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) | ||
| 239 | #define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) | ||
| 240 | #define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) | ||
| 241 | |||
| 242 | #define S_IO_SLEW1 8 | ||
| 243 | #define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) | ||
| 244 | #define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) | ||
| 245 | #define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) | ||
| 246 | |||
| 247 | #define S_IO_DRV_G 10 | ||
| 248 | #define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) | ||
| 249 | #define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) | ||
| 250 | #define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) | ||
| 251 | |||
| 252 | #define S_IO_SLEW2 12 | ||
| 253 | #define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) | ||
| 254 | #define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) | ||
| 255 | #define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) | ||
| 256 | |||
| 257 | #define S_IO_DRV_H 14 | ||
| 258 | #define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) | ||
| 259 | #define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) | ||
| 260 | #define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) | ||
| 261 | |||
| 262 | /* | ||
| 263 | * Generic Bus Output Drive Control Register 2 (Table 14-20) | ||
| 264 | */ | ||
| 265 | |||
| 266 | #define S_IO_DRV_J 2 | ||
| 267 | #define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) | ||
| 268 | #define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) | ||
| 269 | #define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) | ||
| 270 | |||
| 271 | #define S_IO_DRV_K 6 | ||
| 272 | #define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) | ||
| 273 | #define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) | ||
| 274 | #define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) | ||
| 275 | |||
| 276 | #define S_IO_DRV_L 10 | ||
| 277 | #define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) | ||
| 278 | #define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) | ||
| 279 | #define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) | ||
| 280 | |||
| 281 | #define S_IO_DRV_M 14 | ||
| 282 | #define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) | ||
| 283 | #define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) | ||
| 284 | #define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Generic Bus Output Drive Control Register 3 (Table 14-21) | ||
| 288 | */ | ||
| 289 | |||
| 290 | #define S_IO_SLEW3 0 | ||
| 291 | #define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) | ||
| 292 | #define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) | ||
| 293 | #define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) | ||
| 294 | |||
| 295 | #define S_IO_DRV_N 2 | ||
| 296 | #define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) | ||
| 297 | #define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) | ||
| 298 | #define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) | ||
| 299 | |||
| 300 | #define S_IO_DRV_P 6 | ||
| 301 | #define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) | ||
| 302 | #define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) | ||
| 303 | #define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) | ||
| 304 | |||
| 305 | #define S_IO_DRV_Q 10 | ||
| 306 | #define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) | ||
| 307 | #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) | ||
| 308 | #define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) | ||
| 309 | |||
| 310 | #define S_IO_DRV_R 14 | ||
| 311 | #define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) | ||
| 312 | #define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) | ||
| 313 | #define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) | ||
| 314 | |||
| 189 | 315 | ||
| 190 | /* | 316 | /* |
| 191 | * PCMCIA configuration register (Table 12-6) | 317 | * PCMCIA configuration register (Table 12-6) |
| @@ -202,6 +328,22 @@ | |||
| 202 | #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) | 328 | #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) |
| 203 | #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) | 329 | #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) |
| 204 | 330 | ||
| 331 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 332 | #define S_PCMCIA_MODE 16 | ||
| 333 | #define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) | ||
| 334 | #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) | ||
| 335 | #define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) | ||
| 336 | |||
| 337 | #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ | ||
| 338 | #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ | ||
| 339 | #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ | ||
| 340 | #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ | ||
| 341 | #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ | ||
| 342 | #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ | ||
| 343 | #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ | ||
| 344 | #endif | ||
| 345 | |||
| 346 | |||
| 205 | /* | 347 | /* |
| 206 | * PCMCIA status register (Table 12-7) | 348 | * PCMCIA status register (Table 12-7) |
| 207 | */ | 349 | */ |
| @@ -272,5 +414,62 @@ | |||
| 272 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) | 414 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) |
| 273 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) | 415 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) |
| 274 | 416 | ||
| 417 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 418 | |||
| 419 | /* | ||
| 420 | * GPIO Interrupt Additional Type Register | ||
| 421 | */ | ||
| 422 | |||
| 423 | #define K_GPIO_INTR_BOTHEDGE 0 | ||
| 424 | #define K_GPIO_INTR_RISEEDGE 1 | ||
| 425 | #define K_GPIO_INTR_UNPRED1 2 | ||
| 426 | #define K_GPIO_INTR_UNPRED2 3 | ||
| 427 | |||
| 428 | #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) | ||
| 429 | #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) | ||
| 430 | #define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) | ||
| 431 | #define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) | ||
| 432 | |||
| 433 | #define S_GPIO_INTR_ATYPE0 0 | ||
| 434 | #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) | ||
| 435 | #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) | ||
| 436 | #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) | ||
| 437 | |||
| 438 | #define S_GPIO_INTR_ATYPE2 2 | ||
| 439 | #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) | ||
| 440 | #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) | ||
| 441 | #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) | ||
| 442 | |||
| 443 | #define S_GPIO_INTR_ATYPE4 4 | ||
| 444 | #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) | ||
| 445 | #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) | ||
| 446 | #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) | ||
| 447 | |||
| 448 | #define S_GPIO_INTR_ATYPE6 6 | ||
| 449 | #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) | ||
| 450 | #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) | ||
| 451 | #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) | ||
| 452 | |||
| 453 | #define S_GPIO_INTR_ATYPE8 8 | ||
| 454 | #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) | ||
| 455 | #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) | ||
| 456 | #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) | ||
| 457 | |||
| 458 | #define S_GPIO_INTR_ATYPE10 10 | ||
| 459 | #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) | ||
| 460 | #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) | ||
| 461 | #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) | ||
| 462 | |||
| 463 | #define S_GPIO_INTR_ATYPE12 12 | ||
| 464 | #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) | ||
| 465 | #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) | ||
| 466 | #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) | ||
| 467 | |||
| 468 | #define S_GPIO_INTR_ATYPE14 14 | ||
| 469 | #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) | ||
| 470 | #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) | ||
| 471 | #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) | ||
| 472 | #endif | ||
| 473 | |||
| 275 | 474 | ||
| 276 | #endif | 475 | #endif |
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index e173e2ea4c98..f631fe05a44c 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h | |||
| @@ -47,6 +47,10 @@ | |||
| 47 | * First, the interrupt numbers. | 47 | * First, the interrupt numbers. |
| 48 | */ | 48 | */ |
| 49 | 49 | ||
| 50 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 51 | |||
| 52 | #define K_INT_SOURCES 64 | ||
| 53 | |||
| 50 | #define K_INT_WATCHDOG_TIMER_0 0 | 54 | #define K_INT_WATCHDOG_TIMER_0 0 |
| 51 | #define K_INT_WATCHDOG_TIMER_1 1 | 55 | #define K_INT_WATCHDOG_TIMER_1 1 |
| 52 | #define K_INT_TIMER_0 2 | 56 | #define K_INT_TIMER_0 2 |
| @@ -244,4 +248,6 @@ | |||
| 244 | #define M_LDTVECT_RAISEMBOX 0x40 | 248 | #define M_LDTVECT_RAISEMBOX 0x40 |
| 245 | 249 | ||
| 246 | 250 | ||
| 251 | #endif /* 1250/112x */ | ||
| 252 | |||
| 247 | #endif | 253 | #endif |
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 8afe8e01581b..5dd340992029 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h | |||
| @@ -89,8 +89,13 @@ | |||
| 89 | #define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) | 89 | #define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) |
| 90 | #define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) | 90 | #define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) |
| 91 | 91 | ||
| 92 | #define S_L2C_MGMT_TAG 21 | 92 | #define S_L2C_MGMT_ECC_DIAG 21 |
| 93 | #define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG) | 93 | #define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) |
| 94 | #define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) | ||
| 95 | #define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) | ||
| 96 | |||
| 97 | #define S_L2C_MGMT_TAG 23 | ||
| 98 | #define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) | ||
| 94 | #define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) | 99 | #define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) |
| 95 | #define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) | 100 | #define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) |
| 96 | 101 | ||
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 18e74e43f4a2..422cc0e96f66 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h | |||
| @@ -81,7 +81,10 @@ | |||
| 81 | #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) | 81 | #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) |
| 82 | 82 | ||
| 83 | #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) | 83 | #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) |
| 84 | #define M_MAC_RESERVED2 _SB_MAKEMASK1(18) | 84 | |
| 85 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 86 | #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) | ||
| 87 | #endif | ||
| 85 | #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) | 88 | #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) |
| 86 | #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) | 89 | #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) |
| 87 | #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) | 90 | #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) |
| @@ -132,9 +135,9 @@ | |||
| 132 | #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) | 135 | #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) |
| 133 | #endif /* 1250 PASS2 || 112x PASS1 */ | 136 | #endif /* 1250 PASS2 || 112x PASS1 */ |
| 134 | 137 | ||
| 135 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 138 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 136 | #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) | 139 | #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) |
| 137 | #endif /* 1250 PASS3 || 112x PASS1 */ | 140 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 138 | 141 | ||
| 139 | #define S_MAC_BYPASS_IFG _SB_MAKE64(46) | 142 | #define S_MAC_BYPASS_IFG _SB_MAKE64(46) |
| 140 | #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) | 143 | #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) |
| @@ -176,10 +179,22 @@ | |||
| 176 | 179 | ||
| 177 | #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) | 180 | #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) |
| 178 | 181 | ||
| 182 | #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) | ||
| 179 | #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) | 183 | #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) |
| 180 | #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) | 184 | #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) |
| 181 | #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) | 185 | #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) |
| 182 | #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) | 186 | #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) |
| 187 | #endif | ||
| 188 | |||
| 189 | /* | ||
| 190 | * MAC reset information register (1280/1255) | ||
| 191 | */ | ||
| 192 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 193 | #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) | ||
| 194 | #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) | ||
| 195 | #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) | ||
| 196 | #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) | ||
| 197 | #endif | ||
| 183 | 198 | ||
| 184 | /* | 199 | /* |
| 185 | * MAC DMA Control Register | 200 | * MAC DMA Control Register |
| @@ -267,12 +282,12 @@ | |||
| 267 | #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) | 282 | #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) |
| 268 | #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) | 283 | #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) |
| 269 | 284 | ||
| 270 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 285 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 271 | #define S_MAC_PRE_LEN _SB_MAKE64(0) | 286 | #define S_MAC_PRE_LEN _SB_MAKE64(0) |
| 272 | #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) | 287 | #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) |
| 273 | #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) | 288 | #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) |
| 274 | #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) | 289 | #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) |
| 275 | #endif /* 1250 PASS3 || 112x PASS1 */ | 290 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 276 | 291 | ||
| 277 | #define S_MAC_IFG_TX _SB_MAKE64(6) | 292 | #define S_MAC_IFG_TX _SB_MAKE64(6) |
| 278 | #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) | 293 | #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) |
| @@ -458,9 +473,9 @@ | |||
| 458 | #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) | 473 | #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) |
| 459 | #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) | 474 | #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) |
| 460 | 475 | ||
| 461 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 476 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 462 | #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) | 477 | #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) |
| 463 | #endif /* 1250 PASS3 || 112x PASS1 */ | 478 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 464 | 479 | ||
| 465 | /* | 480 | /* |
| 466 | * MAC Fifo Pointer Registers (Table 9-19) [Debug register] | 481 | * MAC Fifo Pointer Registers (Table 9-19) [Debug register] |
| @@ -594,7 +609,7 @@ | |||
| 594 | #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) | 609 | #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) |
| 595 | #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) | 610 | #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) |
| 596 | 611 | ||
| 597 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 612 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 598 | #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) | 613 | #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) |
| 599 | #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) | 614 | #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) |
| 600 | #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) | 615 | #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) |
| @@ -612,7 +627,7 @@ | |||
| 612 | #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) | 627 | #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) |
| 613 | #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) | 628 | #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) |
| 614 | #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) | 629 | #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) |
| 615 | #endif /* 1250 PASS3 || 112x PASS1 */ | 630 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ |
| 616 | 631 | ||
| 617 | /* | 632 | /* |
| 618 | * MAC Receive Channel Select Registers (Table 9-25) | 633 | * MAC Receive Channel Select Registers (Table 9-25) |
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 1dd41c927996..8d6c1e37a4fa 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h | |||
| @@ -324,6 +324,10 @@ | |||
| 324 | #define K_MC_tRFC_DEFAULT 12 | 324 | #define K_MC_tRFC_DEFAULT 12 |
| 325 | #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) | 325 | #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) |
| 326 | 326 | ||
| 327 | #if SIBYTE_HDR_FEATURE(1250, PASS3) | ||
| 328 | #define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ | ||
| 329 | #endif | ||
| 330 | |||
| 327 | #define S_MC_tCwCr 40 | 331 | #define S_MC_tCwCr 40 |
| 328 | #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) | 332 | #define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) |
| 329 | #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) | 333 | #define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) |
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 9db80cd13a79..3aab13730408 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h | |||
| @@ -61,6 +61,8 @@ | |||
| 61 | * XXX: can't remove MC base 0 if 112x, since it's used by other macros, | 61 | * XXX: can't remove MC base 0 if 112x, since it's used by other macros, |
| 62 | * since there is one reg there (but it could get its addr/offset constant). | 62 | * since there is one reg there (but it could get its addr/offset constant). |
| 63 | */ | 63 | */ |
| 64 | |||
| 65 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 64 | #define A_MC_BASE_0 0x0010051000 | 66 | #define A_MC_BASE_0 0x0010051000 |
| 65 | #define A_MC_BASE_1 0x0010052000 | 67 | #define A_MC_BASE_1 0x0010052000 |
| 66 | #define MC_REGISTER_SPACING 0x1000 | 68 | #define MC_REGISTER_SPACING 0x1000 |
| @@ -101,10 +103,14 @@ | |||
| 101 | #define R_MC_TEST_ECC 0x0000000420 | 103 | #define R_MC_TEST_ECC 0x0000000420 |
| 102 | #define R_MC_MCLK_CFG 0x0000000500 | 104 | #define R_MC_MCLK_CFG 0x0000000500 |
| 103 | 105 | ||
| 106 | #endif /* 1250 & 112x */ | ||
| 107 | |||
| 104 | /* ********************************************************************* | 108 | /* ********************************************************************* |
| 105 | * L2 Cache Control Registers | 109 | * L2 Cache Control Registers |
| 106 | ********************************************************************* */ | 110 | ********************************************************************* */ |
| 107 | 111 | ||
| 112 | #if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ | ||
| 113 | |||
| 108 | #define A_L2_READ_TAG 0x0010040018 | 114 | #define A_L2_READ_TAG 0x0010040018 |
| 109 | #define A_L2_ECC_TAG 0x0010040038 | 115 | #define A_L2_ECC_TAG 0x0010040038 |
| 110 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | 116 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
| @@ -125,13 +131,16 @@ | |||
| 125 | #define A_L2_READ_ADDRESS A_L2_READ_TAG | 131 | #define A_L2_READ_ADDRESS A_L2_READ_TAG |
| 126 | #define A_L2_EEC_ADDRESS A_L2_ECC_TAG | 132 | #define A_L2_EEC_ADDRESS A_L2_ECC_TAG |
| 127 | 133 | ||
| 134 | #endif | ||
| 128 | 135 | ||
| 129 | /* ********************************************************************* | 136 | /* ********************************************************************* |
| 130 | * PCI Interface Registers | 137 | * PCI Interface Registers |
| 131 | ********************************************************************* */ | 138 | ********************************************************************* */ |
| 132 | 139 | ||
| 140 | #if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ | ||
| 133 | #define A_PCI_TYPE00_HEADER 0x00DE000000 | 141 | #define A_PCI_TYPE00_HEADER 0x00DE000000 |
| 134 | #define A_PCI_TYPE01_HEADER 0x00DE000800 | 142 | #define A_PCI_TYPE01_HEADER 0x00DE000800 |
| 143 | #endif | ||
| 135 | 144 | ||
| 136 | 145 | ||
| 137 | /* ********************************************************************* | 146 | /* ********************************************************************* |
| @@ -264,15 +273,15 @@ | |||
| 264 | ********************************************************************* */ | 273 | ********************************************************************* */ |
| 265 | 274 | ||
| 266 | 275 | ||
| 276 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 267 | #define R_DUART_NUM_PORTS 2 | 277 | #define R_DUART_NUM_PORTS 2 |
| 268 | 278 | ||
| 269 | #define A_DUART 0x0010060000 | 279 | #define A_DUART 0x0010060000 |
| 270 | 280 | ||
| 271 | #define A_DUART_REG(r) | ||
| 272 | |||
| 273 | #define DUART_CHANREG_SPACING 0x100 | 281 | #define DUART_CHANREG_SPACING 0x100 |
| 274 | #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) | 282 | #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) |
| 275 | #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) | 283 | #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) |
| 284 | #endif /* 1250 & 112x */ | ||
| 276 | 285 | ||
| 277 | #define R_DUART_MODE_REG_1 0x100 | 286 | #define R_DUART_MODE_REG_1 0x100 |
| 278 | #define R_DUART_MODE_REG_2 0x110 | 287 | #define R_DUART_MODE_REG_2 0x110 |
| @@ -307,11 +316,13 @@ | |||
| 307 | 316 | ||
| 308 | #define DUART_IMRISR_SPACING 0x20 | 317 | #define DUART_IMRISR_SPACING 0x20 |
| 309 | 318 | ||
| 319 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 310 | #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) | 320 | #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) |
| 311 | #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) | 321 | #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) |
| 312 | 322 | ||
| 313 | #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) | 323 | #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) |
| 314 | #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) | 324 | #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) |
| 325 | #endif /* 1250 & 112x */ | ||
| 315 | 326 | ||
| 316 | 327 | ||
| 317 | 328 | ||
| @@ -368,6 +379,8 @@ | |||
| 368 | ********************************************************************* */ | 379 | ********************************************************************* */ |
| 369 | 380 | ||
| 370 | 381 | ||
| 382 | #if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ | ||
| 383 | |||
| 371 | #define A_SER_BASE_0 0x0010060400 | 384 | #define A_SER_BASE_0 0x0010060400 |
| 372 | #define A_SER_BASE_1 0x0010060800 | 385 | #define A_SER_BASE_1 0x0010060800 |
| 373 | #define SER_SPACING 0x400 | 386 | #define SER_SPACING 0x400 |
| @@ -457,6 +470,8 @@ | |||
| 457 | #define R_SER_RMON_RX_ERRORS 0x000001F0 | 470 | #define R_SER_RMON_RX_ERRORS 0x000001F0 |
| 458 | #define R_SER_RMON_RX_BADADDR 0x000001F8 | 471 | #define R_SER_RMON_RX_BADADDR 0x000001F8 |
| 459 | 472 | ||
| 473 | #endif /* 1250/112x */ | ||
| 474 | |||
| 460 | /* ********************************************************************* | 475 | /* ********************************************************************* |
| 461 | * Generic Bus Registers | 476 | * Generic Bus Registers |
| 462 | ********************************************************************* */ | 477 | ********************************************************************* */ |
| @@ -634,12 +649,13 @@ | |||
| 634 | 649 | ||
| 635 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 650 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
| 636 | #define A_SCD_SCRATCH 0x0010020C10 | 651 | #define A_SCD_SCRATCH 0x0010020C10 |
| 652 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 637 | 653 | ||
| 654 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 638 | #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 | 655 | #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 |
| 639 | #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 | 656 | #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 |
| 640 | #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 | 657 | #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 |
| 641 | #endif /* 1250 PASS2 || 112x PASS1 */ | 658 | #endif |
| 642 | |||
| 643 | 659 | ||
| 644 | /* ********************************************************************* | 660 | /* ********************************************************************* |
| 645 | * System Control Registers | 661 | * System Control Registers |
| @@ -667,15 +683,16 @@ | |||
| 667 | #define A_ADDR_TRAP_CFG_1 0x0010020448 | 683 | #define A_ADDR_TRAP_CFG_1 0x0010020448 |
| 668 | #define A_ADDR_TRAP_CFG_2 0x0010020450 | 684 | #define A_ADDR_TRAP_CFG_2 0x0010020450 |
| 669 | #define A_ADDR_TRAP_CFG_3 0x0010020458 | 685 | #define A_ADDR_TRAP_CFG_3 0x0010020458 |
| 670 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 686 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 671 | #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 | 687 | #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 |
| 672 | #endif /* 1250 PASS2 || 112x PASS1 */ | 688 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 673 | 689 | ||
| 674 | 690 | ||
| 675 | /* ********************************************************************* | 691 | /* ********************************************************************* |
| 676 | * System Interrupt Mapper Registers | 692 | * System Interrupt Mapper Registers |
| 677 | ********************************************************************* */ | 693 | ********************************************************************* */ |
| 678 | 694 | ||
| 695 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 679 | #define A_IMR_CPU0_BASE 0x0010020000 | 696 | #define A_IMR_CPU0_BASE 0x0010020000 |
| 680 | #define A_IMR_CPU1_BASE 0x0010022000 | 697 | #define A_IMR_CPU1_BASE 0x0010022000 |
| 681 | #define IMR_REGISTER_SPACING 0x2000 | 698 | #define IMR_REGISTER_SPACING 0x2000 |
| @@ -700,6 +717,7 @@ | |||
| 700 | #define R_IMR_INTERRUPT_STATUS_COUNT 7 | 717 | #define R_IMR_INTERRUPT_STATUS_COUNT 7 |
| 701 | #define R_IMR_INTERRUPT_MAP_BASE 0x0200 | 718 | #define R_IMR_INTERRUPT_MAP_BASE 0x0200 |
| 702 | #define R_IMR_INTERRUPT_MAP_COUNT 64 | 719 | #define R_IMR_INTERRUPT_MAP_COUNT 64 |
| 720 | #endif /* 1250/112x */ | ||
| 703 | 721 | ||
| 704 | /* ********************************************************************* | 722 | /* ********************************************************************* |
| 705 | * System Performance Counter Registers | 723 | * System Performance Counter Registers |
| @@ -718,6 +736,7 @@ | |||
| 718 | #define A_SCD_BUS_ERR_STATUS 0x0010020880 | 736 | #define A_SCD_BUS_ERR_STATUS 0x0010020880 |
| 719 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 737 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
| 720 | #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 | 738 | #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 |
| 739 | #define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 | ||
| 721 | #endif /* 1250 PASS2 || 112x PASS1 */ | 740 | #endif /* 1250 PASS2 || 112x PASS1 */ |
| 722 | #define A_BUS_ERR_DATA_0 0x00100208A0 | 741 | #define A_BUS_ERR_DATA_0 0x00100208A0 |
| 723 | #define A_BUS_ERR_DATA_1 0x00100208A8 | 742 | #define A_BUS_ERR_DATA_1 0x00100208A8 |
| @@ -798,6 +817,7 @@ | |||
| 798 | * Physical Address Map | 817 | * Physical Address Map |
| 799 | ********************************************************************* */ | 818 | ********************************************************************* */ |
| 800 | 819 | ||
| 820 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 801 | #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) | 821 | #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) |
| 802 | #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) | 822 | #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) |
| 803 | #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) | 823 | #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) |
| @@ -831,6 +851,7 @@ | |||
| 831 | #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) | 851 | #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) |
| 832 | #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) | 852 | #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) |
| 833 | #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) | 853 | #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) |
| 854 | #endif | ||
| 834 | 855 | ||
| 835 | 856 | ||
| 836 | #endif | 857 | #endif |
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index dbbd682fb47e..14c1d5e54a04 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h | |||
| @@ -51,26 +51,70 @@ | |||
| 51 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) | 51 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) |
| 52 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) | 52 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) |
| 53 | 53 | ||
| 54 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | 54 | #define K_SYS_REVISION_BCM1250_PASS1 0x01 |
| 55 | #define K_SYS_REVISION_BCM1250_PASS1 1 | 55 | |
| 56 | #define K_SYS_REVISION_BCM1250_PASS2 3 | 56 | #define K_SYS_REVISION_BCM1250_PASS2 0x03 |
| 57 | #define K_SYS_REVISION_BCM1250_A10 11 | 57 | #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ |
| 58 | #define K_SYS_REVISION_BCM1250_PASS2_2 16 | 58 | #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ |
| 59 | #define K_SYS_REVISION_BCM1250_B2 17 | 59 | #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ |
| 60 | #define K_SYS_REVISION_BCM1250_PASS3 32 | 60 | #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ |
| 61 | #define K_SYS_REVISION_BCM1250_C1 33 | 61 | #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ |
| 62 | #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ | ||
| 63 | #define K_SYS_REVISION_BCM1250_A9 0x08 | ||
| 64 | #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 | ||
| 65 | |||
| 66 | #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 | ||
| 67 | #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 | ||
| 68 | #define K_SYS_REVISION_BCM1250_B1 0x10 | ||
| 69 | #define K_SYS_REVISION_BCM1250_B2 0x11 | ||
| 70 | |||
| 71 | #define K_SYS_REVISION_BCM1250_C0 0x20 | ||
| 72 | #define K_SYS_REVISION_BCM1250_C1 0x21 | ||
| 73 | #define K_SYS_REVISION_BCM1250_C2 0x22 | ||
| 74 | #define K_SYS_REVISION_BCM1250_C3 0x23 | ||
| 62 | 75 | ||
| 76 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | ||
| 63 | /* XXX: discourage people from using these constants. */ | 77 | /* XXX: discourage people from using these constants. */ |
| 64 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 | 78 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 |
| 65 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 | 79 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 |
| 66 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 | 80 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 |
| 67 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 | 81 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 |
| 82 | #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 | ||
| 68 | #endif /* 1250 */ | 83 | #endif /* 1250 */ |
| 69 | 84 | ||
| 70 | #if SIBYTE_HDR_FEATURE_CHIP(112x) | 85 | #define K_SYS_REVISION_BCM112x_A1 0x20 |
| 71 | #define K_SYS_REVISION_BCM112x_A1 32 | 86 | #define K_SYS_REVISION_BCM112x_A2 0x21 |
| 72 | #define K_SYS_REVISION_BCM112x_A2 33 | 87 | #define K_SYS_REVISION_BCM112x_A3 0x22 |
| 73 | #endif /* 112x */ | 88 | #define K_SYS_REVISION_BCM112x_A4 0x23 |
| 89 | |||
| 90 | #define K_SYS_REVISION_BCM1480_S0 0x01 | ||
| 91 | #define K_SYS_REVISION_BCM1480_A1 0x02 | ||
| 92 | #define K_SYS_REVISION_BCM1480_A2 0x03 | ||
| 93 | #define K_SYS_REVISION_BCM1480_A3 0x04 | ||
| 94 | #define K_SYS_REVISION_BCM1480_B0 0x11 | ||
| 95 | |||
| 96 | /*Cache size - 23:20 of revision register*/ | ||
| 97 | #define S_SYS_L2C_SIZE _SB_MAKE64(20) | ||
| 98 | #define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) | ||
| 99 | #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) | ||
| 100 | #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) | ||
| 101 | |||
| 102 | #define K_SYS_L2C_SIZE_1MB 0 | ||
| 103 | #define K_SYS_L2C_SIZE_512KB 5 | ||
| 104 | #define K_SYS_L2C_SIZE_256KB 2 | ||
| 105 | #define K_SYS_L2C_SIZE_128KB 1 | ||
| 106 | |||
| 107 | #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB | ||
| 108 | #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB | ||
| 109 | #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB | ||
| 110 | |||
| 111 | |||
| 112 | /* Number of CPU cores, bits 27:24 of revision register*/ | ||
| 113 | #define S_SYS_NUM_CPUS _SB_MAKE64(24) | ||
| 114 | #define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) | ||
| 115 | #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) | ||
| 116 | #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) | ||
| 117 | |||
| 74 | 118 | ||
| 75 | /* XXX: discourage people from using these constants. */ | 119 | /* XXX: discourage people from using these constants. */ |
| 76 | #define S_SYS_PART _SB_MAKE64(16) | 120 | #define S_SYS_PART _SB_MAKE64(16) |
| @@ -83,6 +127,8 @@ | |||
| 83 | #define K_SYS_PART_BCM1120 0x1121 | 127 | #define K_SYS_PART_BCM1120 0x1121 |
| 84 | #define K_SYS_PART_BCM1125 0x1123 | 128 | #define K_SYS_PART_BCM1125 0x1123 |
| 85 | #define K_SYS_PART_BCM1125H 0x1124 | 129 | #define K_SYS_PART_BCM1125H 0x1124 |
| 130 | #define K_SYS_PART_BCM1122 0x1113 | ||
| 131 | |||
| 86 | 132 | ||
| 87 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ | 133 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ |
| 88 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) | 134 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) |
| @@ -96,6 +142,8 @@ | |||
| 96 | #define K_SYS_SOC_TYPE_BCM1125 0x3 | 142 | #define K_SYS_SOC_TYPE_BCM1125 0x3 |
| 97 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 | 143 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 |
| 98 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ | 144 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ |
| 145 | #define K_SYS_SOC_TYPE_BCM1x80 0x6 | ||
| 146 | #define K_SYS_SOC_TYPE_BCM1x55 0x7 | ||
| 99 | 147 | ||
| 100 | /* | 148 | /* |
| 101 | * Calculate correct SOC type given a copy of system revision register. | 149 | * Calculate correct SOC type given a copy of system revision register. |
| @@ -127,10 +175,12 @@ | |||
| 127 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) | 175 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) |
| 128 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) | 176 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) |
| 129 | 177 | ||
| 130 | /* System Manufacturing Register | 178 | /* |
| 131 | * Register: SCD_SYSTEM_MANUF | 179 | * System Manufacturing Register |
| 132 | */ | 180 | * Register: SCD_SYSTEM_MANUF |
| 181 | */ | ||
| 133 | 182 | ||
| 183 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 134 | /* Wafer ID: bits 31:0 */ | 184 | /* Wafer ID: bits 31:0 */ |
| 135 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) | 185 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) |
| 136 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) | 186 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) |
| @@ -139,8 +189,8 @@ | |||
| 139 | 189 | ||
| 140 | #define S_SYS_BIN _SB_MAKE64(32) | 190 | #define S_SYS_BIN _SB_MAKE64(32) |
| 141 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) | 191 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) |
| 142 | #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) | 192 | #define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) |
| 143 | #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) | 193 | #define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) |
| 144 | 194 | ||
| 145 | /* Wafer ID: bits 39:36 */ | 195 | /* Wafer ID: bits 39:36 */ |
| 146 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) | 196 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) |
| @@ -163,12 +213,14 @@ | |||
| 163 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) | 213 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) |
| 164 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) | 214 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) |
| 165 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) | 215 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) |
| 216 | #endif | ||
| 166 | 217 | ||
| 167 | /* | 218 | /* |
| 168 | * System Config Register (Table 4-2) | 219 | * System Config Register (Table 4-2) |
| 169 | * Register: SCD_SYSTEM_CFG | 220 | * Register: SCD_SYSTEM_CFG |
| 170 | */ | 221 | */ |
| 171 | 222 | ||
| 223 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 172 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) | 224 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) |
| 173 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) | 225 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) |
| 174 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) | 226 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) |
| @@ -253,6 +305,8 @@ | |||
| 253 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) | 305 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) |
| 254 | #endif /* 1250 PASS2 || 112x PASS1 */ | 306 | #endif /* 1250 PASS2 || 112x PASS1 */ |
| 255 | 307 | ||
| 308 | #endif | ||
| 309 | |||
| 256 | 310 | ||
| 257 | /* | 311 | /* |
| 258 | * Mailbox Registers (Table 4-3) | 312 | * Mailbox Registers (Table 4-3) |
| @@ -326,6 +380,7 @@ | |||
| 326 | * System Performance Counters | 380 | * System Performance Counters |
| 327 | */ | 381 | */ |
| 328 | 382 | ||
| 383 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 329 | #define S_SPC_CFG_SRC0 0 | 384 | #define S_SPC_CFG_SRC0 0 |
| 330 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) | 385 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) |
| 331 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) | 386 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) |
| @@ -348,6 +403,7 @@ | |||
| 348 | 403 | ||
| 349 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) | 404 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) |
| 350 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) | 405 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) |
| 406 | #endif | ||
| 351 | 407 | ||
| 352 | 408 | ||
| 353 | /* | 409 | /* |
| @@ -412,6 +468,7 @@ | |||
| 412 | * Address Trap Registers | 468 | * Address Trap Registers |
| 413 | */ | 469 | */ |
| 414 | 470 | ||
| 471 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 415 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) | 472 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) |
| 416 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) | 473 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) |
| 417 | 474 | ||
| @@ -436,7 +493,6 @@ | |||
| 436 | #define K_BUS_AGENT_IOB0 2 | 493 | #define K_BUS_AGENT_IOB0 2 |
| 437 | #define K_BUS_AGENT_IOB1 3 | 494 | #define K_BUS_AGENT_IOB1 3 |
| 438 | #define K_BUS_AGENT_SCD 4 | 495 | #define K_BUS_AGENT_SCD 4 |
| 439 | #define K_BUS_AGENT_RESERVED 5 | ||
| 440 | #define K_BUS_AGENT_L2C 6 | 496 | #define K_BUS_AGENT_L2C 6 |
| 441 | #define K_BUS_AGENT_MC 7 | 497 | #define K_BUS_AGENT_MC 7 |
| 442 | 498 | ||
| @@ -454,10 +510,14 @@ | |||
| 454 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 | 510 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 |
| 455 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 | 511 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 |
| 456 | 512 | ||
| 513 | #endif /* 1250/112x */ | ||
| 514 | |||
| 457 | /* | 515 | /* |
| 458 | * Trace Buffer Config register | 516 | * Trace Buffer Config register |
| 459 | */ | 517 | */ |
| 460 | 518 | ||
| 519 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 520 | |||
| 461 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | 521 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) |
| 462 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | 522 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) |
| 463 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | 523 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) |
| @@ -475,6 +535,8 @@ | |||
| 475 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) | 535 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) |
| 476 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) | 536 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) |
| 477 | 537 | ||
| 538 | #endif /* 1250/112x */ | ||
| 539 | |||
| 478 | /* | 540 | /* |
| 479 | * Trace Event registers | 541 | * Trace Event registers |
| 480 | */ | 542 | */ |
| @@ -578,5 +640,7 @@ | |||
| 578 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) | 640 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) |
| 579 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) | 641 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) |
| 580 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) | 642 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) |
| 643 | #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) | ||
| 644 | #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) | ||
| 581 | 645 | ||
| 582 | #endif | 646 | #endif |
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 335c53e92936..c41948221837 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h | |||
| @@ -47,6 +47,7 @@ | |||
| 47 | 47 | ||
| 48 | #define K_SMB_FREQ_400KHZ 0x1F | 48 | #define K_SMB_FREQ_400KHZ 0x1F |
| 49 | #define K_SMB_FREQ_100KHZ 0x7D | 49 | #define K_SMB_FREQ_100KHZ 0x7D |
| 50 | #define K_SMB_FREQ_10KHZ 1250 | ||
| 50 | 51 | ||
| 51 | #define S_SMB_CMD 0 | 52 | #define S_SMB_CMD 0 |
| 52 | #define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) | 53 | #define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) |
| @@ -58,7 +59,11 @@ | |||
| 58 | 59 | ||
| 59 | #define M_SMB_ERR_INTR _SB_MAKEMASK1(0) | 60 | #define M_SMB_ERR_INTR _SB_MAKEMASK1(0) |
| 60 | #define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) | 61 | #define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) |
| 61 | #define M_SMB_DATA_OUT _SB_MAKEMASK1(4) | 62 | |
| 63 | #define S_SMB_DATA_OUT 4 | ||
| 64 | #define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) | ||
| 65 | #define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) | ||
| 66 | |||
| 62 | #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) | 67 | #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) |
| 63 | #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR | 68 | #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR |
| 64 | #define M_SMB_CLK_OUT _SB_MAKEMASK1(6) | 69 | #define M_SMB_CLK_OUT _SB_MAKEMASK1(6) |
| @@ -71,8 +76,23 @@ | |||
| 71 | #define M_SMB_BUSY _SB_MAKEMASK1(0) | 76 | #define M_SMB_BUSY _SB_MAKEMASK1(0) |
| 72 | #define M_SMB_ERROR _SB_MAKEMASK1(1) | 77 | #define M_SMB_ERROR _SB_MAKEMASK1(1) |
| 73 | #define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) | 78 | #define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) |
| 74 | #define M_SMB_REF _SB_MAKEMASK1(6) | 79 | |
| 75 | #define M_SMB_DATA_IN _SB_MAKEMASK1(7) | 80 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 81 | #define S_SMB_SCL_IN 5 | ||
| 82 | #define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) | ||
| 83 | #define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) | ||
| 84 | #define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) | ||
| 85 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 86 | |||
| 87 | #define S_SMB_REF 6 | ||
| 88 | #define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) | ||
| 89 | #define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) | ||
| 90 | #define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) | ||
| 91 | |||
| 92 | #define S_SMB_DATA_IN 7 | ||
| 93 | #define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) | ||
| 94 | #define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) | ||
| 95 | #define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) | ||
| 76 | 96 | ||
| 77 | /* | 97 | /* |
| 78 | * SMBus Start/Command registers (Table 14-9) | 98 | * SMBus Start/Command registers (Table 14-9) |
| @@ -132,16 +152,14 @@ | |||
| 132 | #define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) | 152 | #define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) |
| 133 | 153 | ||
| 134 | 154 | ||
| 135 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 155 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 136 | 156 | ||
| 137 | #define S_SMB_CMDH 8 | 157 | #define S_SMB_CMDH 8 |
| 138 | #define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD) | 158 | #define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) |
| 139 | #define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMBH_CMD) | 159 | #define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) |
| 140 | 160 | ||
| 141 | #define M_SMB_EXTEND _SB_MAKEMASK1(14) | 161 | #define M_SMB_EXTEND _SB_MAKEMASK1(14) |
| 142 | 162 | ||
| 143 | #define M_SMB_DIR _SB_MAKEMASK1(13) | ||
| 144 | |||
| 145 | #define S_SMB_DFMT 8 | 163 | #define S_SMB_DFMT 8 |
| 146 | #define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) | 164 | #define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) |
| 147 | #define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) | 165 | #define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) |
| @@ -165,6 +183,23 @@ | |||
| 165 | #define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) | 183 | #define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) |
| 166 | #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) | 184 | #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) |
| 167 | 185 | ||
| 168 | #endif /* 1250 PASS2 || 112x PASS1 */ | 186 | #define S_SMB_AFMT 11 |
| 187 | #define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) | ||
| 188 | #define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) | ||
| 189 | #define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) | ||
| 190 | |||
| 191 | #define K_SMB_AFMT_NONE 0 | ||
| 192 | #define K_SMB_AFMT_ADDR 1 | ||
| 193 | #define K_SMB_AFMT_ADDR_CMD1BYTE 2 | ||
| 194 | #define K_SMB_AFMT_ADDR_CMD2BYTE 3 | ||
| 195 | |||
| 196 | #define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE) | ||
| 197 | #define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR) | ||
| 198 | #define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE) | ||
| 199 | #define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE) | ||
| 200 | |||
| 201 | #define M_SMB_DIR _SB_MAKEMASK1(13) | ||
| 202 | |||
| 203 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 169 | 204 | ||
| 170 | #endif | 205 | #endif |
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index 923ea4f44e0f..9f02e6884ae1 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h | |||
| @@ -240,7 +240,12 @@ | |||
| 240 | */ | 240 | */ |
| 241 | 241 | ||
| 242 | #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) | 242 | #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) |
| 243 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) | 243 | |
| 244 | #define S_DUART_ISR_RX_A 1 | ||
| 245 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) | ||
| 246 | #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) | ||
| 247 | #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) | ||
| 248 | |||
| 244 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) | 249 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) |
| 245 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) | 250 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) |
| 246 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) | 251 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) |
| @@ -331,7 +336,7 @@ | |||
| 331 | #define M_DUART_OUT_PIN_CLR(chan) \ | 336 | #define M_DUART_OUT_PIN_CLR(chan) \ |
| 332 | (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) | 337 | (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) |
| 333 | 338 | ||
| 334 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | 339 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) |
| 335 | /* | 340 | /* |
| 336 | * Full Interrupt Control Register | 341 | * Full Interrupt Control Register |
| 337 | */ | 342 | */ |
| @@ -345,7 +350,7 @@ | |||
| 345 | #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) | 350 | #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) |
| 346 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) | 351 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) |
| 347 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) | 352 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) |
| 348 | #endif /* 1250 PASS2 || 112x PASS1 */ | 353 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ |
| 349 | 354 | ||
| 350 | 355 | ||
| 351 | /* ********************************************************************** */ | 356 | /* ********************************************************************** */ |