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-rw-r--r--include/asm-mips/irq_gt641xx.h60
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h26
-rw-r--r--include/asm-mips/mach-cobalt/irq.h58
3 files changed, 118 insertions, 26 deletions
diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h
new file mode 100644
index 000000000000..f9a7c3ac2e66
--- /dev/null
+++ b/include/asm-mips/irq_gt641xx.h
@@ -0,0 +1,60 @@
1/*
2 * Galileo/Marvell GT641xx IRQ definitions.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#ifndef _ASM_IRQ_GT641XX_H
21#define _ASM_IRQ_GT641XX_H
22
23#ifndef GT641XX_IRQ_BASE
24#define GT641XX_IRQ_BASE 8
25#endif
26
27#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
28#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
29#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
30#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
31#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
32#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
33#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
34#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
35#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
36#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
37#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
38#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
39#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
40#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
41#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
42#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
43#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
44#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
45#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
46#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
47#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
48#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
49#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
50#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
51#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
52#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
53#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
54#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
55#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
56
57extern void gt641xx_irq_dispatch(void);
58extern void gt641xx_irq_init(void);
59
60#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 9c9d2b998ca4..408eeccbe512 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -12,32 +12,6 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15#include <irq.h>
16
17/*
18 * i8259 legacy interrupts used on Cobalt:
19 *
20 * 8 - RTC
21 * 9 - PCI
22 * 14 - IDE0
23 * 15 - IDE1
24 */
25#define COBALT_QUBE_SLOT_IRQ 9
26
27/*
28 * CPU IRQs are 16 ... 23
29 */
30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
31
32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
33#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
34#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
35#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
36#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
37#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
38#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
39#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
40
41/* 15/*
42 * PCI configuration space manifest constants. These are wired into 16 * PCI configuration space manifest constants. These are wired into
43 * the board layout according to the PCI spec to enable the software 17 * the board layout according to the PCI spec to enable the software
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
new file mode 100644
index 000000000000..179d0e850b59
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -0,0 +1,58 @@
1/*
2 * Cobalt IRQ definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
12 */
13#ifndef _ASM_COBALT_IRQ_H
14#define _ASM_COBALT_IRQ_H
15
16/*
17 * i8259 interrupts used on Cobalt:
18 *
19 * 8 - RTC
20 * 9 - PCI slot
21 * 14 - IDE0
22 * 15 - IDE1(no connector on board)
23 */
24#define I8259A_IRQ_BASE 0
25
26#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
27
28/*
29 * CPU interrupts used on Cobalt:
30 *
31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
33 * 2 - cascade GT64111
34 * 3 - ethernet or SCSI host controller
35 * 4 - ethernet
36 * 5 - 16550 UART
37 * 6 - cascade i8259
38 * 7 - CP0 counter (unused)
39 */
40#define MIPS_CPU_IRQ_BASE 16
41
42#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50
51
52#define GT641XX_IRQ_BASE 24
53
54#include <asm/irq_gt641xx.h>
55
56#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
57
58#endif /* _ASM_COBALT_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 20:43:40 -0500