84 files changed, 2631 insertions, 1876 deletions

diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index a798d6299a79..1232be3885b0 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -283,10 +283,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       beqz    %0, 2f                                  \n"
                 "        subu   %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "1:                                                     \n"
                 "       .subsection 2                                   \n"
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
+                "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
@@ -664,10 +664,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       beqz    %0, 2f                                  \n"
                 "        dsubu  %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "1:                                                     \n"
                 "       .subsection 2                                   \n"
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
+                "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
index 9d8cfbb5e796..8e9ac313ca3b 100644
--- a/include/asm-mips/barrier.h
+++ b/include/asm-mips/barrier.h
@@ -92,11 +92,25 @@
 #define fast_wmb()      __sync()
 #define fast_rmb()      __sync()
 #define fast_mb()       __sync()
+#ifdef CONFIG_SGI_IP28
+#define fast_iob()                              \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "sync\n\t"                      \
+                "lw     $0,%0\n\t"              \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
+                : "memory")
+#else
 #define fast_iob()                              \
         do {                                    \
                 __sync();                       \
                 __fast_iob();                   \
         } while (0)
+#endif
 
 #ifdef CONFIG_CPU_HAS_WB
 
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 642724734eba..49df8c4c9d25 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "2:     b       1b                                      \n"
                 "       .previous                                       \n"
                 : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ri" (bit), "m" (*m)
+                : "ir" (bit), "m" (*m)
                 : "memory");
 #endif
         } else if (cpu_has_llsc) {
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index e031bdff9920..610fe3af7a03 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -26,13 +26,6 @@
 #define  MACH_UNKNOWN           0       /* whatever...                  */
 
 /*
- * Valid machtype values for group JAZZ
- */
-#define  MACH_ACER_PICA_61      0       /* Acer PICA-61 (PICA1)         */
-#define  MACH_MIPS_MAGNUM_4000  1       /* Mips Magnum 4000 "RC4030"    */
-#define  MACH_OLIVETTI_M700     2       /* Olivetti M700-10 (-15 ??)    */
-
-/*
  * Valid machtype for group DEC
  */
 #define  MACH_DSUNKNOWN         0
@@ -48,42 +41,6 @@
 #define  MACH_DS5900            10      /* DECsystem 5900               */
 
 /*
- * Valid machtype for group SNI_RM
- */
-#define  MACH_SNI_RM200_PCI     0       /* RM200/RM300/RM400 PCI series */
-
-/*
- * Valid machtype for group SGI
- */
-#define  MACH_SGI_IP22          0       /* Indy, Indigo2, Challenge S   */
-#define  MACH_SGI_IP27          1       /* Origin 200, Origin 2000, Onyx 2 */
-#define  MACH_SGI_IP28          2       /* Indigo2 Impact               */
-#define  MACH_SGI_IP32          3       /* O2                           */
-#define  MACH_SGI_IP30          4       /* Octane, Octane2              */
-
-/*
- * Valid machtypes for group Toshiba
- */
-#define  MACH_PALLAS            0
-#define  MACH_TOPAS             1
-#define  MACH_JMR               2
-#define  MACH_TOSHIBA_JMR3927   3       /* JMR-TX3927 CPU/IO board */
-#define  MACH_TOSHIBA_RBTX4927  4
-#define  MACH_TOSHIBA_RBTX4937  5
-#define  MACH_TOSHIBA_RBTX4938  6
-
-/*
- * Valid machtype for group LASAT
- */
-#define  MACH_LASAT_100         0       /* Masquerade II/SP100/SP50/SP25 */
-#define  MACH_LASAT_200         1       /* Masquerade PRO/SP200 */
-
-/*
- * Valid machtype for group NEC EMMA2RH
- */
-#define  MACH_NEC_MARKEINS      0       /* NEC EMMA2RH Mark-eins        */
-
-/*
  * Valid machtype for group PMC-MSP
  */
 #define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
@@ -94,6 +51,12 @@
 #define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
 #define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
 
+/*
+ * Valid machtype for group Mikrotik
+ */
+#define MACH_MIKROTIK_RB532     0       /* Mikrotik RouterBoard 532     */
+#define MACH_MIKROTIK_RB532A    1       /* Mikrotik RouterBoard 532A    */
+
 #define CL_SIZE                 COMMAND_LINE_SIZE
 
 extern char *system_type;
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 0c5a358863f3..2de73dbb2e9e 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -56,7 +56,7 @@ struct cpuinfo_mips {
         struct cache_desc       tcache; /* Tertiary/split secondary cache */
         int                     srsets; /* Shadow register sets */
         int                     core;   /* physical core number */
-#if defined(CONFIG_MIPS_MT_SMTC)
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
         /*
          * In the MIPS MT "SMTC" model, each TC is considered
          * to be a "CPU" for the purposes of scheduling, but
@@ -64,7 +64,7 @@ struct cpuinfo_mips {
          * to all TCs within the same VPE.
          */
         int                     vpe_id;  /* Virtual Processor number */
-#endif /* CONFIG_MIPS_MT */
+#endif
 #ifdef CONFIG_MIPS_MT_SMTC
         int                     tc_id;   /* Thread Context number */
 #endif
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 1c35cac6f35b..229a786101d9 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -66,8 +66,10 @@
 #define PRID_IMP_RM7000         0x2700
 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
 #define PRID_IMP_RM9000         0x3400
+#define PRID_IMP_LOONGSON1      0x4200
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
+#define PRID_IMP_LOONGSON2      0x6300
 
 #define PRID_IMP_UNKNOWN        0xff00
 
@@ -90,8 +92,6 @@
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
 #define PRID_IMP_1004K          0x9900
-#define PRID_IMP_LOONGSON1      0x4200
-#define PRID_IMP_LOONGSON2      0x6300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index 15fe8f881e60..56d22dc8803a 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -6,7 +6,7 @@
  *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
  *      definitions.
  *
- *      Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -54,11 +54,11 @@
  */
 #define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
 #define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN4K_MB_INT_MT          (1<<3)          /* ??? */
+#define KN4K_MB_INT_MT          (1<<3)          /* I/O ASIC cascade */
 
 /*
  * Bits for the MB control & status register.
- * Set to 0x00bf8001 on my system by the ROM.
+ * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
  */
 #define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
 #define KN4K_MB_CSR_F           (1<<1)          /* ??? */
@@ -69,7 +69,8 @@
 #define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
 #define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
 #define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* ??? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
 #define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_W           (1<<31)         /* ??? */
 
 #endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
index 230b3f1b69b1..c64afb40cd06 100644
--- a/include/asm-mips/dma-mapping.h
+++ b/include/asm-mips/dma-mapping.h
@@ -42,7 +42,7 @@ extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
         int nelems, enum dma_data_direction direction);
 extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
         int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(dma_addr_t dma_addr);
+extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
 extern int dma_supported(struct device *dev, u64 mask);
 
 static inline int
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index e59d4c039661..8a3ef247659a 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -35,6 +35,8 @@ extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
 extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
 
 extern void fpu_emulator_init_fpu(void);
+extern int fpu_emulator_save_context(struct sigcontext __user *sc);
+extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
 extern void _init_fpu(void);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
index 3a492f225f00..954807d9d66a 100644
--- a/include/asm-mips/gic.h
+++ b/include/asm-mips/gic.h
@@ -24,8 +24,8 @@
 
 #define MSK(n) ((1 << (n)) - 1)
 #define REG32(addr)             (*(volatile unsigned int *) (addr))
-#define REG(base, offs)         REG32((unsigned int)(base) + offs##_##OFS)
-#define REGP(base, phys)        REG32((unsigned int)(base) + (phys))
+#define REG(base, offs)         REG32((unsigned long)(base) + offs##_##OFS)
+#define REGP(base, phys)        REG32((unsigned long)(base) + (phys))
 
 /* Accessors */
 #define GIC_REG(segment, offset) \
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
deleted file mode 100644
index cc88aed23f0f..000000000000
--- a/include/asm-mips/inventory.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Miguel de Icaza
- */
-#ifndef __ASM_INVENTORY_H
-#define __ASM_INVENTORY_H
-
-#include <linux/compiler.h>
-
-typedef struct inventory_s {
-        struct inventory_s *inv_next;
-        int    inv_class;
-        int    inv_type;
-        int    inv_controller;
-        int    inv_unit;
-        int    inv_state;
-} inventory_t;
-
-extern int inventory_items;
-
-extern void add_to_inventory(int class, int type, int controller, int unit, int state);
-extern int dump_inventory_to_user(void __user *userbuf, int size);
-extern int __init init_inventory(void);
-
-#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index f18d2816cbec..501a40b9f18d 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -161,13 +161,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
 #define bus_to_virt phys_to_virt
 
 /*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.  This implies the assumption that there is only
- * one of these busses.
- */
-extern unsigned long isa_slot_offset;
-
-/*
  * Change "struct page" to physical address.
  */
 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
@@ -528,16 +521,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
 }
 
 /*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(isa_slot_offset))
-
-/*
  * The caches on some architectures aren't dma-coherent and have need to
  * handle this in software.  There are three types of operations that
  * can be applied to dma buffers.
diff --git a/include/asm-mips/kvm.h b/include/asm-mips/kvm.h
deleted file mode 100644
index 093a5b7f796b..000000000000
--- a/include/asm-mips/kvm.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __LINUX_KVM_MIPS_H
-#define __LINUX_KVM_MIPS_H
-
-/* mips does not support KVM */
-
-#endif
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
index ea04d9262edc..caeba1e302a2 100644
--- a/include/asm-mips/lasat/lasat.h
+++ b/include/asm-mips/lasat/lasat.h
@@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns)
         __delay(ns / lasat_ndelay_divider);
 }
 
+#define IS_LASAT_200()     (current_cpu_data.cputype == CPU_R5000)
+
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 #define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index bafe68b10614..1c37d70579b8 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -4,10 +4,10 @@
 #define LASAT_BASE_BAUD_100             (7372800 / 16)
 #define LASAT_UART_REGS_BASE_100        0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100       2
-#define LASATINT_UART_100               8
+#define LASATINT_UART_100               16
 
 /* * LASAT 200 boards serial configuration */
 #define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
 #define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
 #define LASAT_UART_REGS_SHIFT_200       3
-#define LASATINT_UART_200               13
+#define LASATINT_UART_200               21
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
deleted file mode 100644
index 51d337e1bbd1..000000000000
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 1999, 2000, 2005  MIPS Technologies, Inc.
- *      All rights reserved.
- *      Authors: Carsten Langgaard <carstenl@mips.com>
- *               Maciej W. Rozycki <macro@mips.com>
- * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org)
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef __ASM_MACH_ATLAS_MC146818RTC_H
-#define __ASM_MACH_ATLAS_MC146818RTC_H
-
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mips-boards/atlas.h>
-#include <asm/mips-boards/atlasint.h>
-
-#define ARCH_RTC_LOCATION
-
-#define RTC_PORT(x)     (ATLAS_RTC_ADR_REG + (x) * 8)
-#define RTC_IO_EXTENT   0x100
-#define RTC_IOMAPPED    0
-#define RTC_IRQ         ATLAS_INT_RTC
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
-        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
-
-        *ireg = addr;
-        return *dreg;
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
-        volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
-
-        *ireg = addr;
-        *dreg = data;
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
-
-#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 1b5064dac007..0d302bad4492 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -615,6 +615,7 @@ enum soc_au1500_ints {
         AU1000_RTC_MATCH1_INT,
         AU1000_RTC_MATCH2_INT,
         AU1500_PCI_ERR_INT,
+        AU1500_RESERVED_INT,
         AU1000_USB_DEV_REQ_INT,
         AU1000_USB_DEV_SUS_INT,
         AU1000_USB_HOST_INT,
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
index 9e0028f60a43..c35e20918490 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -38,15 +38,15 @@
 #ifndef __ASM_AU1100_MMC_H
 #define __ASM_AU1100_MMC_H
 
-
-#define NUM_AU1100_MMC_CONTROLLERS      2
-
-#if defined(CONFIG_SOC_AU1100)
-#define AU1100_SD_IRQ   AU1100_SD_INT
-#elif defined(CONFIG_SOC_AU1200)
-#define AU1100_SD_IRQ   AU1200_SD_INT
-#endif
-
+#include <linux/leds.h>
+
+struct au1xmmc_platform_data {
+        int(*cd_setup)(void *mmc_host, int on);
+        int(*card_inserted)(void *mmc_host);
+        int(*card_readonly)(void *mmc_host);
+        void(*set_power)(void *mmc_host, int state);
+        struct led_classdev *led;
+};
 
 #define SD0_BASE        0xB0600000
 #define SD1_BASE        0xB0680000
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
index 40e6c489833a..08e1958e9410 100644
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ b/include/asm-mips/mach-au1x00/au1550_spi.h
@@ -6,7 +6,6 @@
 #define _AU1550_SPI_H_
 
 struct au1550_spi_info {
-        s16 bus_num;            /* defines which PSC and IRQ to use */
         u32 mainclk_hz;         /* main input clock frequency of PSC */
         u16 num_chipselect;     /* number of chipselects supported */
         void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index dae4eca2417e..892b7f168eb4 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -204,6 +204,14 @@ typedef struct	psc_i2s {
         u32     psc_i2sudf;
 } psc_i2s_t;
 
+#define PSC_I2SCFG_OFFSET       0x08
+#define PSC_I2SMASK_OFFSET      0x0C
+#define PSC_I2SPCR_OFFSET       0x10
+#define PSC_I2SSTAT_OFFSET      0x14
+#define PSC_I2SEVENT_OFFSET     0x18
+#define PSC_I2SRXTX_OFFSET      0x1C
+#define PSC_I2SUDF_OFFSET       0x20
+
 /* I2S Config Register. */
 #define PSC_I2SCFG_RT_MASK      (3 << 30)
 #define PSC_I2SCFG_RT_FIFO1     (0 << 30)
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 612ae90dbcb8..1a515b8c870f 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -146,51 +146,6 @@ typedef volatile struct
         ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
 
 /*
- * SD controller macros
- */
-
-/* Detect card. */
-#define mmc_card_inserted(_n_, _res_) \
-        do { \
-                BCSR * const bcsr = (BCSR *)0xAE000000; \
-                unsigned long mmc_wp, board_specific; \
-                if ((_n_)) { \
-                        mmc_wp = BCSR_BOARD_SD1_WP; \
-                } else { \
-                        mmc_wp = BCSR_BOARD_SD0_WP; \
-                } \
-                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
-                if (!(board_specific & mmc_wp)) {/* low means card present */ \
-                        *(int *)(_res_) = 1; \
-                } else { \
-                        *(int *)(_res_) = 0; \
-                } \
-        } while (0)
-
-/*
- * Apply power to card slot(s).
- */
-#define mmc_power_on(_n_) \
-        do { \
-                BCSR * const bcsr = (BCSR *)0xAE000000; \
-                unsigned long mmc_pwr, mmc_wp, board_specific; \
-                if ((_n_)) { \
-                        mmc_pwr = BCSR_BOARD_SD1_PWR; \
-                        mmc_wp  = BCSR_BOARD_SD1_WP; \
-                } else { \
-                        mmc_pwr = BCSR_BOARD_SD0_PWR; \
-                        mmc_wp  = BCSR_BOARD_SD0_WP; \
-                } \
-                board_specific = au_readl((unsigned long)(&bcsr->specific)); \
-                if (!(board_specific & mmc_wp)) {/* low means card present */ \
-                        board_specific |= mmc_pwr; \
-                        au_writel(board_specific, (int)(&bcsr->specific)); \
-                        au_sync(); \
-                } \
-        } while (0)
-
-
-/*
  * NAND defines
  *
  * Timing values as described in databook, * ns value stripped of the
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
index e6b376bd9d06..b4e70208da64 100644
--- a/include/asm-mips/mach-generic/gpio.h
+++ b/include/asm-mips/mach-generic/gpio.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_GENERIC_GPIO_H
 #define __ASM_MACH_GENERIC_GPIO_H
 
-#ifdef CONFIG_HAVE_GPIO_LIB
+#ifdef CONFIG_GPIOLIB
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 0f6c251f5fec..73008f7bdc93 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -19,14 +19,6 @@
 #include <linux/stddef.h>
 #include <asm/processor.h>
 
-#ifndef MAX_HWIFS
-# ifdef CONFIG_BLK_DEV_IDEPCI
-#define MAX_HWIFS       10
-# else
-#define MAX_HWIFS       6
-# endif
-#endif
-
 static __inline__ int ide_probe_legacy(void)
 {
 #ifdef CONFIG_PCI
@@ -56,46 +48,6 @@ found:
 #endif
 }
 
-static __inline__ int ide_default_irq(unsigned long base)
-{
-        switch (base) {
-                case 0x1f0: return 14;
-                case 0x170: return 15;
-                case 0x1e8: return 11;
-                case 0x168: return 10;
-                case 0x1e0: return 8;
-                case 0x160: return 12;
-                default:
-                        return 0;
-        }
-}
-
-static __inline__ unsigned long ide_default_io_base(int index)
-{
-        if (!ide_probe_legacy())
-                return 0;
-        /*
-         *      If PCI is present then it is not safe to poke around
-         *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
-         *      defined compatibility mode ports for PCI. A user can
-         *      override this using ide= but we must default safe.
-         */
-        if (no_pci_devices()) {
-                switch (index) {
-                case 2: return 0x1e8;
-                case 3: return 0x168;
-                case 4: return 0x1e0;
-                case 5: return 0x160;
-                }
-        }
-        switch (index) {
-        case 0: return 0x1f0;
-        case 1: return 0x170;
-        default:
-                return 0;
-        }
-}
-
 /* MIPS port and memory-mapped I/O string operations.  */
 static inline void __ide_flush_prologue(void)
 {
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h
index 7f3e3f9bd23a..7f3e3f9bd23a 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-malta/irq.h
index 9b9da26683c2..9b9da26683c2 100644
--- a/include/asm-mips/mach-mips/irq.h
+++ b/include/asm-mips/mach-malta/irq.h
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h
index 0b793e7bf67e..0b793e7bf67e 100644
--- a/include/asm-mips/mach-mips/kernel-entry-init.h
+++ b/include/asm-mips/mach-malta/kernel-entry-init.h
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h
index 0f863148f3b6..0f863148f3b6 100644
--- a/include/asm-mips/mach-mips/mach-gt64120.h
+++ b/include/asm-mips/mach-malta/mach-gt64120.h
diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h
index ea612f37f614..ea612f37f614 100644
--- a/include/asm-mips/mach-mips/mc146818rtc.h
+++ b/include/asm-mips/mach-malta/mc146818rtc.h
diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-malta/war.h
index 7c6931d5f45f..7c6931d5f45f 100644
--- a/include/asm-mips/mach-mips/war.h
+++ b/include/asm-mips/mach-malta/war.h
diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f3bc7efa2608
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,81 @@
+/*
+ *  IDT RC32434 specific CPU feature overrides
+ *
+ *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the
+ *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ *  Boston, MA  02110-1301, USA.
+ */
+#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_sb1_cache               0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+
+#define cpu_has_mips16                  0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+
+#define cpu_has_vtag_icache             0
+/* #define cpu_has_dc_aliases           ? */
+/* #define cpu_has_ic_fills_f_dc        ? */
+/* #define cpu_has_pindexed_dcache      ? */
+
+/* #define cpu_icache_snoops_remote_store       ? */
+
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_mipsmt                  0
+
+/* #define cpu_has_nofpuex              ? */
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#define cpu_has_64bit_gp_regs           0
+#define cpu_has_64bit_addresses         0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+
+#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h
new file mode 100644
index 000000000000..291e2cf9dde0
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
+/*
+ *  Definitions for the DDR registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _ASM_RC32434_DDR_H_
+#define _ASM_RC32434_DDR_H_
+
+#include <asm/mach-rc32434/rb.h>
+
+/* DDR register structure */
+struct ddr_ram {
+        u32 ddrbase;
+        u32 ddrmask;
+        u32 res1;
+        u32 res2;
+        u32 ddrc;
+        u32 ddrabase;
+        u32 ddramask;
+        u32 ddramap;
+        u32 ddrcust;
+        u32 ddrrdc;
+        u32 ddrspare;
+};
+
+#define DDR0_PHYS_ADDR          0x18018000
+
+/* DDR banks masks */
+#define DDR_MASK                0xffff0000
+#define DDR0_BASE_MSK           DDR_MASK
+#define DDR1_BASE_MSK           DDR_MASK
+
+/* DDR bank0 registers */
+#define RC32434_DDR0_ATA_BIT            5
+#define RC32434_DDR0_ATA_MSK            0x000000E0
+#define RC32434_DDR0_DBW_BIT            8
+#define RC32434_DDR0_DBW_MSK            0x00000100
+#define RC32434_DDR0_WR_BIT             9
+#define RC32434_DDR0_WR_MSK             0x00000600
+#define RC32434_DDR0_PS_BIT             11
+#define RC32434_DDR0_PS_MSK             0x00001800
+#define RC32434_DDR0_DTYPE_BIT          13
+#define RC32434_DDR0_DTYPE_MSK          0x0000e000
+#define RC32434_DDR0_RFC_BIT            16
+#define RC32434_DDR0_RFC_MSK            0x000f0000
+#define RC32434_DDR0_RP_BIT             20
+#define RC32434_DDR0_RP_MSK             0x00300000
+#define RC32434_DDR0_AP_BIT             22
+#define RC32434_DDR0_AP_MSK             0x00400000
+#define RC32434_DDR0_RCD_BIT            23
+#define RC32434_DDR0_RCD_MSK            0x01800000
+#define RC32434_DDR0_CL_BIT             25
+#define RC32434_DDR0_CL_MSK             0x06000000
+#define RC32434_DDR0_DBM_BIT            27
+#define RC32434_DDR0_DBM_MSK            0x08000000
+#define RC32434_DDR0_SDS_BIT            28
+#define RC32434_DDR0_SDS_MSK            0x10000000
+#define RC32434_DDR0_ATP_BIT            29
+#define RC32434_DDR0_ATP_MSK            0x60000000
+#define RC32434_DDR0_RE_BIT             31
+#define RC32434_DDR0_RE_MSK             0x80000000
+
+/* DDR bank C registers */
+#define RC32434_DDRC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DDRC_CES_BIT            0
+#define RC32434_DDRC_ACE_BIT            1
+
+/* Custom DDR bank registers */
+#define RC32434_DCST_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DCST_CS_BIT             0
+#define RC32434_DCST_CS_MSK             0x00000003
+#define RC32434_DCST_WE_BIT             2
+#define RC32434_DCST_RAS_BIT            3
+#define RC32434_DCST_CAS_BIT            4
+#define RC32434_DSCT_CKE_BIT            5
+#define RC32434_DSCT_BA_BIT             6
+#define RC32434_DSCT_BA_MSK             0x000000c0
+
+/* DDR QSC registers */
+#define RC32434_QSC_DM_BIT              0
+#define RC32434_QSC_DM_MSK              0x00000003
+#define RC32434_QSC_DQSBS_BIT           2
+#define RC32434_QSC_DQSBS_MSK           0x000000fc
+#define RC32434_QSC_DB_BIT              8
+#define RC32434_QSC_DB_MSK              0x00000100
+#define RC32434_QSC_DBSP_BIT            9
+#define RC32434_QSC_DBSP_MSK            0x01fffe00
+#define RC32434_QSC_BDP_BIT             25
+#define RC32434_QSC_BDP_MSK             0x7e000000
+
+/* DDR LLC registers */
+#define RC32434_LLC_EAO_BIT             0
+#define RC32434_LLC_EAO_MSK             0x00000001
+#define RC32434_LLC_EO_BIT              1
+#define RC32434_LLC_EO_MSK              0x0000003e
+#define RC32434_LLC_FS_BIT              6
+#define RC32434_LLC_FS_MSK              0x000000c0
+#define RC32434_LLC_AS_BIT              8
+#define RC32434_LLC_AS_MSK              0x00000700
+#define RC32434_LLC_SP_BIT              11
+#define RC32434_LLC_SP_MSK              0x001ff800
+
+/* DDR LLFC registers */
+#define RC32434_LLFC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_LLFC_MEN_BIT            0
+#define RC32434_LLFC_EAN_BIT            1
+#define RC32434_LLFC_FF_BIT             2
+
+/* DDR DLLTA registers */
+#define RC32434_DLLTA_ADDR_BIT          2
+#define RC32434_DLLTA_ADDR_MSK          0xfffffffc
+
+/* DDR DLLED registers */
+#define RC32434_DLLED_MSK(x)            BIT_TO_MASK(x)
+#define RC32434_DLLED_DBE_BIT           0
+#define RC32434_DLLED_DTE_BIT           1
+
+#endif  /* _ASM_RC32434_DDR_H_ */
diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h
new file mode 100644
index 000000000000..5f898b5873f7
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef __ASM_RC32434_DMA_H
+#define __ASM_RC32434_DMA_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define DMA0_BASE_ADDR                  0x18040000
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+struct dma_desc {
+        u32 control;                    /* Control. use DMAD_* */
+        u32 ca;                         /* Current Address. */
+        u32 devcs;                      /* Device control and status. */
+        u32 link;                       /* Next descriptor in chain. */
+};
+
+#define DMA_DESC_SIZ                    sizeof(struct dma_desc)
+#define DMA_DESC_COUNT_BIT              0
+#define DMA_DESC_COUNT_MSK              0x0003ffff
+#define DMA_DESC_DS_BIT                 20
+#define DMA_DESC_DS_MSK                 0x00300000
+
+#define DMA_DESC_DEV_CMD_BIT            22
+#define DMA_DESC_DEV_CMD_MSK            0x01c00000
+
+/* DMA command sizes */
+#define DMA_DESC_DEV_CMD_BYTE           0
+#define DMA_DESC_DEV_CMD_HLF_WD         1
+#define DMA_DESC_DEV_CMD_WORD           2
+#define DMA_DESC_DEV_CMD_2WORDS         3
+#define DMA_DESC_DEV_CMD_4WORDS         4
+#define DMA_DESC_DEV_CMD_6WORDS         5
+#define DMA_DESC_DEV_CMD_8WORDS         6
+#define DMA_DESC_DEV_CMD_16WORDS        7
+
+/* DMA descriptors interrupts */
+#define DMA_DESC_COF                    (1 << 25) /* Chain on finished */
+#define DMA_DESC_COD                    (1 << 26) /* Chain on done */
+#define DMA_DESC_IOF                    (1 << 27) /* Interrupt on finished */
+#define DMA_DESC_IOD                    (1 << 28) /* Interrupt on done */
+#define DMA_DESC_TERM                   (1 << 29) /* Terminated */
+#define DMA_DESC_DONE                   (1 << 30) /* Done */
+#define DMA_DESC_FINI                   (1 << 31) /* Finished */
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct dma_reg {
+        u32 dmac;               /* Control. */
+        u32 dmas;               /* Status. */
+        u32 dmasm;              /* Mask. */
+        u32 dmadptr;            /* Descriptor pointer. */
+        u32 dmandptr;           /* Next descriptor pointer. */
+};
+
+/* DMA channels specific registers */
+#define DMA_CHAN_RUN_BIT                (1 << 0)
+#define DMA_CHAN_DONE_BIT               (1 << 1)
+#define DMA_CHAN_MODE_BIT               (1 << 2)
+#define DMA_CHAN_MODE_MSK               0x0000000c
+#define  DMA_CHAN_MODE_AUTO             0
+#define  DMA_CHAN_MODE_BURST            1
+#define  DMA_CHAN_MODE_XFRT             2
+#define  DMA_CHAN_MODE_RSVD             3
+#define DMA_CHAN_ACT_BIT                (1 << 4)
+
+/* DMA status registers */
+#define DMA_STAT_FINI                   (1 << 0)
+#define DMA_STAT_DONE                   (1 << 1)
+#define DMA_STAT_CHAIN                  (1 << 2)
+#define DMA_STAT_ERR                    (1 << 3)
+#define DMA_STAT_HALT                   (1 << 4)
+
+/*
+ * DMA channel definitions
+ */
+
+#define DMA_CHAN_ETH_RCV                0
+#define DMA_CHAN_ETH_XMT                1
+#define DMA_CHAN_MEM_TO_FIFO            2
+#define DMA_CHAN_FIFO_TO_MEM            3
+#define DMA_CHAN_PCI_TO_MEM             4
+#define DMA_CHAN_MEM_TO_PCI             5
+#define DMA_CHAN_COUNT                  6
+
+struct dma_channel {
+        struct dma_reg ch[DMA_CHAN_COUNT];
+};
+
+#endif  /* __ASM_RC32434_DMA_H */
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h
new file mode 100644
index 000000000000..173a9f9146cd
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/dma_v.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef _ASM_RC32434_DMA_V_H_
+#define _ASM_RC32434_DMA_V_H_
+
+#include  <asm/mach-rc32434/dma.h>
+#include  <asm/mach-rc32434/rc32434.h>
+
+#define DMA_CHAN_OFFSET         0x14
+#define IS_DMA_USED(X)          (((X) & \
+                                (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
+                                != 0)
+#define DMA_COUNT(count)        ((count) & DMA_DESC_COUNT_MSK)
+
+#define DMA_HALT_TIMEOUT        500
+
+static inline int rc32434_halt_dma(struct dma_reg *ch)
+{
+        int timeout = 1;
+        if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
+                __raw_writel(0, &ch->dmac);
+                for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+                        if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
+                                __raw_writel(0, &ch->dmas);
+                                break;
+                        }
+                }
+        }
+
+        return timeout ? 0 : 1;
+}
+
+static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(0, &ch->dmandptr);
+        __raw_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(dma_addr, &ch->dmandptr);
+}
+
+#endif  /* _ASM_RC32434_DMA_V_H_ */
diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h
new file mode 100644
index 000000000000..a25cbc56173d
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
+/*
+ *  Definitions for the Ethernet registers
+ *
+ *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_ETH_H
+#define __ASM_RC32434_ETH_H
+
+
+#define ETH0_BASE_ADDR          0x18060000
+
+struct eth_regs {
+        u32 ethintfc;
+        u32 ethfifott;
+        u32 etharc;
+        u32 ethhash0;
+        u32 ethhash1;
+        u32 ethu0[4];           /* Reserved. */
+        u32 ethpfs;
+        u32 ethmcp;
+        u32 eth_u1[10];         /* Reserved. */
+        u32 ethspare;
+        u32 eth_u2[42];         /* Reserved. */
+        u32 ethsal0;
+        u32 ethsah0;
+        u32 ethsal1;
+        u32 ethsah1;
+        u32 ethsal2;
+        u32 ethsah2;
+        u32 ethsal3;
+        u32 ethsah3;
+        u32 ethrbc;
+        u32 ethrpc;
+        u32 ethrupc;
+        u32 ethrfc;
+        u32 ethtbc;
+        u32 ethgpf;
+        u32 eth_u9[50];         /* Reserved. */
+        u32 ethmac1;
+        u32 ethmac2;
+        u32 ethipgt;
+        u32 ethipgr;
+        u32 ethclrt;
+        u32 ethmaxf;
+        u32 eth_u10;            /* Reserved. */
+        u32 ethmtest;
+        u32 miimcfg;
+        u32 miimcmd;
+        u32 miimaddr;
+        u32 miimwtd;
+        u32 miimrdd;
+        u32 miimind;
+        u32 eth_u11;            /* Reserved. */
+        u32 eth_u12;            /* Reserved. */
+        u32 ethcfsa0;
+        u32 ethcfsa1;
+        u32 ethcfsa2;
+};
+
+/* Ethernet interrupt registers */
+#define ETH_INT_FC_EN           (1 << 0)
+#define ETH_INT_FC_ITS          (1 << 1)
+#define ETH_INT_FC_RIP          (1 << 2)
+#define ETH_INT_FC_JAM          (1 << 3)
+#define ETH_INT_FC_OVR          (1 << 4)
+#define ETH_INT_FC_UND          (1 << 5)
+#define ETH_INT_FC_IOC          0x000000c0
+
+/* Ethernet FIFO registers */
+#define ETH_FIFI_TT_TTH_BIT     0
+#define ETH_FIFO_TT_TTH         0x0000007f
+
+/* Ethernet ARC/multicast registers */
+#define ETH_ARC_PRO             (1 << 0)
+#define ETH_ARC_AM              (1 << 1)
+#define ETH_ARC_AFM             (1 << 2)
+#define ETH_ARC_AB              (1 << 3)
+
+/* Ethernet SAL registers */
+#define ETH_SAL_BYTE_5          0x000000ff
+#define ETH_SAL_BYTE_4          0x0000ff00
+#define ETH_SAL_BYTE_3          0x00ff0000
+#define ETH_SAL_BYTE_2          0xff000000
+
+/* Ethernet SAH registers */
+#define ETH_SAH_BYTE1           0x000000ff
+#define ETH_SAH_BYTE0           0x0000ff00
+
+/* Ethernet GPF register */
+#define ETH_GPF_PTV             0x0000ffff
+
+/* Ethernet PFG register */
+#define ETH_PFS_PFD             (1 << 0)
+
+/* Ethernet CFSA[0-3] registers */
+#define ETH_CFSA0_CFSA4         0x000000ff
+#define ETH_CFSA0_CFSA5         0x0000ff00
+#define ETH_CFSA1_CFSA2         0x000000ff
+#define ETH_CFSA1_CFSA3         0x0000ff00
+#define ETH_CFSA1_CFSA0         0x000000ff
+#define ETH_CFSA1_CFSA1         0x0000ff00
+
+/* Ethernet MAC1 registers */
+#define ETH_MAC1_RE             (1 << 0)
+#define ETH_MAC1_PAF            (1 << 1)
+#define ETH_MAC1_RFC            (1 << 2)
+#define ETH_MAC1_TFC            (1 << 3)
+#define ETH_MAC1_LB             (1 << 4)
+#define ETH_MAC1_MR             (1 << 31)
+
+/* Ethernet MAC2 registers */
+#define ETH_MAC2_FD             (1 << 0)
+#define ETH_MAC2_FLC            (1 << 1)
+#define ETH_MAC2_HFE            (1 << 2)
+#define ETH_MAC2_DC             (1 << 3)
+#define ETH_MAC2_CEN            (1 << 4)
+#define ETH_MAC2_PE             (1 << 5)
+#define ETH_MAC2_VPE            (1 << 6)
+#define ETH_MAC2_APE            (1 << 7)
+#define ETH_MAC2_PPE            (1 << 8)
+#define ETH_MAC2_LPE            (1 << 9)
+#define ETH_MAC2_NB             (1 << 12)
+#define ETH_MAC2_BP             (1 << 13)
+#define ETH_MAC2_ED             (1 << 14)
+
+/* Ethernet IPGT register */
+#define ETH_IPGT                0x0000007f
+
+/* Ethernet IPGR registers */
+#define ETH_IPGR_IPGR2          0x0000007f
+#define ETH_IPGR_IPGR1          0x00007f00
+
+/* Ethernet CLRT registers */
+#define ETH_CLRT_MAX_RET        0x0000000f
+#define ETH_CLRT_COL_WIN        0x00003f00
+
+/* Ethernet MAXF register */
+#define ETH_MAXF                0x0000ffff
+
+/* Ethernet test registers */
+#define ETH_TEST_REG            (1 << 2)
+#define ETH_MCP_DIV             0x000000ff
+
+/* MII registers */
+#define ETH_MII_CFG_RSVD        0x0000000c
+#define ETH_MII_CMD_RD          (1 << 0)
+#define ETH_MII_CMD_SCN         (1 << 1)
+#define ETH_MII_REG_ADDR        0x0000001f
+#define ETH_MII_PHY_ADDR        0x00001f00
+#define ETH_MII_WTD_DATA        0x0000ffff
+#define ETH_MII_RDD_DATA        0x0000ffff
+#define ETH_MII_IND_BSY         (1 << 0)
+#define ETH_MII_IND_SCN         (1 << 1)
+#define ETH_MII_IND_NV          (1 << 2)
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+
+#define ETH_RX_FD               (1 << 0)
+#define ETH_RX_LD               (1 << 1)
+#define ETH_RX_ROK              (1 << 2)
+#define ETH_RX_FM               (1 << 3)
+#define ETH_RX_MP               (1 << 4)
+#define ETH_RX_BP               (1 << 5)
+#define ETH_RX_VLT              (1 << 6)
+#define ETH_RX_CF               (1 << 7)
+#define ETH_RX_OVR              (1 << 8)
+#define ETH_RX_CRC              (1 << 9)
+#define ETH_RX_CV               (1 << 10)
+#define ETH_RX_DB               (1 << 11)
+#define ETH_RX_LE               (1 << 12)
+#define ETH_RX_LOR              (1 << 13)
+#define ETH_RX_CES              (1 << 14)
+#define ETH_RX_LEN_BIT          16
+#define ETH_RX_LEN              0xffff0000
+
+#define ETH_TX_FD               (1 << 0)
+#define ETH_TX_LD               (1 << 1)
+#define ETH_TX_OEN              (1 << 2)
+#define ETH_TX_PEN              (1 << 3)
+#define ETH_TX_CEN              (1 << 4)
+#define ETH_TX_HEN              (1 << 5)
+#define ETH_TX_TOK              (1 << 6)
+#define ETH_TX_MP               (1 << 7)
+#define ETH_TX_BP               (1 << 8)
+#define ETH_TX_UND              (1 << 9)
+#define ETH_TX_OF               (1 << 10)
+#define ETH_TX_ED               (1 << 11)
+#define ETH_TX_EC               (1 << 12)
+#define ETH_TX_LC               (1 << 13)
+#define ETH_TX_TD               (1 << 14)
+#define ETH_TX_CRC              (1 << 15)
+#define ETH_TX_LE               (1 << 16)
+#define ETH_TX_CC               0x001E0000
+
+#endif  /* __ASM_RC32434_ETH_H */
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
new file mode 100644
index 000000000000..f946f5f45bbb
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *      All rights reserved.
+ *
+ * GPIO register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ */
+
+#ifndef _RC32434_GPIO_H_
+#define _RC32434_GPIO_H_
+
+#include <linux/types.h>
+
+struct rb532_gpio_reg {
+        u32   gpiofunc;   /* GPIO Function Register
+                           * gpiofunc[x]==0 bit = gpio
+                           * func[x]==1  bit = altfunc
+                           */
+        u32   gpiocfg;    /* GPIO Configuration Register
+                           * gpiocfg[x]==0 bit = input
+                           * gpiocfg[x]==1 bit = output
+                           */
+        u32   gpiod;      /* GPIO Data Register
+                           * gpiod[x] read/write gpio pinX status
+                           */
+        u32   gpioilevel; /* GPIO Interrupt Status Register
+                           * interrupt level (see gpioistat)
+                           */
+        u32   gpioistat;  /* Gpio Interrupt Status Register
+                           * istat[x] = (gpiod[x] == level[x])
+                           * cleared in ISR (STICKY bits)
+                           */
+        u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+};
+
+/* UART GPIO signals */
+#define RC32434_UART0_SOUT      (1 << 0)
+#define RC32434_UART0_SIN       (1 << 1)
+#define RC32434_UART0_RTS       (1 << 2)
+#define RC32434_UART0_CTS       (1 << 3)
+
+/* M & P bus GPIO signals */
+#define RC32434_MP_BIT_22       (1 << 4)
+#define RC32434_MP_BIT_23       (1 << 5)
+#define RC32434_MP_BIT_24       (1 << 6)
+#define RC32434_MP_BIT_25       (1 << 7)
+
+/* CPU GPIO signals */
+#define RC32434_CPU_GPIO        (1 << 8)
+
+/* Reserved GPIO signals */
+#define RC32434_AF_SPARE_6      (1 << 9)
+#define RC32434_AF_SPARE_4      (1 << 10)
+#define RC32434_AF_SPARE_3      (1 << 11)
+#define RC32434_AF_SPARE_2      (1 << 12)
+
+/* PCI messaging unit */
+#define RC32434_PCI_MSU_GPIO    (1 << 13)
+
+
+extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
+extern unsigned get_434_reg(unsigned reg_offs);
+extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
+extern unsigned char get_latch_u5(void);
+
+extern int rb532_gpio_get_value(unsigned gpio);
+extern void rb532_gpio_set_value(unsigned gpio, int value);
+extern int rb532_gpio_direction_input(unsigned gpio);
+extern int rb532_gpio_direction_output(unsigned gpio, int value);
+extern void rb532_gpio_set_int_level(unsigned gpio, int value);
+extern int rb532_gpio_get_int_level(unsigned gpio);
+extern void rb532_gpio_set_int_status(unsigned gpio, int value);
+extern int rb532_gpio_get_int_status(unsigned gpio);
+
+
+/* Wrappers for the arch-neutral GPIO API */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        /* Not yet implemented */
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        /* Not yet implemented */
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return rb532_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return rb532_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return rb532_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        rb532_gpio_set_value(gpio, value);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+
+/* For cansleep */
+#include <asm-generic/gpio.h>
+
+#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h
new file mode 100644
index 000000000000..fa65bc3d8807
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
+/*
+ *  Definitions for the Watchdog registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __RC32434_INTEG_H__
+#define __RC32434_INTEG_H__
+
+#include <asm/mach-rc32434/rb.h>
+
+#define INTEG0_BASE_ADDR        0x18030030
+
+struct integ {
+        u32 errcs;                      /* sticky use ERRCS_ */
+        u32 wtcount;                    /* Watchdog timer count reg. */
+        u32 wtcompare;                  /* Watchdog timer timeout value. */
+        u32 wtc;                        /* Watchdog timer control. use WTC_ */
+};
+
+/* Error counters */
+#define RC32434_ERR_WTO         0
+#define RC32434_ERR_WNE         1
+#define RC32434_ERR_UCW         2
+#define RC32434_ERR_UCR         3
+#define RC32434_ERR_UPW         4
+#define RC32434_ERR_UPR         5
+#define RC32434_ERR_UDW         6
+#define RC32434_ERR_UDR         7
+#define RC32434_ERR_SAE         8
+#define RC32434_ERR_WRE         9
+
+/* Watchdog control bits */
+#define RC32434_WTC_EN          0
+#define RC32434_WTC_TO          1
+
+#endif  /* __RC32434_INTEG_H__ */
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
new file mode 100644
index 000000000000..cb9e4725f5dc
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/irq.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_RC32434_IRQ_H
+#define __ASM_RC32434_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif  /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
new file mode 100644
index 000000000000..410638f2af74
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/pci.h
@@ -0,0 +1,481 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * Initial Release
+ */
+
+#ifndef _ASM_RC32434_PCI_H_
+#define _ASM_RC32434_PCI_H_
+
+#define epld_mask ((volatile unsigned char *)0xB900000d)
+
+#define PCI0_BASE_ADDR          0x18080000
+#define PCI_LBA_COUNT           4
+
+struct pci_map {
+        u32 address;            /* Address. */
+        u32 control;            /* Control. */
+        u32 mapping;            /* mapping. */
+};
+
+struct pci_reg {
+        u32 pcic;
+        u32 pcis;
+        u32 pcism;
+        u32 pcicfga;
+        u32 pcicfgd;
+        volatile struct pci_map pcilba[PCI_LBA_COUNT];
+        u32 pcidac;
+        u32 pcidas;
+        u32 pcidasm;
+        u32 pcidad;
+        u32 pcidma8c;
+        u32 pcidma9c;
+        u32 pcitc;
+};
+
+#define PCI_MSU_COUNT           2
+
+struct pci_msu {
+        u32 pciim[PCI_MSU_COUNT];
+        u32 pciom[PCI_MSU_COUNT];
+        u32 pciid;
+        u32 pciiic;
+        u32 pciiim;
+        u32 pciiod;
+        u32 pciioic;
+        u32 pciioim;
+};
+
+/*
+ * PCI Control Register
+ */
+
+#define PCI_CTL_EN              (1 << 0)
+#define PCI_CTL_TNR             (1 << 1)
+#define PCI_CTL_SCE             (1 << 2)
+#define PCI_CTL_IEN             (1 << 3)
+#define PCI_CTL_AAA             (1 << 4)
+#define PCI_CTL_EAP             (1 << 5)
+#define PCI_CTL_PCIM_BIT        6
+#define PCI_CTL_PCIM            0x000001c0
+
+#define PCI_CTL_PCIM_DIS        0
+#define PCI_CTL_PCIM_TNR        1 /* Satellite - target not ready */
+#define PCI_CTL_PCIM_SUS        2 /* Satellite - suspended CPU. */
+#define PCI_CTL_PCIM_EXT        3 /* Host - external arbiter. */
+#define PCI_CTL PCIM_PRIO       4 /* Host - fixed priority arb. */
+#define PCI_CTL_PCIM_RR         5 /* Host - round robin priority. */
+#define PCI_CTL_PCIM_RSVD6      6
+#define PCI_CTL_PCIM_RSVD7      7
+
+#define PCI_CTL_IGM             (1 << 9)
+
+/*
+ * PCI Status Register
+ */
+
+#define PCI_STAT_EED            (1 << 0)
+#define PCI_STAT_WR             (1 << 1)
+#define PCI_STAT_NMI            (1 << 2)
+#define PCI_STAT_II             (1 << 3)
+#define PCI_STAT_CWE            (1 << 4)
+#define PCI_STAT_CRE            (1 << 5)
+#define PCI_STAT_MDPE           (1 << 6)
+#define PCI_STAT_STA            (1 << 7)
+#define PCI_STAT_RTA            (1 << 8)
+#define PCI_STAT_RMA            (1 << 9)
+#define PCI_STAT_SSE            (1 << 10)
+#define PCI_STAT_OSE            (1 << 11)
+#define PCI_STAT_PE             (1 << 12)
+#define PCI_STAT_TAE            (1 << 13)
+#define PCI_STAT_RLE            (1 << 14)
+#define PCI_STAT_BME            (1 << 15)
+#define PCI_STAT_PRD            (1 << 16)
+#define PCI_STAT_RIP            (1 << 17)
+
+/*
+ * PCI Status Mask Register
+ */
+
+#define PCI_STATM_EED           PCI_STAT_EED
+#define PCI_STATM_WR            PCI_STAT_WR
+#define PCI_STATM_NMI           PCI_STAT_NMI
+#define PCI_STATM_II            PCI_STAT_II
+#define PCI_STATM_CWE           PCI_STAT_CWE
+#define PCI_STATM_CRE           PCI_STAT_CRE
+#define PCI_STATM_MDPE          PCI_STAT_MDPE
+#define PCI_STATM_STA           PCI_STAT_STA
+#define PCI_STATM_RTA           PCI_STAT_RTA
+#define PCI_STATM_RMA           PCI_STAT_RMA
+#define PCI_STATM_SSE           PCI_STAT_SSE
+#define PCI_STATM_OSE           PCI_STAT_OSE
+#define PCI_STATM_PE            PCI_STAT_PE
+#define PCI_STATM_TAE           PCI_STAT_TAE
+#define PCI_STATM_RLE           PCI_STAT_RLE
+#define PCI_STATM_BME           PCI_STAT_BME
+#define PCI_STATM_PRD           PCI_STAT_PRD
+#define PCI_STATM_RIP           PCI_STAT_RIP
+
+/*
+ * PCI Configuration Address Register
+ */
+#define PCI_CFGA_REG_BIT        2
+#define PCI_CFGA_REG            0x000000fc
+#define  PCI_CFGA_REG_ID        (0x00 >> 2)     /* use PCFGID */
+#define  PCI_CFGA_REG_04        (0x04 >> 2)     /* use PCFG04_ */
+#define  PCI_CFGA_REG_08        (0x08 >> 2)     /* use PCFG08_ */
+#define  PCI_CFGA_REG_0C        (0x0C >> 2)     /* use PCFG0C_ */
+#define  PCI_CFGA_REG_PBA0      (0x10 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA1      (0x14 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */
+#define  PCI_CFGA_REG_3C        (0x3C >> 2)     /* use PCFG3C_ */
+#define  PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA0M     (0x48 >> 2)
+#define  PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA1M     (0x50 >> 2)
+#define  PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA2M     (0x58 >> 2)
+#define  PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA3M     (0x60 >> 2)
+#define  PCI_CFGA_REG_PMGT      (0x64 >> 2)
+#define PCI_CFGA_FUNC_BIT       8
+#define PCI_CFGA_FUNC           0x00000700
+#define PCI_CFGA_DEV_BIT        11
+#define PCI_CFGA_DEV            0x0000f800
+#define PCI_CFGA_DEV_INTERN     0
+#define PCI_CFGA_BUS_BIT        16
+#define PCI CFGA_BUS            0x00ff0000
+#define PCI_CFGA_BUS_TYPE0      0
+#define PCI_CFGA_EN             (1 << 31)
+
+/* PCI CFG04 commands */
+#define PCI_CFG04_CMD_IO_ENA    (1 << 0)
+#define PCI_CFG04_CMD_MEM_ENA   (1 << 1)
+#define PCI_CFG04_CMD_BM_ENA    (1 << 2)
+#define PCI_CFG04_CMD_MW_INV    (1 << 4)
+#define PCI_CFG04_CMD_PAR_ENA   (1 << 6)
+#define PCI_CFG04_CMD_SER_ENA   (1 << 8)
+#define PCI_CFG04_CMD_FAST_ENA  (1 << 9)
+
+/* PCI CFG04 status fields */
+#define PCI_CFG04_STAT_BIT      16
+#define PCI_CFG04_STAT          0xffff0000
+#define PCI_CFG04_STAT_66_MHZ   (1 << 21)
+#define PCI_CFG04_STAT_FBB      (1 << 23)
+#define PCI_CFG04_STAT_MDPE     (1 << 24)
+#define PCI_CFG04_STAT_DST      (1 << 25)
+#define PCI_CFG04_STAT_STA      (1 << 27)
+#define PCI_CFG04_STAT_RTA      (1 << 28)
+#define PCI_CFG04_STAT_RMA      (1 << 29)
+#define PCI_CFG04_STAT_SSE      (1 << 30)
+#define PCI_CFG04_STAT_PE       (1 << 31)
+
+#define PCI_PBA_MSI             (1 << 0)
+#define PCI_PBA_P               (1 << 2)
+
+/* PCI PBAC registers */
+#define PCI_PBAC_MSI            (1 << 0)
+#define PCI_PBAC_P              (1 << 1)
+#define PCI_PBAC_SIZE_BIT       2
+#define PCI_PBAC_SIZE           0x0000007c
+#define PCI_PBAC_SB             (1 << 7)
+#define PCI_PBAC_PP             (1 << 8)
+#define PCI_PBAC_MR_BIT         9
+#define PCI_PBAC_MR             0x00000600
+#define  PCI_PBAC_MR_RD         0
+#define  PCI_PBAC_MR_RD_LINE    1
+#define  PCI_PBAC_MR_RD_MULT    2
+#define PCI_PBAC_MRL            (1 << 11)
+#define PCI_PBAC_MRM            (1 << 12)
+#define PCI_PBAC_TRP            (1 << 13)
+
+#define PCI_CFG40_TRDY_TIM      0x000000ff
+#define PCI_CFG40_RET_LIM       0x0000ff00
+
+/*
+ * PCI Local Base Address [0|1|2|3] Register
+ */
+
+#define PCI_LBA_BADDR_BIT       0
+#define PCI_LBA_BADDR           0xffffff00
+
+/*
+ * PCI Local Base Address Control Register
+ */
+
+#define PCI_LBAC_MSI            (1 << 0)
+#define  PCI_LBAC_MSI_MEM       0
+#define  PCI_LBAC_MSI_IO        1
+#define PCI_LBAC_SIZE_BIT       2
+#define PCI_LBAC_SIZE           0x0000007c
+#define PCI_LBAC_SB             (1 << 7)
+#define PCI_LBAC_RT             (1 << 8)
+#define  PCI_LBAC_RT_NO_PREF    0
+#define  PCI_LBAC_RT_PREF       1
+
+/*
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ */
+#define PCI_LBAM_MADDR_BIT      8
+#define PCI_LBAM_MADDR          0xffffff00
+
+/*
+ * PCI Decoupled Access Control Register
+ */
+#define PCI_DAC_DEN             (1 << 0)
+
+/*
+ * PCI Decoupled Access Status Register
+ */
+#define PCI_DAS_D               (1 << 0)
+#define PCI_DAS_B               (1 << 1)
+#define PCI_DAS_E               (1 << 2)
+#define PCI_DAS_OFE             (1 << 3)
+#define PCI_DAS_OFF             (1 << 4)
+#define PCI_DAS_IFE             (1 << 5)
+#define PCI_DAS_IFF             (1 << 6)
+
+/*
+ * PCI DMA Channel 8 Configuration Register
+ */
+#define PCI_DMA8C_MBS_BIT       0
+#define PCI_DMA8C_MBS           0x00000fff /* Maximum Burst Size. */
+#define PCI_DMA8C_OUR           (1 << 12)
+
+/*
+ * PCI DMA Channel 9 Configuration Register
+ */
+#define PCI_DMA9C_MBS_BIT       0       /* Maximum Burst Size. */
+#define PCI_DMA9C_MBS           0x00000fff
+
+/*
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ */
+
+#define PCI_DMAD_PT_BIT         22              /* in DEVCMD field (descriptor) */
+#define PCI_DMAD_PT             0x00c00000      /* preferred transaction field */
+/* These are for reads (DMA channel 8) */
+#define PCI_DMAD_DEVCMD_MR      0               /* memory read */
+#define PCI_DMAD_DEVCMD_MRL     1               /* memory read line */
+#define PCI_DMAD_DEVCMD_MRM     2               /* memory read multiple */
+#define PCI_DMAD_DEVCMD_IOR     3               /* I/O read */
+/* These are for writes (DMA channel 9) */
+#define PCI_DMAD_DEVCMD_MW      0               /* memory write */
+#define PCI_DMAD_DEVCMD_MWI     1               /* memory write invalidate */
+#define PCI_DMAD_DEVCMD_IOW     3               /* I/O write */
+
+/* Swap byte field applies to both DMA channel 8 and 9 */
+#define PCI_DMAD_SB             (1 << 24)       /* swap byte field */
+
+
+/*
+ * PCI Target Control Register
+ */
+
+#define PCI_TC_RTIMER_BIT       0
+#define PCI_TC_RTIMER           0x000000ff
+#define PCI_TC_DTIMER_BIT       8
+#define PCI_TC_DTIMER           0x0000ff00
+#define PCI_TC_RDR              (1 << 18)
+#define PCI_TC_DDT              (1 << 19)
+
+/*
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ */
+#define PCI_MSU_M0              (1 << 0)
+#define PCI_MSU_M1              (1 << 1)
+#define PCI_MSU_DB              (1 << 2)
+
+#define PCI_MSG_ADDR            0xB8088010
+#define PCI0_ADDR               0xB8080000
+#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
+#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
+
+#define PCIM_SHFT               0x6
+#define PCIM_BIT_LEN            0x7
+#define PCIM_H_EA               0x3
+#define PCIM_H_IA_FIX           0x4
+#define PCIM_H_IA_RR            0x5
+#if 0
+#define PCI_ADDR_START          0x13000000
+#endif
+
+#define PCI_ADDR_START          0x50000000
+
+#define CPUTOPCI_MEM_WIN        0x02000000
+#define CPUTOPCI_IO_WIN         0x00100000
+#define PCILBA_SIZE_SHFT        2
+#define PCILBA_SIZE_MASK        0x1F
+#define SIZE_256MB              0x1C
+#define SIZE_128MB              0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB               0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB                0x16
+#define SIZE_2MB                0x15
+#define SIZE_1MB                0x14
+#define KORINA_CONFIG0_ADDR     0x80000000
+#define KORINA_CONFIG1_ADDR     0x80000004
+#define KORINA_CONFIG2_ADDR     0x80000008
+#define KORINA_CONFIG3_ADDR     0x8000000C
+#define KORINA_CONFIG4_ADDR     0x80000010
+#define KORINA_CONFIG5_ADDR     0x80000014
+#define KORINA_CONFIG6_ADDR     0x80000018
+#define KORINA_CONFIG7_ADDR     0x8000001C
+#define KORINA_CONFIG8_ADDR     0x80000020
+#define KORINA_CONFIG9_ADDR     0x80000024
+#define KORINA_CONFIG10_ADDR    0x80000028
+#define KORINA_CONFIG11_ADDR    0x8000002C
+#define KORINA_CONFIG12_ADDR    0x80000030
+#define KORINA_CONFIG13_ADDR    0x80000034
+#define KORINA_CONFIG14_ADDR    0x80000038
+#define KORINA_CONFIG15_ADDR    0x8000003C
+#define KORINA_CONFIG16_ADDR    0x80000040
+#define KORINA_CONFIG17_ADDR    0x80000044
+#define KORINA_CONFIG18_ADDR    0x80000048
+#define KORINA_CONFIG19_ADDR    0x8000004C
+#define KORINA_CONFIG20_ADDR    0x80000050
+#define KORINA_CONFIG21_ADDR    0x80000054
+#define KORINA_CONFIG22_ADDR    0x80000058
+#define KORINA_CONFIG23_ADDR    0x8000005C
+#define KORINA_CONFIG24_ADDR    0x80000060
+#define KORINA_CONFIG25_ADDR    0x80000064
+#define KORINA_CMD              (PCI_CFG04_CMD_IO_ENA | \
+                                 PCI_CFG04_CMD_MEM_ENA | \
+                                 PCI_CFG04_CMD_BM_ENA | \
+                                 PCI_CFG04_CMD_MW_INV | \
+                                 PCI_CFG04_CMD_PAR_ENA | \
+                                 PCI_CFG04_CMD_SER_ENA)
+
+#define KORINA_STAT             (PCI_CFG04_STAT_MDPE | \
+                                 PCI_CFG04_STAT_STA | \
+                                 PCI_CFG04_STAT_RTA | \
+                                 PCI_CFG04_STAT_RMA | \
+                                 PCI_CFG04_STAT_SSE | \
+                                 PCI_CFG04_STAT_PE)
+
+#define KORINA_CNFG1            ((KORINA_STAT<<16)|KORINA_CMD)
+
+#define KORINA_REVID            0
+#define KORINA_CLASS_CODE       0
+#define KORINA_CNFG2            ((KORINA_CLASS_CODE<<8) | \
+                                  KORINA_REVID)
+
+#define KORINA_CACHE_LINE_SIZE  4
+#define KORINA_MASTER_LAT       0x3c
+#define KORINA_HEADER_TYPE      0
+#define KORINA_BIST             0
+
+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
+                      (KORINA_HEADER_TYPE<<16) | \
+                      (KORINA_MASTER_LAT<<8) | \
+                      KORINA_CACHE_LINE_SIZE)
+
+#define KORINA_BAR0     0x00000008      /* 128 MB Memory */
+#define KORINA_BAR1     0x18800001      /* 1 MB IO */
+#define KORINA_BAR2     0x18000001      /* 2 MB IO window for Korina
+                                           internal Registers */
+#define KORINA_BAR3     0x48000008      /* Spare 128 MB Memory */
+
+#define KORINA_CNFG4    KORINA_BAR0
+#define KORINA_CNFG5    KORINA_BAR1
+#define KORINA_CNFG6    KORINA_BAR2
+#define KORINA_CNFG7    KORINA_BAR3
+
+#define KORINA_SUBSYS_VENDOR_ID 0x011d
+#define KORINA_SUBSYSTEM_ID     0x0214
+#define KORINA_CNFG8            0
+#define KORINA_CNFG9            0
+#define KORINA_CNFG10           0
+#define KORINA_CNFG11   ((KORINA_SUBSYS_VENDOR_ID<<16) | \
+                          KORINA_SUBSYSTEM_ID)
+#define KORINA_INT_LINE         1
+#define KORINA_INT_PIN          1
+#define KORINA_MIN_GNT          8
+#define KORINA_MAX_LAT          0x38
+#define KORINA_CNFG12           0
+#define KORINA_CNFG13           0
+#define KORINA_CNFG14           0
+#define KORINA_CNFG15   ((KORINA_MAX_LAT<<24) | \
+                         (KORINA_MIN_GNT<<16) | \
+                         (KORINA_INT_PIN<<8)  | \
+                          KORINA_INT_LINE)
+#define KORINA_RETRY_LIMIT      0x80
+#define KORINA_TRDY_LIMIT       0x80
+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
+                        KORINA_TRDY_LIMIT)
+#define PCI_PBAxC_R             0x0
+#define PCI_PBAxC_RL            0x1
+#define PCI_PBAxC_RM            0x2
+#define SIZE_SHFT               2
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA0C    (PCI_PBAC_MRL | PCI_PBAC_SB | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#else
+#define KORINA_PBA0C    (PCI_PBAC_MRL | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#endif
+#define KORINA_CNFG17   KORINA_PBA0C
+#define KORINA_PBA0M    0x0
+#define KORINA_CNFG18   KORINA_PBA0M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG19   KORINA_PBA1C
+#define KORINA_PBA1M    0x0
+#define KORINA_CNFG20   KORINA_PBA1M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG21   KORINA_PBA2C
+#define KORINA_PBA2M    0x18000000
+#define KORINA_CNFG22   KORINA_PBA2M
+#define KORINA_PBA3C    0
+#define KORINA_CNFG23   KORINA_PBA3C
+#define KORINA_PBA3M    0
+#define KORINA_CNFG24   KORINA_PBA3M
+
+#define PCITC_DTIMER_VAL        8
+#define PCITC_RTIMER_VAL        0x10
+
+#endif  /* __ASM_RC32434_PCI_H */
diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
new file mode 100644
index 000000000000..1d66ddcda89a
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/prom.h
@@ -0,0 +1,44 @@
+/*
+ *  Definitions for the PROM
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#define PROM_ENTRY(x)           (0xbfc00000 + ((x) * 8))
+
+#define GPIO_INIT_NOBUTTON      ""
+#define GPIO_INIT_BUTTON        " 2"
+
+#define SR_NMI                  0x00180000
+#define SERIAL_SPEED_ENTRY      0x00000001
+
+#define FREQ_TAG                "HZ="
+#define GPIO_TAG                "gpio="
+#define KMAC_TAG                "kmac="
+#define MEM_TAG                 "mem="
+#define BOARD_TAG               "board="
+
+#define BOARD_RB532             "500"
+#define BOARD_RB532A            "500r5"
diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
new file mode 100644
index 000000000000..e0a76e3ffea8
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rb.h
@@ -0,0 +1,81 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *  GNU General Public License for more details.
+ *
+ *  Copyright (C) 2004 IDT Inc.
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ */
+#ifndef __ASM_RC32434_RB_H
+#define __ASM_RC32434_RB_H
+
+#include <linux/genhd.h>
+
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
+#define DEV0BASE        0x010000
+#define DEV0MASK        0x010004
+#define DEV0C           0x010008
+#define DEV0T           0x01000C
+#define DEV1BASE        0x010010
+#define DEV1MASK        0x010014
+#define DEV1C           0x010018
+#define DEV1TC          0x01001C
+#define DEV2BASE        0x010020
+#define DEV2MASK        0x010024
+#define DEV2C           0x010028
+#define DEV2TC          0x01002C
+#define DEV3BASE        0x010030
+#define DEV3MASK        0x010034
+#define DEV3C           0x010038
+#define DEV3TC          0x01003C
+#define BTCS            0x010040
+#define BTCOMPARE       0x010044
+#define GPIOBASE        0x050000
+#define GPIOCFG         0x050004
+#define GPIOD           0x050008
+#define GPIOILEVEL      0x05000C
+#define GPIOISTAT       0x050010
+#define GPIONMIEN       0x050014
+#define IMASK6          0x038038
+#define LO_WPX          (1 << 0)
+#define LO_ALE          (1 << 1)
+#define LO_CLE          (1 << 2)
+#define LO_CEX          (1 << 3)
+#define LO_FOFF         (1 << 5)
+#define LO_SPICS        (1 << 6)
+#define LO_ULED         (1 << 7)
+
+#define BIT_TO_MASK(x)  (1 << x)
+
+struct dev_reg {
+        u32     base;
+        u32     mask;
+        u32     ctl;
+        u32     timing;
+};
+
+struct korina_device {
+        char *name;
+        unsigned char mac[6];
+        struct net_device *dev;
+};
+
+struct cf_device {
+        int gpio_pin;
+        void *dev;
+        struct gendisk *gd;
+};
+
+struct mpmc_device {
+        unsigned char   state;
+        spinlock_t      lock;
+        void __iomem    *base;
+};
+
+#endif  /* __ASM_RC32434_RB_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..c4a02145104e
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/rc32434.h
@@ -0,0 +1,61 @@
+/*
+ * Definitions for IDT RC323434 CPU.
+ */
+
+#ifndef _ASM_RC32434_RC32434_H_
+#define _ASM_RC32434_RC32434_H_
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#define RC32434_REG_BASE        0x18000000
+#define RC32434_RST             (1 << 15)
+
+#define IDT_CLOCK_MULT          2
+#define MIPS_CPU_TIMER_IRQ      7
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND          (RC32434_REG_BASE + 0x38000)
+#define IC_GROUP0_MASK          (RC32434_REG_BASE + 0x38008)
+#define IC_GROUP_OFFSET         0x0C
+
+#define NUM_INTR_GROUPS         5
+
+/* 16550 UARTs */
+#define GROUP0_IRQ_BASE         8       /* GRP2 IRQ numbers start here */
+                                        /* GRP3 IRQ numbers start here */
+#define GROUP1_IRQ_BASE         (GROUP0_IRQ_BASE + 32)
+                                        /* GRP4 IRQ numbers start here */
+#define GROUP2_IRQ_BASE         (GROUP1_IRQ_BASE + 32)
+                                        /* GRP5 IRQ numbers start here */
+#define GROUP3_IRQ_BASE         (GROUP2_IRQ_BASE + 32)
+#define GROUP4_IRQ_BASE         (GROUP3_IRQ_BASE + 32)
+
+
+#ifdef __MIPSEB__
+#define RC32434_UART0_BASE      (RC32434_REG_BASE + 0x58003)
+#else
+#define RC32434_UART0_BASE      (RC32434_REG_BASE + 0x58000)
+#endif
+
+#define RC32434_UART0_IRQ       (GROUP3_IRQ_BASE + 0)
+
+/* cpu pipeline flush */
+static inline void rc32434_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+static inline void rc32434_sync_udelay(int us)
+{
+        __asm__ volatile ("sync");
+        udelay(us);
+}
+
+static inline void rc32434_sync_delay(int ms)
+{
+        __asm__ volatile ("sync");
+        mdelay(ms);
+}
+
+#endif  /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h
new file mode 100644
index 000000000000..e49b1d57a017
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
+/*
+ *  Definitions for timer registers
+ *
+ *  Copyright 2004 Philip Rischel <rischelp@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_TIMER_H
+#define __ASM_RC32434_TIMER_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define TIMER0_BASE_ADDR                0x18028000
+#define TIMER_COUNT                     3
+
+struct timer_counter {
+        u32 count;
+        u32 compare;
+        u32 ctc;                /*use CTC_ */
+};
+
+struct timer {
+        struct timer_counter tim[TIMER_COUNT];
+        u32 rcount;     /* use RCOUNT_ */
+        u32 rcompare;   /* use RCOMPARE_ */
+        u32 rtc;        /* use RTC_ */
+};
+
+#define RC32434_CTC_EN_BIT              0
+#define RC32434_CTC_TO_BIT              1
+
+/* Real time clock registers */
+#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
+#define RC32434_RTC_CE_BIT              0
+#define RC32434_RTC_TO_BIT              1
+#define RC32434_RTC_RQE_BIT             2
+
+/* Counter registers */
+#define RC32434_RCOUNT_BIT              0
+#define RC32434_RCOUNT_MSK              0x0000ffff
+#define RC32434_RCOMP_BIT               0
+#define RC32434_RCOMP_MSK               0x0000ffff
+
+#endif  /* __ASM_RC32434_TIMER_H */
diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h
new file mode 100644
index 000000000000..3ddf187e98a6
--- /dev/null
+++ b/include/asm-mips/mach-rc32434/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        1
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h
index 29989ff10d66..93c6c04ffda3 100644
--- a/include/asm-mips/mach-jmr3927/ioremap.h
+++ b/include/asm-mips/mach-tx39xx/ioremap.h
@@ -1,13 +1,13 @@
 /*
- *      include/asm-mips/mach-jmr3927/ioremap.h
+ *      include/asm-mips/mach-tx39xx/ioremap.h
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
  *      as published by the Free Software Foundation; either version
  *      2 of the License, or (at your option) any later version.
  */
-#ifndef __ASM_MACH_JMR3927_IOREMAP_H
-#define __ASM_MACH_JMR3927_IOREMAP_H
+#ifndef __ASM_MACH_TX39XX_IOREMAP_H
+#define __ASM_MACH_TX39XX_IOREMAP_H
 
 #include <linux/types.h>
 
@@ -35,4 +35,4 @@ static inline int plat_iounmap(const volatile void __iomem *addr)
         return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
 }
 
-#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
+#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h
index 11bffcd1043b..ef0b502fd8b7 100644
--- a/include/asm-mips/mach-jmr3927/mangle-port.h
+++ b/include/asm-mips/mach-tx39xx/mangle-port.h
@@ -1,7 +1,12 @@
-#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H
-#define __ASM_MACH_JMR3927_MANGLE_PORT_H
+#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
+#define __ASM_MACH_TX39XX_MANGLE_PORT_H
 
-extern unsigned long __swizzle_addr_b(unsigned long port);
+#if defined(CONFIG_TOSHIBA_JMR3927)
+extern unsigned long (*__swizzle_addr_b)(unsigned long port);
+#define NEEDS_TXX9_SWIZZLE_ADDR_B
+#else
+#define __swizzle_addr_b(port)  (port)
+#endif
 #define __swizzle_addr_w(port)  (port)
 #define __swizzle_addr_l(port)  (port)
 #define __swizzle_addr_q(port)  (port)
@@ -15,4 +20,4 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
 #define ioswabq(a, x)           le64_to_cpu(x)
 #define __mem_ioswabq(a, x)     (x)
 
-#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
+#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-tx39xx/war.h
index 1ff55fb3fbcb..433814616359 100644
--- a/include/asm-mips/mach-jmr3927/war.h
+++ b/include/asm-mips/mach-tx39xx/war.h
@@ -5,8 +5,8 @@
  *
  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
  */
-#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H
-#define __ASM_MIPS_MACH_JMR3927_WAR_H
+#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
+#define __ASM_MIPS_MACH_TX39XX_WAR_H
 
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #define R4600_V1_HIT_CACHEOP_WAR        0
@@ -22,4 +22,4 @@
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
 
-#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */
+#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h
index 848812296052..862058d3f81b 100644
--- a/include/asm-mips/mach-vr41xx/irq.h
+++ b/include/asm-mips/mach-vr41xx/irq.h
@@ -2,9 +2,6 @@
 #define __ASM_MACH_VR41XX_IRQ_H
 
 #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
-#ifdef CONFIG_NEC_CMBVR4133
-#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
-#endif
 
 #include_next <irq.h>
 
diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h
deleted file mode 100644
index a8ae12d120ee..000000000000
--- a/include/asm-mips/mips-boards/atlas.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines of the Atlas board specific address-MAP, registers, etc.
- *
- */
-#ifndef _MIPS_ATLAS_H
-#define _MIPS_ATLAS_H
-
-#include <asm/addrspace.h>
-
-/*
- * Atlas RTC-device indirect register access.
- */
-#define ATLAS_RTC_ADR_REG       0x1f000800
-#define ATLAS_RTC_DAT_REG       0x1f000808
-
-/*
- * Atlas interrupt controller register base.
- */
-#define ATLAS_ICTRL_REGS_BASE   0x1f000000
-
-/*
- * Atlas registers are memory mapped on 64-bit aligned boundaries and
- * only word access are allowed.
- */
-struct atlas_ictrl_regs {
-        volatile unsigned int intraw;
-        int dummy1;
-        volatile unsigned int intseten;
-        int dummy2;
-        volatile unsigned int intrsten;
-        int dummy3;
-        volatile unsigned int intenable;
-        int dummy4;
-        volatile unsigned int intstatus;
-        int dummy5;
-};
-
-/*
- * Atlas UART register base.
- */
-#define ATLAS_UART_REGS_BASE    0x1f000900
-#define ATLAS_BASE_BAUD ( 3686400 / 16 )
-
-/*
- * Atlas PSU standby register.
- */
-#define ATLAS_PSUSTBY_REG       0x1f000600
-#define ATLAS_GOSTBY            0x4d
-
-/*
- * We make a universal assumption about the way the bootloader (YAMON)
- * have located the Philips SAA9730 chip.
- * This is not ideal, but is needed for setting up remote debugging as
- * soon as possible.
- */
-#define ATLAS_SAA9730_REG       0x10800000
-
-#define ATLAS_SAA9730_BAUDCLOCK 3692300
-
-#endif /* !(_MIPS_ATLAS_H) */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
deleted file mode 100644
index 93ba1c1b2a4f..000000000000
--- a/include/asm-mips/mips-boards/atlasint.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (C) 1999, 2006  MIPS Technologies, Inc.  All rights reserved.
- *      Authors: Carsten Langgaard <carstenl@mips.com>
- *               Maciej W. Rozycki <macro@mips.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines for the Atlas interrupt controller.
- *
- */
-#ifndef _MIPS_ATLASINT_H
-#define _MIPS_ATLASINT_H
-
-#include <irq.h>
-
-/* CPU interrupt offsets */
-#define MIPSCPU_INT_SW0         0
-#define MIPSCPU_INT_SW1         1
-#define MIPSCPU_INT_MB0         2
-#define MIPSCPU_INT_ATLAS       MIPSCPU_INT_MB0
-#define MIPSCPU_INT_MB1         3
-#define MIPSCPU_INT_MB2         4
-#define MIPSCPU_INT_MB3         5
-#define MIPSCPU_INT_MB4         6
-
-/*
- * Interrupts 8..39 are used for Atlas interrupt controller interrupts
- */
-#define ATLAS_INT_BASE          8
-#define ATLAS_INT_UART          (ATLAS_INT_BASE + 0)
-#define ATLAS_INT_TIM0          (ATLAS_INT_BASE + 1)
-#define ATLAS_INT_RES2          (ATLAS_INT_BASE + 2)
-#define ATLAS_INT_RES3          (ATLAS_INT_BASE + 3)
-#define ATLAS_INT_RTC           (ATLAS_INT_BASE + 4)
-#define ATLAS_INT_COREHI        (ATLAS_INT_BASE + 5)
-#define ATLAS_INT_CORELO        (ATLAS_INT_BASE + 6)
-#define ATLAS_INT_RES7          (ATLAS_INT_BASE + 7)
-#define ATLAS_INT_PCIA          (ATLAS_INT_BASE + 8)
-#define ATLAS_INT_PCIB          (ATLAS_INT_BASE + 9)
-#define ATLAS_INT_PCIC          (ATLAS_INT_BASE + 10)
-#define ATLAS_INT_PCID          (ATLAS_INT_BASE + 11)
-#define ATLAS_INT_ENUM          (ATLAS_INT_BASE + 12)
-#define ATLAS_INT_DEG           (ATLAS_INT_BASE + 13)
-#define ATLAS_INT_ATXFAIL       (ATLAS_INT_BASE + 14)
-#define ATLAS_INT_INTA          (ATLAS_INT_BASE + 15)
-#define ATLAS_INT_INTB          (ATLAS_INT_BASE + 16)
-#define ATLAS_INT_ETH           ATLAS_INT_INTB
-#define ATLAS_INT_INTC          (ATLAS_INT_BASE + 17)
-#define ATLAS_INT_SCSI          ATLAS_INT_INTC
-#define ATLAS_INT_INTD          (ATLAS_INT_BASE + 18)
-#define ATLAS_INT_SERR          (ATLAS_INT_BASE + 19)
-#define ATLAS_INT_RES20         (ATLAS_INT_BASE + 20)
-#define ATLAS_INT_RES21         (ATLAS_INT_BASE + 21)
-#define ATLAS_INT_RES22         (ATLAS_INT_BASE + 22)
-#define ATLAS_INT_RES23         (ATLAS_INT_BASE + 23)
-#define ATLAS_INT_RES24         (ATLAS_INT_BASE + 24)
-#define ATLAS_INT_RES25         (ATLAS_INT_BASE + 25)
-#define ATLAS_INT_RES26         (ATLAS_INT_BASE + 26)
-#define ATLAS_INT_RES27         (ATLAS_INT_BASE + 27)
-#define ATLAS_INT_RES28         (ATLAS_INT_BASE + 28)
-#define ATLAS_INT_RES29         (ATLAS_INT_BASE + 29)
-#define ATLAS_INT_RES30         (ATLAS_INT_BASE + 30)
-#define ATLAS_INT_RES31         (ATLAS_INT_BASE + 31)
-#define ATLAS_INT_END           (ATLAS_INT_BASE + 31)
-
-/*
- * Interrupts 64..127 are used for Soc-it Classic interrupts
- */
-#define MSC01C_INT_BASE         64
-
-/* SOC-it Classic interrupt offsets */
-#define MSC01C_INT_TMR          0
-#define MSC01C_INT_PCI          1
-
-/*
- * Interrupts 64..127 are used for Soc-it EIC interrupts
- */
-#define MSC01E_INT_BASE         64
-
-/* SOC-it EIC interrupt offsets */
-#define MSC01E_INT_SW0          1
-#define MSC01E_INT_SW1          2
-#define MSC01E_INT_MB0          3
-#define MSC01E_INT_ATLAS        MSC01E_INT_MB0
-#define MSC01E_INT_MB1          4
-#define MSC01E_INT_MB2          5
-#define MSC01E_INT_MB3          6
-#define MSC01E_INT_MB4          7
-#define MSC01E_INT_TMR          8
-#define MSC01E_INT_PCI          9
-#define MSC01E_INT_PERFCTR      10
-#define MSC01E_INT_CPUCTR       11
-
-#endif /* !(_MIPS_ATLASINT_H) */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 33407bee4e73..7f0b034dd9a5 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -27,12 +27,8 @@
 /*
  * Display register base.
  */
-#ifdef CONFIG_MIPS_SEAD
-#define ASCII_DISPLAY_POS_BASE     0x1f0005c0
-#else
 #define ASCII_DISPLAY_WORD_BASE    0x1f000410
 #define ASCII_DISPLAY_POS_BASE     0x1f000418
-#endif
 
 
 /*
@@ -44,13 +40,8 @@
 /*
  * Reset register.
  */
-#ifdef CONFIG_MIPS_SEAD
-#define SOFTRES_REG       0x1e800050
-#define GORESET           0x4d
-#else
 #define SOFTRES_REG       0x1f000500
 #define GORESET           0x42
-#endif
 
 /*
  * Revision register.
diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h
deleted file mode 100644
index 8d7e955d506e..000000000000
--- a/include/asm-mips/mips-boards/maltasmp.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * There are several SMP models supported
- * SMTC is mutually exclusive to other options (atm)
- */
-#if defined(CONFIG_MIPS_MT_SMTC)
-#define malta_smtc      1
-#define malta_cmp       0
-#define malta_smvp      0
-#else
-#define malta_smtc      0
-#if defined(CONFIG_MIPS_CMP)
-extern int gcmp_present;
-#define malta_cmp       gcmp_present
-#else
-#define malta_cmp       0
-#endif
-/* FIXME: should become COMFIG_MIPS_MT_SMVP */
-#if defined(CONFIG_MIPS_MT_SMP)
-#define malta_smvp      1
-#else
-#define malta_smvp      0
-#endif
-#endif
-
-#include <asm/mipsregs.h>
-#include <asm/mipsmtregs.h>
-
-/* malta_smtc */
-#include <asm/smtc.h>
-#include <asm/smtc_ipi.h>
-
-/* malta_cmp */
-#include <asm/cmp.h>
-
-/* malta_smvp */
-#include <asm/smvp.h>
diff --git a/include/asm-mips/mips-boards/saa9730_uart.h b/include/asm-mips/mips-boards/saa9730_uart.h
deleted file mode 100644
index c913143d58ec..000000000000
--- a/include/asm-mips/mips-boards/saa9730_uart.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Register definitions for the UART part of the Philips SAA9730 chip.
- *
- */
-
-#ifndef SAA9730_UART_H
-#define SAA9730_UART_H
-
-/* The SAA9730 UART register map, as seen via the PCI bus */
-
-#define SAA9730_UART_REGS_ADDR  0x21800
-
-struct uart_saa9730_regmap {
-        volatile unsigned char Thr_Rbr;
-        volatile unsigned char Ier;
-        volatile unsigned char Iir_Fcr;
-        volatile unsigned char Lcr;
-        volatile unsigned char Mcr;
-        volatile unsigned char Lsr;
-        volatile unsigned char Msr;
-        volatile unsigned char Scr;
-        volatile unsigned char BaudDivLsb;
-        volatile unsigned char BaudDivMsb;
-        volatile unsigned char Junk0;
-        volatile unsigned char Junk1;
-        volatile unsigned int Config;           /* 0x2180c */
-        volatile unsigned int TxStart;          /* 0x21810 */
-        volatile unsigned int TxLength;         /* 0x21814 */
-        volatile unsigned int TxCounter;        /* 0x21818 */
-        volatile unsigned int RxStart;          /* 0x2181c */
-        volatile unsigned int RxLength;         /* 0x21820 */
-        volatile unsigned int RxCounter;        /* 0x21824 */
-};
-typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
-
-/*
- * Only a subset of the UART control bits are defined here,
- * enough to make the serial debug port work.
- */
-
-#define SAA9730_LCR_DATA8       0x03
-
-#define SAA9730_MCR_DTR         0x01
-#define SAA9730_MCR_RTS         0x02
-
-#define SAA9730_LSR_DR          0x01
-#define SAA9730_LSR_THRE        0x20
-
-#endif /* !(SAA9730_UART_H) */
diff --git a/include/asm-mips/mips-boards/sead.h b/include/asm-mips/mips-boards/sead.h
deleted file mode 100644
index 68c69de0b66f..000000000000
--- a/include/asm-mips/mips-boards/sead.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines of the SEAD board specific address-MAP, registers, etc.
- *
- */
-#ifndef _MIPS_SEAD_H
-#define _MIPS_SEAD_H
-
-#include <asm/addrspace.h>
-
-/*
- * SEAD UART register base.
- */
-#define SEAD_UART0_REGS_BASE    (0x1f000800)
-#define SEAD_BASE_BAUD ( 3686400 / 16 )
-
-#endif /* !(_MIPS_SEAD_H) */
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
deleted file mode 100644
index e710bae07340..000000000000
--- a/include/asm-mips/mips-boards/seadint.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Defines for the SEAD interrupt controller.
- */
-#ifndef _MIPS_SEADINT_H
-#define _MIPS_SEADINT_H
-
-#include <irq.h>
-
-#define MIPSCPU_INT_UART0       2
-#define MIPSCPU_INT_UART1       3
-
-#endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h
deleted file mode 100644
index c94d12d1f868..000000000000
--- a/include/asm-mips/namei.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef _ASM_NAMEI_H
-#define _ASM_NAMEI_H
-
-#include <linux/personality.h>
-#include <linux/stddef.h>
-
-#define IRIX_EMUL       "/usr/gnemul/irix/"
-#define RISCOS_EMUL     "/usr/gnemul/riscos/"
-
-static inline char *__emul_prefix(void)
-{
-        switch (current->personality) {
-        case PER_IRIX32:
-        case PER_IRIXN32:
-        case PER_IRIX64:
-                return IRIX_EMUL;
-
-        case PER_RISCOS:
-                return RISCOS_EMUL;
-
-        default:
-                return NULL;
-        }
-}
-
-#endif /* _ASM_NAMEI_H */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 8735aa0b8963..fe7a88ea066e 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,6 +34,9 @@
 #include <linux/pfn.h>
 #include <asm/io.h>
 
+extern void build_clear_page(void);
+extern void build_copy_page(void);
+
 /*
  * It's normally defined only for FLATMEM config but it's
  * used in our early mem init code for all memory models.
@@ -134,9 +137,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 #endif /* !__ASSEMBLY__ */
 
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)        (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
-
 /*
  * __pa()/__va() should be used only during mem init.
  */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 301ff2f28012..c205875d7f31 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -172,4 +172,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+extern int pci_probe_only;
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 60e2f9338fcd..51b34a48c84a 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -134,6 +134,4 @@
 
 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
 
-#define CONF_CM_DEFAULT         (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
-
 #endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
deleted file mode 100644
index 8121a9a75bfd..000000000000
--- a/include/asm-mips/prctl.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * IRIX prctl interface
- *
- * The IRIX kernel maps a page at PRDA_ADDRESS with the
- * contents of prda and fills it the bits on prda_sys.
- */
-
-#ifndef __PRCTL_H__
-#define __PRCTL_H__
-
-#define PRDA_ADDRESS 0x200000L
-#define PRDA ((struct prda *) PRDA_ADDRESS)
-
-struct prda_sys {
-        pid_t t_pid;
-        u32   t_hint;
-        u32   t_dlactseq;
-        u32   t_fpflags;
-        u32   t_prid;           /* processor type, $prid CP0 register */
-        u32   t_dlendseq;
-        u64   t_unused1[5];
-        pid_t t_rpid;
-        s32   t_resched;
-        u32   t_unused[8];
-        u32   t_cpu;            /* current/last cpu */
-
-        /* FIXME: The signal information, not supported by Linux now */
-        u32   t_flags;          /* if true, then the sigprocmask is in userspace */
-        u32   t_sigprocmask [1]; /* the sigprocmask */
-};
-
-struct prda {
-        char fill [0xe00];
-        struct prda_sys prda_sys;
-};
-
-#define t_sys           prda_sys
-
-ptrdiff_t prctl(int op, int v1, int v2);
-
-#endif
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 58cbac5a64e4..a1e4453469f9 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -45,7 +45,7 @@ extern unsigned int vced_count, vcei_count;
  * This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
  */
-#define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
+#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
 #endif
 
 #ifdef CONFIG_64BIT
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
deleted file mode 100644
index d9b2034ed1d2..000000000000
--- a/include/asm-mips/semaphore.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/semaphore.h>
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
index 70009a902639..e600cedda976 100644
--- a/include/asm-mips/setup.h
+++ b/include/asm-mips/setup.h
@@ -3,4 +3,8 @@
 
 #define COMMAND_LINE_SIZE       256
 
+#ifdef  __KERNEL__
+extern void setup_early_printk(void);
+#endif /* __KERNEL__ */
+
 #endif /* __SETUP_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 7a28989f7ee3..bee5153aca48 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -119,9 +119,6 @@ struct sigaction {
 
 struct k_sigaction {
         struct sigaction sa;
-#ifdef CONFIG_BINFMT_IRIX
-        void            (*sa_restorer)(void);
-#endif
 };
 
 /* IRIX compatible stack_t  */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 84fef1aeec0c..0ff5b523ea77 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -35,16 +35,6 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define NO_PROC_ID      (-1)
 
-struct call_data_struct {
-        void            (*func)(void *);
-        void            *info;
-        atomic_t        started;
-        atomic_t        finished;
-        int             wait;
-};
-
-extern struct call_data_struct *call_data;
-
 #define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
 #define SMP_CALL_FUNCTION       0x2
 
@@ -67,4 +57,7 @@ static inline void smp_send_reschedule(int cpu)
 
 extern asmlinkage void smp_call_function_interrupt(void);
 
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
 #endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 63f60254d308..facc2d7a87ca 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -102,6 +102,13 @@ enum sock_type {
 };
 
 #define SOCK_MAX (SOCK_PACKET + 1)
+/* Mask which covers at least up to SOCK_MASK-1.  The
+ *  * remaining bits are used as flags. */
+#define SOCK_TYPE_MASK 0xf
+
+/* Flags for socket, socketpair, paccept */
+#define SOCK_CLOEXEC    O_CLOEXEC
+#define SOCK_NONBLOCK   O_NONBLOCK
 
 #define ARCH_HAS_SOCKET_TYPES 1
 
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index b2772df1a1bd..bb3060699df2 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -82,6 +82,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define THREAD_MASK (THREAD_SIZE - 1UL)
 
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
 #ifdef CONFIG_DEBUG_STACK_USAGE
 #define alloc_thread_info(tsk)                                  \
 ({                                                              \
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index e5dbde625ec2..90ff2f497c50 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
-extern void (*board_watchpoint_handler)(struct pt_regs *regs);
 
 #endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
deleted file mode 100644
index b188a659ce02..000000000000
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2001-2002 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
-#define __ASM_TX4927_TOSHIBA_RBTX4927_H
-
-#include <asm/tx4927/tx4927.h>
-#ifdef CONFIG_PCI
-#include <asm/tx4927/tx4927_pci.h>
-#endif
-
-#ifdef CONFIG_PCI
-#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
-#else
-#define TBTX4927_ISA_IO_OFFSET 0
-#endif
-
-#define RBTX4927_SW_RESET_DO         (void __iomem *)0xbc00f000UL
-#define RBTX4927_SW_RESET_DO_SET                0x01
-
-#define RBTX4927_SW_RESET_ENABLE     (void __iomem *)0xbc00f002UL
-#define RBTX4927_SW_RESET_ENABLE_SET            0x01
-
-
-#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
-
-int toshiba_rbtx4927_irq_nested(int sw_irq);
-
-#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
deleted file mode 100644
index 193e80a17c12..000000000000
--- a/include/asm-mips/tx4927/tx4927.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2001-2006 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TX4927_TX4927_H
-#define __ASM_TX4927_TX4927_H
-
-#include <asm/txx9irq.h>
-
-#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
-#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
-
-#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
-#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
-
-
-#define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
-#define TX4927_IRQ_USER1            (TX4927_IRQ_CP0_BEG+1)
-#define TX4927_IRQ_NEST_PIC_ON_CP0  (TX4927_IRQ_CP0_BEG+2)
-#define TX4927_IRQ_CPU_TIMER        (TX4927_IRQ_CP0_BEG+7)
-
-#define TX4927_IRQ_NEST_EXT_ON_PIC  (TX4927_IRQ_PIC_BEG+3)
-
-#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
deleted file mode 100644
index 0be77df70f2b..000000000000
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- */
-#ifndef __ASM_TX4927_TX4927_PCI_H
-#define __ASM_TX4927_TX4927_PCI_H
-
-#define TX4927_CCFG_TOE 0x00004000
-#define TX4927_CCFG_WR  0x00008000
-#define TX4927_CCFG_TINTDIS     0x01000000
-
-#define TX4927_PCIMEM      0x08000000
-#define TX4927_PCIMEM_SIZE 0x08000000
-#define TX4927_PCIIO       0x16000000
-#define TX4927_PCIIO_SIZE  0x01000000
-
-#define TX4927_SDRAMC_REG       0xff1f8000
-#define TX4927_EBUSC_REG        0xff1f9000
-#define TX4927_PCIC_REG         0xff1fd000
-#define TX4927_CCFG_REG         0xff1fe000
-#define TX4927_IRC_REG          0xff1ff600
-#define TX4927_NR_TMR   3
-#define TX4927_TMR_REG(ch)      (0xff1ff000 + (ch) * 0x100)
-#define TX4927_CE3      0x17f00000      /* 1M */
-#define TX4927_PCIRESET_ADDR    0xbc00f006
-#define TX4927_PCI_CLK_ADDR     (KSEG1 + TX4927_CE3 + 0x00040020)
-
-#define TX4927_IMSTAT_ADDR(n)   (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
-#define tx4927_imstat_ptr(n)    \
-        ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
-
-/* bits for ISTAT3/IMASK3/IMSTAT3 */
-#define TX4927_INT3B_PCID       0
-#define TX4927_INT3B_PCIC       1
-#define TX4927_INT3B_PCIB       2
-#define TX4927_INT3B_PCIA       3
-#define TX4927_INT3F_PCID       (1 << TX4927_INT3B_PCID)
-#define TX4927_INT3F_PCIC       (1 << TX4927_INT3B_PCIC)
-#define TX4927_INT3F_PCIB       (1 << TX4927_INT3B_PCIB)
-#define TX4927_INT3F_PCIA       (1 << TX4927_INT3B_PCIA)
-
-/* bits for PCI_CLK (S6) */
-#define TX4927_PCI_CLK_HOST     0x80
-#define TX4927_PCI_CLK_MASK     (0x0f << 3)
-#define TX4927_PCI_CLK_33       (0x01 << 3)
-#define TX4927_PCI_CLK_25       (0x04 << 3)
-#define TX4927_PCI_CLK_66       (0x09 << 3)
-#define TX4927_PCI_CLK_50       (0x0c << 3)
-#define TX4927_PCI_CLK_ACK      0x04
-#define TX4927_PCI_CLK_ACE      0x02
-#define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
-#define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
-
-#define TX4927_IR_PCIC          16
-#define TX4927_IR_PCIERR        22
-#define TX4927_IR_PCIPMA        23
-#define TX4927_IRQ_IRC_PCIC     (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
-#define TX4927_IRQ_IRC_PCIERR   (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
-#define TX4927_IRQ_IOC1         (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
-#define TX4927_IRQ_IOC_PCID     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
-#define TX4927_IRQ_IOC_PCIC     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
-#define TX4927_IRQ_IOC_PCIB     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
-#define TX4927_IRQ_IOC_PCIA     (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
-
-#ifdef _LANGUAGE_ASSEMBLY
-#define _CONST64(c)     c
-#else
-#define _CONST64(c)     c##ull
-
-#include <asm/byteorder.h>
-
-#define tx4927_pcireset_ptr     \
-        ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
-#define tx4927_pci_clk_ptr      \
-        ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
-
-struct tx4927_sdramc_reg {
-        volatile unsigned long long cr[4];
-        volatile unsigned long long unused0[4];
-        volatile unsigned long long tr;
-        volatile unsigned long long unused1[2];
-        volatile unsigned long long cmd;
-};
-
-struct tx4927_ebusc_reg {
-        volatile unsigned long long cr[8];
-};
-
-struct tx4927_ccfg_reg {
-        volatile unsigned long long ccfg;
-        volatile unsigned long long crir;
-        volatile unsigned long long pcfg;
-        volatile unsigned long long tear;
-        volatile unsigned long long clkctr;
-        volatile unsigned long long unused0;
-        volatile unsigned long long garbc;
-        volatile unsigned long long unused1;
-        volatile unsigned long long unused2;
-        volatile unsigned long long ramp;
-};
-
-struct tx4927_pcic_reg {
-        volatile unsigned long pciid;
-        volatile unsigned long pcistatus;
-        volatile unsigned long pciccrev;
-        volatile unsigned long pcicfg1;
-        volatile unsigned long p2gm0plbase;             /* +10 */
-        volatile unsigned long p2gm0pubase;
-        volatile unsigned long p2gm1plbase;
-        volatile unsigned long p2gm1pubase;
-        volatile unsigned long p2gm2pbase;              /* +20 */
-        volatile unsigned long p2giopbase;
-        volatile unsigned long unused0;
-        volatile unsigned long pcisid;
-        volatile unsigned long unused1;         /* +30 */
-        volatile unsigned long pcicapptr;
-        volatile unsigned long unused2;
-        volatile unsigned long pcicfg2;
-        volatile unsigned long g2ptocnt;                /* +40 */
-        volatile unsigned long unused3[15];
-        volatile unsigned long g2pstatus;               /* +80 */
-        volatile unsigned long g2pmask;
-        volatile unsigned long pcisstatus;
-        volatile unsigned long pcimask;
-        volatile unsigned long p2gcfg;          /* +90 */
-        volatile unsigned long p2gstatus;
-        volatile unsigned long p2gmask;
-        volatile unsigned long p2gccmd;
-        volatile unsigned long unused4[24];             /* +a0 */
-        volatile unsigned long pbareqport;              /* +100 */
-        volatile unsigned long pbacfg;
-        volatile unsigned long pbastatus;
-        volatile unsigned long pbamask;
-        volatile unsigned long pbabm;           /* +110 */
-        volatile unsigned long pbacreq;
-        volatile unsigned long pbacgnt;
-        volatile unsigned long pbacstate;
-        volatile unsigned long long g2pmgbase[3];               /* +120 */
-        volatile unsigned long long g2piogbase;
-        volatile unsigned long g2pmmask[3];             /* +140 */
-        volatile unsigned long g2piomask;
-        volatile unsigned long long g2pmpbase[3];               /* +150 */
-        volatile unsigned long long g2piopbase;
-        volatile unsigned long pciccfg;         /* +170 */
-        volatile unsigned long pcicstatus;
-        volatile unsigned long pcicmask;
-        volatile unsigned long unused5;
-        volatile unsigned long long p2gmgbase[3];               /* +180 */
-        volatile unsigned long long p2giogbase;
-        volatile unsigned long g2pcfgadrs;              /* +1a0 */
-        volatile unsigned long g2pcfgdata;
-        volatile unsigned long unused6[8];
-        volatile unsigned long g2pintack;
-        volatile unsigned long g2pspc;
-        volatile unsigned long unused7[12];             /* +1d0 */
-        volatile unsigned long long pdmca;              /* +200 */
-        volatile unsigned long long pdmga;
-        volatile unsigned long long pdmpa;
-        volatile unsigned long long pdmcut;
-        volatile unsigned long long pdmcnt;             /* +220 */
-        volatile unsigned long long pdmsts;
-        volatile unsigned long long unused8[2];
-        volatile unsigned long long pdmdb[4];           /* +240 */
-        volatile unsigned long long pdmtdh;             /* +260 */
-        volatile unsigned long long pdmdms;
-};
-
-#endif /* _LANGUAGE_ASSEMBLY */
-
-/*
- * PCIC
- */
-
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
-#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
-#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
-
-/* bits for PBACFG */
-#define TX4927_PCIC_PBACFG_RPBA 0x00000004
-#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
-#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4927_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4927_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for G2PIOGBASE */
-#define TX4927_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4927_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4927_PCIC_PCICSTATUS_ALL      0x000007dc
-
-/* bits for PCICCFG */
-#define TX4927_PCIC_PCICCFG_LBWC_MASK   0x0fff0000
-#define TX4927_PCIC_PCICCFG_HRST        0x00000800
-#define TX4927_PCIC_PCICCFG_SRST        0x00000400
-#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
-#define TX4927_PCIC_PCICCFG_IMSE0       0x00000100
-#define TX4927_PCIC_PCICCFG_IMSE1       0x00000080
-#define TX4927_PCIC_PCICCFG_IMSE2       0x00000040
-#define TX4927_PCIC_PCICCFG_IISE        0x00000020
-#define TX4927_PCIC_PCICCFG_ATR 0x00000010
-#define TX4927_PCIC_PCICCFG_ICAE        0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4927_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
-#define TX4927_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4927_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
-
-/* bits for P2GIOGBASE */
-#define TX4927_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
-#define TX4927_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4927_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
-
-#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4927_CCFG_PCI66       0x00800000
-#define TX4927_CCFG_PCIMIDE     0x00400000
-#define TX4927_CCFG_PCIXARB     0x00002000
-#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
-#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
-#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
-#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
-#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
-
-#define TX4937_CCFG_PCIDIVMODE_MASK     0x00001c00
-#define TX4937_CCFG_PCIDIVMODE_8        0x00000000
-#define TX4937_CCFG_PCIDIVMODE_4        0x00000400
-#define TX4937_CCFG_PCIDIVMODE_9        0x00000800
-#define TX4937_CCFG_PCIDIVMODE_4_5      0x00000c00
-#define TX4937_CCFG_PCIDIVMODE_10       0x00001000
-#define TX4937_CCFG_PCIDIVMODE_5        0x00001400
-#define TX4937_CCFG_PCIDIVMODE_11       0x00001800
-#define TX4937_CCFG_PCIDIVMODE_5_5      0x00001c00
-
-/* PCFG : Pin Configuration */
-#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
-#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
-
-/* CLKCTR : Clock Control */
-#define TX4927_CLKCTR_PCICKD    0x00400000
-#define TX4927_CLKCTR_PCIRST    0x00000040
-
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-#define tx4927_sdramcptr        ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
-#define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
-#define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
-#define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-
-#endif /* _LANGUAGE_ASSEMBLY */
-
-#endif /* __ASM_TX4927_TX4927_PCI_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
deleted file mode 100644
index e8807f5c61e9..000000000000
--- a/include/asm-mips/tx4938/tx4938.h
+++ /dev/null
@@ -1,628 +0,0 @@
-/*
- * linux/include/asm-mips/tx4938/tx4938.h
- * Definitions for TX4937/TX4938
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TX_BOARDS_TX4938_H
-#define __ASM_TX_BOARDS_TX4938_H
-
-#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
-#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
-
-#define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
-
-#define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
-#define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
-
-#define TX4938_PCIIO_0 0x10000000
-#define TX4938_PCIIO_1 0x01010000
-#define TX4938_PCIMEM_0 0x08000000
-#define TX4938_PCIMEM_1 0x11000000
-
-#define TX4938_PCIIO_SIZE_0 0x01000000
-#define TX4938_PCIIO_SIZE_1 0x00010000
-#define TX4938_PCIMEM_SIZE_0 0x08000000
-#define TX4938_PCIMEM_SIZE_1 0x00010000
-
-#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
-#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
-
-/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
-#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
-#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
-#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
-#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
-#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
-#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
-#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
-#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
-#define TX4938_NR_TMR   3
-#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
-#define TX4938_NR_SIO   2
-#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
-#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
-#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
-#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
-#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
-
-#ifdef __ASSEMBLY__
-#define _CONST64(c)     c
-#else
-#define _CONST64(c)     c##ull
-
-#include <asm/byteorder.h>
-
-#ifdef __BIG_ENDIAN
-#define endian_def_l2(e1, e2)   \
-        volatile unsigned long e1, e2
-#define endian_def_s2(e1, e2)   \
-        volatile unsigned short e1, e2
-#define endian_def_sb2(e1, e2, e3)      \
-        volatile unsigned short e1;volatile unsigned char e2, e3
-#define endian_def_b2s(e1, e2, e3)      \
-        volatile unsigned char e1, e2;volatile unsigned short e3
-#define endian_def_b4(e1, e2, e3, e4)   \
-        volatile unsigned char e1, e2, e3, e4
-#else
-#define endian_def_l2(e1, e2)   \
-        volatile unsigned long e2, e1
-#define endian_def_s2(e1, e2)   \
-        volatile unsigned short e2, e1
-#define endian_def_sb2(e1, e2, e3)      \
-        volatile unsigned char e3, e2;volatile unsigned short e1
-#define endian_def_b2s(e1, e2, e3)      \
-        volatile unsigned short e3;volatile unsigned char e2, e1
-#define endian_def_b4(e1, e2, e3, e4)   \
-        volatile unsigned char e4, e3, e2, e1
-#endif
-
-
-struct tx4938_sdramc_reg {
-        volatile unsigned long long cr[4];
-        volatile unsigned long long unused0[4];
-        volatile unsigned long long tr;
-        volatile unsigned long long unused1[2];
-        volatile unsigned long long cmd;
-        volatile unsigned long long sfcmd;
-};
-
-struct tx4938_ebusc_reg {
-        volatile unsigned long long cr[8];
-};
-
-struct tx4938_dma_reg {
-        struct tx4938_dma_ch_reg {
-                volatile unsigned long long cha;
-                volatile unsigned long long sar;
-                volatile unsigned long long dar;
-                endian_def_l2(unused0, cntr);
-                endian_def_l2(unused1, sair);
-                endian_def_l2(unused2, dair);
-                endian_def_l2(unused3, ccr);
-                endian_def_l2(unused4, csr);
-        } ch[4];
-        volatile unsigned long long dbr[8];
-        volatile unsigned long long tdhr;
-        volatile unsigned long long midr;
-        endian_def_l2(unused0, mcr);
-};
-
-struct tx4938_pcic_reg {
-        volatile unsigned long pciid;
-        volatile unsigned long pcistatus;
-        volatile unsigned long pciccrev;
-        volatile unsigned long pcicfg1;
-        volatile unsigned long p2gm0plbase;             /* +10 */
-        volatile unsigned long p2gm0pubase;
-        volatile unsigned long p2gm1plbase;
-        volatile unsigned long p2gm1pubase;
-        volatile unsigned long p2gm2pbase;              /* +20 */
-        volatile unsigned long p2giopbase;
-        volatile unsigned long unused0;
-        volatile unsigned long pcisid;
-        volatile unsigned long unused1;         /* +30 */
-        volatile unsigned long pcicapptr;
-        volatile unsigned long unused2;
-        volatile unsigned long pcicfg2;
-        volatile unsigned long g2ptocnt;                /* +40 */
-        volatile unsigned long unused3[15];
-        volatile unsigned long g2pstatus;               /* +80 */
-        volatile unsigned long g2pmask;
-        volatile unsigned long pcisstatus;
-        volatile unsigned long pcimask;
-        volatile unsigned long p2gcfg;          /* +90 */
-        volatile unsigned long p2gstatus;
-        volatile unsigned long p2gmask;
-        volatile unsigned long p2gccmd;
-        volatile unsigned long unused4[24];             /* +a0 */
-        volatile unsigned long pbareqport;              /* +100 */
-        volatile unsigned long pbacfg;
-        volatile unsigned long pbastatus;
-        volatile unsigned long pbamask;
-        volatile unsigned long pbabm;           /* +110 */
-        volatile unsigned long pbacreq;
-        volatile unsigned long pbacgnt;
-        volatile unsigned long pbacstate;
-        volatile unsigned long long g2pmgbase[3];               /* +120 */
-        volatile unsigned long long g2piogbase;
-        volatile unsigned long g2pmmask[3];             /* +140 */
-        volatile unsigned long g2piomask;
-        volatile unsigned long long g2pmpbase[3];               /* +150 */
-        volatile unsigned long long g2piopbase;
-        volatile unsigned long pciccfg;         /* +170 */
-        volatile unsigned long pcicstatus;
-        volatile unsigned long pcicmask;
-        volatile unsigned long unused5;
-        volatile unsigned long long p2gmgbase[3];               /* +180 */
-        volatile unsigned long long p2giogbase;
-        volatile unsigned long g2pcfgadrs;              /* +1a0 */
-        volatile unsigned long g2pcfgdata;
-        volatile unsigned long unused6[8];
-        volatile unsigned long g2pintack;
-        volatile unsigned long g2pspc;
-        volatile unsigned long unused7[12];             /* +1d0 */
-        volatile unsigned long long pdmca;              /* +200 */
-        volatile unsigned long long pdmga;
-        volatile unsigned long long pdmpa;
-        volatile unsigned long long pdmctr;
-        volatile unsigned long long pdmcfg;             /* +220 */
-        volatile unsigned long long pdmsts;
-};
-
-struct tx4938_aclc_reg {
-        volatile unsigned long acctlen;
-        volatile unsigned long acctldis;
-        volatile unsigned long acregacc;
-        volatile unsigned long unused0;
-        volatile unsigned long acintsts;
-        volatile unsigned long acintmsts;
-        volatile unsigned long acinten;
-        volatile unsigned long acintdis;
-        volatile unsigned long acsemaph;
-        volatile unsigned long unused1[7];
-        volatile unsigned long acgpidat;
-        volatile unsigned long acgpodat;
-        volatile unsigned long acslten;
-        volatile unsigned long acsltdis;
-        volatile unsigned long acfifosts;
-        volatile unsigned long unused2[11];
-        volatile unsigned long acdmasts;
-        volatile unsigned long acdmasel;
-        volatile unsigned long unused3[6];
-        volatile unsigned long acaudodat;
-        volatile unsigned long acsurrdat;
-        volatile unsigned long accentdat;
-        volatile unsigned long aclfedat;
-        volatile unsigned long acaudiat;
-        volatile unsigned long unused4;
-        volatile unsigned long acmodoat;
-        volatile unsigned long acmodidat;
-        volatile unsigned long unused5[15];
-        volatile unsigned long acrevid;
-};
-
-
-struct tx4938_tmr_reg {
-        volatile unsigned long tcr;
-        volatile unsigned long tisr;
-        volatile unsigned long cpra;
-        volatile unsigned long cprb;
-        volatile unsigned long itmr;
-        volatile unsigned long unused0[3];
-        volatile unsigned long ccdr;
-        volatile unsigned long unused1[3];
-        volatile unsigned long pgmr;
-        volatile unsigned long unused2[3];
-        volatile unsigned long wtmr;
-        volatile unsigned long unused3[43];
-        volatile unsigned long trr;
-};
-
-struct tx4938_sio_reg {
-        volatile unsigned long lcr;
-        volatile unsigned long dicr;
-        volatile unsigned long disr;
-        volatile unsigned long cisr;
-        volatile unsigned long fcr;
-        volatile unsigned long flcr;
-        volatile unsigned long bgr;
-        volatile unsigned long tfifo;
-        volatile unsigned long rfifo;
-};
-
-struct tx4938_ndfmc_reg {
-        endian_def_l2(unused0, dtr);
-        endian_def_l2(unused1, mcr);
-        endian_def_l2(unused2, sr);
-        endian_def_l2(unused3, isr);
-        endian_def_l2(unused4, imr);
-        endian_def_l2(unused5, spr);
-        endian_def_l2(unused6, rstr);
-};
-
-struct tx4938_spi_reg {
-        volatile unsigned long mcr;
-        volatile unsigned long cr0;
-        volatile unsigned long cr1;
-        volatile unsigned long fs;
-        volatile unsigned long unused1;
-        volatile unsigned long sr;
-        volatile unsigned long dr;
-        volatile unsigned long unused2;
-};
-
-struct tx4938_sramc_reg {
-        volatile unsigned long long cr;
-};
-
-struct tx4938_ccfg_reg {
-        volatile unsigned long long ccfg;
-        volatile unsigned long long crir;
-        volatile unsigned long long pcfg;
-        volatile unsigned long long tear;
-        volatile unsigned long long clkctr;
-        volatile unsigned long long unused0;
-        volatile unsigned long long garbc;
-        volatile unsigned long long unused1;
-        volatile unsigned long long unused2;
-        volatile unsigned long long ramp;
-        volatile unsigned long long unused3;
-        volatile unsigned long long jmpadr;
-};
-
-#undef endian_def_l2
-#undef endian_def_s2
-#undef endian_def_sb2
-#undef endian_def_b2s
-#undef endian_def_b4
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * NDFMC
- */
-
-/* NDFMCR : NDFMC Mode Control */
-#define TX4938_NDFMCR_WE        0x80
-#define TX4938_NDFMCR_ECC_ALL   0x60
-#define TX4938_NDFMCR_ECC_RESET 0x60
-#define TX4938_NDFMCR_ECC_READ  0x40
-#define TX4938_NDFMCR_ECC_ON    0x20
-#define TX4938_NDFMCR_ECC_OFF   0x00
-#define TX4938_NDFMCR_CE        0x10
-#define TX4938_NDFMCR_BSPRT     0x04
-#define TX4938_NDFMCR_ALE       0x02
-#define TX4938_NDFMCR_CLE       0x01
-
-/* NDFMCR : NDFMC Status */
-#define TX4938_NDFSR_BUSY       0x80
-
-/* NDFMCR : NDFMC Reset */
-#define TX4938_NDFRSTR_RST      0x01
-
-/*
- * IRC
- */
-
-#define TX4938_IR_ECCERR        0
-#define TX4938_IR_WTOERR        1
-#define TX4938_NUM_IR_INT       6
-#define TX4938_IR_INT(n)        (2 + (n))
-#define TX4938_NUM_IR_SIO       2
-#define TX4938_IR_SIO(n)        (8 + (n))
-#define TX4938_NUM_IR_DMA       4
-#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
-#define TX4938_IR_PIO   14
-#define TX4938_IR_PDMAC 15
-#define TX4938_IR_PCIC  16
-#define TX4938_NUM_IR_TMR       3
-#define TX4938_IR_TMR(n)        (17 + (n))
-#define TX4938_IR_NDFMC 21
-#define TX4938_IR_PCIERR        22
-#define TX4938_IR_PCIPME        23
-#define TX4938_IR_ACLC  24
-#define TX4938_IR_ACLCPME       25
-#define TX4938_IR_PCIC1 26
-#define TX4938_IR_SPI   31
-#define TX4938_NUM_IR   32
-/* multiplex */
-#define TX4938_IR_ETH0  TX4938_IR_INT(4)
-#define TX4938_IR_ETH1  TX4938_IR_INT(3)
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
-#define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
-#define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
-#define TX4938_CCFG_TINTDIS     0x01000000
-#define TX4938_CCFG_PCI66       0x00800000
-#define TX4938_CCFG_PCIMODE     0x00400000
-#define TX4938_CCFG_PCI1_66     0x00200000
-#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
-#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
-#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
-#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
-#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
-#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
-#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
-#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
-#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
-#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
-#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
-#define TX4938_CCFG_BEOW        0x00010000
-#define TX4938_CCFG_WR  0x00008000
-#define TX4938_CCFG_TOE 0x00004000
-#define TX4938_CCFG_PCIXARB     0x00002000
-#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
-#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
-#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
-#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
-#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
-#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
-#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
-#define TX4938_CCFG_PCI1DMD     0x00000100
-#define TX4938_CCFG_SYSSP_MASK  0x000000c0
-#define TX4938_CCFG_ENDIAN      0x00000004
-#define TX4938_CCFG_HALT        0x00000002
-#define TX4938_CCFG_ACEHOLD     0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
-#define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
-#define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
-#define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
-#define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
-#define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
-#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
-#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
-#define TX4938_PCFG_SYSCLKEN    0x08000000
-#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
-#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
-#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
-#define TX4938_PCFG_SEL2        0x00000200
-#define TX4938_PCFG_SEL1        0x00000100
-#define TX4938_PCFG_DMASEL_ALL  0x0000000f
-#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
-#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
-#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
-#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
-#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
-#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
-#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
-#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
-
-/* CLKCTR : Clock Control */
-#define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
-#define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
-#define TX4938_CLKCTR_ETH1CKD   0x80000000
-#define TX4938_CLKCTR_ETH0CKD   0x40000000
-#define TX4938_CLKCTR_SPICKD    0x20000000
-#define TX4938_CLKCTR_SRAMCKD   0x10000000
-#define TX4938_CLKCTR_PCIC1CKD  0x08000000
-#define TX4938_CLKCTR_DMA1CKD   0x04000000
-#define TX4938_CLKCTR_ACLCKD    0x02000000
-#define TX4938_CLKCTR_PIOCKD    0x01000000
-#define TX4938_CLKCTR_DMACKD    0x00800000
-#define TX4938_CLKCTR_PCICKD    0x00400000
-#define TX4938_CLKCTR_TM0CKD    0x00100000
-#define TX4938_CLKCTR_TM1CKD    0x00080000
-#define TX4938_CLKCTR_TM2CKD    0x00040000
-#define TX4938_CLKCTR_SIO0CKD   0x00020000
-#define TX4938_CLKCTR_SIO1CKD   0x00010000
-#define TX4938_CLKCTR_ETH1RST   0x00008000
-#define TX4938_CLKCTR_ETH0RST   0x00004000
-#define TX4938_CLKCTR_SPIRST    0x00002000
-#define TX4938_CLKCTR_SRAMRST   0x00001000
-#define TX4938_CLKCTR_PCIC1RST  0x00000800
-#define TX4938_CLKCTR_DMA1RST   0x00000400
-#define TX4938_CLKCTR_ACLRST    0x00000200
-#define TX4938_CLKCTR_PIORST    0x00000100
-#define TX4938_CLKCTR_DMARST    0x00000080
-#define TX4938_CLKCTR_PCIRST    0x00000040
-#define TX4938_CLKCTR_TM0RST    0x00000010
-#define TX4938_CLKCTR_TM1RST    0x00000008
-#define TX4938_CLKCTR_TM2RST    0x00000004
-#define TX4938_CLKCTR_SIO0RST   0x00000002
-#define TX4938_CLKCTR_SIO1RST   0x00000001
-
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
-#define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
-#define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
-
-/* bits for PBACFG */
-#define TX4938_PCIC_PBACFG_FIXPA        0x00000008
-#define TX4938_PCIC_PBACFG_RPBA 0x00000004
-#define TX4938_PCIC_PBACFG_PBAEN        0x00000002
-#define TX4938_PCIC_PBACFG_BMCEN        0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for G2PIOGBASE */
-#define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
-#define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
-#define TX4938_PCIC_PCICSTATUS_PME      0x00000400
-#define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
-#define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
-#define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
-#define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
-#define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
-#define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
-#define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
-#define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
-
-/* bits for PCICCFG */
-#define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
-#define TX4938_PCIC_PCICCFG_HRST        0x00000800
-#define TX4938_PCIC_PCICCFG_SRST        0x00000400
-#define TX4938_PCIC_PCICCFG_IRBER       0x00000200
-#define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
-#define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
-#define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
-#define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
-#define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
-#define TX4938_PCIC_PCICCFG_TCAR        0x00000010
-#define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
-#define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
-
-/* bits for P2GIOGBASE */
-#define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
-#define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
-#define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
-
-#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/* bits for PDMCFG */
-#define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
-#define TX4938_PCIC_PDMCFG_EXFER        0x00100000
-#define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
-#define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
-#define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
-#define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
-#define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
-#define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
-#define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
-#define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
-#define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
-#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
-#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
-#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
-#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
-#define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
-#define TX4938_PCIC_PDMCFG_CHRST        0x00000001
-
-/* bits for PDMSTS */
-#define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
-#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
-#define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
-#define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
-#define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
-#define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
-#define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
-#define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
-#define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
-#define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
-#define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
-#define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
-#define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
-#define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
-#define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
-#define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
-#define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
-
-/*
- * DMA
- */
-/* bits for MCR */
-#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
-#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
-#define TX4938_DMA_MCR_RSFIF    0x00000080
-#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
-#define TX4938_DMA_MCR_RPRT     0x00000002
-#define TX4938_DMA_MCR_MSTEN    0x00000001
-
-/* bits for CCRn */
-#define TX4938_DMA_CCR_IMMCHN   0x20000000
-#define TX4938_DMA_CCR_USEXFSZ  0x10000000
-#define TX4938_DMA_CCR_LE       0x08000000
-#define TX4938_DMA_CCR_DBINH    0x04000000
-#define TX4938_DMA_CCR_SBINH    0x02000000
-#define TX4938_DMA_CCR_CHRST    0x01000000
-#define TX4938_DMA_CCR_RVBYTE   0x00800000
-#define TX4938_DMA_CCR_ACKPOL   0x00400000
-#define TX4938_DMA_CCR_REQPL    0x00200000
-#define TX4938_DMA_CCR_EGREQ    0x00100000
-#define TX4938_DMA_CCR_CHDN     0x00080000
-#define TX4938_DMA_CCR_DNCTL    0x00060000
-#define TX4938_DMA_CCR_EXTRQ    0x00010000
-#define TX4938_DMA_CCR_INTRQD   0x0000e000
-#define TX4938_DMA_CCR_INTENE   0x00001000
-#define TX4938_DMA_CCR_INTENC   0x00000800
-#define TX4938_DMA_CCR_INTENT   0x00000400
-#define TX4938_DMA_CCR_CHNEN    0x00000200
-#define TX4938_DMA_CCR_XFACT    0x00000100
-#define TX4938_DMA_CCR_SMPCHN   0x00000020
-#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
-#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
-#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
-#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
-#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
-#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
-#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
-#define TX4938_DMA_CCR_MEMIO    0x00000002
-#define TX4938_DMA_CCR_SNGAD    0x00000001
-
-/* bits for CSRn */
-#define TX4938_DMA_CSR_CHNEN    0x00000400
-#define TX4938_DMA_CSR_STLXFER  0x00000200
-#define TX4938_DMA_CSR_CHNACT   0x00000100
-#define TX4938_DMA_CSR_ABCHC    0x00000080
-#define TX4938_DMA_CSR_NCHNC    0x00000040
-#define TX4938_DMA_CSR_NTRNFC   0x00000020
-#define TX4938_DMA_CSR_EXTDN    0x00000010
-#define TX4938_DMA_CSR_CFERR    0x00000008
-#define TX4938_DMA_CSR_CHERR    0x00000004
-#define TX4938_DMA_CSR_DESERR   0x00000002
-#define TX4938_DMA_CSR_SORERR   0x00000001
-
-#ifndef __ASSEMBLY__
-
-#define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
-#define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
-#define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
-#define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
-#define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
-#define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
-#define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
-#define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
-#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
-#define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
-#define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
-#define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
-
-
-#define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
-#define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
-
-#define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
-#define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
-
-#define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
-#define TX4938_EBUSC_SIZE(ch)   \
-        (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
new file mode 100644
index 000000000000..cbae37ec3d88
--- /dev/null
+++ b/include/asm-mips/txx9/generic.h
@@ -0,0 +1,48 @@
+/*
+ * linux/include/asm-mips/txx9/generic.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_GENERIC_H
+#define __ASM_TXX9_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/ioport.h>       /* for struct resource */
+
+extern struct resource txx9_ce_res[];
+#define TXX9_CE(n)      (unsigned long)(txx9_ce_res[(n)].start)
+extern unsigned int txx9_pcode;
+extern char txx9_pcode_str[8];
+void txx9_reg_res_init(unsigned int pcode, unsigned long base,
+                       unsigned long size);
+
+extern unsigned int txx9_master_clock;
+extern unsigned int txx9_cpu_clock;
+extern unsigned int txx9_gbus_clock;
+#define TXX9_IMCLK      (txx9_gbus_clock / 2)
+
+extern int txx9_ccfg_toeon;
+struct uart_port;
+int early_serial_txx9_setup(struct uart_port *port);
+
+struct pci_dev;
+struct txx9_board_vec {
+        const char *system;
+        void (*prom_init)(void);
+        void (*mem_setup)(void);
+        void (*irq_setup)(void);
+        void (*time_init)(void);
+        void (*arch_init)(void);
+        void (*device_init)(void);
+#ifdef CONFIG_PCI
+        int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+#endif
+};
+extern struct txx9_board_vec *txx9_board_vec;
+extern int (*txx9_irq_dispatch)(int pending);
+void prom_init_cmdline(void);
+char *prom_getcmdline(void);
+
+#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index a162268f17df..d6eb1b6a54eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -7,10 +7,10 @@
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
  */
-#ifndef __ASM_TX3927_JMR3927_H
-#define __ASM_TX3927_JMR3927_H
+#ifndef __ASM_TXX9_JMR3927_H
+#define __ASM_TXX9_JMR3927_H
 
-#include <asm/jmr3927/tx3927.h>
+#include <asm/txx9/tx3927.h>
 #include <asm/addrspace.h>
 #include <asm/system.h>
 #include <asm/txx9irq.h>
@@ -174,4 +174,9 @@
  *      INT[3:0]
  */
 
-#endif /* __ASM_TX3927_JMR3927_H */
+void jmr3927_prom_init(void);
+void jmr3927_irq_setup(void);
+struct pci_dev;
+int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
new file mode 100644
index 000000000000..d89a45091e24
--- /dev/null
+++ b/include/asm-mips/txx9/pci.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_PCI_H
+#define __ASM_TXX9_PCI_H
+
+#include <linux/pci.h>
+
+extern struct pci_controller txx9_primary_pcic;
+struct pci_controller *
+txx9_alloc_pci_controller(struct pci_controller *pcic,
+                          unsigned long mem_base, unsigned long mem_size,
+                          unsigned long io_base, unsigned long io_size);
+
+int txx9_pci66_check(struct pci_controller *hose, int top_bus,
+                        int current_bus);
+extern int txx9_pci_mem_high __initdata;
+
+extern int txx9_pci_option;
+#define TXX9_PCI_OPT_PICMG      0x0002
+#define TXX9_PCI_OPT_CLK_33     0x0008
+#define TXX9_PCI_OPT_CLK_66     0x0010
+#define TXX9_PCI_OPT_CLK_MASK   \
+        (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
+#define TXX9_PCI_OPT_CLK_AUTO   TXX9_PCI_OPT_CLK_MASK
+
+enum txx9_pci_err_action {
+        TXX9_PCI_ERR_REPORT,
+        TXX9_PCI_ERR_IGNORE,
+        TXX9_PCI_ERR_PANIC,
+};
+extern enum txx9_pci_err_action txx9_pci_err_action;
+
+#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
new file mode 100644
index 000000000000..6fcec912c143
--- /dev/null
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -0,0 +1,89 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_RBTX4927_H
+#define __ASM_TXX9_RBTX4927_H
+
+#include <asm/txx9/tx4927.h>
+
+#define RBTX4927_PCIMEM         0x08000000
+#define RBTX4927_PCIMEM_SIZE    0x08000000
+#define RBTX4927_PCIIO          0x16000000
+#define RBTX4927_PCIIO_SIZE     0x01000000
+
+#define RBTX4927_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4927_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
+#define RBTX4927_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000f002)
+#define RBTX4927_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x0000f006)
+#define RBTX4927_BRAMRTC_BASE   (IO_BASE + TXX9_CE(2) + 0x00010000)
+#define RBTX4927_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4927_ETHER_ADDR     (RBTX4927_ETHER_BASE + 0x280)
+
+#define rbtx4927_imask_addr     ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
+#define rbtx4927_imstat_addr    ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
+#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
+#define rbtx4927_softresetlock_addr     \
+                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
+#define rbtx4927_pcireset_addr  ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4927_INTB_PCID      0
+#define RBTX4927_INTB_PCIC      1
+#define RBTX4927_INTB_PCIB      2
+#define RBTX4927_INTB_PCIA      3
+#define RBTX4927_INTF_PCID      (1 << RBTX4927_INTB_PCID)
+#define RBTX4927_INTF_PCIC      (1 << RBTX4927_INTB_PCIC)
+#define RBTX4927_INTF_PCIB      (1 << RBTX4927_INTB_PCIB)
+#define RBTX4927_INTF_PCIA      (1 << RBTX4927_INTB_PCIA)
+
+#define RBTX4927_NR_IRQ_IOC     8       /* IOC */
+
+#define RBTX4927_IRQ_IOC        (TXX9_IRQ_BASE + TX4927_NUM_IR)
+#define RBTX4927_IRQ_IOC_PCID   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
+#define RBTX4927_IRQ_IOC_PCIC   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
+#define RBTX4927_IRQ_IOC_PCIB   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
+#define RBTX4927_IRQ_IOC_PCIA   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
+
+#define RBTX4927_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4927_IR_INT(1))
+
+#ifdef CONFIG_PCI
+#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
+#else
+#define RBTX4927_ISA_IO_OFFSET 0
+#endif
+
+#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
+#define RBTX4927_RTL_8019_IRQ  (TXX9_IRQ_BASE + TX4927_IR_INT(3))
+
+void rbtx4927_prom_init(void);
+void rbtx4927_irq_setup(void);
+struct pci_dev;
+int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index dfed7beb533f..9f0441a28126 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -1,5 +1,4 @@
 /*
- * linux/include/asm-mips/tx4938/rbtx4938.h
  * Definitions for TX4937/TX4938
  *
  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
@@ -9,42 +8,38 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#ifndef __ASM_TX_BOARDS_RBTX4938_H
-#define __ASM_TX_BOARDS_RBTX4938_H
+#ifndef __ASM_TXX9_RBTX4938_H
+#define __ASM_TXX9_RBTX4938_H
 
 #include <asm/addrspace.h>
-#include <asm/tx4938/tx4938.h>
 #include <asm/txx9irq.h>
-
-/* CS */
-#define RBTX4938_CE0    0x1c000000      /* 64M */
-#define RBTX4938_CE2    0x17f00000      /* 1M */
+#include <asm/txx9/tx4938.h>
 
 /* Address map */
-#define RBTX4938_FPGA_REG_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000000)
-#define RBTX4938_FPGA_REV_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000002)
-#define RBTX4938_CONFIG1_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000004)
-#define RBTX4938_CONFIG2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000006)
-#define RBTX4938_CONFIG3_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000008)
-#define RBTX4938_LED_ADDR       (KSEG1 + RBTX4938_CE2 + 0x00001000)
-#define RBTX4938_DIPSW_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00001002)
-#define RBTX4938_BDIPSW_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00001004)
-#define RBTX4938_IMASK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002000)
-#define RBTX4938_IMASK2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002002)
-#define RBTX4938_INTPOL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002004)
-#define RBTX4938_ISTAT_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002006)
-#define RBTX4938_ISTAT2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002008)
-#define RBTX4938_IMSTAT_ADDR    (KSEG1 + RBTX4938_CE2 + 0x0000200a)
-#define RBTX4938_IMSTAT2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x0000200c)
-#define RBTX4938_SOFTINT_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00003000)
-#define RBTX4938_PIOSEL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00005000)
-#define RBTX4938_SPICS_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005002)
-#define RBTX4938_SFPWR_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005008)
-#define RBTX4938_SFVOL_ADDR     (KSEG1 + RBTX4938_CE2 + 0x0000500a)
-#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
-#define RBTX4938_SOFTRESETLOCK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00007002)
-#define RBTX4938_PCIRESET_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00007004)
-#define RBTX4938_ETHER_BASE     (KSEG1 + RBTX4938_CE2 + 0x00020000)
+#define RBTX4938_FPGA_REG_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000000)
+#define RBTX4938_FPGA_REV_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000002)
+#define RBTX4938_CONFIG1_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000004)
+#define RBTX4938_CONFIG2_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000006)
+#define RBTX4938_CONFIG3_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000008)
+#define RBTX4938_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
+#define RBTX4938_DIPSW_ADDR     (IO_BASE + TXX9_CE(2) + 0x00001002)
+#define RBTX4938_BDIPSW_ADDR    (IO_BASE + TXX9_CE(2) + 0x00001004)
+#define RBTX4938_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4938_IMASK2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002002)
+#define RBTX4938_INTPOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002004)
+#define RBTX4938_ISTAT_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4938_ISTAT2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002008)
+#define RBTX4938_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000200a)
+#define RBTX4938_IMSTAT2_ADDR   (IO_BASE + TXX9_CE(2) + 0x0000200c)
+#define RBTX4938_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
+#define RBTX4938_PIOSEL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005000)
+#define RBTX4938_SPICS_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005002)
+#define RBTX4938_SFPWR_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005008)
+#define RBTX4938_SFVOL_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000500a)
+#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
+#define RBTX4938_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00007002)
+#define RBTX4938_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x00007004)
+#define RBTX4938_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
 
 /* Ethernet port address (Jumperless Mode (W12:Open)) */
 #define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
@@ -102,35 +97,12 @@
  * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
  * IRQ hardware is supported.
  */
-#define RBTX4938_NR_IRQ_LOCAL   8
-#define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
 #define RBTX4938_NR_IRQ_IOC     8
 
-#define TX4938_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
-#define TX4938_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
-
-#define TX4938_IRQ_PIC_BEG  TXX9_IRQ_BASE
-#define TX4938_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
-#define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
-#define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
-#define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
-#define TX4938_IRQ_USER1            (TX4938_IRQ_CP0_BEG+1)
-#define TX4938_IRQ_CPU_TIMER        (TX4938_IRQ_CP0_BEG+7)
-
-#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG   0
-#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END   7
-
-#define TOSHIBA_RBTX4938_IRQ_IOC_BEG  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
-#define TOSHIBA_RBTX4938_IRQ_IOC_END  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
-#define RBTX4938_IRQ_LOCAL      TX4938_IRQ_CP0_BEG
-#define RBTX4938_IRQ_IRC        (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
-#define RBTX4938_IRQ_IOC        (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
+#define RBTX4938_IRQ_IRC        TXX9_IRQ_BASE
+#define RBTX4938_IRQ_IOC        (TXX9_IRQ_BASE + TX4938_NUM_IR)
 #define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
 
-#define RBTX4938_IRQ_LOCAL_SOFT0        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
-#define RBTX4938_IRQ_LOCAL_SOFT1        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
-#define RBTX4938_IRQ_LOCAL_IRC  (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
-#define RBTX4938_IRQ_LOCAL_TIMER        (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
 #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
 #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
 #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
@@ -158,11 +130,16 @@
 
 
 /* IOC (PCI, etc) */
-#define RBTX4938_IRQ_IOCINT     (TX4938_IRQ_NEST_EXT_ON_PIC)
+#define RBTX4938_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4938_IR_INT(0))
 /* Onboard 10M Ether */
-#define RBTX4938_IRQ_ETHER      (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
+#define RBTX4938_IRQ_ETHER      (TXX9_IRQ_BASE + TX4938_IR_INT(1))
 
 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 
-#endif /* __ASM_TX_BOARDS_RBTX4938_H */
+void rbtx4938_prom_init(void);
+void rbtx4938_irq_setup(void);
+struct pci_dev;
+int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 5d93bab51254..9375e4fc2289 100644
--- a/include/asm-mips/tx4927/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -1,6 +1,4 @@
 /*
- * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
- *
  * Interface for smsc fdc48m81x Super IO chip
  *
  * Author: MontaVista Software, Inc. source@mvista.com
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/txx9/spi.h
index 6a60c83e152b..ddfb2a0dc432 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/txx9/spi.h
@@ -1,5 +1,4 @@
 /*
- * linux/include/asm-mips/tx4938/spi.h
  * Definitions for TX4937/TX4938 SPI
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
@@ -11,10 +10,10 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
-#define __ASM_TX_BOARDS_TX4938_SPI_H
+#ifndef __ASM_TXX9_SPI_H
+#define __ASM_TXX9_SPI_H
 
 extern int spi_eeprom_register(int chipid);
 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
 
-#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
+#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/txx9/tx3927.h
index fb580333c102..ea79e1b16e71 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -5,22 +5,23 @@
  *
  * Copyright (C) 2000 Toshiba Corporation
  */
-#ifndef __ASM_TX3927_H
-#define __ASM_TX3927_H
+#ifndef __ASM_TXX9_TX3927_H
+#define __ASM_TXX9_TX3927_H
 
-#include <asm/jmr3927/txx927.h>
+#include <asm/txx9/txx927.h>
 
-#define TX3927_SDRAMC_REG       0xfffe8000
-#define TX3927_ROMC_REG         0xfffe9000
-#define TX3927_DMA_REG          0xfffeb000
-#define TX3927_IRC_REG          0xfffec000
-#define TX3927_PCIC_REG         0xfffed000
-#define TX3927_CCFG_REG         0xfffee000
+#define TX3927_REG_BASE 0xfffe0000UL
+#define TX3927_SDRAMC_REG       (TX3927_REG_BASE + 0x8000)
+#define TX3927_ROMC_REG         (TX3927_REG_BASE + 0x9000)
+#define TX3927_DMA_REG          (TX3927_REG_BASE + 0xb000)
+#define TX3927_IRC_REG          (TX3927_REG_BASE + 0xc000)
+#define TX3927_PCIC_REG         (TX3927_REG_BASE + 0xd000)
+#define TX3927_CCFG_REG         (TX3927_REG_BASE + 0xe000)
 #define TX3927_NR_TMR   3
-#define TX3927_TMR_REG(ch)      (0xfffef000 + (ch) * 0x100)
+#define TX3927_TMR_REG(ch)      (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
 #define TX3927_NR_SIO   2
-#define TX3927_SIO_REG(ch)      (0xfffef300 + (ch) * 0x100)
-#define TX3927_PIO_REG          0xfffef500
+#define TX3927_SIO_REG(ch)      (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX3927_PIO_REG          (TX3927_REG_BASE + 0xf500)
 
 struct tx3927_sdramc_reg {
         volatile unsigned long cr[8];
@@ -316,4 +317,8 @@ struct tx3927_ccfg_reg {
 #define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
 #define tx3927_pioptr           ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
 
-#endif /* __ASM_TX3927_H */
+struct pci_controller;
+void __init tx3927_pcic_setup(struct pci_controller *channel,
+                              unsigned long sdram_size, int extarb);
+
+#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
new file mode 100644
index 000000000000..ceb4b79ff4e3
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927.h
@@ -0,0 +1,254 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2006 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_TX4927_H
+#define __ASM_TXX9_TX4927_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4927pcic.h>
+
+#ifdef CONFIG_64BIT
+#define TX4927_REG_BASE 0xffffffffff1f0000UL
+#else
+#define TX4927_REG_BASE 0xff1f0000UL
+#endif
+#define TX4927_REG_SIZE 0x00010000
+
+#define TX4927_SDRAMC_REG       (TX4927_REG_BASE + 0x8000)
+#define TX4927_EBUSC_REG        (TX4927_REG_BASE + 0x9000)
+#define TX4927_PCIC_REG         (TX4927_REG_BASE + 0xd000)
+#define TX4927_CCFG_REG         (TX4927_REG_BASE + 0xe000)
+#define TX4927_IRC_REG          (TX4927_REG_BASE + 0xf600)
+#define TX4927_NR_TMR   3
+#define TX4927_TMR_REG(ch)      (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
+#define TX4927_NR_SIO   2
+#define TX4927_SIO_REG(ch)      (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX4927_PIO_REG          (TX4927_REG_BASE + 0xf500)
+
+#define TX4927_IR_INT(n)        (2 + (n))
+#define TX4927_IR_SIO(n)        (8 + (n))
+#define TX4927_IR_PCIC          16
+#define TX4927_NUM_IR_TMR       3
+#define TX4927_IR_TMR(n)        (17 + (n))
+#define TX4927_IR_PCIERR        22
+#define TX4927_NUM_IR   32
+
+#define TX4927_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4927_NUM_PIO  16
+
+struct tx4927_sdramc_reg {
+        u64 cr[4];
+        u64 unused0[4];
+        u64 tr;
+        u64 unused1[2];
+        u64 cmd;
+};
+
+struct tx4927_ebusc_reg {
+        u64 cr[8];
+};
+
+struct tx4927_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+};
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_WDRST       0x0000020000000000ULL
+#define TX4927_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4927_CCFG_TINTDIS     0x01000000
+#define TX4927_CCFG_PCI66       0x00800000
+#define TX4927_CCFG_PCIMODE     0x00400000
+#define TX4927_CCFG_DIVMODE_MASK        0x000e0000
+#define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
+#define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
+#define TX4927_CCFG_BEOW        0x00010000
+#define TX4927_CCFG_WR  0x00008000
+#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_PCIARB      0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
+#define TX4927_CCFG_SYSSP_MASK  0x000000c0
+#define TX4927_CCFG_ENDIAN      0x00000004
+#define TX4927_CCFG_HALT        0x00000002
+#define TX4927_CCFG_ACEHOLD     0x00000001
+#define TX4927_CCFG_W1CBITS     (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4927_PCFG_SYSCLKEN    0x08000000
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4927_PCFG_SEL2        0x00000200
+#define TX4927_PCFG_SEL1        0x00000100
+#define TX4927_PCFG_DMASEL_ALL  0x000000ff
+#define TX4927_PCFG_DMASEL0_MASK        0x00000003
+#define TX4927_PCFG_DMASEL1_MASK        0x0000000c
+#define TX4927_PCFG_DMASEL2_MASK        0x00000030
+#define TX4927_PCFG_DMASEL3_MASK        0x000000c0
+#define TX4927_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4927_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4927_PCFG_DMASEL0_ACL0        0x00000002
+#define TX4927_PCFG_DMASEL0_ACL2        0x00000003
+#define TX4927_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4927_PCFG_DMASEL1_SIO1        0x00000004
+#define TX4927_PCFG_DMASEL1_ACL1        0x00000008
+#define TX4927_PCFG_DMASEL1_ACL3        0x0000000c
+#define TX4927_PCFG_DMASEL2_DRQ2        0x00000000      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_SIO0        0x00000010      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_ACL1        0x00000000      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL2        0x00000020      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL0        0x00000030      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4927_PCFG_DMASEL3_SIO0        0x00000040
+#define TX4927_PCFG_DMASEL3_ACL3        0x00000080
+#define TX4927_PCFG_DMASEL3_ACL1        0x000000c0
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_ACLCKD    0x02000000
+#define TX4927_CLKCTR_PIOCKD    0x01000000
+#define TX4927_CLKCTR_DMACKD    0x00800000
+#define TX4927_CLKCTR_PCICKD    0x00400000
+#define TX4927_CLKCTR_TM0CKD    0x00100000
+#define TX4927_CLKCTR_TM1CKD    0x00080000
+#define TX4927_CLKCTR_TM2CKD    0x00040000
+#define TX4927_CLKCTR_SIO0CKD   0x00020000
+#define TX4927_CLKCTR_SIO1CKD   0x00010000
+#define TX4927_CLKCTR_ACLRST    0x00000200
+#define TX4927_CLKCTR_PIORST    0x00000100
+#define TX4927_CLKCTR_DMARST    0x00000080
+#define TX4927_CLKCTR_PCIRST    0x00000040
+#define TX4927_CLKCTR_TM0RST    0x00000010
+#define TX4927_CLKCTR_TM1RST    0x00000008
+#define TX4927_CLKCTR_TM2RST    0x00000004
+#define TX4927_CLKCTR_SIO0RST   0x00000002
+#define TX4927_CLKCTR_SIO1RST   0x00000001
+
+#define tx4927_sdramcptr \
+                ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr \
+                ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr \
+                ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
+#define tx4927_pioptr           ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
+
+#define TX4927_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
+
+#define TX4927_SDRAMC_CR(ch)    __raw_readq(&tx4927_sdramcptr->cr[(ch)])
+#define TX4927_SDRAMC_BA(ch)    ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
+#define TX4927_SDRAMC_SIZE(ch)  \
+        ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
+
+#define TX4927_EBUSC_CR(ch)     __raw_readq(&tx4927_ebuscptr->cr[(ch)])
+#define TX4927_EBUSC_BA(ch)     ((TX4927_EBUSC_CR(ch) >> 48) << 20)
+#define TX4927_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
+
+/* utilities */
+static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) & ~bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) | bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+
+/* These functions are not interrupt safe. */
+static inline void tx4927_ccfg_clear(__u64 bits)
+{
+        ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
+                       & ~(TX4927_CCFG_W1CBITS | bits),
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_set(__u64 bits)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~TX4927_CCFG_W1CBITS) | bits,
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_change(__u64 change, __u64 new)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~(TX4927_CCFG_W1CBITS | change)) |
+                       new,
+                       &tx4927_ccfgptr->ccfg);
+}
+
+unsigned int tx4927_get_mem_size(void);
+void tx4927_wdr_init(void);
+void tx4927_setup(void);
+void tx4927_time_init(unsigned int tmrnr);
+void tx4927_setup_serial(void);
+int tx4927_report_pciclk(void);
+int tx4927_pciclk66_setup(void);
+void tx4927_irq_init(void);
+
+#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..d61c3d09c4a2
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -0,0 +1,199 @@
+/*
+ * include/asm-mips/txx9/tx4927pcic.h
+ * TX4927 PCI controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_TX4927PCIC_H
+#define __ASM_TXX9_TX4927PCIC_H
+
+#include <linux/pci.h>
+
+struct tx4927_pcic_reg {
+        u32 pciid;
+        u32 pcistatus;
+        u32 pciccrev;
+        u32 pcicfg1;
+        u32 p2gm0plbase;                /* +10 */
+        u32 p2gm0pubase;
+        u32 p2gm1plbase;
+        u32 p2gm1pubase;
+        u32 p2gm2pbase;         /* +20 */
+        u32 p2giopbase;
+        u32 unused0;
+        u32 pcisid;
+        u32 unused1;            /* +30 */
+        u32 pcicapptr;
+        u32 unused2;
+        u32 pcicfg2;
+        u32 g2ptocnt;           /* +40 */
+        u32 unused3[15];
+        u32 g2pstatus;          /* +80 */
+        u32 g2pmask;
+        u32 pcisstatus;
+        u32 pcimask;
+        u32 p2gcfg;             /* +90 */
+        u32 p2gstatus;
+        u32 p2gmask;
+        u32 p2gccmd;
+        u32 unused4[24];                /* +a0 */
+        u32 pbareqport;         /* +100 */
+        u32 pbacfg;
+        u32 pbastatus;
+        u32 pbamask;
+        u32 pbabm;              /* +110 */
+        u32 pbacreq;
+        u32 pbacgnt;
+        u32 pbacstate;
+        u64 g2pmgbase[3];               /* +120 */
+        u64 g2piogbase;
+        u32 g2pmmask[3];                /* +140 */
+        u32 g2piomask;
+        u64 g2pmpbase[3];               /* +150 */
+        u64 g2piopbase;
+        u32 pciccfg;            /* +170 */
+        u32 pcicstatus;
+        u32 pcicmask;
+        u32 unused5;
+        u64 p2gmgbase[3];               /* +180 */
+        u64 p2giogbase;
+        u32 g2pcfgadrs;         /* +1a0 */
+        u32 g2pcfgdata;
+        u32 unused6[8];
+        u32 g2pintack;
+        u32 g2pspc;
+        u32 unused7[12];                /* +1d0 */
+        u64 pdmca;              /* +200 */
+        u64 pdmga;
+        u64 pdmpa;
+        u64 pdmctr;
+        u64 pdmcfg;             /* +220 */
+        u64 pdmsts;
+};
+
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci_regs.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci_regs.h */
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
+#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for PBASTATUS/PBAMASK */
+#define TX4927_PCIC_PBASTATUS_ALL       0x00000001
+#define TX4927_PCIC_PBASTATUS_BM        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PMnGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PIOGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4927_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4927_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4927_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4927_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4927_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4927_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4927_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4927_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST        0x00000800
+#define TX4927_PCIC_PCICCFG_SRST        0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4927_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4927_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4927_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4927_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4927_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4927_PCIC_PCICCFG_ICAEN       0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/* bits for PDMCFG */
+#define TX4927_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4927_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4927_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4927_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4927_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4927_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4927_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4927_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4927_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4927_PCIC_PDMCFG_CHRST        0x00000001
+
+/* bits for PDMSTS */
+#define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4927_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4927_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4927_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4927_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4927_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4927_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4927_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4927_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4927_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4927_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4927_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4927_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4927_PCIC_PDMSTS_ALL_ERR      0x0000000f
+
+struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
+        struct pci_controller *channel);
+void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
+                              struct pci_controller *channel, int extarb);
+void tx4927_report_pcic_status(void);
+
+#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
new file mode 100644
index 000000000000..1ed969d381d6
--- /dev/null
+++ b/include/asm-mips/txx9/tx4938.h
@@ -0,0 +1,290 @@
+/*
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_TX4938_H
+#define __ASM_TXX9_TX4938_H
+
+/* some controllers are compatible with 4927 */
+#include <asm/txx9/tx4927.h>
+
+#ifdef CONFIG_64BIT
+#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
+#else
+#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
+#endif
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+
+struct tx4938_sramc_reg {
+        u64 cr;
+};
+
+struct tx4938_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+        u64 unused3;
+        u64 jmpadr;
+};
+
+/*
+ * IRC
+ */
+
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+
+#define TX4938_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4938_NUM_PIO  16
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       0x0000020000000000ULL
+#define TX4938_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIARB      0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
+#define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
+#define TX4938_PCFG_ATA_SEL     0x2000000000000000ULL
+#define TX4938_PCFG_ISA_SEL     0x1000000000000000ULL
+#define TX4938_PCFG_SPI_SEL     0x0800000000000000ULL
+#define TX4938_PCFG_NDF_SEL     0x0400000000000000ULL
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
+#define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+
+#define tx4938_sdramcptr        tx4927_sdramcptr
+#define tx4938_ebuscptr         tx4927_ebuscptr
+#define tx4938_pcicptr          tx4927_pcicptr
+#define tx4938_pcic1ptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr \
+                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
+#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
+#define tx4938_sramcptr \
+                ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
+
+
+#define TX4938_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
+
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
+
+#define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
+#define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
+#define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
+
+#define TX4938_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
+#define TX4938_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
+#define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
+
+#define tx4938_get_mem_size() tx4927_get_mem_size()
+void tx4938_wdr_init(void);
+void tx4938_setup(void);
+void tx4938_time_init(unsigned int tmrnr);
+void tx4938_setup_serial(void);
+int tx4938_report_pciclk(void);
+void tx4938_report_pci1clk(void);
+int tx4938_pciclk66_setup(void);
+struct pci_dev;
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+void tx4938_irq_init(void);
+
+#endif
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/txx9/txx927.h
index 25dcf2feb095..97dd7ad1a890 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/txx9/txx927.h
@@ -7,8 +7,8 @@
  *
  * Copyright (C) 2000 Toshiba Corporation
  */
-#ifndef __ASM_TXX927_H
-#define __ASM_TXX927_H
+#ifndef __ASM_TXX9_TXX927_H
+#define __ASM_TXX9_TXX927_H
 
 struct txx927_sio_reg {
         volatile unsigned long lcr;
@@ -118,4 +118,4 @@ struct txx927_sio_reg {
  * PIO
  */
 
-#endif /* __ASM_TXX927_H */
+#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
deleted file mode 100644
index 42300037d593..000000000000
--- a/include/asm-mips/vr41xx/cmbvr4133.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * include/asm-mips/vr41xx/cmbvr4133.h
- *
- * Include file for NEC CMB-VR4133.
- *
- * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
- *         Jun Sun <jsun@mvista.com, or source@mvista.com> and
- *         Alex Sapkov <asapkov@ru.mvista.com>
- *
- * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __NEC_CMBVR4133_H
-#define __NEC_CMBVR4133_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define CMBVR41XX_INTA_PIN              1
-#define CMBVR41XX_INTB_PIN              1
-#define CMBVR41XX_INTC_PIN              3
-#define CMBVR41XX_INTD_PIN              1
-#define CMBVR41XX_INTE_PIN              1
-
-/*
- * Interrupt Number
- */
-#define CMBVR41XX_INTA_IRQ              GIU_IRQ(CMBVR41XX_INTA_PIN)
-#define CMBVR41XX_INTB_IRQ              GIU_IRQ(CMBVR41XX_INTB_PIN)
-#define CMBVR41XX_INTC_IRQ              GIU_IRQ(CMBVR41XX_INTC_PIN)
-#define CMBVR41XX_INTD_IRQ              GIU_IRQ(CMBVR41XX_INTD_PIN)
-#define CMBVR41XX_INTE_IRQ              GIU_IRQ(CMBVR41XX_INTE_PIN)
-
-#define I8259A_IRQ_BASE                 72
-#define I8259_IRQ(x)                    (I8259A_IRQ_BASE + (x))
-#define TIMER_IRQ                       I8259_IRQ(0)
-#define KEYBOARD_IRQ                    I8259_IRQ(1)
-#define I8259_SLAVE_IRQ                 I8259_IRQ(2)
-#define UART3_IRQ                       I8259_IRQ(3)
-#define UART1_IRQ                       I8259_IRQ(4)
-#define UART2_IRQ                       I8259_IRQ(5)
-#define FDC_IRQ                         I8259_IRQ(6)
-#define PARPORT_IRQ                     I8259_IRQ(7)
-#define RTC_IRQ                         I8259_IRQ(8)
-#define USB_IRQ                         I8259_IRQ(9)
-#define I8259_INTA_IRQ                  I8259_IRQ(10)
-#define AUDIO_IRQ                       I8259_IRQ(11)
-#define AUX_IRQ                         I8259_IRQ(12)
-#define IDE_PRIMARY_IRQ                 I8259_IRQ(14)
-#define IDE_SECONDARY_IRQ               I8259_IRQ(15)
-
-#endif /* __NEC_CMBVR4133_H */