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-rw-r--r--include/asm-mips/8253pit.h10
-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/asm.h8
-rw-r--r--include/asm-mips/bootinfo.h105
-rw-r--r--include/asm-mips/bugs.h25
-rw-r--r--include/asm-mips/cacheops.h2
-rw-r--r--include/asm-mips/cpu-features.h6
-rw-r--r--include/asm-mips/cpu-info.h6
-rw-r--r--include/asm-mips/cpu.h4
-rw-r--r--include/asm-mips/delay.h23
-rw-r--r--include/asm-mips/dma.h8
-rw-r--r--include/asm-mips/fixmap.h10
-rw-r--r--include/asm-mips/futex.h6
-rw-r--r--include/asm-mips/fw/cfe/cfe_api.h87
-rw-r--r--include/asm-mips/fw/cfe/cfe_error.h19
-rw-r--r--include/asm-mips/i8253.h17
-rw-r--r--include/asm-mips/ip32/ip32_ints.h4
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h9
-rw-r--r--include/asm-mips/jmr3927/tx3927.h4
-rw-r--r--include/asm-mips/jmr3927/txx927.h37
-rw-r--r--include/asm-mips/lasat/lasatint.h5
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h30
-rw-r--r--include/asm-mips/mach-au1x00/au1100_mmc.h7
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h1
-rw-r--r--include/asm-mips/mach-au1x00/timex.h13
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h15
-rw-r--r--include/asm-mips/mach-cobalt/irq.h3
-rw-r--r--include/asm-mips/mach-generic/timex.h13
-rw-r--r--include/asm-mips/mach-ip28/cpu-feature-overrides.h50
-rw-r--r--include/asm-mips/mach-ip28/ds1286.h4
-rw-r--r--include/asm-mips/mach-ip28/spaces.h22
-rw-r--r--include/asm-mips/mach-ip28/war.h (renamed from include/asm-mips/mach-qemu/war.h)8
-rw-r--r--include/asm-mips/mach-jazz/timex.h16
-rw-r--r--include/asm-mips/mach-lasat/irq.h13
-rw-r--r--include/asm-mips/mach-qemu/cpu-feature-overrides.h32
-rw-r--r--include/asm-mips/mach-qemu/timex.h16
-rw-r--r--include/asm-mips/mach-rm/timex.h13
-rw-r--r--include/asm-mips/mips-boards/generic.h6
-rw-r--r--include/asm-mips/mipsprom.h2
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regs.h4
-rw-r--r--include/asm-mips/r4kcache.h7
-rw-r--r--include/asm-mips/sgi/ioc.h4
-rw-r--r--include/asm-mips/sibyte/board.h6
-rw-r--r--include/asm-mips/sibyte/sb1250.h2
-rw-r--r--include/asm-mips/sibyte/swarm.h18
-rw-r--r--include/asm-mips/smp-ops.h56
-rw-r--r--include/asm-mips/smp.h64
-rw-r--r--include/asm-mips/smtc_ipi.h6
-rw-r--r--include/asm-mips/sni.h159
-rw-r--r--include/asm-mips/socket.h2
-rw-r--r--include/asm-mips/stackframe.h9
-rw-r--r--include/asm-mips/system.h10
-rw-r--r--include/asm-mips/time.h45
-rw-r--r--include/asm-mips/timex.h27
-rw-r--r--include/asm-mips/topology.h16
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h4
-rw-r--r--include/asm-mips/tx4938/tx4938.h1
-rw-r--r--include/asm-mips/txx9tmr.h67
-rw-r--r--include/asm-mips/uaccess.h13
-rw-r--r--include/asm-mips/war.h62
60 files changed, 592 insertions, 651 deletions
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f78488ccb..000000000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * 8253/8254 Programmable Interval Timer
3 */
4
5#ifndef _8253PIT_H
6#define _8253PIT_H
7
8#define PIT_TICK_RATE 1193182UL
9
10#endif
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 0bb7a93b7a5e..569f80aacbd2 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -127,7 +127,7 @@
127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
130 ((cm)<<59) | (a)) 130 (_CONST64_(cm) << 59) | (a))
131 131
132/* 132/*
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting 133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index 12e17581b823..608cfcfbb3ea 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -398,4 +398,12 @@ symbol = value
398 398
399#define SSNOP sll zero, zero, 1 399#define SSNOP sll zero, zero, 1
400 400
401#ifdef CONFIG_SGI_IP28
402/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
403#include <asm/cacheops.h>
404#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
405#else
406#define R10KCBARRIER(addr)
407#endif
408
401#endif /* __ASM_ASM_H */ 409#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b2dd9b33de8f..e031bdff9920 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -48,22 +48,11 @@
48#define MACH_DS5900 10 /* DECsystem 5900 */ 48#define MACH_DS5900 10 /* DECsystem 5900 */
49 49
50/* 50/*
51 * Valid machtype for group ARC
52 */
53#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */
54#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */
55
56/*
57 * Valid machtype for group SNI_RM 51 * Valid machtype for group SNI_RM
58 */ 52 */
59#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ 53#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
60 54
61/* 55/*
62 * Valid machtype for group ACN
63 */
64#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */
65
66/*
67 * Valid machtype for group SGI 56 * Valid machtype for group SGI
68 */ 57 */
69#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ 58#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
@@ -73,44 +62,6 @@
73#define MACH_SGI_IP30 4 /* Octane, Octane2 */ 62#define MACH_SGI_IP30 4 /* Octane, Octane2 */
74 63
75/* 64/*
76 * Valid machtype for group COBALT
77 */
78#define MACH_COBALT_27 0 /* Proto "27" hardware */
79
80/*
81 * Valid machtype for group BAGET
82 */
83#define MACH_BAGET201 0 /* BT23-201 */
84#define MACH_BAGET202 1 /* BT23-202 */
85
86/*
87 * Cosine boards.
88 */
89#define MACH_COSINE_ORION 0
90
91/*
92 * Valid machtype for group MOMENCO
93 */
94#define MACH_MOMENCO_OCELOT 0
95#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
96#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */
97#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
98#define MACH_MOMENCO_OCELOT_3 4
99
100/*
101 * Valid machtype for group PHILIPS
102 */
103#define MACH_PHILIPS_NINO 0 /* Nino */
104#define MACH_PHILIPS_VELO 1 /* Velo */
105#define MACH_PHILIPS_JBS 2 /* JBS */
106#define MACH_PHILIPS_STB810 3 /* STB810 */
107
108/*
109 * Valid machtype for group SIBYTE
110 */
111#define MACH_SWARM 0
112
113/*
114 * Valid machtypes for group Toshiba 65 * Valid machtypes for group Toshiba
115 */ 66 */
116#define MACH_PALLAS 0 67#define MACH_PALLAS 0
@@ -122,64 +73,17 @@
122#define MACH_TOSHIBA_RBTX4938 6 73#define MACH_TOSHIBA_RBTX4938 6
123 74
124/* 75/*
125 * Valid machtype for group Alchemy
126 */
127#define MACH_PB1000 0 /* Au1000-based eval board */
128#define MACH_PB1100 1 /* Au1100-based eval board */
129#define MACH_PB1500 2 /* Au1500-based eval board */
130#define MACH_DB1000 3 /* Au1000-based eval board */
131#define MACH_DB1100 4 /* Au1100-based eval board */
132#define MACH_DB1500 5 /* Au1500-based eval board */
133#define MACH_XXS1500 6 /* Au1500-based eval board */
134#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
135#define MACH_PB1550 8 /* Au1550-based eval board */
136#define MACH_DB1550 9 /* Au1550-based eval board */
137#define MACH_PB1200 10 /* Au1200-based eval board */
138#define MACH_DB1200 11 /* Au1200-based eval board */
139
140/*
141 * Valid machtype for group NEC_VR41XX
142 *
143 * Various NEC-based devices.
144 *
145 * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by
146 * technical properties, so no new additions to this group.
147 */
148#define MACH_NEC_OSPREY 0 /* Osprey eval board */
149#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */
150#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */
151#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */
152#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */
153#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */
154#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */
155#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
156#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */
157
158#define MACH_HP_LASERJET 1
159
160/*
161 * Valid machtype for group LASAT 76 * Valid machtype for group LASAT
162 */ 77 */
163#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ 78#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
164#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ 79#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
165 80
166/* 81/*
167 * Valid machtype for group TITAN
168 */
169#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
170#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
171
172/*
173 * Valid machtype for group NEC EMMA2RH 82 * Valid machtype for group NEC EMMA2RH
174 */ 83 */
175#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ 84#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
176 85
177/* 86/*
178 * Valid machtype for group LEMOTE
179 */
180#define MACH_LEMOTE_FULONG 0
181
182/*
183 * Valid machtype for group PMC-MSP 87 * Valid machtype for group PMC-MSP
184 */ 88 */
185#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ 89#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
@@ -190,16 +94,9 @@
190#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ 94#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
191#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ 95#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
192 96
193#define MACH_WRPPMC 1
194
195/*
196 * Valid machtype for group Broadcom
197 */
198#define MACH_GROUP_BRCM 23 /* Broadcom */
199#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
200
201#define CL_SIZE COMMAND_LINE_SIZE 97#define CL_SIZE COMMAND_LINE_SIZE
202 98
99extern char *system_type;
203const char *get_system_type(void); 100const char *get_system_type(void);
204 101
205extern unsigned long mips_machtype; 102extern unsigned long mips_machtype;
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index 0d7f9c1f5546..9dc10df32078 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -1,19 +1,34 @@
1/* 1/*
2 * This is included by init/main.c to check for architecture-dependent bugs. 2 * This is included by init/main.c to check for architecture-dependent bugs.
3 * 3 *
4 * Copyright (C) 2007 Maciej W. Rozycki
5 *
4 * Needs: 6 * Needs:
5 * void check_bugs(void); 7 * void check_bugs(void);
6 */ 8 */
7#ifndef _ASM_BUGS_H 9#ifndef _ASM_BUGS_H
8#define _ASM_BUGS_H 10#define _ASM_BUGS_H
9 11
12#include <linux/bug.h>
10#include <linux/delay.h> 13#include <linux/delay.h>
14
11#include <asm/cpu.h> 15#include <asm/cpu.h>
12#include <asm/cpu-info.h> 16#include <asm/cpu-info.h>
13 17
18extern int daddiu_bug;
19
20extern void check_bugs64_early(void);
21
14extern void check_bugs32(void); 22extern void check_bugs32(void);
15extern void check_bugs64(void); 23extern void check_bugs64(void);
16 24
25static inline void check_bugs_early(void)
26{
27#ifdef CONFIG_64BIT
28 check_bugs64_early();
29#endif
30}
31
17static inline void check_bugs(void) 32static inline void check_bugs(void)
18{ 33{
19 unsigned int cpu = smp_processor_id(); 34 unsigned int cpu = smp_processor_id();
@@ -25,4 +40,14 @@ static inline void check_bugs(void)
25#endif 40#endif
26} 41}
27 42
43static inline int r4k_daddiu_bug(void)
44{
45#ifdef CONFIG_64BIT
46 WARN_ON(daddiu_bug < 0);
47 return daddiu_bug != 0;
48#else
49 return 0;
50#endif
51}
52
28#endif /* _ASM_BUGS_H */ 53#endif /* _ASM_BUGS_H */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index df7f2deb3b56..256ad2cc6eb8 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -64,7 +64,7 @@
64#define Page_Invalidate_T 0x16 64#define Page_Invalidate_T 0x16
65 65
66/* 66/*
67 * R1000-specific cacheops 67 * R10000-specific cacheops
68 * 68 *
69 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 69 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
70 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 70 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index f6bd308f047f..5ea701fc3425 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -207,13 +207,13 @@
207#endif 207#endif
208 208
209#ifndef cpu_dcache_line_size 209#ifndef cpu_dcache_line_size
210#define cpu_dcache_line_size() current_cpu_data.dcache.linesz 210#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
211#endif 211#endif
212#ifndef cpu_icache_line_size 212#ifndef cpu_icache_line_size
213#define cpu_icache_line_size() current_cpu_data.icache.linesz 213#define cpu_icache_line_size() cpu_data[0].icache.linesz
214#endif 214#endif
215#ifndef cpu_scache_line_size 215#ifndef cpu_scache_line_size
216#define cpu_scache_line_size() current_cpu_data.scache.linesz 216#define cpu_scache_line_size() cpu_data[0].scache.linesz
217#endif 217#endif
218 218
219#endif /* __ASM_CPU_FEATURES_H */ 219#endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360..0c5a358863f3 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,8 @@ struct cpuinfo_mips {
54 struct cache_desc dcache; /* Primary D or combined I/D cache */ 54 struct cache_desc dcache; /* Primary D or combined I/D cache */
55 struct cache_desc scache; /* Secondary cache */ 55 struct cache_desc scache; /* Secondary cache */
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */
58 int core; /* physical core number */
57#if defined(CONFIG_MIPS_MT_SMTC) 59#if defined(CONFIG_MIPS_MT_SMTC)
58 /* 60 /*
59 * In the MIPS MT "SMTC" model, each TC is considered 61 * In the MIPS MT "SMTC" model, each TC is considered
@@ -62,8 +64,10 @@ struct cpuinfo_mips {
62 * to all TCs within the same VPE. 64 * to all TCs within the same VPE.
63 */ 65 */
64 int vpe_id; /* Virtual Processor number */ 66 int vpe_id; /* Virtual Processor number */
65 int tc_id; /* Thread Context number */
66#endif /* CONFIG_MIPS_MT */ 67#endif /* CONFIG_MIPS_MT */
68#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */
70#endif
67 void *data; /* Additional data */ 71 void *data; /* Additional data */
68} __attribute__((aligned(SMP_CACHE_BYTES))); 72} __attribute__((aligned(SMP_CACHE_BYTES)));
69 73
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 54fc18a4e5a8..bf5bbc78a9f7 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -195,8 +195,8 @@ enum cpu_type_enum {
195 * MIPS32 class processors 195 * MIPS32 class processors
196 */ 196 */
197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, 197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
198 CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, 198 CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
199 CPU_BCM3302, CPU_BCM4710, 199 CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
200 200
201 /* 201 /*
202 * MIPS64 class processors 202 * MIPS64 class processors
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index fab32131e9b4..b0bccd2c4ed5 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -6,13 +6,16 @@
6 * Copyright (C) 1994 by Waldorf Electronics 6 * Copyright (C) 1994 by Waldorf Electronics
7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle 7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
9 */ 10 */
10#ifndef _ASM_DELAY_H 11#ifndef _ASM_DELAY_H
11#define _ASM_DELAY_H 12#define _ASM_DELAY_H
12 13
13#include <linux/param.h> 14#include <linux/param.h>
14#include <linux/smp.h> 15#include <linux/smp.h>
16
15#include <asm/compiler.h> 17#include <asm/compiler.h>
18#include <asm/war.h>
16 19
17static inline void __delay(unsigned long loops) 20static inline void __delay(unsigned long loops)
18{ 21{
@@ -25,7 +28,7 @@ static inline void __delay(unsigned long loops)
25 " .set reorder \n" 28 " .set reorder \n"
26 : "=r" (loops) 29 : "=r" (loops)
27 : "0" (loops)); 30 : "0" (loops));
28 else if (sizeof(long) == 8) 31 else if (sizeof(long) == 8 && !DADDI_WAR)
29 __asm__ __volatile__ ( 32 __asm__ __volatile__ (
30 " .set noreorder \n" 33 " .set noreorder \n"
31 " .align 3 \n" 34 " .align 3 \n"
@@ -34,6 +37,15 @@ static inline void __delay(unsigned long loops)
34 " .set reorder \n" 37 " .set reorder \n"
35 : "=r" (loops) 38 : "=r" (loops)
36 : "0" (loops)); 39 : "0" (loops));
40 else if (sizeof(long) == 8 && DADDI_WAR)
41 __asm__ __volatile__ (
42 " .set noreorder \n"
43 " .align 3 \n"
44 "1: bnez %0, 1b \n"
45 " dsubu %0, %2 \n"
46 " .set reorder \n"
47 : "=r" (loops)
48 : "0" (loops), "r" (1));
37} 49}
38 50
39 51
@@ -50,7 +62,7 @@ static inline void __delay(unsigned long loops)
50 62
51static inline void __udelay(unsigned long usecs, unsigned long lpj) 63static inline void __udelay(unsigned long usecs, unsigned long lpj)
52{ 64{
53 unsigned long lo; 65 unsigned long hi, lo;
54 66
55 /* 67 /*
56 * The rates of 128 is rounded wrongly by the catchall case 68 * The rates of 128 is rounded wrongly by the catchall case
@@ -70,11 +82,16 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
70 : "=h" (usecs), "=l" (lo) 82 : "=h" (usecs), "=l" (lo)
71 : "r" (usecs), "r" (lpj) 83 : "r" (usecs), "r" (lpj)
72 : GCC_REG_ACCUM); 84 : GCC_REG_ACCUM);
73 else if (sizeof(long) == 8) 85 else if (sizeof(long) == 8 && !R4000_WAR)
74 __asm__("dmultu\t%2, %3" 86 __asm__("dmultu\t%2, %3"
75 : "=h" (usecs), "=l" (lo) 87 : "=h" (usecs), "=l" (lo)
76 : "r" (usecs), "r" (lpj) 88 : "r" (usecs), "r" (lpj)
77 : GCC_REG_ACCUM); 89 : GCC_REG_ACCUM);
90 else if (sizeof(long) == 8 && R4000_WAR)
91 __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
92 : "=r" (usecs), "=h" (hi), "=l" (lo)
93 : "r" (usecs), "r" (lpj)
94 : GCC_REG_ACCUM);
78 95
79 __delay(usecs); 96 __delay(usecs);
80} 97}
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d31ef1..1353c81065d1 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -84,14 +84,14 @@
84 * Deskstations or Acer PICA but not the much more versatile DMA logic used 84 * Deskstations or Acer PICA but not the much more versatile DMA logic used
85 * for the local devices on Acer PICA or Magnums. 85 * for the local devices on Acer PICA or Magnums.
86 */ 86 */
87#ifdef CONFIG_SGI_IP22 87#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
88/* Horrible hack to have a correct DMA window on IP22 */ 88/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
89#include <asm/sgi/mc.h> 89#define MAX_DMA_ADDRESS PAGE_OFFSET
90#define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
91#else 90#else
92#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) 91#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
93#endif 92#endif
94#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) 93#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
94#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
95 95
96/* 8237 DMA controllers */ 96/* 8237 DMA controllers */
97#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 97#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index f27b96cfac2e..9cc8522a394f 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -60,16 +60,6 @@ enum fixed_addresses {
60 __end_of_fixed_addresses 60 __end_of_fixed_addresses
61}; 61};
62 62
63extern void __set_fixmap(enum fixed_addresses idx,
64 unsigned long phys, pgprot_t flags);
65
66#define set_fixmap(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL)
68/*
69 * Some hardware wants to get fixmapped without caching.
70 */
71#define set_fixmap_nocache(idx, phys) \
72 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
73/* 63/*
74 * used by vmalloc.c. 64 * used by vmalloc.c.
75 * 65 *
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d4f418..17f082cfea85 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
35 " .set mips0 \n" \ 35 " .set mips0 \n" \
36 " .section .fixup,\"ax\" \n" \ 36 " .section .fixup,\"ax\" \n" \
37 "4: li %0, %6 \n" \ 37 "4: li %0, %6 \n" \
38 " j 2b \n" \ 38 " j 3b \n" \
39 " .previous \n" \ 39 " .previous \n" \
40 " .section __ex_table,\"a\" \n" \ 40 " .section __ex_table,\"a\" \n" \
41 " "__UA_ADDR "\t1b, 4b \n" \ 41 " "__UA_ADDR "\t1b, 4b \n" \
@@ -61,7 +61,7 @@
61 " .set mips0 \n" \ 61 " .set mips0 \n" \
62 " .section .fixup,\"ax\" \n" \ 62 " .section .fixup,\"ax\" \n" \
63 "4: li %0, %6 \n" \ 63 "4: li %0, %6 \n" \
64 " j 2b \n" \ 64 " j 3b \n" \
65 " .previous \n" \ 65 " .previous \n" \
66 " .section __ex_table,\"a\" \n" \ 66 " .section __ex_table,\"a\" \n" \
67 " "__UA_ADDR "\t1b, 4b \n" \ 67 " "__UA_ADDR "\t1b, 4b \n" \
@@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
200} 200}
201 201
202#endif 202#endif
203#endif 203#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h
index 1003e7156bfc..0995575db320 100644
--- a/include/asm-mips/fw/cfe/cfe_api.h
+++ b/include/asm-mips/fw/cfe/cfe_api.h
@@ -15,49 +15,27 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18/*
19/* ********************************************************************* 19 * Broadcom Common Firmware Environment (CFE)
20 * 20 *
21 * Broadcom Common Firmware Environment (CFE) 21 * This file contains declarations for doing callbacks to
22 * 22 * cfe from an application. It should be the only header
23 * Device function prototypes File: cfe_api.h 23 * needed by the application to use this library
24 * 24 *
25 * This file contains declarations for doing callbacks to 25 * Authors: Mitch Lichtenberg, Chris Demetriou
26 * cfe from an application. It should be the only header 26 */
27 * needed by the application to use this library
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_H 27#ifndef CFE_API_H
34#define CFE_API_H 28#define CFE_API_H
35 29
36/*
37 * Apply customizations here for different OSes. These need to:
38 * * typedef uint64_t, int64_t, intptr_t, uintptr_t.
39 * * define cfe_strlen() if use of an existing function is desired.
40 * * define CFE_API_IMPL_NAMESPACE if API functions are to use
41 * names in the implementation namespace.
42 * Also, optionally, if the build environment does not do so automatically,
43 * CFE_API_* can be defined here as desired.
44 */
45/* Begin customization. */
46#include <linux/types.h> 30#include <linux/types.h>
47#include <linux/string.h> 31#include <linux/string.h>
48 32
49typedef long intptr_t; 33typedef long intptr_t;
50 34
51#define cfe_strlen strlen
52 35
53#define CFE_API_ALL 36/*
54#define CFE_API_STRLEN_CUSTOM 37 * Constants
55/* End customization. */ 38 */
56
57
58/* *********************************************************************
59 * Constants
60 ********************************************************************* */
61 39
62/* Seal indicating CFE's presence, passed to user program. */ 40/* Seal indicating CFE's presence, passed to user program. */
63#define CFE_EPTSEAL 0x43464531 41#define CFE_EPTSEAL 0x43464531
@@ -109,54 +87,13 @@ typedef struct {
109 87
110 88
111/* 89/*
112 * cfe_strlen is handled specially: If already defined, it has been
113 * overridden in this environment with a standard strlen-like function.
114 */
115#ifdef cfe_strlen
116# define CFE_API_STRLEN_CUSTOM
117#else
118# ifdef CFE_API_IMPL_NAMESPACE
119# define cfe_strlen(a) __cfe_strlen(a)
120# endif
121int cfe_strlen(char *name);
122#endif
123
124/*
125 * Defines and prototypes for functions which take no arguments. 90 * Defines and prototypes for functions which take no arguments.
126 */ 91 */
127#ifdef CFE_API_IMPL_NAMESPACE
128int64_t __cfe_getticks(void);
129#define cfe_getticks() __cfe_getticks()
130#else
131int64_t cfe_getticks(void); 92int64_t cfe_getticks(void);
132#endif
133 93
134/* 94/*
135 * Defines and prototypes for the rest of the functions. 95 * Defines and prototypes for the rest of the functions.
136 */ 96 */
137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f)
142#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e)
143#define cfe_exit(a, b) __cfe_exit(a, b)
144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a, b) __cfe_init(a, b)
150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f)
152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a, b, c) __cfe_read(a, b, c)
154#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d)
155#define cfe_setenv(a, b) __cfe_setenv(a, b)
156#define cfe_write(a, b, c) __cfe_write(a, b, c)
157#define cfe_writeblk(a, b, c, d) __cfe_writeblk(a, b, c, d)
158#endif /* CFE_API_IMPL_NAMESPACE */
159
160int cfe_close(int handle); 97int cfe_close(int handle);
161int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); 98int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
162int cfe_cpu_stop(int cpu); 99int cfe_cpu_stop(int cpu);
diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h
index 975f00002cbe..b80374636279 100644
--- a/include/asm-mips/fw/cfe/cfe_error.h
+++ b/include/asm-mips/fw/cfe/cfe_error.h
@@ -16,18 +16,13 @@
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18
19/* ********************************************************************* 19/*
20 * 20 * Broadcom Common Firmware Environment (CFE)
21 * Broadcom Common Firmware Environment (CFE) 21 *
22 * 22 * CFE's global error code list is here.
23 * Error codes File: cfe_error.h 23 *
24 * 24 * Author: Mitch Lichtenberg
25 * CFE's global error code list is here. 25 */
26 *
27 * Author: Mitch Lichtenberg
28 *
29 ********************************************************************* */
30
31 26
32#define CFE_OK 0 27#define CFE_OK 0
33#define CFE_ERR -1 /* generic error */ 28#define CFE_ERR -1 /* generic error */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index affb32ce4af9..5dabc870b322 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -5,25 +5,16 @@
5#ifndef __ASM_I8253_H 5#ifndef __ASM_I8253_H
6#define __ASM_I8253_H 6#define __ASM_I8253_H
7 7
8#include <linux/spinlock.h>
9
8/* i8253A PIT registers */ 10/* i8253A PIT registers */
9#define PIT_MODE 0x43 11#define PIT_MODE 0x43
10#define PIT_CH0 0x40 12#define PIT_CH0 0x40
11#define PIT_CH2 0x42 13#define PIT_CH2 0x42
12 14
13/* i8259A PIC registers */ 15#define PIT_TICK_RATE 1193182UL
14#define PIC_MASTER_CMD 0x20
15#define PIC_MASTER_IMR 0x21
16#define PIC_MASTER_ISR PIC_MASTER_CMD
17#define PIC_MASTER_POLL PIC_MASTER_ISR
18#define PIC_MASTER_OCW3 PIC_MASTER_ISR
19#define PIC_SLAVE_CMD 0xa0
20#define PIC_SLAVE_IMR 0xa1
21 16
22/* i8259A PIC related value */ 17extern spinlock_t i8253_lock;
23#define PIC_CASCADE_IR 2
24#define MASTER_ICW4_DEFAULT 0x01
25#define SLAVE_ICW4_DEFAULT 0x01
26#define PIC_ICW4_AEOI 2
27 18
28extern void setup_pit_timer(void); 19extern void setup_pit_timer(void);
29 20
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index 042f821899a8..85bc5302bce0 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,10 +22,12 @@ enum ip32_irq_no {
22 * CPU interrupts are 0 ... 7 22 * CPU interrupts are 0 ... 7
23 */ 23 */
24 24
25 CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
26
25 /* 27 /*
26 * MACE 28 * MACE
27 */ 29 */
28 MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8, 30 MACE_VID_IN1_IRQ = CRIME_IRQ_BASE,
29 MACE_VID_IN2_IRQ, 31 MACE_VID_IN2_IRQ,
30 MACE_VID_OUT_IRQ, 32 MACE_VID_OUT_IRQ,
31 MACE_ETHERNET_IRQ, 33 MACE_ETHERNET_IRQ,
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index b2dc35f56181..81602c8047eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -132,9 +132,7 @@
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) 132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) 133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) 134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) 135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
137#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
138#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) 136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
139#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) 137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
140#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) 138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
@@ -148,17 +146,12 @@
148#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
149/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ 147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
150#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
151/* Clock Tick (10ms) */
152#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
153 149
154/* Clocks */ 150/* Clocks */
155#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
156#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ 152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
157#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ 153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
158 154
159#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
160
161
162/* 155/*
163 * TX3927 Pin Configuration: 156 * TX3927 Pin Configuration:
164 * 157 *
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 211bcf47fffb..338f99882a39 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -222,9 +222,7 @@ struct tx3927_ccfg_reg {
222#define TX3927_IR_DMA 8 222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9 223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10 224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR0 13 225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_IR_TMR1 14
227#define TX3927_IR_TMR2 15
228#define TX3927_NUM_IR 16 226#define TX3927_NUM_IR 16
229 227
230/* 228/*
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
index 58a8ff6be815..0474fe8dac3f 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -10,22 +10,6 @@
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX927_H
12 12
13struct txx927_tmr_reg {
14 volatile unsigned long tcr;
15 volatile unsigned long tisr;
16 volatile unsigned long cpra;
17 volatile unsigned long cprb;
18 volatile unsigned long itmr;
19 volatile unsigned long unused0[3];
20 volatile unsigned long ccdr;
21 volatile unsigned long unused1[3];
22 volatile unsigned long pgmr;
23 volatile unsigned long unused2[3];
24 volatile unsigned long wtmr;
25 volatile unsigned long unused3[43];
26 volatile unsigned long trr;
27};
28
29struct txx927_sio_reg { 13struct txx927_sio_reg {
30 volatile unsigned long lcr; 14 volatile unsigned long lcr;
31 volatile unsigned long dicr; 15 volatile unsigned long dicr;
@@ -51,27 +35,6 @@ struct txx927_pio_reg {
51}; 35};
52 36
53/* 37/*
54 * TMR
55 */
56/* TMTCR : Timer Control */
57#define TXx927_TMTCR_TCE 0x00000080
58#define TXx927_TMTCR_CCDE 0x00000040
59#define TXx927_TMTCR_CRE 0x00000020
60#define TXx927_TMTCR_ECES 0x00000008
61#define TXx927_TMTCR_CCS 0x00000004
62#define TXx927_TMTCR_TMODE_MASK 0x00000003
63#define TXx927_TMTCR_TMODE_ITVL 0x00000000
64
65/* TMTISR : Timer Int. Status */
66#define TXx927_TMTISR_TPIBS 0x00000004
67#define TXx927_TMTISR_TPIAS 0x00000002
68#define TXx927_TMTISR_TIIS 0x00000001
69
70/* TMTITMR : Interval Timer Mode */
71#define TXx927_TMTITMR_TIIE 0x00008000
72#define TXx927_TMTITMR_TZCE 0x00000001
73
74/*
75 * SIO 38 * SIO
76 */ 39 */
77/* SILCR : Line Control */ 40/* SILCR : Line Control */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
index 581dc45685a2..e0d2458b43d0 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/include/asm-mips/lasat/lasatint.h
@@ -1,11 +1,6 @@
1#ifndef __ASM_LASAT_LASATINT_H 1#ifndef __ASM_LASAT_LASATINT_H
2#define __ASM_LASAT_LASATINT_H 2#define __ASM_LASAT_LASATINT_H
3 3
4#include <linux/irq.h>
5
6#define LASATINT_BASE MIPS_CPU_IRQ_BASE
7#define LASATINT_END (LASATINT_BASE + 16)
8
9/* lasat 100 */ 4/* lasat 100 */
10#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) 5#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
11#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) 6#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 3bdce9126f16..cb18af989645 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -526,7 +526,7 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
526/* Au1000 */ 526/* Au1000 */
527#ifdef CONFIG_SOC_AU1000 527#ifdef CONFIG_SOC_AU1000
528enum soc_au1000_ints { 528enum soc_au1000_ints {
529 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE, 529 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
530 AU1000_UART0_INT = AU1000_FIRST_INT, 530 AU1000_UART0_INT = AU1000_FIRST_INT,
531 AU1000_UART1_INT, /* au1000 */ 531 AU1000_UART1_INT, /* au1000 */
532 AU1000_UART2_INT, /* au1000 */ 532 AU1000_UART2_INT, /* au1000 */
@@ -605,7 +605,7 @@ enum soc_au1000_ints {
605/* Au1500 */ 605/* Au1500 */
606#ifdef CONFIG_SOC_AU1500 606#ifdef CONFIG_SOC_AU1500
607enum soc_au1500_ints { 607enum soc_au1500_ints {
608 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE, 608 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
609 AU1500_UART0_INT = AU1500_FIRST_INT, 609 AU1500_UART0_INT = AU1500_FIRST_INT,
610 AU1000_PCI_INTA, /* au1500 */ 610 AU1000_PCI_INTA, /* au1500 */
611 AU1000_PCI_INTB, /* au1500 */ 611 AU1000_PCI_INTB, /* au1500 */
@@ -686,7 +686,7 @@ enum soc_au1500_ints {
686/* Au1100 */ 686/* Au1100 */
687#ifdef CONFIG_SOC_AU1100 687#ifdef CONFIG_SOC_AU1100
688enum soc_au1100_ints { 688enum soc_au1100_ints {
689 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE, 689 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
690 AU1100_UART0_INT, 690 AU1100_UART0_INT,
691 AU1100_UART1_INT, 691 AU1100_UART1_INT,
692 AU1100_SD_INT, 692 AU1100_SD_INT,
@@ -761,7 +761,7 @@ enum soc_au1100_ints {
761 761
762#ifdef CONFIG_SOC_AU1550 762#ifdef CONFIG_SOC_AU1550
763enum soc_au1550_ints { 763enum soc_au1550_ints {
764 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE, 764 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
765 AU1550_UART0_INT = AU1550_FIRST_INT, 765 AU1550_UART0_INT = AU1550_FIRST_INT,
766 AU1550_PCI_INTA, 766 AU1550_PCI_INTA,
767 AU1550_PCI_INTB, 767 AU1550_PCI_INTB,
@@ -851,7 +851,7 @@ enum soc_au1550_ints {
851 851
852#ifdef CONFIG_SOC_AU1200 852#ifdef CONFIG_SOC_AU1200
853enum soc_au1200_ints { 853enum soc_au1200_ints {
854 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE, 854 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
855 AU1200_UART0_INT = AU1200_FIRST_INT, 855 AU1200_UART0_INT = AU1200_FIRST_INT,
856 AU1200_SWT_INT, 856 AU1200_SWT_INT,
857 AU1200_SD_INT, 857 AU1200_SD_INT,
@@ -948,11 +948,12 @@ enum soc_au1200_ints {
948 948
949#endif /* CONFIG_SOC_AU1200 */ 949#endif /* CONFIG_SOC_AU1200 */
950 950
951#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0) 951#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
952#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31) 952#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
953#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32) 953#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
954#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63) 954#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
955#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63) 955
956#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
956#define INTX 0xFF /* not valid */ 957#define INTX 0xFF /* not valid */
957 958
958/* Programmable Counters 0 and 1 */ 959/* Programmable Counters 0 and 1 */
@@ -1679,10 +1680,11 @@ enum soc_au1200_ints {
1679#define Au1500_PCI_MEM_START 0x440000000ULL 1680#define Au1500_PCI_MEM_START 0x440000000ULL
1680#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1681#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1681 1682
1682#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) 1683#define PCI_IO_START 0x00001000
1683#define PCI_IO_END (Au1500_PCI_IO_END) 1684#define PCI_IO_END 0x000FFFFF
1684#define PCI_MEM_START (Au1500_PCI_MEM_START) 1685#define PCI_MEM_START 0x40000000
1685#define PCI_MEM_END (Au1500_PCI_MEM_END) 1686#define PCI_MEM_END 0x4FFFFFFF
1687
1686#define PCI_FIRST_DEVFN (0<<3) 1688#define PCI_FIRST_DEVFN (0<<3)
1687#define PCI_LAST_DEVFN (19<<3) 1689#define PCI_LAST_DEVFN (19<<3)
1688 1690
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
index 9e7d1ba21b55..9e0028f60a43 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -41,8 +41,11 @@
41 41
42#define NUM_AU1100_MMC_CONTROLLERS 2 42#define NUM_AU1100_MMC_CONTROLLERS 2
43 43
44 44#if defined(CONFIG_SOC_AU1100)
45#define AU1100_SD_IRQ 2 45#define AU1100_SD_IRQ AU1100_SD_INT
46#elif defined(CONFIG_SOC_AU1200)
47#define AU1100_SD_IRQ AU1200_SD_INT
48#endif
46 49
47 50
48#define SD0_BASE 0xB0600000 51#define SD0_BASE 0xB0600000
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index aef0edbfe4c6..e4fe26c160ba 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -74,7 +74,6 @@ typedef struct
74 struct dbdma_cmd *dma_table_cpu; 74 struct dbdma_cmd *dma_table_cpu;
75 dma_addr_t dma_table_dma; 75 dma_addr_t dma_table_dma;
76#endif 76#endif
77 struct device *dev;
78 int irq; 77 int irq;
79 u32 regbase; 78 u32 regbase;
80#ifdef CONFIG_PM 79#ifdef CONFIG_PM
diff --git a/include/asm-mips/mach-au1x00/timex.h b/include/asm-mips/mach-au1x00/timex.h
deleted file mode 100644
index e3ada66cb636..000000000000
--- a/include/asm-mips/mach-au1x00/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_AU1X00_TIMEX_H
9#define __ASM_MACH_AU1X00_TIMEX_H
10
11#define CLOCK_TICK_RATE ((HZ * 100000UL) / 2)
12
13#endif /* __ASM_MACH_AU1X00_TIMEX_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index a79e7caf3a86..5b9fce73f11d 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Lowlevel hardware stuff for the MIPS based Cobalt microservers. 2 * The Cobalt board ID information.
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
@@ -12,9 +12,6 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15/*
16 * The Cobalt board ID information.
17 */
18extern int cobalt_board_id; 15extern int cobalt_board_id;
19 16
20#define COBALT_BRD_ID_QUBE1 0x3 17#define COBALT_BRD_ID_QUBE1 0x3
@@ -22,14 +19,4 @@ extern int cobalt_board_id;
22#define COBALT_BRD_ID_QUBE2 0x5 19#define COBALT_BRD_ID_QUBE2 0x5
23#define COBALT_BRD_ID_RAQ2 0x6 20#define COBALT_BRD_ID_RAQ2 0x6
24 21
25#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
26# define COBALT_KEY_CLEAR (1 << 1)
27# define COBALT_KEY_LEFT (1 << 2)
28# define COBALT_KEY_UP (1 << 3)
29# define COBALT_KEY_DOWN (1 << 4)
30# define COBALT_KEY_RIGHT (1 << 5)
31# define COBALT_KEY_ENTER (1 << 6)
32# define COBALT_KEY_SELECT (1 << 7)
33# define COBALT_KEY_MASK 0xfe
34
35#endif /* __ASM_COBALT_H */ 22#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
index 179d0e850b59..57c8c9ac5851 100644
--- a/include/asm-mips/mach-cobalt/irq.h
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -35,7 +35,7 @@
35 * 4 - ethernet 35 * 4 - ethernet
36 * 5 - 16550 UART 36 * 5 - 16550 UART
37 * 6 - cascade i8259 37 * 6 - cascade i8259
38 * 7 - CP0 counter (unused) 38 * 7 - CP0 counter
39 */ 39 */
40#define MIPS_CPU_IRQ_BASE 16 40#define MIPS_CPU_IRQ_BASE 16
41 41
@@ -48,7 +48,6 @@
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) 48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) 49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50 50
51
52#define GT641XX_IRQ_BASE 24 51#define GT641XX_IRQ_BASE 24
53 52
54#include <asm/irq_gt641xx.h> 53#include <asm/irq_gt641xx.h>
diff --git a/include/asm-mips/mach-generic/timex.h b/include/asm-mips/mach-generic/timex.h
deleted file mode 100644
index 48b4cfaa0d50..000000000000
--- a/include/asm-mips/mach-generic/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2005 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_TIMEX_H
9#define __ASM_MACH_GENERIC_TIMEX_H
10
11#define CLOCK_TICK_RATE 500000
12
13#endif /* __ASM_MACH_GENERIC_TIMEX_H */
diff --git a/include/asm-mips/mach-ip28/cpu-feature-overrides.h b/include/asm-mips/mach-ip28/cpu-feature-overrides.h
new file mode 100644
index 000000000000..9a53b326f848
--- /dev/null
+++ b/include/asm-mips/mach-ip28/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 * 6/2004 pf
8 */
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * IP28 only comes with R10000 family processors all using the same config
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 /* see probe_pcache() */
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 1
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_4kex 1
38#define cpu_has_4k_cache 1
39
40#define cpu_has_inclusive_pcaches 1
41
42#define cpu_dcache_line_size() 32
43#define cpu_icache_line_size() 64
44
45#define cpu_has_mips32r1 0
46#define cpu_has_mips32r2 0
47#define cpu_has_mips64r1 0
48#define cpu_has_mips64r2 0
49
50#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h
new file mode 100644
index 000000000000..471bb9a33e0f
--- /dev/null
+++ b/include/asm-mips/mach-ip28/ds1286.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_MACH_IP28_DS1286_H
2#define __ASM_MACH_IP28_DS1286_H
3#include <asm/mach-ip22/ds1286.h>
4#endif /* __ASM_MACH_IP28_DS1286_H */
diff --git a/include/asm-mips/mach-ip28/spaces.h b/include/asm-mips/mach-ip28/spaces.h
new file mode 100644
index 000000000000..05aabb27e5e7
--- /dev/null
+++ b/include/asm-mips/mach-ip28/spaces.h
@@ -0,0 +1,22 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
9 * 2004 pf
10 */
11#ifndef _ASM_MACH_IP28_SPACES_H
12#define _ASM_MACH_IP28_SPACES_H
13
14#define CAC_BASE 0xa800000000000000
15
16#define HIGHMEM_START (~0UL)
17
18#define PHYS_OFFSET _AC(0x20000000, UL)
19
20#include <asm/mach-generic/spaces.h>
21
22#endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-ip28/war.h
index 0eaf0c548a47..a1baafab486a 100644
--- a/include/asm-mips/mach-qemu/war.h
+++ b/include/asm-mips/mach-ip28/war.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */ 7 */
8#ifndef __ASM_MIPS_MACH_QEMU_WAR_H 8#ifndef __ASM_MIPS_MACH_IP28_WAR_H
9#define __ASM_MIPS_MACH_QEMU_WAR_H 9#define __ASM_MIPS_MACH_IP28_WAR_H
10 10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 12#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -19,7 +19,7 @@
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0 20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
24 24
25#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ 25#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/include/asm-mips/mach-jazz/timex.h b/include/asm-mips/mach-jazz/timex.h
deleted file mode 100644
index 93affa33dfa8..000000000000
--- a/include/asm-mips/mach-jazz/timex.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_JAZZ_TIMEX_H
9#define __ASM_MACH_JAZZ_TIMEX_H
10
11/*
12 * Jazz is still using the R4030 100Hz counter
13 */
14#define CLOCK_TICK_RATE 100
15
16#endif /* __ASM_MACH_JAZZ_TIMEX_H */
diff --git a/include/asm-mips/mach-lasat/irq.h b/include/asm-mips/mach-lasat/irq.h
new file mode 100644
index 000000000000..da75f89f3723
--- /dev/null
+++ b/include/asm-mips/mach-lasat/irq.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_MACH_LASAT_IRQ_H
2#define _ASM_MACH_LASAT_IRQ_H
3
4#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 0)
5
6#define LASAT_IRQ_BASE 8
7#define LASAT_IRQ_END 23
8
9#define NR_IRQS 24
10
11#include_next <irq.h>
12
13#endif /* _ASM_MACH_LASAT_IRQ_H */
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
deleted file mode 100644
index d2daaed235d5..000000000000
--- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 07 Ralf Baechle
7 */
8#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
13 */
14#define cpu_has_mips16 0
15#define cpu_has_divec 0
16#define cpu_has_cache_cdex_p 0
17#define cpu_has_prefetch 0
18#define cpu_has_mcheck 0
19#define cpu_has_ejtag 0
20
21#define cpu_has_llsc 1
22#define cpu_has_vtag_icache 0
23#define cpu_has_dc_aliases 0
24#define cpu_has_ic_fills_f_dc 0
25
26#define cpu_has_dsp 0
27#define cpu_has_mipsmt 0
28
29#define cpu_has_nofpuex 0
30#define cpu_has_64bits 0
31
32#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-qemu/timex.h b/include/asm-mips/mach-qemu/timex.h
deleted file mode 100644
index cd543693fb0a..000000000000
--- a/include/asm-mips/mach-qemu/timex.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Daniel Jacobowitz
7 */
8#ifndef __ASM_MACH_QEMU_TIMEX_H
9#define __ASM_MACH_QEMU_TIMEX_H
10
11/*
12 * We use a simulated i8254 PIC...
13 */
14#define CLOCK_TICK_RATE 1193182
15
16#endif /* __ASM_MACH_QEMU_TIMEX_H */
diff --git a/include/asm-mips/mach-rm/timex.h b/include/asm-mips/mach-rm/timex.h
deleted file mode 100644
index 11ff6cb0f214..000000000000
--- a/include/asm-mips/mach-rm/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2005 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_RM200_TIMEX_H
9#define __ASM_MACH_RM200_TIMEX_H
10
11#define CLOCK_TICK_RATE 1193182
12
13#endif /* __ASM_MACH_RM200_TIMEX_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index d58977483534..1c39d339521e 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -97,10 +97,16 @@ extern int mips_revision_corid;
97 97
98extern int mips_revision_sconid; 98extern int mips_revision_sconid;
99 99
100extern void mips_reboot_setup(void);
101
100#ifdef CONFIG_PCI 102#ifdef CONFIG_PCI
101extern void mips_pcibios_init(void); 103extern void mips_pcibios_init(void);
102#else 104#else
103#define mips_pcibios_init() do { } while (0) 105#define mips_pcibios_init() do { } while (0)
104#endif 106#endif
105 107
108#ifdef CONFIG_KGDB
109extern void kgdb_config(void);
110#endif
111
106#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 112#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
index ce7cff7f1e8e..146d41b67adc 100644
--- a/include/asm-mips/mipsprom.h
+++ b/include/asm-mips/mipsprom.h
@@ -71,4 +71,6 @@
71#define PROM_NV_GET 53 /* XXX */ 71#define PROM_NV_GET 53 /* XXX */
72#define PROM_NV_SET 54 /* XXX */ 72#define PROM_NV_SET 54 /* XXX */
73 73
74extern char *prom_getenv(char *);
75
74#endif /* __ASM_MIPS_PROM_H */ 76#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
index 0b56f55206c6..603eb737b4a8 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -585,11 +585,7 @@
585 * UART defines * 585 * UART defines *
586 *************************************************************************** 586 ***************************************************************************
587 */ 587 */
588#ifndef CONFIG_MSP_FPGA
589#define MSP_BASE_BAUD 25000000 588#define MSP_BASE_BAUD 25000000
590#else
591#define MSP_BASE_BAUD 6000000
592#endif
593#define MSP_UART_REG_LEN 0x20 589#define MSP_UART_REG_LEN 0x20
594 590
595/* 591/*
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 2b8466ffd3ca..4c140db36786 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -403,6 +403,13 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) 403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) 404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
405 405
406__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
407__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
408__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
409__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
410__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
411__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
412
406/* build blast_xxx_range, protected_blast_xxx_range */ 413/* build blast_xxx_range, protected_blast_xxx_range */
407#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 414#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
408static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 415static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index f3e3dc9bb732..343ed15f8dc4 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -138,8 +138,8 @@ struct sgioc_regs {
138 u8 _sysid[3]; 138 u8 _sysid[3];
139 volatile u8 sysid; 139 volatile u8 sysid;
140#define SGIOC_SYSID_FULLHOUSE 0x01 140#define SGIOC_SYSID_FULLHOUSE 0x01
141#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 141#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
142#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) 142#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
143 u32 _unused2; 143 u32 _unused2;
144 u8 _read[3]; 144 u8 _read[3];
145 volatile u8 read; 145 volatile u8 read;
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index da198a1c8c81..25372ae0e814 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -19,10 +19,8 @@
19#ifndef _SIBYTE_BOARD_H 19#ifndef _SIBYTE_BOARD_H
20#define _SIBYTE_BOARD_H 20#define _SIBYTE_BOARD_H
21 21
22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ 22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
23 defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \ 23 defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
25 defined(CONFIG_SIBYTE_LITTLESUR)
26#include <asm/sibyte/swarm.h> 24#include <asm/sibyte/swarm.h>
27#endif 25#endif
28 26
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index 0dad844a3b5b..80c1a052662a 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -48,12 +48,10 @@ extern unsigned int zbbus_mhz;
48extern void sb1250_time_init(void); 48extern void sb1250_time_init(void);
49extern void sb1250_mask_irq(int cpu, int irq); 49extern void sb1250_mask_irq(int cpu, int irq);
50extern void sb1250_unmask_irq(int cpu, int irq); 50extern void sb1250_unmask_irq(int cpu, int irq);
51extern void sb1250_smp_finish(void);
52 51
53extern void bcm1480_time_init(void); 52extern void bcm1480_time_init(void);
54extern void bcm1480_mask_irq(int cpu, int irq); 53extern void bcm1480_mask_irq(int cpu, int irq);
55extern void bcm1480_unmask_irq(int cpu, int irq); 54extern void bcm1480_unmask_irq(int cpu, int irq);
56extern void bcm1480_smp_finish(void);
57 55
58#define AT_spin \ 56#define AT_spin \
59 __asm__ __volatile__ ( \ 57 __asm__ __volatile__ ( \
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 540865fa7ec3..114d9d29ca9d 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -26,24 +26,6 @@
26#define SIBYTE_HAVE_PCMCIA 1 26#define SIBYTE_HAVE_PCMCIA 1
27#define SIBYTE_HAVE_IDE 1 27#define SIBYTE_HAVE_IDE 1
28#endif 28#endif
29#ifdef CONFIG_SIBYTE_PTSWARM
30#define SIBYTE_BOARD_NAME "PTSWARM"
31#define SIBYTE_HAVE_PCMCIA 1
32#define SIBYTE_HAVE_IDE 1
33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
34#endif
35#ifdef CONFIG_SIBYTE_PT1120
36#define SIBYTE_BOARD_NAME "PT1120"
37#define SIBYTE_HAVE_PCMCIA 1
38#define SIBYTE_HAVE_IDE 1
39#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
40#endif
41#ifdef CONFIG_SIBYTE_PT1125
42#define SIBYTE_BOARD_NAME "PT1125"
43#define SIBYTE_HAVE_PCMCIA 1
44#define SIBYTE_HAVE_IDE 1
45#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
46#endif
47#ifdef CONFIG_SIBYTE_LITTLESUR 29#ifdef CONFIG_SIBYTE_LITTLESUR
48#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" 30#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
49#define SIBYTE_HAVE_PCMCIA 0 31#define SIBYTE_HAVE_PCMCIA 0
diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h
new file mode 100644
index 000000000000..b17fdfb5d818
--- /dev/null
+++ b/include/asm-mips/smp-ops.h
@@ -0,0 +1,56 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General
3 * Public License. See the file "COPYING" in the main directory of this
4 * archive for more details.
5 *
6 * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
7 * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
8 * Copyright (C) 2000, 2001, 2002 Ralf Baechle
9 * Copyright (C) 2000, 2001 Broadcom Corporation
10 */
11#ifndef __ASM_SMP_OPS_H
12#define __ASM_SMP_OPS_H
13
14#ifdef CONFIG_SMP
15
16#include <linux/cpumask.h>
17
18struct plat_smp_ops {
19 void (*send_ipi_single)(int cpu, unsigned int action);
20 void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
21 void (*init_secondary)(void);
22 void (*smp_finish)(void);
23 void (*cpus_done)(void);
24 void (*boot_secondary)(int cpu, struct task_struct *idle);
25 void (*smp_setup)(void);
26 void (*prepare_cpus)(unsigned int max_cpus);
27};
28
29extern void register_smp_ops(struct plat_smp_ops *ops);
30
31static inline void plat_smp_setup(void)
32{
33 extern struct plat_smp_ops *mp_ops; /* private */
34
35 mp_ops->smp_setup();
36}
37
38#else /* !CONFIG_SMP */
39
40struct plat_smp_ops;
41
42static inline void plat_smp_setup(void)
43{
44 /* UP, nothing to do ... */
45}
46
47static inline void register_smp_ops(struct plat_smp_ops *ops)
48{
49}
50
51#endif /* !CONFIG_SMP */
52
53extern struct plat_smp_ops up_smp_ops;
54extern struct plat_smp_ops vsmp_smp_ops;
55
56#endif /* __ASM_SMP_OPS_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index dc770025a9b0..84fef1aeec0c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -11,14 +11,16 @@
11#ifndef __ASM_SMP_H 11#ifndef __ASM_SMP_H
12#define __ASM_SMP_H 12#define __ASM_SMP_H
13 13
14
15#ifdef CONFIG_SMP
16
17#include <linux/bitops.h> 14#include <linux/bitops.h>
18#include <linux/linkage.h> 15#include <linux/linkage.h>
19#include <linux/threads.h> 16#include <linux/threads.h>
20#include <linux/cpumask.h> 17#include <linux/cpumask.h>
18
21#include <asm/atomic.h> 19#include <asm/atomic.h>
20#include <asm/smp-ops.h>
21
22extern int smp_num_siblings;
23extern cpumask_t cpu_sibling_map[];
22 24
23#define raw_smp_processor_id() (current_thread_info()->cpu) 25#define raw_smp_processor_id() (current_thread_info()->cpu)
24 26
@@ -49,56 +51,6 @@ extern struct call_data_struct *call_data;
49extern cpumask_t phys_cpu_present_map; 51extern cpumask_t phys_cpu_present_map;
50#define cpu_possible_map phys_cpu_present_map 52#define cpu_possible_map phys_cpu_present_map
51 53
52/*
53 * These are defined by the board-specific code.
54 */
55
56/*
57 * Cause the function described by call_data to be executed on the passed
58 * cpu. When the function has finished, increment the finished field of
59 * call_data.
60 */
61extern void core_send_ipi(int cpu, unsigned int action);
62
63static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action)
64{
65 unsigned int i;
66
67 for_each_cpu_mask(i, mask)
68 core_send_ipi(i, action);
69}
70
71
72/*
73 * Firmware CPU startup hook
74 */
75extern void prom_boot_secondary(int cpu, struct task_struct *idle);
76
77/*
78 * After we've done initial boot, this function is called to allow the
79 * board code to clean up state, if needed
80 */
81extern void prom_init_secondary(void);
82
83/*
84 * Populate cpu_possible_map before smp_init, called from setup_arch.
85 */
86extern void plat_smp_setup(void);
87
88/*
89 * Called in smp_prepare_cpus.
90 */
91extern void plat_prepare_cpus(unsigned int max_cpus);
92
93/*
94 * Last chance for the board code to finish SMP initialization before
95 * the CPU is "online".
96 */
97extern void prom_smp_finish(void);
98
99/* Hook for after all CPUs are online */
100extern void prom_cpus_done(void);
101
102extern void asmlinkage smp_bootstrap(void); 54extern void asmlinkage smp_bootstrap(void);
103 55
104/* 56/*
@@ -108,11 +60,11 @@ extern void asmlinkage smp_bootstrap(void);
108 */ 60 */
109static inline void smp_send_reschedule(int cpu) 61static inline void smp_send_reschedule(int cpu)
110{ 62{
111 core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); 63 extern struct plat_smp_ops *mp_ops; /* private */
64
65 mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
112} 66}
113 67
114extern asmlinkage void smp_call_function_interrupt(void); 68extern asmlinkage void smp_call_function_interrupt(void);
115 69
116#endif /* CONFIG_SMP */
117
118#endif /* __ASM_SMP_H */ 70#endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
index e09131a6127d..8ce517574340 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/include/asm-mips/smtc_ipi.h
@@ -49,7 +49,7 @@ struct smtc_ipi_q {
49 49
50static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) 50static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
51{ 51{
52 long flags; 52 unsigned long flags;
53 53
54 spin_lock_irqsave(&q->lock, flags); 54 spin_lock_irqsave(&q->lock, flags);
55 if (q->head == NULL) 55 if (q->head == NULL)
@@ -98,7 +98,7 @@ static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q)
98 98
99static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p) 99static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p)
100{ 100{
101 long flags; 101 unsigned long flags;
102 102
103 spin_lock_irqsave(&q->lock, flags); 103 spin_lock_irqsave(&q->lock, flags);
104 if (q->head == NULL) { 104 if (q->head == NULL) {
@@ -114,7 +114,7 @@ static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p)
114 114
115static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q) 115static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q)
116{ 116{
117 long flags; 117 unsigned long flags;
118 int retval; 118 int retval;
119 119
120 spin_lock_irqsave(&q->lock, flags); 120 spin_lock_irqsave(&q->lock, flags);
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index af081457f847..e716447e5e03 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -35,23 +35,23 @@ extern unsigned int sni_brd_type;
35#define SNI_CPU_M8050 0x0b 35#define SNI_CPU_M8050 0x0b
36#define SNI_CPU_M8053 0x0d 36#define SNI_CPU_M8053 0x0d
37 37
38#define SNI_PORT_BASE 0xb4000000 38#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
39 39
40#ifndef __MIPSEL__ 40#ifndef __MIPSEL__
41/* 41/*
42 * ASIC PCI registers for big endian configuration. 42 * ASIC PCI registers for big endian configuration.
43 */ 43 */
44#define PCIMT_UCONF 0xbfff0004 44#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
45#define PCIMT_IOADTIMEOUT2 0xbfff000c 45#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
46#define PCIMT_IOMEMCONF 0xbfff0014 46#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
47#define PCIMT_IOMMU 0xbfff001c 47#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
48#define PCIMT_IOADTIMEOUT1 0xbfff0024 48#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
49#define PCIMT_DMAACCESS 0xbfff002c 49#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
50#define PCIMT_DMAHIT 0xbfff0034 50#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
51#define PCIMT_ERRSTATUS 0xbfff003c 51#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
52#define PCIMT_ERRADDR 0xbfff0044 52#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
53#define PCIMT_SYNDROME 0xbfff004c 53#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
54#define PCIMT_ITPEND 0xbfff0054 54#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
55#define IT_INT2 0x01 55#define IT_INT2 0x01
56#define IT_INTD 0x02 56#define IT_INTD 0x02
57#define IT_INTC 0x04 57#define IT_INTC 0x04
@@ -60,32 +60,32 @@ extern unsigned int sni_brd_type;
60#define IT_EISA 0x20 60#define IT_EISA 0x20
61#define IT_SCSI 0x40 61#define IT_SCSI 0x40
62#define IT_ETH 0x80 62#define IT_ETH 0x80
63#define PCIMT_IRQSEL 0xbfff005c 63#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
64#define PCIMT_TESTMEM 0xbfff0064 64#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
65#define PCIMT_ECCREG 0xbfff006c 65#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
66#define PCIMT_CONFIG_ADDRESS 0xbfff0074 66#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
67#define PCIMT_ASIC_ID 0xbfff007c /* read */ 67#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
68#define PCIMT_SOFT_RESET 0xbfff007c /* write */ 68#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
69#define PCIMT_PIA_OE 0xbfff0084 69#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
70#define PCIMT_PIA_DATAOUT 0xbfff008c 70#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
71#define PCIMT_PIA_DATAIN 0xbfff0094 71#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
72#define PCIMT_CACHECONF 0xbfff009c 72#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
73#define PCIMT_INVSPACE 0xbfff00a4 73#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
74#else 74#else
75/* 75/*
76 * ASIC PCI registers for little endian configuration. 76 * ASIC PCI registers for little endian configuration.
77 */ 77 */
78#define PCIMT_UCONF 0xbfff0000 78#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
79#define PCIMT_IOADTIMEOUT2 0xbfff0008 79#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
80#define PCIMT_IOMEMCONF 0xbfff0010 80#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
81#define PCIMT_IOMMU 0xbfff0018 81#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
82#define PCIMT_IOADTIMEOUT1 0xbfff0020 82#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
83#define PCIMT_DMAACCESS 0xbfff0028 83#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
84#define PCIMT_DMAHIT 0xbfff0030 84#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
85#define PCIMT_ERRSTATUS 0xbfff0038 85#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
86#define PCIMT_ERRADDR 0xbfff0040 86#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
87#define PCIMT_SYNDROME 0xbfff0048 87#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
88#define PCIMT_ITPEND 0xbfff0050 88#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
89#define IT_INT2 0x01 89#define IT_INT2 0x01
90#define IT_INTD 0x02 90#define IT_INTD 0x02
91#define IT_INTC 0x04 91#define IT_INTC 0x04
@@ -94,20 +94,20 @@ extern unsigned int sni_brd_type;
94#define IT_EISA 0x20 94#define IT_EISA 0x20
95#define IT_SCSI 0x40 95#define IT_SCSI 0x40
96#define IT_ETH 0x80 96#define IT_ETH 0x80
97#define PCIMT_IRQSEL 0xbfff0058 97#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
98#define PCIMT_TESTMEM 0xbfff0060 98#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
99#define PCIMT_ECCREG 0xbfff0068 99#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
100#define PCIMT_CONFIG_ADDRESS 0xbfff0070 100#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
101#define PCIMT_ASIC_ID 0xbfff0078 /* read */ 101#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
102#define PCIMT_SOFT_RESET 0xbfff0078 /* write */ 102#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
103#define PCIMT_PIA_OE 0xbfff0080 103#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
104#define PCIMT_PIA_DATAOUT 0xbfff0088 104#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
105#define PCIMT_PIA_DATAIN 0xbfff0090 105#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
106#define PCIMT_CACHECONF 0xbfff0098 106#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
107#define PCIMT_INVSPACE 0xbfff00a0 107#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
108#endif 108#endif
109 109
110#define PCIMT_PCI_CONF 0xbfff0100 110#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
111 111
112/* 112/*
113 * Data port for the PCI bus in IO space 113 * Data port for the PCI bus in IO space
@@ -117,34 +117,34 @@ extern unsigned int sni_brd_type;
117/* 117/*
118 * Board specific registers 118 * Board specific registers
119 */ 119 */
120#define PCIMT_CSMSR 0xbfd00000 120#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
121#define PCIMT_CSSWITCH 0xbfd10000 121#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
122#define PCIMT_CSITPEND 0xbfd20000 122#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
123#define PCIMT_AUTO_PO_EN 0xbfd30000 123#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
124#define PCIMT_CLR_TEMP 0xbfd40000 124#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
125#define PCIMT_AUTO_PO_DIS 0xbfd50000 125#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
126#define PCIMT_EXMSR 0xbfd60000 126#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
127#define PCIMT_UNUSED1 0xbfd70000 127#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
128#define PCIMT_CSWCSM 0xbfd80000 128#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
129#define PCIMT_UNUSED2 0xbfd90000 129#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
130#define PCIMT_CSLED 0xbfda0000 130#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
131#define PCIMT_CSMAPISA 0xbfdb0000 131#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
132#define PCIMT_CSRSTBP 0xbfdc0000 132#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
133#define PCIMT_CLRPOFF 0xbfdd0000 133#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
134#define PCIMT_CSTIMER 0xbfde0000 134#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
135#define PCIMT_PWDN 0xbfdf0000 135#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
136 136
137/* 137/*
138 * A20R based boards 138 * A20R based boards
139 */ 139 */
140#define A20R_PT_CLOCK_BASE 0xbc040000 140#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
141#define A20R_PT_TIM0_ACK 0xbc050000 141#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
142#define A20R_PT_TIM1_ACK 0xbc060000 142#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
143 143
144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE 144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
146 146
147#define SNI_PCIT_INT_REG 0xbfff000c 147#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
148 148
149#define SNI_PCIT_INT_START 24 149#define SNI_PCIT_INT_START 24
150#define SNI_PCIT_INT_END 30 150#define SNI_PCIT_INT_END 30
@@ -186,10 +186,30 @@ extern unsigned int sni_brd_type;
186/* 186/*
187 * Base address for the mapped 16mb EISA bus segment. 187 * Base address for the mapped 16mb EISA bus segment.
188 */ 188 */
189#define PCIMT_EISA_BASE 0xb0000000 189#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
190 190
191/* PCI EISA Interrupt acknowledge */ 191/* PCI EISA Interrupt acknowledge */
192#define PCIMT_INT_ACKNOWLEDGE 0xba000000 192#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
193
194/*
195 * SNI ID PROM
196 *
197 * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities
198 * SNI_IDPROM_BRDTYPE Board Type
199 * SNI_IDPROM_CPUTYPE CPU Type on RM400
200 */
201#ifdef CONFIG_CPU_BIG_ENDIAN
202#define __SNI_END 0
203#endif
204#ifdef CONFIG_CPU_LITTLE_ENDIAN
205#define __SNI_END 3
206#endif
207#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
208#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
209#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
210#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
211
212#define SNI_IDPROM_SIZE 0x1000
193 213
194/* board specific init functions */ 214/* board specific init functions */
195extern void sni_a20r_init(void); 215extern void sni_a20r_init(void);
@@ -207,6 +227,9 @@ extern void sni_pcimt_irq_init(void);
207/* timer inits */ 227/* timer inits */
208extern void sni_cpu_time_init(void); 228extern void sni_cpu_time_init(void);
209 229
230/* eisa init for RM200/400 */
231extern int sni_eisa_root_init(void);
232
210/* common irq stuff */ 233/* common irq stuff */
211extern void (*sni_hwint)(void); 234extern void (*sni_hwint)(void);
212extern struct irqaction sni_isa_irq; 235extern struct irqaction sni_isa_irq;
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 95945689b1c6..63f60254d308 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -73,6 +73,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
73#define SO_TIMESTAMPNS 35 73#define SO_TIMESTAMPNS 35
74#define SCM_TIMESTAMPNS SO_TIMESTAMPNS 74#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
75 75
76#define SO_MARK 36
77
76#ifdef __KERNEL__ 78#ifdef __KERNEL__
77 79
78/** sock_type - Socket types 80/** sock_type - Socket types
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index fb41a8d76392..051e1af0bb95 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -6,6 +6,7 @@
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle 6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. 7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc. 8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
9 */ 10 */
10#ifndef _ASM_STACKFRAME_H 11#ifndef _ASM_STACKFRAME_H
11#define _ASM_STACKFRAME_H 12#define _ASM_STACKFRAME_H
@@ -145,8 +146,16 @@
145 .set reorder 146 .set reorder
146 /* Called from user mode, new stack. */ 147 /* Called from user mode, new stack. */
147 get_saved_sp 148 get_saved_sp
149#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
1488: move k0, sp 1508: move k0, sp
149 PTR_SUBU sp, k1, PT_SIZE 151 PTR_SUBU sp, k1, PT_SIZE
152#else
153 .set at=k0
1548: PTR_SUBU k1, PT_SIZE
155 .set noat
156 move k0, sp
157 move sp, k1
158#endif
150 LONG_S k0, PT_R29(sp) 159 LONG_S k0, PT_R29(sp)
151 LONG_S $3, PT_R3(sp) 160 LONG_S $3, PT_R3(sp)
152 /* 161 /*
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b403f531..a944eda4faf5 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@ do { \
68 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
69 __save_dsp(prev); \ 69 __save_dsp(prev); \
70 (last) = resume(prev, next, task_thread_info(next)); \ 70 (last) = resume(prev, next, task_thread_info(next)); \
71} while (0)
72
73#define finish_arch_switch(prev) \
74do { \
71 if (cpu_has_dsp) \ 75 if (cpu_has_dsp) \
72 __restore_dsp(current); \ 76 __restore_dsp(current); \
73 if (cpu_has_userlocal) \ 77 if (cpu_has_userlocal) \
74 write_c0_userlocal(task_thread_info(current)->tp_value);\ 78 write_c0_userlocal(current_thread_info()->tp_value); \
75} while(0) 79} while (0)
76 80
77static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 81static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
78{ 82{
@@ -205,8 +209,6 @@ extern void *set_except_vector(int n, void *addr);
205extern unsigned long ebase; 209extern unsigned long ebase;
206extern void per_cpu_trap_init(void); 210extern void per_cpu_trap_init(void);
207 211
208extern int stop_a_enabled;
209
210/* 212/*
211 * See include/asm-ia64/system.h; prevents deadlock on SMP 213 * See include/asm-ia64/system.h; prevents deadlock on SMP
212 * systems. 214 * systems.
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index bc47af313bcd..a8fd16e1981f 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -10,15 +10,10 @@
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 *
14 * Please refer to Documentation/mips/time.README.
15 */ 13 */
16#ifndef _ASM_TIME_H 14#ifndef _ASM_TIME_H
17#define _ASM_TIME_H 15#define _ASM_TIME_H
18 16
19#include <linux/interrupt.h>
20#include <linux/linkage.h>
21#include <linux/ptrace.h>
22#include <linux/rtc.h> 17#include <linux/rtc.h>
23#include <linux/spinlock.h> 18#include <linux/spinlock.h>
24#include <linux/clockchips.h> 19#include <linux/clockchips.h>
@@ -36,34 +31,13 @@ extern int rtc_mips_set_time(unsigned long);
36extern int rtc_mips_set_mmss(unsigned long); 31extern int rtc_mips_set_mmss(unsigned long);
37 32
38/* 33/*
39 * Timer interrupt functions.
40 * mips_timer_state is needed for high precision timer calibration.
41 * mips_timer_ack may be NULL if the interrupt is self-recoverable.
42 */
43extern int (*mips_timer_state)(void);
44
45/*
46 * High precision timer clocksource.
47 * If .read is NULL, an R4k-compatible timer setup is attempted.
48 */
49extern struct clocksource clocksource_mips;
50
51/*
52 * profiling and process accouting is done separately in local_timer_interrupt
53 */
54extern void local_timer_interrupt(int irq, void *dev_id);
55
56/*
57 * board specific routines required by time_init(). 34 * board specific routines required by time_init().
58 */ 35 */
59struct irqaction;
60extern void plat_time_init(void); 36extern void plat_time_init(void);
61extern void plat_timer_setup(struct irqaction *irq);
62 37
63/* 38/*
64 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 39 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
65 * counter as a timer interrupt source; otherwise it can be set up 40 * counter as a timer interrupt source.
66 * automagically with an aid of mips_timer_state.
67 */ 41 */
68extern unsigned int mips_hpt_frequency; 42extern unsigned int mips_hpt_frequency;
69 43
@@ -77,9 +51,22 @@ extern int (*perf_irq)(void);
77 * Initialize the calling CPU's compare interrupt as clockevent device 51 * Initialize the calling CPU's compare interrupt as clockevent device
78 */ 52 */
79#ifdef CONFIG_CEVT_R4K 53#ifdef CONFIG_CEVT_R4K
80extern void mips_clockevent_init(void); 54extern int mips_clockevent_init(void);
55extern unsigned int __weak get_c0_compare_int(void);
56#else
57static inline int mips_clockevent_init(void)
58{
59 return -ENXIO;
60}
61#endif
62
63/*
64 * Initialize the count register as a clocksource
65 */
66#ifdef CONFIG_CEVT_R4K
67extern void init_mips_clocksource(void);
81#else 68#else
82static inline void mips_clockevent_init(void) 69static inline void init_mips_clocksource(void)
83{ 70{
84} 71}
85#endif 72#endif
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index 87c68ae76ff8..6529704aa73a 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -13,27 +13,12 @@
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15/* 15/*
16 * This is the frequency of the timer used for Linux's timer interrupt. 16 * This is the clock rate of the i8253 PIT. A MIPS system may not have
17 * The value should be defined as accurate as possible or under certain 17 * a PIT by the symbol is used all over the kernel including some APIs.
18 * circumstances Linux timekeeping might become inaccurate or fail. 18 * So keeping it defined to the number for the PIT is the only sane thing
19 * 19 * for now.
20 * For many system the exact clockrate of the timer isn't known but due to
21 * the way this value is used we can get away with a wrong value as long
22 * as this value is:
23 *
24 * - a multiple of HZ
25 * - a divisor of the actual rate
26 *
27 * 500000 is a good such cheat value.
28 *
29 * The obscure number 1193182 is the same as used by the original i8254
30 * time in legacy PC hardware; the chip unfortunately also found in a
31 * bunch of MIPS systems. The last remaining user of the i8254 for the
32 * timer interrupt is the RM200; it's a very standard system so there is
33 * no reason to make this a separate architecture.
34 */ 20 */
35 21#define CLOCK_TICK_RATE 1193182
36#include <timex.h>
37 22
38/* 23/*
39 * Standard way to access the cycle counter. 24 * Standard way to access the cycle counter.
@@ -50,7 +35,7 @@ typedef unsigned int cycles_t;
50 35
51static inline cycles_t get_cycles(void) 36static inline cycles_t get_cycles(void)
52{ 37{
53 return read_c0_count(); 38 return 0;
54} 39}
55 40
56#endif /* __KERNEL__ */ 41#endif /* __KERNEL__ */
diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h
index 0440fb9f2180..259145e07e97 100644
--- a/include/asm-mips/topology.h
+++ b/include/asm-mips/topology.h
@@ -1 +1,17 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#ifndef __ASM_TOPOLOGY_H
9#define __ASM_TOPOLOGY_H
10
1#include <topology.h> 11#include <topology.h>
12
13#ifdef CONFIG_SMP
14#define smt_capable() (smp_num_siblings > 1)
15#endif
16
17#endif /* __ASM_TOPOLOGY_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index f98b2bb719d5..0be77df70f2b 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -9,6 +9,8 @@
9#define __ASM_TX4927_TX4927_PCI_H 9#define __ASM_TX4927_TX4927_PCI_H
10 10
11#define TX4927_CCFG_TOE 0x00004000 11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_WR 0x00008000
13#define TX4927_CCFG_TINTDIS 0x01000000
12 14
13#define TX4927_PCIMEM 0x08000000 15#define TX4927_PCIMEM 0x08000000
14#define TX4927_PCIMEM_SIZE 0x08000000 16#define TX4927_PCIMEM_SIZE 0x08000000
@@ -20,6 +22,8 @@
20#define TX4927_PCIC_REG 0xff1fd000 22#define TX4927_PCIC_REG 0xff1fd000
21#define TX4927_CCFG_REG 0xff1fe000 23#define TX4927_CCFG_REG 0xff1fe000
22#define TX4927_IRC_REG 0xff1ff600 24#define TX4927_IRC_REG 0xff1ff600
25#define TX4927_NR_TMR 3
26#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
23#define TX4927_CE3 0x17f00000 /* 1M */ 27#define TX4927_CE3 0x17f00000 /* 1M */
24#define TX4927_PCIRESET_ADDR 0xbc00f006 28#define TX4927_PCIRESET_ADDR 0xbc00f006
25#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) 29#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index 650b010761f9..f7c448b90578 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -641,7 +641,6 @@ struct tx4938_ccfg_reg {
641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
644#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
645#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 644#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
646#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) 645#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
647#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 646#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h
new file mode 100644
index 000000000000..67f70a8f09bd
--- /dev/null
+++ b/include/asm-mips/txx9tmr.h
@@ -0,0 +1,67 @@
1/*
2 * include/asm-mips/txx9tmr.h
3 * TX39/TX49 timer controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9TMR_H
10#define __ASM_TXX9TMR_H
11
12#include <linux/types.h>
13
14struct txx9_tmr_reg {
15 u32 tcr;
16 u32 tisr;
17 u32 cpra;
18 u32 cprb;
19 u32 itmr;
20 u32 unused0[3];
21 u32 ccdr;
22 u32 unused1[3];
23 u32 pgmr;
24 u32 unused2[3];
25 u32 wtmr;
26 u32 unused3[43];
27 u32 trr;
28};
29
30/* TMTCR : Timer Control */
31#define TXx9_TMTCR_TCE 0x00000080
32#define TXx9_TMTCR_CCDE 0x00000040
33#define TXx9_TMTCR_CRE 0x00000020
34#define TXx9_TMTCR_ECES 0x00000008
35#define TXx9_TMTCR_CCS 0x00000004
36#define TXx9_TMTCR_TMODE_MASK 0x00000003
37#define TXx9_TMTCR_TMODE_ITVL 0x00000000
38#define TXx9_TMTCR_TMODE_PGEN 0x00000001
39#define TXx9_TMTCR_TMODE_WDOG 0x00000002
40
41/* TMTISR : Timer Int. Status */
42#define TXx9_TMTISR_TPIBS 0x00000004
43#define TXx9_TMTISR_TPIAS 0x00000002
44#define TXx9_TMTISR_TIIS 0x00000001
45
46/* TMITMR : Interval Timer Mode */
47#define TXx9_TMITMR_TIIE 0x00008000
48#define TXx9_TMITMR_TZCE 0x00000001
49
50/* TMWTMR : Watchdog Timer Mode */
51#define TXx9_TMWTMR_TWIE 0x00008000
52#define TXx9_TMWTMR_WDIS 0x00000080
53#define TXx9_TMWTMR_TWC 0x00000001
54
55void txx9_clocksource_init(unsigned long baseaddr,
56 unsigned int imbusclk);
57void txx9_clockevent_init(unsigned long baseaddr, int irq,
58 unsigned int imbusclk);
59void txx9_tmr_init(unsigned long baseaddr);
60
61#ifdef CONFIG_CPU_TX39XX
62#define TXX9_TIMER_BITS 24
63#else
64#define TXX9_TIMER_BITS 32
65#endif
66
67#endif /* __ASM_TXX9TMR_H */
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index c30c718994c9..66523d610950 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle 6 * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2007 Maciej W. Rozycki
8 */ 9 */
9#ifndef _ASM_UACCESS_H 10#ifndef _ASM_UACCESS_H
10#define _ASM_UACCESS_H 11#define _ASM_UACCESS_H
@@ -387,6 +388,12 @@ extern void __put_user_unknown(void);
387 "jal\t" #destination "\n\t" 388 "jal\t" #destination "\n\t"
388#endif 389#endif
389 390
391#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
392#define DADDI_SCRATCH "$0"
393#else
394#define DADDI_SCRATCH "$3"
395#endif
396
390extern size_t __copy_user(void *__to, const void *__from, size_t __n); 397extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 398
392#define __invoke_copy_to_user(to, from, n) \ 399#define __invoke_copy_to_user(to, from, n) \
@@ -403,7 +410,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
403 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 410 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
404 : \ 411 : \
405 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 412 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
406 "memory"); \ 413 DADDI_SCRATCH, "memory"); \
407 __cu_len_r; \ 414 __cu_len_r; \
408}) 415})
409 416
@@ -512,7 +519,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
512 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 519 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
513 : \ 520 : \
514 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 521 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
515 "memory"); \ 522 DADDI_SCRATCH, "memory"); \
516 __cu_len_r; \ 523 __cu_len_r; \
517}) 524})
518 525
@@ -535,7 +542,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
535 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 542 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
536 : \ 543 : \
537 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 544 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
538 "memory"); \ 545 DADDI_SCRATCH, "memory"); \
539 __cu_len_r; \ 546 __cu_len_r; \
540}) 547})
541 548
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index d2808edfd4e9..22361d5e3bf0 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
7 * Copyright (C) 2007 Maciej W. Rozycki
7 */ 8 */
8#ifndef _ASM_WAR_H 9#ifndef _ASM_WAR_H
9#define _ASM_WAR_H 10#define _ASM_WAR_H
@@ -11,6 +12,67 @@
11#include <war.h> 12#include <war.h>
12 13
13/* 14/*
15 * Work around certain R4000 CPU errata (as implemented by GCC):
16 *
17 * - A double-word or a variable shift may give an incorrect result
18 * if executed immediately after starting an integer division:
19 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
20 * erratum #28
21 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
22 * #19
23 *
24 * - A double-word or a variable shift may give an incorrect result
25 * if executed while an integer multiplication is in progress:
26 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
27 * errata #16 & #28
28 *
29 * - An integer division may give an incorrect result if started in
30 * a delay slot of a taken branch or a jump:
31 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
32 * erratum #52
33 */
34#ifdef CONFIG_CPU_R4000_WORKAROUNDS
35#define R4000_WAR 1
36#else
37#define R4000_WAR 0
38#endif
39
40/*
41 * Work around certain R4400 CPU errata (as implemented by GCC):
42 *
43 * - A double-word or a variable shift may give an incorrect result
44 * if executed immediately after starting an integer division:
45 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
46 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
47 */
48#ifdef CONFIG_CPU_R4400_WORKAROUNDS
49#define R4400_WAR 1
50#else
51#define R4400_WAR 0
52#endif
53
54/*
55 * Work around the "daddi" and "daddiu" CPU errata:
56 *
57 * - The `daddi' instruction fails to trap on overflow.
58 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
59 * erratum #23
60 *
61 * - The `daddiu' instruction can produce an incorrect result.
62 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
63 * erratum #41
64 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
65 * #15
66 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
67 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
68 */
69#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
70#define DADDI_WAR 1
71#else
72#define DADDI_WAR 0
73#endif
74
75/*
14 * Another R4600 erratum. Due to the lack of errata information the exact 76 * Another R4600 erratum. Due to the lack of errata information the exact
15 * technical details aren't known. I've experimentally found that disabling 77 * technical details aren't known. I've experimentally found that disabling
16 * interrupts during indexed I-cache flushes seems to be sufficient to deal 78 * interrupts during indexed I-cache flushes seems to be sufficient to deal
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-13 23:02:57 -0500