aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/cpu-features.h4
-rw-r--r--include/asm-mips/cpu.h1
-rw-r--r--include/asm-mips/mipsregs.h6
-rw-r--r--include/asm-mips/system.h2
4 files changed, 12 insertions, 1 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 5e4bed123b48..d95a83e3e1d7 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -150,6 +150,10 @@
150#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 150#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
151#endif 151#endif
152 152
153#ifndef cpu_has_userlocal
154#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
155#endif
156
153#ifdef CONFIG_32BIT 157#ifdef CONFIG_32BIT
154# ifndef cpu_has_nofpuex 158# ifndef cpu_has_nofpuex
155# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 159# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 2924069075e0..49c1f0011863 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -257,6 +257,7 @@
257#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 257#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
258#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 258#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
259#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 259#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
260#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
260 261
261/* 262/*
262 * CPU ASE encodings 263 * CPU ASE encodings
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 89c81922d47c..668db02c2804 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,7 +7,7 @@
7 * Copyright (C) 2000 Silicon Graphics, Inc. 7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */ 12 */
13#ifndef _ASM_MIPSREGS_H 13#ifndef _ASM_MIPSREGS_H
@@ -533,6 +533,7 @@
533#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 533#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
534#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 534#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
535#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 535#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
536#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
536 537
537#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 538#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
538 539
@@ -772,6 +773,9 @@ do { \
772#define read_c0_context() __read_ulong_c0_register($4, 0) 773#define read_c0_context() __read_ulong_c0_register($4, 0)
773#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 774#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
774 775
776#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
777#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
778
775#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 779#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
776#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 780#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
777 781
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 9b3a8dd2c3db..be64fc55562a 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -67,6 +67,8 @@ do { \
67 (last) = resume(prev, next, task_thread_info(next)); \ 67 (last) = resume(prev, next, task_thread_info(next)); \
68 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
69 __restore_dsp(current); \ 69 __restore_dsp(current); \
70 if (cpu_has_userlocal) \
71 write_c0_userlocal(task_thread_info(current)->tp_value);\
70} while(0) 72} while(0)
71 73
72/* 74/*