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-rw-r--r--include/asm-mips/bitops.h14
-rw-r--r--include/asm-mips/compiler.h4
-rw-r--r--include/asm-mips/cpu-info.h4
-rw-r--r--include/asm-mips/gic.h6
-rw-r--r--include/asm-mips/lasat/serial.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1645
-rw-r--r--include/asm-mips/mach-au1x00/au1000_dma.h179
-rw-r--r--include/asm-mips/mach-au1x00/au1000_gpio.h18
-rw-r--r--include/asm-mips/mach-au1x00/au1550_spi.h2
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h156
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h251
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h131
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h73
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h83
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h189
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h96
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h93
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h38
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h51
-rw-r--r--include/asm-mips/mipsregs.h3
-rw-r--r--include/asm-mips/pgtable-bits.h2
-rw-r--r--include/asm-mips/pgtable.h3
-rw-r--r--include/asm-mips/rtlx.h6
24 files changed, 1466 insertions, 1589 deletions
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index c2bd126c3b4e..642724734eba 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -558,11 +558,13 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
558 __clear_bit(nr, addr); 558 __clear_bit(nr, addr);
559} 559}
560 560
561#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
562
561/* 563/*
562 * Return the bit position (0..63) of the most significant 1 bit in a word 564 * Return the bit position (0..63) of the most significant 1 bit in a word
563 * Returns -1 if no 1 bit exists 565 * Returns -1 if no 1 bit exists
564 */ 566 */
565static inline int __ilog2(unsigned long x) 567static inline unsigned long __fls(unsigned long x)
566{ 568{
567 int lz; 569 int lz;
568 570
@@ -591,13 +593,6 @@ static inline int __ilog2(unsigned long x)
591 return 63 - lz; 593 return 63 - lz;
592} 594}
593 595
594static inline unsigned long __fls(unsigned long x)
595{
596 return __ilog2(x);
597}
598
599#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
600
601/* 596/*
602 * __ffs - find first bit in word. 597 * __ffs - find first bit in word.
603 * @word: The word to search 598 * @word: The word to search
@@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x)
607 */ 602 */
608static inline unsigned long __ffs(unsigned long word) 603static inline unsigned long __ffs(unsigned long word)
609{ 604{
610 return __ilog2(word & -word); 605 return __fls(word & -word);
611} 606}
612 607
613/* 608/*
@@ -654,6 +649,7 @@ static inline int ffs(int word)
654#else 649#else
655 650
656#include <asm-generic/bitops/__ffs.h> 651#include <asm-generic/bitops/__ffs.h>
652#include <asm-generic/bitops/__fls.h>
657#include <asm-generic/bitops/ffs.h> 653#include <asm-generic/bitops/ffs.h>
658#include <asm-generic/bitops/fls.h> 654#include <asm-generic/bitops/fls.h>
659#include <asm-generic/bitops/fls64.h> 655#include <asm-generic/bitops/fls64.h>
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
index aa6b876bbd78..71f5c5cfc58a 100644
--- a/include/asm-mips/compiler.h
+++ b/include/asm-mips/compiler.h
@@ -9,10 +9,10 @@
9#define _ASM_COMPILER_H 9#define _ASM_COMPILER_H
10 10
11#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) 11#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
12#define GCC_IMM_ASM "n" 12#define GCC_IMM_ASM() "n"
13#define GCC_REG_ACCUM "$0" 13#define GCC_REG_ACCUM "$0"
14#else 14#else
15#define GCC_IMM_ASM "rn" 15#define GCC_IMM_ASM() "rn"
16#define GCC_REG_ACCUM "accum" 16#define GCC_REG_ACCUM "accum"
17#endif 17#endif
18 18
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 0c5a358863f3..2de73dbb2e9e 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -56,7 +56,7 @@ struct cpuinfo_mips {
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */ 57 int srsets; /* Shadow register sets */
58 int core; /* physical core number */ 58 int core; /* physical core number */
59#if defined(CONFIG_MIPS_MT_SMTC) 59#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
60 /* 60 /*
61 * In the MIPS MT "SMTC" model, each TC is considered 61 * In the MIPS MT "SMTC" model, each TC is considered
62 * to be a "CPU" for the purposes of scheduling, but 62 * to be a "CPU" for the purposes of scheduling, but
@@ -64,7 +64,7 @@ struct cpuinfo_mips {
64 * to all TCs within the same VPE. 64 * to all TCs within the same VPE.
65 */ 65 */
66 int vpe_id; /* Virtual Processor number */ 66 int vpe_id; /* Virtual Processor number */
67#endif /* CONFIG_MIPS_MT */ 67#endif
68#ifdef CONFIG_MIPS_MT_SMTC 68#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */ 69 int tc_id; /* Thread Context number */
70#endif 70#endif
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
index 01b2f92dc33d..954807d9d66a 100644
--- a/include/asm-mips/gic.h
+++ b/include/asm-mips/gic.h
@@ -24,8 +24,8 @@
24 24
25#define MSK(n) ((1 << (n)) - 1) 25#define MSK(n) ((1 << (n)) - 1)
26#define REG32(addr) (*(volatile unsigned int *) (addr)) 26#define REG32(addr) (*(volatile unsigned int *) (addr))
27#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) 27#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
28#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) 28#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
29 29
30/* Accessors */ 30/* Accessors */
31#define GIC_REG(segment, offset) \ 31#define GIC_REG(segment, offset) \
@@ -330,7 +330,7 @@
330 330
331#define GIC_SH_RMASK_OFS 0x0300 331#define GIC_SH_RMASK_OFS 0x0300
332#define GIC_CLR_INTR_MASK(intr, val) \ 332#define GIC_CLR_INTR_MASK(intr, val) \
333 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)) 333 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
334 334
335/* Register Map for Local Section */ 335/* Register Map for Local Section */
336#define GIC_VPE_CTL_OFS 0x0000 336#define GIC_VPE_CTL_OFS 0x0000
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index bafe68b10614..1c37d70579b8 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -4,10 +4,10 @@
4#define LASAT_BASE_BAUD_100 (7372800 / 16) 4#define LASAT_BASE_BAUD_100 (7372800 / 16)
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000 5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2 6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8 7#define LASATINT_UART_100 16
8 8
9/* * LASAT 200 boards serial configuration */ 9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) 10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) 11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3 12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13 13#define LASATINT_UART_200 21
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index a05555165d05..0d302bad4492 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -40,8 +40,8 @@
40#include <linux/delay.h> 40#include <linux/delay.h>
41#include <linux/types.h> 41#include <linux/types.h>
42 42
43#include <asm/io.h> 43#include <linux/io.h>
44#include <asm/irq.h> 44#include <linux/irq.h>
45 45
46/* cpu pipeline flush */ 46/* cpu pipeline flush */
47void static inline au_sync(void) 47void static inline au_sync(void)
@@ -63,32 +63,32 @@ void static inline au_sync_delay(int ms)
63 63
64void static inline au_writeb(u8 val, unsigned long reg) 64void static inline au_writeb(u8 val, unsigned long reg)
65{ 65{
66 *(volatile u8 *)(reg) = val; 66 *(volatile u8 *)reg = val;
67} 67}
68 68
69void static inline au_writew(u16 val, unsigned long reg) 69void static inline au_writew(u16 val, unsigned long reg)
70{ 70{
71 *(volatile u16 *)(reg) = val; 71 *(volatile u16 *)reg = val;
72} 72}
73 73
74void static inline au_writel(u32 val, unsigned long reg) 74void static inline au_writel(u32 val, unsigned long reg)
75{ 75{
76 *(volatile u32 *)(reg) = val; 76 *(volatile u32 *)reg = val;
77} 77}
78 78
79static inline u8 au_readb(unsigned long reg) 79static inline u8 au_readb(unsigned long reg)
80{ 80{
81 return (*(volatile u8 *)reg); 81 return *(volatile u8 *)reg;
82} 82}
83 83
84static inline u16 au_readw(unsigned long reg) 84static inline u16 au_readw(unsigned long reg)
85{ 85{
86 return (*(volatile u16 *)reg); 86 return *(volatile u16 *)reg;
87} 87}
88 88
89static inline u32 au_readl(unsigned long reg) 89static inline u32 au_readl(unsigned long reg)
90{ 90{
91 return (*(volatile u32 *)reg); 91 return *(volatile u32 *)reg;
92} 92}
93 93
94 94
@@ -117,76 +117,77 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 117#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118 118
119/* 119/*
120 * SDRAM Register Offsets 120 * SDRAM register offsets
121 */ 121 */
122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
123#define MEM_SDMODE0 (0x0000) 123 defined(CONFIG_SOC_AU1100)
124#define MEM_SDMODE1 (0x0004) 124#define MEM_SDMODE0 0x0000
125#define MEM_SDMODE2 (0x0008) 125#define MEM_SDMODE1 0x0004
126#define MEM_SDADDR0 (0x000C) 126#define MEM_SDMODE2 0x0008
127#define MEM_SDADDR1 (0x0010) 127#define MEM_SDADDR0 0x000C
128#define MEM_SDADDR2 (0x0014) 128#define MEM_SDADDR1 0x0010
129#define MEM_SDREFCFG (0x0018) 129#define MEM_SDADDR2 0x0014
130#define MEM_SDPRECMD (0x001C) 130#define MEM_SDREFCFG 0x0018
131#define MEM_SDAUTOREF (0x0020) 131#define MEM_SDPRECMD 0x001C
132#define MEM_SDWRMD0 (0x0024) 132#define MEM_SDAUTOREF 0x0020
133#define MEM_SDWRMD1 (0x0028) 133#define MEM_SDWRMD0 0x0024
134#define MEM_SDWRMD2 (0x002C) 134#define MEM_SDWRMD1 0x0028
135#define MEM_SDSLEEP (0x0030) 135#define MEM_SDWRMD2 0x002C
136#define MEM_SDSMCKE (0x0034) 136#define MEM_SDSLEEP 0x0030
137#define MEM_SDSMCKE 0x0034
137 138
138/* 139/*
139 * MEM_SDMODE register content definitions 140 * MEM_SDMODE register content definitions
140 */ 141 */
141#define MEM_SDMODE_F (1<<22) 142#define MEM_SDMODE_F (1 << 22)
142#define MEM_SDMODE_SR (1<<21) 143#define MEM_SDMODE_SR (1 << 21)
143#define MEM_SDMODE_BS (1<<20) 144#define MEM_SDMODE_BS (1 << 20)
144#define MEM_SDMODE_RS (3<<18) 145#define MEM_SDMODE_RS (3 << 18)
145#define MEM_SDMODE_CS (7<<15) 146#define MEM_SDMODE_CS (7 << 15)
146#define MEM_SDMODE_TRAS (15<<11) 147#define MEM_SDMODE_TRAS (15 << 11)
147#define MEM_SDMODE_TMRD (3<<9) 148#define MEM_SDMODE_TMRD (3 << 9)
148#define MEM_SDMODE_TWR (3<<7) 149#define MEM_SDMODE_TWR (3 << 7)
149#define MEM_SDMODE_TRP (3<<5) 150#define MEM_SDMODE_TRP (3 << 5)
150#define MEM_SDMODE_TRCD (3<<3) 151#define MEM_SDMODE_TRCD (3 << 3)
151#define MEM_SDMODE_TCL (7<<0) 152#define MEM_SDMODE_TCL (7 << 0)
152 153
153#define MEM_SDMODE_BS_2Bank (0<<20) 154#define MEM_SDMODE_BS_2Bank (0 << 20)
154#define MEM_SDMODE_BS_4Bank (1<<20) 155#define MEM_SDMODE_BS_4Bank (1 << 20)
155#define MEM_SDMODE_RS_11Row (0<<18) 156#define MEM_SDMODE_RS_11Row (0 << 18)
156#define MEM_SDMODE_RS_12Row (1<<18) 157#define MEM_SDMODE_RS_12Row (1 << 18)
157#define MEM_SDMODE_RS_13Row (2<<18) 158#define MEM_SDMODE_RS_13Row (2 << 18)
158#define MEM_SDMODE_RS_N(N) ((N)<<18) 159#define MEM_SDMODE_RS_N(N) ((N) << 18)
159#define MEM_SDMODE_CS_7Col (0<<15) 160#define MEM_SDMODE_CS_7Col (0 << 15)
160#define MEM_SDMODE_CS_8Col (1<<15) 161#define MEM_SDMODE_CS_8Col (1 << 15)
161#define MEM_SDMODE_CS_9Col (2<<15) 162#define MEM_SDMODE_CS_9Col (2 << 15)
162#define MEM_SDMODE_CS_10Col (3<<15) 163#define MEM_SDMODE_CS_10Col (3 << 15)
163#define MEM_SDMODE_CS_11Col (4<<15) 164#define MEM_SDMODE_CS_11Col (4 << 15)
164#define MEM_SDMODE_CS_N(N) ((N)<<15) 165#define MEM_SDMODE_CS_N(N) ((N) << 15)
165#define MEM_SDMODE_TRAS_N(N) ((N)<<11) 166#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
166#define MEM_SDMODE_TMRD_N(N) ((N)<<9) 167#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
167#define MEM_SDMODE_TWR_N(N) ((N)<<7) 168#define MEM_SDMODE_TWR_N(N) ((N) << 7)
168#define MEM_SDMODE_TRP_N(N) ((N)<<5) 169#define MEM_SDMODE_TRP_N(N) ((N) << 5)
169#define MEM_SDMODE_TRCD_N(N) ((N)<<3) 170#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
170#define MEM_SDMODE_TCL_N(N) ((N)<<0) 171#define MEM_SDMODE_TCL_N(N) ((N) << 0)
171 172
172/* 173/*
173 * MEM_SDADDR register contents definitions 174 * MEM_SDADDR register contents definitions
174 */ 175 */
175#define MEM_SDADDR_E (1<<20) 176#define MEM_SDADDR_E (1 << 20)
176#define MEM_SDADDR_CSBA (0x03FF<<10) 177#define MEM_SDADDR_CSBA (0x03FF << 10)
177#define MEM_SDADDR_CSMASK (0x03FF<<0) 178#define MEM_SDADDR_CSMASK (0x03FF << 0)
178#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12) 179#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
179#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22) 180#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
180 181
181/* 182/*
182 * MEM_SDREFCFG register content definitions 183 * MEM_SDREFCFG register content definitions
183 */ 184 */
184#define MEM_SDREFCFG_TRC (15<<28) 185#define MEM_SDREFCFG_TRC (15 << 28)
185#define MEM_SDREFCFG_TRPM (3<<26) 186#define MEM_SDREFCFG_TRPM (3 << 26)
186#define MEM_SDREFCFG_E (1<<25) 187#define MEM_SDREFCFG_E (1 << 25)
187#define MEM_SDREFCFG_RE (0x1ffffff<<0) 188#define MEM_SDREFCFG_RE (0x1ffffff << 0)
188#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC) 189#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
189#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM) 190#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
190#define MEM_SDREFCFG_REF_N(N) (N) 191#define MEM_SDREFCFG_REF_N(N) (N)
191#endif 192#endif
192 193
@@ -199,25 +200,25 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
199/***********************************************************************/ 200/***********************************************************************/
200 201
201#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 202#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
202#define MEM_SDMODE0 (0x0800) 203#define MEM_SDMODE0 0x0800
203#define MEM_SDMODE1 (0x0808) 204#define MEM_SDMODE1 0x0808
204#define MEM_SDMODE2 (0x0810) 205#define MEM_SDMODE2 0x0810
205#define MEM_SDADDR0 (0x0820) 206#define MEM_SDADDR0 0x0820
206#define MEM_SDADDR1 (0x0828) 207#define MEM_SDADDR1 0x0828
207#define MEM_SDADDR2 (0x0830) 208#define MEM_SDADDR2 0x0830
208#define MEM_SDCONFIGA (0x0840) 209#define MEM_SDCONFIGA 0x0840
209#define MEM_SDCONFIGB (0x0848) 210#define MEM_SDCONFIGB 0x0848
210#define MEM_SDSTAT (0x0850) 211#define MEM_SDSTAT 0x0850
211#define MEM_SDERRADDR (0x0858) 212#define MEM_SDERRADDR 0x0858
212#define MEM_SDSTRIDE0 (0x0860) 213#define MEM_SDSTRIDE0 0x0860
213#define MEM_SDSTRIDE1 (0x0868) 214#define MEM_SDSTRIDE1 0x0868
214#define MEM_SDSTRIDE2 (0x0870) 215#define MEM_SDSTRIDE2 0x0870
215#define MEM_SDWRMD0 (0x0880) 216#define MEM_SDWRMD0 0x0880
216#define MEM_SDWRMD1 (0x0888) 217#define MEM_SDWRMD1 0x0888
217#define MEM_SDWRMD2 (0x0890) 218#define MEM_SDWRMD2 0x0890
218#define MEM_SDPRECMD (0x08C0) 219#define MEM_SDPRECMD 0x08C0
219#define MEM_SDAUTOREF (0x08C8) 220#define MEM_SDAUTOREF 0x08C8
220#define MEM_SDSREF (0x08D0) 221#define MEM_SDSREF 0x08D0
221#define MEM_SDSLEEP MEM_SDSREF 222#define MEM_SDSLEEP MEM_SDSREF
222 223
223#endif 224#endif
@@ -256,9 +257,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
256#define SSI0_PHYS_ADDR 0x11600000 257#define SSI0_PHYS_ADDR 0x11600000
257#define SSI1_PHYS_ADDR 0x11680000 258#define SSI1_PHYS_ADDR 0x11680000
258#define SYS_PHYS_ADDR 0x11900000 259#define SYS_PHYS_ADDR 0x11900000
259#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 260#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
260#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 261#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
261#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 262#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
262#endif 263#endif
263 264
264/********************************************************************/ 265/********************************************************************/
@@ -290,13 +291,13 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
290#define UART3_PHYS_ADDR 0x11400000 291#define UART3_PHYS_ADDR 0x11400000
291#define GPIO2_PHYS_ADDR 0x11700000 292#define GPIO2_PHYS_ADDR 0x11700000
292#define SYS_PHYS_ADDR 0x11900000 293#define SYS_PHYS_ADDR 0x11900000
293#define PCI_MEM_PHYS_ADDR 0x400000000ULL 294#define PCI_MEM_PHYS_ADDR 0x400000000ULL
294#define PCI_IO_PHYS_ADDR 0x500000000ULL 295#define PCI_IO_PHYS_ADDR 0x500000000ULL
295#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 296#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
296#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 297#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
297#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 298#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
298#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 299#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
299#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 300#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
300#endif 301#endif
301 302
302/********************************************************************/ 303/********************************************************************/
@@ -333,9 +334,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
333#define GPIO2_PHYS_ADDR 0x11700000 334#define GPIO2_PHYS_ADDR 0x11700000
334#define SYS_PHYS_ADDR 0x11900000 335#define SYS_PHYS_ADDR 0x11900000
335#define LCD_PHYS_ADDR 0x15000000 336#define LCD_PHYS_ADDR 0x15000000
336#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 337#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
337#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 338#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
338#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 339#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
339#endif 340#endif
340 341
341/***********************************************************************/ 342/***********************************************************************/
@@ -360,17 +361,17 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
360#define SYS_PHYS_ADDR 0x11900000 361#define SYS_PHYS_ADDR 0x11900000
361#define DDMA_PHYS_ADDR 0x14002000 362#define DDMA_PHYS_ADDR 0x14002000
362#define PE_PHYS_ADDR 0x14008000 363#define PE_PHYS_ADDR 0x14008000
363#define PSC0_PHYS_ADDR 0x11A00000 364#define PSC0_PHYS_ADDR 0x11A00000
364#define PSC1_PHYS_ADDR 0x11B00000 365#define PSC1_PHYS_ADDR 0x11B00000
365#define PSC2_PHYS_ADDR 0x10A00000 366#define PSC2_PHYS_ADDR 0x10A00000
366#define PSC3_PHYS_ADDR 0x10B00000 367#define PSC3_PHYS_ADDR 0x10B00000
367#define PCI_MEM_PHYS_ADDR 0x400000000ULL 368#define PCI_MEM_PHYS_ADDR 0x400000000ULL
368#define PCI_IO_PHYS_ADDR 0x500000000ULL 369#define PCI_IO_PHYS_ADDR 0x500000000ULL
369#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 370#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
370#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 371#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
371#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 372#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
372#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 373#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
373#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 374#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
374#endif 375#endif
375 376
376/***********************************************************************/ 377/***********************************************************************/
@@ -397,122 +398,121 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
397#define SWCNT_PHYS_ADDR 0x1110010C 398#define SWCNT_PHYS_ADDR 0x1110010C
398#define MAEFE_PHYS_ADDR 0x14012000 399#define MAEFE_PHYS_ADDR 0x14012000
399#define MAEBE_PHYS_ADDR 0x14010000 400#define MAEBE_PHYS_ADDR 0x14010000
400#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 401#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
401#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 402#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
402#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 403#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
403#endif 404#endif
404 405
405
406/* Static Bus Controller */ 406/* Static Bus Controller */
407#define MEM_STCFG0 0xB4001000 407#define MEM_STCFG0 0xB4001000
408#define MEM_STTIME0 0xB4001004 408#define MEM_STTIME0 0xB4001004
409#define MEM_STADDR0 0xB4001008 409#define MEM_STADDR0 0xB4001008
410 410
411#define MEM_STCFG1 0xB4001010 411#define MEM_STCFG1 0xB4001010
412#define MEM_STTIME1 0xB4001014 412#define MEM_STTIME1 0xB4001014
413#define MEM_STADDR1 0xB4001018 413#define MEM_STADDR1 0xB4001018
414 414
415#define MEM_STCFG2 0xB4001020 415#define MEM_STCFG2 0xB4001020
416#define MEM_STTIME2 0xB4001024 416#define MEM_STTIME2 0xB4001024
417#define MEM_STADDR2 0xB4001028 417#define MEM_STADDR2 0xB4001028
418 418
419#define MEM_STCFG3 0xB4001030 419#define MEM_STCFG3 0xB4001030
420#define MEM_STTIME3 0xB4001034 420#define MEM_STTIME3 0xB4001034
421#define MEM_STADDR3 0xB4001038 421#define MEM_STADDR3 0xB4001038
422 422
423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
424#define MEM_STNDCTL 0xB4001100 424#define MEM_STNDCTL 0xB4001100
425#define MEM_STSTAT 0xB4001104 425#define MEM_STSTAT 0xB4001104
426 426
427#define MEM_STNAND_CMD (0x0) 427#define MEM_STNAND_CMD 0x0
428#define MEM_STNAND_ADDR (0x4) 428#define MEM_STNAND_ADDR 0x4
429#define MEM_STNAND_DATA (0x20) 429#define MEM_STNAND_DATA 0x20
430#endif 430#endif
431 431
432/* Interrupt Controller 0 */ 432/* Interrupt Controller 0 */
433#define IC0_CFG0RD 0xB0400040 433#define IC0_CFG0RD 0xB0400040
434#define IC0_CFG0SET 0xB0400040 434#define IC0_CFG0SET 0xB0400040
435#define IC0_CFG0CLR 0xB0400044 435#define IC0_CFG0CLR 0xB0400044
436 436
437#define IC0_CFG1RD 0xB0400048 437#define IC0_CFG1RD 0xB0400048
438#define IC0_CFG1SET 0xB0400048 438#define IC0_CFG1SET 0xB0400048
439#define IC0_CFG1CLR 0xB040004C 439#define IC0_CFG1CLR 0xB040004C
440 440
441#define IC0_CFG2RD 0xB0400050 441#define IC0_CFG2RD 0xB0400050
442#define IC0_CFG2SET 0xB0400050 442#define IC0_CFG2SET 0xB0400050
443#define IC0_CFG2CLR 0xB0400054 443#define IC0_CFG2CLR 0xB0400054
444 444
445#define IC0_REQ0INT 0xB0400054 445#define IC0_REQ0INT 0xB0400054
446#define IC0_SRCRD 0xB0400058 446#define IC0_SRCRD 0xB0400058
447#define IC0_SRCSET 0xB0400058 447#define IC0_SRCSET 0xB0400058
448#define IC0_SRCCLR 0xB040005C 448#define IC0_SRCCLR 0xB040005C
449#define IC0_REQ1INT 0xB040005C 449#define IC0_REQ1INT 0xB040005C
450 450
451#define IC0_ASSIGNRD 0xB0400060 451#define IC0_ASSIGNRD 0xB0400060
452#define IC0_ASSIGNSET 0xB0400060 452#define IC0_ASSIGNSET 0xB0400060
453#define IC0_ASSIGNCLR 0xB0400064 453#define IC0_ASSIGNCLR 0xB0400064
454 454
455#define IC0_WAKERD 0xB0400068 455#define IC0_WAKERD 0xB0400068
456#define IC0_WAKESET 0xB0400068 456#define IC0_WAKESET 0xB0400068
457#define IC0_WAKECLR 0xB040006C 457#define IC0_WAKECLR 0xB040006C
458 458
459#define IC0_MASKRD 0xB0400070 459#define IC0_MASKRD 0xB0400070
460#define IC0_MASKSET 0xB0400070 460#define IC0_MASKSET 0xB0400070
461#define IC0_MASKCLR 0xB0400074 461#define IC0_MASKCLR 0xB0400074
462 462
463#define IC0_RISINGRD 0xB0400078 463#define IC0_RISINGRD 0xB0400078
464#define IC0_RISINGCLR 0xB0400078 464#define IC0_RISINGCLR 0xB0400078
465#define IC0_FALLINGRD 0xB040007C 465#define IC0_FALLINGRD 0xB040007C
466#define IC0_FALLINGCLR 0xB040007C 466#define IC0_FALLINGCLR 0xB040007C
467 467
468#define IC0_TESTBIT 0xB0400080 468#define IC0_TESTBIT 0xB0400080
469 469
470/* Interrupt Controller 1 */ 470/* Interrupt Controller 1 */
471#define IC1_CFG0RD 0xB1800040 471#define IC1_CFG0RD 0xB1800040
472#define IC1_CFG0SET 0xB1800040 472#define IC1_CFG0SET 0xB1800040
473#define IC1_CFG0CLR 0xB1800044 473#define IC1_CFG0CLR 0xB1800044
474 474
475#define IC1_CFG1RD 0xB1800048 475#define IC1_CFG1RD 0xB1800048
476#define IC1_CFG1SET 0xB1800048 476#define IC1_CFG1SET 0xB1800048
477#define IC1_CFG1CLR 0xB180004C 477#define IC1_CFG1CLR 0xB180004C
478 478
479#define IC1_CFG2RD 0xB1800050 479#define IC1_CFG2RD 0xB1800050
480#define IC1_CFG2SET 0xB1800050 480#define IC1_CFG2SET 0xB1800050
481#define IC1_CFG2CLR 0xB1800054 481#define IC1_CFG2CLR 0xB1800054
482 482
483#define IC1_REQ0INT 0xB1800054 483#define IC1_REQ0INT 0xB1800054
484#define IC1_SRCRD 0xB1800058 484#define IC1_SRCRD 0xB1800058
485#define IC1_SRCSET 0xB1800058 485#define IC1_SRCSET 0xB1800058
486#define IC1_SRCCLR 0xB180005C 486#define IC1_SRCCLR 0xB180005C
487#define IC1_REQ1INT 0xB180005C 487#define IC1_REQ1INT 0xB180005C
488 488
489#define IC1_ASSIGNRD 0xB1800060 489#define IC1_ASSIGNRD 0xB1800060
490#define IC1_ASSIGNSET 0xB1800060 490#define IC1_ASSIGNSET 0xB1800060
491#define IC1_ASSIGNCLR 0xB1800064 491#define IC1_ASSIGNCLR 0xB1800064
492 492
493#define IC1_WAKERD 0xB1800068 493#define IC1_WAKERD 0xB1800068
494#define IC1_WAKESET 0xB1800068 494#define IC1_WAKESET 0xB1800068
495#define IC1_WAKECLR 0xB180006C 495#define IC1_WAKECLR 0xB180006C
496 496
497#define IC1_MASKRD 0xB1800070 497#define IC1_MASKRD 0xB1800070
498#define IC1_MASKSET 0xB1800070 498#define IC1_MASKSET 0xB1800070
499#define IC1_MASKCLR 0xB1800074 499#define IC1_MASKCLR 0xB1800074
500 500
501#define IC1_RISINGRD 0xB1800078 501#define IC1_RISINGRD 0xB1800078
502#define IC1_RISINGCLR 0xB1800078 502#define IC1_RISINGCLR 0xB1800078
503#define IC1_FALLINGRD 0xB180007C 503#define IC1_FALLINGRD 0xB180007C
504#define IC1_FALLINGCLR 0xB180007C 504#define IC1_FALLINGCLR 0xB180007C
505 505
506#define IC1_TESTBIT 0xB1800080 506#define IC1_TESTBIT 0xB1800080
507 507
508/* Interrupt Configuration Modes */ 508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0 509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1 510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2 511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3 512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5 513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6 514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516 516
517/* Interrupt Numbers */ 517/* Interrupt Numbers */
518/* Au1000 */ 518/* Au1000 */
@@ -579,18 +579,18 @@ enum soc_au1000_ints {
579 AU1000_GPIO_31, 579 AU1000_GPIO_31,
580}; 580};
581 581
582#define UART0_ADDR 0xB1100000 582#define UART0_ADDR 0xB1100000
583#define UART1_ADDR 0xB1200000 583#define UART1_ADDR 0xB1200000
584#define UART2_ADDR 0xB1300000 584#define UART2_ADDR 0xB1300000
585#define UART3_ADDR 0xB1400000 585#define UART3_ADDR 0xB1400000
586 586
587#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 587#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
588#define USB_HOST_CONFIG 0xB017fffc 588#define USB_HOST_CONFIG 0xB017FFFC
589 589
590#define AU1000_ETH0_BASE 0xB0500000 590#define AU1000_ETH0_BASE 0xB0500000
591#define AU1000_ETH1_BASE 0xB0510000 591#define AU1000_ETH1_BASE 0xB0510000
592#define AU1000_MAC0_ENABLE 0xB0520000 592#define AU1000_MAC0_ENABLE 0xB0520000
593#define AU1000_MAC1_ENABLE 0xB0520004 593#define AU1000_MAC1_ENABLE 0xB0520004
594#define NUM_ETH_INTERFACES 2 594#define NUM_ETH_INTERFACES 2
595#endif /* CONFIG_SOC_AU1000 */ 595#endif /* CONFIG_SOC_AU1000 */
596 596
@@ -615,6 +615,7 @@ enum soc_au1500_ints {
615 AU1000_RTC_MATCH1_INT, 615 AU1000_RTC_MATCH1_INT,
616 AU1000_RTC_MATCH2_INT, 616 AU1000_RTC_MATCH2_INT,
617 AU1500_PCI_ERR_INT, 617 AU1500_PCI_ERR_INT,
618 AU1500_RESERVED_INT,
618 AU1000_USB_DEV_REQ_INT, 619 AU1000_USB_DEV_REQ_INT,
619 AU1000_USB_DEV_SUS_INT, 620 AU1000_USB_DEV_SUS_INT,
620 AU1000_USB_HOST_INT, 621 AU1000_USB_HOST_INT,
@@ -662,16 +663,16 @@ enum soc_au1500_ints {
662#define INTC AU1000_PCI_INTC 663#define INTC AU1000_PCI_INTC
663#define INTD AU1000_PCI_INTD 664#define INTD AU1000_PCI_INTD
664 665
665#define UART0_ADDR 0xB1100000 666#define UART0_ADDR 0xB1100000
666#define UART3_ADDR 0xB1400000 667#define UART3_ADDR 0xB1400000
667 668
668#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 669#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
669#define USB_HOST_CONFIG 0xB017fffc 670#define USB_HOST_CONFIG 0xB017fffc
670 671
671#define AU1500_ETH0_BASE 0xB1500000 672#define AU1500_ETH0_BASE 0xB1500000
672#define AU1500_ETH1_BASE 0xB1510000 673#define AU1500_ETH1_BASE 0xB1510000
673#define AU1500_MAC0_ENABLE 0xB1520000 674#define AU1500_MAC0_ENABLE 0xB1520000
674#define AU1500_MAC1_ENABLE 0xB1520004 675#define AU1500_MAC1_ENABLE 0xB1520004
675#define NUM_ETH_INTERFACES 2 676#define NUM_ETH_INTERFACES 2
676#endif /* CONFIG_SOC_AU1500 */ 677#endif /* CONFIG_SOC_AU1500 */
677 678
@@ -739,15 +740,15 @@ enum soc_au1100_ints {
739 AU1000_GPIO_31, 740 AU1000_GPIO_31,
740}; 741};
741 742
742#define UART0_ADDR 0xB1100000 743#define UART0_ADDR 0xB1100000
743#define UART1_ADDR 0xB1200000 744#define UART1_ADDR 0xB1200000
744#define UART3_ADDR 0xB1400000 745#define UART3_ADDR 0xB1400000
745 746
746#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap 747#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
747#define USB_HOST_CONFIG 0xB017fffc 748#define USB_HOST_CONFIG 0xB017FFFC
748 749
749#define AU1100_ETH0_BASE 0xB0500000 750#define AU1100_ETH0_BASE 0xB0500000
750#define AU1100_MAC0_ENABLE 0xB0520000 751#define AU1100_MAC0_ENABLE 0xB0520000
751#define NUM_ETH_INTERFACES 1 752#define NUM_ETH_INTERFACES 1
752#endif /* CONFIG_SOC_AU1100 */ 753#endif /* CONFIG_SOC_AU1100 */
753 754
@@ -826,18 +827,18 @@ enum soc_au1550_ints {
826#define INTC AU1550_PCI_INTC 827#define INTC AU1550_PCI_INTC
827#define INTD AU1550_PCI_INTD 828#define INTD AU1550_PCI_INTD
828 829
829#define UART0_ADDR 0xB1100000 830#define UART0_ADDR 0xB1100000
830#define UART1_ADDR 0xB1200000 831#define UART1_ADDR 0xB1200000
831#define UART3_ADDR 0xB1400000 832#define UART3_ADDR 0xB1400000
832 833
833#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 834#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
834#define USB_OHCI_LEN 0x00060000 835#define USB_OHCI_LEN 0x00060000
835#define USB_HOST_CONFIG 0xB4027ffc 836#define USB_HOST_CONFIG 0xB4027ffc
836 837
837#define AU1550_ETH0_BASE 0xB0500000 838#define AU1550_ETH0_BASE 0xB0500000
838#define AU1550_ETH1_BASE 0xB0510000 839#define AU1550_ETH1_BASE 0xB0510000
839#define AU1550_MAC0_ENABLE 0xB0520000 840#define AU1550_MAC0_ENABLE 0xB0520000
840#define AU1550_MAC1_ENABLE 0xB0520004 841#define AU1550_MAC1_ENABLE 0xB0520004
841#define NUM_ETH_INTERFACES 2 842#define NUM_ETH_INTERFACES 2
842#endif /* CONFIG_SOC_AU1550 */ 843#endif /* CONFIG_SOC_AU1550 */
843 844
@@ -911,32 +912,32 @@ enum soc_au1200_ints {
911 AU1000_GPIO_31, 912 AU1000_GPIO_31,
912}; 913};
913 914
914#define UART0_ADDR 0xB1100000 915#define UART0_ADDR 0xB1100000
915#define UART1_ADDR 0xB1200000 916#define UART1_ADDR 0xB1200000
916 917
917#define USB_UOC_BASE 0x14020020 918#define USB_UOC_BASE 0x14020020
918#define USB_UOC_LEN 0x20 919#define USB_UOC_LEN 0x20
919#define USB_OHCI_BASE 0x14020100 920#define USB_OHCI_BASE 0x14020100
920#define USB_OHCI_LEN 0x100 921#define USB_OHCI_LEN 0x100
921#define USB_EHCI_BASE 0x14020200 922#define USB_EHCI_BASE 0x14020200
922#define USB_EHCI_LEN 0x100 923#define USB_EHCI_LEN 0x100
923#define USB_UDC_BASE 0x14022000 924#define USB_UDC_BASE 0x14022000
924#define USB_UDC_LEN 0x2000 925#define USB_UDC_LEN 0x2000
925#define USB_MSR_BASE 0xB4020000 926#define USB_MSR_BASE 0xB4020000
926#define USB_MSR_MCFG 4 927#define USB_MSR_MCFG 4
927#define USBMSRMCFG_OMEMEN 0 928#define USBMSRMCFG_OMEMEN 0
928#define USBMSRMCFG_OBMEN 1 929#define USBMSRMCFG_OBMEN 1
929#define USBMSRMCFG_EMEMEN 2 930#define USBMSRMCFG_EMEMEN 2
930#define USBMSRMCFG_EBMEN 3 931#define USBMSRMCFG_EBMEN 3
931#define USBMSRMCFG_DMEMEN 4 932#define USBMSRMCFG_DMEMEN 4
932#define USBMSRMCFG_DBMEN 5 933#define USBMSRMCFG_DBMEN 5
933#define USBMSRMCFG_GMEMEN 6 934#define USBMSRMCFG_GMEMEN 6
934#define USBMSRMCFG_OHCCLKEN 16 935#define USBMSRMCFG_OHCCLKEN 16
935#define USBMSRMCFG_EHCCLKEN 17 936#define USBMSRMCFG_EHCCLKEN 17
936#define USBMSRMCFG_UDCCLKEN 18 937#define USBMSRMCFG_UDCCLKEN 18
937#define USBMSRMCFG_PHYPLLEN 19 938#define USBMSRMCFG_PHYPLLEN 19
938#define USBMSRMCFG_RDCOMB 30 939#define USBMSRMCFG_RDCOMB 30
939#define USBMSRMCFG_PFEN 31 940#define USBMSRMCFG_PFEN 31
940 941
941#endif /* CONFIG_SOC_AU1200 */ 942#endif /* CONFIG_SOC_AU1200 */
942 943
@@ -949,259 +950,258 @@ enum soc_au1200_ints {
949#define INTX 0xFF /* not valid */ 950#define INTX 0xFF /* not valid */
950 951
951/* Programmable Counters 0 and 1 */ 952/* Programmable Counters 0 and 1 */
952#define SYS_BASE 0xB1900000 953#define SYS_BASE 0xB1900000
953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 954#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954# define SYS_CNTRL_E1S (1<<23) 955# define SYS_CNTRL_E1S (1 << 23)
955# define SYS_CNTRL_T1S (1<<20) 956# define SYS_CNTRL_T1S (1 << 20)
956# define SYS_CNTRL_M21 (1<<19) 957# define SYS_CNTRL_M21 (1 << 19)
957# define SYS_CNTRL_M11 (1<<18) 958# define SYS_CNTRL_M11 (1 << 18)
958# define SYS_CNTRL_M01 (1<<17) 959# define SYS_CNTRL_M01 (1 << 17)
959# define SYS_CNTRL_C1S (1<<16) 960# define SYS_CNTRL_C1S (1 << 16)
960# define SYS_CNTRL_BP (1<<14) 961# define SYS_CNTRL_BP (1 << 14)
961# define SYS_CNTRL_EN1 (1<<13) 962# define SYS_CNTRL_EN1 (1 << 13)
962# define SYS_CNTRL_BT1 (1<<12) 963# define SYS_CNTRL_BT1 (1 << 12)
963# define SYS_CNTRL_EN0 (1<<11) 964# define SYS_CNTRL_EN0 (1 << 11)
964# define SYS_CNTRL_BT0 (1<<10) 965# define SYS_CNTRL_BT0 (1 << 10)
965# define SYS_CNTRL_E0 (1<<8) 966# define SYS_CNTRL_E0 (1 << 8)
966# define SYS_CNTRL_E0S (1<<7) 967# define SYS_CNTRL_E0S (1 << 7)
967# define SYS_CNTRL_32S (1<<5) 968# define SYS_CNTRL_32S (1 << 5)
968# define SYS_CNTRL_T0S (1<<4) 969# define SYS_CNTRL_T0S (1 << 4)
969# define SYS_CNTRL_M20 (1<<3) 970# define SYS_CNTRL_M20 (1 << 3)
970# define SYS_CNTRL_M10 (1<<2) 971# define SYS_CNTRL_M10 (1 << 2)
971# define SYS_CNTRL_M00 (1<<1) 972# define SYS_CNTRL_M00 (1 << 1)
972# define SYS_CNTRL_C0S (1<<0) 973# define SYS_CNTRL_C0S (1 << 0)
973 974
974/* Programmable Counter 0 Registers */ 975/* Programmable Counter 0 Registers */
975#define SYS_TOYTRIM (SYS_BASE + 0) 976#define SYS_TOYTRIM (SYS_BASE + 0)
976#define SYS_TOYWRITE (SYS_BASE + 4) 977#define SYS_TOYWRITE (SYS_BASE + 4)
977#define SYS_TOYMATCH0 (SYS_BASE + 8) 978#define SYS_TOYMATCH0 (SYS_BASE + 8)
978#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 979#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
979#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 980#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
980#define SYS_TOYREAD (SYS_BASE + 0x40) 981#define SYS_TOYREAD (SYS_BASE + 0x40)
981 982
982/* Programmable Counter 1 Registers */ 983/* Programmable Counter 1 Registers */
983#define SYS_RTCTRIM (SYS_BASE + 0x44) 984#define SYS_RTCTRIM (SYS_BASE + 0x44)
984#define SYS_RTCWRITE (SYS_BASE + 0x48) 985#define SYS_RTCWRITE (SYS_BASE + 0x48)
985#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 986#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
986#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 987#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
987#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 988#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
988#define SYS_RTCREAD (SYS_BASE + 0x58) 989#define SYS_RTCREAD (SYS_BASE + 0x58)
989 990
990/* I2S Controller */ 991/* I2S Controller */
991#define I2S_DATA 0xB1000000 992#define I2S_DATA 0xB1000000
992# define I2S_DATA_MASK (0xffffff) 993# define I2S_DATA_MASK 0xffffff
993#define I2S_CONFIG 0xB1000004 994#define I2S_CONFIG 0xB1000004
994# define I2S_CONFIG_XU (1<<25) 995# define I2S_CONFIG_XU (1 << 25)
995# define I2S_CONFIG_XO (1<<24) 996# define I2S_CONFIG_XO (1 << 24)
996# define I2S_CONFIG_RU (1<<23) 997# define I2S_CONFIG_RU (1 << 23)
997# define I2S_CONFIG_RO (1<<22) 998# define I2S_CONFIG_RO (1 << 22)
998# define I2S_CONFIG_TR (1<<21) 999# define I2S_CONFIG_TR (1 << 21)
999# define I2S_CONFIG_TE (1<<20) 1000# define I2S_CONFIG_TE (1 << 20)
1000# define I2S_CONFIG_TF (1<<19) 1001# define I2S_CONFIG_TF (1 << 19)
1001# define I2S_CONFIG_RR (1<<18) 1002# define I2S_CONFIG_RR (1 << 18)
1002# define I2S_CONFIG_RE (1<<17) 1003# define I2S_CONFIG_RE (1 << 17)
1003# define I2S_CONFIG_RF (1<<16) 1004# define I2S_CONFIG_RF (1 << 16)
1004# define I2S_CONFIG_PD (1<<11) 1005# define I2S_CONFIG_PD (1 << 11)
1005# define I2S_CONFIG_LB (1<<10) 1006# define I2S_CONFIG_LB (1 << 10)
1006# define I2S_CONFIG_IC (1<<9) 1007# define I2S_CONFIG_IC (1 << 9)
1007# define I2S_CONFIG_FM_BIT 7 1008# define I2S_CONFIG_FM_BIT 7
1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1009# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1012# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012# define I2S_CONFIG_TN (1<<6) 1013# define I2S_CONFIG_TN (1 << 6)
1013# define I2S_CONFIG_RN (1<<5) 1014# define I2S_CONFIG_RN (1 << 5)
1014# define I2S_CONFIG_SZ_BIT 0 1015# define I2S_CONFIG_SZ_BIT 0
1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1016# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1016 1017
1017#define I2S_CONTROL 0xB1000008 1018#define I2S_CONTROL 0xB1000008
1018# define I2S_CONTROL_D (1<<1) 1019# define I2S_CONTROL_D (1 << 1)
1019# define I2S_CONTROL_CE (1<<0) 1020# define I2S_CONTROL_CE (1 << 0)
1020 1021
1021/* USB Host Controller */ 1022/* USB Host Controller */
1022#ifndef USB_OHCI_LEN 1023#ifndef USB_OHCI_LEN
1023#define USB_OHCI_LEN 0x00100000 1024#define USB_OHCI_LEN 0x00100000
1024#endif 1025#endif
1025 1026
1026#ifndef CONFIG_SOC_AU1200 1027#ifndef CONFIG_SOC_AU1200
1027 1028
1028/* USB Device Controller */ 1029/* USB Device Controller */
1029#define USBD_EP0RD 0xB0200000 1030#define USBD_EP0RD 0xB0200000
1030#define USBD_EP0WR 0xB0200004 1031#define USBD_EP0WR 0xB0200004
1031#define USBD_EP2WR 0xB0200008 1032#define USBD_EP2WR 0xB0200008
1032#define USBD_EP3WR 0xB020000C 1033#define USBD_EP3WR 0xB020000C
1033#define USBD_EP4RD 0xB0200010 1034#define USBD_EP4RD 0xB0200010
1034#define USBD_EP5RD 0xB0200014 1035#define USBD_EP5RD 0xB0200014
1035#define USBD_INTEN 0xB0200018 1036#define USBD_INTEN 0xB0200018
1036#define USBD_INTSTAT 0xB020001C 1037#define USBD_INTSTAT 0xB020001C
1037# define USBDEV_INT_SOF (1<<12) 1038# define USBDEV_INT_SOF (1 << 12)
1038# define USBDEV_INT_HF_BIT 6 1039# define USBDEV_INT_HF_BIT 6
1039# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1040# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1040# define USBDEV_INT_CMPLT_BIT 0 1041# define USBDEV_INT_CMPLT_BIT 0
1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1042# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042#define USBD_CONFIG 0xB0200020 1043#define USBD_CONFIG 0xB0200020
1043#define USBD_EP0CS 0xB0200024 1044#define USBD_EP0CS 0xB0200024
1044#define USBD_EP2CS 0xB0200028 1045#define USBD_EP2CS 0xB0200028
1045#define USBD_EP3CS 0xB020002C 1046#define USBD_EP3CS 0xB020002C
1046#define USBD_EP4CS 0xB0200030 1047#define USBD_EP4CS 0xB0200030
1047#define USBD_EP5CS 0xB0200034 1048#define USBD_EP5CS 0xB0200034
1048# define USBDEV_CS_SU (1<<14) 1049# define USBDEV_CS_SU (1 << 14)
1049# define USBDEV_CS_NAK (1<<13) 1050# define USBDEV_CS_NAK (1 << 13)
1050# define USBDEV_CS_ACK (1<<12) 1051# define USBDEV_CS_ACK (1 << 12)
1051# define USBDEV_CS_BUSY (1<<11) 1052# define USBDEV_CS_BUSY (1 << 11)
1052# define USBDEV_CS_TSIZE_BIT 1 1053# define USBDEV_CS_TSIZE_BIT 1
1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1054# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054# define USBDEV_CS_STALL (1<<0) 1055# define USBDEV_CS_STALL (1 << 0)
1055#define USBD_EP0RDSTAT 0xB0200040 1056#define USBD_EP0RDSTAT 0xB0200040
1056#define USBD_EP0WRSTAT 0xB0200044 1057#define USBD_EP0WRSTAT 0xB0200044
1057#define USBD_EP2WRSTAT 0xB0200048 1058#define USBD_EP2WRSTAT 0xB0200048
1058#define USBD_EP3WRSTAT 0xB020004C 1059#define USBD_EP3WRSTAT 0xB020004C
1059#define USBD_EP4RDSTAT 0xB0200050 1060#define USBD_EP4RDSTAT 0xB0200050
1060#define USBD_EP5RDSTAT 0xB0200054 1061#define USBD_EP5RDSTAT 0xB0200054
1061# define USBDEV_FSTAT_FLUSH (1<<6) 1062# define USBDEV_FSTAT_FLUSH (1 << 6)
1062# define USBDEV_FSTAT_UF (1<<5) 1063# define USBDEV_FSTAT_UF (1 << 5)
1063# define USBDEV_FSTAT_OF (1<<4) 1064# define USBDEV_FSTAT_OF (1 << 4)
1064# define USBDEV_FSTAT_FCNT_BIT 0 1065# define USBDEV_FSTAT_FCNT_BIT 0
1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1066# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066#define USBD_ENABLE 0xB0200058 1067#define USBD_ENABLE 0xB0200058
1067# define USBDEV_ENABLE (1<<1) 1068# define USBDEV_ENABLE (1 << 1)
1068# define USBDEV_CE (1<<0) 1069# define USBDEV_CE (1 << 0)
1069 1070
1070#endif /* !CONFIG_SOC_AU1200 */ 1071#endif /* !CONFIG_SOC_AU1200 */
1071 1072
1072/* Ethernet Controllers */ 1073/* Ethernet Controllers */
1073 1074
1074/* 4 byte offsets from AU1000_ETH_BASE */ 1075/* 4 byte offsets from AU1000_ETH_BASE */
1075#define MAC_CONTROL 0x0 1076#define MAC_CONTROL 0x0
1076# define MAC_RX_ENABLE (1<<2) 1077# define MAC_RX_ENABLE (1 << 2)
1077# define MAC_TX_ENABLE (1<<3) 1078# define MAC_TX_ENABLE (1 << 3)
1078# define MAC_DEF_CHECK (1<<5) 1079# define MAC_DEF_CHECK (1 << 5)
1079# define MAC_SET_BL(X) (((X)&0x3)<<6) 1080# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1080# define MAC_AUTO_PAD (1<<8) 1081# define MAC_AUTO_PAD (1 << 8)
1081# define MAC_DISABLE_RETRY (1<<10) 1082# define MAC_DISABLE_RETRY (1 << 10)
1082# define MAC_DISABLE_BCAST (1<<11) 1083# define MAC_DISABLE_BCAST (1 << 11)
1083# define MAC_LATE_COL (1<<12) 1084# define MAC_LATE_COL (1 << 12)
1084# define MAC_HASH_MODE (1<<13) 1085# define MAC_HASH_MODE (1 << 13)
1085# define MAC_HASH_ONLY (1<<15) 1086# define MAC_HASH_ONLY (1 << 15)
1086# define MAC_PASS_ALL (1<<16) 1087# define MAC_PASS_ALL (1 << 16)
1087# define MAC_INVERSE_FILTER (1<<17) 1088# define MAC_INVERSE_FILTER (1 << 17)
1088# define MAC_PROMISCUOUS (1<<18) 1089# define MAC_PROMISCUOUS (1 << 18)
1089# define MAC_PASS_ALL_MULTI (1<<19) 1090# define MAC_PASS_ALL_MULTI (1 << 19)
1090# define MAC_FULL_DUPLEX (1<<20) 1091# define MAC_FULL_DUPLEX (1 << 20)
1091# define MAC_NORMAL_MODE 0 1092# define MAC_NORMAL_MODE 0
1092# define MAC_INT_LOOPBACK (1<<21) 1093# define MAC_INT_LOOPBACK (1 << 21)
1093# define MAC_EXT_LOOPBACK (1<<22) 1094# define MAC_EXT_LOOPBACK (1 << 22)
1094# define MAC_DISABLE_RX_OWN (1<<23) 1095# define MAC_DISABLE_RX_OWN (1 << 23)
1095# define MAC_BIG_ENDIAN (1<<30) 1096# define MAC_BIG_ENDIAN (1 << 30)
1096# define MAC_RX_ALL (1<<31) 1097# define MAC_RX_ALL (1 << 31)
1097#define MAC_ADDRESS_HIGH 0x4 1098#define MAC_ADDRESS_HIGH 0x4
1098#define MAC_ADDRESS_LOW 0x8 1099#define MAC_ADDRESS_LOW 0x8
1099#define MAC_MCAST_HIGH 0xC 1100#define MAC_MCAST_HIGH 0xC
1100#define MAC_MCAST_LOW 0x10 1101#define MAC_MCAST_LOW 0x10
1101#define MAC_MII_CNTRL 0x14 1102#define MAC_MII_CNTRL 0x14
1102# define MAC_MII_BUSY (1<<0) 1103# define MAC_MII_BUSY (1 << 0)
1103# define MAC_MII_READ 0 1104# define MAC_MII_READ 0
1104# define MAC_MII_WRITE (1<<1) 1105# define MAC_MII_WRITE (1 << 1)
1105# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1106# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1106# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1107# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1107#define MAC_MII_DATA 0x18 1108#define MAC_MII_DATA 0x18
1108#define MAC_FLOW_CNTRL 0x1C 1109#define MAC_FLOW_CNTRL 0x1C
1109# define MAC_FLOW_CNTRL_BUSY (1<<0) 1110# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1110# define MAC_FLOW_CNTRL_ENABLE (1<<1) 1111# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1111# define MAC_PASS_CONTROL (1<<2) 1112# define MAC_PASS_CONTROL (1 << 2)
1112# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1113# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1113#define MAC_VLAN1_TAG 0x20 1114#define MAC_VLAN1_TAG 0x20
1114#define MAC_VLAN2_TAG 0x24 1115#define MAC_VLAN2_TAG 0x24
1115 1116
1116/* Ethernet Controller Enable */ 1117/* Ethernet Controller Enable */
1117 1118
1118# define MAC_EN_CLOCK_ENABLE (1<<0) 1119# define MAC_EN_CLOCK_ENABLE (1 << 0)
1119# define MAC_EN_RESET0 (1<<1) 1120# define MAC_EN_RESET0 (1 << 1)
1120# define MAC_EN_TOSS (0<<2) 1121# define MAC_EN_TOSS (0 << 2)
1121# define MAC_EN_CACHEABLE (1<<3) 1122# define MAC_EN_CACHEABLE (1 << 3)
1122# define MAC_EN_RESET1 (1<<4) 1123# define MAC_EN_RESET1 (1 << 4)
1123# define MAC_EN_RESET2 (1<<5) 1124# define MAC_EN_RESET2 (1 << 5)
1124# define MAC_DMA_RESET (1<<6) 1125# define MAC_DMA_RESET (1 << 6)
1125 1126
1126/* Ethernet Controller DMA Channels */ 1127/* Ethernet Controller DMA Channels */
1127 1128
1128#define MAC0_TX_DMA_ADDR 0xB4004000 1129#define MAC0_TX_DMA_ADDR 0xB4004000
1129#define MAC1_TX_DMA_ADDR 0xB4004200 1130#define MAC1_TX_DMA_ADDR 0xB4004200
1130/* offsets from MAC_TX_RING_ADDR address */ 1131/* offsets from MAC_TX_RING_ADDR address */
1131#define MAC_TX_BUFF0_STATUS 0x0 1132#define MAC_TX_BUFF0_STATUS 0x0
1132# define TX_FRAME_ABORTED (1<<0) 1133# define TX_FRAME_ABORTED (1 << 0)
1133# define TX_JAB_TIMEOUT (1<<1) 1134# define TX_JAB_TIMEOUT (1 << 1)
1134# define TX_NO_CARRIER (1<<2) 1135# define TX_NO_CARRIER (1 << 2)
1135# define TX_LOSS_CARRIER (1<<3) 1136# define TX_LOSS_CARRIER (1 << 3)
1136# define TX_EXC_DEF (1<<4) 1137# define TX_EXC_DEF (1 << 4)
1137# define TX_LATE_COLL_ABORT (1<<5) 1138# define TX_LATE_COLL_ABORT (1 << 5)
1138# define TX_EXC_COLL (1<<6) 1139# define TX_EXC_COLL (1 << 6)
1139# define TX_UNDERRUN (1<<7) 1140# define TX_UNDERRUN (1 << 7)
1140# define TX_DEFERRED (1<<8) 1141# define TX_DEFERRED (1 << 8)
1141# define TX_LATE_COLL (1<<9) 1142# define TX_LATE_COLL (1 << 9)
1142# define TX_COLL_CNT_MASK (0xF<<10) 1143# define TX_COLL_CNT_MASK (0xF << 10)
1143# define TX_PKT_RETRY (1<<31) 1144# define TX_PKT_RETRY (1 << 31)
1144#define MAC_TX_BUFF0_ADDR 0x4 1145#define MAC_TX_BUFF0_ADDR 0x4
1145# define TX_DMA_ENABLE (1<<0) 1146# define TX_DMA_ENABLE (1 << 0)
1146# define TX_T_DONE (1<<1) 1147# define TX_T_DONE (1 << 1)
1147# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1148# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1148#define MAC_TX_BUFF0_LEN 0x8 1149#define MAC_TX_BUFF0_LEN 0x8
1149#define MAC_TX_BUFF1_STATUS 0x10 1150#define MAC_TX_BUFF1_STATUS 0x10
1150#define MAC_TX_BUFF1_ADDR 0x14 1151#define MAC_TX_BUFF1_ADDR 0x14
1151#define MAC_TX_BUFF1_LEN 0x18 1152#define MAC_TX_BUFF1_LEN 0x18
1152#define MAC_TX_BUFF2_STATUS 0x20 1153#define MAC_TX_BUFF2_STATUS 0x20
1153#define MAC_TX_BUFF2_ADDR 0x24 1154#define MAC_TX_BUFF2_ADDR 0x24
1154#define MAC_TX_BUFF2_LEN 0x28 1155#define MAC_TX_BUFF2_LEN 0x28
1155#define MAC_TX_BUFF3_STATUS 0x30 1156#define MAC_TX_BUFF3_STATUS 0x30
1156#define MAC_TX_BUFF3_ADDR 0x34 1157#define MAC_TX_BUFF3_ADDR 0x34
1157#define MAC_TX_BUFF3_LEN 0x38 1158#define MAC_TX_BUFF3_LEN 0x38
1158 1159
1159#define MAC0_RX_DMA_ADDR 0xB4004100 1160#define MAC0_RX_DMA_ADDR 0xB4004100
1160#define MAC1_RX_DMA_ADDR 0xB4004300 1161#define MAC1_RX_DMA_ADDR 0xB4004300
1161/* offsets from MAC_RX_RING_ADDR */ 1162/* offsets from MAC_RX_RING_ADDR */
1162#define MAC_RX_BUFF0_STATUS 0x0 1163#define MAC_RX_BUFF0_STATUS 0x0
1163# define RX_FRAME_LEN_MASK 0x3fff 1164# define RX_FRAME_LEN_MASK 0x3fff
1164# define RX_WDOG_TIMER (1<<14) 1165# define RX_WDOG_TIMER (1 << 14)
1165# define RX_RUNT (1<<15) 1166# define RX_RUNT (1 << 15)
1166# define RX_OVERLEN (1<<16) 1167# define RX_OVERLEN (1 << 16)
1167# define RX_COLL (1<<17) 1168# define RX_COLL (1 << 17)
1168# define RX_ETHER (1<<18) 1169# define RX_ETHER (1 << 18)
1169# define RX_MII_ERROR (1<<19) 1170# define RX_MII_ERROR (1 << 19)
1170# define RX_DRIBBLING (1<<20) 1171# define RX_DRIBBLING (1 << 20)
1171# define RX_CRC_ERROR (1<<21) 1172# define RX_CRC_ERROR (1 << 21)
1172# define RX_VLAN1 (1<<22) 1173# define RX_VLAN1 (1 << 22)
1173# define RX_VLAN2 (1<<23) 1174# define RX_VLAN2 (1 << 23)
1174# define RX_LEN_ERROR (1<<24) 1175# define RX_LEN_ERROR (1 << 24)
1175# define RX_CNTRL_FRAME (1<<25) 1176# define RX_CNTRL_FRAME (1 << 25)
1176# define RX_U_CNTRL_FRAME (1<<26) 1177# define RX_U_CNTRL_FRAME (1 << 26)
1177# define RX_MCAST_FRAME (1<<27) 1178# define RX_MCAST_FRAME (1 << 27)
1178# define RX_BCAST_FRAME (1<<28) 1179# define RX_BCAST_FRAME (1 << 28)
1179# define RX_FILTER_FAIL (1<<29) 1180# define RX_FILTER_FAIL (1 << 29)
1180# define RX_PACKET_FILTER (1<<30) 1181# define RX_PACKET_FILTER (1 << 30)
1181# define RX_MISSED_FRAME (1<<31) 1182# define RX_MISSED_FRAME (1 << 31)
1182 1183
1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1184# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1185 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1186 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186#define MAC_RX_BUFF0_ADDR 0x4 1187#define MAC_RX_BUFF0_ADDR 0x4
1187# define RX_DMA_ENABLE (1<<0) 1188# define RX_DMA_ENABLE (1 << 0)
1188# define RX_T_DONE (1<<1) 1189# define RX_T_DONE (1 << 1)
1189# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1190# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1190# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1191# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1191#define MAC_RX_BUFF1_STATUS 0x10 1192#define MAC_RX_BUFF1_STATUS 0x10
1192#define MAC_RX_BUFF1_ADDR 0x14 1193#define MAC_RX_BUFF1_ADDR 0x14
1193#define MAC_RX_BUFF2_STATUS 0x20 1194#define MAC_RX_BUFF2_STATUS 0x20
1194#define MAC_RX_BUFF2_ADDR 0x24 1195#define MAC_RX_BUFF2_ADDR 0x24
1195#define MAC_RX_BUFF3_STATUS 0x30 1196#define MAC_RX_BUFF3_STATUS 0x30
1196#define MAC_RX_BUFF3_ADDR 0x34 1197#define MAC_RX_BUFF3_ADDR 0x34
1197
1198 1198
1199/* UARTS 0-3 */ 1199/* UARTS 0-3 */
1200#define UART_BASE UART0_ADDR 1200#define UART_BASE UART0_ADDR
1201#ifdef CONFIG_SOC_AU1200 1201#ifdef CONFIG_SOC_AU1200
1202#define UART_DEBUG_BASE UART1_ADDR 1202#define UART_DEBUG_BASE UART1_ADDR
1203#else 1203#else
1204#define UART_DEBUG_BASE UART3_ADDR 1204#define UART_DEBUG_BASE UART3_ADDR
1205#endif 1205#endif
1206 1206
1207#define UART_RX 0 /* Receive buffer */ 1207#define UART_RX 0 /* Receive buffer */
@@ -1294,341 +1294,337 @@ enum soc_au1200_ints {
1294#define UART_MSR_DCTS 0x01 /* Delta CTS */ 1294#define UART_MSR_DCTS 0x01 /* Delta CTS */
1295#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 1295#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1296 1296
1297
1298
1299/* SSIO */ 1297/* SSIO */
1300#define SSI0_STATUS 0xB1600000 1298#define SSI0_STATUS 0xB1600000
1301# define SSI_STATUS_BF (1<<4) 1299# define SSI_STATUS_BF (1 << 4)
1302# define SSI_STATUS_OF (1<<3) 1300# define SSI_STATUS_OF (1 << 3)
1303# define SSI_STATUS_UF (1<<2) 1301# define SSI_STATUS_UF (1 << 2)
1304# define SSI_STATUS_D (1<<1) 1302# define SSI_STATUS_D (1 << 1)
1305# define SSI_STATUS_B (1<<0) 1303# define SSI_STATUS_B (1 << 0)
1306#define SSI0_INT 0xB1600004 1304#define SSI0_INT 0xB1600004
1307# define SSI_INT_OI (1<<3) 1305# define SSI_INT_OI (1 << 3)
1308# define SSI_INT_UI (1<<2) 1306# define SSI_INT_UI (1 << 2)
1309# define SSI_INT_DI (1<<1) 1307# define SSI_INT_DI (1 << 1)
1310#define SSI0_INT_ENABLE 0xB1600008 1308#define SSI0_INT_ENABLE 0xB1600008
1311# define SSI_INTE_OIE (1<<3) 1309# define SSI_INTE_OIE (1 << 3)
1312# define SSI_INTE_UIE (1<<2) 1310# define SSI_INTE_UIE (1 << 2)
1313# define SSI_INTE_DIE (1<<1) 1311# define SSI_INTE_DIE (1 << 1)
1314#define SSI0_CONFIG 0xB1600020 1312#define SSI0_CONFIG 0xB1600020
1315# define SSI_CONFIG_AO (1<<24) 1313# define SSI_CONFIG_AO (1 << 24)
1316# define SSI_CONFIG_DO (1<<23) 1314# define SSI_CONFIG_DO (1 << 23)
1317# define SSI_CONFIG_ALEN_BIT 20 1315# define SSI_CONFIG_ALEN_BIT 20
1318# define SSI_CONFIG_ALEN_MASK (0x7<<20) 1316# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1319# define SSI_CONFIG_DLEN_BIT 16 1317# define SSI_CONFIG_DLEN_BIT 16
1320# define SSI_CONFIG_DLEN_MASK (0x7<<16) 1318# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1321# define SSI_CONFIG_DD (1<<11) 1319# define SSI_CONFIG_DD (1 << 11)
1322# define SSI_CONFIG_AD (1<<10) 1320# define SSI_CONFIG_AD (1 << 10)
1323# define SSI_CONFIG_BM_BIT 8 1321# define SSI_CONFIG_BM_BIT 8
1324# define SSI_CONFIG_BM_MASK (0x3<<8) 1322# define SSI_CONFIG_BM_MASK (0x3 << 8)
1325# define SSI_CONFIG_CE (1<<7) 1323# define SSI_CONFIG_CE (1 << 7)
1326# define SSI_CONFIG_DP (1<<6) 1324# define SSI_CONFIG_DP (1 << 6)
1327# define SSI_CONFIG_DL (1<<5) 1325# define SSI_CONFIG_DL (1 << 5)
1328# define SSI_CONFIG_EP (1<<4) 1326# define SSI_CONFIG_EP (1 << 4)
1329#define SSI0_ADATA 0xB1600024 1327#define SSI0_ADATA 0xB1600024
1330# define SSI_AD_D (1<<24) 1328# define SSI_AD_D (1 << 24)
1331# define SSI_AD_ADDR_BIT 16 1329# define SSI_AD_ADDR_BIT 16
1332# define SSI_AD_ADDR_MASK (0xff<<16) 1330# define SSI_AD_ADDR_MASK (0xff << 16)
1333# define SSI_AD_DATA_BIT 0 1331# define SSI_AD_DATA_BIT 0
1334# define SSI_AD_DATA_MASK (0xfff<<0) 1332# define SSI_AD_DATA_MASK (0xfff << 0)
1335#define SSI0_CLKDIV 0xB1600028 1333#define SSI0_CLKDIV 0xB1600028
1336#define SSI0_CONTROL 0xB1600100 1334#define SSI0_CONTROL 0xB1600100
1337# define SSI_CONTROL_CD (1<<1) 1335# define SSI_CONTROL_CD (1 << 1)
1338# define SSI_CONTROL_E (1<<0) 1336# define SSI_CONTROL_E (1 << 0)
1339 1337
1340/* SSI1 */ 1338/* SSI1 */
1341#define SSI1_STATUS 0xB1680000 1339#define SSI1_STATUS 0xB1680000
1342#define SSI1_INT 0xB1680004 1340#define SSI1_INT 0xB1680004
1343#define SSI1_INT_ENABLE 0xB1680008 1341#define SSI1_INT_ENABLE 0xB1680008
1344#define SSI1_CONFIG 0xB1680020 1342#define SSI1_CONFIG 0xB1680020
1345#define SSI1_ADATA 0xB1680024 1343#define SSI1_ADATA 0xB1680024
1346#define SSI1_CLKDIV 0xB1680028 1344#define SSI1_CLKDIV 0xB1680028
1347#define SSI1_ENABLE 0xB1680100 1345#define SSI1_ENABLE 0xB1680100
1348 1346
1349/* 1347/*
1350 * Register content definitions 1348 * Register content definitions
1351 */ 1349 */
1352#define SSI_STATUS_BF (1<<4) 1350#define SSI_STATUS_BF (1 << 4)
1353#define SSI_STATUS_OF (1<<3) 1351#define SSI_STATUS_OF (1 << 3)
1354#define SSI_STATUS_UF (1<<2) 1352#define SSI_STATUS_UF (1 << 2)
1355#define SSI_STATUS_D (1<<1) 1353#define SSI_STATUS_D (1 << 1)
1356#define SSI_STATUS_B (1<<0) 1354#define SSI_STATUS_B (1 << 0)
1357 1355
1358/* SSI_INT */ 1356/* SSI_INT */
1359#define SSI_INT_OI (1<<3) 1357#define SSI_INT_OI (1 << 3)
1360#define SSI_INT_UI (1<<2) 1358#define SSI_INT_UI (1 << 2)
1361#define SSI_INT_DI (1<<1) 1359#define SSI_INT_DI (1 << 1)
1362 1360
1363/* SSI_INTEN */ 1361/* SSI_INTEN */
1364#define SSI_INTEN_OIE (1<<3) 1362#define SSI_INTEN_OIE (1 << 3)
1365#define SSI_INTEN_UIE (1<<2) 1363#define SSI_INTEN_UIE (1 << 2)
1366#define SSI_INTEN_DIE (1<<1) 1364#define SSI_INTEN_DIE (1 << 1)
1367 1365
1368#define SSI_CONFIG_AO (1<<24) 1366#define SSI_CONFIG_AO (1 << 24)
1369#define SSI_CONFIG_DO (1<<23) 1367#define SSI_CONFIG_DO (1 << 23)
1370#define SSI_CONFIG_ALEN (7<<20) 1368#define SSI_CONFIG_ALEN (7 << 20)
1371#define SSI_CONFIG_DLEN (15<<16) 1369#define SSI_CONFIG_DLEN (15 << 16)
1372#define SSI_CONFIG_DD (1<<11) 1370#define SSI_CONFIG_DD (1 << 11)
1373#define SSI_CONFIG_AD (1<<10) 1371#define SSI_CONFIG_AD (1 << 10)
1374#define SSI_CONFIG_BM (3<<8) 1372#define SSI_CONFIG_BM (3 << 8)
1375#define SSI_CONFIG_CE (1<<7) 1373#define SSI_CONFIG_CE (1 << 7)
1376#define SSI_CONFIG_DP (1<<6) 1374#define SSI_CONFIG_DP (1 << 6)
1377#define SSI_CONFIG_DL (1<<5) 1375#define SSI_CONFIG_DL (1 << 5)
1378#define SSI_CONFIG_EP (1<<4) 1376#define SSI_CONFIG_EP (1 << 4)
1379#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) 1377#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1380#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) 1378#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1381#define SSI_CONFIG_BM_HI (0<<8) 1379#define SSI_CONFIG_BM_HI (0 << 8)
1382#define SSI_CONFIG_BM_LO (1<<8) 1380#define SSI_CONFIG_BM_LO (1 << 8)
1383#define SSI_CONFIG_BM_CY (2<<8) 1381#define SSI_CONFIG_BM_CY (2 << 8)
1384 1382
1385#define SSI_ADATA_D (1<<24) 1383#define SSI_ADATA_D (1 << 24)
1386#define SSI_ADATA_ADDR (0xFF<<16) 1384#define SSI_ADATA_ADDR (0xFF << 16)
1387#define SSI_ADATA_DATA (0x0FFF) 1385#define SSI_ADATA_DATA 0x0FFF
1388#define SSI_ADATA_ADDR_N(N) (N<<16) 1386#define SSI_ADATA_ADDR_N(N) (N << 16)
1389 1387
1390#define SSI_ENABLE_CD (1<<1) 1388#define SSI_ENABLE_CD (1 << 1)
1391#define SSI_ENABLE_E (1<<0) 1389#define SSI_ENABLE_E (1 << 0)
1392
1393 1390
1394/* IrDA Controller */ 1391/* IrDA Controller */
1395#define IRDA_BASE 0xB0300000 1392#define IRDA_BASE 0xB0300000
1396#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) 1393#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1397#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) 1394#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1398#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) 1395#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1399#define IR_RING_SIZE (IRDA_BASE+0x0C) 1396#define IR_RING_SIZE (IRDA_BASE + 0x0C)
1400#define IR_RING_PROMPT (IRDA_BASE+0x10) 1397#define IR_RING_PROMPT (IRDA_BASE + 0x10)
1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1398#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1402#define IR_INT_CLEAR (IRDA_BASE+0x18) 1399#define IR_INT_CLEAR (IRDA_BASE + 0x18)
1403#define IR_CONFIG_1 (IRDA_BASE+0x20) 1400#define IR_CONFIG_1 (IRDA_BASE + 0x20)
1404# define IR_RX_INVERT_LED (1<<0) 1401# define IR_RX_INVERT_LED (1 << 0)
1405# define IR_TX_INVERT_LED (1<<1) 1402# define IR_TX_INVERT_LED (1 << 1)
1406# define IR_ST (1<<2) 1403# define IR_ST (1 << 2)
1407# define IR_SF (1<<3) 1404# define IR_SF (1 << 3)
1408# define IR_SIR (1<<4) 1405# define IR_SIR (1 << 4)
1409# define IR_MIR (1<<5) 1406# define IR_MIR (1 << 5)
1410# define IR_FIR (1<<6) 1407# define IR_FIR (1 << 6)
1411# define IR_16CRC (1<<7) 1408# define IR_16CRC (1 << 7)
1412# define IR_TD (1<<8) 1409# define IR_TD (1 << 8)
1413# define IR_RX_ALL (1<<9) 1410# define IR_RX_ALL (1 << 9)
1414# define IR_DMA_ENABLE (1<<10) 1411# define IR_DMA_ENABLE (1 << 10)
1415# define IR_RX_ENABLE (1<<11) 1412# define IR_RX_ENABLE (1 << 11)
1416# define IR_TX_ENABLE (1<<12) 1413# define IR_TX_ENABLE (1 << 12)
1417# define IR_LOOPBACK (1<<14) 1414# define IR_LOOPBACK (1 << 14)
1418# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1415# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1416 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1417#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1421#define IR_ENABLE (IRDA_BASE+0x28) 1418#define IR_ENABLE (IRDA_BASE + 0x28)
1422# define IR_RX_STATUS (1<<9) 1419# define IR_RX_STATUS (1 << 9)
1423# define IR_TX_STATUS (1<<10) 1420# define IR_TX_STATUS (1 << 10)
1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1421#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1422#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1423#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1424#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1428#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1425#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1429# define IR_MODE_INV (1<<0) 1426# define IR_MODE_INV (1 << 0)
1430# define IR_ONE_PIN (1<<1) 1427# define IR_ONE_PIN (1 << 1)
1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1428#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1432 1429
1433/* GPIO */ 1430/* GPIO */
1434#define SYS_PINFUNC 0xB190002C 1431#define SYS_PINFUNC 0xB190002C
1435# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1432# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1436# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1433# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1437# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1434# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1438# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1435# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1439# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1436# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1440# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1437# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1441# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1438# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1442# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1439# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1443# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1440# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1444# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1441# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1445# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1442# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1446# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1443# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1447# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1444# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1448# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1445# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1449# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1446# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1450# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1447# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1451 1448
1452/* Au1100 Only */ 1449/* Au1100 only */
1453# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1450# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1454# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1451# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1455# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1452# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1456# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1453# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1457 1454
1458/* Au1550 Only. Redefines lots of pins */ 1455/* Au1550 only. Redefines lots of pins */
1459# define SYS_PF_PSC2_MASK (7 << 17) 1456# define SYS_PF_PSC2_MASK (7 << 17)
1460# define SYS_PF_PSC2_AC97 (0) 1457# define SYS_PF_PSC2_AC97 0
1461# define SYS_PF_PSC2_SPI (0) 1458# define SYS_PF_PSC2_SPI 0
1462# define SYS_PF_PSC2_I2S (1 << 17) 1459# define SYS_PF_PSC2_I2S (1 << 17)
1463# define SYS_PF_PSC2_SMBUS (3 << 17) 1460# define SYS_PF_PSC2_SMBUS (3 << 17)
1464# define SYS_PF_PSC2_GPIO (7 << 17) 1461# define SYS_PF_PSC2_GPIO (7 << 17)
1465# define SYS_PF_PSC3_MASK (7 << 20) 1462# define SYS_PF_PSC3_MASK (7 << 20)
1466# define SYS_PF_PSC3_AC97 (0) 1463# define SYS_PF_PSC3_AC97 0
1467# define SYS_PF_PSC3_SPI (0) 1464# define SYS_PF_PSC3_SPI 0
1468# define SYS_PF_PSC3_I2S (1 << 20) 1465# define SYS_PF_PSC3_I2S (1 << 20)
1469# define SYS_PF_PSC3_SMBUS (3 << 20) 1466# define SYS_PF_PSC3_SMBUS (3 << 20)
1470# define SYS_PF_PSC3_GPIO (7 << 20) 1467# define SYS_PF_PSC3_GPIO (7 << 20)
1471# define SYS_PF_PSC1_S1 (1 << 1) 1468# define SYS_PF_PSC1_S1 (1 << 1)
1472# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1469# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1473 1470
1474/* Au1200 Only */ 1471/* Au1200 only */
1475#ifdef CONFIG_SOC_AU1200 1472#ifdef CONFIG_SOC_AU1200
1476#define SYS_PINFUNC_DMA (1<<31) 1473#define SYS_PINFUNC_DMA (1 << 31)
1477#define SYS_PINFUNC_S0A (1<<30) 1474#define SYS_PINFUNC_S0A (1 << 30)
1478#define SYS_PINFUNC_S1A (1<<29) 1475#define SYS_PINFUNC_S1A (1 << 29)
1479#define SYS_PINFUNC_LP0 (1<<28) 1476#define SYS_PINFUNC_LP0 (1 << 28)
1480#define SYS_PINFUNC_LP1 (1<<27) 1477#define SYS_PINFUNC_LP1 (1 << 27)
1481#define SYS_PINFUNC_LD16 (1<<26) 1478#define SYS_PINFUNC_LD16 (1 << 26)
1482#define SYS_PINFUNC_LD8 (1<<25) 1479#define SYS_PINFUNC_LD8 (1 << 25)
1483#define SYS_PINFUNC_LD1 (1<<24) 1480#define SYS_PINFUNC_LD1 (1 << 24)
1484#define SYS_PINFUNC_LD0 (1<<23) 1481#define SYS_PINFUNC_LD0 (1 << 23)
1485#define SYS_PINFUNC_P1A (3<<21) 1482#define SYS_PINFUNC_P1A (3 << 21)
1486#define SYS_PINFUNC_P1B (1<<20) 1483#define SYS_PINFUNC_P1B (1 << 20)
1487#define SYS_PINFUNC_FS3 (1<<19) 1484#define SYS_PINFUNC_FS3 (1 << 19)
1488#define SYS_PINFUNC_P0A (3<<17) 1485#define SYS_PINFUNC_P0A (3 << 17)
1489#define SYS_PINFUNC_CS (1<<16) 1486#define SYS_PINFUNC_CS (1 << 16)
1490#define SYS_PINFUNC_CIM (1<<15) 1487#define SYS_PINFUNC_CIM (1 << 15)
1491#define SYS_PINFUNC_P1C (1<<14) 1488#define SYS_PINFUNC_P1C (1 << 14)
1492#define SYS_PINFUNC_U1T (1<<12) 1489#define SYS_PINFUNC_U1T (1 << 12)
1493#define SYS_PINFUNC_U1R (1<<11) 1490#define SYS_PINFUNC_U1R (1 << 11)
1494#define SYS_PINFUNC_EX1 (1<<10) 1491#define SYS_PINFUNC_EX1 (1 << 10)
1495#define SYS_PINFUNC_EX0 (1<<9) 1492#define SYS_PINFUNC_EX0 (1 << 9)
1496#define SYS_PINFUNC_U0R (1<<8) 1493#define SYS_PINFUNC_U0R (1 << 8)
1497#define SYS_PINFUNC_MC (1<<7) 1494#define SYS_PINFUNC_MC (1 << 7)
1498#define SYS_PINFUNC_S0B (1<<6) 1495#define SYS_PINFUNC_S0B (1 << 6)
1499#define SYS_PINFUNC_S0C (1<<5) 1496#define SYS_PINFUNC_S0C (1 << 5)
1500#define SYS_PINFUNC_P0B (1<<4) 1497#define SYS_PINFUNC_P0B (1 << 4)
1501#define SYS_PINFUNC_U0T (1<<3) 1498#define SYS_PINFUNC_U0T (1 << 3)
1502#define SYS_PINFUNC_S1B (1<<2) 1499#define SYS_PINFUNC_S1B (1 << 2)
1503#endif 1500#endif
1504 1501
1505#define SYS_TRIOUTRD 0xB1900100 1502#define SYS_TRIOUTRD 0xB1900100
1506#define SYS_TRIOUTCLR 0xB1900100 1503#define SYS_TRIOUTCLR 0xB1900100
1507#define SYS_OUTPUTRD 0xB1900108 1504#define SYS_OUTPUTRD 0xB1900108
1508#define SYS_OUTPUTSET 0xB1900108 1505#define SYS_OUTPUTSET 0xB1900108
1509#define SYS_OUTPUTCLR 0xB190010C 1506#define SYS_OUTPUTCLR 0xB190010C
1510#define SYS_PINSTATERD 0xB1900110 1507#define SYS_PINSTATERD 0xB1900110
1511#define SYS_PININPUTEN 0xB1900110 1508#define SYS_PININPUTEN 0xB1900110
1512 1509
1513/* GPIO2, Au1500, Au1550 only */ 1510/* GPIO2, Au1500, Au1550 only */
1514#define GPIO2_BASE 0xB1700000 1511#define GPIO2_BASE 0xB1700000
1515#define GPIO2_DIR (GPIO2_BASE + 0) 1512#define GPIO2_DIR (GPIO2_BASE + 0)
1516#define GPIO2_OUTPUT (GPIO2_BASE + 8) 1513#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1517#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 1514#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1518#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 1515#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1519#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 1516#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1520 1517
1521/* Power Management */ 1518/* Power Management */
1522#define SYS_SCRATCH0 0xB1900018 1519#define SYS_SCRATCH0 0xB1900018
1523#define SYS_SCRATCH1 0xB190001C 1520#define SYS_SCRATCH1 0xB190001C
1524#define SYS_WAKEMSK 0xB1900034 1521#define SYS_WAKEMSK 0xB1900034
1525#define SYS_ENDIAN 0xB1900038 1522#define SYS_ENDIAN 0xB1900038
1526#define SYS_POWERCTRL 0xB190003C 1523#define SYS_POWERCTRL 0xB190003C
1527#define SYS_WAKESRC 0xB190005C 1524#define SYS_WAKESRC 0xB190005C
1528#define SYS_SLPPWR 0xB1900078 1525#define SYS_SLPPWR 0xB1900078
1529#define SYS_SLEEP 0xB190007C 1526#define SYS_SLEEP 0xB190007C
1530 1527
1531/* Clock Controller */ 1528/* Clock Controller */
1532#define SYS_FREQCTRL0 0xB1900020 1529#define SYS_FREQCTRL0 0xB1900020
1533# define SYS_FC_FRDIV2_BIT 22 1530# define SYS_FC_FRDIV2_BIT 22
1534# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1531# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535# define SYS_FC_FE2 (1<<21) 1532# define SYS_FC_FE2 (1 << 21)
1536# define SYS_FC_FS2 (1<<20) 1533# define SYS_FC_FS2 (1 << 20)
1537# define SYS_FC_FRDIV1_BIT 12 1534# define SYS_FC_FRDIV1_BIT 12
1538# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1535# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539# define SYS_FC_FE1 (1<<11) 1536# define SYS_FC_FE1 (1 << 11)
1540# define SYS_FC_FS1 (1<<10) 1537# define SYS_FC_FS1 (1 << 10)
1541# define SYS_FC_FRDIV0_BIT 2 1538# define SYS_FC_FRDIV0_BIT 2
1542# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1539# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543# define SYS_FC_FE0 (1<<1) 1540# define SYS_FC_FE0 (1 << 1)
1544# define SYS_FC_FS0 (1<<0) 1541# define SYS_FC_FS0 (1 << 0)
1545#define SYS_FREQCTRL1 0xB1900024 1542#define SYS_FREQCTRL1 0xB1900024
1546# define SYS_FC_FRDIV5_BIT 22 1543# define SYS_FC_FRDIV5_BIT 22
1547# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1544# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548# define SYS_FC_FE5 (1<<21) 1545# define SYS_FC_FE5 (1 << 21)
1549# define SYS_FC_FS5 (1<<20) 1546# define SYS_FC_FS5 (1 << 20)
1550# define SYS_FC_FRDIV4_BIT 12 1547# define SYS_FC_FRDIV4_BIT 12
1551# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1548# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552# define SYS_FC_FE4 (1<<11) 1549# define SYS_FC_FE4 (1 << 11)
1553# define SYS_FC_FS4 (1<<10) 1550# define SYS_FC_FS4 (1 << 10)
1554# define SYS_FC_FRDIV3_BIT 2 1551# define SYS_FC_FRDIV3_BIT 2
1555# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1552# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556# define SYS_FC_FE3 (1<<1) 1553# define SYS_FC_FE3 (1 << 1)
1557# define SYS_FC_FS3 (1<<0) 1554# define SYS_FC_FS3 (1 << 0)
1558#define SYS_CLKSRC 0xB1900028 1555#define SYS_CLKSRC 0xB1900028
1559# define SYS_CS_ME1_BIT 27 1556# define SYS_CS_ME1_BIT 27
1560# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1557# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1561# define SYS_CS_DE1 (1<<26) 1558# define SYS_CS_DE1 (1 << 26)
1562# define SYS_CS_CE1 (1<<25) 1559# define SYS_CS_CE1 (1 << 25)
1563# define SYS_CS_ME0_BIT 22 1560# define SYS_CS_ME0_BIT 22
1564# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1561# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1565# define SYS_CS_DE0 (1<<21) 1562# define SYS_CS_DE0 (1 << 21)
1566# define SYS_CS_CE0 (1<<20) 1563# define SYS_CS_CE0 (1 << 20)
1567# define SYS_CS_MI2_BIT 17 1564# define SYS_CS_MI2_BIT 17
1568# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1565# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1569# define SYS_CS_DI2 (1<<16) 1566# define SYS_CS_DI2 (1 << 16)
1570# define SYS_CS_CI2 (1<<15) 1567# define SYS_CS_CI2 (1 << 15)
1571#ifdef CONFIG_SOC_AU1100 1568#ifdef CONFIG_SOC_AU1100
1572# define SYS_CS_ML_BIT 7 1569# define SYS_CS_ML_BIT 7
1573# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1570# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1574# define SYS_CS_DL (1<<6) 1571# define SYS_CS_DL (1 << 6)
1575# define SYS_CS_CL (1<<5) 1572# define SYS_CS_CL (1 << 5)
1576#else 1573#else
1577# define SYS_CS_MUH_BIT 12 1574# define SYS_CS_MUH_BIT 12
1578# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1575# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1579# define SYS_CS_DUH (1<<11) 1576# define SYS_CS_DUH (1 << 11)
1580# define SYS_CS_CUH (1<<10) 1577# define SYS_CS_CUH (1 << 10)
1581# define SYS_CS_MUD_BIT 7 1578# define SYS_CS_MUD_BIT 7
1582# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1579# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1583# define SYS_CS_DUD (1<<6) 1580# define SYS_CS_DUD (1 << 6)
1584# define SYS_CS_CUD (1<<5) 1581# define SYS_CS_CUD (1 << 5)
1585#endif 1582#endif
1586# define SYS_CS_MIR_BIT 2 1583# define SYS_CS_MIR_BIT 2
1587# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1584# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1588# define SYS_CS_DIR (1<<1) 1585# define SYS_CS_DIR (1 << 1)
1589# define SYS_CS_CIR (1<<0) 1586# define SYS_CS_CIR (1 << 0)
1590 1587
1591# define SYS_CS_MUX_AUX 0x1 1588# define SYS_CS_MUX_AUX 0x1
1592# define SYS_CS_MUX_FQ0 0x2 1589# define SYS_CS_MUX_FQ0 0x2
1593# define SYS_CS_MUX_FQ1 0x3 1590# define SYS_CS_MUX_FQ1 0x3
1594# define SYS_CS_MUX_FQ2 0x4 1591# define SYS_CS_MUX_FQ2 0x4
1595# define SYS_CS_MUX_FQ3 0x5 1592# define SYS_CS_MUX_FQ3 0x5
1596# define SYS_CS_MUX_FQ4 0x6 1593# define SYS_CS_MUX_FQ4 0x6
1597# define SYS_CS_MUX_FQ5 0x7 1594# define SYS_CS_MUX_FQ5 0x7
1598#define SYS_CPUPLL 0xB1900060 1595#define SYS_CPUPLL 0xB1900060
1599#define SYS_AUXPLL 0xB1900064 1596#define SYS_AUXPLL 0xB1900064
1600 1597
1601/* AC97 Controller */ 1598/* AC97 Controller */
1602#define AC97C_CONFIG 0xB0000000 1599#define AC97C_CONFIG 0xB0000000
1603# define AC97C_RECV_SLOTS_BIT 13 1600# define AC97C_RECV_SLOTS_BIT 13
1604# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1601# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605# define AC97C_XMIT_SLOTS_BIT 3 1602# define AC97C_XMIT_SLOTS_BIT 3
1606# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1603# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607# define AC97C_SG (1<<2) 1604# define AC97C_SG (1 << 2)
1608# define AC97C_SYNC (1<<1) 1605# define AC97C_SYNC (1 << 1)
1609# define AC97C_RESET (1<<0) 1606# define AC97C_RESET (1 << 0)
1610#define AC97C_STATUS 0xB0000004 1607#define AC97C_STATUS 0xB0000004
1611# define AC97C_XU (1<<11) 1608# define AC97C_XU (1 << 11)
1612# define AC97C_XO (1<<10) 1609# define AC97C_XO (1 << 10)
1613# define AC97C_RU (1<<9) 1610# define AC97C_RU (1 << 9)
1614# define AC97C_RO (1<<8) 1611# define AC97C_RO (1 << 8)
1615# define AC97C_READY (1<<7) 1612# define AC97C_READY (1 << 7)
1616# define AC97C_CP (1<<6) 1613# define AC97C_CP (1 << 6)
1617# define AC97C_TR (1<<5) 1614# define AC97C_TR (1 << 5)
1618# define AC97C_TE (1<<4) 1615# define AC97C_TE (1 << 4)
1619# define AC97C_TF (1<<3) 1616# define AC97C_TF (1 << 3)
1620# define AC97C_RR (1<<2) 1617# define AC97C_RR (1 << 2)
1621# define AC97C_RE (1<<1) 1618# define AC97C_RE (1 << 1)
1622# define AC97C_RF (1<<0) 1619# define AC97C_RF (1 << 0)
1623#define AC97C_DATA 0xB0000008 1620#define AC97C_DATA 0xB0000008
1624#define AC97C_CMD 0xB000000C 1621#define AC97C_CMD 0xB000000C
1625# define AC97C_WD_BIT 16 1622# define AC97C_WD_BIT 16
1626# define AC97C_READ (1<<7) 1623# define AC97C_READ (1 << 7)
1627# define AC97C_INDEX_MASK 0x7f 1624# define AC97C_INDEX_MASK 0x7f
1628#define AC97C_CNTRL 0xB0000010 1625#define AC97C_CNTRL 0xB0000010
1629# define AC97C_RS (1<<1) 1626# define AC97C_RS (1 << 1)
1630# define AC97C_CE (1<<0) 1627# define AC97C_CE (1 << 0)
1631
1632 1628
1633/* Secure Digital (SD) Controller */ 1629/* Secure Digital (SD) Controller */
1634#define SD0_XMIT_FIFO 0xB0600000 1630#define SD0_XMIT_FIFO 0xB0600000
@@ -1638,73 +1634,74 @@ enum soc_au1200_ints {
1638 1634
1639#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1635#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640/* Au1500 PCI Controller */ 1636/* Au1500 PCI Controller */
1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1637#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1638#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1639#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1640# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1641 (1 << 25) | (1 << 26) | (1 << 27))
1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1642#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1643#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1648#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1644#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1645#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1649#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1646#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1650#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1647#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1651#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1648#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1652#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1649#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1653#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1650#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1654#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1651#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1655#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1652#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1656#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1653#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1657 1654
1658#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr 1655#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1659 1656
1660/* All of our structures, like pci resource, have 32 bit members. 1657/*
1658 * All of our structures, like PCI resource, have 32-bit members.
1661 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1659 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1662 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch 1660 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1663 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1661 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1664 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM 1662 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1665 * addresses. For PCI IO, it's simpler because we get to do the ioremap 1663 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1666 * ourselves and then adjust the device's resources. 1664 * ourselves and then adjust the device's resources.
1667 */ 1665 */
1668#define Au1500_EXT_CFG 0x600000000ULL 1666#define Au1500_EXT_CFG 0x600000000ULL
1669#define Au1500_EXT_CFG_TYPE1 0x680000000ULL 1667#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1670#define Au1500_PCI_IO_START 0x500000000ULL 1668#define Au1500_PCI_IO_START 0x500000000ULL
1671#define Au1500_PCI_IO_END 0x5000FFFFFULL 1669#define Au1500_PCI_IO_END 0x5000FFFFFULL
1672#define Au1500_PCI_MEM_START 0x440000000ULL 1670#define Au1500_PCI_MEM_START 0x440000000ULL
1673#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1671#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1674 1672
1675#define PCI_IO_START 0x00001000 1673#define PCI_IO_START 0x00001000
1676#define PCI_IO_END 0x000FFFFF 1674#define PCI_IO_END 0x000FFFFF
1677#define PCI_MEM_START 0x40000000 1675#define PCI_MEM_START 0x40000000
1678#define PCI_MEM_END 0x4FFFFFFF 1676#define PCI_MEM_END 0x4FFFFFFF
1679 1677
1680#define PCI_FIRST_DEVFN (0<<3) 1678#define PCI_FIRST_DEVFN (0 << 3)
1681#define PCI_LAST_DEVFN (19<<3) 1679#define PCI_LAST_DEVFN (19 << 3)
1682 1680
1683#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1681#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1684#define IOPORT_RESOURCE_END 0xffffffff 1682#define IOPORT_RESOURCE_END 0xffffffff
1685#define IOMEM_RESOURCE_START 0x10000000 1683#define IOMEM_RESOURCE_START 0x10000000
1686#define IOMEM_RESOURCE_END 0xffffffff 1684#define IOMEM_RESOURCE_END 0xffffffff
1687 1685
1688#else /* Au1000 and Au1100 and Au1200 */ 1686#else /* Au1000 and Au1100 and Au1200 */
1689 1687
1690/* don't allow any legacy ports probing */ 1688/* Don't allow any legacy ports probing */
1691#define IOPORT_RESOURCE_START 0x10000000 1689#define IOPORT_RESOURCE_START 0x10000000
1692#define IOPORT_RESOURCE_END 0xffffffff 1690#define IOPORT_RESOURCE_END 0xffffffff
1693#define IOMEM_RESOURCE_START 0x10000000 1691#define IOMEM_RESOURCE_START 0x10000000
1694#define IOMEM_RESOURCE_END 0xffffffff 1692#define IOMEM_RESOURCE_END 0xffffffff
1695 1693
1696#define PCI_IO_START 0 1694#define PCI_IO_START 0
1697#define PCI_IO_END 0 1695#define PCI_IO_END 0
1698#define PCI_MEM_START 0 1696#define PCI_MEM_START 0
1699#define PCI_MEM_END 0 1697#define PCI_MEM_END 0
1700#define PCI_FIRST_DEVFN 0 1698#define PCI_FIRST_DEVFN 0
1701#define PCI_LAST_DEVFN 0 1699#define PCI_LAST_DEVFN 0
1702 1700
1703#endif 1701#endif
1704 1702
1705#ifndef _LANGUAGE_ASSEMBLY 1703#ifndef _LANGUAGE_ASSEMBLY
1706typedef volatile struct 1704typedef volatile struct {
1707{
1708 /* 0x0000 */ u32 toytrim; 1705 /* 0x0000 */ u32 toytrim;
1709 /* 0x0004 */ u32 toywrite; 1706 /* 0x0004 */ u32 toywrite;
1710 /* 0x0008 */ u32 toymatch0; 1707 /* 0x0008 */ u32 toymatch0;
@@ -1746,13 +1743,14 @@ typedef volatile struct
1746 /* 0x010C */ u32 outputclr; 1743 /* 0x010C */ u32 outputclr;
1747 /* 0x0110 */ u32 pinstaterd; 1744 /* 0x0110 */ u32 pinstaterd;
1748#define pininputen pinstaterd 1745#define pininputen pinstaterd
1749
1750} AU1X00_SYS; 1746} AU1X00_SYS;
1751 1747
1752static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE; 1748static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1753 1749
1754#endif 1750#endif
1755/* Processor information base on prid. 1751
1752/*
1753 * Processor information based on PRID.
1756 * Copied from PowerPC. 1754 * Copied from PowerPC.
1757 */ 1755 */
1758#ifndef _LANGUAGE_ASSEMBLY 1756#ifndef _LANGUAGE_ASSEMBLY
@@ -1767,9 +1765,8 @@ struct cpu_spec {
1767 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ 1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1768}; 1766};
1769 1767
1770extern struct cpu_spec cpu_specs[]; 1768extern struct cpu_spec cpu_specs[];
1771extern struct cpu_spec *cur_cpu_spec[]; 1769extern struct cpu_spec *cur_cpu_spec[];
1772#endif 1770#endif
1773 1771
1774#endif 1772#endif
1775
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
index 9f29520e8fb0..c333b4e1cd44 100644
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ b/include/asm-mips/mach-au1x00/au1000_dma.h
@@ -1,11 +1,10 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Defines for using and allocating dma channels on the Alchemy 3 * Defines for using and allocating DMA channels on the Alchemy
4 * Au1000 mips processor. 4 * Au1x00 MIPS processors.
5 * 5 *
6 * Copyright 2000 MontaVista Software Inc. 6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * stevel@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -31,7 +30,7 @@
31#ifndef __ASM_AU1000_DMA_H 30#ifndef __ASM_AU1000_DMA_H
32#define __ASM_AU1000_DMA_H 31#define __ASM_AU1000_DMA_H
33 32
34#include <asm/io.h> /* need byte IO */ 33#include <linux/io.h> /* need byte IO */
35#include <linux/spinlock.h> /* And spinlocks */ 34#include <linux/spinlock.h> /* And spinlocks */
36#include <linux/delay.h> 35#include <linux/delay.h>
37#include <asm/system.h> 36#include <asm/system.h>
@@ -50,36 +49,36 @@
50#define DMA_DAH_MASK (0x0f << 20) 49#define DMA_DAH_MASK (0x0f << 20)
51#define DMA_DID_BIT 16 50#define DMA_DID_BIT 16
52#define DMA_DID_MASK (0x0f << DMA_DID_BIT) 51#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
53#define DMA_DS (1<<15) 52#define DMA_DS (1 << 15)
54#define DMA_BE (1<<13) 53#define DMA_BE (1 << 13)
55#define DMA_DR (1<<12) 54#define DMA_DR (1 << 12)
56#define DMA_TS8 (1<<11) 55#define DMA_TS8 (1 << 11)
57#define DMA_DW_BIT 9 56#define DMA_DW_BIT 9
58#define DMA_DW_MASK (0x03 << DMA_DW_BIT) 57#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
59#define DMA_DW8 (0 << DMA_DW_BIT) 58#define DMA_DW8 (0 << DMA_DW_BIT)
60#define DMA_DW16 (1 << DMA_DW_BIT) 59#define DMA_DW16 (1 << DMA_DW_BIT)
61#define DMA_DW32 (2 << DMA_DW_BIT) 60#define DMA_DW32 (2 << DMA_DW_BIT)
62#define DMA_NC (1<<8) 61#define DMA_NC (1 << 8)
63#define DMA_IE (1<<7) 62#define DMA_IE (1 << 7)
64#define DMA_HALT (1<<6) 63#define DMA_HALT (1 << 6)
65#define DMA_GO (1<<5) 64#define DMA_GO (1 << 5)
66#define DMA_AB (1<<4) 65#define DMA_AB (1 << 4)
67#define DMA_D1 (1<<3) 66#define DMA_D1 (1 << 3)
68#define DMA_BE1 (1<<2) 67#define DMA_BE1 (1 << 2)
69#define DMA_D0 (1<<1) 68#define DMA_D0 (1 << 1)
70#define DMA_BE0 (1<<0) 69#define DMA_BE0 (1 << 0)
71 70
72#define DMA_PERIPHERAL_ADDR 0x00000008 71#define DMA_PERIPHERAL_ADDR 0x00000008
73#define DMA_BUFFER0_START 0x0000000C 72#define DMA_BUFFER0_START 0x0000000C
74#define DMA_BUFFER1_START 0x00000014 73#define DMA_BUFFER1_START 0x00000014
75#define DMA_BUFFER0_COUNT 0x00000010 74#define DMA_BUFFER0_COUNT 0x00000010
76#define DMA_BUFFER1_COUNT 0x00000018 75#define DMA_BUFFER1_COUNT 0x00000018
77#define DMA_BAH_BIT 16 76#define DMA_BAH_BIT 16
78#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) 77#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
79#define DMA_COUNT_BIT 0 78#define DMA_COUNT_BIT 0
80#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) 79#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
81 80
82/* DMA Device ID's follow */ 81/* DMA Device IDs follow */
83enum { 82enum {
84 DMA_ID_UART0_TX = 0, 83 DMA_ID_UART0_TX = 0,
85 DMA_ID_UART0_RX, 84 DMA_ID_UART0_RX,
@@ -110,7 +109,8 @@ enum {
110}; 109};
111 110
112struct dma_chan { 111struct dma_chan {
113 int dev_id; // this channel is allocated if >=0, free otherwise 112 int dev_id; /* this channel is allocated if >= 0, */
113 /* free otherwise */
114 unsigned int io; 114 unsigned int io;
115 const char *dev_str; 115 const char *dev_str;
116 int irq; 116 int irq;
@@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
132extern void dump_au1000_dma_channel(unsigned int dmanr); 132extern void dump_au1000_dma_channel(unsigned int dmanr);
133extern spinlock_t au1000_dma_spin_lock; 133extern spinlock_t au1000_dma_spin_lock;
134 134
135 135static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
136static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
137{ 136{
138 if (dmanr >= NUM_AU1000_DMA_CHANNELS 137 if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
139 || au1000_dma_table[dmanr].dev_id < 0) 138 au1000_dma_table[dmanr].dev_id < 0)
140 return NULL; 139 return NULL;
141 return &au1000_dma_table[dmanr]; 140 return &au1000_dma_table[dmanr];
142} 141}
143 142
144static __inline__ unsigned long claim_dma_lock(void) 143static inline unsigned long claim_dma_lock(void)
145{ 144{
146 unsigned long flags; 145 unsigned long flags;
146
147 spin_lock_irqsave(&au1000_dma_spin_lock, flags); 147 spin_lock_irqsave(&au1000_dma_spin_lock, flags);
148 return flags; 148 return flags;
149} 149}
150 150
151static __inline__ void release_dma_lock(unsigned long flags) 151static inline void release_dma_lock(unsigned long flags)
152{ 152{
153 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags); 153 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
154} 154}
@@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags)
156/* 156/*
157 * Set the DMA buffer enable bits in the mode register. 157 * Set the DMA buffer enable bits in the mode register.
158 */ 158 */
159static __inline__ void enable_dma_buffer0(unsigned int dmanr) 159static inline void enable_dma_buffer0(unsigned int dmanr)
160{ 160{
161 struct dma_chan *chan = get_dma_chan(dmanr); 161 struct dma_chan *chan = get_dma_chan(dmanr);
162
162 if (!chan) 163 if (!chan)
163 return; 164 return;
164 au_writel(DMA_BE0, chan->io + DMA_MODE_SET); 165 au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
165} 166}
166static __inline__ void enable_dma_buffer1(unsigned int dmanr) 167
168static inline void enable_dma_buffer1(unsigned int dmanr)
167{ 169{
168 struct dma_chan *chan = get_dma_chan(dmanr); 170 struct dma_chan *chan = get_dma_chan(dmanr);
171
169 if (!chan) 172 if (!chan)
170 return; 173 return;
171 au_writel(DMA_BE1, chan->io + DMA_MODE_SET); 174 au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
172} 175}
173static __inline__ void enable_dma_buffers(unsigned int dmanr) 176static inline void enable_dma_buffers(unsigned int dmanr)
174{ 177{
175 struct dma_chan *chan = get_dma_chan(dmanr); 178 struct dma_chan *chan = get_dma_chan(dmanr);
179
176 if (!chan) 180 if (!chan)
177 return; 181 return;
178 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); 182 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
179} 183}
180 184
181static __inline__ void start_dma(unsigned int dmanr) 185static inline void start_dma(unsigned int dmanr)
182{ 186{
183 struct dma_chan *chan = get_dma_chan(dmanr); 187 struct dma_chan *chan = get_dma_chan(dmanr);
188
184 if (!chan) 189 if (!chan)
185 return; 190 return;
186
187 au_writel(DMA_GO, chan->io + DMA_MODE_SET); 191 au_writel(DMA_GO, chan->io + DMA_MODE_SET);
188} 192}
189 193
190#define DMA_HALT_POLL 0x5000 194#define DMA_HALT_POLL 0x5000
191 195
192static __inline__ void halt_dma(unsigned int dmanr) 196static inline void halt_dma(unsigned int dmanr)
193{ 197{
194 struct dma_chan *chan = get_dma_chan(dmanr); 198 struct dma_chan *chan = get_dma_chan(dmanr);
195 int i; 199 int i;
200
196 if (!chan) 201 if (!chan)
197 return; 202 return;
198
199 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); 203 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
200 // poll the halt bit 204
205 /* Poll the halt bit */
201 for (i = 0; i < DMA_HALT_POLL; i++) 206 for (i = 0; i < DMA_HALT_POLL; i++)
202 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) 207 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
203 break; 208 break;
@@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr)
205 printk(KERN_INFO "halt_dma: HALT poll expired!\n"); 210 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
206} 211}
207 212
208 213static inline void disable_dma(unsigned int dmanr)
209static __inline__ void disable_dma(unsigned int dmanr)
210{ 214{
211 struct dma_chan *chan = get_dma_chan(dmanr); 215 struct dma_chan *chan = get_dma_chan(dmanr);
216
212 if (!chan) 217 if (!chan)
213 return; 218 return;
214 219
215 halt_dma(dmanr); 220 halt_dma(dmanr);
216 221
217 // now we can disable the buffers 222 /* Now we can disable the buffers */
218 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); 223 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
219} 224}
220 225
221static __inline__ int dma_halted(unsigned int dmanr) 226static inline int dma_halted(unsigned int dmanr)
222{ 227{
223 struct dma_chan *chan = get_dma_chan(dmanr); 228 struct dma_chan *chan = get_dma_chan(dmanr);
229
224 if (!chan) 230 if (!chan)
225 return 1; 231 return 1;
226 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; 232 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
227} 233}
228 234
229/* initialize a DMA channel */ 235/* Initialize a DMA channel. */
230static __inline__ void init_dma(unsigned int dmanr) 236static inline void init_dma(unsigned int dmanr)
231{ 237{
232 struct dma_chan *chan = get_dma_chan(dmanr); 238 struct dma_chan *chan = get_dma_chan(dmanr);
233 u32 mode; 239 u32 mode;
240
234 if (!chan) 241 if (!chan)
235 return; 242 return;
236 243
237 disable_dma(dmanr); 244 disable_dma(dmanr);
238 245
239 // set device FIFO address 246 /* Set device FIFO address */
240 au_writel(CPHYSADDR(chan->fifo_addr), 247 au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
241 chan->io + DMA_PERIPHERAL_ADDR);
242 248
243 mode = chan->mode | (chan->dev_id << DMA_DID_BIT); 249 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
244 if (chan->irq) 250 if (chan->irq)
245 mode |= DMA_IE; 251 mode |= DMA_IE;
246 252
247 au_writel(~mode, chan->io + DMA_MODE_CLEAR); 253 au_writel(~mode, chan->io + DMA_MODE_CLEAR);
248 au_writel(mode, chan->io + DMA_MODE_SET); 254 au_writel(mode, chan->io + DMA_MODE_SET);
249} 255}
250 256
251/* 257/*
252 * set mode for a specific DMA channel 258 * Set mode for a specific DMA channel
253 */ 259 */
254static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode) 260static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
255{ 261{
256 struct dma_chan *chan = get_dma_chan(dmanr); 262 struct dma_chan *chan = get_dma_chan(dmanr);
263
257 if (!chan) 264 if (!chan)
258 return; 265 return;
259 /* 266 /*
@@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
266 chan->mode |= mode; 273 chan->mode |= mode;
267} 274}
268 275
269static __inline__ unsigned int get_dma_mode(unsigned int dmanr) 276static inline unsigned int get_dma_mode(unsigned int dmanr)
270{ 277{
271 struct dma_chan *chan = get_dma_chan(dmanr); 278 struct dma_chan *chan = get_dma_chan(dmanr);
279
272 if (!chan) 280 if (!chan)
273 return 0; 281 return 0;
274 return chan->mode; 282 return chan->mode;
275} 283}
276 284
277static __inline__ int get_dma_active_buffer(unsigned int dmanr) 285static inline int get_dma_active_buffer(unsigned int dmanr)
278{ 286{
279 struct dma_chan *chan = get_dma_chan(dmanr); 287 struct dma_chan *chan = get_dma_chan(dmanr);
288
280 if (!chan) 289 if (!chan)
281 return -1; 290 return -1;
282 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; 291 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
283} 292}
284 293
285
286/* 294/*
287 * set the device FIFO address for a specific DMA channel - only 295 * Set the device FIFO address for a specific DMA channel - only
288 * applicable to GPO4 and GPO5. All the other devices have fixed 296 * applicable to GPO4 and GPO5. All the other devices have fixed
289 * FIFO addresses. 297 * FIFO addresses.
290 */ 298 */
291static __inline__ void set_dma_fifo_addr(unsigned int dmanr, 299static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
292 unsigned int a)
293{ 300{
294 struct dma_chan *chan = get_dma_chan(dmanr); 301 struct dma_chan *chan = get_dma_chan(dmanr);
302
295 if (!chan) 303 if (!chan)
296 return; 304 return;
297 305
298 if (chan->mode & DMA_DS) /* second bank of device ids */ 306 if (chan->mode & DMA_DS) /* second bank of device IDs */
299 return; 307 return;
300 308
301 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) 309 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
@@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
307/* 315/*
308 * Clear the DMA buffer done bits in the mode register. 316 * Clear the DMA buffer done bits in the mode register.
309 */ 317 */
310static __inline__ void clear_dma_done0(unsigned int dmanr) 318static inline void clear_dma_done0(unsigned int dmanr)
311{ 319{
312 struct dma_chan *chan = get_dma_chan(dmanr); 320 struct dma_chan *chan = get_dma_chan(dmanr);
321
313 if (!chan) 322 if (!chan)
314 return; 323 return;
315 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); 324 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
316} 325}
317static __inline__ void clear_dma_done1(unsigned int dmanr) 326
327static inline void clear_dma_done1(unsigned int dmanr)
318{ 328{
319 struct dma_chan *chan = get_dma_chan(dmanr); 329 struct dma_chan *chan = get_dma_chan(dmanr);
330
320 if (!chan) 331 if (!chan)
321 return; 332 return;
322 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); 333 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
@@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr)
325/* 336/*
326 * This does nothing - not applicable to Au1000 DMA. 337 * This does nothing - not applicable to Au1000 DMA.
327 */ 338 */
328static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 339static inline void set_dma_page(unsigned int dmanr, char pagenr)
329{ 340{
330} 341}
331 342
332/* 343/*
333 * Set Buffer 0 transfer address for specific DMA channel. 344 * Set Buffer 0 transfer address for specific DMA channel.
334 */ 345 */
335static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a) 346static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
336{ 347{
337 struct dma_chan *chan = get_dma_chan(dmanr); 348 struct dma_chan *chan = get_dma_chan(dmanr);
349
338 if (!chan) 350 if (!chan)
339 return; 351 return;
340 au_writel(a, chan->io + DMA_BUFFER0_START); 352 au_writel(a, chan->io + DMA_BUFFER0_START);
@@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
343/* 355/*
344 * Set Buffer 1 transfer address for specific DMA channel. 356 * Set Buffer 1 transfer address for specific DMA channel.
345 */ 357 */
346static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a) 358static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
347{ 359{
348 struct dma_chan *chan = get_dma_chan(dmanr); 360 struct dma_chan *chan = get_dma_chan(dmanr);
361
349 if (!chan) 362 if (!chan)
350 return; 363 return;
351 au_writel(a, chan->io + DMA_BUFFER1_START); 364 au_writel(a, chan->io + DMA_BUFFER1_START);
@@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
355/* 368/*
356 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel. 369 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
357 */ 370 */
358static __inline__ void set_dma_count0(unsigned int dmanr, 371static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
359 unsigned int count)
360{ 372{
361 struct dma_chan *chan = get_dma_chan(dmanr); 373 struct dma_chan *chan = get_dma_chan(dmanr);
374
362 if (!chan) 375 if (!chan)
363 return; 376 return;
364 count &= DMA_COUNT_MASK; 377 count &= DMA_COUNT_MASK;
@@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr,
368/* 381/*
369 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel. 382 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
370 */ 383 */
371static __inline__ void set_dma_count1(unsigned int dmanr, 384static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
372 unsigned int count)
373{ 385{
374 struct dma_chan *chan = get_dma_chan(dmanr); 386 struct dma_chan *chan = get_dma_chan(dmanr);
387
375 if (!chan) 388 if (!chan)
376 return; 389 return;
377 count &= DMA_COUNT_MASK; 390 count &= DMA_COUNT_MASK;
@@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr,
381/* 394/*
382 * Set both buffer transfer sizes (max 64k) for a specific DMA channel. 395 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
383 */ 396 */
384static __inline__ void set_dma_count(unsigned int dmanr, 397static inline void set_dma_count(unsigned int dmanr, unsigned int count)
385 unsigned int count)
386{ 398{
387 struct dma_chan *chan = get_dma_chan(dmanr); 399 struct dma_chan *chan = get_dma_chan(dmanr);
400
388 if (!chan) 401 if (!chan)
389 return; 402 return;
390 count &= DMA_COUNT_MASK; 403 count &= DMA_COUNT_MASK;
@@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr,
396 * Returns which buffer has its done bit set in the mode register. 409 * Returns which buffer has its done bit set in the mode register.
397 * Returns -1 if neither or both done bits set. 410 * Returns -1 if neither or both done bits set.
398 */ 411 */
399static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr) 412static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
400{ 413{
401 struct dma_chan *chan = get_dma_chan(dmanr); 414 struct dma_chan *chan = get_dma_chan(dmanr);
415
402 if (!chan) 416 if (!chan)
403 return 0; 417 return 0;
404 418 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
405 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
406} 419}
407 420
408 421
409/* 422/*
410 * Returns the DMA channel's Buffer Done IRQ number. 423 * Returns the DMA channel's Buffer Done IRQ number.
411 */ 424 */
412static __inline__ int get_dma_done_irq(unsigned int dmanr) 425static inline int get_dma_done_irq(unsigned int dmanr)
413{ 426{
414 struct dma_chan *chan = get_dma_chan(dmanr); 427 struct dma_chan *chan = get_dma_chan(dmanr);
428
415 if (!chan) 429 if (!chan)
416 return -1; 430 return -1;
417
418 return chan->irq; 431 return chan->irq;
419} 432}
420 433
421/* 434/*
422 * Get DMA residue count. Returns the number of _bytes_ left to transfer. 435 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
423 */ 436 */
424static __inline__ int get_dma_residue(unsigned int dmanr) 437static inline int get_dma_residue(unsigned int dmanr)
425{ 438{
426 int curBufCntReg, count; 439 int curBufCntReg, count;
427 struct dma_chan *chan = get_dma_chan(dmanr); 440 struct dma_chan *chan = get_dma_chan(dmanr);
441
428 if (!chan) 442 if (!chan)
429 return 0; 443 return 0;
430 444
@@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
442} 456}
443 457
444#endif /* __ASM_AU1000_DMA_H */ 458#endif /* __ASM_AU1000_DMA_H */
445
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
index 298f92012e8e..d8c96fda5549 100644
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ b/include/asm-mips/mach-au1x00/au1000_gpio.h
@@ -2,12 +2,12 @@
2 * FILE NAME au1000_gpio.h 2 * FILE NAME au1000_gpio.h
3 * 3 *
4 * BRIEF MODULE DESCRIPTION 4 * BRIEF MODULE DESCRIPTION
5 * API to Alchemy Au1000 GPIO device. 5 * API to Alchemy Au1xx0 GPIO device.
6 * 6 *
7 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Steve Longerbeam <stevel@mvista.com> 8 * Steve Longerbeam
9 * 9 *
10 * Copyright 2001 MontaVista Software Inc. 10 * Copyright 2001, 2008 MontaVista Software Inc.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -37,12 +37,12 @@
37 37
38#define AU1000GPIO_IOC_MAGIC 'A' 38#define AU1000GPIO_IOC_MAGIC 'A'
39 39
40#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int) 40#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
41#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int) 41#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
42#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int) 42#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
43#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int) 43#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
44#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int) 44#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
45#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int) 45#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
46 46
47#ifdef __KERNEL__ 47#ifdef __KERNEL__
48extern u32 get_au1000_avail_gpio_mask(void); 48extern u32 get_au1000_avail_gpio_mask(void);
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
index c2f0466523ec..40e6c489833a 100644
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ b/include/asm-mips/mach-au1x00/au1550_spi.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * au1550_spi.h - au1550 psc spi controller driver - platform data struct 2 * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
3 */ 3 */
4 4
5#ifndef _AU1550_SPI_H_ 5#ifndef _AU1550_SPI_H_
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
index 947135941033..1b3655090ed3 100644
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ b/include/asm-mips/mach-au1x00/au1xxx.h
@@ -23,10 +23,10 @@
23#ifndef _AU1XXX_H_ 23#ifndef _AU1XXX_H_
24#define _AU1XXX_H_ 24#define _AU1XXX_H_
25 25
26
27#include <asm/mach-au1x00/au1000.h> 26#include <asm/mach-au1x00/au1000.h>
28 27
29#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) 28#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
29 defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
30#include <asm/mach-db1x00/db1x00.h> 30#include <asm/mach-db1x00/db1x00.h>
31 31
32#elif defined(CONFIG_MIPS_PB1550) 32#elif defined(CONFIG_MIPS_PB1550)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index 93d507cea518..44a67bf05dc1 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -28,17 +28,18 @@
28 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */ 29 */
30 30
31/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first 31/*
32 * seen in the AU1550 part. 32 * Specifics for the Au1xxx Descriptor-Based DMA Controller,
33 * first seen in the AU1550 part.
33 */ 34 */
34#ifndef _AU1000_DBDMA_H_ 35#ifndef _AU1000_DBDMA_H_
35#define _AU1000_DBDMA_H_ 36#define _AU1000_DBDMA_H_
36 37
37
38#ifndef _LANGUAGE_ASSEMBLY 38#ifndef _LANGUAGE_ASSEMBLY
39 39
40/* The DMA base addresses. 40/*
41 * The Channels are every 256 bytes (0x0100) from the channel 0 base. 41 * The DMA base addresses.
42 * The channels are every 256 bytes (0x0100) from the channel 0 base.
42 * Interrupt status/enable is bits 15:0 for channels 15 to zero. 43 * Interrupt status/enable is bits 15:0 for channels 15 to zero.
43 */ 44 */
44#define DDMA_GLOBAL_BASE 0xb4003000 45#define DDMA_GLOBAL_BASE 0xb4003000
@@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
51 u32 ddma_inten; 52 u32 ddma_inten;
52} dbdma_global_t; 53} dbdma_global_t;
53 54
54/* General Configuration. 55/* General Configuration. */
55*/
56#define DDMA_CONFIG_AF (1 << 2) 56#define DDMA_CONFIG_AF (1 << 2)
57#define DDMA_CONFIG_AH (1 << 1) 57#define DDMA_CONFIG_AH (1 << 1)
58#define DDMA_CONFIG_AL (1 << 0) 58#define DDMA_CONFIG_AL (1 << 0)
59 59
60#define DDMA_THROTTLE_EN (1 << 31) 60#define DDMA_THROTTLE_EN (1 << 31)
61 61
62/* The structure of a DMA Channel. 62/* The structure of a DMA Channel. */
63*/
64typedef volatile struct au1xxx_dma_channel { 63typedef volatile struct au1xxx_dma_channel {
65 u32 ddma_cfg; /* See below */ 64 u32 ddma_cfg; /* See below */
66 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ 65 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
@@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
69 u32 ddma_irq; /* If bit 0 set, interrupt pending */ 68 u32 ddma_irq; /* If bit 0 set, interrupt pending */
70 u32 ddma_stat; /* See below */ 69 u32 ddma_stat; /* See below */
71 u32 ddma_bytecnt; /* Byte count, valid only when chan idle */ 70 u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
72 /* Remainder, up to the 256 byte boundary, is reserved. 71 /* Remainder, up to the 256 byte boundary, is reserved. */
73 */
74} au1x_dma_chan_t; 72} au1x_dma_chan_t;
75 73
76#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */ 74#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
@@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
84#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */ 82#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
85#define DDMA_CFG_EN (1 << 0) /* Channel enable */ 83#define DDMA_CFG_EN (1 << 0) /* Channel enable */
86 84
87/* Always set when descriptor processing done, regardless of 85/*
86 * Always set when descriptor processing done, regardless of
88 * interrupt enable state. Reflected in global intstat, don't 87 * interrupt enable state. Reflected in global intstat, don't
89 * clear this until global intstat is read/used. 88 * clear this until global intstat is read/used.
90 */ 89 */
@@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
94#define DDMA_STAT_V (1 << 1) /* Descriptor valid */ 93#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
95#define DDMA_STAT_H (1 << 0) /* Channel Halted */ 94#define DDMA_STAT_H (1 << 0) /* Channel Halted */
96 95
97/* "Standard" DDMA Descriptor. 96/*
97 * "Standard" DDMA Descriptor.
98 * Must be 32-byte aligned. 98 * Must be 32-byte aligned.
99 */ 99 */
100typedef volatile struct au1xxx_ddma_desc { 100typedef volatile struct au1xxx_ddma_desc {
@@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
106 u32 dscr_dest1; /* See below */ 106 u32 dscr_dest1; /* See below */
107 u32 dscr_stat; /* completion status */ 107 u32 dscr_stat; /* completion status */
108 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 108 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
109 /* First 32bytes are HW specific!!! 109 /*
110 Lets have some SW data following.. make sure its 32bytes 110 * First 32 bytes are HW specific!!!
111 * Lets have some SW data following -- make sure it's 32 bytes.
111 */ 112 */
112 u32 sw_status; 113 u32 sw_status;
113 u32 sw_context; 114 u32 sw_context;
@@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
130#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ 131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
131#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
132 133
133#define SW_STATUS_INUSE (1<<0) 134#define SW_STATUS_INUSE (1 << 0)
134 135
135/* Command 0 device IDs. 136/* Command 0 device IDs. */
136*/
137#ifdef CONFIG_SOC_AU1550 137#ifdef CONFIG_SOC_AU1550
138#define DSCR_CMD0_UART0_TX 0 138#define DSCR_CMD0_UART0_TX 0
139#define DSCR_CMD0_UART0_RX 1 139#define DSCR_CMD0_UART0_RX 1
@@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
198#define DSCR_CMD0_THROTTLE 30 198#define DSCR_CMD0_THROTTLE 30
199#define DSCR_CMD0_ALWAYS 31 199#define DSCR_CMD0_ALWAYS 31
200#define DSCR_NDEV_IDS 32 200#define DSCR_NDEV_IDS 32
201/* THis macro is used to find/create custom device types */ 201/* This macro is used to find/create custom device types */
202#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) 202#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
203#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) 203 ((d) & 0xFF))
204 204#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
205 205
206#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) 206#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
207#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) 207#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
208 208
209/* Source/Destination transfer width. 209/* Source/Destination transfer width. */
210*/
211#define DSCR_CMD0_BYTE 0 210#define DSCR_CMD0_BYTE 0
212#define DSCR_CMD0_HALFWORD 1 211#define DSCR_CMD0_HALFWORD 1
213#define DSCR_CMD0_WORD 2 212#define DSCR_CMD0_WORD 2
@@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
215#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) 214#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
216#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) 215#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
217 216
218/* DDMA Descriptor Type. 217/* DDMA Descriptor Type. */
219*/
220#define DSCR_CMD0_STANDARD 0 218#define DSCR_CMD0_STANDARD 0
221#define DSCR_CMD0_LITERAL 1 219#define DSCR_CMD0_LITERAL 1
222#define DSCR_CMD0_CMP_BRANCH 2 220#define DSCR_CMD0_CMP_BRANCH 2
223 221
224#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) 222#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
225 223
226/* Status Instruction. 224/* Status Instruction. */
227*/
228#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */ 225#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
229#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */ 226#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
230#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */ 227#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
@@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
232 229
233#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) 230#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
234 231
235/* Descriptor Command 1 232/* Descriptor Command 1. */
236*/
237#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */ 233#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
238#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */ 234#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
239#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ 235#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
240#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */ 236#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
241 237
242/* Flag description. 238/* Flag description. */
243*/
244#define DSCR_CMD1_FL_MEM_STRIDE0 0 239#define DSCR_CMD1_FL_MEM_STRIDE0 0
245#define DSCR_CMD1_FL_MEM_STRIDE1 1 240#define DSCR_CMD1_FL_MEM_STRIDE1 1
246#define DSCR_CMD1_FL_MEM_STRIDE2 2 241#define DSCR_CMD1_FL_MEM_STRIDE2 2
247 242
248#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) 243#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
249 244
250/* Source1, 1-dimensional stride. 245/* Source1, 1-dimensional stride. */
251*/
252#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */ 246#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
253#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */ 247#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
254#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */ 248#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
@@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
256#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */ 250#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
257#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) 251#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
258 252
259/* Dest1, 1-dimensional stride. 253/* Dest1, 1-dimensional stride. */
260*/
261#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */ 254#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
262#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */ 255#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
263#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */ 256#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
@@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
279#define DSCR_SRC1_SAM(x) (((x) & 3) << 28) 272#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
280#define DSCR_DEST1_DAM(x) (((x) & 3) << 28) 273#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
281 274
282/* The next descriptor pointer. 275/* The next descriptor pointer. */
283*/
284#define DSCR_NXTPTR_MASK (0x07ffffff) 276#define DSCR_NXTPTR_MASK (0x07ffffff)
285#define DSCR_NXTPTR(x) ((x) >> 5) 277#define DSCR_NXTPTR(x) ((x) >> 5)
286#define DSCR_GET_NXTPTR(x) ((x) << 5) 278#define DSCR_GET_NXTPTR(x) ((x) << 5)
287#define DSCR_NXTPTR_MS (1 << 27) 279#define DSCR_NXTPTR_MS (1 << 27)
288 280
289/* The number of DBDMA channels. 281/* The number of DBDMA channels. */
290*/
291#define NUM_DBDMA_CHANS 16 282#define NUM_DBDMA_CHANS 16
292 283
293/* 284/*
294 * Ddma API definitions 285 * DDMA API definitions
295 * FIXME: may not fit to this header file 286 * FIXME: may not fit to this header file
296 */ 287 */
297typedef struct dbdma_device_table { 288typedef struct dbdma_device_table {
298 u32 dev_id; 289 u32 dev_id;
299 u32 dev_flags; 290 u32 dev_flags;
300 u32 dev_tsize; 291 u32 dev_tsize;
301 u32 dev_devwidth; 292 u32 dev_devwidth;
302 u32 dev_physaddr; /* If FIFO */ 293 u32 dev_physaddr; /* If FIFO */
303 u32 dev_intlevel; 294 u32 dev_intlevel;
304 u32 dev_intpolarity; 295 u32 dev_intpolarity;
305} dbdev_tab_t; 296} dbdev_tab_t;
306 297
307 298
@@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
316 au1x_ddma_desc_t *chan_desc_base; 307 au1x_ddma_desc_t *chan_desc_base;
317 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; 308 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
318 void *chan_callparam; 309 void *chan_callparam;
319 void (*chan_callback)(int, void *); 310 void (*chan_callback)(int, void *);
320} chan_tab_t; 311} chan_tab_t;
321 312
322#define DEV_FLAGS_INUSE (1 << 0) 313#define DEV_FLAGS_INUSE (1 << 0)
323#define DEV_FLAGS_ANYUSE (1 << 1) 314#define DEV_FLAGS_ANYUSE (1 << 1)
324#define DEV_FLAGS_OUT (1 << 2) 315#define DEV_FLAGS_OUT (1 << 2)
325#define DEV_FLAGS_IN (1 << 3) 316#define DEV_FLAGS_IN (1 << 3)
326#define DEV_FLAGS_BURSTABLE (1 << 4) 317#define DEV_FLAGS_BURSTABLE (1 << 4)
327#define DEV_FLAGS_SYNC (1 << 5) 318#define DEV_FLAGS_SYNC (1 << 5)
328/* end Ddma API definitions */ 319/* end DDMA API definitions */
329 320
330/* External functions for drivers to use. 321/*
331*/ 322 * External functions for drivers to use.
332/* Use this to allocate a dbdma channel. The device ids are one of the 323 * Use this to allocate a DBDMA channel. The device IDs are one of
333 * DSCR_CMD0 devices IDs, which is usually redefined to a more 324 * the DSCR_CMD0 devices IDs, which is usually redefined to a more
334 * meaningful name. The 'callback' is called during dma completion 325 * meaningful name. The 'callback' is called during DMA completion
335 * interrupt. 326 * interrupt.
336 */ 327 */
337extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 328extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
338 void (*callback)(int, void *), void *callparam); 329 void (*callback)(int, void *),
330 void *callparam);
339 331
340#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 332#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
341 333
342/* Set the device width of a in/out fifo. 334/* Set the device width of an in/out FIFO. */
343*/
344u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); 335u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
345 336
346/* Allocate a ring of descriptors for dbdma. 337/* Allocate a ring of descriptors for DBDMA. */
347*/
348u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); 338u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
349 339
350/* Put buffers on source/destination descriptors. 340/* Put buffers on source/destination descriptors. */
351*/
352u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); 341u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
353u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); 342u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
354 343
355/* Get a buffer from the destination descriptor. 344/* Get a buffer from the destination descriptor. */
356*/
357u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); 345u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
358 346
359void au1xxx_dbdma_stop(u32 chanid); 347void au1xxx_dbdma_stop(u32 chanid);
@@ -364,29 +352,35 @@ u32 au1xxx_get_dma_residue(u32 chanid);
364void au1xxx_dbdma_chan_free(u32 chanid); 352void au1xxx_dbdma_chan_free(u32 chanid);
365void au1xxx_dbdma_dump(u32 chanid); 353void au1xxx_dbdma_dump(u32 chanid);
366 354
367u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ); 355u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
368 356
369u32 au1xxx_ddma_add_device( dbdev_tab_t *dev ); 357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
370void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); 358extern void au1xxx_ddma_del_device(u32 devid);
359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
371 360
372/* 361/*
373 Some compatibilty macros -- 362 * Some compatibilty macros -- needed to make changes to API
374 Needed to make changes to API without breaking existing drivers 363 * without breaking existing drivers.
375*/ 364 */
376#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) 365#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
377#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) 366 _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
378#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) 367#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
379 368 _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
380 369#define put_source_flags(chanid, buf, nbytes, flags) \
381#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) 370 au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
382#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) 371
383#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) 372#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
373 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
374#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
375 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
376#define put_dest_flags(chanid, buf, nbytes, flags) \
377 au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
384 378
385/* 379/*
386 * Flags for the put_source/put_dest functions. 380 * Flags for the put_source/put_dest functions.
387 */ 381 */
388#define DDMA_FLAGS_IE (1<<0) 382#define DDMA_FLAGS_IE (1 << 0)
389#define DDMA_FLAGS_NOIE (1<<1) 383#define DDMA_FLAGS_NOIE (1 << 1)
390 384
391#endif /* _LANGUAGE_ASSEMBLY */ 385#endif /* _LANGUAGE_ASSEMBLY */
392#endif /* _AU1000_DBDMA_H_ */ 386#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index b493a5e46c63..60638b8969ba 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -31,167 +31,164 @@
31 */ 31 */
32 32
33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34 #define DMA_WAIT_TIMEOUT 100 34#define DMA_WAIT_TIMEOUT 100
35 #define NUM_DESCRIPTORS PRD_ENTRIES 35#define NUM_DESCRIPTORS PRD_ENTRIES
36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ 36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37 #define NUM_DESCRIPTORS 2 37#define NUM_DESCRIPTORS 2
38#endif 38#endif
39 39
40#ifndef AU1XXX_ATA_RQSIZE 40#ifndef AU1XXX_ATA_RQSIZE
41 #define AU1XXX_ATA_RQSIZE 128 41#define AU1XXX_ATA_RQSIZE 128
42#endif 42#endif
43 43
44/* Disable Burstable-Support for DBDMA */ 44/* Disable Burstable-Support for DBDMA */
45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47#endif 47#endif
48 48
49#ifdef CONFIG_PM 49#ifdef CONFIG_PM
50/* 50/*
51* This will enable the device to be powered up when write() or read() 51 * This will enable the device to be powered up when write() or read()
52* is called. If this is not defined, the driver will return -EBUSY. 52 * is called. If this is not defined, the driver will return -EBUSY.
53*/ 53 */
54#define WAKE_ON_ACCESS 1 54#define WAKE_ON_ACCESS 1
55 55
56typedef struct 56typedef struct {
57{ 57 spinlock_t lock; /* Used to block on state transitions */
58 spinlock_t lock; /* Used to block on state transitions */ 58 au1xxx_power_dev_t *dev; /* Power Managers device structure */
59 au1xxx_power_dev_t *dev; /* Power Managers device structure */ 59 unsigned stopped; /* Used to signal device is stopped */
60 unsigned stopped; /* USed to signaling device is stopped */
61} pm_state; 60} pm_state;
62#endif 61#endif
63 62
64 63typedef struct {
65typedef struct 64 u32 tx_dev_id, rx_dev_id, target_dev_id;
66{ 65 u32 tx_chan, rx_chan;
67 u32 tx_dev_id, rx_dev_id, target_dev_id; 66 void *tx_desc_head, *rx_desc_head;
68 u32 tx_chan, rx_chan; 67 ide_hwif_t *hwif;
69 void *tx_desc_head, *rx_desc_head;
70 ide_hwif_t *hwif;
71#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 68#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
72 ide_drive_t *drive; 69 ide_drive_t *drive;
73 struct dbdma_cmd *dma_table_cpu; 70 struct dbdma_cmd *dma_table_cpu;
74 dma_addr_t dma_table_dma; 71 dma_addr_t dma_table_dma;
75#endif 72#endif
76 int irq; 73 int irq;
77 u32 regbase; 74 u32 regbase;
78#ifdef CONFIG_PM 75#ifdef CONFIG_PM
79 pm_state pm; 76 pm_state pm;
80#endif 77#endif
81} _auide_hwif; 78} _auide_hwif;
82 79
83/******************************************************************************* 80/******************************************************************************/
84* PIO Mode timing calculation : * 81/* PIO Mode timing calculation : */
85* * 82/* */
86* Static Bus Spec ATA Spec * 83/* Static Bus Spec ATA Spec */
87* Tcsoe = t1 * 84/* Tcsoe = t1 */
88* Toecs = t9 * 85/* Toecs = t9 */
89* Twcs = t9 * 86/* Twcs = t9 */
90* Tcsh = t2i | t2 * 87/* Tcsh = t2i | t2 */
91* Tcsoff = t2i | t2 * 88/* Tcsoff = t2i | t2 */
92* Twp = t2 * 89/* Twp = t2 */
93* Tcsw = t1 * 90/* Tcsw = t1 */
94* Tpm = 0 * 91/* Tpm = 0 */
95* Ta = t1+t2 * 92/* Ta = t1+t2 */
96*******************************************************************************/ 93/******************************************************************************/
97 94
98#define TCSOE_MASK (0x07<<29) 95#define TCSOE_MASK (0x07 << 29)
99#define TOECS_MASK (0x07<<26) 96#define TOECS_MASK (0x07 << 26)
100#define TWCS_MASK (0x07<<28) 97#define TWCS_MASK (0x07 << 28)
101#define TCSH_MASK (0x0F<<24) 98#define TCSH_MASK (0x0F << 24)
102#define TCSOFF_MASK (0x07<<20) 99#define TCSOFF_MASK (0x07 << 20)
103#define TWP_MASK (0x3F<<14) 100#define TWP_MASK (0x3F << 14)
104#define TCSW_MASK (0x0F<<10) 101#define TCSW_MASK (0x0F << 10)
105#define TPM_MASK (0x0F<<6) 102#define TPM_MASK (0x0F << 6)
106#define TA_MASK (0x3F<<0) 103#define TA_MASK (0x3F << 0)
107#define TS_MASK (1<<8) 104#define TS_MASK (1 << 8)
108 105
109/* Timing parameters PIO mode 0 */ 106/* Timing parameters PIO mode 0 */
110#define SBC_IDE_PIO0_TCSOE (0x04<<29) 107#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
111#define SBC_IDE_PIO0_TOECS (0x01<<26) 108#define SBC_IDE_PIO0_TOECS (0x01 << 26)
112#define SBC_IDE_PIO0_TWCS (0x02<<28) 109#define SBC_IDE_PIO0_TWCS (0x02 << 28)
113#define SBC_IDE_PIO0_TCSH (0x08<<24) 110#define SBC_IDE_PIO0_TCSH (0x08 << 24)
114#define SBC_IDE_PIO0_TCSOFF (0x07<<20) 111#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
115#define SBC_IDE_PIO0_TWP (0x10<<14) 112#define SBC_IDE_PIO0_TWP (0x10 << 14)
116#define SBC_IDE_PIO0_TCSW (0x04<<10) 113#define SBC_IDE_PIO0_TCSW (0x04 << 10)
117#define SBC_IDE_PIO0_TPM (0x0<<6) 114#define SBC_IDE_PIO0_TPM (0x00 << 6)
118#define SBC_IDE_PIO0_TA (0x15<<0) 115#define SBC_IDE_PIO0_TA (0x15 << 0)
119/* Timing parameters PIO mode 1 */ 116/* Timing parameters PIO mode 1 */
120#define SBC_IDE_PIO1_TCSOE (0x03<<29) 117#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
121#define SBC_IDE_PIO1_TOECS (0x01<<26) 118#define SBC_IDE_PIO1_TOECS (0x01 << 26)
122#define SBC_IDE_PIO1_TWCS (0x01<<28) 119#define SBC_IDE_PIO1_TWCS (0x01 << 28)
123#define SBC_IDE_PIO1_TCSH (0x06<<24) 120#define SBC_IDE_PIO1_TCSH (0x06 << 24)
124#define SBC_IDE_PIO1_TCSOFF (0x06<<20) 121#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
125#define SBC_IDE_PIO1_TWP (0x08<<14) 122#define SBC_IDE_PIO1_TWP (0x08 << 14)
126#define SBC_IDE_PIO1_TCSW (0x03<<10) 123#define SBC_IDE_PIO1_TCSW (0x03 << 10)
127#define SBC_IDE_PIO1_TPM (0x00<<6) 124#define SBC_IDE_PIO1_TPM (0x00 << 6)
128#define SBC_IDE_PIO1_TA (0x0B<<0) 125#define SBC_IDE_PIO1_TA (0x0B << 0)
129/* Timing parameters PIO mode 2 */ 126/* Timing parameters PIO mode 2 */
130#define SBC_IDE_PIO2_TCSOE (0x05<<29) 127#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
131#define SBC_IDE_PIO2_TOECS (0x01<<26) 128#define SBC_IDE_PIO2_TOECS (0x01 << 26)
132#define SBC_IDE_PIO2_TWCS (0x01<<28) 129#define SBC_IDE_PIO2_TWCS (0x01 << 28)
133#define SBC_IDE_PIO2_TCSH (0x07<<24) 130#define SBC_IDE_PIO2_TCSH (0x07 << 24)
134#define SBC_IDE_PIO2_TCSOFF (0x07<<20) 131#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
135#define SBC_IDE_PIO2_TWP (0x1F<<14) 132#define SBC_IDE_PIO2_TWP (0x1F << 14)
136#define SBC_IDE_PIO2_TCSW (0x05<<10) 133#define SBC_IDE_PIO2_TCSW (0x05 << 10)
137#define SBC_IDE_PIO2_TPM (0x00<<6) 134#define SBC_IDE_PIO2_TPM (0x00 << 6)
138#define SBC_IDE_PIO2_TA (0x22<<0) 135#define SBC_IDE_PIO2_TA (0x22 << 0)
139/* Timing parameters PIO mode 3 */ 136/* Timing parameters PIO mode 3 */
140#define SBC_IDE_PIO3_TCSOE (0x05<<29) 137#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
141#define SBC_IDE_PIO3_TOECS (0x01<<26) 138#define SBC_IDE_PIO3_TOECS (0x01 << 26)
142#define SBC_IDE_PIO3_TWCS (0x01<<28) 139#define SBC_IDE_PIO3_TWCS (0x01 << 28)
143#define SBC_IDE_PIO3_TCSH (0x0D<<24) 140#define SBC_IDE_PIO3_TCSH (0x0D << 24)
144#define SBC_IDE_PIO3_TCSOFF (0x0D<<20) 141#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
145#define SBC_IDE_PIO3_TWP (0x15<<14) 142#define SBC_IDE_PIO3_TWP (0x15 << 14)
146#define SBC_IDE_PIO3_TCSW (0x05<<10) 143#define SBC_IDE_PIO3_TCSW (0x05 << 10)
147#define SBC_IDE_PIO3_TPM (0x00<<6) 144#define SBC_IDE_PIO3_TPM (0x00 << 6)
148#define SBC_IDE_PIO3_TA (0x1A<<0) 145#define SBC_IDE_PIO3_TA (0x1A << 0)
149/* Timing parameters PIO mode 4 */ 146/* Timing parameters PIO mode 4 */
150#define SBC_IDE_PIO4_TCSOE (0x04<<29) 147#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
151#define SBC_IDE_PIO4_TOECS (0x01<<26) 148#define SBC_IDE_PIO4_TOECS (0x01 << 26)
152#define SBC_IDE_PIO4_TWCS (0x01<<28) 149#define SBC_IDE_PIO4_TWCS (0x01 << 28)
153#define SBC_IDE_PIO4_TCSH (0x04<<24) 150#define SBC_IDE_PIO4_TCSH (0x04 << 24)
154#define SBC_IDE_PIO4_TCSOFF (0x04<<20) 151#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
155#define SBC_IDE_PIO4_TWP (0x0D<<14) 152#define SBC_IDE_PIO4_TWP (0x0D << 14)
156#define SBC_IDE_PIO4_TCSW (0x03<<10) 153#define SBC_IDE_PIO4_TCSW (0x03 << 10)
157#define SBC_IDE_PIO4_TPM (0x00<<6) 154#define SBC_IDE_PIO4_TPM (0x00 << 6)
158#define SBC_IDE_PIO4_TA (0x12<<0) 155#define SBC_IDE_PIO4_TA (0x12 << 0)
159/* Timing parameters MDMA mode 0 */ 156/* Timing parameters MDMA mode 0 */
160#define SBC_IDE_MDMA0_TCSOE (0x03<<29) 157#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
161#define SBC_IDE_MDMA0_TOECS (0x01<<26) 158#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
162#define SBC_IDE_MDMA0_TWCS (0x01<<28) 159#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
163#define SBC_IDE_MDMA0_TCSH (0x07<<24) 160#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
164#define SBC_IDE_MDMA0_TCSOFF (0x07<<20) 161#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
165#define SBC_IDE_MDMA0_TWP (0x0C<<14) 162#define SBC_IDE_MDMA0_TWP (0x0C << 14)
166#define SBC_IDE_MDMA0_TCSW (0x03<<10) 163#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
167#define SBC_IDE_MDMA0_TPM (0x00<<6) 164#define SBC_IDE_MDMA0_TPM (0x00 << 6)
168#define SBC_IDE_MDMA0_TA (0x0F<<0) 165#define SBC_IDE_MDMA0_TA (0x0F << 0)
169/* Timing parameters MDMA mode 1 */ 166/* Timing parameters MDMA mode 1 */
170#define SBC_IDE_MDMA1_TCSOE (0x05<<29) 167#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
171#define SBC_IDE_MDMA1_TOECS (0x01<<26) 168#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
172#define SBC_IDE_MDMA1_TWCS (0x01<<28) 169#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
173#define SBC_IDE_MDMA1_TCSH (0x05<<24) 170#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
174#define SBC_IDE_MDMA1_TCSOFF (0x05<<20) 171#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
175#define SBC_IDE_MDMA1_TWP (0x0F<<14) 172#define SBC_IDE_MDMA1_TWP (0x0F << 14)
176#define SBC_IDE_MDMA1_TCSW (0x05<<10) 173#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
177#define SBC_IDE_MDMA1_TPM (0x00<<6) 174#define SBC_IDE_MDMA1_TPM (0x00 << 6)
178#define SBC_IDE_MDMA1_TA (0x15<<0) 175#define SBC_IDE_MDMA1_TA (0x15 << 0)
179/* Timing parameters MDMA mode 2 */ 176/* Timing parameters MDMA mode 2 */
180#define SBC_IDE_MDMA2_TCSOE (0x04<<29) 177#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
181#define SBC_IDE_MDMA2_TOECS (0x01<<26) 178#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
182#define SBC_IDE_MDMA2_TWCS (0x01<<28) 179#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
183#define SBC_IDE_MDMA2_TCSH (0x04<<24) 180#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
184#define SBC_IDE_MDMA2_TCSOFF (0x04<<20) 181#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
185#define SBC_IDE_MDMA2_TWP (0x0D<<14) 182#define SBC_IDE_MDMA2_TWP (0x0D << 14)
186#define SBC_IDE_MDMA2_TCSW (0x04<<10) 183#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
187#define SBC_IDE_MDMA2_TPM (0x00<<6) 184#define SBC_IDE_MDMA2_TPM (0x00 << 6)
188#define SBC_IDE_MDMA2_TA (0x12<<0) 185#define SBC_IDE_MDMA2_TA (0x12 << 0)
189 186
190#define SBC_IDE_TIMING(mode) \ 187#define SBC_IDE_TIMING(mode) \
191 SBC_IDE_##mode##_TWCS | \ 188 (SBC_IDE_##mode##_TWCS | \
192 SBC_IDE_##mode##_TCSH | \ 189 SBC_IDE_##mode##_TCSH | \
193 SBC_IDE_##mode##_TCSOFF | \ 190 SBC_IDE_##mode##_TCSOFF | \
194 SBC_IDE_##mode##_TWP | \ 191 SBC_IDE_##mode##_TWP | \
195 SBC_IDE_##mode##_TCSW | \ 192 SBC_IDE_##mode##_TCSW | \
196 SBC_IDE_##mode##_TPM | \ 193 SBC_IDE_##mode##_TPM | \
197 SBC_IDE_##mode##_TA 194 SBC_IDE_##mode##_TA)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 1bd4e27caf6b..dae4eca2417e 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,7 +33,6 @@
33#ifndef _AU1000_PSC_H_ 33#ifndef _AU1000_PSC_H_
34#define _AU1000_PSC_H_ 34#define _AU1000_PSC_H_
35 35
36
37/* The PSC base addresses. */ 36/* The PSC base addresses. */
38#ifdef CONFIG_SOC_AU1550 37#ifdef CONFIG_SOC_AU1550
39#define PSC0_BASE_ADDR 0xb1a00000 38#define PSC0_BASE_ADDR 0xb1a00000
@@ -47,8 +46,8 @@
47#define PSC1_BASE_ADDR 0xb1b00000 46#define PSC1_BASE_ADDR 0xb1b00000
48#endif 47#endif
49 48
50/* The PSC select and control registers are common to 49/*
51 * all protocols. 50 * The PSC select and control registers are common to all protocols.
52 */ 51 */
53#define PSC_SEL_OFFSET 0x00000000 52#define PSC_SEL_OFFSET 0x00000000
54#define PSC_CTRL_OFFSET 0x00000004 53#define PSC_CTRL_OFFSET 0x00000004
@@ -59,18 +58,17 @@
59#define PSC_SEL_CLK_SERCLK (2 << 4) 58#define PSC_SEL_CLK_SERCLK (2 << 4)
60 59
61#define PSC_SEL_PS_MASK 0x00000007 60#define PSC_SEL_PS_MASK 0x00000007
62#define PSC_SEL_PS_DISABLED (0) 61#define PSC_SEL_PS_DISABLED 0
63#define PSC_SEL_PS_SPIMODE (2) 62#define PSC_SEL_PS_SPIMODE 2
64#define PSC_SEL_PS_I2SMODE (3) 63#define PSC_SEL_PS_I2SMODE 3
65#define PSC_SEL_PS_AC97MODE (4) 64#define PSC_SEL_PS_AC97MODE 4
66#define PSC_SEL_PS_SMBUSMODE (5) 65#define PSC_SEL_PS_SMBUSMODE 5
67 66
68#define PSC_CTRL_DISABLE (0) 67#define PSC_CTRL_DISABLE 0
69#define PSC_CTRL_SUSPEND (2) 68#define PSC_CTRL_SUSPEND 2
70#define PSC_CTRL_ENABLE (3) 69#define PSC_CTRL_ENABLE 3
71 70
72/* AC97 Registers. 71/* AC97 Registers. */
73*/
74#define PSC_AC97CFG_OFFSET 0x00000008 72#define PSC_AC97CFG_OFFSET 0x00000008
75#define PSC_AC97MSK_OFFSET 0x0000000c 73#define PSC_AC97MSK_OFFSET 0x0000000c
76#define PSC_AC97PCR_OFFSET 0x00000010 74#define PSC_AC97PCR_OFFSET 0x00000010
@@ -95,8 +93,7 @@
95#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) 93#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
96#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) 94#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
97 95
98/* AC97 Config Register. 96/* AC97 Config Register. */
99*/
100#define PSC_AC97CFG_RT_MASK (3 << 30) 97#define PSC_AC97CFG_RT_MASK (3 << 30)
101#define PSC_AC97CFG_RT_FIFO1 (0 << 30) 98#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
102#define PSC_AC97CFG_RT_FIFO2 (1 << 30) 99#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
@@ -118,20 +115,19 @@
118#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) 115#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
119#define PSC_AC97CFG_GE_ENABLE (1) 116#define PSC_AC97CFG_GE_ENABLE (1)
120 117
121/* Enable slots 3-12. 118/* Enable slots 3-12. */
122*/
123#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) 119#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
124#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) 120#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
125 121
126/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. 122/*
123 * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
127 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the 124 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
128 * arithmetic in the macro. 125 * arithmetic in the macro.
129 */ 126 */
130#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21) 127#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
131#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) 128#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
132 129
133/* AC97 Mask Register. 130/* AC97 Mask Register. */
134*/
135#define PSC_AC97MSK_GR (1 << 25) 131#define PSC_AC97MSK_GR (1 << 25)
136#define PSC_AC97MSK_CD (1 << 24) 132#define PSC_AC97MSK_CD (1 << 24)
137#define PSC_AC97MSK_RR (1 << 13) 133#define PSC_AC97MSK_RR (1 << 13)
@@ -148,8 +144,7 @@
148 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ 144 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
149 PSC_AC97MSK_RD | PSC_AC97MSK_TD) 145 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
150 146
151/* AC97 Protocol Control Register. 147/* AC97 Protocol Control Register. */
152*/
153#define PSC_AC97PCR_RC (1 << 6) 148#define PSC_AC97PCR_RC (1 << 6)
154#define PSC_AC97PCR_RP (1 << 5) 149#define PSC_AC97PCR_RP (1 << 5)
155#define PSC_AC97PCR_RS (1 << 4) 150#define PSC_AC97PCR_RS (1 << 4)
@@ -157,8 +152,7 @@
157#define PSC_AC97PCR_TP (1 << 1) 152#define PSC_AC97PCR_TP (1 << 1)
158#define PSC_AC97PCR_TS (1 << 0) 153#define PSC_AC97PCR_TS (1 << 0)
159 154
160/* AC97 Status register (read only). 155/* AC97 Status register (read only). */
161*/
162#define PSC_AC97STAT_CB (1 << 26) 156#define PSC_AC97STAT_CB (1 << 26)
163#define PSC_AC97STAT_CP (1 << 25) 157#define PSC_AC97STAT_CP (1 << 25)
164#define PSC_AC97STAT_CR (1 << 24) 158#define PSC_AC97STAT_CR (1 << 24)
@@ -174,8 +168,7 @@
174#define PSC_AC97STAT_DR (1 << 1) 168#define PSC_AC97STAT_DR (1 << 1)
175#define PSC_AC97STAT_SR (1 << 0) 169#define PSC_AC97STAT_SR (1 << 0)
176 170
177/* AC97 Event Register. 171/* AC97 Event Register. */
178*/
179#define PSC_AC97EVNT_GR (1 << 25) 172#define PSC_AC97EVNT_GR (1 << 25)
180#define PSC_AC97EVNT_CD (1 << 24) 173#define PSC_AC97EVNT_CD (1 << 24)
181#define PSC_AC97EVNT_RR (1 << 13) 174#define PSC_AC97EVNT_RR (1 << 13)
@@ -187,22 +180,18 @@
187#define PSC_AC97EVNT_RD (1 << 5) 180#define PSC_AC97EVNT_RD (1 << 5)
188#define PSC_AC97EVNT_TD (1 << 4) 181#define PSC_AC97EVNT_TD (1 << 4)
189 182
190/* CODEC Command Register. 183/* CODEC Command Register. */
191*/
192#define PSC_AC97CDC_RD (1 << 25) 184#define PSC_AC97CDC_RD (1 << 25)
193#define PSC_AC97CDC_ID_MASK (3 << 23) 185#define PSC_AC97CDC_ID_MASK (3 << 23)
194#define PSC_AC97CDC_INDX_MASK (0x7f << 16) 186#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
195#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23) 187#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
196#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) 188#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
197 189
198/* AC97 Reset Control Register. 190/* AC97 Reset Control Register. */
199*/
200#define PSC_AC97RST_RST (1 << 1) 191#define PSC_AC97RST_RST (1 << 1)
201#define PSC_AC97RST_SNC (1 << 0) 192#define PSC_AC97RST_SNC (1 << 0)
202 193
203 194/* PSC in I2S Mode. */
204/* PSC in I2S Mode.
205*/
206typedef struct psc_i2s { 195typedef struct psc_i2s {
207 u32 psc_sel; 196 u32 psc_sel;
208 u32 psc_ctrl; 197 u32 psc_ctrl;
@@ -215,8 +204,7 @@ typedef struct psc_i2s {
215 u32 psc_i2sudf; 204 u32 psc_i2sudf;
216} psc_i2s_t; 205} psc_i2s_t;
217 206
218/* I2S Config Register. 207/* I2S Config Register. */
219*/
220#define PSC_I2SCFG_RT_MASK (3 << 30) 208#define PSC_I2SCFG_RT_MASK (3 << 30)
221#define PSC_I2SCFG_RT_FIFO1 (0 << 30) 209#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
222#define PSC_I2SCFG_RT_FIFO2 (1 << 30) 210#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
@@ -247,8 +235,7 @@ typedef struct psc_i2s {
247#define PSC_I2SCFG_MLJ (1 << 10) 235#define PSC_I2SCFG_MLJ (1 << 10)
248#define PSC_I2SCFG_XM (1 << 9) 236#define PSC_I2SCFG_XM (1 << 9)
249 237
250/* The word length equation is simply LEN+1. 238/* The word length equation is simply LEN+1. */
251 */
252#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) 239#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
253#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) 240#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
254 241
@@ -256,8 +243,7 @@ typedef struct psc_i2s {
256#define PSC_I2SCFG_MLF (1 << 1) 243#define PSC_I2SCFG_MLF (1 << 1)
257#define PSC_I2SCFG_MS (1 << 0) 244#define PSC_I2SCFG_MS (1 << 0)
258 245
259/* I2S Mask Register. 246/* I2S Mask Register. */
260*/
261#define PSC_I2SMSK_RR (1 << 13) 247#define PSC_I2SMSK_RR (1 << 13)
262#define PSC_I2SMSK_RO (1 << 12) 248#define PSC_I2SMSK_RO (1 << 12)
263#define PSC_I2SMSK_RU (1 << 11) 249#define PSC_I2SMSK_RU (1 << 11)
@@ -271,8 +257,7 @@ typedef struct psc_i2s {
271 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ 257 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
272 PSC_I2SMSK_RD | PSC_I2SMSK_TD) 258 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
273 259
274/* I2S Protocol Control Register. 260/* I2S Protocol Control Register. */
275*/
276#define PSC_I2SPCR_RC (1 << 6) 261#define PSC_I2SPCR_RC (1 << 6)
277#define PSC_I2SPCR_RP (1 << 5) 262#define PSC_I2SPCR_RP (1 << 5)
278#define PSC_I2SPCR_RS (1 << 4) 263#define PSC_I2SPCR_RS (1 << 4)
@@ -280,8 +265,7 @@ typedef struct psc_i2s {
280#define PSC_I2SPCR_TP (1 << 1) 265#define PSC_I2SPCR_TP (1 << 1)
281#define PSC_I2SPCR_TS (1 << 0) 266#define PSC_I2SPCR_TS (1 << 0)
282 267
283/* I2S Status register (read only). 268/* I2S Status register (read only). */
284*/
285#define PSC_I2SSTAT_RF (1 << 13) 269#define PSC_I2SSTAT_RF (1 << 13)
286#define PSC_I2SSTAT_RE (1 << 12) 270#define PSC_I2SSTAT_RE (1 << 12)
287#define PSC_I2SSTAT_RR (1 << 11) 271#define PSC_I2SSTAT_RR (1 << 11)
@@ -294,8 +278,7 @@ typedef struct psc_i2s {
294#define PSC_I2SSTAT_DR (1 << 1) 278#define PSC_I2SSTAT_DR (1 << 1)
295#define PSC_I2SSTAT_SR (1 << 0) 279#define PSC_I2SSTAT_SR (1 << 0)
296 280
297/* I2S Event Register. 281/* I2S Event Register. */
298*/
299#define PSC_I2SEVNT_RR (1 << 13) 282#define PSC_I2SEVNT_RR (1 << 13)
300#define PSC_I2SEVNT_RO (1 << 12) 283#define PSC_I2SEVNT_RO (1 << 12)
301#define PSC_I2SEVNT_RU (1 << 11) 284#define PSC_I2SEVNT_RU (1 << 11)
@@ -305,8 +288,7 @@ typedef struct psc_i2s {
305#define PSC_I2SEVNT_RD (1 << 5) 288#define PSC_I2SEVNT_RD (1 << 5)
306#define PSC_I2SEVNT_TD (1 << 4) 289#define PSC_I2SEVNT_TD (1 << 4)
307 290
308/* PSC in SPI Mode. 291/* PSC in SPI Mode. */
309*/
310typedef struct psc_spi { 292typedef struct psc_spi {
311 u32 psc_sel; 293 u32 psc_sel;
312 u32 psc_ctrl; 294 u32 psc_ctrl;
@@ -318,8 +300,7 @@ typedef struct psc_spi {
318 u32 psc_spitxrx; 300 u32 psc_spitxrx;
319} psc_spi_t; 301} psc_spi_t;
320 302
321/* SPI Config Register. 303/* SPI Config Register. */
322*/
323#define PSC_SPICFG_RT_MASK (3 << 30) 304#define PSC_SPICFG_RT_MASK (3 << 30)
324#define PSC_SPICFG_RT_FIFO1 (0 << 30) 305#define PSC_SPICFG_RT_FIFO1 (0 << 30)
325#define PSC_SPICFG_RT_FIFO2 (1 << 30) 306#define PSC_SPICFG_RT_FIFO2 (1 << 30)
@@ -355,8 +336,7 @@ typedef struct psc_spi {
355#define PSC_SPICFG_MLF (1 << 1) 336#define PSC_SPICFG_MLF (1 << 1)
356#define PSC_SPICFG_MO (1 << 0) 337#define PSC_SPICFG_MO (1 << 0)
357 338
358/* SPI Mask Register. 339/* SPI Mask Register. */
359*/
360#define PSC_SPIMSK_MM (1 << 16) 340#define PSC_SPIMSK_MM (1 << 16)
361#define PSC_SPIMSK_RR (1 << 13) 341#define PSC_SPIMSK_RR (1 << 13)
362#define PSC_SPIMSK_RO (1 << 12) 342#define PSC_SPIMSK_RO (1 << 12)
@@ -371,16 +351,14 @@ typedef struct psc_spi {
371 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ 351 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
372 PSC_SPIMSK_MD) 352 PSC_SPIMSK_MD)
373 353
374/* SPI Protocol Control Register. 354/* SPI Protocol Control Register. */
375*/
376#define PSC_SPIPCR_RC (1 << 6) 355#define PSC_SPIPCR_RC (1 << 6)
377#define PSC_SPIPCR_SP (1 << 5) 356#define PSC_SPIPCR_SP (1 << 5)
378#define PSC_SPIPCR_SS (1 << 4) 357#define PSC_SPIPCR_SS (1 << 4)
379#define PSC_SPIPCR_TC (1 << 2) 358#define PSC_SPIPCR_TC (1 << 2)
380#define PSC_SPIPCR_MS (1 << 0) 359#define PSC_SPIPCR_MS (1 << 0)
381 360
382/* SPI Status register (read only). 361/* SPI Status register (read only). */
383*/
384#define PSC_SPISTAT_RF (1 << 13) 362#define PSC_SPISTAT_RF (1 << 13)
385#define PSC_SPISTAT_RE (1 << 12) 363#define PSC_SPISTAT_RE (1 << 12)
386#define PSC_SPISTAT_RR (1 << 11) 364#define PSC_SPISTAT_RR (1 << 11)
@@ -393,8 +371,7 @@ typedef struct psc_spi {
393#define PSC_SPISTAT_DR (1 << 1) 371#define PSC_SPISTAT_DR (1 << 1)
394#define PSC_SPISTAT_SR (1 << 0) 372#define PSC_SPISTAT_SR (1 << 0)
395 373
396/* SPI Event Register. 374/* SPI Event Register. */
397*/
398#define PSC_SPIEVNT_MM (1 << 16) 375#define PSC_SPIEVNT_MM (1 << 16)
399#define PSC_SPIEVNT_RR (1 << 13) 376#define PSC_SPIEVNT_RR (1 << 13)
400#define PSC_SPIEVNT_RO (1 << 12) 377#define PSC_SPIEVNT_RO (1 << 12)
@@ -405,13 +382,11 @@ typedef struct psc_spi {
405#define PSC_SPIEVNT_SD (1 << 5) 382#define PSC_SPIEVNT_SD (1 << 5)
406#define PSC_SPIEVNT_MD (1 << 4) 383#define PSC_SPIEVNT_MD (1 << 4)
407 384
408/* Transmit register control. 385/* Transmit register control. */
409*/
410#define PSC_SPITXRX_LC (1 << 29) 386#define PSC_SPITXRX_LC (1 << 29)
411#define PSC_SPITXRX_SR (1 << 28) 387#define PSC_SPITXRX_SR (1 << 28)
412 388
413/* PSC in SMBus (I2C) Mode. 389/* PSC in SMBus (I2C) Mode. */
414*/
415typedef struct psc_smb { 390typedef struct psc_smb {
416 u32 psc_sel; 391 u32 psc_sel;
417 u32 psc_ctrl; 392 u32 psc_ctrl;
@@ -424,8 +399,7 @@ typedef struct psc_smb {
424 u32 psc_smbtmr; 399 u32 psc_smbtmr;
425} psc_smb_t; 400} psc_smb_t;
426 401
427/* SMBus Config Register. 402/* SMBus Config Register. */
428*/
429#define PSC_SMBCFG_RT_MASK (3 << 30) 403#define PSC_SMBCFG_RT_MASK (3 << 30)
430#define PSC_SMBCFG_RT_FIFO1 (0 << 30) 404#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
431#define PSC_SMBCFG_RT_FIFO2 (1 << 30) 405#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
@@ -452,8 +426,7 @@ typedef struct psc_smb {
452 426
453#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) 427#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
454 428
455/* SMBus Mask Register. 429/* SMBus Mask Register. */
456*/
457#define PSC_SMBMSK_DN (1 << 30) 430#define PSC_SMBMSK_DN (1 << 30)
458#define PSC_SMBMSK_AN (1 << 29) 431#define PSC_SMBMSK_AN (1 << 29)
459#define PSC_SMBMSK_AL (1 << 28) 432#define PSC_SMBMSK_AL (1 << 28)
@@ -471,13 +444,11 @@ typedef struct psc_smb {
471 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ 444 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
472 PSC_SMBMSK_MD) 445 PSC_SMBMSK_MD)
473 446
474/* SMBus Protocol Control Register. 447/* SMBus Protocol Control Register. */
475*/
476#define PSC_SMBPCR_DC (1 << 2) 448#define PSC_SMBPCR_DC (1 << 2)
477#define PSC_SMBPCR_MS (1 << 0) 449#define PSC_SMBPCR_MS (1 << 0)
478 450
479/* SMBus Status register (read only). 451/* SMBus Status register (read only). */
480*/
481#define PSC_SMBSTAT_BB (1 << 28) 452#define PSC_SMBSTAT_BB (1 << 28)
482#define PSC_SMBSTAT_RF (1 << 13) 453#define PSC_SMBSTAT_RF (1 << 13)
483#define PSC_SMBSTAT_RE (1 << 12) 454#define PSC_SMBSTAT_RE (1 << 12)
@@ -491,8 +462,7 @@ typedef struct psc_smb {
491#define PSC_SMBSTAT_DR (1 << 1) 462#define PSC_SMBSTAT_DR (1 << 1)
492#define PSC_SMBSTAT_SR (1 << 0) 463#define PSC_SMBSTAT_SR (1 << 0)
493 464
494/* SMBus Event Register. 465/* SMBus Event Register. */
495*/
496#define PSC_SMBEVNT_DN (1 << 30) 466#define PSC_SMBEVNT_DN (1 << 30)
497#define PSC_SMBEVNT_AN (1 << 29) 467#define PSC_SMBEVNT_AN (1 << 29)
498#define PSC_SMBEVNT_AL (1 << 28) 468#define PSC_SMBEVNT_AL (1 << 28)
@@ -510,15 +480,13 @@ typedef struct psc_smb {
510 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ 480 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
511 PSC_SMBEVNT_MD) 481 PSC_SMBEVNT_MD)
512 482
513/* Transmit register control. 483/* Transmit register control. */
514*/
515#define PSC_SMBTXRX_RSR (1 << 28) 484#define PSC_SMBTXRX_RSR (1 << 28)
516#define PSC_SMBTXRX_STP (1 << 29) 485#define PSC_SMBTXRX_STP (1 << 29)
517#define PSC_SMBTXRX_DATAMASK (0xff) 486#define PSC_SMBTXRX_DATAMASK 0xff
518 487
519/* SMBus protocol timers register. 488/* SMBus protocol timers register. */
520*/ 489#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
521#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
522#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) 490#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
523#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) 491#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
524#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) 492#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
@@ -526,5 +494,4 @@ typedef struct psc_smb {
526#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) 494#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
527#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) 495#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
528 496
529
530#endif /* _AU1000_PSC_H_ */ 497#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index eedd048a7261..27f26102b1bb 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * AMD Alchemy DB1200 Referrence Board 2 * AMD Alchemy DBAu1200 Reference Board
3 * Board Registers defines. 3 * Board register defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
6 * 6 *
@@ -27,26 +27,25 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the DBAu1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
48 47
49#define BCSR_KSEG1_ADDR 0xB9800000 48#define BCSR_KSEG1_ADDR 0xB9800000
50 49
51typedef volatile struct 50typedef volatile struct
52{ 51{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_U0RXD 0x1000 105#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000 106#define BCSR_STATUS_U1RXD 0x2000
108 107
109#define BCSR_SWITCHES_OCTAL 0x00FF 108#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080 109#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
122#define BCSR_RESETS_DC 0x0004 121#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008 122#define BCSR_RESETS_IDE 0x0008
124#define BCSR_RESETS_TV 0x0010 123#define BCSR_RESETS_TV 0x0010
125/* not resets but in the same register */ 124/* Not resets but in the same register */
126#define BCSR_RESETS_PWMR1mUX 0x0800 125#define BCSR_RESETS_PWMR1MUX 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
160#define BCSR_INT_PC0STSCHG 0x0008 159#define BCSR_INT_PC0STSCHG 0x0008
161#define BCSR_INT_PC1 0x0010 160#define BCSR_INT_PC1 0x0010
162#define BCSR_INT_PC1STSCHG 0x0020 161#define BCSR_INT_PC1STSCHG 0x0020
163#define BCSR_INT_DC 0x0040 162#define BCSR_INT_DC 0x0040
164#define BCSR_INT_FLASHBUSY 0x0080 163#define BCSR_INT_FLASHBUSY 0x0080
165#define BCSR_INT_PC0INSERT 0x0100 164#define BCSR_INT_PC0INSERT 0x0100
166#define BCSR_INT_PC0EJECT 0x0200 165#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
179#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
180#define IDE_RQSIZE 128 179#define IDE_RQSIZE 128
181 180
182#define NAND_PHYS_ADDR 0x20000000 181#define NAND_PHYS_ADDR 0x20000000
183 182
184/* 183/*
185 * External Interrupts for Pb1200 as of 8/6/2004. 184 * External Interrupts for DBAu1200 as of 8/6/2004.
186 * Bit positions in the CPLD registers can be calculated by taking 185 * Bit positions in the CPLD registers can be calculated by taking
187 * the interrupt define and subtracting the DB1200_INT_BEGIN value. 186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
188 * 187 *
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
211}; 210};
212 211
213 212
214/* For drivers/pcmcia/au1000_db1x00.c */ 213/*
215 214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
216/* PCMCIA Db1x00 specific defines */ 215 */
217 216#define PCMCIA_MAX_SOCK 1
218#define PCMCIA_MAX_SOCK 1 217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
219#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
220 218
221/* VPP/VCC */ 219/* VPP/VCC */
222#define SET_VCC_VPP(VCC, VPP, SLOT)\ 220#define SET_VCC_VPP(VCC, VPP, SLOT) \
223 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
224 222
225#define BOARD_PC0_INT DB1200_PC0_INT 223#define BOARD_PC0_INT DB1200_PC0_INT
226#define BOARD_PC1_INT DB1200_PC1_INT 224#define BOARD_PC1_INT DB1200_PC1_INT
227#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
228 226
229/* Nand chip select */ 227/* NAND chip select */
230#define NAND_CS 1 228#define NAND_CS 1
231 229
232#endif /* __ASM_DB1200_H */ 230#endif /* __ASM_DB1200_H */
233
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index e7a88ba35833..612ae90dbcb8 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * AMD Alchemy DB1x00 Reference Boards 2 * AMD Alchemy DBAu1x00 Reference Boards
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 * 7 *
9 * ######################################################################## 8 * ########################################################################
@@ -32,26 +31,26 @@
32 31
33#ifdef CONFIG_MIPS_DB1550 32#ifdef CONFIG_MIPS_DB1550
34 33
35#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
36#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
37#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
38#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
39 38
40#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define AC97_PSC_BASE PSC1_BASE_ADDR 40#define AC97_PSC_BASE PSC1_BASE_ADDR
42#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
43#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR
44 43
45#define BCSR_KSEG1_ADDR 0xAF000000 44#define BCSR_KSEG1_ADDR 0xAF000000
46#define NAND_PHYS_ADDR 0x20000000 45#define NAND_PHYS_ADDR 0x20000000
47 46
48#else 47#else
49#define BCSR_KSEG1_ADDR 0xAE000000 48#define BCSR_KSEG1_ADDR 0xAE000000
50#endif 49#endif
51 50
52/* 51/*
53 * Overlay data structure of the Db1x00 board registers. 52 * Overlay data structure of the DBAu1x00 board registers.
54 * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx 53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
55 */ 54 */
56typedef volatile struct 55typedef volatile struct
57{ 56{
@@ -138,18 +137,19 @@ typedef volatile struct
138 137
139#define BCSR_SWRESET_RESET 0x0080 138#define BCSR_SWRESET_RESET 0x0080
140 139
141/* PCMCIA Db1x00 specific defines */ 140/* PCMCIA DBAu1x00 specific defines */
142#define PCMCIA_MAX_SOCK 1 141#define PCMCIA_MAX_SOCK 1
143#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
144 143
145/* VPP/VCC */ 144/* VPP/VCC */
146#define SET_VCC_VPP(VCC, VPP, SLOT)\ 145#define SET_VCC_VPP(VCC, VPP, SLOT)\
147 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
148 147
149/* SD controller macros */
150/* 148/*
151 * Detect card. 149 * SD controller macros
152 */ 150 */
151
152/* Detect card. */
153#define mmc_card_inserted(_n_, _res_) \ 153#define mmc_card_inserted(_n_, _res_) \
154 do { \ 154 do { \
155 BCSR * const bcsr = (BCSR *)0xAE000000; \ 155 BCSR * const bcsr = (BCSR *)0xAE000000; \
@@ -176,10 +176,10 @@ typedef volatile struct
176 unsigned long mmc_pwr, mmc_wp, board_specific; \ 176 unsigned long mmc_pwr, mmc_wp, board_specific; \
177 if ((_n_)) { \ 177 if ((_n_)) { \
178 mmc_pwr = BCSR_BOARD_SD1_PWR; \ 178 mmc_pwr = BCSR_BOARD_SD1_PWR; \
179 mmc_wp = BCSR_BOARD_SD1_WP; \ 179 mmc_wp = BCSR_BOARD_SD1_WP; \
180 } else { \ 180 } else { \
181 mmc_pwr = BCSR_BOARD_SD0_PWR; \ 181 mmc_pwr = BCSR_BOARD_SD0_PWR; \
182 mmc_wp = BCSR_BOARD_SD0_WP; \ 182 mmc_wp = BCSR_BOARD_SD0_WP; \
183 } \ 183 } \
184 board_specific = au_readl((unsigned long)(&bcsr->specific)); \ 184 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
185 if (!(board_specific & mmc_wp)) {/* low means card present */ \ 185 if (!(board_specific & mmc_wp)) {/* low means card present */ \
@@ -190,17 +190,19 @@ typedef volatile struct
190 } while (0) 190 } while (0)
191 191
192 192
193/* NAND defines */ 193/*
194/* Timing values as described in databook, * ns value stripped of 194 * NAND defines
195 *
196 * Timing values as described in databook, * ns value stripped of the
195 * lower 2 bits. 197 * lower 2 bits.
196 * These defines are here rather than an SOC1550 generic file because 198 * These defines are here rather than an Au1550 generic file because
197 * the parts chosen on another board may be different and may require 199 * the parts chosen on another board may be different and may require
198 * different timings. 200 * different timings.
199 */ 201 */
200#define NAND_T_H (18 >> 2) 202#define NAND_T_H (18 >> 2)
201#define NAND_T_PUL (30 >> 2) 203#define NAND_T_PUL (30 >> 2)
202#define NAND_T_SU (30 >> 2) 204#define NAND_T_SU (30 >> 2)
203#define NAND_T_WH (30 >> 2) 205#define NAND_T_WH (30 >> 2)
204 206
205/* Bitfield shift amounts */ 207/* Bitfield shift amounts */
206#define NAND_T_H_SHIFT 0 208#define NAND_T_H_SHIFT 0
@@ -208,16 +210,15 @@ typedef volatile struct
208#define NAND_T_SU_SHIFT 8 210#define NAND_T_SU_SHIFT 8
209#define NAND_T_WH_SHIFT 12 211#define NAND_T_WH_SHIFT 12
210 212
211#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 213#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
212 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 214 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
213 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 215 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
214 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 216 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
215#define NAND_CS 1 217#define NAND_CS 1
216 218
217/* should be done by yamon */ 219/* Should be done by YAMON */
218#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 220#define NAND_STCFG 0x00400005 /* 8-bit NAND */
219#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 221#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
220#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 222#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
221 223
222#endif /* __ASM_DB1X00_H */ 224#endif /* __ASM_DB1X00_H */
223
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index b52e0e7ee3fb..6d1ff9060e44 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1000 Referrence Board 2 * Alchemy Semi Pb1000 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -28,145 +27,61 @@
28#define __ASM_PB1000_H 27#define __ASM_PB1000_H
29 28
30/* PCMCIA PB1000 specific defines */ 29/* PCMCIA PB1000 specific defines */
31#define PCMCIA_MAX_SOCK 1 30#define PCMCIA_MAX_SOCK 1
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
33 32
34#define PB1000_PCR 0xBE000000 33#define PB1000_PCR 0xBE000000
35# define PCR_SLOT_0_VPP0 (1<<0) 34# define PCR_SLOT_0_VPP0 (1 << 0)
36# define PCR_SLOT_0_VPP1 (1<<1) 35# define PCR_SLOT_0_VPP1 (1 << 1)
37# define PCR_SLOT_0_VCC0 (1<<2) 36# define PCR_SLOT_0_VCC0 (1 << 2)
38# define PCR_SLOT_0_VCC1 (1<<3) 37# define PCR_SLOT_0_VCC1 (1 << 3)
39# define PCR_SLOT_0_RST (1<<4) 38# define PCR_SLOT_0_RST (1 << 4)
40 39# define PCR_SLOT_1_VPP0 (1 << 8)
41# define PCR_SLOT_1_VPP0 (1<<8) 40# define PCR_SLOT_1_VPP1 (1 << 9)
42# define PCR_SLOT_1_VPP1 (1<<9) 41# define PCR_SLOT_1_VCC0 (1 << 10)
43# define PCR_SLOT_1_VCC0 (1<<10) 42# define PCR_SLOT_1_VCC1 (1 << 11)
44# define PCR_SLOT_1_VCC1 (1<<11) 43# define PCR_SLOT_1_RST (1 << 12)
45# define PCR_SLOT_1_RST (1<<12) 44
46 45#define PB1000_MDR 0xBE000004
47#define PB1000_MDR 0xBE000004 46# define MDR_PI (1 << 5) /* PCMCIA int latch */
48# define MDR_PI (1<<5) /* pcmcia int latch */ 47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
49# define MDR_EPI (1<<14) /* enable pcmcia int */ 48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
50# define MDR_CPI (1<<15) /* clear pcmcia int */ 49
51 50#define PB1000_ACR1 0xBE000008
52#define PB1000_ACR1 0xBE000008 51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
53# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
54# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
55# define ACR1_SLOT_0_READY (1<<2) /* ready */ 54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
56# define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
57# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
58# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
59# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
60# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
61# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
62# define ACR1_SLOT_1_READY (1<<10) /* ready */ 61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
63# define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
64# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
65# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
66# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 65
67 66#define CPLD_AUX0 0xBE00000C
68#define CPLD_AUX0 0xBE00000C 67#define CPLD_AUX1 0xBE000010
69#define CPLD_AUX1 0xBE000010 68#define CPLD_AUX2 0xBE000014
70#define CPLD_AUX2 0xBE000014
71 69
72/* Voltage levels */ 70/* Voltage levels */
73 71
74/* VPPEN1 - VPPEN0 */ 72/* VPPEN1 - VPPEN0 */
75#define VPP_GND ((0<<1) | (0<<0)) 73#define VPP_GND ((0 << 1) | (0 << 0))
76#define VPP_5V ((1<<1) | (0<<0)) 74#define VPP_5V ((1 << 1) | (0 << 0))
77#define VPP_3V ((0<<1) | (1<<0)) 75#define VPP_3V ((0 << 1) | (1 << 0))
78#define VPP_12V ((0<<1) | (1<<0)) 76#define VPP_12V ((0 << 1) | (1 << 0))
79#define VPP_HIZ ((1<<1) | (1<<0)) 77#define VPP_HIZ ((1 << 1) | (1 << 0))
80 78
81/* VCCEN1 - VCCEN0 */ 79/* VCCEN1 - VCCEN0 */
82#define VCC_3V ((0<<1) | (1<<0)) 80#define VCC_3V ((0 << 1) | (1 << 0))
83#define VCC_5V ((1<<1) | (0<<0)) 81#define VCC_5V ((1 << 1) | (0 << 0))
84#define VCC_HIZ ((0<<1) | (0<<0)) 82#define VCC_HIZ ((0 << 1) | (0 << 0))
85 83
86/* VPP/VCC */ 84/* VPP/VCC */
87#define SET_VCC_VPP(VCC, VPP, SLOT)\ 85#define SET_VCC_VPP(VCC, VPP, SLOT) \
88 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
89
90
91/* PCI PB1000 specific defines */
92/* The reason these defines are here instead of au1000.h is because
93 * the Au1000 does not have a PCI bus controller so the PCI implementation
94 * on the some of the older Pb1000 boards was very board specific.
95 */
96#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
97
98#define SDRAM_DEVID 0xBA010000
99#define SDRAM_CMD 0xBA010004
100#define SDRAM_CLASS 0xBA010008
101#define SDRAM_MISC 0xBA01000C
102#define SDRAM_MBAR 0xBA010010
103
104#define PCI_IO_DATA_PORT 0xBA800000
105
106#define PCI_IO_ADDR 0xBE00001C
107#define PCI_INT_ACK 0xBBC00000
108#define PCI_IO_READ 0xBBC00020
109#define PCI_IO_WRITE 0xBBC00030
110
111#define PCI_BRIDGE_CONFIG 0xBE000018
112
113#define PCI_IO_START 0x10000000
114#define PCI_IO_END 0x1000ffff
115#define PCI_MEM_START 0x18000000
116#define PCI_MEM_END 0x18ffffff
117
118#define PCI_FIRST_DEVFN 0
119#define PCI_LAST_DEVFN 1
120
121static inline u8 au_pci_io_readb(u32 addr)
122{
123 writel(addr, PCI_IO_ADDR);
124 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
125 return (readl(PCI_IO_DATA_PORT) & 0xff);
126}
127
128static inline u16 au_pci_io_readw(u32 addr)
129{
130 writel(addr, PCI_IO_ADDR);
131 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
132 return (readl(PCI_IO_DATA_PORT) & 0xffff);
133}
134
135static inline u32 au_pci_io_readl(u32 addr)
136{
137 writel(addr, PCI_IO_ADDR);
138 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
139 return readl(PCI_IO_DATA_PORT);
140}
141
142static inline void au_pci_io_writeb(u8 val, u32 addr)
143{
144 writel(addr, PCI_IO_ADDR);
145 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
146 writel(val, PCI_IO_DATA_PORT);
147}
148
149static inline void au_pci_io_writew(u16 val, u32 addr)
150{
151 writel(addr, PCI_IO_ADDR);
152 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
153 writel(val, PCI_IO_DATA_PORT);
154}
155
156static inline void au_pci_io_writel(u32 val, u32 addr)
157{
158 writel(addr, PCI_IO_ADDR);
159 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
160 writel(val, PCI_IO_DATA_PORT);
161}
162
163static inline void set_sdram_extbyte(void)
164{
165 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
166}
167
168static inline void set_slot_extbyte(void)
169{
170 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
171}
172#endif /* __ASM_PB1000_H */ 87#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 63aa3926b297..b1a60f1cbd02 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1100 Referrence Board 2 * Alchemy Semi Pb1100 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -27,59 +26,60 @@
27#ifndef __ASM_PB1100_H 26#ifndef __ASM_PB1100_H
28#define __ASM_PB1100_H 27#define __ASM_PB1100_H
29 28
30#define PB1100_IDENT 0xAE000000 29#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 30#define BOARD_STATUS_REG 0xAE000004
32# define PB1100_ROM_SEL (1<<15) 31# define PB1100_ROM_SEL (1 << 15)
33# define PB1100_ROM_SIZ (1<<14) 32# define PB1100_ROM_SIZ (1 << 14)
34# define PB1100_SWAP_BOOT (1<<13) 33# define PB1100_SWAP_BOOT (1 << 13)
35# define PB1100_FLASH_WP (1<<12) 34# define PB1100_FLASH_WP (1 << 12)
36# define PB1100_ROM_H_STS (1<<11) 35# define PB1100_ROM_H_STS (1 << 11)
37# define PB1100_ROM_L_STS (1<<10) 36# define PB1100_ROM_L_STS (1 << 10)
38# define PB1100_FLASH_H_STS (1<<9) 37# define PB1100_FLASH_H_STS (1 << 9)
39# define PB1100_FLASH_L_STS (1<<8) 38# define PB1100_FLASH_L_STS (1 << 8)
40# define PB1100_SRAM_SIZ (1<<7) 39# define PB1100_SRAM_SIZ (1 << 7)
41# define PB1100_TSC_BUSY (1<<6) 40# define PB1100_TSC_BUSY (1 << 6)
42# define PB1100_PCMCIA_VS_MASK (3<<4) 41# define PB1100_PCMCIA_VS_MASK (3 << 4)
43# define PB1100_RS232_CD (1<<3) 42# define PB1100_RS232_CD (1 << 3)
44# define PB1100_RS232_CTS (1<<2) 43# define PB1100_RS232_CTS (1 << 2)
45# define PB1100_RS232_DSR (1<<1) 44# define PB1100_RS232_DSR (1 << 1)
46# define PB1100_RS232_RI (1<<0) 45# define PB1100_RS232_RI (1 << 0)
47 46
48#define PB1100_IRDA_RS232 0xAE00000C 47#define PB1100_IRDA_RS232 0xAE00000C
49# define PB1100_IRDA_FULL (0<<14) /* full power */ 48# define PB1100_IRDA_FULL (0 << 14) /* full power */
50# define PB1100_IRDA_SHUTDOWN (1<<14) 49# define PB1100_IRDA_SHUTDOWN (1 << 14)
51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
53# define PB1100_IRDA_FIR (1<<13) 52# define PB1100_IRDA_FIR (1 << 13)
54 53
55#define PCMCIA_BOARD_REG 0xAE000010 54#define PCMCIA_BOARD_REG 0xAE000010
56# define PB1100_SD_WP1_RO (1<<15) /* read only */ 55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
57# define PB1100_SD_WP0_RO (1<<14) /* read only */ 56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
60# define PB1100_SEL_SD_CONN1 (1<<9) 59# define PB1100_SEL_SD_CONN1 (1 << 9)
61# define PB1100_SEL_SD_CONN0 (1<<8) 60# define PB1100_SEL_SD_CONN0 (1 << 8)
62# define PC_DEASSERT_RST (1<<7) 61# define PC_DEASSERT_RST (1 << 7)
63# define PC_DRV_EN (1<<4) 62# define PC_DRV_EN (1 << 4)
64 63
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 65
67#define PB1100_RST_VDDI 0xAE00001C 66#define PB1100_RST_VDDI 0xAE00001C
68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
69# define PB1100_VDDI_MASK (0x1F) 68# define PB1100_VDDI_MASK 0x1F
70 69
71#define PB1100_LEDS 0xAE000018 70#define PB1100_LEDS 0xAE000018
72 71
73/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. 72/*
74 * 7:0 is the LED Display's decimal points. 73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */ 75 */
76#define PB1100_HEX_LED 0xAE000018 76#define PB1100_HEX_LED 0xAE000018
77 77
78/* PCMCIA PB1100 specific defines */ 78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0 79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81 81
82/* VPP/VCC */ 82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) 83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84 84
85#endif /* __ASM_PB1100_H */ 85#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b42..c8618df88cb5 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy PB1200 Referrence Board 2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
@@ -27,21 +27,20 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the Pb1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_SD1WP 0x0800 105#define BCSR_STATUS_SD1WP 0x0800
107#define BCSR_STATUS_U0RXD 0x1000 106#define BCSR_STATUS_U0RXD 0x1000
108#define BCSR_STATUS_U1RXD 0x2000 107#define BCSR_STATUS_U1RXD 0x2000
109 108
110#define BCSR_SWITCHES_OCTAL 0x00FF 109#define BCSR_SWITCHES_OCTAL 0x00FF
111#define BCSR_SWITCHES_DIP_1 0x0080 110#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
123#define BCSR_RESETS_DC 0x0004 122#define BCSR_RESETS_DC 0x0004
124#define BCSR_RESETS_IDE 0x0008 123#define BCSR_RESETS_IDE 0x0008
125/* not resets but in the same register */ 124/* not resets but in the same register */
126#define BCSR_RESETS_WSCFSM 0x0800 125#define BCSR_RESETS_WSCFSM 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
130#define BCSR_RESETS_SD1MUX 0x8000 129#define BCSR_RESETS_SD1MUX 0x8000
131 130
132#define BCSR_PCMCIA_PC0VPP 0x0003 131#define BCSR_PCMCIA_PC0VPP 0x0003
133#define BCSR_PCMCIA_PC0VCC 0x000C 132#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
163#define BCSR_INT_PC0STSCHG 0x0008 162#define BCSR_INT_PC0STSCHG 0x0008
164#define BCSR_INT_PC1 0x0010 163#define BCSR_INT_PC1 0x0010
165#define BCSR_INT_PC1STSCHG 0x0020 164#define BCSR_INT_PC1STSCHG 0x0020
166#define BCSR_INT_DC 0x0040 165#define BCSR_INT_DC 0x0040
167#define BCSR_INT_FLASHBUSY 0x0080 166#define BCSR_INT_FLASHBUSY 0x0080
168#define BCSR_INT_PC0INSERT 0x0100 167#define BCSR_INT_PC0INSERT 0x0100
169#define BCSR_INT_PC0EJECT 0x0200 168#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
174#define BCSR_INT_SD1INSERT 0x4000 173#define BCSR_INT_SD1INSERT 0x4000
175#define BCSR_INT_SD1EJECT 0x8000 174#define BCSR_INT_SD1EJECT 0x8000
176 175
177/* PCMCIA Db1x00 specific defines */
178#define PCMCIA_MAX_SOCK 1
179#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
180
181/* VPP/VCC */
182#define SET_VCC_VPP(VCC, VPP, SLOT)\
183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
184
185#define SMC91C111_PHYS_ADDR 0x0D000300 176#define SMC91C111_PHYS_ADDR 0x0D000300
186#define SMC91C111_INT PB1200_ETH_INT 177#define SMC91C111_INT PB1200_ETH_INT
187 178
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
192#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 183#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
193#define IDE_RQSIZE 128 184#define IDE_RQSIZE 128
194 185
195#define NAND_PHYS_ADDR 0x1C000000 186#define NAND_PHYS_ADDR 0x1C000000
196 187
197/* Timing values as described in databook, * ns value stripped of 188/*
189 * Timing values as described in databook, * ns value stripped of
198 * lower 2 bits. 190 * lower 2 bits.
199 * These defines are here rather than an SOC1200 generic file because 191 * These defines are here rather than an Au1200 generic file because
200 * the parts chosen on another board may be different and may require 192 * the parts chosen on another board may be different and may require
201 * different timings. 193 * different timings.
202 */ 194 */
203#define NAND_T_H (18 >> 2) 195#define NAND_T_H (18 >> 2)
204#define NAND_T_PUL (30 >> 2) 196#define NAND_T_PUL (30 >> 2)
205#define NAND_T_SU (30 >> 2) 197#define NAND_T_SU (30 >> 2)
206#define NAND_T_WH (30 >> 2) 198#define NAND_T_WH (30 >> 2)
207 199
208/* Bitfield shift amounts */ 200/* Bitfield shift amounts */
209#define NAND_T_H_SHIFT 0 201#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
211#define NAND_T_SU_SHIFT 8 203#define NAND_T_SU_SHIFT 8
212#define NAND_T_WH_SHIFT 12 204#define NAND_T_WH_SHIFT 12
213 205
214#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 206#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
215 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 207 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
216 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 208 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
217 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 209 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
218
219 210
220/* 211/*
221 * External Interrupts for Pb1200 as of 8/6/2004. 212 * External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
248 PB1200_INT_END = PB1200_INT_BEGIN + 15 239 PB1200_INT_END = PB1200_INT_BEGIN + 15
249}; 240};
250 241
251/* For drivers/pcmcia/au1000_db1x00.c */ 242/*
252#define BOARD_PC0_INT PB1200_PC0_INT 243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
253#define BOARD_PC1_INT PB1200_PC1_INT 244 */
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
255 247
256/* Nand chip select */ 248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */
257#define NAND_CS 1 257#define NAND_CS 1
258 258
259#endif /* __ASM_PB1200_H */ 259#endif /* __ASM_PB1200_H */
260
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index ff6d40c87a25..da51a2eb7b82 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1500 Referrence Board 2 * Alchemy Semi Pb1500 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -27,25 +26,24 @@
27#ifndef __ASM_PB1500_H 26#ifndef __ASM_PB1500_H
28#define __ASM_PB1500_H 27#define __ASM_PB1500_H
29 28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
30 38
31#define IDENT_BOARD_REG 0xAE000000 39#define PB1500_HEX_LED 0xAF000004
32#define BOARD_STATUS_REG 0xAE000004 40#define PB1500_HEX_LED_BLANK 0xAF000008
33#define PCI_BOARD_REG 0xAE000010
34#define PCMCIA_BOARD_REG 0xAE000010
35 #define PC_DEASSERT_RST 0x80
36 #define PC_DRV_EN 0x10
37#define PB1500_G_CONTROL 0xAE000014
38#define PB1500_RST_VDDI 0xAE00001C
39#define PB1500_LEDS 0xAE000018
40 41
41#define PB1500_HEX_LED 0xAF000004 42/* PCMCIA Pb1500 specific defines */
42#define PB1500_HEX_LED_BLANK 0xAF000008 43#define PCMCIA_MAX_SOCK 0
43 44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
44/* PCMCIA PB1500 specific defines */
45#define PCMCIA_MAX_SOCK 0
46#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
47 45
48/* VPP/VCC */ 46/* VPP/VCC */
49#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) 47#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
50 48
51#endif /* __ASM_PB1500_H */ 49#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index c2ab0e2df4ae..6704a11497db 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -30,15 +30,15 @@
30#include <linux/types.h> 30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h> 31#include <asm/mach-au1x00/au1xxx_psc.h>
32 32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37 37
38#define SPI_PSC_BASE PSC0_BASE_ADDR 38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR 39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000 43#define BCSR_PHYS_ADDR 0xAF000000
44 44
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
129#define BCSR_SYSTEM_POWEROFF 0x4000 129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000 130#define BCSR_SYSTEM_RESET 0x8000
131 131
132#define PCMCIA_MAX_SOCK 1 132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134 134
135/* VPP/VCC */ 135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT)\ 136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138 138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS 140#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
144#define PB1550_USER_ONLY 144#define PB1550_USER_ONLY
145#endif 145#endif
146 146
147/* Timing values as described in databook, * ns value stripped of 147/*
148 * Timing values as described in databook, * ns value stripped of
148 * lower 2 bits. 149 * lower 2 bits.
149 * These defines are here rather than an SOC1550 generic file because 150 * These defines are here rather than an SOC1550 generic file because
150 * the parts chosen on another board may be different and may require 151 * the parts chosen on another board may be different and may require
151 * different timings. 152 * different timings.
152 */ 153 */
153#define NAND_T_H (18 >> 2) 154#define NAND_T_H (18 >> 2)
154#define NAND_T_PUL (30 >> 2) 155#define NAND_T_PUL (30 >> 2)
155#define NAND_T_SU (30 >> 2) 156#define NAND_T_SU (30 >> 2)
156#define NAND_T_WH (30 >> 2) 157#define NAND_T_WH (30 >> 2)
157 158
158/* Bitfield shift amounts */ 159/* Bitfield shift amounts */
159#define NAND_T_H_SHIFT 0 160#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
161#define NAND_T_SU_SHIFT 8 162#define NAND_T_SU_SHIFT 8
162#define NAND_T_WH_SHIFT 12 163#define NAND_T_WH_SHIFT 12
163 164
164#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 165#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
165 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 166 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 167 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 168 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
168 169
169#define NAND_CS 1 170#define NAND_CS 1
170 171
171/* should be done by yamon */ 172/* Should be done by YAMON */
172#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 173#define NAND_STCFG 0x00400005 /* 8-bit NAND */
173#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 174#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
174#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 175#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
175 176
176#endif /* __ASM_PB1550_H */ 177#endif /* __ASM_PB1550_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index aa17f658f73c..a46f8e258e6b 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -765,6 +765,9 @@ do { \
765#define read_c0_index() __read_32bit_c0_register($0, 0) 765#define read_c0_index() __read_32bit_c0_register($0, 0)
766#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 766#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
767 767
768#define read_c0_random() __read_32bit_c0_register($1, 0)
769#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
770
768#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 771#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
769#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 772#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
770 773
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 60e2f9338fcd..51b34a48c84a 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -134,6 +134,4 @@
134 134
135#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 135#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
136 136
137#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
138
139#endif /* _ASM_PGTABLE_BITS_H */ 137#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 2f597eea4448..6a0edf72ffbc 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -239,9 +239,10 @@ static inline pte_t pte_mkdirty(pte_t pte)
239static inline pte_t pte_mkyoung(pte_t pte) 239static inline pte_t pte_mkyoung(pte_t pte)
240{ 240{
241 pte.pte_low |= _PAGE_ACCESSED; 241 pte.pte_low |= _PAGE_ACCESSED;
242 if (pte.pte_low & _PAGE_READ) 242 if (pte.pte_low & _PAGE_READ) {
243 pte.pte_low |= _PAGE_SILENT_READ; 243 pte.pte_low |= _PAGE_SILENT_READ;
244 pte.pte_high |= _PAGE_SILENT_READ; 244 pte.pte_high |= _PAGE_SILENT_READ;
245 }
245 return pte; 246 return pte;
246} 247}
247#else 248#else
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
index 65778c890a62..4ca3063ed2ce 100644
--- a/include/asm-mips/rtlx.h
+++ b/include/asm-mips/rtlx.h
@@ -3,7 +3,7 @@
3 * 3 *
4 */ 4 */
5 5
6#ifndef __ASM_RTLX_H 6#ifndef __ASM_RTLX_H_
7#define __ASM_RTLX_H_ 7#define __ASM_RTLX_H_
8 8
9#include <irq.h> 9#include <irq.h>
@@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep);
29extern unsigned int rtlx_write_poll(int index); 29extern unsigned int rtlx_write_poll(int index);
30 30
31enum rtlx_state { 31enum rtlx_state {
32 RTLX_STATE_UNUSED, 32 RTLX_STATE_UNUSED = 0,
33 RTLX_STATE_INITIALISED, 33 RTLX_STATE_INITIALISED,
34 RTLX_STATE_REMOTE_READY, 34 RTLX_STATE_REMOTE_READY,
35 RTLX_STATE_OPENED 35 RTLX_STATE_OPENED
36}; 36};
37 37
38#define RTLX_BUFFER_SIZE 1024 38#define RTLX_BUFFER_SIZE 2048
39 39
40/* each channel supports read and write. 40/* each channel supports read and write.
41 linux (vpe0) reads lx_buffer and writes rt_buffer 41 linux (vpe0) reads lx_buffer and writes rt_buffer
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 14:55:51 -0500