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-rw-r--r--include/asm-mips/vr41xx/capcella.h2
-rw-r--r--include/asm-mips/vr41xx/cmbvr4133.h6
-rw-r--r--include/asm-mips/vr41xx/e55.h43
-rw-r--r--include/asm-mips/vr41xx/irq.h101
-rw-r--r--include/asm-mips/vr41xx/mpc30x.h2
-rw-r--r--include/asm-mips/vr41xx/tb0219.h2
-rw-r--r--include/asm-mips/vr41xx/tb0226.h2
-rw-r--r--include/asm-mips/vr41xx/tb0287.h2
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h53
-rw-r--r--include/asm-mips/vr41xx/vrc4173.h221
-rw-r--r--include/asm-mips/vr41xx/workpad.h43
11 files changed, 107 insertions, 370 deletions
diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h
index d10ffda50de7..e0ee05a3dfcc 100644
--- a/include/asm-mips/vr41xx/capcella.h
+++ b/include/asm-mips/vr41xx/capcella.h
@@ -20,7 +20,7 @@
20#ifndef __ZAO_CAPCELLA_H 20#ifndef __ZAO_CAPCELLA_H
21#define __ZAO_CAPCELLA_H 21#define __ZAO_CAPCELLA_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
index 42af389019ea..9490ade58b46 100644
--- a/include/asm-mips/vr41xx/cmbvr4133.h
+++ b/include/asm-mips/vr41xx/cmbvr4133.h
@@ -15,8 +15,7 @@
15#ifndef __NEC_CMBVR4133_H 15#ifndef __NEC_CMBVR4133_H
16#define __NEC_CMBVR4133_H 16#define __NEC_CMBVR4133_H
17 17
18#include <asm/addrspace.h> 18#include <asm/vr41xx/irq.h>
19#include <asm/vr41xx/vr41xx.h>
20 19
21/* 20/*
22 * General-Purpose I/O Pin Number 21 * General-Purpose I/O Pin Number
@@ -55,7 +54,4 @@
55#define IDE_SECONDARY_IRQ I8259_IRQ(15) 54#define IDE_SECONDARY_IRQ I8259_IRQ(15)
56#define I8259_IRQ_LAST IDE_SECONDARY_IRQ 55#define I8259_IRQ_LAST IDE_SECONDARY_IRQ
57 56
58#define RTC_PORT(x) (0xaf000100 + (x))
59#define RTC_IO_EXTENT 0x140
60
61#endif /* __NEC_CMBVR4133_H */ 57#endif /* __NEC_CMBVR4133_H */
diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h
deleted file mode 100644
index 558f2269bf37..000000000000
--- a/include/asm-mips/vr41xx/e55.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65.
3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __CASIO_E55_H
21#define __CASIO_E55_H
22
23#include <asm/addrspace.h>
24#include <asm/vr41xx/vr41xx.h>
25
26/*
27 * Board specific address mapping
28 */
29#define VR41XX_ISA_MEM_BASE 0x10000000
30#define VR41XX_ISA_MEM_SIZE 0x04000000
31
32/* VR41XX_ISA_IO_BASE includes offset from real base. */
33#define VR41XX_ISA_IO_BASE 0x1400c000
34#define VR41XX_ISA_IO_SIZE 0x03ff4000
35
36#define ISA_BUS_IO_BASE 0
37#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE
38
39#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
40#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE
41#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
42
43#endif /* __CASIO_E55_H */
diff --git a/include/asm-mips/vr41xx/irq.h b/include/asm-mips/vr41xx/irq.h
new file mode 100644
index 000000000000..d315dfbc08f2
--- /dev/null
+++ b/include/asm-mips/vr41xx/irq.h
@@ -0,0 +1,101 @@
1/*
2 * include/asm-mips/vr41xx/irq.h
3 *
4 * Interrupt numbers for NEC VR4100 series.
5 *
6 * Copyright (C) 1999 Michael Klar
7 * Copyright (C) 2001, 2002 Paul Mundt
8 * Copyright (C) 2002 MontaVista Software, Inc.
9 * Copyright (C) 2002 TimeSys Corp.
10 * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef __NEC_VR41XX_IRQ_H
18#define __NEC_VR41XX_IRQ_H
19
20/*
21 * CPU core Interrupt Numbers
22 */
23#define MIPS_CPU_IRQ_BASE 0
24#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
25#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
26#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
27#define INT0_IRQ MIPS_CPU_IRQ(2)
28#define INT1_IRQ MIPS_CPU_IRQ(3)
29#define INT2_IRQ MIPS_CPU_IRQ(4)
30#define INT3_IRQ MIPS_CPU_IRQ(5)
31#define INT4_IRQ MIPS_CPU_IRQ(6)
32#define TIMER_IRQ MIPS_CPU_IRQ(7)
33
34/*
35 * SYINT1 Interrupt Numbers
36 */
37#define SYSINT1_IRQ_BASE 8
38#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
39#define BATTRY_IRQ SYSINT1_IRQ(0)
40#define POWER_IRQ SYSINT1_IRQ(1)
41#define RTCLONG1_IRQ SYSINT1_IRQ(2)
42#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
43/* RFU */
44#define PIU_IRQ SYSINT1_IRQ(5)
45#define AIU_IRQ SYSINT1_IRQ(6)
46#define KIU_IRQ SYSINT1_IRQ(7)
47#define GIUINT_IRQ SYSINT1_IRQ(8)
48#define SIU_IRQ SYSINT1_IRQ(9)
49#define BUSERR_IRQ SYSINT1_IRQ(10)
50#define SOFTINT_IRQ SYSINT1_IRQ(11)
51#define CLKRUN_IRQ SYSINT1_IRQ(12)
52#define DOZEPIU_IRQ SYSINT1_IRQ(13)
53#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
54
55/*
56 * SYSINT2 Interrupt Numbers
57 */
58#define SYSINT2_IRQ_BASE 24
59#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
60#define RTCLONG2_IRQ SYSINT2_IRQ(0)
61#define LED_IRQ SYSINT2_IRQ(1)
62#define HSP_IRQ SYSINT2_IRQ(2)
63#define TCLOCK_IRQ SYSINT2_IRQ(3)
64#define FIR_IRQ SYSINT2_IRQ(4)
65#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
66#define DSIU_IRQ SYSINT2_IRQ(5)
67#define PCI_IRQ SYSINT2_IRQ(6)
68#define SCU_IRQ SYSINT2_IRQ(7)
69#define CSI_IRQ SYSINT2_IRQ(8)
70#define BCU_IRQ SYSINT2_IRQ(9)
71#define ETHERNET_IRQ SYSINT2_IRQ(10)
72#define SYSINT2_IRQ_LAST ETHERNET_IRQ
73
74/*
75 * GIU Interrupt Numbers
76 */
77#define GIU_IRQ_BASE 40
78#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
79#define GIU_IRQ_LAST GIU_IRQ(31)
80
81/*
82 * VRC4173 Interrupt Numbers
83 */
84#define VRC4173_IRQ_BASE 72
85#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
86#define VRC4173_USB_IRQ VRC4173_IRQ(0)
87#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
88#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
89#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
90#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
91#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
92#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
93#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
94#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
95#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
96#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
97/* RFU */
98#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
99#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
100
101#endif /* __NEC_VR41XX_IRQ_H */
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h
index a6cbe4da6667..1d67df843dc3 100644
--- a/include/asm-mips/vr41xx/mpc30x.h
+++ b/include/asm-mips/vr41xx/mpc30x.h
@@ -20,7 +20,7 @@
20#ifndef __VICTOR_MPC30X_H 20#ifndef __VICTOR_MPC30X_H
21#define __VICTOR_MPC30X_H 21#define __VICTOR_MPC30X_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h
index b318b9612a83..dc981b4be0a4 100644
--- a/include/asm-mips/vr41xx/tb0219.h
+++ b/include/asm-mips/vr41xx/tb0219.h
@@ -23,7 +23,7 @@
23#ifndef __TANBAC_TB0219_H 23#ifndef __TANBAC_TB0219_H
24#define __TANBAC_TB0219_H 24#define __TANBAC_TB0219_H
25 25
26#include <asm/vr41xx/vr41xx.h> 26#include <asm/vr41xx/irq.h>
27 27
28/* 28/*
29 * General-Purpose I/O Pin Number 29 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h
index 2513f450e2d6..de527dcfa5f3 100644
--- a/include/asm-mips/vr41xx/tb0226.h
+++ b/include/asm-mips/vr41xx/tb0226.h
@@ -20,7 +20,7 @@
20#ifndef __TANBAC_TB0226_H 20#ifndef __TANBAC_TB0226_H
21#define __TANBAC_TB0226_H 21#define __TANBAC_TB0226_H
22 22
23#include <asm/vr41xx/vr41xx.h> 23#include <asm/vr41xx/irq.h>
24 24
25/* 25/*
26 * General-Purpose I/O Pin Number 26 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/tb0287.h b/include/asm-mips/vr41xx/tb0287.h
index dd9832313afe..61bead68abf0 100644
--- a/include/asm-mips/vr41xx/tb0287.h
+++ b/include/asm-mips/vr41xx/tb0287.h
@@ -22,7 +22,7 @@
22#ifndef __TANBAC_TB0287_H 22#ifndef __TANBAC_TB0287_H
23#define __TANBAC_TB0287_H 23#define __TANBAC_TB0287_H
24 24
25#include <asm/vr41xx/vr41xx.h> 25#include <asm/vr41xx/irq.h>
26 26
27/* 27/*
28 * General-Purpose I/O Pin Number 28 * General-Purpose I/O Pin Number
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 70828d5fae9c..dd3eb3dc5886 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -74,59 +74,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
74/* 74/*
75 * Interrupt Control Unit 75 * Interrupt Control Unit
76 */ 76 */
77/* CPU core Interrupt Numbers */
78#define MIPS_CPU_IRQ_BASE 0
79#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
80#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
81#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
82#define INT0_IRQ MIPS_CPU_IRQ(2)
83#define INT1_IRQ MIPS_CPU_IRQ(3)
84#define INT2_IRQ MIPS_CPU_IRQ(4)
85#define INT3_IRQ MIPS_CPU_IRQ(5)
86#define INT4_IRQ MIPS_CPU_IRQ(6)
87#define TIMER_IRQ MIPS_CPU_IRQ(7)
88
89/* SYINT1 Interrupt Numbers */
90#define SYSINT1_IRQ_BASE 8
91#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
92#define BATTRY_IRQ SYSINT1_IRQ(0)
93#define POWER_IRQ SYSINT1_IRQ(1)
94#define RTCLONG1_IRQ SYSINT1_IRQ(2)
95#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
96/* RFU */
97#define PIU_IRQ SYSINT1_IRQ(5)
98#define AIU_IRQ SYSINT1_IRQ(6)
99#define KIU_IRQ SYSINT1_IRQ(7)
100#define GIUINT_IRQ SYSINT1_IRQ(8)
101#define SIU_IRQ SYSINT1_IRQ(9)
102#define BUSERR_IRQ SYSINT1_IRQ(10)
103#define SOFTINT_IRQ SYSINT1_IRQ(11)
104#define CLKRUN_IRQ SYSINT1_IRQ(12)
105#define DOZEPIU_IRQ SYSINT1_IRQ(13)
106#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
107
108/* SYSINT2 Interrupt Numbers */
109#define SYSINT2_IRQ_BASE 24
110#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
111#define RTCLONG2_IRQ SYSINT2_IRQ(0)
112#define LED_IRQ SYSINT2_IRQ(1)
113#define HSP_IRQ SYSINT2_IRQ(2)
114#define TCLOCK_IRQ SYSINT2_IRQ(3)
115#define FIR_IRQ SYSINT2_IRQ(4)
116#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
117#define DSIU_IRQ SYSINT2_IRQ(5)
118#define PCI_IRQ SYSINT2_IRQ(6)
119#define SCU_IRQ SYSINT2_IRQ(7)
120#define CSI_IRQ SYSINT2_IRQ(8)
121#define BCU_IRQ SYSINT2_IRQ(9)
122#define ETHERNET_IRQ SYSINT2_IRQ(10)
123#define SYSINT2_IRQ_LAST ETHERNET_IRQ
124
125/* GIU Interrupt Numbers */
126#define GIU_IRQ_BASE 40
127#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
128#define GIU_IRQ_LAST GIU_IRQ(31)
129
130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); 77extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
131extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); 78extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
132 79
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
deleted file mode 100644
index 96fdcd54cec7..000000000000
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * vrc4173.h, Include file for NEC VRC4173.
3 *
4 * Copyright (C) 2000 Michael R. McDonald
5 * Copyright (C) 2001-2003 Montavista Software Inc.
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
7 * Copyright (C) 2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
8 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __NEC_VRC4173_H
25#define __NEC_VRC4173_H
26
27#include <asm/io.h>
28
29/*
30 * Interrupt Number
31 */
32#define VRC4173_IRQ_BASE 72
33#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
34#define VRC4173_USB_IRQ VRC4173_IRQ(0)
35#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
36#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
37#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
38#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
39#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
40#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
41#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
42#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
43#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
44#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
45/* RFU */
46#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
47#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
48
49/*
50 * PCI I/O accesses
51 */
52#ifdef CONFIG_VRC4173
53
54extern unsigned long vrc4173_io_offset;
55
56#define set_vrc4173_io_offset(offset) do { vrc4173_io_offset = (offset); } while (0)
57
58#define vrc4173_outb(val,port) outb((val), vrc4173_io_offset+(port))
59#define vrc4173_outw(val,port) outw((val), vrc4173_io_offset+(port))
60#define vrc4173_outl(val,port) outl((val), vrc4173_io_offset+(port))
61#define vrc4173_outb_p(val,port) outb_p((val), vrc4173_io_offset+(port))
62#define vrc4173_outw_p(val,port) outw_p((val), vrc4173_io_offset+(port))
63#define vrc4173_outl_p(val,port) outl_p((val), vrc4173_io_offset+(port))
64
65#define vrc4173_inb(port) inb(vrc4173_io_offset+(port))
66#define vrc4173_inw(port) inw(vrc4173_io_offset+(port))
67#define vrc4173_inl(port) inl(vrc4173_io_offset+(port))
68#define vrc4173_inb_p(port) inb_p(vrc4173_io_offset+(port))
69#define vrc4173_inw_p(port) inw_p(vrc4173_io_offset+(port))
70#define vrc4173_inl_p(port) inl_p(vrc4173_io_offset+(port))
71
72#define vrc4173_outsb(port,addr,count) outsb(vrc4173_io_offset+(port),(addr),(count))
73#define vrc4173_outsw(port,addr,count) outsw(vrc4173_io_offset+(port),(addr),(count))
74#define vrc4173_outsl(port,addr,count) outsl(vrc4173_io_offset+(port),(addr),(count))
75
76#define vrc4173_insb(port,addr,count) insb(vrc4173_io_offset+(port),(addr),(count))
77#define vrc4173_insw(port,addr,count) insw(vrc4173_io_offset+(port),(addr),(count))
78#define vrc4173_insl(port,addr,count) insl(vrc4173_io_offset+(port),(addr),(count))
79
80#else
81
82#define set_vrc4173_io_offset(offset) do {} while (0)
83
84#define vrc4173_outb(val,port) do {} while (0)
85#define vrc4173_outw(val,port) do {} while (0)
86#define vrc4173_outl(val,port) do {} while (0)
87#define vrc4173_outb_p(val,port) do {} while (0)
88#define vrc4173_outw_p(val,port) do {} while (0)
89#define vrc4173_outl_p(val,port) do {} while (0)
90
91#define vrc4173_inb(port) 0
92#define vrc4173_inw(port) 0
93#define vrc4173_inl(port) 0
94#define vrc4173_inb_p(port) 0
95#define vrc4173_inw_p(port) 0
96#define vrc4173_inl_p(port) 0
97
98#define vrc4173_outsb(port,addr,count) do {} while (0)
99#define vrc4173_outsw(port,addr,count) do {} while (0)
100#define vrc4173_outsl(port,addr,count) do {} while (0)
101
102#define vrc4173_insb(port,addr,count) do {} while (0)
103#define vrc4173_insw(port,addr,count) do {} while (0)
104#define vrc4173_insl(port,addr,count) do {} while (0)
105
106#endif
107
108/*
109 * Clock Mask Unit
110 */
111typedef enum vrc4173_clock {
112 VRC4173_PIU_CLOCK,
113 VRC4173_KIU_CLOCK,
114 VRC4173_AIU_CLOCK,
115 VRC4173_PS2_CH1_CLOCK,
116 VRC4173_PS2_CH2_CLOCK,
117 VRC4173_USBU_PCI_CLOCK,
118 VRC4173_CARDU1_PCI_CLOCK,
119 VRC4173_CARDU2_PCI_CLOCK,
120 VRC4173_AC97U_PCI_CLOCK,
121 VRC4173_USBU_48MHz_CLOCK,
122 VRC4173_EXT_48MHz_CLOCK,
123 VRC4173_48MHz_CLOCK,
124} vrc4173_clock_t;
125
126#ifdef CONFIG_VRC4173
127
128extern void vrc4173_supply_clock(vrc4173_clock_t clock);
129extern void vrc4173_mask_clock(vrc4173_clock_t clock);
130
131#else
132
133static inline void vrc4173_supply_clock(vrc4173_clock_t clock) {}
134static inline void vrc4173_mask_clock(vrc4173_clock_t clock) {}
135
136#endif
137
138/*
139 * Interupt Control Unit
140 */
141
142#define VRC4173_PIUINT_COMMAND 0x0040
143#define VRC4173_PIUINT_DATA 0x0020
144#define VRC4173_PIUINT_PAGE1 0x0010
145#define VRC4173_PIUINT_PAGE0 0x0008
146#define VRC4173_PIUINT_DATALOST 0x0004
147#define VRC4173_PIUINT_STATUSCHANGE 0x0001
148
149#ifdef CONFIG_VRC4173
150
151extern void vrc4173_enable_piuint(uint16_t mask);
152extern void vrc4173_disable_piuint(uint16_t mask);
153
154#else
155
156static inline void vrc4173_enable_piuint(uint16_t mask) {}
157static inline void vrc4173_disable_piuint(uint16_t mask) {}
158
159#endif
160
161#define VRC4173_AIUINT_INPUT_DMAEND 0x0800
162#define VRC4173_AIUINT_INPUT_DMAHALT 0x0400
163#define VRC4173_AIUINT_INPUT_DATALOST 0x0200
164#define VRC4173_AIUINT_INPUT_DATA 0x0100
165#define VRC4173_AIUINT_OUTPUT_DMAEND 0x0008
166#define VRC4173_AIUINT_OUTPUT_DMAHALT 0x0004
167#define VRC4173_AIUINT_OUTPUT_NODATA 0x0002
168
169#ifdef CONFIG_VRC4173
170
171extern void vrc4173_enable_aiuint(uint16_t mask);
172extern void vrc4173_disable_aiuint(uint16_t mask);
173
174#else
175
176static inline void vrc4173_enable_aiuint(uint16_t mask) {}
177static inline void vrc4173_disable_aiuint(uint16_t mask) {}
178
179#endif
180
181#define VRC4173_KIUINT_DATALOST 0x0004
182#define VRC4173_KIUINT_DATAREADY 0x0002
183#define VRC4173_KIUINT_SCAN 0x0001
184
185#ifdef CONFIG_VRC4173
186
187extern void vrc4173_enable_kiuint(uint16_t mask);
188extern void vrc4173_disable_kiuint(uint16_t mask);
189
190#else
191
192static inline void vrc4173_enable_kiuint(uint16_t mask) {}
193static inline void vrc4173_disable_kiuint(uint16_t mask) {}
194
195#endif
196
197/*
198 * General-Purpose I/O Unit
199 */
200typedef enum vrc4173_function {
201 PS2_CHANNEL1,
202 PS2_CHANNEL2,
203 TOUCHPANEL,
204 KEYBOARD_8SCANLINES,
205 KEYBOARD_10SCANLINES,
206 KEYBOARD_12SCANLINES,
207 GPIO_0_15PINS,
208 GPIO_16_20PINS,
209} vrc4173_function_t;
210
211#ifdef CONFIG_VRC4173
212
213extern void vrc4173_select_function(vrc4173_function_t function);
214
215#else
216
217static inline void vrc4173_select_function(vrc4173_function_t function) {}
218
219#endif
220
221#endif /* __NEC_VRC4173_H */
diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h
deleted file mode 100644
index 6bfa9c009a9b..000000000000
--- a/include/asm-mips/vr41xx/workpad.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * workpad.h, Include file for IBM WorkPad z50.
3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __IBM_WORKPAD_H
21#define __IBM_WORKPAD_H
22
23#include <asm/addrspace.h>
24#include <asm/vr41xx/vr41xx.h>
25
26/*
27 * Board specific address mapping
28 */
29#define VR41XX_ISA_MEM_BASE 0x10000000
30#define VR41XX_ISA_MEM_SIZE 0x04000000
31
32/* VR41XX_ISA_IO_BASE includes offset from real base. */
33#define VR41XX_ISA_IO_BASE 0x15000000
34#define VR41XX_ISA_IO_SIZE 0x03000000
35
36#define ISA_BUS_IO_BASE 0
37#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE
38
39#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
40#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE
41#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1)
42
43#endif /* __IBM_WORKPAD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 07:23:37 -0400