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-rw-r--r--include/asm-mips/txx9/generic.h7
-rw-r--r--include/asm-mips/txx9/rbtx4927.h26
-rw-r--r--include/asm-mips/txx9/rbtx4938.h52
-rw-r--r--include/asm-mips/txx9/tx3927.h19
-rw-r--r--include/asm-mips/txx9/tx4927.h63
-rw-r--r--include/asm-mips/txx9/tx4938.h243
6 files changed, 142 insertions, 268 deletions
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index d8756660523d..cbae37ec3d88 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -12,6 +12,8 @@
12#include <linux/ioport.h> /* for struct resource */ 12#include <linux/ioport.h> /* for struct resource */
13 13
14extern struct resource txx9_ce_res[]; 14extern struct resource txx9_ce_res[];
15#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start)
16extern unsigned int txx9_pcode;
15extern char txx9_pcode_str[8]; 17extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base, 18void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size); 19 unsigned long size);
@@ -19,6 +21,11 @@ void txx9_reg_res_init(unsigned int pcode, unsigned long base,
19extern unsigned int txx9_master_clock; 21extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock; 22extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock; 23extern unsigned int txx9_gbus_clock;
24#define TXX9_IMCLK (txx9_gbus_clock / 2)
25
26extern int txx9_ccfg_toeon;
27struct uart_port;
28int early_serial_txx9_setup(struct uart_port *port);
22 29
23struct pci_dev; 30struct pci_dev;
24struct txx9_board_vec { 31struct txx9_board_vec {
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index bf194589216f..6fcec912c143 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -34,7 +34,23 @@
34#define RBTX4927_PCIIO 0x16000000 34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000 35#define RBTX4927_PCIIO_SIZE 0x01000000
36 36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) 37#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
38#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
39#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
40#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
41#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
42#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
43#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
44
45/* Ethernet port address */
46#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280)
47
48#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
49#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
50#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
51#define rbtx4927_softresetlock_addr \
52 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
53#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
38 54
39/* bits for ISTAT/IMASK/IMSTAT */ 55/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0 56#define RBTX4927_INTB_PCID 0
@@ -62,13 +78,7 @@
62#define RBTX4927_ISA_IO_OFFSET 0 78#define RBTX4927_ISA_IO_OFFSET 0
63#endif 79#endif
64 80
65#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL 81#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
66#define RBTX4927_SW_RESET_DO_SET 0x01
67
68#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
69#define RBTX4927_SW_RESET_ENABLE_SET 0x01
70
71#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
72#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) 82#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
73 83
74void rbtx4927_prom_init(void); 84void rbtx4927_prom_init(void);
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index 2f5d5e705a41..9f0441a28126 100644
--- a/include/asm-mips/txx9/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -15,35 +15,31 @@
15#include <asm/txx9irq.h> 15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h> 16#include <asm/txx9/tx4938.h>
17 17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */ 18/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) 19#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) 20#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) 21#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) 22#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) 23#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) 24#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) 25#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) 26#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) 27#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) 28#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) 29#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) 30#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) 31#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) 32#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) 33#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) 34#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) 35#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) 36#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) 37#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) 38#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) 39#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) 40#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) 41#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) 42#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
47 43
48/* Ethernet port address (Jumperless Mode (W12:Open)) */ 44/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) 45#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index ca414c7624e1..ea79e1b16e71 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -10,17 +10,18 @@
10 10
11#include <asm/txx9/txx927.h> 11#include <asm/txx9/txx927.h>
12 12
13#define TX3927_SDRAMC_REG 0xfffe8000 13#define TX3927_REG_BASE 0xfffe0000UL
14#define TX3927_ROMC_REG 0xfffe9000 14#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15#define TX3927_DMA_REG 0xfffeb000 15#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16#define TX3927_IRC_REG 0xfffec000 16#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
17#define TX3927_PCIC_REG 0xfffed000 17#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
18#define TX3927_CCFG_REG 0xfffee000 18#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
19#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
19#define TX3927_NR_TMR 3 20#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) 21#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2 22#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) 23#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500 24#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
24 25
25struct tx3927_sdramc_reg { 26struct tx3927_sdramc_reg {
26 volatile unsigned long cr[8]; 27 volatile unsigned long cr[8];
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index 46d60afc038b..ceb4b79ff4e3 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -32,32 +32,46 @@
32#include <asm/txx9irq.h> 32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h> 33#include <asm/txx9/tx4927pcic.h>
34 34
35#define TX4927_SDRAMC_REG 0xff1f8000 35#ifdef CONFIG_64BIT
36#define TX4927_EBUSC_REG 0xff1f9000 36#define TX4927_REG_BASE 0xffffffffff1f0000UL
37#define TX4927_PCIC_REG 0xff1fd000 37#else
38#define TX4927_CCFG_REG 0xff1fe000 38#define TX4927_REG_BASE 0xff1f0000UL
39#define TX4927_IRC_REG 0xff1ff600 39#endif
40#define TX4927_REG_SIZE 0x00010000
41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
40#define TX4927_NR_TMR 3 47#define TX4927_NR_TMR 3
41#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) 48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
49#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
42 52
43#define TX4927_IR_INT(n) (2 + (n)) 53#define TX4927_IR_INT(n) (2 + (n))
44#define TX4927_IR_SIO(n) (8 + (n)) 54#define TX4927_IR_SIO(n) (8 + (n))
45#define TX4927_IR_PCIC 16 55#define TX4927_IR_PCIC 16
56#define TX4927_NUM_IR_TMR 3
57#define TX4927_IR_TMR(n) (17 + (n))
46#define TX4927_IR_PCIERR 22 58#define TX4927_IR_PCIERR 22
47#define TX4927_NUM_IR 32 59#define TX4927_NUM_IR 32
48 60
49#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 61#define TX4927_IRC_INT 2 /* IP[2] in Status register */
50 62
63#define TX4927_NUM_PIO 16
64
51struct tx4927_sdramc_reg { 65struct tx4927_sdramc_reg {
52 volatile unsigned long long cr[4]; 66 u64 cr[4];
53 volatile unsigned long long unused0[4]; 67 u64 unused0[4];
54 volatile unsigned long long tr; 68 u64 tr;
55 volatile unsigned long long unused1[2]; 69 u64 unused1[2];
56 volatile unsigned long long cmd; 70 u64 cmd;
57}; 71};
58 72
59struct tx4927_ebusc_reg { 73struct tx4927_ebusc_reg {
60 volatile unsigned long long cr[8]; 74 u64 cr[8];
61}; 75};
62 76
63struct tx4927_ccfg_reg { 77struct tx4927_ccfg_reg {
@@ -160,12 +174,28 @@ struct tx4927_ccfg_reg {
160#define TX4927_CLKCTR_SIO0RST 0x00000002 174#define TX4927_CLKCTR_SIO0RST 0x00000002
161#define TX4927_CLKCTR_SIO1RST 0x00000001 175#define TX4927_CLKCTR_SIO1RST 0x00000001
162 176
163#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) 177#define tx4927_sdramcptr \
178 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
164#define tx4927_pcicptr \ 179#define tx4927_pcicptr \
165 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) 180 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
166#define tx4927_ccfgptr \ 181#define tx4927_ccfgptr \
167 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 182 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
168#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 183#define tx4927_ebuscptr \
184 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
185#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
186
187#define TX4927_REV_PCODE() \
188 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
189
190#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
191#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
192#define TX4927_SDRAMC_SIZE(ch) \
193 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
194
195#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
196#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
197#define TX4927_EBUSC_SIZE(ch) \
198 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
169 199
170/* utilities */ 200/* utilities */
171static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 201static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
@@ -212,6 +242,11 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
212 &tx4927_ccfgptr->ccfg); 242 &tx4927_ccfgptr->ccfg);
213} 243}
214 244
245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void);
247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void);
215int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
216int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
217void tx4927_irq_init(void); 252void tx4927_irq_init(void);
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 12de68a4c10a..1ed969d381d6 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -15,20 +15,11 @@
15/* some controllers are compatible with 4927 */ 15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h> 16#include <asm/txx9/tx4927.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#ifdef CONFIG_64BIT
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
20 20#else
21#define TX4938_PCIIO_0 0x10000000 21#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
22#define TX4938_PCIIO_1 0x01010000 22#endif
23#define TX4938_PCIMEM_0 0x08000000
24#define TX4938_PCIMEM_1 0x11000000
25
26#define TX4938_PCIIO_SIZE_0 0x01000000
27#define TX4938_PCIIO_SIZE_1 0x00010000
28#define TX4938_PCIMEM_SIZE_0 0x08000000
29#define TX4938_PCIMEM_SIZE_1 0x00010000
30
31#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
32#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ 23#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
33 24
34/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ 25/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
@@ -49,149 +40,8 @@
49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 40#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 41#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
51 42
52#define _CONST64(c) c##ull
53
54#include <asm/byteorder.h>
55
56#ifdef __BIG_ENDIAN
57#define endian_def_l2(e1, e2) \
58 volatile unsigned long e1, e2
59#define endian_def_s2(e1, e2) \
60 volatile unsigned short e1, e2
61#define endian_def_sb2(e1, e2, e3) \
62 volatile unsigned short e1;volatile unsigned char e2, e3
63#define endian_def_b2s(e1, e2, e3) \
64 volatile unsigned char e1, e2;volatile unsigned short e3
65#define endian_def_b4(e1, e2, e3, e4) \
66 volatile unsigned char e1, e2, e3, e4
67#else
68#define endian_def_l2(e1, e2) \
69 volatile unsigned long e2, e1
70#define endian_def_s2(e1, e2) \
71 volatile unsigned short e2, e1
72#define endian_def_sb2(e1, e2, e3) \
73 volatile unsigned char e3, e2;volatile unsigned short e1
74#define endian_def_b2s(e1, e2, e3) \
75 volatile unsigned short e3;volatile unsigned char e2, e1
76#define endian_def_b4(e1, e2, e3, e4) \
77 volatile unsigned char e4, e3, e2, e1
78#endif
79
80
81struct tx4938_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87 volatile unsigned long long sfcmd;
88};
89
90struct tx4938_ebusc_reg {
91 volatile unsigned long long cr[8];
92};
93
94struct tx4938_dma_reg {
95 struct tx4938_dma_ch_reg {
96 volatile unsigned long long cha;
97 volatile unsigned long long sar;
98 volatile unsigned long long dar;
99 endian_def_l2(unused0, cntr);
100 endian_def_l2(unused1, sair);
101 endian_def_l2(unused2, dair);
102 endian_def_l2(unused3, ccr);
103 endian_def_l2(unused4, csr);
104 } ch[4];
105 volatile unsigned long long dbr[8];
106 volatile unsigned long long tdhr;
107 volatile unsigned long long midr;
108 endian_def_l2(unused0, mcr);
109};
110
111struct tx4938_aclc_reg {
112 volatile unsigned long acctlen;
113 volatile unsigned long acctldis;
114 volatile unsigned long acregacc;
115 volatile unsigned long unused0;
116 volatile unsigned long acintsts;
117 volatile unsigned long acintmsts;
118 volatile unsigned long acinten;
119 volatile unsigned long acintdis;
120 volatile unsigned long acsemaph;
121 volatile unsigned long unused1[7];
122 volatile unsigned long acgpidat;
123 volatile unsigned long acgpodat;
124 volatile unsigned long acslten;
125 volatile unsigned long acsltdis;
126 volatile unsigned long acfifosts;
127 volatile unsigned long unused2[11];
128 volatile unsigned long acdmasts;
129 volatile unsigned long acdmasel;
130 volatile unsigned long unused3[6];
131 volatile unsigned long acaudodat;
132 volatile unsigned long acsurrdat;
133 volatile unsigned long accentdat;
134 volatile unsigned long aclfedat;
135 volatile unsigned long acaudiat;
136 volatile unsigned long unused4;
137 volatile unsigned long acmodoat;
138 volatile unsigned long acmodidat;
139 volatile unsigned long unused5[15];
140 volatile unsigned long acrevid;
141};
142
143
144struct tx4938_tmr_reg {
145 volatile unsigned long tcr;
146 volatile unsigned long tisr;
147 volatile unsigned long cpra;
148 volatile unsigned long cprb;
149 volatile unsigned long itmr;
150 volatile unsigned long unused0[3];
151 volatile unsigned long ccdr;
152 volatile unsigned long unused1[3];
153 volatile unsigned long pgmr;
154 volatile unsigned long unused2[3];
155 volatile unsigned long wtmr;
156 volatile unsigned long unused3[43];
157 volatile unsigned long trr;
158};
159
160struct tx4938_sio_reg {
161 volatile unsigned long lcr;
162 volatile unsigned long dicr;
163 volatile unsigned long disr;
164 volatile unsigned long cisr;
165 volatile unsigned long fcr;
166 volatile unsigned long flcr;
167 volatile unsigned long bgr;
168 volatile unsigned long tfifo;
169 volatile unsigned long rfifo;
170};
171
172struct tx4938_ndfmc_reg {
173 endian_def_l2(unused0, dtr);
174 endian_def_l2(unused1, mcr);
175 endian_def_l2(unused2, sr);
176 endian_def_l2(unused3, isr);
177 endian_def_l2(unused4, imr);
178 endian_def_l2(unused5, spr);
179 endian_def_l2(unused6, rstr);
180};
181
182struct tx4938_spi_reg {
183 volatile unsigned long mcr;
184 volatile unsigned long cr0;
185 volatile unsigned long cr1;
186 volatile unsigned long fs;
187 volatile unsigned long unused1;
188 volatile unsigned long sr;
189 volatile unsigned long dr;
190 volatile unsigned long unused2;
191};
192
193struct tx4938_sramc_reg { 43struct tx4938_sramc_reg {
194 volatile unsigned long long cr; 44 u64 cr;
195}; 45};
196 46
197struct tx4938_ccfg_reg { 47struct tx4938_ccfg_reg {
@@ -209,34 +59,6 @@ struct tx4938_ccfg_reg {
209 u64 jmpadr; 59 u64 jmpadr;
210}; 60};
211 61
212#undef endian_def_l2
213#undef endian_def_s2
214#undef endian_def_sb2
215#undef endian_def_b2s
216#undef endian_def_b4
217
218/*
219 * NDFMC
220 */
221
222/* NDFMCR : NDFMC Mode Control */
223#define TX4938_NDFMCR_WE 0x80
224#define TX4938_NDFMCR_ECC_ALL 0x60
225#define TX4938_NDFMCR_ECC_RESET 0x60
226#define TX4938_NDFMCR_ECC_READ 0x40
227#define TX4938_NDFMCR_ECC_ON 0x20
228#define TX4938_NDFMCR_ECC_OFF 0x00
229#define TX4938_NDFMCR_CE 0x10
230#define TX4938_NDFMCR_BSPRT 0x04
231#define TX4938_NDFMCR_ALE 0x02
232#define TX4938_NDFMCR_CLE 0x01
233
234/* NDFMCR : NDFMC Status */
235#define TX4938_NDFSR_BUSY 0x80
236
237/* NDFMCR : NDFMC Reset */
238#define TX4938_NDFRSTR_RST 0x01
239
240/* 62/*
241 * IRC 63 * IRC
242 */ 64 */
@@ -268,13 +90,15 @@ struct tx4938_ccfg_reg {
268 90
269#define TX4938_IRC_INT 2 /* IP[2] in Status register */ 91#define TX4938_IRC_INT 2 /* IP[2] in Status register */
270 92
93#define TX4938_NUM_PIO 16
94
271/* 95/*
272 * CCFG 96 * CCFG
273 */ 97 */
274/* CCFG : Chip Configuration */ 98/* CCFG : Chip Configuration */
275#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) 99#define TX4938_CCFG_WDRST 0x0000020000000000ULL
276#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) 100#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
277#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) 101#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
278#define TX4938_CCFG_TINTDIS 0x01000000 102#define TX4938_CCFG_TINTDIS 0x01000000
279#define TX4938_CCFG_PCI66 0x00800000 103#define TX4938_CCFG_PCI66 0x00800000
280#define TX4938_CCFG_PCIMODE 0x00400000 104#define TX4938_CCFG_PCIMODE 0x00400000
@@ -310,12 +134,12 @@ struct tx4938_ccfg_reg {
310#define TX4938_CCFG_ACEHOLD 0x00000001 134#define TX4938_CCFG_ACEHOLD 0x00000001
311 135
312/* PCFG : Pin Configuration */ 136/* PCFG : Pin Configuration */
313#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) 137#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
314#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) 138#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
315#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) 139#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
316#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) 140#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
317#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) 141#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
318#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) 142#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
319#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 143#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
320#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) 144#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
321#define TX4938_PCFG_SYSCLKEN 0x08000000 145#define TX4938_PCFG_SYSCLKEN 0x08000000
@@ -336,8 +160,8 @@ struct tx4938_ccfg_reg {
336#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 160#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
337 161
338/* CLKCTR : Clock Control */ 162/* CLKCTR : Clock Control */
339#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) 163#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
340#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) 164#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
341#define TX4938_CLKCTR_ETH1CKD 0x80000000 165#define TX4938_CLKCTR_ETH1CKD 0x80000000
342#define TX4938_CLKCTR_ETH0CKD 0x40000000 166#define TX4938_CLKCTR_ETH0CKD 0x40000000
343#define TX4938_CLKCTR_SPICKD 0x20000000 167#define TX4938_CLKCTR_SPICKD 0x20000000
@@ -424,20 +248,16 @@ struct tx4938_ccfg_reg {
424#define TX4938_DMA_CSR_DESERR 0x00000002 248#define TX4938_DMA_CSR_DESERR 0x00000002
425#define TX4938_DMA_CSR_SORERR 0x00000001 249#define TX4938_DMA_CSR_SORERR 0x00000001
426 250
427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 251#define tx4938_sdramcptr tx4927_sdramcptr
428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 252#define tx4938_ebuscptr tx4927_ebuscptr
429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
431#define tx4938_pcicptr tx4927_pcicptr 253#define tx4938_pcicptr tx4927_pcicptr
432#define tx4938_pcic1ptr \ 254#define tx4938_pcic1ptr \
433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) 255 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \ 256#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) 257 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 258#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 259#define tx4938_sramcptr \
439#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) 260 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
441 261
442 262
443#define TX4938_REV_PCODE() \ 263#define TX4938_REV_PCODE() \
@@ -447,14 +267,19 @@ struct tx4938_ccfg_reg {
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) 267#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) 268#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
449 269
450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 270#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 271#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
272#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
452 273
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) 274#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 275#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
455#define TX4938_EBUSC_SIZE(ch) \ 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
457 277
278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void);
280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void);
458int tx4938_report_pciclk(void); 283int tx4938_report_pciclk(void);
459void tx4938_report_pci1clk(void); 284void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void); 285int tx4938_pciclk66_setup(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:49:03 -0500