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-rw-r--r--include/asm-mips/txx9/generic.h41
-rw-r--r--include/asm-mips/txx9/jmr3927.h182
-rw-r--r--include/asm-mips/txx9/pci.h36
-rw-r--r--include/asm-mips/txx9/rbtx4927.h79
-rw-r--r--include/asm-mips/txx9/rbtx4938.h149
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h67
-rw-r--r--include/asm-mips/txx9/spi.h19
-rw-r--r--include/asm-mips/txx9/tx3927.h323
-rw-r--r--include/asm-mips/txx9/tx4927.h219
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h199
-rw-r--r--include/asm-mips/txx9/tx4938.h465
-rw-r--r--include/asm-mips/txx9/txx927.h121
12 files changed, 1900 insertions, 0 deletions
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
new file mode 100644
index 000000000000..d8756660523d
--- /dev/null
+++ b/include/asm-mips/txx9/generic.h
@@ -0,0 +1,41 @@
1/*
2 * linux/include/asm-mips/txx9/generic.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8#ifndef __ASM_TXX9_GENERIC_H
9#define __ASM_TXX9_GENERIC_H
10
11#include <linux/init.h>
12#include <linux/ioport.h> /* for struct resource */
13
14extern struct resource txx9_ce_res[];
15extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size);
18
19extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock;
22
23struct pci_dev;
24struct txx9_board_vec {
25 const char *system;
26 void (*prom_init)(void);
27 void (*mem_setup)(void);
28 void (*irq_setup)(void);
29 void (*time_init)(void);
30 void (*arch_init)(void);
31 void (*device_init)(void);
32#ifdef CONFIG_PCI
33 int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
34#endif
35};
36extern struct txx9_board_vec *txx9_board_vec;
37extern int (*txx9_irq_dispatch)(int pending);
38void prom_init_cmdline(void);
39char *prom_getcmdline(void);
40
41#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
new file mode 100644
index 000000000000..d6eb1b6a54eb
--- /dev/null
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -0,0 +1,182 @@
1/*
2 * Defines for the TJSYS JMR-TX3927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_JMR3927_H
11#define __ASM_TXX9_JMR3927_H
12
13#include <asm/txx9/tx3927.h>
14#include <asm/addrspace.h>
15#include <asm/system.h>
16#include <asm/txx9irq.h>
17
18/* CS */
19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
20#define JMR3927_ROMCE1 0x1e000000 /* 4M */
21#define JMR3927_ROMCE2 0x14000000 /* 16M */
22#define JMR3927_ROMCE3 0x10000000 /* 64M */
23#define JMR3927_ROMCE5 0x1d000000 /* 4M */
24#define JMR3927_SDCS0 0x00000000 /* 32M */
25#define JMR3927_SDCS1 0x02000000 /* 32M */
26/* PCI Direct Mappings */
27
28#define JMR3927_PCIMEM 0x08000000
29#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
30#define JMR3927_PCIIO 0x15000000
31#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
32
33#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
34#define JMR3927_PORT_BASE KSEG1
35
36/* Address map (virtual address) */
37#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
38#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
39#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
40#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
41#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
42
43#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
44#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
45#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
46#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
47#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
48#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
49#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
50#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
51#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
52#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
53#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
54
55/* Flash ROM */
56#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
57#define JMR3927_FLASH_SIZE 0x00400000
58
59/* bits for IOC_REV/IOC_BREV (high byte) */
60#define JMR3927_IDT_MASK 0xfc
61#define JMR3927_REV_MASK 0x03
62#define JMR3927_IOC_IDT 0xe0
63
64/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
65#define JMR3927_IOC_INTB_PCIA 0
66#define JMR3927_IOC_INTB_PCIB 1
67#define JMR3927_IOC_INTB_PCIC 2
68#define JMR3927_IOC_INTB_PCID 3
69#define JMR3927_IOC_INTB_MODEM 4
70#define JMR3927_IOC_INTB_INT6 5
71#define JMR3927_IOC_INTB_INT7 6
72#define JMR3927_IOC_INTB_SOFT 7
73#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
74#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
75#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
76#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
77#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
78#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
79#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
80#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
81
82/* bits for IOC_RESET (high byte) */
83#define JMR3927_IOC_RESET_CPU 1
84#define JMR3927_IOC_RESET_PCI 2
85
86#if defined(__BIG_ENDIAN)
87#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
88#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
89#elif defined(__LITTLE_ENDIAN)
90#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
91#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
92#else
93#error "No Endian"
94#endif
95
96/* LED macro */
97#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
98
99#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
100
101/* DIPSW4 macro */
102#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
103#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
104#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
105#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
106
107/*
108 * IRQ mappings
109 */
110
111/* These are the virtual IRQ numbers, we divide all IRQ's into
112 * 'spaces', the 'space' determines where and how to enable/disable
113 * that particular IRQ on an JMR machine. Add new 'spaces' as new
114 * IRQ hardware is supported.
115 */
116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
118
119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
122
123#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
124#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
125#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
126#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
127#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
128#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
129#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
130#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
131#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
139#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
140#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
141#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
142#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
143#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
144
145/* IOC (PCI, MODEM) */
146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
149
150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
154
155/*
156 * TX3927 Pin Configuration:
157 *
158 * PCFG bits Avail Dead
159 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
160 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
161 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
162 * GDBGE* PIO[2:1]
163 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
164 * SELTMR[2:0]:000 TIMER[1:0]
165 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
166 * DMAREQ[1],DMAACK[1]
167 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
168 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
169 * SELDONE:1 DMADONE PIO[7]
170 *
171 * Usable pins are:
172 * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
173 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
174 * INT[3:0]
175 */
176
177void jmr3927_prom_init(void);
178void jmr3927_irq_setup(void);
179struct pci_dev;
180int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
181
182#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
new file mode 100644
index 000000000000..d89a45091e24
--- /dev/null
+++ b/include/asm-mips/txx9/pci.h
@@ -0,0 +1,36 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef __ASM_TXX9_PCI_H
7#define __ASM_TXX9_PCI_H
8
9#include <linux/pci.h>
10
11extern struct pci_controller txx9_primary_pcic;
12struct pci_controller *
13txx9_alloc_pci_controller(struct pci_controller *pcic,
14 unsigned long mem_base, unsigned long mem_size,
15 unsigned long io_base, unsigned long io_size);
16
17int txx9_pci66_check(struct pci_controller *hose, int top_bus,
18 int current_bus);
19extern int txx9_pci_mem_high __initdata;
20
21extern int txx9_pci_option;
22#define TXX9_PCI_OPT_PICMG 0x0002
23#define TXX9_PCI_OPT_CLK_33 0x0008
24#define TXX9_PCI_OPT_CLK_66 0x0010
25#define TXX9_PCI_OPT_CLK_MASK \
26 (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
27#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
28
29enum txx9_pci_err_action {
30 TXX9_PCI_ERR_REPORT,
31 TXX9_PCI_ERR_IGNORE,
32 TXX9_PCI_ERR_PANIC,
33};
34extern enum txx9_pci_err_action txx9_pci_err_action;
35
36#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
new file mode 100644
index 000000000000..bf194589216f
--- /dev/null
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -0,0 +1,79 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_RBTX4927_H
28#define __ASM_TXX9_RBTX4927_H
29
30#include <asm/txx9/tx4927.h>
31
32#define RBTX4927_PCIMEM 0x08000000
33#define RBTX4927_PCIMEM_SIZE 0x08000000
34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000
36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL)
38
39/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0
41#define RBTX4927_INTB_PCIC 1
42#define RBTX4927_INTB_PCIB 2
43#define RBTX4927_INTB_PCIA 3
44#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
45#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
46#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
47#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
48
49#define RBTX4927_NR_IRQ_IOC 8 /* IOC */
50
51#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR)
52#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
53#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
54#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
55#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
56
57#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1))
58
59#ifdef CONFIG_PCI
60#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
61#else
62#define RBTX4927_ISA_IO_OFFSET 0
63#endif
64
65#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
66#define RBTX4927_SW_RESET_DO_SET 0x01
67
68#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
69#define RBTX4927_SW_RESET_ENABLE_SET 0x01
70
71#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
72#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
73
74void rbtx4927_prom_init(void);
75void rbtx4927_irq_setup(void);
76struct pci_dev;
77int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
78
79#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
new file mode 100644
index 000000000000..2f5d5e705a41
--- /dev/null
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -0,0 +1,149 @@
1/*
2 * Definitions for TX4937/TX4938
3 *
4 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
5 * terms of the GNU General Public License version 2. This program is
6 * licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 *
9 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
10 */
11#ifndef __ASM_TXX9_RBTX4938_H
12#define __ASM_TXX9_RBTX4938_H
13
14#include <asm/addrspace.h>
15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h>
17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
47
48/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
50
51/* bits for ISTAT/IMASK/IMSTAT */
52#define RBTX4938_INTB_PCID 0
53#define RBTX4938_INTB_PCIC 1
54#define RBTX4938_INTB_PCIB 2
55#define RBTX4938_INTB_PCIA 3
56#define RBTX4938_INTB_RTC 4
57#define RBTX4938_INTB_ATA 5
58#define RBTX4938_INTB_MODEM 6
59#define RBTX4938_INTB_SWINT 7
60#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
61#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
62#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
63#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
64#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
65#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
66#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
67#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
68
69#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
70#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
71#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
72#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
73#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
74#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
75#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
76#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
77#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
78#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
79#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
80#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
81#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
82#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
83#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
84#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
85#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
86#define rbtx4938_softresetlock_addr \
87 ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
88#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
89
90/*
91 * IRQ mappings
92 */
93
94#define RBTX4938_SOFT_INT0 0 /* not used */
95#define RBTX4938_SOFT_INT1 1 /* not used */
96#define RBTX4938_IRC_INT 2
97#define RBTX4938_TIMER_INT 7
98
99/* These are the virtual IRQ numbers, we divide all IRQ's into
100 * 'spaces', the 'space' determines where and how to enable/disable
101 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
102 * IRQ hardware is supported.
103 */
104#define RBTX4938_NR_IRQ_IOC 8
105
106#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
107#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
108#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
109
110#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
111#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
112#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
113#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
114#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
115#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
116#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
117#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
118#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
119#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
120#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
121#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
122#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
123#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
124#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
125#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
126#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
127#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
128#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
129#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
130#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
131#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
132#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
133#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
134
135
136/* IOC (PCI, etc) */
137#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
138/* Onboard 10M Ether */
139#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
140
141#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
142#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
143
144void rbtx4938_prom_init(void);
145void rbtx4938_irq_setup(void);
146struct pci_dev;
147int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
148
149#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
new file mode 100644
index 000000000000..9375e4fc2289
--- /dev/null
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -0,0 +1,67 @@
1/*
2 * Interface for smsc fdc48m81x Super IO chip
3 *
4 * Author: MontaVista Software, Inc. source@mvista.com
5 *
6 * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright (C) 2004 MontaVista Software Inc.
12 * Manish Lachwani, mlachwani@mvista.com
13 */
14
15#ifndef _SMSC_FDC37M81X_H_
16#define _SMSC_FDC37M81X_H_
17
18/* Common Registers */
19#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
20#define SMSC_FDC37M81X_CONFIG_DATA 0x01
21#define SMSC_FDC37M81X_CONF 0x02
22#define SMSC_FDC37M81X_INDEX 0x03
23#define SMSC_FDC37M81X_DNUM 0x07
24#define SMSC_FDC37M81X_DID 0x20
25#define SMSC_FDC37M81X_DREV 0x21
26#define SMSC_FDC37M81X_PCNT 0x22
27#define SMSC_FDC37M81X_PMGT 0x23
28#define SMSC_FDC37M81X_OSC 0x24
29#define SMSC_FDC37M81X_CONFPA0 0x26
30#define SMSC_FDC37M81X_CONFPA1 0x27
31#define SMSC_FDC37M81X_TEST4 0x2B
32#define SMSC_FDC37M81X_TEST5 0x2C
33#define SMSC_FDC37M81X_TEST1 0x2D
34#define SMSC_FDC37M81X_TEST2 0x2E
35#define SMSC_FDC37M81X_TEST3 0x2F
36
37/* Logical device numbers */
38#define SMSC_FDC37M81X_FDD 0x00
39#define SMSC_FDC37M81X_PARALLEL 0x03
40#define SMSC_FDC37M81X_SERIAL1 0x04
41#define SMSC_FDC37M81X_SERIAL2 0x05
42#define SMSC_FDC37M81X_KBD 0x07
43#define SMSC_FDC37M81X_AUXIO 0x08
44#define SMSC_FDC37M81X_NONE 0xff
45
46/* Logical device Config Registers */
47#define SMSC_FDC37M81X_ACTIVE 0x30
48#define SMSC_FDC37M81X_BASEADDR0 0x60
49#define SMSC_FDC37M81X_BASEADDR1 0x61
50#define SMSC_FDC37M81X_INT 0x70
51#define SMSC_FDC37M81X_INT2 0x72
52#define SMSC_FDC37M81X_LDCR_F0 0xF0
53
54/* Chip Config Values */
55#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
57#define SMSC_FDC37M81X_CHIP_ID 0x4d
58
59unsigned long __init smsc_fdc37m81x_init(unsigned long port);
60
61void smsc_fdc37m81x_config_beg(void);
62
63void smsc_fdc37m81x_config_end(void);
64
65void smsc_fdc37m81x_config_set(u8 reg, u8 val);
66
67#endif
diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h
new file mode 100644
index 000000000000..ddfb2a0dc432
--- /dev/null
+++ b/include/asm-mips/txx9/spi.h
@@ -0,0 +1,19 @@
1/*
2 * Definitions for TX4937/TX4938 SPI
3 *
4 * Copyright (C) 2000-2001 Toshiba Corporation
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13#ifndef __ASM_TXX9_SPI_H
14#define __ASM_TXX9_SPI_H
15
16extern int spi_eeprom_register(int chipid);
17extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
18
19#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
new file mode 100644
index 000000000000..ca414c7624e1
--- /dev/null
+++ b/include/asm-mips/txx9/tx3927.h
@@ -0,0 +1,323 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Toshiba Corporation
7 */
8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H
10
11#include <asm/txx9/txx927.h>
12
13#define TX3927_SDRAMC_REG 0xfffe8000
14#define TX3927_ROMC_REG 0xfffe9000
15#define TX3927_DMA_REG 0xfffeb000
16#define TX3927_IRC_REG 0xfffec000
17#define TX3927_PCIC_REG 0xfffed000
18#define TX3927_CCFG_REG 0xfffee000
19#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500
24
25struct tx3927_sdramc_reg {
26 volatile unsigned long cr[8];
27 volatile unsigned long tr[3];
28 volatile unsigned long cmd;
29 volatile unsigned long smrs[2];
30};
31
32struct tx3927_romc_reg {
33 volatile unsigned long cr[8];
34};
35
36struct tx3927_dma_reg {
37 struct tx3927_dma_ch_reg {
38 volatile unsigned long cha;
39 volatile unsigned long sar;
40 volatile unsigned long dar;
41 volatile unsigned long cntr;
42 volatile unsigned long sair;
43 volatile unsigned long dair;
44 volatile unsigned long ccr;
45 volatile unsigned long csr;
46 } ch[4];
47 volatile unsigned long dbr[8];
48 volatile unsigned long tdhr;
49 volatile unsigned long mcr;
50 volatile unsigned long unused0;
51};
52
53#include <asm/byteorder.h>
54
55#ifdef __BIG_ENDIAN
56#define endian_def_s2(e1, e2) \
57 volatile unsigned short e1, e2
58#define endian_def_sb2(e1, e2, e3) \
59 volatile unsigned short e1;volatile unsigned char e2, e3
60#define endian_def_b2s(e1, e2, e3) \
61 volatile unsigned char e1, e2;volatile unsigned short e3
62#define endian_def_b4(e1, e2, e3, e4) \
63 volatile unsigned char e1, e2, e3, e4
64#else
65#define endian_def_s2(e1, e2) \
66 volatile unsigned short e2, e1
67#define endian_def_sb2(e1, e2, e3) \
68 volatile unsigned char e3, e2;volatile unsigned short e1
69#define endian_def_b2s(e1, e2, e3) \
70 volatile unsigned short e3;volatile unsigned char e2, e1
71#define endian_def_b4(e1, e2, e3, e4) \
72 volatile unsigned char e4, e3, e2, e1
73#endif
74
75struct tx3927_pcic_reg {
76 endian_def_s2(did, vid);
77 endian_def_s2(pcistat, pcicmd);
78 endian_def_b4(cc, scc, rpli, rid);
79 endian_def_b4(unused0, ht, mlt, cls);
80 volatile unsigned long ioba; /* +10 */
81 volatile unsigned long mba;
82 volatile unsigned long unused1[5];
83 endian_def_s2(svid, ssvid);
84 volatile unsigned long unused2; /* +30 */
85 endian_def_sb2(unused3, unused4, capptr);
86 volatile unsigned long unused5;
87 endian_def_b4(ml, mg, ip, il);
88 volatile unsigned long unused6; /* +40 */
89 volatile unsigned long istat;
90 volatile unsigned long iim;
91 volatile unsigned long rrt;
92 volatile unsigned long unused7[3]; /* +50 */
93 volatile unsigned long ipbmma;
94 volatile unsigned long ipbioma; /* +60 */
95 volatile unsigned long ilbmma;
96 volatile unsigned long ilbioma;
97 volatile unsigned long unused8[9];
98 volatile unsigned long tc; /* +90 */
99 volatile unsigned long tstat;
100 volatile unsigned long tim;
101 volatile unsigned long tccmd;
102 volatile unsigned long pcirrt; /* +a0 */
103 volatile unsigned long pcirrt_cmd;
104 volatile unsigned long pcirrdt;
105 volatile unsigned long unused9[3];
106 volatile unsigned long tlboap;
107 volatile unsigned long tlbiap;
108 volatile unsigned long tlbmma; /* +c0 */
109 volatile unsigned long tlbioma;
110 volatile unsigned long sc_msg;
111 volatile unsigned long sc_be;
112 volatile unsigned long tbl; /* +d0 */
113 volatile unsigned long unused10[3];
114 volatile unsigned long pwmng; /* +e0 */
115 volatile unsigned long pwmngs;
116 volatile unsigned long unused11[6];
117 volatile unsigned long req_trace; /* +100 */
118 volatile unsigned long pbapmc;
119 volatile unsigned long pbapms;
120 volatile unsigned long pbapmim;
121 volatile unsigned long bm; /* +110 */
122 volatile unsigned long cpcibrs;
123 volatile unsigned long cpcibgs;
124 volatile unsigned long pbacs;
125 volatile unsigned long iobas; /* +120 */
126 volatile unsigned long mbas;
127 volatile unsigned long lbc;
128 volatile unsigned long lbstat;
129 volatile unsigned long lbim; /* +130 */
130 volatile unsigned long pcistatim;
131 volatile unsigned long ica;
132 volatile unsigned long icd;
133 volatile unsigned long iiadp; /* +140 */
134 volatile unsigned long iscdp;
135 volatile unsigned long mmas;
136 volatile unsigned long iomas;
137 volatile unsigned long ipciaddr; /* +150 */
138 volatile unsigned long ipcidata;
139 volatile unsigned long ipcibe;
140};
141
142struct tx3927_ccfg_reg {
143 volatile unsigned long ccfg;
144 volatile unsigned long crir;
145 volatile unsigned long pcfg;
146 volatile unsigned long tear;
147 volatile unsigned long pdcr;
148};
149
150/*
151 * SDRAMC
152 */
153
154/*
155 * ROMC
156 */
157
158/*
159 * DMA
160 */
161/* bits for MCR */
162#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
163#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
164#define TX3927_DMA_MCR_RSFIF 0x00000080
165#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
166#define TX3927_DMA_MCR_LE 0x00000004
167#define TX3927_DMA_MCR_RPRT 0x00000002
168#define TX3927_DMA_MCR_MSTEN 0x00000001
169
170/* bits for CCRn */
171#define TX3927_DMA_CCR_DBINH 0x04000000
172#define TX3927_DMA_CCR_SBINH 0x02000000
173#define TX3927_DMA_CCR_CHRST 0x01000000
174#define TX3927_DMA_CCR_RVBYTE 0x00800000
175#define TX3927_DMA_CCR_ACKPOL 0x00400000
176#define TX3927_DMA_CCR_REQPL 0x00200000
177#define TX3927_DMA_CCR_EGREQ 0x00100000
178#define TX3927_DMA_CCR_CHDN 0x00080000
179#define TX3927_DMA_CCR_DNCTL 0x00060000
180#define TX3927_DMA_CCR_EXTRQ 0x00010000
181#define TX3927_DMA_CCR_INTRQD 0x0000e000
182#define TX3927_DMA_CCR_INTENE 0x00001000
183#define TX3927_DMA_CCR_INTENC 0x00000800
184#define TX3927_DMA_CCR_INTENT 0x00000400
185#define TX3927_DMA_CCR_CHNEN 0x00000200
186#define TX3927_DMA_CCR_XFACT 0x00000100
187#define TX3927_DMA_CCR_SNOP 0x00000080
188#define TX3927_DMA_CCR_DSTINC 0x00000040
189#define TX3927_DMA_CCR_SRCINC 0x00000020
190#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
191#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
192#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
193#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
194#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
195#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
196#define TX3927_DMA_CCR_MEMIO 0x00000002
197#define TX3927_DMA_CCR_ONEAD 0x00000001
198
199/* bits for CSRn */
200#define TX3927_DMA_CSR_CHNACT 0x00000100
201#define TX3927_DMA_CSR_ABCHC 0x00000080
202#define TX3927_DMA_CSR_NCHNC 0x00000040
203#define TX3927_DMA_CSR_NTRNFC 0x00000020
204#define TX3927_DMA_CSR_EXTDN 0x00000010
205#define TX3927_DMA_CSR_CFERR 0x00000008
206#define TX3927_DMA_CSR_CHERR 0x00000004
207#define TX3927_DMA_CSR_DESERR 0x00000002
208#define TX3927_DMA_CSR_SORERR 0x00000001
209
210/*
211 * IRC
212 */
213#define TX3927_IR_INT0 0
214#define TX3927_IR_INT1 1
215#define TX3927_IR_INT2 2
216#define TX3927_IR_INT3 3
217#define TX3927_IR_INT4 4
218#define TX3927_IR_INT5 5
219#define TX3927_IR_SIO0 6
220#define TX3927_IR_SIO1 7
221#define TX3927_IR_SIO(ch) (6 + (ch))
222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_NUM_IR 16
227
228/*
229 * PCIC
230 */
231/* bits for PCICMD */
232/* see PCI_COMMAND_XXX in linux/pci.h */
233
234/* bits for PCISTAT */
235/* see PCI_STATUS_XXX in linux/pci.h */
236#define PCI_STATUS_NEW_CAP 0x0010
237
238/* bits for TC */
239#define TX3927_PCIC_TC_OF16E 0x00000020
240#define TX3927_PCIC_TC_IF8E 0x00000010
241#define TX3927_PCIC_TC_OF8E 0x00000008
242
243/* bits for IOBA/MBA */
244/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
245
246/* bits for PBAPMC */
247#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
248#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
249#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
250
251/* bits for LBSTAT/LBIM */
252#define TX3927_PCIC_LBIM_ALL 0x0000003e
253
254/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
255#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
256
257/* bits for LBC */
258#define TX3927_PCIC_LBC_IBSE 0x00004000
259#define TX3927_PCIC_LBC_TIBSE 0x00002000
260#define TX3927_PCIC_LBC_TMFBSE 0x00001000
261#define TX3927_PCIC_LBC_HRST 0x00000800
262#define TX3927_PCIC_LBC_SRST 0x00000400
263#define TX3927_PCIC_LBC_EPCAD 0x00000200
264#define TX3927_PCIC_LBC_MSDSE 0x00000100
265#define TX3927_PCIC_LBC_CRR 0x00000080
266#define TX3927_PCIC_LBC_ILMDE 0x00000040
267#define TX3927_PCIC_LBC_ILIDE 0x00000020
268
269#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
270#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
271
272/*
273 * CCFG
274 */
275/* CCFG : Chip Configuration */
276#define TX3927_CCFG_TLBOFF 0x00020000
277#define TX3927_CCFG_BEOW 0x00010000
278#define TX3927_CCFG_WR 0x00008000
279#define TX3927_CCFG_TOE 0x00004000
280#define TX3927_CCFG_PCIXARB 0x00002000
281#define TX3927_CCFG_PCI3 0x00001000
282#define TX3927_CCFG_PSNP 0x00000800
283#define TX3927_CCFG_PPRI 0x00000400
284#define TX3927_CCFG_PLLM 0x00000030
285#define TX3927_CCFG_ENDIAN 0x00000004
286#define TX3927_CCFG_HALT 0x00000002
287#define TX3927_CCFG_ACEHOLD 0x00000001
288
289/* PCFG : Pin Configuration */
290#define TX3927_PCFG_SYSCLKEN 0x08000000
291#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
292#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
293#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
294#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
295#define TX3927_PCFG_SELALL 0x0003ffff
296#define TX3927_PCFG_SELCS 0x00020000
297#define TX3927_PCFG_SELDSF 0x00010000
298#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
299#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
300#define TX3927_PCFG_SELSIO_ALL 0x00003000
301#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
302#define TX3927_PCFG_SELTMR_ALL 0x00000e00
303#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
304#define TX3927_PCFG_SELDONE 0x00000100
305#define TX3927_PCFG_INTDMA_ALL 0x000000f0
306#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
307#define TX3927_PCFG_SELDMA_ALL 0x0000000f
308#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
309
310#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
311#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
312#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
313#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
314#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
315#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
318
319struct pci_controller;
320void __init tx3927_pcic_setup(struct pci_controller *channel,
321 unsigned long sdram_size, int extarb);
322
323#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
new file mode 100644
index 000000000000..46d60afc038b
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927.h
@@ -0,0 +1,219 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_TX4927_H
28#define __ASM_TXX9_TX4927_H
29
30#include <linux/types.h>
31#include <linux/io.h>
32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h>
34
35#define TX4927_SDRAMC_REG 0xff1f8000
36#define TX4927_EBUSC_REG 0xff1f9000
37#define TX4927_PCIC_REG 0xff1fd000
38#define TX4927_CCFG_REG 0xff1fe000
39#define TX4927_IRC_REG 0xff1ff600
40#define TX4927_NR_TMR 3
41#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
42
43#define TX4927_IR_INT(n) (2 + (n))
44#define TX4927_IR_SIO(n) (8 + (n))
45#define TX4927_IR_PCIC 16
46#define TX4927_IR_PCIERR 22
47#define TX4927_NUM_IR 32
48
49#define TX4927_IRC_INT 2 /* IP[2] in Status register */
50
51struct tx4927_sdramc_reg {
52 volatile unsigned long long cr[4];
53 volatile unsigned long long unused0[4];
54 volatile unsigned long long tr;
55 volatile unsigned long long unused1[2];
56 volatile unsigned long long cmd;
57};
58
59struct tx4927_ebusc_reg {
60 volatile unsigned long long cr[8];
61};
62
63struct tx4927_ccfg_reg {
64 u64 ccfg;
65 u64 crir;
66 u64 pcfg;
67 u64 toea;
68 u64 clkctr;
69 u64 unused0;
70 u64 garbc;
71 u64 unused1;
72 u64 unused2;
73 u64 ramp;
74};
75
76/*
77 * CCFG
78 */
79/* CCFG : Chip Configuration */
80#define TX4927_CCFG_WDRST 0x0000020000000000ULL
81#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
82#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
83#define TX4927_CCFG_TINTDIS 0x01000000
84#define TX4927_CCFG_PCI66 0x00800000
85#define TX4927_CCFG_PCIMODE 0x00400000
86#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
87#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
88#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
89#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
90#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
91#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
92#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
93#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
94#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
95#define TX4927_CCFG_BEOW 0x00010000
96#define TX4927_CCFG_WR 0x00008000
97#define TX4927_CCFG_TOE 0x00004000
98#define TX4927_CCFG_PCIARB 0x00002000
99#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
100#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
101#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
102#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
103#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
104#define TX4927_CCFG_SYSSP_MASK 0x000000c0
105#define TX4927_CCFG_ENDIAN 0x00000004
106#define TX4927_CCFG_HALT 0x00000002
107#define TX4927_CCFG_ACEHOLD 0x00000001
108#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
109
110/* PCFG : Pin Configuration */
111#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
112#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
113#define TX4927_PCFG_SYSCLKEN 0x08000000
114#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
115#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
116#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
117#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
118#define TX4927_PCFG_SEL2 0x00000200
119#define TX4927_PCFG_SEL1 0x00000100
120#define TX4927_PCFG_DMASEL_ALL 0x000000ff
121#define TX4927_PCFG_DMASEL0_MASK 0x00000003
122#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
123#define TX4927_PCFG_DMASEL2_MASK 0x00000030
124#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
125#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
126#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
127#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
128#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
129#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
130#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
131#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
132#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
133#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
134#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
135#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
136#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
137#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
138#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
139#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
140#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
141#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
142
143/* CLKCTR : Clock Control */
144#define TX4927_CLKCTR_ACLCKD 0x02000000
145#define TX4927_CLKCTR_PIOCKD 0x01000000
146#define TX4927_CLKCTR_DMACKD 0x00800000
147#define TX4927_CLKCTR_PCICKD 0x00400000
148#define TX4927_CLKCTR_TM0CKD 0x00100000
149#define TX4927_CLKCTR_TM1CKD 0x00080000
150#define TX4927_CLKCTR_TM2CKD 0x00040000
151#define TX4927_CLKCTR_SIO0CKD 0x00020000
152#define TX4927_CLKCTR_SIO1CKD 0x00010000
153#define TX4927_CLKCTR_ACLRST 0x00000200
154#define TX4927_CLKCTR_PIORST 0x00000100
155#define TX4927_CLKCTR_DMARST 0x00000080
156#define TX4927_CLKCTR_PCIRST 0x00000040
157#define TX4927_CLKCTR_TM0RST 0x00000010
158#define TX4927_CLKCTR_TM1RST 0x00000008
159#define TX4927_CLKCTR_TM2RST 0x00000004
160#define TX4927_CLKCTR_SIO0RST 0x00000002
161#define TX4927_CLKCTR_SIO1RST 0x00000001
162
163#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
164#define tx4927_pcicptr \
165 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
166#define tx4927_ccfgptr \
167 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
168#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
169
170/* utilities */
171static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
172{
173#ifdef CONFIG_32BIT
174 unsigned long flags;
175 local_irq_save(flags);
176#endif
177 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
178#ifdef CONFIG_32BIT
179 local_irq_restore(flags);
180#endif
181}
182static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
183{
184#ifdef CONFIG_32BIT
185 unsigned long flags;
186 local_irq_save(flags);
187#endif
188 ____raw_writeq(____raw_readq(adr) | bits, adr);
189#ifdef CONFIG_32BIT
190 local_irq_restore(flags);
191#endif
192}
193
194/* These functions are not interrupt safe. */
195static inline void tx4927_ccfg_clear(__u64 bits)
196{
197 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
198 & ~(TX4927_CCFG_W1CBITS | bits),
199 &tx4927_ccfgptr->ccfg);
200}
201static inline void tx4927_ccfg_set(__u64 bits)
202{
203 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
204 & ~TX4927_CCFG_W1CBITS) | bits,
205 &tx4927_ccfgptr->ccfg);
206}
207static inline void tx4927_ccfg_change(__u64 change, __u64 new)
208{
209 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
210 & ~(TX4927_CCFG_W1CBITS | change)) |
211 new,
212 &tx4927_ccfgptr->ccfg);
213}
214
215int tx4927_report_pciclk(void);
216int tx4927_pciclk66_setup(void);
217void tx4927_irq_init(void);
218
219#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..d61c3d09c4a2
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -0,0 +1,199 @@
1/*
2 * include/asm-mips/txx9/tx4927pcic.h
3 * TX4927 PCI controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9_TX4927PCIC_H
10#define __ASM_TXX9_TX4927PCIC_H
11
12#include <linux/pci.h>
13
14struct tx4927_pcic_reg {
15 u32 pciid;
16 u32 pcistatus;
17 u32 pciccrev;
18 u32 pcicfg1;
19 u32 p2gm0plbase; /* +10 */
20 u32 p2gm0pubase;
21 u32 p2gm1plbase;
22 u32 p2gm1pubase;
23 u32 p2gm2pbase; /* +20 */
24 u32 p2giopbase;
25 u32 unused0;
26 u32 pcisid;
27 u32 unused1; /* +30 */
28 u32 pcicapptr;
29 u32 unused2;
30 u32 pcicfg2;
31 u32 g2ptocnt; /* +40 */
32 u32 unused3[15];
33 u32 g2pstatus; /* +80 */
34 u32 g2pmask;
35 u32 pcisstatus;
36 u32 pcimask;
37 u32 p2gcfg; /* +90 */
38 u32 p2gstatus;
39 u32 p2gmask;
40 u32 p2gccmd;
41 u32 unused4[24]; /* +a0 */
42 u32 pbareqport; /* +100 */
43 u32 pbacfg;
44 u32 pbastatus;
45 u32 pbamask;
46 u32 pbabm; /* +110 */
47 u32 pbacreq;
48 u32 pbacgnt;
49 u32 pbacstate;
50 u64 g2pmgbase[3]; /* +120 */
51 u64 g2piogbase;
52 u32 g2pmmask[3]; /* +140 */
53 u32 g2piomask;
54 u64 g2pmpbase[3]; /* +150 */
55 u64 g2piopbase;
56 u32 pciccfg; /* +170 */
57 u32 pcicstatus;
58 u32 pcicmask;
59 u32 unused5;
60 u64 p2gmgbase[3]; /* +180 */
61 u64 p2giogbase;
62 u32 g2pcfgadrs; /* +1a0 */
63 u32 g2pcfgdata;
64 u32 unused6[8];
65 u32 g2pintack;
66 u32 g2pspc;
67 u32 unused7[12]; /* +1d0 */
68 u64 pdmca; /* +200 */
69 u64 pdmga;
70 u64 pdmpa;
71 u64 pdmctr;
72 u64 pdmcfg; /* +220 */
73 u64 pdmsts;
74};
75
76/* bits for PCICMD */
77/* see PCI_COMMAND_XXX in linux/pci_regs.h */
78
79/* bits for PCISTAT */
80/* see PCI_STATUS_XXX in linux/pci_regs.h */
81
82/* bits for IOBA/MBA */
83/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
84
85/* bits for G2PSTATUS/G2PMASK */
86#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
87#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
88#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
89
90/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
91#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
92
93/* bits for PBACFG */
94#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
95#define TX4927_PCIC_PBACFG_RPBA 0x00000004
96#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
97#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
98
99/* bits for PBASTATUS/PBAMASK */
100#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
101#define TX4927_PCIC_PBASTATUS_BM 0x00000001
102
103/* bits for G2PMnGBASE */
104#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
105#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
106
107/* bits for G2PIOGBASE */
108#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
109#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
110
111/* bits for PCICSTATUS/PCICMASK */
112#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
113#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
114#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
115#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
116#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
117#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
118#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
119#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
120#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
121#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
122
123/* bits for PCICCFG */
124#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
125#define TX4927_PCIC_PCICCFG_HRST 0x00000800
126#define TX4927_PCIC_PCICCFG_SRST 0x00000400
127#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
128#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
129#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
130#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
131#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
132#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
133#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
134#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
135
136/* bits for P2GMnGBASE */
137#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
138#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
139#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
140
141/* bits for P2GIOGBASE */
142#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
143#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
144#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
145
146#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
147#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
148
149/* bits for PDMCFG */
150#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
151#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
152#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
153#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
154#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
155#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
156#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
157#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
158#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
159#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
160#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
161#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
162#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
163#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
164#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
165#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
166#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
167#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
168#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
169#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
170#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
171#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
172#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
173
174/* bits for PDMSTS */
175#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
176#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
177#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
178#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
179#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
180#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
181#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
182#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
183#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
184#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
185#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
186#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
187#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
188#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
189#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
190#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
191#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
192
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void);
198
199#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
new file mode 100644
index 000000000000..12de68a4c10a
--- /dev/null
+++ b/include/asm-mips/txx9/tx4938.h
@@ -0,0 +1,465 @@
1/*
2 * Definitions for TX4937/TX4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#ifndef __ASM_TXX9_TX4938_H
13#define __ASM_TXX9_TX4938_H
14
15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h>
17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
20
21#define TX4938_PCIIO_0 0x10000000
22#define TX4938_PCIIO_1 0x01010000
23#define TX4938_PCIMEM_0 0x08000000
24#define TX4938_PCIMEM_1 0x11000000
25
26#define TX4938_PCIIO_SIZE_0 0x01000000
27#define TX4938_PCIIO_SIZE_1 0x00010000
28#define TX4938_PCIMEM_SIZE_0 0x08000000
29#define TX4938_PCIMEM_SIZE_1 0x00010000
30
31#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
32#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
33
34/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
35#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
36#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
37#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
38#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
39#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
40#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
41#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
42#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
43#define TX4938_NR_TMR 3
44#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
45#define TX4938_NR_SIO 2
46#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
47#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
48#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
51
52#define _CONST64(c) c##ull
53
54#include <asm/byteorder.h>
55
56#ifdef __BIG_ENDIAN
57#define endian_def_l2(e1, e2) \
58 volatile unsigned long e1, e2
59#define endian_def_s2(e1, e2) \
60 volatile unsigned short e1, e2
61#define endian_def_sb2(e1, e2, e3) \
62 volatile unsigned short e1;volatile unsigned char e2, e3
63#define endian_def_b2s(e1, e2, e3) \
64 volatile unsigned char e1, e2;volatile unsigned short e3
65#define endian_def_b4(e1, e2, e3, e4) \
66 volatile unsigned char e1, e2, e3, e4
67#else
68#define endian_def_l2(e1, e2) \
69 volatile unsigned long e2, e1
70#define endian_def_s2(e1, e2) \
71 volatile unsigned short e2, e1
72#define endian_def_sb2(e1, e2, e3) \
73 volatile unsigned char e3, e2;volatile unsigned short e1
74#define endian_def_b2s(e1, e2, e3) \
75 volatile unsigned short e3;volatile unsigned char e2, e1
76#define endian_def_b4(e1, e2, e3, e4) \
77 volatile unsigned char e4, e3, e2, e1
78#endif
79
80
81struct tx4938_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87 volatile unsigned long long sfcmd;
88};
89
90struct tx4938_ebusc_reg {
91 volatile unsigned long long cr[8];
92};
93
94struct tx4938_dma_reg {
95 struct tx4938_dma_ch_reg {
96 volatile unsigned long long cha;
97 volatile unsigned long long sar;
98 volatile unsigned long long dar;
99 endian_def_l2(unused0, cntr);
100 endian_def_l2(unused1, sair);
101 endian_def_l2(unused2, dair);
102 endian_def_l2(unused3, ccr);
103 endian_def_l2(unused4, csr);
104 } ch[4];
105 volatile unsigned long long dbr[8];
106 volatile unsigned long long tdhr;
107 volatile unsigned long long midr;
108 endian_def_l2(unused0, mcr);
109};
110
111struct tx4938_aclc_reg {
112 volatile unsigned long acctlen;
113 volatile unsigned long acctldis;
114 volatile unsigned long acregacc;
115 volatile unsigned long unused0;
116 volatile unsigned long acintsts;
117 volatile unsigned long acintmsts;
118 volatile unsigned long acinten;
119 volatile unsigned long acintdis;
120 volatile unsigned long acsemaph;
121 volatile unsigned long unused1[7];
122 volatile unsigned long acgpidat;
123 volatile unsigned long acgpodat;
124 volatile unsigned long acslten;
125 volatile unsigned long acsltdis;
126 volatile unsigned long acfifosts;
127 volatile unsigned long unused2[11];
128 volatile unsigned long acdmasts;
129 volatile unsigned long acdmasel;
130 volatile unsigned long unused3[6];
131 volatile unsigned long acaudodat;
132 volatile unsigned long acsurrdat;
133 volatile unsigned long accentdat;
134 volatile unsigned long aclfedat;
135 volatile unsigned long acaudiat;
136 volatile unsigned long unused4;
137 volatile unsigned long acmodoat;
138 volatile unsigned long acmodidat;
139 volatile unsigned long unused5[15];
140 volatile unsigned long acrevid;
141};
142
143
144struct tx4938_tmr_reg {
145 volatile unsigned long tcr;
146 volatile unsigned long tisr;
147 volatile unsigned long cpra;
148 volatile unsigned long cprb;
149 volatile unsigned long itmr;
150 volatile unsigned long unused0[3];
151 volatile unsigned long ccdr;
152 volatile unsigned long unused1[3];
153 volatile unsigned long pgmr;
154 volatile unsigned long unused2[3];
155 volatile unsigned long wtmr;
156 volatile unsigned long unused3[43];
157 volatile unsigned long trr;
158};
159
160struct tx4938_sio_reg {
161 volatile unsigned long lcr;
162 volatile unsigned long dicr;
163 volatile unsigned long disr;
164 volatile unsigned long cisr;
165 volatile unsigned long fcr;
166 volatile unsigned long flcr;
167 volatile unsigned long bgr;
168 volatile unsigned long tfifo;
169 volatile unsigned long rfifo;
170};
171
172struct tx4938_ndfmc_reg {
173 endian_def_l2(unused0, dtr);
174 endian_def_l2(unused1, mcr);
175 endian_def_l2(unused2, sr);
176 endian_def_l2(unused3, isr);
177 endian_def_l2(unused4, imr);
178 endian_def_l2(unused5, spr);
179 endian_def_l2(unused6, rstr);
180};
181
182struct tx4938_spi_reg {
183 volatile unsigned long mcr;
184 volatile unsigned long cr0;
185 volatile unsigned long cr1;
186 volatile unsigned long fs;
187 volatile unsigned long unused1;
188 volatile unsigned long sr;
189 volatile unsigned long dr;
190 volatile unsigned long unused2;
191};
192
193struct tx4938_sramc_reg {
194 volatile unsigned long long cr;
195};
196
197struct tx4938_ccfg_reg {
198 u64 ccfg;
199 u64 crir;
200 u64 pcfg;
201 u64 toea;
202 u64 clkctr;
203 u64 unused0;
204 u64 garbc;
205 u64 unused1;
206 u64 unused2;
207 u64 ramp;
208 u64 unused3;
209 u64 jmpadr;
210};
211
212#undef endian_def_l2
213#undef endian_def_s2
214#undef endian_def_sb2
215#undef endian_def_b2s
216#undef endian_def_b4
217
218/*
219 * NDFMC
220 */
221
222/* NDFMCR : NDFMC Mode Control */
223#define TX4938_NDFMCR_WE 0x80
224#define TX4938_NDFMCR_ECC_ALL 0x60
225#define TX4938_NDFMCR_ECC_RESET 0x60
226#define TX4938_NDFMCR_ECC_READ 0x40
227#define TX4938_NDFMCR_ECC_ON 0x20
228#define TX4938_NDFMCR_ECC_OFF 0x00
229#define TX4938_NDFMCR_CE 0x10
230#define TX4938_NDFMCR_BSPRT 0x04
231#define TX4938_NDFMCR_ALE 0x02
232#define TX4938_NDFMCR_CLE 0x01
233
234/* NDFMCR : NDFMC Status */
235#define TX4938_NDFSR_BUSY 0x80
236
237/* NDFMCR : NDFMC Reset */
238#define TX4938_NDFRSTR_RST 0x01
239
240/*
241 * IRC
242 */
243
244#define TX4938_IR_ECCERR 0
245#define TX4938_IR_WTOERR 1
246#define TX4938_NUM_IR_INT 6
247#define TX4938_IR_INT(n) (2 + (n))
248#define TX4938_NUM_IR_SIO 2
249#define TX4938_IR_SIO(n) (8 + (n))
250#define TX4938_NUM_IR_DMA 4
251#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
252#define TX4938_IR_PIO 14
253#define TX4938_IR_PDMAC 15
254#define TX4938_IR_PCIC 16
255#define TX4938_NUM_IR_TMR 3
256#define TX4938_IR_TMR(n) (17 + (n))
257#define TX4938_IR_NDFMC 21
258#define TX4938_IR_PCIERR 22
259#define TX4938_IR_PCIPME 23
260#define TX4938_IR_ACLC 24
261#define TX4938_IR_ACLCPME 25
262#define TX4938_IR_PCIC1 26
263#define TX4938_IR_SPI 31
264#define TX4938_NUM_IR 32
265/* multiplex */
266#define TX4938_IR_ETH0 TX4938_IR_INT(4)
267#define TX4938_IR_ETH1 TX4938_IR_INT(3)
268
269#define TX4938_IRC_INT 2 /* IP[2] in Status register */
270
271/*
272 * CCFG
273 */
274/* CCFG : Chip Configuration */
275#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000)
276#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000)
277#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000)
278#define TX4938_CCFG_TINTDIS 0x01000000
279#define TX4938_CCFG_PCI66 0x00800000
280#define TX4938_CCFG_PCIMODE 0x00400000
281#define TX4938_CCFG_PCI1_66 0x00200000
282#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
283#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
284#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
285#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
286#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
287#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
288#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
289#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
290#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
291#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
292#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
293#define TX4938_CCFG_BEOW 0x00010000
294#define TX4938_CCFG_WR 0x00008000
295#define TX4938_CCFG_TOE 0x00004000
296#define TX4938_CCFG_PCIARB 0x00002000
297#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
298#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
299#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
300#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
301#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
302#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
303#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
304#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
305#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
306#define TX4938_CCFG_PCI1DMD 0x00000100
307#define TX4938_CCFG_SYSSP_MASK 0x000000c0
308#define TX4938_CCFG_ENDIAN 0x00000004
309#define TX4938_CCFG_HALT 0x00000002
310#define TX4938_CCFG_ACEHOLD 0x00000001
311
312/* PCFG : Pin Configuration */
313#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000)
314#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000)
315#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000)
316#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000)
317#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000)
318#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000)
319#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
320#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
321#define TX4938_PCFG_SYSCLKEN 0x08000000
322#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
323#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
324#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
325#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
326#define TX4938_PCFG_SEL2 0x00000200
327#define TX4938_PCFG_SEL1 0x00000100
328#define TX4938_PCFG_DMASEL_ALL 0x0000000f
329#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
330#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
331#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
332#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
333#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
334#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
335#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
336#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
337
338/* CLKCTR : Clock Control */
339#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000)
340#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000)
341#define TX4938_CLKCTR_ETH1CKD 0x80000000
342#define TX4938_CLKCTR_ETH0CKD 0x40000000
343#define TX4938_CLKCTR_SPICKD 0x20000000
344#define TX4938_CLKCTR_SRAMCKD 0x10000000
345#define TX4938_CLKCTR_PCIC1CKD 0x08000000
346#define TX4938_CLKCTR_DMA1CKD 0x04000000
347#define TX4938_CLKCTR_ACLCKD 0x02000000
348#define TX4938_CLKCTR_PIOCKD 0x01000000
349#define TX4938_CLKCTR_DMACKD 0x00800000
350#define TX4938_CLKCTR_PCICKD 0x00400000
351#define TX4938_CLKCTR_TM0CKD 0x00100000
352#define TX4938_CLKCTR_TM1CKD 0x00080000
353#define TX4938_CLKCTR_TM2CKD 0x00040000
354#define TX4938_CLKCTR_SIO0CKD 0x00020000
355#define TX4938_CLKCTR_SIO1CKD 0x00010000
356#define TX4938_CLKCTR_ETH1RST 0x00008000
357#define TX4938_CLKCTR_ETH0RST 0x00004000
358#define TX4938_CLKCTR_SPIRST 0x00002000
359#define TX4938_CLKCTR_SRAMRST 0x00001000
360#define TX4938_CLKCTR_PCIC1RST 0x00000800
361#define TX4938_CLKCTR_DMA1RST 0x00000400
362#define TX4938_CLKCTR_ACLRST 0x00000200
363#define TX4938_CLKCTR_PIORST 0x00000100
364#define TX4938_CLKCTR_DMARST 0x00000080
365#define TX4938_CLKCTR_PCIRST 0x00000040
366#define TX4938_CLKCTR_TM0RST 0x00000010
367#define TX4938_CLKCTR_TM1RST 0x00000008
368#define TX4938_CLKCTR_TM2RST 0x00000004
369#define TX4938_CLKCTR_SIO0RST 0x00000002
370#define TX4938_CLKCTR_SIO1RST 0x00000001
371
372/*
373 * DMA
374 */
375/* bits for MCR */
376#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
377#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
378#define TX4938_DMA_MCR_RSFIF 0x00000080
379#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
380#define TX4938_DMA_MCR_RPRT 0x00000002
381#define TX4938_DMA_MCR_MSTEN 0x00000001
382
383/* bits for CCRn */
384#define TX4938_DMA_CCR_IMMCHN 0x20000000
385#define TX4938_DMA_CCR_USEXFSZ 0x10000000
386#define TX4938_DMA_CCR_LE 0x08000000
387#define TX4938_DMA_CCR_DBINH 0x04000000
388#define TX4938_DMA_CCR_SBINH 0x02000000
389#define TX4938_DMA_CCR_CHRST 0x01000000
390#define TX4938_DMA_CCR_RVBYTE 0x00800000
391#define TX4938_DMA_CCR_ACKPOL 0x00400000
392#define TX4938_DMA_CCR_REQPL 0x00200000
393#define TX4938_DMA_CCR_EGREQ 0x00100000
394#define TX4938_DMA_CCR_CHDN 0x00080000
395#define TX4938_DMA_CCR_DNCTL 0x00060000
396#define TX4938_DMA_CCR_EXTRQ 0x00010000
397#define TX4938_DMA_CCR_INTRQD 0x0000e000
398#define TX4938_DMA_CCR_INTENE 0x00001000
399#define TX4938_DMA_CCR_INTENC 0x00000800
400#define TX4938_DMA_CCR_INTENT 0x00000400
401#define TX4938_DMA_CCR_CHNEN 0x00000200
402#define TX4938_DMA_CCR_XFACT 0x00000100
403#define TX4938_DMA_CCR_SMPCHN 0x00000020
404#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
405#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
406#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
407#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
408#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
409#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
410#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
411#define TX4938_DMA_CCR_MEMIO 0x00000002
412#define TX4938_DMA_CCR_SNGAD 0x00000001
413
414/* bits for CSRn */
415#define TX4938_DMA_CSR_CHNEN 0x00000400
416#define TX4938_DMA_CSR_STLXFER 0x00000200
417#define TX4938_DMA_CSR_CHNACT 0x00000100
418#define TX4938_DMA_CSR_ABCHC 0x00000080
419#define TX4938_DMA_CSR_NCHNC 0x00000040
420#define TX4938_DMA_CSR_NTRNFC 0x00000020
421#define TX4938_DMA_CSR_EXTDN 0x00000010
422#define TX4938_DMA_CSR_CFERR 0x00000008
423#define TX4938_DMA_CSR_CHERR 0x00000004
424#define TX4938_DMA_CSR_DESERR 0x00000002
425#define TX4938_DMA_CSR_SORERR 0x00000001
426
427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
431#define tx4938_pcicptr tx4927_pcicptr
432#define tx4938_pcic1ptr \
433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
439#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
441
442
443#define TX4938_REV_PCODE() \
444 ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
445
446#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
449
450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
452
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
455#define TX4938_EBUSC_SIZE(ch) \
456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
457
458int tx4938_report_pciclk(void);
459void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void);
461struct pci_dev;
462int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
463void tx4938_irq_init(void);
464
465#endif
diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h
new file mode 100644
index 000000000000..97dd7ad1a890
--- /dev/null
+++ b/include/asm-mips/txx9/txx927.h
@@ -0,0 +1,121 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_TXX927_H
11#define __ASM_TXX9_TXX927_H
12
13struct txx927_sio_reg {
14 volatile unsigned long lcr;
15 volatile unsigned long dicr;
16 volatile unsigned long disr;
17 volatile unsigned long cisr;
18 volatile unsigned long fcr;
19 volatile unsigned long flcr;
20 volatile unsigned long bgr;
21 volatile unsigned long tfifo;
22 volatile unsigned long rfifo;
23};
24
25/*
26 * SIO
27 */
28/* SILCR : Line Control */
29#define TXx927_SILCR_SCS_MASK 0x00000060
30#define TXx927_SILCR_SCS_IMCLK 0x00000000
31#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
32#define TXx927_SILCR_SCS_SCLK 0x00000040
33#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
34#define TXx927_SILCR_UEPS 0x00000010
35#define TXx927_SILCR_UPEN 0x00000008
36#define TXx927_SILCR_USBL_MASK 0x00000004
37#define TXx927_SILCR_USBL_1BIT 0x00000004
38#define TXx927_SILCR_USBL_2BIT 0x00000000
39#define TXx927_SILCR_UMODE_MASK 0x00000003
40#define TXx927_SILCR_UMODE_8BIT 0x00000000
41#define TXx927_SILCR_UMODE_7BIT 0x00000001
42
43/* SIDICR : DMA/Int. Control */
44#define TXx927_SIDICR_TDE 0x00008000
45#define TXx927_SIDICR_RDE 0x00004000
46#define TXx927_SIDICR_TIE 0x00002000
47#define TXx927_SIDICR_RIE 0x00001000
48#define TXx927_SIDICR_SPIE 0x00000800
49#define TXx927_SIDICR_CTSAC 0x00000600
50#define TXx927_SIDICR_STIE_MASK 0x0000003f
51#define TXx927_SIDICR_STIE_OERS 0x00000020
52#define TXx927_SIDICR_STIE_CTSS 0x00000010
53#define TXx927_SIDICR_STIE_RBRKD 0x00000008
54#define TXx927_SIDICR_STIE_TRDY 0x00000004
55#define TXx927_SIDICR_STIE_TXALS 0x00000002
56#define TXx927_SIDICR_STIE_UBRKD 0x00000001
57
58/* SIDISR : DMA/Int. Status */
59#define TXx927_SIDISR_UBRK 0x00008000
60#define TXx927_SIDISR_UVALID 0x00004000
61#define TXx927_SIDISR_UFER 0x00002000
62#define TXx927_SIDISR_UPER 0x00001000
63#define TXx927_SIDISR_UOER 0x00000800
64#define TXx927_SIDISR_ERI 0x00000400
65#define TXx927_SIDISR_TOUT 0x00000200
66#define TXx927_SIDISR_TDIS 0x00000100
67#define TXx927_SIDISR_RDIS 0x00000080
68#define TXx927_SIDISR_STIS 0x00000040
69#define TXx927_SIDISR_RFDN_MASK 0x0000001f
70
71/* SICISR : Change Int. Status */
72#define TXx927_SICISR_OERS 0x00000020
73#define TXx927_SICISR_CTSS 0x00000010
74#define TXx927_SICISR_RBRKD 0x00000008
75#define TXx927_SICISR_TRDY 0x00000004
76#define TXx927_SICISR_TXALS 0x00000002
77#define TXx927_SICISR_UBRKD 0x00000001
78
79/* SIFCR : FIFO Control */
80#define TXx927_SIFCR_SWRST 0x00008000
81#define TXx927_SIFCR_RDIL_MASK 0x00000180
82#define TXx927_SIFCR_RDIL_1 0x00000000
83#define TXx927_SIFCR_RDIL_4 0x00000080
84#define TXx927_SIFCR_RDIL_8 0x00000100
85#define TXx927_SIFCR_RDIL_12 0x00000180
86#define TXx927_SIFCR_RDIL_MAX 0x00000180
87#define TXx927_SIFCR_TDIL_MASK 0x00000018
88#define TXx927_SIFCR_TDIL_MASK 0x00000018
89#define TXx927_SIFCR_TDIL_1 0x00000000
90#define TXx927_SIFCR_TDIL_4 0x00000001
91#define TXx927_SIFCR_TDIL_8 0x00000010
92#define TXx927_SIFCR_TDIL_MAX 0x00000010
93#define TXx927_SIFCR_TFRST 0x00000004
94#define TXx927_SIFCR_RFRST 0x00000002
95#define TXx927_SIFCR_FRSTE 0x00000001
96#define TXx927_SIO_TX_FIFO 8
97#define TXx927_SIO_RX_FIFO 16
98
99/* SIFLCR : Flow Control */
100#define TXx927_SIFLCR_RCS 0x00001000
101#define TXx927_SIFLCR_TES 0x00000800
102#define TXx927_SIFLCR_RTSSC 0x00000200
103#define TXx927_SIFLCR_RSDE 0x00000100
104#define TXx927_SIFLCR_TSDE 0x00000080
105#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
106#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
107#define TXx927_SIFLCR_TBRK 0x00000001
108
109/* SIBGR : Baudrate Control */
110#define TXx927_SIBGR_BCLK_MASK 0x00000300
111#define TXx927_SIBGR_BCLK_T0 0x00000000
112#define TXx927_SIBGR_BCLK_T2 0x00000100
113#define TXx927_SIBGR_BCLK_T4 0x00000200
114#define TXx927_SIBGR_BCLK_T6 0x00000300
115#define TXx927_SIBGR_BRD_MASK 0x000000ff
116
117/*
118 * PIO
119 */
120
121#endif /* __ASM_TXX9_TXX927_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 00:49:36 -0500