1 files changed, 465 insertions, 0 deletions
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
new file mode 100644
index 000000000000..12de68a4c10a
--- /dev/null
+++ b/include/asm-mips/txx9/tx4938.h
@@ -0,0 +1,465 @@
+/*
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_TX4938_H
+#define __ASM_TXX9_TX4938_H
+/* some controllers are compatible with 4927 */
+#include <asm/txx9/tx4927.h>
+#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
+#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
+#define TX4938_PCIIO_0 0x10000000
+#define TX4938_PCIIO_1 0x01010000
+#define TX4938_PCIMEM_0 0x08000000
+#define TX4938_PCIMEM_1 0x11000000
+#define TX4938_PCIIO_SIZE_0 0x01000000
+#define TX4938_PCIIO_SIZE_1 0x00010000
+#define TX4938_PCIMEM_SIZE_0 0x08000000
+#define TX4938_PCIMEM_SIZE_1 0x00010000
+#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+#define _CONST64(c)     c##ull
+#include <asm/byteorder.h>
+#ifdef __BIG_ENDIAN
+#define endian_def_l2(e1, e2)   \
+        volatile unsigned long e1, e2
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e1, e2
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned short e1;volatile unsigned char e2, e3
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned char e1, e2;volatile unsigned short e3
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e1, e2, e3, e4
+#else
+#define endian_def_l2(e1, e2)   \
+        volatile unsigned long e2, e1
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e2, e1
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned char e3, e2;volatile unsigned short e1
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned short e3;volatile unsigned char e2, e1
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e4, e3, e2, e1
+#endif
+struct tx4938_sdramc_reg {
+        volatile unsigned long long cr[4];
+        volatile unsigned long long unused0[4];
+        volatile unsigned long long tr;
+        volatile unsigned long long unused1[2];
+        volatile unsigned long long cmd;
+        volatile unsigned long long sfcmd;
+};
+struct tx4938_ebusc_reg {
+        volatile unsigned long long cr[8];
+};
+struct tx4938_dma_reg {
+        struct tx4938_dma_ch_reg {
+                volatile unsigned long long cha;
+                volatile unsigned long long sar;
+                volatile unsigned long long dar;
+                endian_def_l2(unused0, cntr);
+                endian_def_l2(unused1, sair);
+                endian_def_l2(unused2, dair);
+                endian_def_l2(unused3, ccr);
+                endian_def_l2(unused4, csr);
+        } ch[4];
+        volatile unsigned long long dbr[8];
+        volatile unsigned long long tdhr;
+        volatile unsigned long long midr;
+        endian_def_l2(unused0, mcr);
+};
+struct tx4938_aclc_reg {
+        volatile unsigned long acctlen;
+        volatile unsigned long acctldis;
+        volatile unsigned long acregacc;
+        volatile unsigned long unused0;
+        volatile unsigned long acintsts;
+        volatile unsigned long acintmsts;
+        volatile unsigned long acinten;
+        volatile unsigned long acintdis;
+        volatile unsigned long acsemaph;
+        volatile unsigned long unused1[7];
+        volatile unsigned long acgpidat;
+        volatile unsigned long acgpodat;
+        volatile unsigned long acslten;
+        volatile unsigned long acsltdis;
+        volatile unsigned long acfifosts;
+        volatile unsigned long unused2[11];
+        volatile unsigned long acdmasts;
+        volatile unsigned long acdmasel;
+        volatile unsigned long unused3[6];
+        volatile unsigned long acaudodat;
+        volatile unsigned long acsurrdat;
+        volatile unsigned long accentdat;
+        volatile unsigned long aclfedat;
+        volatile unsigned long acaudiat;
+        volatile unsigned long unused4;
+        volatile unsigned long acmodoat;
+        volatile unsigned long acmodidat;
+        volatile unsigned long unused5[15];
+        volatile unsigned long acrevid;
+};
+struct tx4938_tmr_reg {
+        volatile unsigned long tcr;
+        volatile unsigned long tisr;
+        volatile unsigned long cpra;
+        volatile unsigned long cprb;
+        volatile unsigned long itmr;
+        volatile unsigned long unused0[3];
+        volatile unsigned long ccdr;
+        volatile unsigned long unused1[3];
+        volatile unsigned long pgmr;
+        volatile unsigned long unused2[3];
+        volatile unsigned long wtmr;
+        volatile unsigned long unused3[43];
+        volatile unsigned long trr;
+};
+struct tx4938_sio_reg {
+        volatile unsigned long lcr;
+        volatile unsigned long dicr;
+        volatile unsigned long disr;
+        volatile unsigned long cisr;
+        volatile unsigned long fcr;
+        volatile unsigned long flcr;
+        volatile unsigned long bgr;
+        volatile unsigned long tfifo;
+        volatile unsigned long rfifo;
+};
+struct tx4938_ndfmc_reg {
+        endian_def_l2(unused0, dtr);
+        endian_def_l2(unused1, mcr);
+        endian_def_l2(unused2, sr);
+        endian_def_l2(unused3, isr);
+        endian_def_l2(unused4, imr);
+        endian_def_l2(unused5, spr);
+        endian_def_l2(unused6, rstr);
+};
+struct tx4938_spi_reg {
+        volatile unsigned long mcr;
+        volatile unsigned long cr0;
+        volatile unsigned long cr1;
+        volatile unsigned long fs;
+        volatile unsigned long unused1;
+        volatile unsigned long sr;
+        volatile unsigned long dr;
+        volatile unsigned long unused2;
+};
+struct tx4938_sramc_reg {
+        volatile unsigned long long cr;
+};
+struct tx4938_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+        u64 unused3;
+        u64 jmpadr;
+};
+#undef endian_def_l2
+#undef endian_def_s2
+#undef endian_def_sb2
+#undef endian_def_b2s
+#undef endian_def_b4
+/*
+ * NDFMC
+ */
+/* NDFMCR : NDFMC Mode Control */
+#define TX4938_NDFMCR_WE        0x80
+#define TX4938_NDFMCR_ECC_ALL   0x60
+#define TX4938_NDFMCR_ECC_RESET 0x60
+#define TX4938_NDFMCR_ECC_READ  0x40
+#define TX4938_NDFMCR_ECC_ON    0x20
+#define TX4938_NDFMCR_ECC_OFF   0x00
+#define TX4938_NDFMCR_CE        0x10
+#define TX4938_NDFMCR_BSPRT     0x04
+#define TX4938_NDFMCR_ALE       0x02
+#define TX4938_NDFMCR_CLE       0x01
+/* NDFMCR : NDFMC Status */
+#define TX4938_NDFSR_BUSY       0x80
+/* NDFMCR : NDFMC Reset */
+#define TX4938_NDFRSTR_RST      0x01
+/*
+ * IRC
+ */
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+#define TX4938_IRC_INT  2       /* IP[2] in Status register */
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
+#define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
+#define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIARB      0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
+#define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
+#define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
+#define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
+#define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
+#define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
+#define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+#define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
+#define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
+#define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
+#define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
+#define tx4938_pcicptr          tx4927_pcicptr
+#define tx4938_pcic1ptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr \
+                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
+#define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
+#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
+#define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
+#define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
+#define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
+#define TX4938_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
+#define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
+#define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
+#define TX4938_EBUSC_CR(ch)     __raw_readq(&tx4938_ebuscptr->cr[(ch)])
+#define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
+#define TX4938_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
+int tx4938_report_pciclk(void);
+void tx4938_report_pci1clk(void);
+int tx4938_pciclk66_setup(void);
+struct pci_dev;
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+void tx4938_irq_init(void);
+#endif

diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h new file mode 100644 index 000000000000..12de68a4c10a --- /dev/null +++ b/include/asm-mips/txx9/tx4938.h
@@ -0,0 +1,465 @@
	1	/*
	2	* Definitions for TX4937/TX4938
	3	* Copyright (C) 2000-2001 Toshiba Corporation
	4	*
	5	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	6	* terms of the GNU General Public License version 2. This program is
	7	* licensed "as is" without any warranty of any kind, whether express
	8	* or implied.
	9	*
	10	* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
	11	*/
	12	#ifndef __ASM_TXX9_TX4938_H
	13	#define __ASM_TXX9_TX4938_H
	14
	15	/* some controllers are compatible with 4927 */
	16	#include <asm/txx9/tx4927.h>
	17
	18	#define tx4938_read_nfmc(addr) ((volatile unsigned int )(addr))
	19	#define tx4938_write_nfmc(b, addr) ((volatile unsigned int )(addr)) = (b)
	20
	21	#define TX4938_PCIIO_0 0x10000000
	22	#define TX4938_PCIIO_1 0x01010000
	23	#define TX4938_PCIMEM_0 0x08000000
	24	#define TX4938_PCIMEM_1 0x11000000
	25
	26	#define TX4938_PCIIO_SIZE_0 0x01000000
	27	#define TX4938_PCIIO_SIZE_1 0x00010000
	28	#define TX4938_PCIMEM_SIZE_0 0x08000000
	29	#define TX4938_PCIMEM_SIZE_1 0x00010000
	30
	31	#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
	32	#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
	33
	34	/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
	35	#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
	36	#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
	37	#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
	38	#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
	39	#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
	40	#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
	41	#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
	42	#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
	43	#define TX4938_NR_TMR 3
	44	#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
	45	#define TX4938_NR_SIO 2
	46	#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
	47	#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
	48	#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
	49	#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
	50	#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
	51
	52	#define _CONST64(c) c##ull
	53
	54	#include <asm/byteorder.h>
	55
	56	#ifdef __BIG_ENDIAN
	57	#define endian_def_l2(e1, e2) \
	58	volatile unsigned long e1, e2
	59	#define endian_def_s2(e1, e2) \
	60	volatile unsigned short e1, e2
	61	#define endian_def_sb2(e1, e2, e3) \
	62	volatile unsigned short e1;volatile unsigned char e2, e3
	63	#define endian_def_b2s(e1, e2, e3) \
	64	volatile unsigned char e1, e2;volatile unsigned short e3
	65	#define endian_def_b4(e1, e2, e3, e4) \
	66	volatile unsigned char e1, e2, e3, e4
	67	#else
	68	#define endian_def_l2(e1, e2) \
	69	volatile unsigned long e2, e1
	70	#define endian_def_s2(e1, e2) \
	71	volatile unsigned short e2, e1
	72	#define endian_def_sb2(e1, e2, e3) \
	73	volatile unsigned char e3, e2;volatile unsigned short e1
	74	#define endian_def_b2s(e1, e2, e3) \
	75	volatile unsigned short e3;volatile unsigned char e2, e1
	76	#define endian_def_b4(e1, e2, e3, e4) \
	77	volatile unsigned char e4, e3, e2, e1
	78	#endif
	79
	80
	81	struct tx4938_sdramc_reg {
	82	volatile unsigned long long cr[4];
	83	volatile unsigned long long unused0[4];
	84	volatile unsigned long long tr;
	85	volatile unsigned long long unused1[2];
	86	volatile unsigned long long cmd;
	87	volatile unsigned long long sfcmd;
	88	};
	89
	90	struct tx4938_ebusc_reg {
	91	volatile unsigned long long cr[8];
	92	};
	93
	94	struct tx4938_dma_reg {
	95	struct tx4938_dma_ch_reg {
	96	volatile unsigned long long cha;
	97	volatile unsigned long long sar;
	98	volatile unsigned long long dar;
	99	endian_def_l2(unused0, cntr);
	100	endian_def_l2(unused1, sair);
	101	endian_def_l2(unused2, dair);
	102	endian_def_l2(unused3, ccr);
	103	endian_def_l2(unused4, csr);
	104	} ch[4];
	105	volatile unsigned long long dbr[8];
	106	volatile unsigned long long tdhr;
	107	volatile unsigned long long midr;
	108	endian_def_l2(unused0, mcr);
	109	};
	110
	111	struct tx4938_aclc_reg {
	112	volatile unsigned long acctlen;
	113	volatile unsigned long acctldis;
	114	volatile unsigned long acregacc;
	115	volatile unsigned long unused0;
	116	volatile unsigned long acintsts;
	117	volatile unsigned long acintmsts;
	118	volatile unsigned long acinten;
	119	volatile unsigned long acintdis;
	120	volatile unsigned long acsemaph;
	121	volatile unsigned long unused1[7];
	122	volatile unsigned long acgpidat;
	123	volatile unsigned long acgpodat;
	124	volatile unsigned long acslten;
	125	volatile unsigned long acsltdis;
	126	volatile unsigned long acfifosts;
	127	volatile unsigned long unused2[11];
	128	volatile unsigned long acdmasts;
	129	volatile unsigned long acdmasel;
	130	volatile unsigned long unused3[6];
	131	volatile unsigned long acaudodat;
	132	volatile unsigned long acsurrdat;
	133	volatile unsigned long accentdat;
	134	volatile unsigned long aclfedat;
	135	volatile unsigned long acaudiat;
	136	volatile unsigned long unused4;
	137	volatile unsigned long acmodoat;
	138	volatile unsigned long acmodidat;
	139	volatile unsigned long unused5[15];
	140	volatile unsigned long acrevid;
	141	};
	142
	143
	144	struct tx4938_tmr_reg {
	145	volatile unsigned long tcr;
	146	volatile unsigned long tisr;
	147	volatile unsigned long cpra;
	148	volatile unsigned long cprb;
	149	volatile unsigned long itmr;
	150	volatile unsigned long unused0[3];
	151	volatile unsigned long ccdr;
	152	volatile unsigned long unused1[3];
	153	volatile unsigned long pgmr;
	154	volatile unsigned long unused2[3];
	155	volatile unsigned long wtmr;
	156	volatile unsigned long unused3[43];
	157	volatile unsigned long trr;
	158	};
	159
	160	struct tx4938_sio_reg {
	161	volatile unsigned long lcr;
	162	volatile unsigned long dicr;
	163	volatile unsigned long disr;
	164	volatile unsigned long cisr;
	165	volatile unsigned long fcr;
	166	volatile unsigned long flcr;
	167	volatile unsigned long bgr;
	168	volatile unsigned long tfifo;
	169	volatile unsigned long rfifo;
	170	};
	171
	172	struct tx4938_ndfmc_reg {
	173	endian_def_l2(unused0, dtr);
	174	endian_def_l2(unused1, mcr);
	175	endian_def_l2(unused2, sr);
	176	endian_def_l2(unused3, isr);
	177	endian_def_l2(unused4, imr);
	178	endian_def_l2(unused5, spr);
	179	endian_def_l2(unused6, rstr);
	180	};
	181
	182	struct tx4938_spi_reg {
	183	volatile unsigned long mcr;
	184	volatile unsigned long cr0;
	185	volatile unsigned long cr1;
	186	volatile unsigned long fs;
	187	volatile unsigned long unused1;
	188	volatile unsigned long sr;
	189	volatile unsigned long dr;
	190	volatile unsigned long unused2;
	191	};
	192
	193	struct tx4938_sramc_reg {
	194	volatile unsigned long long cr;
	195	};
	196
	197	struct tx4938_ccfg_reg {
	198	u64 ccfg;
	199	u64 crir;
	200	u64 pcfg;
	201	u64 toea;
	202	u64 clkctr;
	203	u64 unused0;
	204	u64 garbc;
	205	u64 unused1;
	206	u64 unused2;
	207	u64 ramp;
	208	u64 unused3;
	209	u64 jmpadr;
	210	};
	211
	212	#undef endian_def_l2
	213	#undef endian_def_s2
	214	#undef endian_def_sb2
	215	#undef endian_def_b2s
	216	#undef endian_def_b4
	217
	218	/*
	219	* NDFMC
	220	*/
	221
	222	/* NDFMCR : NDFMC Mode Control */
	223	#define TX4938_NDFMCR_WE 0x80
	224	#define TX4938_NDFMCR_ECC_ALL 0x60
	225	#define TX4938_NDFMCR_ECC_RESET 0x60
	226	#define TX4938_NDFMCR_ECC_READ 0x40
	227	#define TX4938_NDFMCR_ECC_ON 0x20
	228	#define TX4938_NDFMCR_ECC_OFF 0x00
	229	#define TX4938_NDFMCR_CE 0x10
	230	#define TX4938_NDFMCR_BSPRT 0x04
	231	#define TX4938_NDFMCR_ALE 0x02
	232	#define TX4938_NDFMCR_CLE 0x01
	233
	234	/* NDFMCR : NDFMC Status */
	235	#define TX4938_NDFSR_BUSY 0x80
	236
	237	/* NDFMCR : NDFMC Reset */
	238	#define TX4938_NDFRSTR_RST 0x01
	239
	240	/*
	241	* IRC
	242	*/
	243
	244	#define TX4938_IR_ECCERR 0
	245	#define TX4938_IR_WTOERR 1
	246	#define TX4938_NUM_IR_INT 6
	247	#define TX4938_IR_INT(n) (2 + (n))
	248	#define TX4938_NUM_IR_SIO 2
	249	#define TX4938_IR_SIO(n) (8 + (n))
	250	#define TX4938_NUM_IR_DMA 4
	251	#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
	252	#define TX4938_IR_PIO 14
	253	#define TX4938_IR_PDMAC 15
	254	#define TX4938_IR_PCIC 16
	255	#define TX4938_NUM_IR_TMR 3
	256	#define TX4938_IR_TMR(n) (17 + (n))
	257	#define TX4938_IR_NDFMC 21
	258	#define TX4938_IR_PCIERR 22
	259	#define TX4938_IR_PCIPME 23
	260	#define TX4938_IR_ACLC 24
	261	#define TX4938_IR_ACLCPME 25
	262	#define TX4938_IR_PCIC1 26
	263	#define TX4938_IR_SPI 31
	264	#define TX4938_NUM_IR 32
	265	/* multiplex */
	266	#define TX4938_IR_ETH0 TX4938_IR_INT(4)
	267	#define TX4938_IR_ETH1 TX4938_IR_INT(3)
	268
	269	#define TX4938_IRC_INT 2 /* IP[2] in Status register */
	270
	271	/*
	272	* CCFG
	273	*/
	274	/* CCFG : Chip Configuration */
	275	#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000)
	276	#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000)
	277	#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000)
	278	#define TX4938_CCFG_TINTDIS 0x01000000
	279	#define TX4938_CCFG_PCI66 0x00800000
	280	#define TX4938_CCFG_PCIMODE 0x00400000
	281	#define TX4938_CCFG_PCI1_66 0x00200000
	282	#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
	283	#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
	284	#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
	285	#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
	286	#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
	287	#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
	288	#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
	289	#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
	290	#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
	291	#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
	292	#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
	293	#define TX4938_CCFG_BEOW 0x00010000
	294	#define TX4938_CCFG_WR 0x00008000
	295	#define TX4938_CCFG_TOE 0x00004000
	296	#define TX4938_CCFG_PCIARB 0x00002000
	297	#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
	298	#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
	299	#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
	300	#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
	301	#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
	302	#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
	303	#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
	304	#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
	305	#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
	306	#define TX4938_CCFG_PCI1DMD 0x00000100
	307	#define TX4938_CCFG_SYSSP_MASK 0x000000c0
	308	#define TX4938_CCFG_ENDIAN 0x00000004
	309	#define TX4938_CCFG_HALT 0x00000002
	310	#define TX4938_CCFG_ACEHOLD 0x00000001
	311
	312	/* PCFG : Pin Configuration */
	313	#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000)
	314	#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000)
	315	#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000)
	316	#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000)
	317	#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000)
	318	#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000)
	319	#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
	320	#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
	321	#define TX4938_PCFG_SYSCLKEN 0x08000000
	322	#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
	323	#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
	324	#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
	325	#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
	326	#define TX4938_PCFG_SEL2 0x00000200
	327	#define TX4938_PCFG_SEL1 0x00000100
	328	#define TX4938_PCFG_DMASEL_ALL 0x0000000f
	329	#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
	330	#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
	331	#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
	332	#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
	333	#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
	334	#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
	335	#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
	336	#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
	337
	338	/* CLKCTR : Clock Control */
	339	#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000)
	340	#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000)
	341	#define TX4938_CLKCTR_ETH1CKD 0x80000000
	342	#define TX4938_CLKCTR_ETH0CKD 0x40000000
	343	#define TX4938_CLKCTR_SPICKD 0x20000000
	344	#define TX4938_CLKCTR_SRAMCKD 0x10000000
	345	#define TX4938_CLKCTR_PCIC1CKD 0x08000000
	346	#define TX4938_CLKCTR_DMA1CKD 0x04000000
	347	#define TX4938_CLKCTR_ACLCKD 0x02000000
	348	#define TX4938_CLKCTR_PIOCKD 0x01000000
	349	#define TX4938_CLKCTR_DMACKD 0x00800000
	350	#define TX4938_CLKCTR_PCICKD 0x00400000
	351	#define TX4938_CLKCTR_TM0CKD 0x00100000
	352	#define TX4938_CLKCTR_TM1CKD 0x00080000
	353	#define TX4938_CLKCTR_TM2CKD 0x00040000
	354	#define TX4938_CLKCTR_SIO0CKD 0x00020000
	355	#define TX4938_CLKCTR_SIO1CKD 0x00010000
	356	#define TX4938_CLKCTR_ETH1RST 0x00008000
	357	#define TX4938_CLKCTR_ETH0RST 0x00004000
	358	#define TX4938_CLKCTR_SPIRST 0x00002000
	359	#define TX4938_CLKCTR_SRAMRST 0x00001000
	360	#define TX4938_CLKCTR_PCIC1RST 0x00000800
	361	#define TX4938_CLKCTR_DMA1RST 0x00000400
	362	#define TX4938_CLKCTR_ACLRST 0x00000200
	363	#define TX4938_CLKCTR_PIORST 0x00000100
	364	#define TX4938_CLKCTR_DMARST 0x00000080
	365	#define TX4938_CLKCTR_PCIRST 0x00000040
	366	#define TX4938_CLKCTR_TM0RST 0x00000010
	367	#define TX4938_CLKCTR_TM1RST 0x00000008
	368	#define TX4938_CLKCTR_TM2RST 0x00000004
	369	#define TX4938_CLKCTR_SIO0RST 0x00000002
	370	#define TX4938_CLKCTR_SIO1RST 0x00000001
	371
	372	/*
	373	* DMA
	374	*/
	375	/* bits for MCR */
	376	#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
	377	#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
	378	#define TX4938_DMA_MCR_RSFIF 0x00000080
	379	#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
	380	#define TX4938_DMA_MCR_RPRT 0x00000002
	381	#define TX4938_DMA_MCR_MSTEN 0x00000001
	382
	383	/* bits for CCRn */
	384	#define TX4938_DMA_CCR_IMMCHN 0x20000000
	385	#define TX4938_DMA_CCR_USEXFSZ 0x10000000
	386	#define TX4938_DMA_CCR_LE 0x08000000
	387	#define TX4938_DMA_CCR_DBINH 0x04000000
	388	#define TX4938_DMA_CCR_SBINH 0x02000000
	389	#define TX4938_DMA_CCR_CHRST 0x01000000
	390	#define TX4938_DMA_CCR_RVBYTE 0x00800000
	391	#define TX4938_DMA_CCR_ACKPOL 0x00400000
	392	#define TX4938_DMA_CCR_REQPL 0x00200000
	393	#define TX4938_DMA_CCR_EGREQ 0x00100000
	394	#define TX4938_DMA_CCR_CHDN 0x00080000
	395	#define TX4938_DMA_CCR_DNCTL 0x00060000
	396	#define TX4938_DMA_CCR_EXTRQ 0x00010000
	397	#define TX4938_DMA_CCR_INTRQD 0x0000e000
	398	#define TX4938_DMA_CCR_INTENE 0x00001000
	399	#define TX4938_DMA_CCR_INTENC 0x00000800
	400	#define TX4938_DMA_CCR_INTENT 0x00000400
	401	#define TX4938_DMA_CCR_CHNEN 0x00000200
	402	#define TX4938_DMA_CCR_XFACT 0x00000100
	403	#define TX4938_DMA_CCR_SMPCHN 0x00000020
	404	#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
	405	#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
	406	#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
	407	#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
	408	#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
	409	#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
	410	#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
	411	#define TX4938_DMA_CCR_MEMIO 0x00000002
	412	#define TX4938_DMA_CCR_SNGAD 0x00000001
	413
	414	/* bits for CSRn */
	415	#define TX4938_DMA_CSR_CHNEN 0x00000400
	416	#define TX4938_DMA_CSR_STLXFER 0x00000200
	417	#define TX4938_DMA_CSR_CHNACT 0x00000100
	418	#define TX4938_DMA_CSR_ABCHC 0x00000080
	419	#define TX4938_DMA_CSR_NCHNC 0x00000040
	420	#define TX4938_DMA_CSR_NTRNFC 0x00000020
	421	#define TX4938_DMA_CSR_EXTDN 0x00000010
	422	#define TX4938_DMA_CSR_CFERR 0x00000008
	423	#define TX4938_DMA_CSR_CHERR 0x00000004
	424	#define TX4938_DMA_CSR_DESERR 0x00000002
	425	#define TX4938_DMA_CSR_SORERR 0x00000001
	426
	427	#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
	428	#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
	429	#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
	430	#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
	431	#define tx4938_pcicptr tx4927_pcicptr
	432	#define tx4938_pcic1ptr \
	433	((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
	434	#define tx4938_ccfgptr \
	435	((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
	436	#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
	437	#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
	438	#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
	439	#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
	440	#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
	441
	442
	443	#define TX4938_REV_PCODE() \
	444	((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
	445
	446	#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
	447	#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
	448	#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
	449
	450	#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
	451	#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
	452
	453	#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
	454	#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
	455	#define TX4938_EBUSC_SIZE(ch) \
	456	(0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
	457
	458	int tx4938_report_pciclk(void);
	459	void tx4938_report_pci1clk(void);
	460	int tx4938_pciclk66_setup(void);
	461	struct pci_dev;
	462	int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
	463	void tx4938_irq_init(void);
	464
	465	#endif