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diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
deleted file mode 100644
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--- a/include/asm-mips/txx9/tx4927.h
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1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_TX4927_H
28#define __ASM_TXX9_TX4927_H
29
30#include <linux/types.h>
31#include <linux/io.h>
32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h>
34
35#ifdef CONFIG_64BIT
36#define TX4927_REG_BASE 0xffffffffff1f0000UL
37#else
38#define TX4927_REG_BASE 0xff1f0000UL
39#endif
40#define TX4927_REG_SIZE 0x00010000
41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
47#define TX4927_NR_TMR 3
48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
49#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
52
53#define TX4927_IR_INT(n) (2 + (n))
54#define TX4927_IR_SIO(n) (8 + (n))
55#define TX4927_IR_PCIC 16
56#define TX4927_NUM_IR_TMR 3
57#define TX4927_IR_TMR(n) (17 + (n))
58#define TX4927_IR_PCIERR 22
59#define TX4927_NUM_IR 32
60
61#define TX4927_IRC_INT 2 /* IP[2] in Status register */
62
63#define TX4927_NUM_PIO 16
64
65struct tx4927_sdramc_reg {
66 u64 cr[4];
67 u64 unused0[4];
68 u64 tr;
69 u64 unused1[2];
70 u64 cmd;
71};
72
73struct tx4927_ebusc_reg {
74 u64 cr[8];
75};
76
77struct tx4927_ccfg_reg {
78 u64 ccfg;
79 u64 crir;
80 u64 pcfg;
81 u64 toea;
82 u64 clkctr;
83 u64 unused0;
84 u64 garbc;
85 u64 unused1;
86 u64 unused2;
87 u64 ramp;
88};
89
90/*
91 * CCFG
92 */
93/* CCFG : Chip Configuration */
94#define TX4927_CCFG_WDRST 0x0000020000000000ULL
95#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
96#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
97#define TX4927_CCFG_TINTDIS 0x01000000
98#define TX4927_CCFG_PCI66 0x00800000
99#define TX4927_CCFG_PCIMODE 0x00400000
100#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
101#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
102#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
103#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
104#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
105#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
106#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
107#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
108#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
109#define TX4927_CCFG_BEOW 0x00010000
110#define TX4927_CCFG_WR 0x00008000
111#define TX4927_CCFG_TOE 0x00004000
112#define TX4927_CCFG_PCIARB 0x00002000
113#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
114#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
115#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
116#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
117#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
118#define TX4927_CCFG_SYSSP_MASK 0x000000c0
119#define TX4927_CCFG_ENDIAN 0x00000004
120#define TX4927_CCFG_HALT 0x00000002
121#define TX4927_CCFG_ACEHOLD 0x00000001
122#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
123
124/* PCFG : Pin Configuration */
125#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
126#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
127#define TX4927_PCFG_SYSCLKEN 0x08000000
128#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
129#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
130#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
131#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
132#define TX4927_PCFG_SEL2 0x00000200
133#define TX4927_PCFG_SEL1 0x00000100
134#define TX4927_PCFG_DMASEL_ALL 0x000000ff
135#define TX4927_PCFG_DMASEL0_MASK 0x00000003
136#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
137#define TX4927_PCFG_DMASEL2_MASK 0x00000030
138#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
139#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
140#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
141#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
142#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
143#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
144#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
145#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
146#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
147#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
148#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
149#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
150#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
151#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
152#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
153#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
154#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
155#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
156
157/* CLKCTR : Clock Control */
158#define TX4927_CLKCTR_ACLCKD 0x02000000
159#define TX4927_CLKCTR_PIOCKD 0x01000000
160#define TX4927_CLKCTR_DMACKD 0x00800000
161#define TX4927_CLKCTR_PCICKD 0x00400000
162#define TX4927_CLKCTR_TM0CKD 0x00100000
163#define TX4927_CLKCTR_TM1CKD 0x00080000
164#define TX4927_CLKCTR_TM2CKD 0x00040000
165#define TX4927_CLKCTR_SIO0CKD 0x00020000
166#define TX4927_CLKCTR_SIO1CKD 0x00010000
167#define TX4927_CLKCTR_ACLRST 0x00000200
168#define TX4927_CLKCTR_PIORST 0x00000100
169#define TX4927_CLKCTR_DMARST 0x00000080
170#define TX4927_CLKCTR_PCIRST 0x00000040
171#define TX4927_CLKCTR_TM0RST 0x00000010
172#define TX4927_CLKCTR_TM1RST 0x00000008
173#define TX4927_CLKCTR_TM2RST 0x00000004
174#define TX4927_CLKCTR_SIO0RST 0x00000002
175#define TX4927_CLKCTR_SIO1RST 0x00000001
176
177#define tx4927_sdramcptr \
178 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
179#define tx4927_pcicptr \
180 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
181#define tx4927_ccfgptr \
182 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
183#define tx4927_ebuscptr \
184 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
185#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
186
187#define TX4927_REV_PCODE() \
188 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
189
190#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
191#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
192#define TX4927_SDRAMC_SIZE(ch) \
193 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
194
195#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
196#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
197#define TX4927_EBUSC_SIZE(ch) \
198 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
199
200/* utilities */
201static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
202{
203#ifdef CONFIG_32BIT
204 unsigned long flags;
205 local_irq_save(flags);
206#endif
207 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
208#ifdef CONFIG_32BIT
209 local_irq_restore(flags);
210#endif
211}
212static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
213{
214#ifdef CONFIG_32BIT
215 unsigned long flags;
216 local_irq_save(flags);
217#endif
218 ____raw_writeq(____raw_readq(adr) | bits, adr);
219#ifdef CONFIG_32BIT
220 local_irq_restore(flags);
221#endif
222}
223
224/* These functions are not interrupt safe. */
225static inline void tx4927_ccfg_clear(__u64 bits)
226{
227 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
228 & ~(TX4927_CCFG_W1CBITS | bits),
229 &tx4927_ccfgptr->ccfg);
230}
231static inline void tx4927_ccfg_set(__u64 bits)
232{
233 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
234 & ~TX4927_CCFG_W1CBITS) | bits,
235 &tx4927_ccfgptr->ccfg);
236}
237static inline void tx4927_ccfg_change(__u64 change, __u64 new)
238{
239 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
240 & ~(TX4927_CCFG_W1CBITS | change)) |
241 new,
242 &tx4927_ccfgptr->ccfg);
243}
244
245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdt_init(void);
247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
250int tx4927_report_pciclk(void);
251int tx4927_pciclk66_setup(void);
252void tx4927_setup_pcierr_irq(void);
253void tx4927_irq_init(void);
254
255#endif /* __ASM_TXX9_TX4927_H */
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