diff options
Diffstat (limited to 'include/asm-mips/txx9/rbtx4927.h')
-rw-r--r-- | include/asm-mips/txx9/rbtx4927.h | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index bf194589216f..6fcec912c143 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h | |||
@@ -34,7 +34,23 @@ | |||
34 | #define RBTX4927_PCIIO 0x16000000 | 34 | #define RBTX4927_PCIIO 0x16000000 |
35 | #define RBTX4927_PCIIO_SIZE 0x01000000 | 35 | #define RBTX4927_PCIIO_SIZE 0x01000000 |
36 | 36 | ||
37 | #define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) | 37 | #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) |
38 | #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) | ||
39 | #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) | ||
40 | #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) | ||
41 | #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) | ||
42 | #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) | ||
43 | #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) | ||
44 | |||
45 | /* Ethernet port address */ | ||
46 | #define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280) | ||
47 | |||
48 | #define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) | ||
49 | #define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) | ||
50 | #define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) | ||
51 | #define rbtx4927_softresetlock_addr \ | ||
52 | ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) | ||
53 | #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) | ||
38 | 54 | ||
39 | /* bits for ISTAT/IMASK/IMSTAT */ | 55 | /* bits for ISTAT/IMASK/IMSTAT */ |
40 | #define RBTX4927_INTB_PCID 0 | 56 | #define RBTX4927_INTB_PCID 0 |
@@ -62,13 +78,7 @@ | |||
62 | #define RBTX4927_ISA_IO_OFFSET 0 | 78 | #define RBTX4927_ISA_IO_OFFSET 0 |
63 | #endif | 79 | #endif |
64 | 80 | ||
65 | #define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL | 81 | #define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base) |
66 | #define RBTX4927_SW_RESET_DO_SET 0x01 | ||
67 | |||
68 | #define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL | ||
69 | #define RBTX4927_SW_RESET_ENABLE_SET 0x01 | ||
70 | |||
71 | #define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) | ||
72 | #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) | 82 | #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) |
73 | 83 | ||
74 | void rbtx4927_prom_init(void); | 84 | void rbtx4927_prom_init(void); |