diff options
Diffstat (limited to 'include/asm-mips/tx4927/tx4927.h')
| -rw-r--r-- | include/asm-mips/tx4927/tx4927.h | 439 |
1 files changed, 0 insertions, 439 deletions
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 4bd4368e188c..193e80a17c12 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h | |||
| @@ -27,447 +27,8 @@ | |||
| 27 | #ifndef __ASM_TX4927_TX4927_H | 27 | #ifndef __ASM_TX4927_TX4927_H |
| 28 | #define __ASM_TX4927_TX4927_H | 28 | #define __ASM_TX4927_TX4927_H |
| 29 | 29 | ||
| 30 | #include <asm/tx4927/tx4927_mips.h> | ||
| 31 | #include <asm/txx9irq.h> | 30 | #include <asm/txx9irq.h> |
| 32 | 31 | ||
| 33 | /* | ||
| 34 | This register naming came from the integrated CPU/controller name TX4927 | ||
| 35 | followed by the device name from table 4.2.2 on page 4-3 and then followed | ||
| 36 | by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul | ||
| 37 | used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define TX4927_SIO_0_BASE | ||
| 41 | |||
| 42 | /* TX4927 controller */ | ||
| 43 | #define TX4927_BASE 0xfff1f0000 | ||
| 44 | #define TX4927_BASE 0xfff1f0000 | ||
| 45 | #define TX4927_LIMIT 0xfff1fffff | ||
| 46 | |||
| 47 | |||
| 48 | /* TX4927 SDRAM controller (64-bit registers) */ | ||
| 49 | #define TX4927_SDRAMC_BASE 0x8000 | ||
| 50 | #define TX4927_SDRAMC_SDCCR0 0x8000 | ||
| 51 | #define TX4927_SDRAMC_SDCCR1 0x8008 | ||
| 52 | #define TX4927_SDRAMC_SDCCR2 0x8010 | ||
| 53 | #define TX4927_SDRAMC_SDCCR3 0x8018 | ||
| 54 | #define TX4927_SDRAMC_SDCTR 0x8040 | ||
| 55 | #define TX4927_SDRAMC_SDCMD 0x8058 | ||
| 56 | #define TX4927_SDRAMC_LIMIT 0x8fff | ||
| 57 | |||
| 58 | |||
| 59 | /* TX4927 external bus controller (64-bit registers) */ | ||
| 60 | #define TX4927_EBUSC_BASE 0x9000 | ||
| 61 | #define TX4927_EBUSC_EBCCR0 0x9000 | ||
| 62 | #define TX4927_EBUSC_EBCCR1 0x9008 | ||
| 63 | #define TX4927_EBUSC_EBCCR2 0x9010 | ||
| 64 | #define TX4927_EBUSC_EBCCR3 0x9018 | ||
| 65 | #define TX4927_EBUSC_EBCCR4 0x9020 | ||
| 66 | #define TX4927_EBUSC_EBCCR5 0x9028 | ||
| 67 | #define TX4927_EBUSC_EBCCR6 0x9030 | ||
| 68 | #define TX4927_EBUSC_EBCCR7 0x9008 | ||
| 69 | #define TX4927_EBUSC_LIMIT 0x9fff | ||
| 70 | |||
| 71 | |||
| 72 | /* TX4927 SDRRAM Error Check Correction (64-bit registers) */ | ||
| 73 | #define TX4927_ECC_BASE 0xa000 | ||
| 74 | #define TX4927_ECC_ECCCR 0xa000 | ||
| 75 | #define TX4927_ECC_ECCSR 0xa008 | ||
| 76 | #define TX4927_ECC_LIMIT 0xafff | ||
| 77 | |||
| 78 | |||
| 79 | /* TX4927 DMA Controller (64-bit registers) */ | ||
| 80 | #define TX4927_DMAC_BASE 0xb000 | ||
| 81 | #define TX4927_DMAC_TBD 0xb000 | ||
| 82 | #define TX4927_DMAC_LIMIT 0xbfff | ||
| 83 | |||
| 84 | |||
| 85 | /* TX4927 PCI Controller (32-bit registers) */ | ||
| 86 | #define TX4927_PCIC_BASE 0xd000 | ||
| 87 | #define TX4927_PCIC_TBD 0xb000 | ||
| 88 | #define TX4927_PCIC_LIMIT 0xdfff | ||
| 89 | |||
| 90 | |||
| 91 | /* TX4927 Configuration registers (64-bit registers) */ | ||
| 92 | #define TX4927_CONFIG_BASE 0xe000 | ||
| 93 | #define TX4927_CONFIG_CCFG 0xe000 | ||
| 94 | #define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 | ||
| 95 | #define TX4927_CONFIG_CCFG_WDRST BM_41_41 | ||
| 96 | #define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 | ||
| 97 | #define TX4927_CONFIG_CCFG_BCFG BM_39_32 | ||
| 98 | #define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 | ||
| 99 | #define TX4927_CONFIG_CCFG_GTOT BM_26_25 | ||
| 100 | #define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 | ||
| 101 | #define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 | ||
| 102 | #define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 | ||
| 103 | #define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) | ||
| 104 | #define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 | ||
| 105 | #define TX4927_CONFIG_CCFG_PCI66 BM_23_23 | ||
| 106 | #define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 | ||
| 107 | #define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 | ||
| 108 | #define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 | ||
| 109 | #define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 | ||
| 110 | #define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) | ||
| 111 | #define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 | ||
| 112 | #define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 | ||
| 113 | #define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) | ||
| 114 | #define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 | ||
| 115 | #define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 | ||
| 116 | #define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 | ||
| 117 | #define TX4927_CONFIG_CCFG_BEOW BM_16_16 | ||
| 118 | #define TX4927_CONFIG_CCFG_WR BM_15_15 | ||
| 119 | #define TX4927_CONFIG_CCFG_TOE BM_14_14 | ||
| 120 | #define TX4927_CONFIG_CCFG_PCIARB BM_13_13 | ||
| 121 | #define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 | ||
| 122 | #define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 | ||
| 123 | #define TX4927_CONFIG_CCFG_SYSSP BM_07_06 | ||
| 124 | #define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 | ||
| 125 | #define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 | ||
| 126 | #define TX4927_CONFIG_CCFG_ARMODE BM_01_01 | ||
| 127 | #define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 | ||
| 128 | #define TX4927_CONFIG_REVID 0xe008 | ||
| 129 | #define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 | ||
| 130 | #define TX4927_CONFIG_REVID_PCODE BM_16_31 | ||
| 131 | #define TX4927_CONFIG_REVID_MJERREV BM_12_15 | ||
| 132 | #define TX4927_CONFIG_REVID_MINEREV BM_08_11 | ||
| 133 | #define TX4927_CONFIG_REVID_MJREV BM_04_07 | ||
| 134 | #define TX4927_CONFIG_REVID_MINREV BM_00_03 | ||
| 135 | #define TX4927_CONFIG_PCFG 0xe010 | ||
| 136 | #define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 | ||
| 137 | #define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 | ||
| 138 | #define TX4927_CONFIG_PCFG_DRVCB BM_55_55 | ||
| 139 | #define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 | ||
| 140 | #define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 | ||
| 141 | #define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 | ||
| 142 | #define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 | ||
| 143 | #define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 | ||
| 144 | #define TX4927_CONFIG_PCFG_DRVWE BM_49_49 | ||
| 145 | #define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 | ||
| 146 | #define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 | ||
| 147 | #define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k | ||
| 148 | #define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 | ||
| 149 | #define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 | ||
| 150 | #define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 | ||
| 151 | #define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 | ||
| 152 | #define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 | ||
| 153 | #define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 | ||
| 154 | #define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 | ||
| 155 | #define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 | ||
| 156 | #define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 | ||
| 157 | #define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 | ||
| 158 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) | ||
| 159 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 | ||
| 160 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 | ||
| 161 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 | ||
| 162 | #define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 | ||
| 163 | #define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 | ||
| 164 | #define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 | ||
| 165 | #define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 | ||
| 166 | #define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 | ||
| 167 | #define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 | ||
| 168 | #define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 | ||
| 169 | #define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 | ||
| 170 | #define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 | ||
| 171 | #define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 | ||
| 172 | #define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 | ||
| 173 | #define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 | ||
| 174 | #define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 | ||
| 175 | #define TX4927_CONFIG_PCFG_SEL2 BM_09_09 | ||
| 176 | #define TX4927_CONFIG_PCFG_SEL1 BM_08_08 | ||
| 177 | #define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 | ||
| 178 | #define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) | ||
| 179 | #define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 | ||
| 180 | #define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 | ||
| 181 | #define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 | ||
| 182 | #define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 | ||
| 183 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) | ||
| 184 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 | ||
| 185 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 | ||
| 186 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 | ||
| 187 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) | ||
| 188 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 | ||
| 189 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 | ||
| 190 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 | ||
| 191 | #define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 | ||
| 192 | #define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) | ||
| 193 | #define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 | ||
| 194 | #define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 | ||
| 195 | #define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 | ||
| 196 | #define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 | ||
| 197 | #define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) | ||
| 198 | #define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 | ||
| 199 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 | ||
| 200 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 | ||
| 201 | #define TX4927_CONFIG_TOEA 0xe018 | ||
| 202 | #define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 | ||
| 203 | #define TX4927_CONFIG_TOEA_TOEA BM_00_35 | ||
| 204 | #define TX4927_CONFIG_CLKCTR 0xe020 | ||
| 205 | #define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 | ||
| 206 | #define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 | ||
| 207 | #define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 | ||
| 208 | #define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 | ||
| 209 | #define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 | ||
| 210 | #define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 | ||
| 211 | #define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 | ||
| 212 | #define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 | ||
| 213 | #define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 | ||
| 214 | #define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 | ||
| 215 | #define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 | ||
| 216 | #define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 | ||
| 217 | #define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 | ||
| 218 | #define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 | ||
| 219 | #define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 | ||
| 220 | #define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 | ||
| 221 | #define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 | ||
| 222 | #define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 | ||
| 223 | #define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 | ||
| 224 | #define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 | ||
| 225 | #define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 | ||
| 226 | #define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 | ||
| 227 | #define TX4927_CONFIG_GARBC 0xe030 | ||
| 228 | #define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 | ||
| 229 | #define TX4927_CONFIG_GARBC_SET_09 BM_09_09 | ||
| 230 | #define TX4927_CONFIG_GARBC_ARBMD BM_08_08 | ||
| 231 | #define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 | ||
| 232 | #define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 | ||
| 233 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) | ||
| 234 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 | ||
| 235 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 | ||
| 236 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 | ||
| 237 | #define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 | ||
| 238 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) | ||
| 239 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 | ||
| 240 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 | ||
| 241 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 | ||
| 242 | #define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 | ||
| 243 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) | ||
| 244 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 | ||
| 245 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 | ||
| 246 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 | ||
| 247 | #define TX4927_CONFIG_RAMP 0xe048 | ||
| 248 | #define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 | ||
| 249 | #define TX4927_CONFIG_RAMP_RAMP BM_00_19 | ||
| 250 | #define TX4927_CONFIG_LIMIT 0xefff | ||
| 251 | |||
| 252 | |||
| 253 | /* TX4927 Timer 0 (32-bit registers) */ | ||
| 254 | #define TX4927_TMR0_BASE 0xf000 | ||
| 255 | #define TX4927_TMR0_TMTCR0 0xf000 | ||
| 256 | #define TX4927_TMR0_TMTISR0 0xf004 | ||
| 257 | #define TX4927_TMR0_TMCPRA0 0xf008 | ||
| 258 | #define TX4927_TMR0_TMCPRB0 0xf00c | ||
| 259 | #define TX4927_TMR0_TMITMR0 0xf010 | ||
| 260 | #define TX4927_TMR0_TMCCDR0 0xf020 | ||
| 261 | #define TX4927_TMR0_TMPGMR0 0xf030 | ||
| 262 | #define TX4927_TMR0_TMTRR0 0xf0f0 | ||
| 263 | #define TX4927_TMR0_LIMIT 0xf0ff | ||
| 264 | |||
| 265 | |||
| 266 | /* TX4927 Timer 1 (32-bit registers) */ | ||
| 267 | #define TX4927_TMR1_BASE 0xf100 | ||
| 268 | #define TX4927_TMR1_TMTCR1 0xf100 | ||
| 269 | #define TX4927_TMR1_TMTISR1 0xf104 | ||
| 270 | #define TX4927_TMR1_TMCPRA1 0xf108 | ||
| 271 | #define TX4927_TMR1_TMCPRB1 0xf10c | ||
| 272 | #define TX4927_TMR1_TMITMR1 0xf110 | ||
| 273 | #define TX4927_TMR1_TMCCDR1 0xf120 | ||
| 274 | #define TX4927_TMR1_TMPGMR1 0xf130 | ||
| 275 | #define TX4927_TMR1_TMTRR1 0xf1f0 | ||
| 276 | #define TX4927_TMR1_LIMIT 0xf1ff | ||
| 277 | |||
| 278 | |||
| 279 | /* TX4927 Timer 2 (32-bit registers) */ | ||
| 280 | #define TX4927_TMR2_BASE 0xf200 | ||
| 281 | #define TX4927_TMR2_TMTCR2 0xf200 | ||
| 282 | #define TX4927_TMR2_TMTISR2 0xf204 | ||
| 283 | #define TX4927_TMR2_TMCPRA2 0xf208 | ||
| 284 | #define TX4927_TMR2_TMITMR2 0xf210 | ||
| 285 | #define TX4927_TMR2_TMCCDR2 0xf220 | ||
| 286 | #define TX4927_TMR2_TMWTMR2 0xf240 | ||
| 287 | #define TX4927_TMR2_TMTRR2 0xf2f0 | ||
| 288 | #define TX4927_TMR2_LIMIT 0xf2ff | ||
| 289 | |||
| 290 | |||
| 291 | /* TX4927 serial port 0 (32-bit registers) */ | ||
| 292 | #define TX4927_SIO0_BASE 0xf300 | ||
| 293 | #define TX4927_SIO0_SILCR0 0xf300 | ||
| 294 | #define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 | ||
| 295 | #define TX4927_SIO0_SILCR0_RWUB BM_15_15 | ||
| 296 | #define TX4927_SIO0_SILCR0_TWUB BM_14_14 | ||
| 297 | #define TX4927_SIO0_SILCR0_UODE BM_13_13 | ||
| 298 | #define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 | ||
| 299 | #define TX4927_SIO0_SILCR0_SCS BM_05_06 | ||
| 300 | #define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) | ||
| 301 | #define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 | ||
| 302 | #define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 | ||
| 303 | #define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 | ||
| 304 | #define TX4927_SIO0_SILCR0_UEPS BM_04_04 | ||
| 305 | #define TX4927_SIO0_SILCR0_UPEN BM_03_03 | ||
| 306 | #define TX4927_SIO0_SILCR0_USBL BM_02_02 | ||
| 307 | #define TX4927_SIO0_SILCR0_UMODE BM_00_01 | ||
| 308 | #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 | ||
| 309 | #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) | ||
| 310 | #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 | ||
| 311 | #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 | ||
| 312 | #define TX4927_SIO0_SIDICR0 0xf304 | ||
| 313 | #define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 | ||
| 314 | #define TX4927_SIO0_SIDICR0_TDE BM_15_15 | ||
| 315 | #define TX4927_SIO0_SIDICR0_RDE BM_14_14 | ||
| 316 | #define TX4927_SIO0_SIDICR0_TIE BM_13_13 | ||
| 317 | #define TX4927_SIO0_SIDICR0_RIE BM_12_12 | ||
| 318 | #define TX4927_SIO0_SIDICR0_SPIE BM_11_11 | ||
| 319 | #define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 | ||
| 320 | #define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) | ||
| 321 | #define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 | ||
| 322 | #define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 | ||
| 323 | #define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 | ||
| 324 | #define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 | ||
| 325 | #define TX4927_SIO0_SIDICR0_STIE BM_00_05 | ||
| 326 | #define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) | ||
| 327 | #define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 | ||
| 328 | #define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 | ||
| 329 | #define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 | ||
| 330 | #define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 | ||
| 331 | #define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 | ||
| 332 | #define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 | ||
| 333 | #define TX4927_SIO0_SIDISR0 0xf308 | ||
| 334 | #define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 | ||
| 335 | #define TX4927_SIO0_SIDISR0_UBRK BM_15_15 | ||
| 336 | #define TX4927_SIO0_SIDISR0_UVALID BM_14_14 | ||
| 337 | #define TX4927_SIO0_SIDISR0_UFER BM_13_13 | ||
| 338 | #define TX4927_SIO0_SIDISR0_UPER BM_12_12 | ||
| 339 | #define TX4927_SIO0_SIDISR0_UOER BM_11_11 | ||
| 340 | #define TX4927_SIO0_SIDISR0_ERI BM_10_10 | ||
| 341 | #define TX4927_SIO0_SIDISR0_TOUT BM_09_09 | ||
| 342 | #define TX4927_SIO0_SIDISR0_TDIS BM_08_08 | ||
| 343 | #define TX4927_SIO0_SIDISR0_RDIS BM_07_07 | ||
| 344 | #define TX4927_SIO0_SIDISR0_STIS BM_06_06 | ||
| 345 | #define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 | ||
| 346 | #define TX4927_SIO0_SIDISR0_RFDN BM_00_04 | ||
| 347 | #define TX4927_SIO0_SISCISR0 0xf30c | ||
| 348 | #define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 | ||
| 349 | #define TX4927_SIO0_SISCISR0_OERS BM_05_05 | ||
| 350 | #define TX4927_SIO0_SISCISR0_CTSS BM_04_04 | ||
| 351 | #define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 | ||
| 352 | #define TX4927_SIO0_SISCISR0_TRDY BM_02_02 | ||
| 353 | #define TX4927_SIO0_SISCISR0_TXALS BM_01_01 | ||
| 354 | #define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 | ||
| 355 | #define TX4927_SIO0_SIFCR0 0xf310 | ||
| 356 | #define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 | ||
| 357 | #define TX4927_SIO0_SIFCR0_SWRST BM_16_31 | ||
| 358 | #define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 | ||
| 359 | #define TX4927_SIO0_SIFCR0_RDIL BM_16_31 | ||
| 360 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) | ||
| 361 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 | ||
| 362 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 | ||
| 363 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 | ||
| 364 | #define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 | ||
| 365 | #define TX4927_SIO0_SIFCR0_TDIL BM_03_04 | ||
| 366 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) | ||
| 367 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 | ||
| 368 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 | ||
| 369 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 | ||
| 370 | #define TX4927_SIO0_SIFCR0_TFRST BM_02_02 | ||
| 371 | #define TX4927_SIO0_SIFCR0_RFRST BM_01_01 | ||
| 372 | #define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 | ||
| 373 | #define TX4927_SIO0_SIFLCR0 0xf314 | ||
| 374 | #define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 | ||
| 375 | #define TX4927_SIO0_SIFLCR0_RCS BM_12_12 | ||
| 376 | #define TX4927_SIO0_SIFLCR0_TES BM_11_11 | ||
| 377 | #define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 | ||
| 378 | #define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 | ||
| 379 | #define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 | ||
| 380 | #define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 | ||
| 381 | #define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 | ||
| 382 | #define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 | ||
| 383 | #define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 | ||
| 384 | #define TX4927_SIO0_SIBGR0 0xf318 | ||
| 385 | #define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 | ||
| 386 | #define TX4927_SIO0_SIBGR0_BCLK BM_08_09 | ||
| 387 | #define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) | ||
| 388 | #define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 | ||
| 389 | #define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 | ||
| 390 | #define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 | ||
| 391 | #define TX4927_SIO0_SIBGR0_BRD BM_00_07 | ||
| 392 | #define TX4927_SIO0_SITFIF00 0xf31c | ||
| 393 | #define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 | ||
| 394 | #define TX4927_SIO0_SITFIF00_TXD BM_00_07 | ||
| 395 | #define TX4927_SIO0_SIRFIFO0 0xf320 | ||
| 396 | #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 | ||
| 397 | #define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 | ||
| 398 | #define TX4927_SIO0_SIRFIFO0 0xf320 | ||
| 399 | #define TX4927_SIO0_LIMIT 0xf3ff | ||
| 400 | |||
| 401 | |||
| 402 | /* TX4927 serial port 1 (32-bit registers) */ | ||
| 403 | #define TX4927_SIO1_BASE 0xf400 | ||
| 404 | #define TX4927_SIO1_SILCR1 0xf400 | ||
| 405 | #define TX4927_SIO1_SIDICR1 0xf404 | ||
| 406 | #define TX4927_SIO1_SIDISR1 0xf408 | ||
| 407 | #define TX4927_SIO1_SISCISR1 0xf40c | ||
| 408 | #define TX4927_SIO1_SIFCR1 0xf410 | ||
| 409 | #define TX4927_SIO1_SIFLCR1 0xf414 | ||
| 410 | #define TX4927_SIO1_SIBGR1 0xf418 | ||
| 411 | #define TX4927_SIO1_SITFIF01 0xf41c | ||
| 412 | #define TX4927_SIO1_SIRFIFO1 0xf420 | ||
| 413 | #define TX4927_SIO1_LIMIT 0xf4ff | ||
| 414 | |||
| 415 | |||
| 416 | /* TX4927 parallel port (32-bit registers) */ | ||
| 417 | #define TX4927_PIO_BASE 0xf500 | ||
| 418 | #define TX4927_PIO_PIOD0 0xf500 | ||
| 419 | #define TX4927_PIO_PIODI 0xf504 | ||
| 420 | #define TX4927_PIO_PIODIR 0xf508 | ||
| 421 | #define TX4927_PIO_PIOOD 0xf50c | ||
| 422 | #define TX4927_PIO_LIMIT 0xf50f | ||
| 423 | |||
| 424 | |||
| 425 | /* TX4927 AC-link controller (32-bit registers) */ | ||
| 426 | #define TX4927_ACLC_BASE 0xf700 | ||
| 427 | #define TX4927_ACLC_ACCTLEN 0xf700 | ||
| 428 | #define TX4927_ACLC_ACCTLDIS 0xf704 | ||
| 429 | #define TX4927_ACLC_ACREGACC 0xf708 | ||
| 430 | #define TX4927_ACLC_ACINTSTS 0xf710 | ||
| 431 | #define TX4927_ACLC_ACINTMSTS 0xf714 | ||
| 432 | #define TX4927_ACLC_ACINTEN 0xf718 | ||
| 433 | #define TX4927_ACLC_ACINTDIS 0xf71c | ||
| 434 | #define TX4927_ACLC_ACSEMAPH 0xf720 | ||
| 435 | #define TX4927_ACLC_ACGPIDAT 0xf740 | ||
| 436 | #define TX4927_ACLC_ACGPODAT 0xf744 | ||
| 437 | #define TX4927_ACLC_ACSLTEN 0xf748 | ||
| 438 | #define TX4927_ACLC_ACSLTDIS 0xf74c | ||
| 439 | #define TX4927_ACLC_ACFIFOSTS 0xf750 | ||
| 440 | #define TX4927_ACLC_ACDMASTS 0xf780 | ||
| 441 | #define TX4927_ACLC_ACDMASEL 0xf784 | ||
| 442 | #define TX4927_ACLC_ACAUDODAT 0xf7a0 | ||
| 443 | #define TX4927_ACLC_ACSURRDAT 0xf7a4 | ||
| 444 | #define TX4927_ACLC_ACCENTDAT 0xf7a8 | ||
| 445 | #define TX4927_ACLC_ACLFEDAT 0xf7ac | ||
| 446 | #define TX4927_ACLC_ACAUDIDAT 0xf7b0 | ||
| 447 | #define TX4927_ACLC_ACMODODAT 0xf7b8 | ||
| 448 | #define TX4927_ACLC_ACMODIDAT 0xf7bc | ||
| 449 | #define TX4927_ACLC_ACREVID 0xf7fc | ||
| 450 | #define TX4927_ACLC_LIMIT 0xf7ff | ||
| 451 | |||
| 452 | |||
| 453 | #define TX4927_REG(x) ((TX4927_BASE)+(x)) | ||
| 454 | |||
| 455 | #define TX4927_RD08( reg ) (*(vu08*)(reg)) | ||
| 456 | #define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) | ||
| 457 | |||
| 458 | #define TX4927_RD16( reg ) (*(vu16*)(reg)) | ||
| 459 | #define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) | ||
| 460 | |||
| 461 | #define TX4927_RD32( reg ) (*(vu32*)(reg)) | ||
| 462 | #define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) | ||
| 463 | |||
| 464 | #define TX4927_RD64( reg ) (*(vu64*)(reg)) | ||
| 465 | #define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) | ||
| 466 | |||
| 467 | #define TX4927_RD( reg ) TX4927_RD32( reg ) | ||
| 468 | #define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) | ||
| 469 | |||
| 470 | |||
| 471 | #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE | 32 | #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE |
| 472 | #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) | 33 | #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) |
| 473 | 34 | ||