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Diffstat (limited to 'include/asm-mips/tx4927/tx4927.h')
-rw-r--r--include/asm-mips/tx4927/tx4927.h49
1 files changed, 5 insertions, 44 deletions
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
28#define __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H
29 29
30#include <asm/tx4927/tx4927_mips.h> 30#include <asm/tx4927/tx4927_mips.h>
31#include <asm/txx9irq.h>
31 32
32/* 33/*
33 This register naming came from the integrated CPU/controller name TX4927 34 This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
421#define TX4927_PIO_LIMIT 0xf50f 422#define TX4927_PIO_LIMIT 0xf50f
422 423
423 424
424/* TX4927 Interrupt Controller (32-bit registers) */
425#define TX4927_IRC_BASE 0xf510
426#define TX4927_IRC_IRFLAG0 0xf510
427#define TX4927_IRC_IRFLAG1 0xf514
428#define TX4927_IRC_IRPOL 0xf518
429#define TX4927_IRC_IRRCNT 0xf51c
430#define TX4927_IRC_IRMASKINT 0xf520
431#define TX4927_IRC_IRMASKEXT 0xf524
432#define TX4927_IRC_IRDEN 0xf600
433#define TX4927_IRC_IRDM0 0xf604
434#define TX4927_IRC_IRDM1 0xf608
435#define TX4927_IRC_IRLVL0 0xf610
436#define TX4927_IRC_IRLVL1 0xf614
437#define TX4927_IRC_IRLVL2 0xf618
438#define TX4927_IRC_IRLVL3 0xf61c
439#define TX4927_IRC_IRLVL4 0xf620
440#define TX4927_IRC_IRLVL5 0xf624
441#define TX4927_IRC_IRLVL6 0xf628
442#define TX4927_IRC_IRLVL7 0xf62c
443#define TX4927_IRC_IRMSK 0xf640
444#define TX4927_IRC_IREDC 0xf660
445#define TX4927_IRC_IRPND 0xf680
446#define TX4927_IRC_IRCS 0xf6a0
447#define TX4927_IRC_LIMIT 0xf6ff
448
449
450/* TX4927 AC-link controller (32-bit registers) */ 425/* TX4927 AC-link controller (32-bit registers) */
451#define TX4927_ACLC_BASE 0xf700 426#define TX4927_ACLC_BASE 0xf700
452#define TX4927_ACLC_ACCTLEN 0xf700 427#define TX4927_ACLC_ACCTLEN 0xf700
@@ -493,25 +468,11 @@
493#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) 468#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
494 469
495 470
471#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
472#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
496 473
497 474#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
498 475#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
499#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
500#define MI8259_IRQ_ISA_RAW_END 15
501#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */
502#define TX4927_IRQ_CP0_RAW_END 7
503#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */
504#define TX4927_IRQ_PIC_RAW_END 31
505
506
507#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
508#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
509
510#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */
511#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */
512
513#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */
514#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */
515 476
516 477
517#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 478#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)