1 files changed, 8 insertions, 8 deletions
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 513aa5133830..158a4cd12e46 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -304,7 +304,7 @@
                mfc0    v0, CP0_TCSTATUS
                ori     v0, TCSTATUS_IXMT
                mtc0    v0, CP0_TCSTATUS
-                ehb
+                _ehb
                DMT     5                               # dmt a1
                jal     mips_ihb
 #endif /* CONFIG_MIPS_MT_SMTC */
@@ -325,14 +325,14 @@
 * restore TCStatus.IXMT.
 */
                LONG_L  v1, PT_TCSTATUS(sp)
-                ehb
+                _ehb
                mfc0    v0, CP0_TCSTATUS
                andi    v1, TCSTATUS_IXMT
                /* We know that TCStatua.IXMT should be set from above */
                xori    v0, v0, TCSTATUS_IXMT
                or      v0, v0, v1
                mtc0    v0, CP0_TCSTATUS
-                ehb
+                _ehb
                andi    a1, a1, VPECONTROL_TE
                beqz    a1, 1f
                emt
@@ -411,7 +411,7 @@
                /* Clear TKSU, leave IXMT */
                xori    t0, 0x00001800
                mtc0    t0, CP0_TCSTATUS
-                ehb
+                _ehb
                /* We need to leave the global IE bit set, but clear EXL...*/
                mfc0    t0, CP0_STATUS
                ori     t0, ST0_EXL | ST0_ERL
@@ -438,7 +438,7 @@
                 * and enable interrupts only for the
                 * current TC, using the TCStatus register.
                 */
-                ehb
+                _ehb
                mfc0    t0,CP0_TCSTATUS
                /* Fortunately CU 0 is in the same place in both registers */
                /* Set TCU0, TKSU (for later inversion) and IXMT */
@@ -447,7 +447,7 @@
                /* Clear TKSU *and* IXMT */
                xori    t0, 0x00001c00
                mtc0    t0, CP0_TCSTATUS
-                ehb
+                _ehb
                /* We need to leave the global IE bit set, but clear EXL...*/
                mfc0    t0, CP0_STATUS
                ori     t0, ST0_EXL
@@ -479,7 +479,7 @@
                andi    v1, v0, TCSTATUS_IXMT
                ori     v0, TCSTATUS_IXMT
                mtc0    v0, CP0_TCSTATUS
-                ehb
+                _ehb
                DMT     2                               # dmt   v0
                /*
                 * We don't know a priori if ra is "live"
@@ -495,7 +495,7 @@
                xori    t0, 0x1e
                mtc0    t0, CP0_STATUS
 #ifdef CONFIG_MIPS_MT_SMTC
-                ehb
+                _ehb
                andi    v0, v0, VPECONTROL_TE
                beqz    v0, 2f
                nop     /* delay slot */

diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 513aa5133830..158a4cd12e46 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h
@@ -304,7 +304,7 @@
304	mfc0 v0, CP0_TCSTATUS	304	mfc0 v0, CP0_TCSTATUS
305	ori v0, TCSTATUS_IXMT	305	ori v0, TCSTATUS_IXMT
306	mtc0 v0, CP0_TCSTATUS	306	mtc0 v0, CP0_TCSTATUS
307	ehb	307	_ehb
308	DMT 5 # dmt a1	308	DMT 5 # dmt a1
309	jal mips_ihb	309	jal mips_ihb
310	#endif /* CONFIG_MIPS_MT_SMTC */	310	#endif /* CONFIG_MIPS_MT_SMTC */
@@ -325,14 +325,14 @@
325	* restore TCStatus.IXMT.	325	* restore TCStatus.IXMT.
326	*/	326	*/
327	LONG_L v1, PT_TCSTATUS(sp)	327	LONG_L v1, PT_TCSTATUS(sp)
328	ehb	328	_ehb
329	mfc0 v0, CP0_TCSTATUS	329	mfc0 v0, CP0_TCSTATUS
330	andi v1, TCSTATUS_IXMT	330	andi v1, TCSTATUS_IXMT
331	/* We know that TCStatua.IXMT should be set from above */	331	/* We know that TCStatua.IXMT should be set from above */
332	xori v0, v0, TCSTATUS_IXMT	332	xori v0, v0, TCSTATUS_IXMT
333	or v0, v0, v1	333	or v0, v0, v1
334	mtc0 v0, CP0_TCSTATUS	334	mtc0 v0, CP0_TCSTATUS
335	ehb	335	_ehb
336	andi a1, a1, VPECONTROL_TE	336	andi a1, a1, VPECONTROL_TE
337	beqz a1, 1f	337	beqz a1, 1f
338	emt	338	emt
@@ -411,7 +411,7 @@
411	/* Clear TKSU, leave IXMT */	411	/* Clear TKSU, leave IXMT */
412	xori t0, 0x00001800	412	xori t0, 0x00001800
413	mtc0 t0, CP0_TCSTATUS	413	mtc0 t0, CP0_TCSTATUS
414	ehb	414	_ehb
415	/* We need to leave the global IE bit set, but clear EXL...*/	415	/* We need to leave the global IE bit set, but clear EXL...*/
416	mfc0 t0, CP0_STATUS	416	mfc0 t0, CP0_STATUS
417	ori t0, ST0_EXL \| ST0_ERL	417	ori t0, ST0_EXL \| ST0_ERL
@@ -438,7 +438,7 @@
438	* and enable interrupts only for the	438	* and enable interrupts only for the
439	* current TC, using the TCStatus register.	439	* current TC, using the TCStatus register.
440	*/	440	*/
441	ehb	441	_ehb
442	mfc0 t0,CP0_TCSTATUS	442	mfc0 t0,CP0_TCSTATUS
443	/* Fortunately CU 0 is in the same place in both registers */	443	/* Fortunately CU 0 is in the same place in both registers */
444	/* Set TCU0, TKSU (for later inversion) and IXMT */	444	/* Set TCU0, TKSU (for later inversion) and IXMT */
@@ -447,7 +447,7 @@
447	/* Clear TKSU and IXMT */	447	/* Clear TKSU and IXMT */
448	xori t0, 0x00001c00	448	xori t0, 0x00001c00
449	mtc0 t0, CP0_TCSTATUS	449	mtc0 t0, CP0_TCSTATUS
450	ehb	450	_ehb
451	/* We need to leave the global IE bit set, but clear EXL...*/	451	/* We need to leave the global IE bit set, but clear EXL...*/
452	mfc0 t0, CP0_STATUS	452	mfc0 t0, CP0_STATUS
453	ori t0, ST0_EXL	453	ori t0, ST0_EXL
@@ -479,7 +479,7 @@
479	andi v1, v0, TCSTATUS_IXMT	479	andi v1, v0, TCSTATUS_IXMT
480	ori v0, TCSTATUS_IXMT	480	ori v0, TCSTATUS_IXMT
481	mtc0 v0, CP0_TCSTATUS	481	mtc0 v0, CP0_TCSTATUS
482	ehb	482	_ehb
483	DMT 2 # dmt v0	483	DMT 2 # dmt v0
484	/*	484	/*
485	* We don't know a priori if ra is "live"	485	* We don't know a priori if ra is "live"
@@ -495,7 +495,7 @@
495	xori t0, 0x1e	495	xori t0, 0x1e
496	mtc0 t0, CP0_STATUS	496	mtc0 t0, CP0_STATUS
497	#ifdef CONFIG_MIPS_MT_SMTC	497	#ifdef CONFIG_MIPS_MT_SMTC
498	ehb	498	_ehb
499	andi v0, v0, VPECONTROL_TE	499	andi v0, v0, VPECONTROL_TE
500	beqz v0, 2f	500	beqz v0, 2f
501	nop /* delay slot */	501	nop /* delay slot */