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-rw-r--r--include/asm-mips/stackframe.h524
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diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
10 */
11#ifndef _ASM_STACKFRAME_H
12#define _ASM_STACKFRAME_H
13
14#include <linux/threads.h>
15
16#include <asm/asm.h>
17#include <asm/asmmacro.h>
18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h>
20
21/*
22 * For SMTC kernel, global IE should be left set, and interrupts
23 * controlled exclusively via IXMT.
24 */
25#ifdef CONFIG_MIPS_MT_SMTC
26#define STATMASK 0x1e
27#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
28#define STATMASK 0x3f
29#else
30#define STATMASK 0x1f
31#endif
32
33#ifdef CONFIG_MIPS_MT_SMTC
34#include <asm/mipsmtregs.h>
35#endif /* CONFIG_MIPS_MT_SMTC */
36
37 .macro SAVE_AT
38 .set push
39 .set noat
40 LONG_S $1, PT_R1(sp)
41 .set pop
42 .endm
43
44 .macro SAVE_TEMP
45#ifdef CONFIG_CPU_HAS_SMARTMIPS
46 mflhxu v1
47 LONG_S v1, PT_LO(sp)
48 mflhxu v1
49 LONG_S v1, PT_HI(sp)
50 mflhxu v1
51 LONG_S v1, PT_ACX(sp)
52#else
53 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
56 LONG_S v1, PT_LO(sp)
57#endif
58#ifdef CONFIG_32BIT
59 LONG_S $8, PT_R8(sp)
60 LONG_S $9, PT_R9(sp)
61#endif
62 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp)
65 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp)
69 .endm
70
71 .macro SAVE_STATIC
72 LONG_S $16, PT_R16(sp)
73 LONG_S $17, PT_R17(sp)
74 LONG_S $18, PT_R18(sp)
75 LONG_S $19, PT_R19(sp)
76 LONG_S $20, PT_R20(sp)
77 LONG_S $21, PT_R21(sp)
78 LONG_S $22, PT_R22(sp)
79 LONG_S $23, PT_R23(sp)
80 LONG_S $30, PT_R30(sp)
81 .endm
82
83#ifdef CONFIG_SMP
84#ifdef CONFIG_MIPS_MT_SMTC
85#define PTEBASE_SHIFT 19 /* TCBIND */
86#else
87#define PTEBASE_SHIFT 23 /* CONTEXT */
88#endif
89 .macro get_saved_sp /* SMP variation */
90#ifdef CONFIG_MIPS_MT_SMTC
91 mfc0 k0, CP0_TCBIND
92#else
93 MFC0 k0, CP0_CONTEXT
94#endif
95#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96 lui k1, %hi(kernelsp)
97#else
98 lui k1, %highest(kernelsp)
99 daddiu k1, %higher(kernelsp)
100 dsll k1, 16
101 daddiu k1, %hi(kernelsp)
102 dsll k1, 16
103#endif
104 LONG_SRL k0, PTEBASE_SHIFT
105 LONG_ADDU k1, k0
106 LONG_L k1, %lo(kernelsp)(k1)
107 .endm
108
109 .macro set_saved_sp stackp temp temp2
110#ifdef CONFIG_MIPS_MT_SMTC
111 mfc0 \temp, CP0_TCBIND
112#else
113 MFC0 \temp, CP0_CONTEXT
114#endif
115 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp)
117 .endm
118#else
119 .macro get_saved_sp /* Uniprocessor variation */
120#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
121 lui k1, %hi(kernelsp)
122#else
123 lui k1, %highest(kernelsp)
124 daddiu k1, %higher(kernelsp)
125 dsll k1, k1, 16
126 daddiu k1, %hi(kernelsp)
127 dsll k1, k1, 16
128#endif
129 LONG_L k1, %lo(kernelsp)(k1)
130 .endm
131
132 .macro set_saved_sp stackp temp temp2
133 LONG_S \stackp, kernelsp
134 .endm
135#endif
136
137 .macro SAVE_SOME
138 .set push
139 .set noat
140 .set reorder
141 mfc0 k0, CP0_STATUS
142 sll k0, 3 /* extract cu0 bit */
143 .set noreorder
144 bltz k0, 8f
145 move k1, sp
146 .set reorder
147 /* Called from user mode, new stack. */
148 get_saved_sp
149#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
1508: move k0, sp
151 PTR_SUBU sp, k1, PT_SIZE
152#else
153 .set at=k0
1548: PTR_SUBU k1, PT_SIZE
155 .set noat
156 move k0, sp
157 move sp, k1
158#endif
159 LONG_S k0, PT_R29(sp)
160 LONG_S $3, PT_R3(sp)
161 /*
162 * You might think that you don't need to save $0,
163 * but the FPU emulator and gdb remote debug stub
164 * need it to operate correctly
165 */
166 LONG_S $0, PT_R0(sp)
167 mfc0 v1, CP0_STATUS
168 LONG_S $2, PT_R2(sp)
169 LONG_S v1, PT_STATUS(sp)
170#ifdef CONFIG_MIPS_MT_SMTC
171 /*
172 * Ideally, these instructions would be shuffled in
173 * to cover the pipeline delay.
174 */
175 .set mips32
176 mfc0 v1, CP0_TCSTATUS
177 .set mips0
178 LONG_S v1, PT_TCSTATUS(sp)
179#endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S $4, PT_R4(sp)
181 mfc0 v1, CP0_CAUSE
182 LONG_S $5, PT_R5(sp)
183 LONG_S v1, PT_CAUSE(sp)
184 LONG_S $6, PT_R6(sp)
185 MFC0 v1, CP0_EPC
186 LONG_S $7, PT_R7(sp)
187#ifdef CONFIG_64BIT
188 LONG_S $8, PT_R8(sp)
189 LONG_S $9, PT_R9(sp)
190#endif
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp)
195 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK
197 .set pop
198 .endm
199
200 .macro SAVE_ALL
201 SAVE_SOME
202 SAVE_AT
203 SAVE_TEMP
204 SAVE_STATIC
205 .endm
206
207 .macro RESTORE_AT
208 .set push
209 .set noat
210 LONG_L $1, PT_R1(sp)
211 .set pop
212 .endm
213
214 .macro RESTORE_TEMP
215#ifdef CONFIG_CPU_HAS_SMARTMIPS
216 LONG_L $24, PT_ACX(sp)
217 mtlhx $24
218 LONG_L $24, PT_HI(sp)
219 mtlhx $24
220 LONG_L $24, PT_LO(sp)
221 mtlhx $24
222#else
223 LONG_L $24, PT_LO(sp)
224 mtlo $24
225 LONG_L $24, PT_HI(sp)
226 mthi $24
227#endif
228#ifdef CONFIG_32BIT
229 LONG_L $8, PT_R8(sp)
230 LONG_L $9, PT_R9(sp)
231#endif
232 LONG_L $10, PT_R10(sp)
233 LONG_L $11, PT_R11(sp)
234 LONG_L $12, PT_R12(sp)
235 LONG_L $13, PT_R13(sp)
236 LONG_L $14, PT_R14(sp)
237 LONG_L $15, PT_R15(sp)
238 LONG_L $24, PT_R24(sp)
239 .endm
240
241 .macro RESTORE_STATIC
242 LONG_L $16, PT_R16(sp)
243 LONG_L $17, PT_R17(sp)
244 LONG_L $18, PT_R18(sp)
245 LONG_L $19, PT_R19(sp)
246 LONG_L $20, PT_R20(sp)
247 LONG_L $21, PT_R21(sp)
248 LONG_L $22, PT_R22(sp)
249 LONG_L $23, PT_R23(sp)
250 LONG_L $30, PT_R30(sp)
251 .endm
252
253#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
254
255 .macro RESTORE_SOME
256 .set push
257 .set reorder
258 .set noat
259 mfc0 a0, CP0_STATUS
260 li v1, 0xff00
261 ori a0, STATMASK
262 xori a0, STATMASK
263 mtc0 a0, CP0_STATUS
264 and a0, v1
265 LONG_L v0, PT_STATUS(sp)
266 nor v1, $0, v1
267 and v0, v1
268 or v0, a0
269 mtc0 v0, CP0_STATUS
270 LONG_L $31, PT_R31(sp)
271 LONG_L $28, PT_R28(sp)
272 LONG_L $25, PT_R25(sp)
273 LONG_L $7, PT_R7(sp)
274 LONG_L $6, PT_R6(sp)
275 LONG_L $5, PT_R5(sp)
276 LONG_L $4, PT_R4(sp)
277 LONG_L $3, PT_R3(sp)
278 LONG_L $2, PT_R2(sp)
279 .set pop
280 .endm
281
282 .macro RESTORE_SP_AND_RET
283 .set push
284 .set noreorder
285 LONG_L k0, PT_EPC(sp)
286 LONG_L sp, PT_R29(sp)
287 jr k0
288 rfe
289 .set pop
290 .endm
291
292#else
293 .macro RESTORE_SOME
294 .set push
295 .set reorder
296 .set noat
297#ifdef CONFIG_MIPS_MT_SMTC
298 .set mips32r2
299 /*
300 * This may not really be necessary if ints are already
301 * inhibited here.
302 */
303 mfc0 v0, CP0_TCSTATUS
304 ori v0, TCSTATUS_IXMT
305 mtc0 v0, CP0_TCSTATUS
306 _ehb
307 DMT 5 # dmt a1
308 jal mips_ihb
309#endif /* CONFIG_MIPS_MT_SMTC */
310 mfc0 a0, CP0_STATUS
311 ori a0, STATMASK
312 xori a0, STATMASK
313 mtc0 a0, CP0_STATUS
314 li v1, 0xff00
315 and a0, v1
316 LONG_L v0, PT_STATUS(sp)
317 nor v1, $0, v1
318 and v0, v1
319 or v0, a0
320 mtc0 v0, CP0_STATUS
321#ifdef CONFIG_MIPS_MT_SMTC
322/*
323 * Only after EXL/ERL have been restored to status can we
324 * restore TCStatus.IXMT.
325 */
326 LONG_L v1, PT_TCSTATUS(sp)
327 _ehb
328 mfc0 v0, CP0_TCSTATUS
329 andi v1, TCSTATUS_IXMT
330 /* We know that TCStatua.IXMT should be set from above */
331 xori v0, v0, TCSTATUS_IXMT
332 or v0, v0, v1
333 mtc0 v0, CP0_TCSTATUS
334 _ehb
335 andi a1, a1, VPECONTROL_TE
336 beqz a1, 1f
337 emt
3381:
339 .set mips0
340#endif /* CONFIG_MIPS_MT_SMTC */
341 LONG_L v1, PT_EPC(sp)
342 MTC0 v1, CP0_EPC
343 LONG_L $31, PT_R31(sp)
344 LONG_L $28, PT_R28(sp)
345 LONG_L $25, PT_R25(sp)
346#ifdef CONFIG_64BIT
347 LONG_L $8, PT_R8(sp)
348 LONG_L $9, PT_R9(sp)
349#endif
350 LONG_L $7, PT_R7(sp)
351 LONG_L $6, PT_R6(sp)
352 LONG_L $5, PT_R5(sp)
353 LONG_L $4, PT_R4(sp)
354 LONG_L $3, PT_R3(sp)
355 LONG_L $2, PT_R2(sp)
356 .set pop
357 .endm
358
359 .macro RESTORE_SP_AND_RET
360 LONG_L sp, PT_R29(sp)
361 .set mips3
362 eret
363 .set mips0
364 .endm
365
366#endif
367
368 .macro RESTORE_SP
369 LONG_L sp, PT_R29(sp)
370 .endm
371
372 .macro RESTORE_ALL
373 RESTORE_TEMP
374 RESTORE_STATIC
375 RESTORE_AT
376 RESTORE_SOME
377 RESTORE_SP
378 .endm
379
380 .macro RESTORE_ALL_AND_RET
381 RESTORE_TEMP
382 RESTORE_STATIC
383 RESTORE_AT
384 RESTORE_SOME
385 RESTORE_SP_AND_RET
386 .endm
387
388/*
389 * Move to kernel mode and disable interrupts.
390 * Set cp0 enable bit as sign that we're running on the kernel stack
391 */
392 .macro CLI
393#if !defined(CONFIG_MIPS_MT_SMTC)
394 mfc0 t0, CP0_STATUS
395 li t1, ST0_CU0 | STATMASK
396 or t0, t1
397 xori t0, STATMASK
398 mtc0 t0, CP0_STATUS
399#else /* CONFIG_MIPS_MT_SMTC */
400 /*
401 * For SMTC, we need to set privilege
402 * and disable interrupts only for the
403 * current TC, using the TCStatus register.
404 */
405 mfc0 t0, CP0_TCSTATUS
406 /* Fortunately CU 0 is in the same place in both registers */
407 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
408 li t1, ST0_CU0 | 0x08001c00
409 or t0, t1
410 /* Clear TKSU, leave IXMT */
411 xori t0, 0x00001800
412 mtc0 t0, CP0_TCSTATUS
413 _ehb
414 /* We need to leave the global IE bit set, but clear EXL...*/
415 mfc0 t0, CP0_STATUS
416 ori t0, ST0_EXL | ST0_ERL
417 xori t0, ST0_EXL | ST0_ERL
418 mtc0 t0, CP0_STATUS
419#endif /* CONFIG_MIPS_MT_SMTC */
420 irq_disable_hazard
421 .endm
422
423/*
424 * Move to kernel mode and enable interrupts.
425 * Set cp0 enable bit as sign that we're running on the kernel stack
426 */
427 .macro STI
428#if !defined(CONFIG_MIPS_MT_SMTC)
429 mfc0 t0, CP0_STATUS
430 li t1, ST0_CU0 | STATMASK
431 or t0, t1
432 xori t0, STATMASK & ~1
433 mtc0 t0, CP0_STATUS
434#else /* CONFIG_MIPS_MT_SMTC */
435 /*
436 * For SMTC, we need to set privilege
437 * and enable interrupts only for the
438 * current TC, using the TCStatus register.
439 */
440 _ehb
441 mfc0 t0, CP0_TCSTATUS
442 /* Fortunately CU 0 is in the same place in both registers */
443 /* Set TCU0, TKSU (for later inversion) and IXMT */
444 li t1, ST0_CU0 | 0x08001c00
445 or t0, t1
446 /* Clear TKSU *and* IXMT */
447 xori t0, 0x00001c00
448 mtc0 t0, CP0_TCSTATUS
449 _ehb
450 /* We need to leave the global IE bit set, but clear EXL...*/
451 mfc0 t0, CP0_STATUS
452 ori t0, ST0_EXL
453 xori t0, ST0_EXL
454 mtc0 t0, CP0_STATUS
455 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
456#endif /* CONFIG_MIPS_MT_SMTC */
457 irq_enable_hazard
458 .endm
459
460/*
461 * Just move to kernel mode and leave interrupts as they are. Note
462 * for the R3000 this means copying the previous enable from IEp.
463 * Set cp0 enable bit as sign that we're running on the kernel stack
464 */
465 .macro KMODE
466#ifdef CONFIG_MIPS_MT_SMTC
467 /*
468 * This gets baroque in SMTC. We want to
469 * protect the non-atomic clearing of EXL
470 * with DMT/EMT, but we don't want to take
471 * an interrupt while DMT is still in effect.
472 */
473
474 /* KMODE gets invoked from both reorder and noreorder code */
475 .set push
476 .set mips32r2
477 .set noreorder
478 mfc0 v0, CP0_TCSTATUS
479 andi v1, v0, TCSTATUS_IXMT
480 ori v0, TCSTATUS_IXMT
481 mtc0 v0, CP0_TCSTATUS
482 _ehb
483 DMT 2 # dmt v0
484 /*
485 * We don't know a priori if ra is "live"
486 */
487 move t0, ra
488 jal mips_ihb
489 nop /* delay slot */
490 move ra, t0
491#endif /* CONFIG_MIPS_MT_SMTC */
492 mfc0 t0, CP0_STATUS
493 li t1, ST0_CU0 | (STATMASK & ~1)
494#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
495 andi t2, t0, ST0_IEP
496 srl t2, 2
497 or t0, t2
498#endif
499 or t0, t1
500 xori t0, STATMASK & ~1
501 mtc0 t0, CP0_STATUS
502#ifdef CONFIG_MIPS_MT_SMTC
503 _ehb
504 andi v0, v0, VPECONTROL_TE
505 beqz v0, 2f
506 nop /* delay slot */
507 emt
5082:
509 mfc0 v0, CP0_TCSTATUS
510 /* Clear IXMT, then OR in previous value */
511 ori v0, TCSTATUS_IXMT
512 xori v0, TCSTATUS_IXMT
513 or v0, v1, v0
514 mtc0 v0, CP0_TCSTATUS
515 /*
516 * irq_disable_hazard below should expand to EHB
517 * on 24K/34K CPUS
518 */
519 .set pop
520#endif /* CONFIG_MIPS_MT_SMTC */
521 irq_disable_hazard
522 .endm
523
524#endif /* _ASM_STACKFRAME_H */
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