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-rw-r--r--include/asm-mips/sn/sn0/addrs.h288
-rw-r--r--include/asm-mips/sn/sn0/arch.h72
-rw-r--r--include/asm-mips/sn/sn0/hub.h40
-rw-r--r--include/asm-mips/sn/sn0/hubio.h972
-rw-r--r--include/asm-mips/sn/sn0/hubmd.h789
-rw-r--r--include/asm-mips/sn/sn0/hubni.h255
-rw-r--r--include/asm-mips/sn/sn0/hubpi.h409
-rw-r--r--include/asm-mips/sn/sn0/ip27.h85
8 files changed, 0 insertions, 2910 deletions
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
deleted file mode 100644
index b06190093bbc..000000000000
--- a/include/asm-mips/sn/sn0/addrs.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_ADDRS_H
12#define _ASM_SN_SN0_ADDRS_H
13
14
15/*
16 * SN0 (on a T5) Address map
17 *
18 * This file contains a set of definitions and macros which are used
19 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
20 * and UNCAC) used by the SN0 architecture. It also contains addresses
21 * for "major" statically locatable PROM/Kernel data structures, such as
22 * the partition table, the configuration data structure, etc.
23 * We make an implicit assumption that the processor using this file
24 * follows the R10K's provisions for specifying uncached attributes;
25 * should this change, the base registers may very well become processor-
26 * dependent.
27 *
28 * For more information on the address spaces, see the "Local Resources"
29 * chapter of the Hub specification.
30 *
31 * NOTE: This header file is included both by C and by assembler source
32 * files. Please bracket any language-dependent definitions
33 * appropriately.
34 */
35
36/*
37 * Some of the macros here need to be casted to appropriate types when used
38 * from C. They definitely must not be casted from assembly language so we
39 * use some new ANSI preprocessor stuff to paste these on where needed.
40 */
41
42/*
43 * The following couple of definitions will eventually need to be variables,
44 * since the amount of address space assigned to each node depends on
45 * whether the system is running in N-mode (more nodes with less memory)
46 * or M-mode (fewer nodes with more memory). We expect that it will
47 * be a while before we need to make this decision dynamically, though,
48 * so for now we just use defines bracketed by an ifdef.
49 */
50
51#ifdef CONFIG_SGI_SN_N_MODE
52
53#define NODE_SIZE_BITS 31
54#define BWIN_SIZE_BITS 28
55
56#define NASID_BITS 9
57#define NASID_BITMASK (0x1ffLL)
58#define NASID_SHFT 31
59#define NASID_META_BITS 5
60#define NASID_LOCAL_BITS 4
61
62#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
64
65#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
66
67#define NODE_SIZE_BITS 32
68#define BWIN_SIZE_BITS 29
69
70#define NASID_BITMASK (0xffLL)
71#define NASID_BITS 8
72#define NASID_SHFT 32
73#define NASID_META_BITS 4
74#define NASID_LOCAL_BITS 4
75
76#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
78
79#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
80
81#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
82
83#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
84#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
85 NASID_SHFT) & NASID_BITMASK)
86
87#if !defined(__ASSEMBLY__)
88
89#define NODE_SWIN_BASE(nasid, widget) \
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ */
96
97/*
98 * The following definitions pertain to the IO special address
99 * space. They define the location of the big and little windows
100 * of any given node.
101 */
102
103#define BWIN_INDEX_BITS 3
104#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
105#define BWIN_SIZEMASK (BWIN_SIZE - 1)
106#define BWIN_WIDGET_MASK 0x7
107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
110
111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
113/*
114 * Verify if addr belongs to large window address of node with "nasid"
115 *
116 *
117 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
118 * address
119 *
120 *
121 */
122
123#define NODE_BWIN_ADDR(nasid, addr) \
124 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
125 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
126 BWIN_SIZE)))
127
128/*
129 * The following define the major position-independent aliases used
130 * in SN0.
131 * CALIAS -- Varies in size, points to the first n bytes of memory
132 * on the reader's node.
133 */
134
135#define CALIAS_BASE CAC_BASE
136
137
138
139#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
140 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
141
142#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
143
144/* Turn on sable logging for the processors whose bits are set. */
145#define SABLE_LOG_TRIGGER(_map)
146
147#ifndef __ASSEMBLY__
148#define KERN_NMI_ADDR(nasid, slice) \
149 TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
150 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
151#endif /* !__ASSEMBLY__ */
152
153#ifdef PROM
154
155#define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
156#define MISC_PROM_SIZE 0x200000
157
158#define DIAG_BASE PHYS_TO_K0(0x01500000)
159#define DIAG_SIZE 0x300000
160
161#define ROUTE_BASE PHYS_TO_K0(0x01800000)
162#define ROUTE_SIZE 0x200000
163
164#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
165#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
166#define IP27PROM_CORP_MAX 32
167#define IP27PROM_CORP PHYS_TO_K0(0x01800000)
168#define IP27PROM_CORP_SIZE 0x10000
169#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
170#define IP27PROM_CORP_STKSIZE 0x2000
171#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
172#define IP27PROM_DECOMP_SIZE 0xfff00
173
174#define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
175#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
176#define IP27PROM_SIZE_MAX 0x100000
177
178#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
179#define IP27PROM_PCFG_SIZE 0xd0000
180#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
181#define IP27PROM_ERRDMP_SIZE 0xf000
182
183#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
184#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
185#define IP27PROM_CONSOLE_SIZE 0x200
186#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
187#define IP27PROM_NETUART_SIZE 0x100
188#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
189#define IP27PROM_UNUSED1_SIZE 0x500
190#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
191#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
192#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
193#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
194#define IP27PROM_STACK_SHFT 16
195#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
196#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
197
198#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
199#define SLAVESTACK_SIZE 0x40000
200
201#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
202#define ENETBUFS_SIZE 0x20000
203
204#define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
205#define IO6PROM_SIZE 0x400000
206#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
207#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
208#define IO6DPROM_SIZE 0x200000
209
210#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
211#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
212
213#define IP27PROM_INT_LAUNCH 10 /* and 11 */
214#define IP27PROM_INT_NETUART 12 /* through 17 */
215
216#endif /* PROM */
217
218/*
219 * needed by symmon so it needs to be outside #if PROM
220 */
221#define IP27PROM_ELSC_SHFT 10
222#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
223
224/*
225 * This address is used by IO6PROM to build MemoryDescriptors of
226 * free memory. This address is important since unix gets loaded
227 * at this address, and this memory has to be FREE if unix is to
228 * be loaded.
229 */
230
231#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
232
233#define IO6PROM_STACK_SHFT 14 /* stack per cpu */
234#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
235
236/*
237 * IP27 PROM vectors
238 */
239
240#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
241#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
242#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
243#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
244#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
245#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
246#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
247#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
248#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
249#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
250
251#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
252#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
253#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
254#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
255
256#ifndef __ASSEMBLY__
257
258/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
260 * the stack could start at CACHE_ERR_SP_PTR
261 */
262#if defined(HUB_ERR_STS_WAR)
263#define CACHE_ERR_EFRAME 0x480
264#else /* HUB_ERR_STS_WAR */
265#define CACHE_ERR_EFRAME 0x400
266#endif /* HUB_ERR_STS_WAR */
267
268#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
269#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
270#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
271#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
272#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
273
274#endif /* !__ASSEMBLY__ */
275
276#define _ARCSPROM
277
278#if defined(HUB_ERR_STS_WAR)
279
280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
282#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
283 /* Used to match addr in error reg. */
284#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
285
286#endif /* HUB_ERR_STS_WAR */
287
288#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
deleted file mode 100644
index f734f2007f24..000000000000
--- a/include/asm-mips/sn/sn0/arch.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI IP27 specific setup.
7 *
8 * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_SN_SN0_ARCH_H
12#define _ASM_SN_SN0_ARCH_H
13
14
15#ifndef SN0XXL /* 128 cpu SMP max */
16/*
17 * This is the maximum number of nodes that can be part of a kernel.
18 * Effectively, it's the maximum number of compact node ids (cnodeid_t).
19 */
20#define MAX_COMPACT_NODES 64
21
22/*
23 * MAXCPUS refers to the maximum number of CPUs in a single kernel.
24 * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
25 */
26#define MAXCPUS 128
27
28#else /* SN0XXL system */
29
30#define MAX_COMPACT_NODES 128
31#define MAXCPUS 256
32
33#endif /* SN0XXL */
34
35/*
36 * This is the maximum number of NASIDS that can be present in a system.
37 * (Highest NASID plus one.)
38 */
39#define MAX_NASIDS 256
40
41/*
42 * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
43 */
44#define MAX_REGIONS 64
45#define MAX_NONPREMIUM_REGIONS 16
46#define MAX_PREMIUM_REGIONS MAX_REGIONS
47
48/*
49 * MAX_PARITIONS refers to the maximum number of logically defined
50 * partitions the system can support.
51 */
52#define MAX_PARTITIONS MAX_REGIONS
53
54#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
55
56/*
57 * Slot constants for SN0
58 */
59#ifdef CONFIG_SGI_SN_N_MODE
60#define MAX_MEM_SLOTS 16 /* max slots per node */
61#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
62#define MAX_MEM_SLOTS 32 /* max slots per node */
63#endif /* CONFIG_SGI_SN_M_MODE */
64
65#define SLOT_SHIFT (27)
66#define SLOT_MIN_MEM_SIZE (32*1024*1024)
67
68#define CPUS_PER_NODE 2 /* CPUs on a single hub */
69#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */
70#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */
71
72#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h
deleted file mode 100644
index 3e228f8e7969..000000000000
--- a/include/asm-mips/sn/sn0/hub.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_SN_SN0_HUB_H
10#define _ASM_SN_SN0_HUB_H
11
12/* The secret password; used to release protection */
13#define HUB_PASSWORD 0x53474972756c6573ull
14
15#define CHIPID_HUB 0
16#define CHIPID_ROUTER 1
17
18#define HUB_REV_1_0 1
19#define HUB_REV_2_0 2
20#define HUB_REV_2_1 3
21#define HUB_REV_2_2 4
22#define HUB_REV_2_3 5
23#define HUB_REV_2_4 6
24
25#define MAX_HUB_PATH 80
26
27#include <asm/sn/sn0/addrs.h>
28#include <asm/sn/sn0/hubpi.h>
29#include <asm/sn/sn0/hubmd.h>
30#include <asm/sn/sn0/hubio.h>
31#include <asm/sn/sn0/hubni.h>
32//#include <asm/sn/sn0/hubcore.h>
33
34/* Translation of uncached attributes */
35#define UATTR_HSPEC 0
36#define UATTR_IO 1
37#define UATTR_MSPEC 2
38#define UATTR_UNCAC 3
39
40#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
deleted file mode 100644
index 0187895e556c..000000000000
--- a/include/asm-mips/sn/sn0/hubio.h
+++ /dev/null
@@ -1,972 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SGI_SN_SN0_HUBIO_H
12#define _ASM_SGI_SN_SN0_HUBIO_H
13
14/*
15 * Hub I/O interface registers
16 *
17 * All registers in this file are subject to change until Hub chip tapeout.
18 * In general, the longer software name should be used when available.
19 */
20
21/*
22 * Slightly friendlier names for some common registers.
23 * The hardware definitions follow.
24 */
25#define IIO_WIDGET IIO_WID /* Widget identification */
26#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
27#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
28#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
29#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
30#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
31#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
32#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
33#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
34#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
35#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
36#define IIO_LLP_LOG IIO_ILLR /* LLP log */
37#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
38#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
39#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
40#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
41
42#define IIO_LLP_CSR_IS_UP 0x00002000
43#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
44#define IIO_LLP_CSR_LLP_STAT_SHFT 12
45
46/* key to IIO_PROTECT_OVRRD */
47#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
48
49/* BTE register names */
50#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
51#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
52#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
53#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
54#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
55#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
56#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
57#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
58
59/* BTE register offsets from base */
60#define BTEOFF_STAT 0
61#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
62#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
63#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
64#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
65#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
66
67
68/*
69 * The following definitions use the names defined in the IO interface
70 * document for ease of reference. When possible, software should
71 * generally use the longer but clearer names defined above.
72 */
73
74#define IIO_BASE 0x400000
75#define IIO_BASE_BTE0 0x410000
76#define IIO_BASE_BTE1 0x420000
77#define IIO_BASE_PERF 0x430000
78#define IIO_PERF_CNT 0x430008
79
80#define IO_PERF_SETS 32
81
82#define IIO_WID 0x400000 /* Widget identification */
83#define IIO_WSTAT 0x400008 /* Widget status */
84#define IIO_WCR 0x400020 /* Widget control */
85
86#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
87#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
88#define IIO_WSTAT_TXRETRY_MASK (0x7F)
89#define IIO_WSTAT_TXRETRY_SHFT (16)
90#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
91 IIO_WSTAT_TXRETRY_MASK)
92
93#define IIO_ILAPR 0x400100 /* Local Access Protection */
94#define IIO_ILAPO 0x400108 /* Protection override */
95#define IIO_IOWA 0x400110 /* outbound widget access */
96#define IIO_IIWA 0x400118 /* inbound widget access */
97#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
98#define IIO_ILCSR 0x400128 /* LLP control and status */
99#define IIO_ILLR 0x400130 /* LLP Log */
100#define IIO_IIDSR 0x400138 /* Interrupt destination */
101
102#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
103
104/* IO Interrupt Destination Register */
105#define IIO_IIDSR_SENT_SHIFT 28
106#define IIO_IIDSR_SENT_MASK 0x10000000
107#define IIO_IIDSR_ENB_SHIFT 24
108#define IIO_IIDSR_ENB_MASK 0x01000000
109#define IIO_IIDSR_NODE_SHIFT 8
110#define IIO_IIDSR_NODE_MASK 0x0000ff00
111#define IIO_IIDSR_LVL_SHIFT 0
112#define IIO_IIDSR_LVL_MASK 0x0000003f
113
114
115/* GFX Flow Control Node/Widget Register */
116#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
117#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
118#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
119#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
120#define IIO_IGFX_W_NUM_SHIFT 0
121#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
122#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
123#define IIO_IGFX_N_NUM_SHIFT 4
124#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
125#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
126#define IIO_IGFX_P_NUM_SHIFT 16
127#define IIO_IGFX_VLD_BITS 1 /* size of valid field */
128#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
129#define IIO_IGFX_VLD_SHIFT 20
130#define IIO_IGFX_INIT(widget, node, cpu, valid) (\
131 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
132 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
133 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
134 (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
135
136/* Scratch registers (not all bits available) */
137#define IIO_SCRATCH_REG0 0x400150
138#define IIO_SCRATCH_REG1 0x400158
139#define IIO_SCRATCH_MASK 0x0000000f00f11fff
140
141#define IIO_SCRATCH_BIT0_0 0x0000000800000000
142#define IIO_SCRATCH_BIT0_1 0x0000000400000000
143#define IIO_SCRATCH_BIT0_2 0x0000000200000000
144#define IIO_SCRATCH_BIT0_3 0x0000000100000000
145#define IIO_SCRATCH_BIT0_4 0x0000000000800000
146#define IIO_SCRATCH_BIT0_5 0x0000000000400000
147#define IIO_SCRATCH_BIT0_6 0x0000000000200000
148#define IIO_SCRATCH_BIT0_7 0x0000000000100000
149#define IIO_SCRATCH_BIT0_8 0x0000000000010000
150#define IIO_SCRATCH_BIT0_9 0x0000000000001000
151#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
152
153/* IO Translation Table Entries */
154#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
155 /* Hw manuals number them 1..7! */
156
157/*
158 * As a permanent workaround for a bug in the PI side of the hub, we've
159 * redefined big window 7 as small window 0.
160 */
161#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
162
163/*
164 * Use the top big window as a surrogate for the first small window
165 */
166#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
167
168#define ILCSR_WARM_RESET 0x100
169/*
170 * The IO LLP control status register and widget control register
171 */
172#ifndef __ASSEMBLY__
173
174typedef union hubii_wid_u {
175 u64 wid_reg_value;
176 struct {
177 u64 wid_rsvd: 32, /* unused */
178 wid_rev_num: 4, /* revision number */
179 wid_part_num: 16, /* the widget type: hub=c101 */
180 wid_mfg_num: 11, /* Manufacturer id (IBM) */
181 wid_rsvd1: 1; /* Reserved */
182 } wid_fields_s;
183} hubii_wid_t;
184
185
186typedef union hubii_wcr_u {
187 u64 wcr_reg_value;
188 struct {
189 u64 wcr_rsvd: 41, /* unused */
190 wcr_e_thresh: 5, /* elasticity threshold */
191 wcr_dir_con: 1, /* widget direct connect */
192 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
193 wcr_xbar_crd: 3, /* LLP crossbar credit */
194 wcr_rsvd1: 8, /* Reserved */
195 wcr_tag_mode: 1, /* Tag mode */
196 wcr_widget_id: 4; /* LLP crossbar credit */
197 } wcr_fields_s;
198} hubii_wcr_t;
199
200#define iwcr_dir_con wcr_fields_s.wcr_dir_con
201
202typedef union hubii_wstat_u {
203 u64 reg_value;
204 struct {
205 u64 rsvd1: 31,
206 crazy: 1, /* Crazy bit */
207 rsvd2: 8,
208 llp_tx_cnt: 8, /* LLP Xmit retry counter */
209 rsvd3: 6,
210 tx_max_rtry: 1, /* LLP Retry Timeout Signal */
211 rsvd4: 2,
212 xt_tail_to: 1, /* Xtalk Tail Timeout */
213 xt_crd_to: 1, /* Xtalk Credit Timeout */
214 pending: 4; /* Pending Requests */
215 } wstat_fields_s;
216} hubii_wstat_t;
217
218
219typedef union hubii_ilcsr_u {
220 u64 icsr_reg_value;
221 struct {
222 u64 icsr_rsvd: 22, /* unused */
223 icsr_max_burst: 10, /* max burst */
224 icsr_rsvd4: 6, /* reserved */
225 icsr_max_retry: 10, /* max retry */
226 icsr_rsvd3: 2, /* reserved */
227 icsr_lnk_stat: 2, /* link status */
228 icsr_bm8: 1, /* Bit mode 8 */
229 icsr_llp_en: 1, /* LLP enable bit */
230 icsr_rsvd2: 1, /* reserver */
231 icsr_wrm_reset: 1, /* Warm reset bit */
232 icsr_rsvd1: 2, /* Data ready offset */
233 icsr_null_to: 6; /* Null timeout */
234
235 } icsr_fields_s;
236} hubii_ilcsr_t;
237
238
239typedef union hubii_iowa_u {
240 u64 iowa_reg_value;
241 struct {
242 u64 iowa_rsvd: 48, /* unused */
243 iowa_wxoac: 8, /* xtalk widget access bits */
244 iowa_rsvd1: 7, /* xtalk widget access bits */
245 iowa_w0oac: 1; /* xtalk widget access bits */
246 } iowa_fields_s;
247} hubii_iowa_t;
248
249typedef union hubii_iiwa_u {
250 u64 iiwa_reg_value;
251 struct {
252 u64 iiwa_rsvd: 48, /* unused */
253 iiwa_wxiac: 8, /* hub wid access bits */
254 iiwa_rsvd1: 7, /* reserved */
255 iiwa_w0iac: 1; /* hub wid0 access */
256 } iiwa_fields_s;
257} hubii_iiwa_t;
258
259typedef union hubii_illr_u {
260 u64 illr_reg_value;
261 struct {
262 u64 illr_rsvd: 32, /* unused */
263 illr_cb_cnt: 16, /* checkbit error count */
264 illr_sn_cnt: 16; /* sequence number count */
265 } illr_fields_s;
266} hubii_illr_t;
267
268/* The structures below are defined to extract and modify the ii
269performance registers */
270
271/* io_perf_sel allows the caller to specify what tests will be
272 performed */
273typedef union io_perf_sel {
274 u64 perf_sel_reg;
275 struct {
276 u64 perf_rsvd : 48,
277 perf_icct : 8,
278 perf_ippr1 : 4,
279 perf_ippr0 : 4;
280 } perf_sel_bits;
281} io_perf_sel_t;
282
283/* io_perf_cnt is to extract the count from the hub registers. Due to
284 hardware problems there is only one counter, not two. */
285
286typedef union io_perf_cnt {
287 u64 perf_cnt;
288 struct {
289 u64 perf_rsvd1 : 32,
290 perf_rsvd2 : 12,
291 perf_cnt : 20;
292 } perf_cnt_bits;
293} io_perf_cnt_t;
294
295#endif /* !__ASSEMBLY__ */
296
297
298#define LNK_STAT_WORKING 0x2
299
300#define IIO_LLP_CB_MAX 0xffff
301#define IIO_LLP_SN_MAX 0xffff
302
303/* IO PRB Entries */
304#define IIO_NUM_IPRBS (9)
305#define IIO_IOPRB_0 0x400198 /* PRB entry 0 */
306#define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */
307#define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */
308#define IIO_IOPRB_A 0x4001b0 /* PRB entry a */
309#define IIO_IOPRB_B 0x4001b8 /* PRB entry b */
310#define IIO_IOPRB_C 0x4001c0 /* PRB entry c */
311#define IIO_IOPRB_D 0x4001c8 /* PRB entry d */
312#define IIO_IOPRB_E 0x4001d0 /* PRB entry e */
313#define IIO_IOPRB_F 0x4001d8 /* PRB entry f */
314
315
316#define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */
317#define IIO_IXTCC IIO_IXCC
318#define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */
319#define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */
320#define IIO_IECLR 0x4001f8 /* IO error clear */
321#define IIO_IBCN 0x400200 /* IO BTE CRB count */
322
323/*
324 * IIO_IMEM Register fields.
325 */
326#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
327#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
328#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
329
330/* PIO Read address Table Entries */
331#define IIO_IPCA 0x400300 /* PRB Counter adjust */
332#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
333#define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */
334#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
335#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
336#define IIO_IPDR 0x400388 /* PIO table entry deallocation */
337#define IIO_ICDR 0x400390 /* CRB Entry Deallocation */
338#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
339#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
340#define IIO_IMMR IIO_IIAP
341#define IIO_ICMR 0x4003a8 /* CRB Management Register */
342#define IIO_ICCR 0x4003b0 /* CRB Control Register */
343#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
344#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
345
346
347/*
348 * ICMR register fields
349 */
350#define IIO_ICMR_PC_VLD_SHFT 36
351#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
352
353#define IIO_ICMR_CRB_VLD_SHFT 20
354#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
355
356#define IIO_ICMR_FC_CNT_SHFT 16
357#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
358
359#define IIO_ICMR_C_CNT_SHFT 4
360#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
361
362#define IIO_ICMR_P_CNT_SHFT 0
363#define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
364
365#define IIO_ICMR_PRECISE (1UL << 52)
366#define IIO_ICMR_CLR_RPPD (1UL << 13)
367#define IIO_ICMR_CLR_RQPD (1UL << 12)
368
369/*
370 * IIO PIO Deallocation register field masks : (IIO_IPDR)
371 */
372#define IIO_IPDR_PND (1 << 4)
373
374/*
375 * IIO CRB deallocation register field masks: (IIO_ICDR)
376 */
377#define IIO_ICDR_PND (1 << 4)
378
379/*
380 * IIO CRB control register Fields: IIO_ICCR
381 */
382#define IIO_ICCR_PENDING (0x10000)
383#define IIO_ICCR_CMD_MASK (0xFF)
384#define IIO_ICCR_CMD_SHFT (7)
385#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
386#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
387#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
388#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
389 * via a WB
390 */
391#define IIO_ICCR_CMD_FLUSH (0x800)
392
393/*
394 * CRB manipulation macros
395 * The CRB macros are slightly complicated, since there are up to
396 * four registers associated with each CRB entry.
397 */
398#define IIO_NUM_CRBS 15 /* Number of CRBs */
399#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */
400#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
401#define IIO_ICRB_OFFSET 8
402#define IIO_ICRB_0 0x400400
403/* XXX - This is now tuneable:
404 #define IIO_FIRST_PC_ENTRY 12
405 */
406
407#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
408#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
409#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
410#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
411
412/* XXX - IBUE register coming for Hub 2 */
413
414/*
415 *
416 * CRB Register description.
417 *
418 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
419 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
420 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
421 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
422 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
423 *
424 * Many of the fields in CRB are status bits used by hardware
425 * for implementation of the protocol. It's very dangerous to
426 * mess around with the CRB registers.
427 *
428 * It's OK to read the CRB registers and try to make sense out of the
429 * fields in CRB.
430 *
431 * Updating CRB requires all activities in Hub IIO to be quiesced.
432 * otherwise, a write to CRB could corrupt other CRB entries.
433 * CRBs are here only as a back door peek to hub IIO's status.
434 * Quiescing implies no dmas no PIOs
435 * either directly from the cpu or from sn0net.
436 * this is not something that can be done easily. So, AVOID updating
437 * CRBs.
438 */
439
440/*
441 * Fields in CRB Register A
442 */
443#ifndef __ASSEMBLY__
444typedef union icrba_u {
445 u64 reg_value;
446 struct {
447 u64 resvd: 6,
448 stall_bte0: 1, /* Stall BTE 0 */
449 stall_bte1: 1, /* Stall BTE 1 */
450 error: 1, /* CRB has an error */
451 ecode: 3, /* Error Code */
452 lnetuce: 1, /* SN0net Uncorrectable error */
453 mark: 1, /* CRB Has been marked */
454 xerr: 1, /* Error bit set in xtalk header */
455 sidn: 4, /* SIDN field from xtalk */
456 tnum: 5, /* TNUM field in xtalk */
457 addr: 38, /* Address of request */
458 valid: 1, /* Valid status */
459 iow: 1; /* IO Write operation */
460 } icrba_fields_s;
461} icrba_t;
462
463/* This is an alternate typedef for the HUB1 CRB A in order to allow
464 runtime selection of the format based on the REV_ID field of the
465 NI_STATUS_REV_ID register. */
466typedef union h1_icrba_u {
467 u64 reg_value;
468
469 struct {
470 u64 resvd: 6,
471 unused: 1, /* Unused but RW!! */
472 error: 1, /* CRB has an error */
473 ecode: 4, /* Error Code */
474 lnetuce: 1, /* SN0net Uncorrectable error */
475 mark: 1, /* CRB Has been marked */
476 xerr: 1, /* Error bit set in xtalk header */
477 sidn: 4, /* SIDN field from xtalk */
478 tnum: 5, /* TNUM field in xtalk */
479 addr: 38, /* Address of request */
480 valid: 1, /* Valid status */
481 iow: 1; /* IO Write operation */
482 } h1_icrba_fields_s;
483} h1_icrba_t;
484
485/* XXX - Is this still right? Check the spec. */
486#define ICRBN_A_CERR_SHFT 54
487#define ICRBN_A_ERR_MASK 0x3ff
488
489#endif /* !__ASSEMBLY__ */
490
491#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
492
493/*
494 * values for "ecode" field
495 */
496#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
497#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
498#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
499 * e.g. WINV to a Read only line.
500 */
501#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
502#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
503#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
504#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
505#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
506
507
508
509/*
510 * Fields in CRB Register B
511 */
512#ifndef __ASSEMBLY__
513typedef union icrbb_u {
514 u64 reg_value;
515 struct {
516 u64 rsvd1: 5,
517 btenum: 1, /* BTE to which entry belongs to */
518 cohtrans: 1, /* Coherent transaction */
519 xtsize: 2, /* Xtalk operation size
520 * 0: Double Word
521 * 1: 32 Bytes.
522 * 2: 128 Bytes,
523 * 3: Reserved.
524 */
525 srcnode: 9, /* Source Node ID */
526 srcinit: 2, /* Source Initiator:
527 * See below for field values.
528 */
529 useold: 1, /* Use OLD command for processing */
530 imsgtype: 2, /* Incoming message type
531 * see below for field values
532 */
533 imsg: 8, /* Incoming message */
534 initator: 3, /* Initiator of original request
535 * See below for field values.
536 */
537 reqtype: 5, /* Identifies type of request
538 * See below for field values.
539 */
540 rsvd2: 7,
541 ackcnt: 11, /* Invalidate ack count */
542 resp: 1, /* data response given to processor */
543 ack: 1, /* indicates data ack received */
544 hold: 1, /* entry is gathering inval acks */
545 wb_pend:1, /* waiting for writeback to complete */
546 intvn: 1, /* Intervention */
547 stall_ib: 1, /* Stall Ibuf (from crosstalk) */
548 stall_intr: 1; /* Stall internal interrupts */
549 } icrbb_field_s;
550} icrbb_t;
551
552/* This is an alternate typedef for the HUB1 CRB B in order to allow
553 runtime selection of the format based on the REV_ID field of the
554 NI_STATUS_REV_ID register. */
555typedef union h1_icrbb_u {
556 u64 reg_value;
557 struct {
558 u64 rsvd1: 5,
559 btenum: 1, /* BTE to which entry belongs to */
560 cohtrans: 1, /* Coherent transaction */
561 xtsize: 2, /* Xtalk operation size
562 * 0: Double Word
563 * 1: 32 Bytes.
564 * 2: 128 Bytes,
565 * 3: Reserved.
566 */
567 srcnode: 9, /* Source Node ID */
568 srcinit: 2, /* Source Initiator:
569 * See below for field values.
570 */
571 useold: 1, /* Use OLD command for processing */
572 imsgtype: 2, /* Incoming message type
573 * see below for field values
574 */
575 imsg: 8, /* Incoming message */
576 initator: 3, /* Initiator of original request
577 * See below for field values.
578 */
579 rsvd2: 1,
580 pcache: 1, /* entry belongs to partial cache */
581 reqtype: 5, /* Identifies type of request
582 * See below for field values.
583 */
584 stl_ib: 1, /* stall Ibus coming from xtalk */
585 stl_intr: 1, /* Stall internal interrupts */
586 stl_bte0: 1, /* Stall BTE 0 */
587 stl_bte1: 1, /* Stall BTE 1 */
588 intrvn: 1, /* Req was target of intervention */
589 ackcnt: 11, /* Invalidate ack count */
590 resp: 1, /* data response given to processor */
591 ack: 1, /* indicates data ack received */
592 hold: 1, /* entry is gathering inval acks */
593 wb_pend:1, /* waiting for writeback to complete */
594 sleep: 1, /* xtalk req sleeping till IO-sync */
595 pnd_reply: 1, /* replies not issed due to IOQ full */
596 pnd_req: 1; /* reqs not issued due to IOQ full */
597 } h1_icrbb_field_s;
598} h1_icrbb_t;
599
600
601#define b_imsgtype icrbb_field_s.imsgtype
602#define b_btenum icrbb_field_s.btenum
603#define b_cohtrans icrbb_field_s.cohtrans
604#define b_xtsize icrbb_field_s.xtsize
605#define b_srcnode icrbb_field_s.srcnode
606#define b_srcinit icrbb_field_s.srcinit
607#define b_imsgtype icrbb_field_s.imsgtype
608#define b_imsg icrbb_field_s.imsg
609#define b_initiator icrbb_field_s.initiator
610
611#endif /* !__ASSEMBLY__ */
612
613/*
614 * values for field xtsize
615 */
616#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */
617#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */
618#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */
619
620/*
621 * values for field srcinit
622 */
623#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
624#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
625#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */
626#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
627
628/*
629 * Values for field imsgtype
630 */
631#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
632#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
633#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
634#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
635
636/*
637 * values for field initiator.
638 */
639#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
640#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
641#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */
642#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
643#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
644
645/*
646 * Values for field reqtype.
647 */
648/* XXX - Need to fix this for Hub 2 */
649#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */
650#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */
651#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */
652#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */
653#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */
654#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */
655#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */
656#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */
657#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */
658#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */
659#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */
660#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */
661#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */
662#define IIO_ICRB_REQ_WB 16 /* Request is Write back */
663#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */
664
665/*
666 * Fields in CRB Register C
667 */
668
669#ifndef __ASSEMBLY__
670
671typedef union icrbc_s {
672 u64 reg_value;
673 struct {
674 u64 rsvd: 6,
675 sleep: 1,
676 pricnt: 4, /* Priority count sent with Read req */
677 pripsc: 4, /* Priority Pre scalar */
678 bteop: 1, /* BTE Operation */
679 push_be: 34, /* Push address Byte enable
680 * Holds push addr, if CRB is for BTE
681 * If CRB belongs to Partial cache,
682 * this contains byte enables bits
683 * ([47:46] = 0)
684 */
685 suppl: 11, /* Supplemental field */
686 barrop: 1, /* Barrier Op bit set in xtalk req */
687 doresp: 1, /* Xtalk req needs a response */
688 gbr: 1; /* GBR bit set in xtalk packet */
689 } icrbc_field_s;
690} icrbc_t;
691
692#define c_pricnt icrbc_field_s.pricnt
693#define c_pripsc icrbc_field_s.pripsc
694#define c_bteop icrbc_field_s.bteop
695#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */
696#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */
697#define c_suppl icrbc_field_s.suppl
698#define c_barrop icrbc_field_s.barrop
699#define c_doresp icrbc_field_s.doresp
700#define c_gbr icrbc_field_s.gbr
701#endif /* !__ASSEMBLY__ */
702
703/*
704 * Fields in CRB Register D
705 */
706
707#ifndef __ASSEMBLY__
708typedef union icrbd_s {
709 u64 reg_value;
710 struct {
711 u64 rsvd: 38,
712 toutvld: 1, /* Timeout in progress for this CRB */
713 ctxtvld: 1, /* Context field below is valid */
714 rsvd2: 1,
715 context: 15, /* Bit vector:
716 * Has a bit set for each CRB entry
717 * which needs to be deallocated
718 * before this CRB entry is processed.
719 * Set only for barrier operations.
720 */
721 timeout: 8; /* Timeout Upper 8 bits */
722 } icrbd_field_s;
723} icrbd_t;
724
725#define icrbd_toutvld icrbd_field_s.toutvld
726#define icrbd_ctxtvld icrbd_field_s.ctxtvld
727#define icrbd_context icrbd_field_s.context
728
729
730typedef union hubii_ifdr_u {
731 u64 hi_ifdr_value;
732 struct {
733 u64 ifdr_rsvd: 49,
734 ifdr_maxrp: 7,
735 ifdr_rsvd1: 1,
736 ifdr_maxrq: 7;
737 } hi_ifdr_fields;
738} hubii_ifdr_t;
739
740#endif /* !__ASSEMBLY__ */
741
742/*
743 * Hardware designed names for the BTE control registers.
744 */
745#define IIO_IBLS_0 0x410000 /* BTE length/status 0 */
746#define IIO_IBSA_0 0x410008 /* BTE source address 0 */
747#define IIO_IBDA_0 0x410010 /* BTE destination address 0 */
748#define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */
749#define IIO_IBNA_0 0x410020 /* BTE notification address 0 */
750#define IIO_IBNR_0 IIO_IBNA_0
751#define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */
752
753#define IIO_IBLS_1 0x420000 /* BTE length/status 1 */
754#define IIO_IBSA_1 0x420008 /* BTE source address 1 */
755#define IIO_IBDA_1 0x420010 /* BTE destination address 1 */
756#define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */
757#define IIO_IBNA_1 0x420020 /* BTE notification address 1 */
758#define IIO_IBNR_1 IIO_IBNA_1
759#define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */
760
761/*
762 * More miscellaneous registers
763 */
764#define IIO_IPCR 0x430000 /* Performance Control */
765#define IIO_IPPR 0x430008 /* Performance Profiling */
766
767/*
768 * IO Error Clear register bit field definitions
769 */
770#define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */
771#define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */
772#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
773#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
774#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
775#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
776#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
777#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
778#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
779#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
780#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
781#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
782
783/*
784 * IO PIO Read Table Entry format
785 */
786
787#ifndef __ASSEMBLY__
788
789typedef union iprte_a {
790 u64 entry;
791 struct {
792 u64 rsvd1 : 7, /* Reserved field */
793 valid : 1, /* Maps to a timeout entry */
794 rsvd2 : 1,
795 srcnode : 9, /* Node which did this PIO */
796 initiator : 2, /* If T5A or T5B or IO */
797 rsvd3 : 3,
798 addr : 38, /* Physical address of PIO */
799 rsvd4 : 3;
800 } iprte_fields;
801} iprte_a_t;
802
803#define iprte_valid iprte_fields.valid
804#define iprte_timeout iprte_fields.timeout
805#define iprte_srcnode iprte_fields.srcnode
806#define iprte_init iprte_fields.initiator
807#define iprte_addr iprte_fields.addr
808
809#endif /* !__ASSEMBLY__ */
810
811#define IPRTE_ADDRSHFT 3
812
813/*
814 * Hub IIO PRB Register format.
815 */
816
817#ifndef __ASSEMBLY__
818/*
819 * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
820 * "Status" fields, and should only be used in case of clean up after errors.
821 */
822
823typedef union iprb_u {
824 u64 reg_value;
825 struct {
826 u64 rsvd1: 15,
827 error: 1, /* Widget rcvd wr resp pkt w/ error */
828 ovflow: 5, /* Over flow count. perf measurement */
829 fire_and_forget: 1, /* Launch Write without response */
830 mode: 2, /* Widget operation Mode */
831 rsvd2: 2,
832 bnakctr: 14,
833 rsvd3: 2,
834 anakctr: 14,
835 xtalkctr: 8;
836 } iprb_fields_s;
837} iprb_t;
838
839#define iprb_regval reg_value
840
841#define iprb_error iprb_fields_s.error
842#define iprb_ovflow iprb_fields_s.ovflow
843#define iprb_ff iprb_fields_s.fire_and_forget
844#define iprb_mode iprb_fields_s.mode
845#define iprb_bnakctr iprb_fields_s.bnakctr
846#define iprb_anakctr iprb_fields_s.anakctr
847#define iprb_xtalkctr iprb_fields_s.xtalkctr
848
849#endif /* !__ASSEMBLY__ */
850
851/*
852 * values for mode field in iprb_t.
853 * For details of the meanings of NAK and Accept, refer the PIO flow
854 * document
855 */
856#define IPRB_MODE_NORMAL (0)
857#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
858#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
859#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
860
861/*
862 * IO CRB entry C_A to E_A : Partial (cache) CRBS
863 */
864#ifndef __ASSEMBLY__
865typedef union icrbp_a {
866 u64 ip_reg; /* the entire register value */
867 struct {
868 u64 error: 1, /* 63, error occurred */
869 ln_uce: 1, /* 62: uncorrectable memory */
870 ln_ae: 1, /* 61: protection violation */
871 ln_werr:1, /* 60: write access error */
872 ln_aerr:1, /* 59: sn0net: Address error */
873 ln_perr:1, /* 58: sn0net: poison error */
874 timeout:1, /* 57: CRB timed out */
875 l_bdpkt:1, /* 56: truncated pkt on sn0net */
876 c_bdpkt:1, /* 55: truncated pkt on xtalk */
877 c_err: 1, /* 54: incoming xtalk req, err set*/
878 rsvd1: 12, /* 53-42: reserved */
879 valid: 1, /* 41: Valid status */
880 sidn: 4, /* 40-37: SIDN field of xtalk rqst */
881 tnum: 5, /* 36-32: TNUM of xtalk request */
882 bo: 1, /* 31: barrier op set in xtalk rqst*/
883 resprqd:1, /* 30: xtalk rqst requires response*/
884 gbr: 1, /* 29: gbr bit set in xtalk rqst */
885 size: 2, /* 28-27: size of xtalk request */
886 excl: 4, /* 26-23: exclusive bit(s) */
887 stall: 3, /* 22-20: stall (xtalk, bte 0/1) */
888 intvn: 1, /* 19: rqst target of intervention*/
889 resp: 1, /* 18: Data response given to t5 */
890 ack: 1, /* 17: Data ack received. */
891 hold: 1, /* 16: crb gathering invalidate acks*/
892 wb: 1, /* 15: writeback pending. */
893 ack_cnt:11, /* 14-04: counter of invalidate acks*/
894 tscaler:4; /* 03-00: Timeout prescaler */
895 } ip_fmt;
896} icrbp_a_t;
897
898#endif /* !__ASSEMBLY__ */
899
900/*
901 * A couple of defines to go with the above structure.
902 */
903#define ICRBP_A_CERR_SHFT 54
904#define ICRBP_A_ERR_MASK 0x3ff
905
906#ifndef __ASSEMBLY__
907typedef union hubii_idsr {
908 u64 iin_reg;
909 struct {
910 u64 rsvd1 : 35,
911 isent : 1,
912 rsvd2 : 3,
913 ienable: 1,
914 rsvd : 7,
915 node : 9,
916 rsvd4 : 1,
917 level : 7;
918 } iin_fmt;
919} hubii_idsr_t;
920#endif /* !__ASSEMBLY__ */
921
922/*
923 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
924 */
925#define IBLS_BUSY (0x1 << 20)
926#define IBLS_ERROR_SHFT 16
927#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
928#define IBLS_LENGTH_MASK 0xffff
929
930/*
931 * IO BTE Control/Terminate register (IBCT) register bit field definitions
932 */
933#define IBCT_POISON (0x1 << 8)
934#define IBCT_NOTIFY (0x1 << 4)
935#define IBCT_ZFIL_MODE (0x1 << 0)
936
937/*
938 * IO BTE Interrupt Address Register (IBIA) register bit field definitions
939 */
940#define IBIA_LEVEL_SHFT 16
941#define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT)
942#define IBIA_NODE_ID_SHFT 0
943#define IBIA_NODE_ID_MASK (0x1ff)
944
945/*
946 * Miscellaneous hub constants
947 */
948
949/* Number of widgets supported by hub */
950#define HUB_NUM_WIDGET 9
951#define HUB_WIDGET_ID_MIN 0x8
952#define HUB_WIDGET_ID_MAX 0xf
953
954#define HUB_WIDGET_PART_NUM 0xc101
955#define MAX_HUBS_PER_XBOW 2
956
957/*
958 * Get a hub's widget id from widget control register
959 */
960#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
961#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
962
963/*
964 * Number of credits Hub widget has while sending req/response to
965 * xbow.
966 * Value of 3 is required by Xbow 1.1
967 * We may be able to increase this to 4 with Xbow 1.2.
968 */
969#define HUBII_XBOW_CREDIT 3
970#define HUBII_XBOW_REV2_CREDIT 4
971
972#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h
deleted file mode 100644
index 14c225d80664..000000000000
--- a/include/asm-mips/sn/sn0/hubmd.h
+++ /dev/null
@@ -1,789 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_HUBMD_H
12#define _ASM_SN_SN0_HUBMD_H
13
14
15/*
16 * Hub Memory/Directory interface registers
17 */
18#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */
19
20#define MAX_REGIONS 64
21
22/* Hardware page size and shift */
23
24#define MD_PAGE_SIZE 4096 /* Page size in bytes */
25#define MD_PAGE_NUM_SHFT 12 /* Address to page number shift */
26
27/* Register offsets from LOCAL_HUB or REMOTE_HUB */
28
29#define MD_BASE 0x200000
30#define MD_BASE_PERF 0x210000
31#define MD_BASE_JUNK 0x220000
32
33#define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34#define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35#define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36#define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
40#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */
41#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */
42#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */
43#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */
44#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */
45#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */
46#define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */
47#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */
48#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */
49#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */
50#define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */
51#define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */
52#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */
53#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */
54#define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */
55
56#define MD_PERF_SEL 0x210000 /* Select perf monitor events */
57#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */
58#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */
59#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */
60#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */
61#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */
62#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */
63
64#define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65#define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66#define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67#define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68#define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69#define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70#define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71#define MD_UREG0_7 0x220038 /* uController/UART 0 register */
72
73#define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
74#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
75#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
76
77#define MD_UREG1_0 0x220080 /* uController/UART 1 register */
78#define MD_UREG1_1 0x220088 /* uController/UART 1 register */
79#define MD_UREG1_2 0x220090 /* uController/UART 1 register */
80#define MD_UREG1_3 0x220098 /* uController/UART 1 register */
81#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
82#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
83#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
84#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
85#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
86#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
87#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
88#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
89#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
90#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
91#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
93
94#ifdef CONFIG_SGI_SN_N_MODE
95#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
96#else
97#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
98#endif
99
100/*
101 * MD_MEMORY_CONFIG fields
102 *
103 * MD_SIZE_xxx are useful for representing the size of a SIMM or bank
104 * (SIMM pair). They correspond to the values needed for the bit
105 * triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
106 * Bits not used by the MD are used by software.
107 */
108
109#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */
110#define MD_SIZE_8MB 1
111#define MD_SIZE_16MB 2
112#define MD_SIZE_32MB 3 /* Broken in Hub 1 */
113#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */
114#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */
115#define MD_SIZE_256MB 6
116#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */
117#define MD_SIZE_1GB 8
118#define MD_SIZE_2GB 9
119#define MD_SIZE_4GB 10
120
121#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
122#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
123
124#define MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */
125#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
126#define MMC_FPROM_WR_SHFT 44 /* for assembler */
127#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
128#define MMC_UCTLR_CYC_SHFT 39
129#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
130#define MMC_UCTLR_WR_SHFT 34
131#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
132#define MMC_DIMM0_SEL_SHFT 32
133#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
134#define MMC_IO_PROT_EN_SHFT 31
135#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
136#define MMC_IO_PROT (UINT64_CAST 1 << 31)
137#define MMC_ARB_MLSS_SHFT 30
138#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
139#define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
140#define MMC_IGNORE_ECC_SHFT 29
141#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
142#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
143#define MMC_DIR_PREMIUM_SHFT 28
144#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
145#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
146#define MMC_REPLY_GUAR_SHFT 24
147#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
148#define MMC_BANK_SHFT(_b) ((_b) * 3)
149#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
150#define MMC_BANK_ALL_MASK 0xffffff
151#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
152 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
153 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
154 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
155 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
156 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
157 MMC_BANK_ALL_MASK)
158
159/* MD_REFRESH_CONTROL fields */
160
161#define MRC_ENABLE_SHFT 63
162#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
163#define MRC_ENABLE (UINT64_CAST 1 << 63)
164#define MRC_COUNTER_SHFT 12
165#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
166#define MRC_CNT_THRESH_MASK 0xfff
167#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
168
169/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
170
171#define MDI_SELECT_SHFT 32
172#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
173#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
174
175/* MD_MOQ_SIZE fields */
176
177#define MMS_RP_SIZE_SHFT 8
178#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
179#define MMS_RQ_SIZE_SHFT 0
180#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
181#define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12)
182
183/* MD_FANDOP_CAC_STAT fields */
184
185#define MFC_VALID_SHFT 63
186#define MFC_VALID_MASK (UINT64_CAST 1 << 63)
187#define MFC_VALID (UINT64_CAST 1 << 63)
188#define MFC_ADDR_SHFT 6
189#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
190
191/* MD_MLAN_CTL fields */
192
193#define MLAN_PHI1_SHFT 27
194#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
195#define MLAN_PHI0_SHFT 20
196#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
197#define MLAN_PULSE_SHFT 10
198#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
199#define MLAN_SAMPLE_SHFT 2
200#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
201#define MLAN_DONE_SHFT 1
202#define MLAN_DONE_MASK 2
203#define MLAN_DONE (UINT64_CAST 0x02)
204#define MLAN_RD_DATA (UINT64_CAST 0x01)
205#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
206 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
207
208/* MD_SLOTID_USTAT bit definitions */
209
210#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */
211#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
212#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
213#define MSU_CORECLK_SHFT 6 /* You don't wanna know */
214#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
215#define MSU_CORECLK (UINT64_CAST 1 << 6)
216#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */
217#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
218#define MSU_NETSYNC (UINT64_CAST 1 << 5)
219#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */
220#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
221#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
222#define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */
223#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
224#define MSU_I2CINTR (UINT64_CAST 1 << 3)
225#define MSU_SLOTID_MASK 0xff
226#define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */
227#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
228#define MSU_SN00_SLOTID_SHFT 7
229#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
230
231#define MSU_PIMM_PSC_SHFT 4
232#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT)
233
234/* MD_MIG_DIFF_THRESH bit definitions */
235
236#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
237#define MD_MIG_DIFF_THRES_VALID_SHFT 63
238#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
239
240/* MD_MIG_VALUE_THRESH bit definitions */
241
242#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
243#define MD_MIG_VALUE_THRES_VALID_SHFT 63
244#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
245
246/* MD_MIG_CANDIDATE bit definitions */
247
248#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
249#define MD_MIG_CANDIDATE_VALID_SHFT 63
250#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
251#define MD_MIG_CANDIDATE_TYPE_SHFT 30
252#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
253#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
254#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
255#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
256#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
257#define MD_MIG_CANDIDATE_NODEID_SHFT 20
258#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
259#define MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */
260
261/* Other MD definitions */
262
263#define MD_BANK_SHFT 29 /* log2(512 MB) */
264#define MD_BANK_MASK (UINT64_CAST 7 << 29)
265#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
266#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
267
268/*
269 * The following definitions cover the bit field definitions for the
270 * various MD registers. For multi-bit registers, we define both
271 * a shift amount and a mask value. By convention, if you want to
272 * isolate a field, you should mask the field and then shift it down,
273 * since this makes the masks useful without a shift.
274 */
275
276/* Directory entry states for both premium and standard SIMMs. */
277
278#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
279#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
280#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
281#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
282#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
283#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
284#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
285
286/*
287 * The MD_DIR_FORCE_ECC bit can be added directory entry write data
288 * to forcing the ECC to be written as-is instead of recalculated.
289 */
290
291#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
292
293/*
294 * Premium SIMM directory entry shifts and masks. Each is valid only in the
295 * context(s) indicated, where A, B, and C indicate the directory entry format
296 * as shown, and low and/or high indicates which double-word of the entry.
297 *
298 * Format A: STATE = shared, FINE = 1
299 * Format B: STATE = shared, FINE = 0
300 * Format C: STATE != shared (FINE must be 0)
301 */
302
303#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */
304#define MD_PDIR_ECC_SHFT 0 /* ABC low or high */
305#define MD_PDIR_ECC_MASK 0x7f
306#define MD_PDIR_PRIO_SHFT 8 /* ABC low */
307#define MD_PDIR_PRIO_MASK (0xf << 8)
308#define MD_PDIR_AX_SHFT 7 /* ABC low */
309#define MD_PDIR_AX_MASK (1 << 7)
310#define MD_PDIR_AX (1 << 7)
311#define MD_PDIR_FINE_SHFT 12 /* ABC low */
312#define MD_PDIR_FINE_MASK (1 << 12)
313#define MD_PDIR_FINE (1 << 12)
314#define MD_PDIR_OCT_SHFT 13 /* A low */
315#define MD_PDIR_OCT_MASK (7 << 13)
316#define MD_PDIR_STATE_SHFT 13 /* BC low */
317#define MD_PDIR_STATE_MASK (7 << 13)
318#define MD_PDIR_ONECNT_SHFT 16 /* BC low */
319#define MD_PDIR_ONECNT_MASK (0x3f << 16)
320#define MD_PDIR_PTR_SHFT 22 /* C low */
321#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
322#define MD_PDIR_VECMSB_SHFT 22 /* AB low */
323#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
324#define MD_PDIR_VECMSB_BITSHFT 27
325#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
326#define MD_PDIR_CWOFF_SHFT 7 /* C high */
327#define MD_PDIR_CWOFF_MASK (7 << 7)
328#define MD_PDIR_VECLSB_SHFT 10 /* AB high */
329#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
330#define MD_PDIR_VECLSB_BITSHFT 0
331#define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10)
332
333/*
334 * Directory initialization values
335 */
336
337#define MD_PDIR_INIT_LO (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
338 MD_PDIR_AX)
339#define MD_PDIR_INIT_HI 0
340#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | \
341 MD_PROT_RW << MD_PPROT_SHFT)
342
343/*
344 * Standard SIMM directory entry shifts and masks. Each is valid only in the
345 * context(s) indicated, where A and C indicate the directory entry format
346 * as shown, and low and/or high indicates which double-word of the entry.
347 *
348 * Format A: STATE == shared
349 * Format C: STATE != shared
350 */
351
352#define MD_SDIR_MASK 0xffff /* Whole entry */
353#define MD_SDIR_ECC_SHFT 0 /* AC low or high */
354#define MD_SDIR_ECC_MASK 0x1f
355#define MD_SDIR_PRIO_SHFT 6 /* AC low */
356#define MD_SDIR_PRIO_MASK (1 << 6)
357#define MD_SDIR_AX_SHFT 5 /* AC low */
358#define MD_SDIR_AX_MASK (1 << 5)
359#define MD_SDIR_AX (1 << 5)
360#define MD_SDIR_STATE_SHFT 7 /* AC low */
361#define MD_SDIR_STATE_MASK (7 << 7)
362#define MD_SDIR_PTR_SHFT 10 /* C low */
363#define MD_SDIR_PTR_MASK (0x3f << 10)
364#define MD_SDIR_CWOFF_SHFT 5 /* C high */
365#define MD_SDIR_CWOFF_MASK (7 << 5)
366#define MD_SDIR_VECMSB_SHFT 11 /* A low */
367#define MD_SDIR_VECMSB_BITMASK 0x1f
368#define MD_SDIR_VECMSB_BITSHFT 7
369#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
370#define MD_SDIR_VECLSB_SHFT 5 /* A high */
371#define MD_SDIR_VECLSB_BITMASK 0x7ff
372#define MD_SDIR_VECLSB_BITSHFT 0
373#define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5)
374
375/*
376 * Directory initialization values
377 */
378
379#define MD_SDIR_INIT_LO (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
380 MD_SDIR_AX)
381#define MD_SDIR_INIT_HI 0
382#define MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT)
383
384/* Protection and migration field values */
385
386#define MD_PROT_RW (UINT64_CAST 0x6)
387#define MD_PROT_RO (UINT64_CAST 0x3)
388#define MD_PROT_NO (UINT64_CAST 0x0)
389#define MD_PROT_BAD (UINT64_CAST 0x5)
390
391/* Premium SIMM protection entry shifts and masks. */
392
393#define MD_PPROT_SHFT 0 /* Prot. field */
394#define MD_PPROT_MASK 7
395#define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */
396#define MD_PPROT_MIGMD_MASK (3 << 3)
397#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */
398#define MD_PPROT_REFCNT_WIDTH 0x7ffff
399#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
400
401#define MD_PPROT_IO_SHFT 45 /* I/O Prot field */
402#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
403
404/* Standard SIMM protection entry shifts and masks. */
405
406#define MD_SPROT_SHFT 0 /* Prot. field */
407#define MD_SPROT_MASK 7
408#define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */
409#define MD_SPROT_MIGMD_MASK (3 << 3)
410#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */
411#define MD_SPROT_REFCNT_WIDTH 0x7ff
412#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)
413
414/* Migration modes used in protection entries */
415
416#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
417#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
418#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
419#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
420
421
422/*
423 * Operations on page migration threshold register
424 */
425
426#ifndef __ASSEMBLY__
427
428/*
429 * LED register macros
430 */
431
432#define CPU_LED_ADDR(_nasid, _slice) \
433 (private.p_sn00 ? \
434 REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \
435 REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3)))
436
437#define SET_CPU_LEDS(_nasid, _slice, _val) \
438 (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
439
440#define SET_MY_LEDS(_v) \
441 SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
442
443/*
444 * Operations on Memory/Directory DIMM control register
445 */
446
447#define DIRTYPE_PREMIUM 1
448#define DIRTYPE_STANDARD 0
449#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
450 (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
451 MMC_DIR_PREMIUM_SHFT)
452
453
454/*
455 * Operations on page migration count difference and absolute threshold
456 * registers
457 */
458
459#define MD_MIG_DIFF_THRESH_GET(region) ( \
460 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
461 MD_MIG_DIFF_THRES_VALUE_MASK)
462
463#define MD_MIG_DIFF_THRESH_SET(region, value) ( \
464 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
465 MD_MIG_DIFF_THRES_VALID_MASK | (value)))
466
467#define MD_MIG_DIFF_THRESH_DISABLE(region) ( \
468 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
469 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
470 & ~MD_MIG_DIFF_THRES_VALID_MASK))
471
472#define MD_MIG_DIFF_THRESH_ENABLE(region) ( \
473 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
474 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
475 | MD_MIG_DIFF_THRES_VALID_MASK))
476
477#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) ( \
478 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
479 MD_MIG_DIFF_THRES_VALID_MASK)
480
481#define MD_MIG_VALUE_THRESH_GET(region) ( \
482 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
483 MD_MIG_VALUE_THRES_VALUE_MASK)
484
485#define MD_MIG_VALUE_THRESH_SET(region, value) ( \
486 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
487 MD_MIG_VALUE_THRES_VALID_MASK | (value)))
488
489#define MD_MIG_VALUE_THRESH_DISABLE(region) ( \
490 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
491 REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH) \
492 & ~MD_MIG_VALUE_THRES_VALID_MASK))
493
494#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \
495 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
496 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \
497 | MD_MIG_VALUE_THRES_VALID_MASK))
498
499#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) ( \
500 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
501 MD_MIG_VALUE_THRES_VALID_MASK)
502
503/*
504 * Operations on page migration candidate register
505 */
506
507#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
508 REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
509
510#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
511
512#define MD_MIG_CANDIDATE_NODEID(value) ( \
513 ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
514
515#define MD_MIG_CANDIDATE_TYPE(value) ( \
516 ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
517
518#define MD_MIG_CANDIDATE_VALID(value) ( \
519 ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
520
521/*
522 * Macros to retrieve fields in the protection entry
523 */
524
525/* for Premium SIMM */
526#define MD_PPROT_REFCNT_GET(value) ( \
527 ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
528
529#define MD_PPROT_MIGMD_GET(value) ( \
530 ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
531
532/* for Standard SIMM */
533#define MD_SPROT_REFCNT_GET(value) ( \
534 ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
535
536#define MD_SPROT_MIGMD_GET(value) ( \
537 ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
538
539/*
540 * Format of dir_error, mem_error, protocol_error and misc_error registers
541 */
542
543struct dir_error_reg {
544 u64 uce_vld: 1, /* 63: valid directory uce */
545 ae_vld: 1, /* 62: valid dir prot ecc error */
546 ce_vld: 1, /* 61: valid correctable ECC err*/
547 rsvd1: 19, /* 60-42: reserved */
548 bad_prot: 3, /* 41-39: encoding, bad access rights*/
549 bad_syn: 7, /* 38-32: bad dir syndrome */
550 rsvd2: 2, /* 31-30: reserved */
551 hspec_addr:27, /* 29-03: bddir space bad entry */
552 uce_ovr: 1, /* 2: multiple dir uce's */
553 ae_ovr: 1, /* 1: multiple prot ecc errs*/
554 ce_ovr: 1; /* 0: multiple correctable errs */
555};
556
557typedef union md_dir_error {
558 u64 derr_reg; /* the entire register */
559 struct dir_error_reg derr_fmt; /* the register format */
560} md_dir_error_t;
561
562
563struct mem_error_reg {
564 u64 uce_vld: 1, /* 63: valid memory uce */
565 ce_vld: 1, /* 62: valid correctable ECC err*/
566 rsvd1: 22, /* 61-40: reserved */
567 bad_syn: 8, /* 39-32: bad mem ecc syndrome */
568 address: 29, /* 31-03: bad entry pointer */
569 rsvd2: 1, /* 2: reserved */
570 uce_ovr: 1, /* 1: multiple mem uce's */
571 ce_ovr: 1; /* 0: multiple correctable errs */
572};
573
574
575typedef union md_mem_error {
576 u64 merr_reg; /* the entire register */
577 struct mem_error_reg merr_fmt; /* format of the mem_error reg */
578} md_mem_error_t;
579
580
581struct proto_error_reg {
582 u64 valid: 1, /* 63: valid protocol error */
583 rsvd1: 2, /* 62-61: reserved */
584 initiator:11, /* 60-50: id of request initiator*/
585 backoff: 2, /* 49-48: backoff control */
586 msg_type: 8, /* 47-40: type of request */
587 access: 2, /* 39-38: access rights of initiator*/
588 priority: 1, /* 37: priority level of requestor*/
589 dir_state: 4, /* 36-33: state of directory */
590 pointer_me:1, /* 32: initiator same as dir ptr */
591 address: 29, /* 31-03: request address */
592 rsvd2: 2, /* 02-01: reserved */
593 overrun: 1; /* 0: multiple protocol errs */
594};
595
596typedef union md_proto_error {
597 u64 perr_reg; /* the entire register */
598 struct proto_error_reg perr_fmt; /* format of the register */
599} md_proto_error_t;
600
601
602struct md_sdir_high_fmt {
603 unsigned short sd_hi_bvec : 11,
604 sd_hi_ecc : 5;
605};
606
607
608typedef union md_sdir_high {
609 /* The 16 bits of standard directory, upper word */
610 unsigned short sd_hi_val;
611 struct md_sdir_high_fmt sd_hi_fmt;
612}md_sdir_high_t;
613
614
615struct md_sdir_low_shared_fmt {
616 /* The meaning of lower directory, shared */
617 unsigned short sds_lo_bvec : 5,
618 sds_lo_unused: 1,
619 sds_lo_state : 3,
620 sds_lo_prio : 1,
621 sds_lo_ax : 1,
622 sds_lo_ecc : 5;
623};
624
625struct md_sdir_low_exclusive_fmt {
626 /* The meaning of lower directory, exclusive */
627 unsigned short sde_lo_ptr : 6,
628 sde_lo_state : 3,
629 sde_lo_prio : 1,
630 sde_lo_ax : 1,
631 sde_lo_ecc : 5;
632};
633
634
635typedef union md_sdir_low {
636 /* The 16 bits of standard directory, lower word */
637 unsigned short sd_lo_val;
638 struct md_sdir_low_exclusive_fmt sde_lo_fmt;
639 struct md_sdir_low_shared_fmt sds_lo_fmt;
640}md_sdir_low_t;
641
642
643
644struct md_pdir_high_fmt {
645 u64 pd_hi_unused : 16,
646 pd_hi_bvec : 38,
647 pd_hi_unused1 : 3,
648 pd_hi_ecc : 7;
649};
650
651
652typedef union md_pdir_high {
653 /* The 48 bits of standard directory, upper word */
654 u64 pd_hi_val;
655 struct md_pdir_high_fmt pd_hi_fmt;
656}md_pdir_high_t;
657
658
659struct md_pdir_low_shared_fmt {
660 /* The meaning of lower directory, shared */
661 u64 pds_lo_unused : 16,
662 pds_lo_bvec : 26,
663 pds_lo_cnt : 6,
664 pds_lo_state : 3,
665 pds_lo_ste : 1,
666 pds_lo_prio : 4,
667 pds_lo_ax : 1,
668 pds_lo_ecc : 7;
669};
670
671struct md_pdir_low_exclusive_fmt {
672 /* The meaning of lower directory, exclusive */
673 u64 pde_lo_unused : 31,
674 pde_lo_ptr : 11,
675 pde_lo_unused1 : 6,
676 pde_lo_state : 3,
677 pde_lo_ste : 1,
678 pde_lo_prio : 4,
679 pde_lo_ax : 1,
680 pde_lo_ecc : 7;
681};
682
683
684typedef union md_pdir_loent {
685 /* The 48 bits of premium directory, lower word */
686 u64 pd_lo_val;
687 struct md_pdir_low_exclusive_fmt pde_lo_fmt;
688 struct md_pdir_low_shared_fmt pds_lo_fmt;
689}md_pdir_low_t;
690
691
692/*
693 * the following two "union" definitions and two
694 * "struct" definitions are used in vmdump.c to
695 * represent directory memory information.
696 */
697
698typedef union md_dir_high {
699 md_sdir_high_t md_sdir_high;
700 md_pdir_high_t md_pdir_high;
701} md_dir_high_t;
702
703typedef union md_dir_low {
704 md_sdir_low_t md_sdir_low;
705 md_pdir_low_t md_pdir_low;
706} md_dir_low_t;
707
708typedef struct bddir_entry {
709 md_dir_low_t md_dir_low;
710 md_dir_high_t md_dir_high;
711} bddir_entry_t;
712
713typedef struct dir_mem_entry {
714 u64 prcpf[MAX_REGIONS];
715 bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
716} dir_mem_entry_t;
717
718
719
720typedef union md_perf_sel {
721 u64 perf_sel_reg;
722 struct {
723 u64 perf_rsvd : 60,
724 perf_en : 1,
725 perf_sel : 3;
726 } perf_sel_bits;
727} md_perf_sel_t;
728
729typedef union md_perf_cnt {
730 u64 perf_cnt;
731 struct {
732 u64 perf_rsvd : 44,
733 perf_cnt : 20;
734 } perf_cnt_bits;
735} md_perf_cnt_t;
736
737
738#endif /* !__ASSEMBLY__ */
739
740
741#define DIR_ERROR_VALID_MASK 0xe000000000000000
742#define DIR_ERROR_VALID_SHFT 61
743#define DIR_ERROR_VALID_UCE 0x8000000000000000
744#define DIR_ERROR_VALID_AE 0x4000000000000000
745#define DIR_ERROR_VALID_CE 0x2000000000000000
746
747#define MEM_ERROR_VALID_MASK 0xc000000000000000
748#define MEM_ERROR_VALID_SHFT 62
749#define MEM_ERROR_VALID_UCE 0x8000000000000000
750#define MEM_ERROR_VALID_CE 0x4000000000000000
751
752#define PROTO_ERROR_VALID_MASK 0x8000000000000000
753
754#define MISC_ERROR_VALID_MASK 0x3ff
755
756/*
757 * Mask for hspec address that is stored in the dir error register.
758 * This represents bits 29 through 3.
759 */
760#define DIR_ERR_HSPEC_MASK 0x3ffffff8
761#define ERROR_HSPEC_MASK 0x3ffffff8
762#define ERROR_HSPEC_SHFT 3
763#define ERROR_ADDR_MASK 0xfffffff8
764#define ERROR_ADDR_SHFT 3
765
766/*
767 * MD_MISC_ERROR register defines.
768 */
769
770#define MMCE_VALID_MASK 0x3ff
771#define MMCE_ILL_MSG_SHFT 8
772#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
773#define MMCE_ILL_REV_SHFT 6
774#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
775#define MMCE_LONG_PACK_SHFT 4
776#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
777#define MMCE_SHORT_PACK_SHFT 2
778#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
779#define MMCE_BAD_DATA_SHFT 0
780#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
781
782
783#define MD_PERF_COUNTERS 6
784#define MD_PERF_SETS 6
785
786#define MEM_DIMM_MASK 0xe0000000
787#define MEM_DIMM_SHFT 29
788
789#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/include/asm-mips/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h
deleted file mode 100644
index b40d3ef97a12..000000000000
--- a/include/asm-mips/sn/sn0/hubni.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
7 *
8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SGI_SN0_HUBNI_H
12#define _ASM_SGI_SN0_HUBNI_H
13
14#ifndef __ASSEMBLY__
15#include <linux/types.h>
16#endif
17
18/*
19 * Hub Network Interface registers
20 *
21 * All registers in this file are subject to change until Hub chip tapeout.
22 */
23
24#define NI_BASE 0x600000
25#define NI_BASE_TABLES 0x630000
26
27#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
28#define NI_PORT_RESET 0x600008 /* Reset the network interface */
29#define NI_PROTECTION 0x600010 /* NI register access permissions */
30#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
31#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
32#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
33#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
34
35#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
36#define NI_VECTOR 0x600208 /* Vector PIO route */
37#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
38#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
39#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
40#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
41#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
42
43#define NI_IO_PROTECT 0x600400 /* PIO protection bits */
44#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
45
46#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
47#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
48#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
49#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
50#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
51#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
52#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
53#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
54#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
55#define NI_AGE_REG_MAX NI_AGE_IO_PIO
56
57#define NI_PORT_PARMS 0x608000 /* LLP Parameters */
58#define NI_PORT_ERROR 0x608008 /* LLP Errors */
59#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
60
61#define NI_META_TABLE0 0x638000 /* First meta routing table entry */
62#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
63#define NI_META_ENTRIES 32
64
65#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
66#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
67#define NI_LOCAL_ENTRIES 16
68
69/*
70 * NI_STATUS_REV_ID mask and shift definitions
71 * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
72 */
73
74#define NSRI_8BITMODE_SHFT 30
75#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
76#define NSRI_LINKUP_SHFT 29
77#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
78#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
79#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
80#define NSRI_MORENODES_SHFT 18
81#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
82#define MORE_MEMORY 0
83#define MORE_NODES 1
84#define NSRI_REGIONSIZE_SHFT 17
85#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
86#define REGIONSIZE_FINE 1
87#define REGIONSIZE_COARSE 0
88#define NSRI_NODEID_SHFT 8
89#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
90#define NSRI_REV_SHFT 4
91#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
92#define NSRI_CHIPID_SHFT 0
93#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
94
95/*
96 * In fine mode, each node is a region. In coarse mode, there are
97 * eight nodes per region.
98 */
99#define NASID_TO_FINEREG_SHFT 0
100#define NASID_TO_COARSEREG_SHFT 3
101
102/* NI_PORT_RESET mask definitions */
103
104#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
107
108/* NI_PROTECTION mask and shift definitions */
109
110#define NPROT_RESETOK (UINT64_CAST 1)
111
112/* NI_GLOBAL_PARMS mask and shift definitions */
113
114#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */
115#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
116#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */
117#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
118
119#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */
120#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
121#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */
122#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
123
124/* NI_DIAG_PARMS mask and shift definitions */
125
126#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
127#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
128#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
129#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
130
131/*
132 * NI_VECTOR_PARMS mask and shift definitions.
133 * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
134 */
135
136#define NVP_PIOID_SHFT 40
137#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
138#define NVP_WRITEID_SHFT 32
139#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
140#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
141#define NVP_TYPE_SHFT 0
142#define NVP_TYPE_MASK (UINT64_CAST 0x3)
143
144/* NI_VECTOR_STATUS mask and shift definitions */
145
146#define NVS_VALID (UINT64_CAST 1 << 63)
147#define NVS_OVERRUN (UINT64_CAST 1 << 62)
148#define NVS_TARGET_SHFT 51
149#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
150#define NVS_PIOID_SHFT 40
151#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
152#define NVS_WRITEID_SHFT 32
153#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
154#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
155#define NVS_TYPE_SHFT 0
156#define NVS_TYPE_MASK (UINT64_CAST 0x7)
157#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
158
159
160#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
161#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */
162#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */
163#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */
164#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */
165#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */
166#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */
167#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */
168
169/* NI_AGE_XXX mask and shift definitions */
170
171#define NAGE_VCH_SHFT 10
172#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
173#define NAGE_CC_SHFT 8
174#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
175#define NAGE_AGE_SHFT 0
176#define NAGE_AGE_MASK (UINT64_CAST 0xff)
177#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
178
179#define VCHANNEL_A 0
180#define VCHANNEL_B 1
181#define VCHANNEL_ANY 2
182
183/* NI_PORT_PARMS mask and shift definitions */
184
185#define NPP_NULLTO_SHFT 10
186#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
187#define NPP_MAXBURST_SHFT 0
188#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
189#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
190 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
191#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
192 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
193
194
195/* NI_PORT_ERROR mask and shift definitions */
196
197#define NPE_LINKRESET (UINT64_CAST 1 << 37)
198#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
199#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
200#define NPE_BADDEST (UINT64_CAST 1 << 34)
201#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
202#define NPE_CREDITTO_SHFT 28
203#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
204#define NPE_TAILTO_SHFT 24
205#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
206#define NPE_RETRYCOUNT_SHFT 16
207#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
208#define NPE_CBERRCOUNT_SHFT 8
209#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
210#define NPE_SNERRCOUNT_SHFT 0
211#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
212#define NPE_MASK 0x3effffffff
213
214#define NPE_COUNT_MAX 0xff
215
216#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \
217 NPE_BADMESSAGE | NPE_BADDEST | \
218 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
219 NPE_TAILTO_MASK)
220
221/* NI_META_TABLE mask and shift definitions */
222
223#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
224
225/* NI_LOCAL_TABLE mask and shift definitions */
226
227#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
228
229#ifndef __ASSEMBLY__
230
231typedef union hubni_port_error_u {
232 u64 nipe_reg_value;
233 struct {
234 u64 nipe_rsvd: 26, /* unused */
235 nipe_lnk_reset: 1, /* link reset */
236 nipe_intl_err: 1, /* internal error */
237 nipe_bad_msg: 1, /* bad message */
238 nipe_bad_dest: 1, /* bad dest */
239 nipe_fifo_ovfl: 1, /* fifo overflow */
240 nipe_rsvd1: 1, /* unused */
241 nipe_credit_to: 4, /* credit timeout */
242 nipe_tail_to: 4, /* tail timeout */
243 nipe_retry_cnt: 8, /* retry error count */
244 nipe_cb_cnt: 8, /* checkbit error count */
245 nipe_sn_cnt: 8; /* sequence number count */
246 } nipe_fields_s;
247} hubni_port_error_t;
248
249#define NI_LLP_RETRY_MAX 0xff
250#define NI_LLP_CB_MAX 0xff
251#define NI_LLP_SN_MAX 0xff
252
253#endif /* !__ASSEMBLY__ */
254
255#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h
deleted file mode 100644
index e39f5f9da040..000000000000
--- a/include/asm-mips/sn/sn0/hubpi.h
+++ /dev/null
@@ -1,409 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_HUBPI_H
12#define _ASM_SN_SN0_HUBPI_H
13
14#include <linux/types.h>
15
16/*
17 * Hub I/O interface registers
18 *
19 * All registers in this file are subject to change until Hub chip tapeout.
20 * All register "addresses" are actually offsets. Use the LOCAL_HUB
21 * or REMOTE_HUB macros to synthesize an actual address
22 */
23
24#define PI_BASE 0x000000
25
26/* General protection and control registers */
27
28#define PI_CPU_PROTECT 0x000000 /* CPU Protection */
29#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
30#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
31#define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */
32#define PI_CPU_NUM 0x000020 /* CPU Number ID */
33#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */
34#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */
35#define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */
36
37/* CALIAS values */
38#define PI_CALIAS_SIZE_0 0
39#define PI_CALIAS_SIZE_4K 1
40#define PI_CALIAS_SIZE_8K 2
41#define PI_CALIAS_SIZE_16K 3
42#define PI_CALIAS_SIZE_32K 4
43#define PI_CALIAS_SIZE_64K 5
44#define PI_CALIAS_SIZE_128K 6
45#define PI_CALIAS_SIZE_256K 7
46#define PI_CALIAS_SIZE_512K 8
47#define PI_CALIAS_SIZE_1M 9
48#define PI_CALIAS_SIZE_2M 10
49#define PI_CALIAS_SIZE_4M 11
50#define PI_CALIAS_SIZE_8M 12
51#define PI_CALIAS_SIZE_16M 13
52#define PI_CALIAS_SIZE_32M 14
53#define PI_CALIAS_SIZE_64M 15
54
55/* Processor control and status checking */
56
57#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */
58#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */
59#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */
60#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */
61#define PI_REPLY_LEVEL 0x000060 /* Reply Level */
62#define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */
63#define PI_NMI_A 0x000070 /* NMI to CPU A */
64#define PI_NMI_B 0x000078 /* NMI to CPU B */
65#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
66#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */
67
68/* Regular Interrupt register checking. */
69
70#define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */
71#define PI_INT_PEND0 0x000098 /* Read to get pending ints */
72#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */
73#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
77
78#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */
79
80/* Crosscall interrupts */
81
82#define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83#define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
84#define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */
85#define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */
86#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */
87
88#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */
89
90/* Realtime Counter and Profiler control registers */
91
92#define PI_RT_COUNT 0x030100 /* Real Time Counter */
93#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */
94#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */
95#define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */
96#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */
97#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */
98#define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */
99#define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */
100#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */
101#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */
102#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */
103#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */
104#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */
105#define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */
106
107#define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */
108
109/* Built-In Self Test support */
110
111#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */
112#define PI_BIST_READ_DATA 0x000208 /* BIST read data */
113#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */
114#define PI_BIST_READY 0x000218 /* BIST Ready indicator */
115#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */
116#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */
117#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */
118
119/* Graphics control registers */
120
121#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */
122#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */
123#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */
124#define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */
125#define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */
126#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */
127#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */
128#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */
129#define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */
130#define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */
131
132#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
133#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
134
135/* Error and timeout registers */
136#define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */
137#define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */
138#define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */
139#define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */
140#define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */
141#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */
142#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */
143#define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */
144#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */
145#define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */
146#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */
147#define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */
148#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */
149#define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */
150#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */
151#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */
152#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */
153#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */
154#define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */
155#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */
156#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */
157#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */
158#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */
159#define PI_NACK_CMP 0x0004b8 /* NACK count compare */
160#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
161#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
162#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
163
164/* Bits in PI_ERR_INT_PEND */
165#define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */
166#define PI_ERR_SPOOL_CMP_A 0x00000002
167#define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */
168#define PI_ERR_SPUR_MSG_A 0x00000008
169#define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */
170#define PI_ERR_WRB_TERR_A 0x00000020
171#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */
172#define PI_ERR_WRB_WERR_A 0x00000080
173#define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */
174#define PI_ERR_SYSSTATE_A 0x00000200
175#define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */
176#define PI_ERR_SYSAD_DATA_A 0x00000800
177#define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */
178#define PI_ERR_SYSAD_ADDR_A 0x00002000
179#define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */
180#define PI_ERR_SYSCMD_DATA_A 0x00008000
181#define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */
182#define PI_ERR_SYSCMD_ADDR_A 0x00020000
183#define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */
184#define PI_ERR_BAD_SPOOL_A 0x00080000
185#define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */
186#define PI_ERR_UNCAC_UNCORR_A 0x00200000
187#define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */
188#define PI_ERR_SYSSTATE_TAG_A 0x00800000
189#define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */
190
191#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa
192#define PI_ERR_CLEAR_ALL_B 0x00555555
193
194
195/*
196 * The following three macros define all possible error int pends.
197 */
198
199#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \
200 PI_ERR_BAD_SPOOL_A | \
201 PI_ERR_SYSCMD_ADDR_A | \
202 PI_ERR_SYSCMD_DATA_A | \
203 PI_ERR_SYSAD_ADDR_A | \
204 PI_ERR_SYSAD_DATA_A | \
205 PI_ERR_SYSSTATE_A)
206
207#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \
208 PI_ERR_WRB_WERR_A | \
209 PI_ERR_WRB_TERR_A | \
210 PI_ERR_SPUR_MSG_A | \
211 PI_ERR_SPOOL_CMP_A)
212
213#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \
214 PI_ERR_BAD_SPOOL_B | \
215 PI_ERR_SYSCMD_ADDR_B | \
216 PI_ERR_SYSCMD_DATA_B | \
217 PI_ERR_SYSAD_ADDR_B | \
218 PI_ERR_SYSAD_DATA_B | \
219 PI_ERR_SYSSTATE_B)
220
221#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \
222 PI_ERR_WRB_WERR_B | \
223 PI_ERR_WRB_TERR_B | \
224 PI_ERR_SPUR_MSG_B | \
225 PI_ERR_SPOOL_CMP_B)
226
227#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)
228
229/*
230 * Error types for PI_ERR_STATUS0_[AB] and error stack:
231 * Use the write types if WRBRRB is 1 else use the read types
232 */
233
234/* Fields in PI_ERR_STATUS0_[AB] */
235#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007
236#define PI_ERR_ST0_TYPE_SHFT 0
237#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038
238#define PI_ERR_ST0_REQNUM_SHFT 3
239#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0
240#define PI_ERR_ST0_SUPPL_SHFT 6
241#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000
242#define PI_ERR_ST0_CMD_SHFT 17
243#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000
244#define PI_ERR_ST0_ADDR_SHFT 25
245#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
246#define PI_ERR_ST0_OVERRUN_SHFT 62
247#define PI_ERR_ST0_VALID_MASK 0x8000000000000000
248#define PI_ERR_ST0_VALID_SHFT 63
249
250/* Fields in PI_ERR_STATUS1_[AB] */
251#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff
252#define PI_ERR_ST1_SPOOL_SHFT 0
253#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
254#define PI_ERR_ST1_TOUTCNT_SHFT 21
255#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000
256#define PI_ERR_ST1_INVCNT_SHFT 29
257#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000
258#define PI_ERR_ST1_CRBNUM_SHFT 39
259#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000
260#define PI_ERR_ST1_WRBRRB_SHFT 42
261#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
262#define PI_ERR_ST1_CRBSTAT_SHFT 43
263#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000
264#define PI_ERR_ST1_MSGSRC_SHFT 53
265
266/* Fields in the error stack */
267#define PI_ERR_STK_TYPE_MASK 0x0000000000000003
268#define PI_ERR_STK_TYPE_SHFT 0
269#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038
270#define PI_ERR_STK_SUPPL_SHFT 3
271#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0
272#define PI_ERR_STK_REQNUM_SHFT 6
273#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00
274#define PI_ERR_STK_CRBNUM_SHFT 9
275#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000
276#define PI_ERR_STK_WRBRRB_SHFT 12
277#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
278#define PI_ERR_STK_CRBSTAT_SHFT 13
279#define PI_ERR_STK_CMD_MASK 0x000000007f800000
280#define PI_ERR_STK_CMD_SHFT 23
281#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000
282#define PI_ERR_STK_ADDR_SHFT 31
283
284/* Error type in the error status or stack on Read CRBs */
285#define PI_ERR_RD_PRERR 1
286#define PI_ERR_RD_DERR 2
287#define PI_ERR_RD_TERR 3
288
289/* Error type in the error status or stack on Write CRBs */
290#define PI_ERR_WR_WERR 0
291#define PI_ERR_WR_PWERR 1
292#define PI_ERR_WR_TERR 3
293
294/* Read or Write CRB in error status or stack */
295#define PI_ERR_RRB 0
296#define PI_ERR_WRB 1
297#define PI_ERR_ANY_CRB 2
298
299/* Address masks in the error status and error stack are not the same */
300#define ERR_STK_ADDR_SHFT 7
301#define ERR_STAT0_ADDR_SHFT 3
302
303#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */
304#define PI_STACK_SIZE_SHFT 12 /* 4k */
305
306#define ERR_STACK_SIZE_BYTES(_sz) \
307 ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
308
309#ifndef __ASSEMBLY__
310/*
311 * format of error stack and error status registers.
312 */
313
314struct err_stack_format {
315 u64 sk_addr : 33, /* address */
316 sk_cmd : 8, /* message command */
317 sk_crb_sts : 10, /* status from RRB or WRB */
318 sk_rw_rb : 1, /* RRB == 0, WRB == 1 */
319 sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
320 sk_t5_req : 3, /* RRB T5 request number */
321 sk_suppl : 3, /* lowest 3 bit of supplemental */
322 sk_err_type: 3; /* error type */
323};
324
325typedef union pi_err_stack {
326 u64 pi_stk_word;
327 struct err_stack_format pi_stk_fmt;
328} pi_err_stack_t;
329
330struct err_status0_format {
331 u64 s0_valid : 1, /* Valid */
332 s0_ovr_run : 1, /* Overrun, spooled to memory */
333 s0_addr : 37, /* address */
334 s0_cmd : 8, /* message command */
335 s0_supl : 11, /* message supplemental field */
336 s0_t5_req : 3, /* RRB T5 request number */
337 s0_err_type: 3; /* error type */
338};
339
340typedef union pi_err_stat0 {
341 u64 pi_stat0_word;
342 struct err_status0_format pi_stat0_fmt;
343} pi_err_stat0_t;
344
345struct err_status1_format {
346 u64 s1_src : 11, /* message source */
347 s1_crb_sts : 10, /* status from RRB or WRB */
348 s1_rw_rb : 1, /* RRB == 0, WRB == 1 */
349 s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
350 s1_inval_cnt:10, /* signed invalidate counter RRB */
351 s1_to_cnt : 8, /* crb timeout counter */
352 s1_spl_cnt : 21; /* number spooled to memory */
353};
354
355typedef union pi_err_stat1 {
356 u64 pi_stat1_word;
357 struct err_status1_format pi_stat1_fmt;
358} pi_err_stat1_t;
359
360typedef u64 rtc_time_t;
361
362#endif /* !__ASSEMBLY__ */
363
364
365/* Bits in PI_SYSAD_ERRCHK_EN */
366#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */
367#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */
368#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */
369#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */
370#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */
371#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */
372#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */
373
374/* Interrupt pending bits on R10000 */
375
376#define HUB_IP_PEND0 0x0400
377#define HUB_IP_PEND1_CC 0x0800
378#define HUB_IP_RT 0x1000
379#define HUB_IP_PROF 0x2000
380#define HUB_IP_ERROR 0x4000
381#define HUB_IP_MASK 0x7c00
382
383/* PI_RT_LOCAL_CTRL mask and shift definitions */
384
385#define PRLC_USE_INT_SHFT 16
386#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16)
387#define PRLC_USE_INT (UINT64_CAST 1 << 16)
388#define PRLC_GCLK_SHFT 15
389#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15)
390#define PRLC_GCLK (UINT64_CAST 1 << 15)
391#define PRLC_GCLK_COUNT_SHFT 8
392#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8)
393#define PRLC_MAX_COUNT_SHFT 1
394#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1)
395#define PRLC_GCLK_EN_SHFT 0
396#define PRLC_GCLK_EN_MASK (UINT64_CAST 1)
397#define PRLC_GCLK_EN (UINT64_CAST 1)
398
399/* PI_RT_FILTER_CTRL mask and shift definitions */
400
401/*
402 * Bits for NACK_CNT_A/B and NACK_CMP
403 */
404#define PI_NACK_CNT_EN_SHFT 20
405#define PI_NACK_CNT_EN_MASK 0x100000
406#define PI_NACK_CNT_MASK 0x0fffff
407#define PI_NACK_CNT_MAX 0x0fffff
408
409#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h
deleted file mode 100644
index 3c97e0855c8d..000000000000
--- a/include/asm-mips/sn/sn0/ip27.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/IP27.h>.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999, 2006 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_IP27_H
12#define _ASM_SN_SN0_IP27_H
13
14#include <asm/mipsregs.h>
15
16/*
17 * Simple definitions for the masks which remove SW bits from pte.
18 */
19
20#define TLBLO_HWBITSHIFT 0 /* Shift value, for masking */
21
22#ifndef __ASSEMBLY__
23
24#define CAUSE_BERRINTR IE_IRQ5
25
26#define ECCF_CACHE_ERR 0
27#define ECCF_TAGLO 1
28#define ECCF_ECC 2
29#define ECCF_ERROREPC 3
30#define ECCF_PADDR 4
31#define ECCF_SIZE (5 * sizeof(long))
32
33#endif /* !__ASSEMBLY__ */
34
35#ifdef __ASSEMBLY__
36
37/*
38 * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
39 * the processor number of the calling processor. The proc parameters
40 * must be a register.
41 */
42#define KL_GET_CPUNUM(proc) \
43 dli proc, LOCAL_HUB(0); \
44 ld proc, PI_CPU_NUM(proc)
45
46#endif /* __ASSEMBLY__ */
47
48/*
49 * R10000 status register interrupt bit mask usage for IP27.
50 */
51#define SRB_SWTIMO IE_SW0 /* 0x0100 */
52#define SRB_NET IE_SW1 /* 0x0200 */
53#define SRB_DEV0 IE_IRQ0 /* 0x0400 */
54#define SRB_DEV1 IE_IRQ1 /* 0x0800 */
55#define SRB_TIMOCLK IE_IRQ2 /* 0x1000 */
56#define SRB_PROFCLK IE_IRQ3 /* 0x2000 */
57#define SRB_ERR IE_IRQ4 /* 0x4000 */
58#define SRB_SCHEDCLK IE_IRQ5 /* 0x8000 */
59
60#define SR_IBIT_HI SRB_DEV0
61#define SR_IBIT_PROF SRB_PROFCLK
62
63#define SRB_SWTIMO_IDX 0
64#define SRB_NET_IDX 1
65#define SRB_DEV0_IDX 2
66#define SRB_DEV1_IDX 3
67#define SRB_TIMOCLK_IDX 4
68#define SRB_PROFCLK_IDX 5
69#define SRB_ERR_IDX 6
70#define SRB_SCHEDCLK_IDX 7
71
72#define NUM_CAUSE_INTRS 8
73
74#define SCACHE_LINESIZE 128
75#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
76
77#include <asm/sn/addrs.h>
78
79#define LED_CYCLE_MASK 0x0f
80#define LED_CYCLE_SHFT 4
81
82#define SEND_NMI(_nasid, _slice) \
83 REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
84
85#endif /* _ASM_SN_SN0_IP27_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 17:02:27 -0500