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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_HUBMD_H
12#define _ASM_SN_SN0_HUBMD_H
13
14
15/*
16 * Hub Memory/Directory interface registers
17 */
18#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */
19
20#define MAX_REGIONS 64
21
22/* Hardware page size and shift */
23
24#define MD_PAGE_SIZE 4096 /* Page size in bytes */
25#define MD_PAGE_NUM_SHFT 12 /* Address to page number shift */
26
27/* Register offsets from LOCAL_HUB or REMOTE_HUB */
28
29#define MD_BASE 0x200000
30#define MD_BASE_PERF 0x210000
31#define MD_BASE_JUNK 0x220000
32
33#define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34#define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35#define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36#define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
40#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */
41#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */
42#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */
43#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */
44#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */
45#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */
46#define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */
47#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */
48#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */
49#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */
50#define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */
51#define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */
52#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */
53#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */
54#define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */
55
56#define MD_PERF_SEL 0x210000 /* Select perf monitor events */
57#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */
58#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */
59#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */
60#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */
61#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */
62#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */
63
64#define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65#define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66#define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67#define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68#define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69#define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70#define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71#define MD_UREG0_7 0x220038 /* uController/UART 0 register */
72
73#define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
74#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
75#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
76
77#define MD_UREG1_0 0x220080 /* uController/UART 1 register */
78#define MD_UREG1_1 0x220088 /* uController/UART 1 register */
79#define MD_UREG1_2 0x220090 /* uController/UART 1 register */
80#define MD_UREG1_3 0x220098 /* uController/UART 1 register */
81#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
82#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
83#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
84#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
85#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
86#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
87#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
88#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
89#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
90#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
91#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
93
94#ifdef CONFIG_SGI_SN_N_MODE
95#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
96#else
97#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
98#endif
99
100/*
101 * MD_MEMORY_CONFIG fields
102 *
103 * MD_SIZE_xxx are useful for representing the size of a SIMM or bank
104 * (SIMM pair). They correspond to the values needed for the bit
105 * triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
106 * Bits not used by the MD are used by software.
107 */
108
109#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */
110#define MD_SIZE_8MB 1
111#define MD_SIZE_16MB 2
112#define MD_SIZE_32MB 3 /* Broken in Hub 1 */
113#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */
114#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */
115#define MD_SIZE_256MB 6
116#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */
117#define MD_SIZE_1GB 8
118#define MD_SIZE_2GB 9
119#define MD_SIZE_4GB 10
120
121#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
122#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
123
124#define MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */
125#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
126#define MMC_FPROM_WR_SHFT 44 /* for assembler */
127#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
128#define MMC_UCTLR_CYC_SHFT 39
129#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
130#define MMC_UCTLR_WR_SHFT 34
131#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
132#define MMC_DIMM0_SEL_SHFT 32
133#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
134#define MMC_IO_PROT_EN_SHFT 31
135#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
136#define MMC_IO_PROT (UINT64_CAST 1 << 31)
137#define MMC_ARB_MLSS_SHFT 30
138#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
139#define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
140#define MMC_IGNORE_ECC_SHFT 29
141#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
142#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
143#define MMC_DIR_PREMIUM_SHFT 28
144#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
145#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
146#define MMC_REPLY_GUAR_SHFT 24
147#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
148#define MMC_BANK_SHFT(_b) ((_b) * 3)
149#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
150#define MMC_BANK_ALL_MASK 0xffffff
151#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
152 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
153 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
154 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
155 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
156 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
157 MMC_BANK_ALL_MASK)
158
159/* MD_REFRESH_CONTROL fields */
160
161#define MRC_ENABLE_SHFT 63
162#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
163#define MRC_ENABLE (UINT64_CAST 1 << 63)
164#define MRC_COUNTER_SHFT 12
165#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
166#define MRC_CNT_THRESH_MASK 0xfff
167#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
168
169/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
170
171#define MDI_SELECT_SHFT 32
172#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
173#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
174
175/* MD_MOQ_SIZE fields */
176
177#define MMS_RP_SIZE_SHFT 8
178#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
179#define MMS_RQ_SIZE_SHFT 0
180#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
181#define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12)
182
183/* MD_FANDOP_CAC_STAT fields */
184
185#define MFC_VALID_SHFT 63
186#define MFC_VALID_MASK (UINT64_CAST 1 << 63)
187#define MFC_VALID (UINT64_CAST 1 << 63)
188#define MFC_ADDR_SHFT 6
189#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
190
191/* MD_MLAN_CTL fields */
192
193#define MLAN_PHI1_SHFT 27
194#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
195#define MLAN_PHI0_SHFT 20
196#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
197#define MLAN_PULSE_SHFT 10
198#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
199#define MLAN_SAMPLE_SHFT 2
200#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
201#define MLAN_DONE_SHFT 1
202#define MLAN_DONE_MASK 2
203#define MLAN_DONE (UINT64_CAST 0x02)
204#define MLAN_RD_DATA (UINT64_CAST 0x01)
205#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
206 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
207
208/* MD_SLOTID_USTAT bit definitions */
209
210#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */
211#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
212#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
213#define MSU_CORECLK_SHFT 6 /* You don't wanna know */
214#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
215#define MSU_CORECLK (UINT64_CAST 1 << 6)
216#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */
217#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
218#define MSU_NETSYNC (UINT64_CAST 1 << 5)
219#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */
220#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
221#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
222#define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */
223#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
224#define MSU_I2CINTR (UINT64_CAST 1 << 3)
225#define MSU_SLOTID_MASK 0xff
226#define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */
227#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
228#define MSU_SN00_SLOTID_SHFT 7
229#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
230
231#define MSU_PIMM_PSC_SHFT 4
232#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT)
233
234/* MD_MIG_DIFF_THRESH bit definitions */
235
236#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
237#define MD_MIG_DIFF_THRES_VALID_SHFT 63
238#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
239
240/* MD_MIG_VALUE_THRESH bit definitions */
241
242#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
243#define MD_MIG_VALUE_THRES_VALID_SHFT 63
244#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
245
246/* MD_MIG_CANDIDATE bit definitions */
247
248#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
249#define MD_MIG_CANDIDATE_VALID_SHFT 63
250#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
251#define MD_MIG_CANDIDATE_TYPE_SHFT 30
252#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
253#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
254#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
255#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
256#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
257#define MD_MIG_CANDIDATE_NODEID_SHFT 20
258#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
259#define MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */
260
261/* Other MD definitions */
262
263#define MD_BANK_SHFT 29 /* log2(512 MB) */
264#define MD_BANK_MASK (UINT64_CAST 7 << 29)
265#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
266#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
267
268/*
269 * The following definitions cover the bit field definitions for the
270 * various MD registers. For multi-bit registers, we define both
271 * a shift amount and a mask value. By convention, if you want to
272 * isolate a field, you should mask the field and then shift it down,
273 * since this makes the masks useful without a shift.
274 */
275
276/* Directory entry states for both premium and standard SIMMs. */
277
278#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
279#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
280#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
281#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
282#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
283#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
284#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
285
286/*
287 * The MD_DIR_FORCE_ECC bit can be added directory entry write data
288 * to forcing the ECC to be written as-is instead of recalculated.
289 */
290
291#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
292
293/*
294 * Premium SIMM directory entry shifts and masks. Each is valid only in the
295 * context(s) indicated, where A, B, and C indicate the directory entry format
296 * as shown, and low and/or high indicates which double-word of the entry.
297 *
298 * Format A: STATE = shared, FINE = 1
299 * Format B: STATE = shared, FINE = 0
300 * Format C: STATE != shared (FINE must be 0)
301 */
302
303#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */
304#define MD_PDIR_ECC_SHFT 0 /* ABC low or high */
305#define MD_PDIR_ECC_MASK 0x7f
306#define MD_PDIR_PRIO_SHFT 8 /* ABC low */
307#define MD_PDIR_PRIO_MASK (0xf << 8)
308#define MD_PDIR_AX_SHFT 7 /* ABC low */
309#define MD_PDIR_AX_MASK (1 << 7)
310#define MD_PDIR_AX (1 << 7)
311#define MD_PDIR_FINE_SHFT 12 /* ABC low */
312#define MD_PDIR_FINE_MASK (1 << 12)
313#define MD_PDIR_FINE (1 << 12)
314#define MD_PDIR_OCT_SHFT 13 /* A low */
315#define MD_PDIR_OCT_MASK (7 << 13)
316#define MD_PDIR_STATE_SHFT 13 /* BC low */
317#define MD_PDIR_STATE_MASK (7 << 13)
318#define MD_PDIR_ONECNT_SHFT 16 /* BC low */
319#define MD_PDIR_ONECNT_MASK (0x3f << 16)
320#define MD_PDIR_PTR_SHFT 22 /* C low */
321#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
322#define MD_PDIR_VECMSB_SHFT 22 /* AB low */
323#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
324#define MD_PDIR_VECMSB_BITSHFT 27
325#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
326#define MD_PDIR_CWOFF_SHFT 7 /* C high */
327#define MD_PDIR_CWOFF_MASK (7 << 7)
328#define MD_PDIR_VECLSB_SHFT 10 /* AB high */
329#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
330#define MD_PDIR_VECLSB_BITSHFT 0
331#define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10)
332
333/*
334 * Directory initialization values
335 */
336
337#define MD_PDIR_INIT_LO (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
338 MD_PDIR_AX)
339#define MD_PDIR_INIT_HI 0
340#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | \
341 MD_PROT_RW << MD_PPROT_SHFT)
342
343/*
344 * Standard SIMM directory entry shifts and masks. Each is valid only in the
345 * context(s) indicated, where A and C indicate the directory entry format
346 * as shown, and low and/or high indicates which double-word of the entry.
347 *
348 * Format A: STATE == shared
349 * Format C: STATE != shared
350 */
351
352#define MD_SDIR_MASK 0xffff /* Whole entry */
353#define MD_SDIR_ECC_SHFT 0 /* AC low or high */
354#define MD_SDIR_ECC_MASK 0x1f
355#define MD_SDIR_PRIO_SHFT 6 /* AC low */
356#define MD_SDIR_PRIO_MASK (1 << 6)
357#define MD_SDIR_AX_SHFT 5 /* AC low */
358#define MD_SDIR_AX_MASK (1 << 5)
359#define MD_SDIR_AX (1 << 5)
360#define MD_SDIR_STATE_SHFT 7 /* AC low */
361#define MD_SDIR_STATE_MASK (7 << 7)
362#define MD_SDIR_PTR_SHFT 10 /* C low */
363#define MD_SDIR_PTR_MASK (0x3f << 10)
364#define MD_SDIR_CWOFF_SHFT 5 /* C high */
365#define MD_SDIR_CWOFF_MASK (7 << 5)
366#define MD_SDIR_VECMSB_SHFT 11 /* A low */
367#define MD_SDIR_VECMSB_BITMASK 0x1f
368#define MD_SDIR_VECMSB_BITSHFT 7
369#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
370#define MD_SDIR_VECLSB_SHFT 5 /* A high */
371#define MD_SDIR_VECLSB_BITMASK 0x7ff
372#define MD_SDIR_VECLSB_BITSHFT 0
373#define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5)
374
375/*
376 * Directory initialization values
377 */
378
379#define MD_SDIR_INIT_LO (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
380 MD_SDIR_AX)
381#define MD_SDIR_INIT_HI 0
382#define MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT)
383
384/* Protection and migration field values */
385
386#define MD_PROT_RW (UINT64_CAST 0x6)
387#define MD_PROT_RO (UINT64_CAST 0x3)
388#define MD_PROT_NO (UINT64_CAST 0x0)
389#define MD_PROT_BAD (UINT64_CAST 0x5)
390
391/* Premium SIMM protection entry shifts and masks. */
392
393#define MD_PPROT_SHFT 0 /* Prot. field */
394#define MD_PPROT_MASK 7
395#define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */
396#define MD_PPROT_MIGMD_MASK (3 << 3)
397#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */
398#define MD_PPROT_REFCNT_WIDTH 0x7ffff
399#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
400
401#define MD_PPROT_IO_SHFT 45 /* I/O Prot field */
402#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
403
404/* Standard SIMM protection entry shifts and masks. */
405
406#define MD_SPROT_SHFT 0 /* Prot. field */
407#define MD_SPROT_MASK 7
408#define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */
409#define MD_SPROT_MIGMD_MASK (3 << 3)
410#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */
411#define MD_SPROT_REFCNT_WIDTH 0x7ff
412#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)
413
414/* Migration modes used in protection entries */
415
416#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
417#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
418#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
419#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
420
421
422/*
423 * Operations on page migration threshold register
424 */
425
426#ifndef __ASSEMBLY__
427
428/*
429 * LED register macros
430 */
431
432#define CPU_LED_ADDR(_nasid, _slice) \
433 (private.p_sn00 ? \
434 REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \
435 REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3)))
436
437#define SET_CPU_LEDS(_nasid, _slice, _val) \
438 (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
439
440#define SET_MY_LEDS(_v) \
441 SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
442
443/*
444 * Operations on Memory/Directory DIMM control register
445 */
446
447#define DIRTYPE_PREMIUM 1
448#define DIRTYPE_STANDARD 0
449#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
450 (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
451 MMC_DIR_PREMIUM_SHFT)
452
453
454/*
455 * Operations on page migration count difference and absolute threshold
456 * registers
457 */
458
459#define MD_MIG_DIFF_THRESH_GET(region) ( \
460 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
461 MD_MIG_DIFF_THRES_VALUE_MASK)
462
463#define MD_MIG_DIFF_THRESH_SET(region, value) ( \
464 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
465 MD_MIG_DIFF_THRES_VALID_MASK | (value)))
466
467#define MD_MIG_DIFF_THRESH_DISABLE(region) ( \
468 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
469 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
470 & ~MD_MIG_DIFF_THRES_VALID_MASK))
471
472#define MD_MIG_DIFF_THRESH_ENABLE(region) ( \
473 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
474 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
475 | MD_MIG_DIFF_THRES_VALID_MASK))
476
477#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) ( \
478 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
479 MD_MIG_DIFF_THRES_VALID_MASK)
480
481#define MD_MIG_VALUE_THRESH_GET(region) ( \
482 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
483 MD_MIG_VALUE_THRES_VALUE_MASK)
484
485#define MD_MIG_VALUE_THRESH_SET(region, value) ( \
486 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
487 MD_MIG_VALUE_THRES_VALID_MASK | (value)))
488
489#define MD_MIG_VALUE_THRESH_DISABLE(region) ( \
490 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
491 REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH) \
492 & ~MD_MIG_VALUE_THRES_VALID_MASK))
493
494#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \
495 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
496 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \
497 | MD_MIG_VALUE_THRES_VALID_MASK))
498
499#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) ( \
500 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
501 MD_MIG_VALUE_THRES_VALID_MASK)
502
503/*
504 * Operations on page migration candidate register
505 */
506
507#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
508 REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
509
510#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
511
512#define MD_MIG_CANDIDATE_NODEID(value) ( \
513 ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
514
515#define MD_MIG_CANDIDATE_TYPE(value) ( \
516 ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
517
518#define MD_MIG_CANDIDATE_VALID(value) ( \
519 ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
520
521/*
522 * Macros to retrieve fields in the protection entry
523 */
524
525/* for Premium SIMM */
526#define MD_PPROT_REFCNT_GET(value) ( \
527 ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
528
529#define MD_PPROT_MIGMD_GET(value) ( \
530 ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
531
532/* for Standard SIMM */
533#define MD_SPROT_REFCNT_GET(value) ( \
534 ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
535
536#define MD_SPROT_MIGMD_GET(value) ( \
537 ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
538
539/*
540 * Format of dir_error, mem_error, protocol_error and misc_error registers
541 */
542
543struct dir_error_reg {
544 u64 uce_vld: 1, /* 63: valid directory uce */
545 ae_vld: 1, /* 62: valid dir prot ecc error */
546 ce_vld: 1, /* 61: valid correctable ECC err*/
547 rsvd1: 19, /* 60-42: reserved */
548 bad_prot: 3, /* 41-39: encoding, bad access rights*/
549 bad_syn: 7, /* 38-32: bad dir syndrome */
550 rsvd2: 2, /* 31-30: reserved */
551 hspec_addr:27, /* 29-03: bddir space bad entry */
552 uce_ovr: 1, /* 2: multiple dir uce's */
553 ae_ovr: 1, /* 1: multiple prot ecc errs*/
554 ce_ovr: 1; /* 0: multiple correctable errs */
555};
556
557typedef union md_dir_error {
558 u64 derr_reg; /* the entire register */
559 struct dir_error_reg derr_fmt; /* the register format */
560} md_dir_error_t;
561
562
563struct mem_error_reg {
564 u64 uce_vld: 1, /* 63: valid memory uce */
565 ce_vld: 1, /* 62: valid correctable ECC err*/
566 rsvd1: 22, /* 61-40: reserved */
567 bad_syn: 8, /* 39-32: bad mem ecc syndrome */
568 address: 29, /* 31-03: bad entry pointer */
569 rsvd2: 1, /* 2: reserved */
570 uce_ovr: 1, /* 1: multiple mem uce's */
571 ce_ovr: 1; /* 0: multiple correctable errs */
572};
573
574
575typedef union md_mem_error {
576 u64 merr_reg; /* the entire register */
577 struct mem_error_reg merr_fmt; /* format of the mem_error reg */
578} md_mem_error_t;
579
580
581struct proto_error_reg {
582 u64 valid: 1, /* 63: valid protocol error */
583 rsvd1: 2, /* 62-61: reserved */
584 initiator:11, /* 60-50: id of request initiator*/
585 backoff: 2, /* 49-48: backoff control */
586 msg_type: 8, /* 47-40: type of request */
587 access: 2, /* 39-38: access rights of initiator*/
588 priority: 1, /* 37: priority level of requestor*/
589 dir_state: 4, /* 36-33: state of directory */
590 pointer_me:1, /* 32: initiator same as dir ptr */
591 address: 29, /* 31-03: request address */
592 rsvd2: 2, /* 02-01: reserved */
593 overrun: 1; /* 0: multiple protocol errs */
594};
595
596typedef union md_proto_error {
597 u64 perr_reg; /* the entire register */
598 struct proto_error_reg perr_fmt; /* format of the register */
599} md_proto_error_t;
600
601
602struct md_sdir_high_fmt {
603 unsigned short sd_hi_bvec : 11,
604 sd_hi_ecc : 5;
605};
606
607
608typedef union md_sdir_high {
609 /* The 16 bits of standard directory, upper word */
610 unsigned short sd_hi_val;
611 struct md_sdir_high_fmt sd_hi_fmt;
612}md_sdir_high_t;
613
614
615struct md_sdir_low_shared_fmt {
616 /* The meaning of lower directory, shared */
617 unsigned short sds_lo_bvec : 5,
618 sds_lo_unused: 1,
619 sds_lo_state : 3,
620 sds_lo_prio : 1,
621 sds_lo_ax : 1,
622 sds_lo_ecc : 5;
623};
624
625struct md_sdir_low_exclusive_fmt {
626 /* The meaning of lower directory, exclusive */
627 unsigned short sde_lo_ptr : 6,
628 sde_lo_state : 3,
629 sde_lo_prio : 1,
630 sde_lo_ax : 1,
631 sde_lo_ecc : 5;
632};
633
634
635typedef union md_sdir_low {
636 /* The 16 bits of standard directory, lower word */
637 unsigned short sd_lo_val;
638 struct md_sdir_low_exclusive_fmt sde_lo_fmt;
639 struct md_sdir_low_shared_fmt sds_lo_fmt;
640}md_sdir_low_t;
641
642
643
644struct md_pdir_high_fmt {
645 u64 pd_hi_unused : 16,
646 pd_hi_bvec : 38,
647 pd_hi_unused1 : 3,
648 pd_hi_ecc : 7;
649};
650
651
652typedef union md_pdir_high {
653 /* The 48 bits of standard directory, upper word */
654 u64 pd_hi_val;
655 struct md_pdir_high_fmt pd_hi_fmt;
656}md_pdir_high_t;
657
658
659struct md_pdir_low_shared_fmt {
660 /* The meaning of lower directory, shared */
661 u64 pds_lo_unused : 16,
662 pds_lo_bvec : 26,
663 pds_lo_cnt : 6,
664 pds_lo_state : 3,
665 pds_lo_ste : 1,
666 pds_lo_prio : 4,
667 pds_lo_ax : 1,
668 pds_lo_ecc : 7;
669};
670
671struct md_pdir_low_exclusive_fmt {
672 /* The meaning of lower directory, exclusive */
673 u64 pde_lo_unused : 31,
674 pde_lo_ptr : 11,
675 pde_lo_unused1 : 6,
676 pde_lo_state : 3,
677 pde_lo_ste : 1,
678 pde_lo_prio : 4,
679 pde_lo_ax : 1,
680 pde_lo_ecc : 7;
681};
682
683
684typedef union md_pdir_loent {
685 /* The 48 bits of premium directory, lower word */
686 u64 pd_lo_val;
687 struct md_pdir_low_exclusive_fmt pde_lo_fmt;
688 struct md_pdir_low_shared_fmt pds_lo_fmt;
689}md_pdir_low_t;
690
691
692/*
693 * the following two "union" definitions and two
694 * "struct" definitions are used in vmdump.c to
695 * represent directory memory information.
696 */
697
698typedef union md_dir_high {
699 md_sdir_high_t md_sdir_high;
700 md_pdir_high_t md_pdir_high;
701} md_dir_high_t;
702
703typedef union md_dir_low {
704 md_sdir_low_t md_sdir_low;
705 md_pdir_low_t md_pdir_low;
706} md_dir_low_t;
707
708typedef struct bddir_entry {
709 md_dir_low_t md_dir_low;
710 md_dir_high_t md_dir_high;
711} bddir_entry_t;
712
713typedef struct dir_mem_entry {
714 u64 prcpf[MAX_REGIONS];
715 bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
716} dir_mem_entry_t;
717
718
719
720typedef union md_perf_sel {
721 u64 perf_sel_reg;
722 struct {
723 u64 perf_rsvd : 60,
724 perf_en : 1,
725 perf_sel : 3;
726 } perf_sel_bits;
727} md_perf_sel_t;
728
729typedef union md_perf_cnt {
730 u64 perf_cnt;
731 struct {
732 u64 perf_rsvd : 44,
733 perf_cnt : 20;
734 } perf_cnt_bits;
735} md_perf_cnt_t;
736
737
738#endif /* !__ASSEMBLY__ */
739
740
741#define DIR_ERROR_VALID_MASK 0xe000000000000000
742#define DIR_ERROR_VALID_SHFT 61
743#define DIR_ERROR_VALID_UCE 0x8000000000000000
744#define DIR_ERROR_VALID_AE 0x4000000000000000
745#define DIR_ERROR_VALID_CE 0x2000000000000000
746
747#define MEM_ERROR_VALID_MASK 0xc000000000000000
748#define MEM_ERROR_VALID_SHFT 62
749#define MEM_ERROR_VALID_UCE 0x8000000000000000
750#define MEM_ERROR_VALID_CE 0x4000000000000000
751
752#define PROTO_ERROR_VALID_MASK 0x8000000000000000
753
754#define MISC_ERROR_VALID_MASK 0x3ff
755
756/*
757 * Mask for hspec address that is stored in the dir error register.
758 * This represents bits 29 through 3.
759 */
760#define DIR_ERR_HSPEC_MASK 0x3ffffff8
761#define ERROR_HSPEC_MASK 0x3ffffff8
762#define ERROR_HSPEC_SHFT 3
763#define ERROR_ADDR_MASK 0xfffffff8
764#define ERROR_ADDR_SHFT 3
765
766/*
767 * MD_MISC_ERROR register defines.
768 */
769
770#define MMCE_VALID_MASK 0x3ff
771#define MMCE_ILL_MSG_SHFT 8
772#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
773#define MMCE_ILL_REV_SHFT 6
774#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
775#define MMCE_LONG_PACK_SHFT 4
776#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
777#define MMCE_SHORT_PACK_SHFT 2
778#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
779#define MMCE_BAD_DATA_SHFT 0
780#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
781
782
783#define MD_PERF_COUNTERS 6
784#define MD_PERF_SETS 6
785
786#define MEM_DIMM_MASK 0xe0000000
787#define MEM_DIMM_SHFT 29
788
789#endif /* _ASM_SN_SN0_HUBMD_H */
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