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diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SGI_SN_SN0_HUBIO_H
12#define _ASM_SGI_SN_SN0_HUBIO_H
13
14/*
15 * Hub I/O interface registers
16 *
17 * All registers in this file are subject to change until Hub chip tapeout.
18 * In general, the longer software name should be used when available.
19 */
20
21/*
22 * Slightly friendlier names for some common registers.
23 * The hardware definitions follow.
24 */
25#define IIO_WIDGET IIO_WID /* Widget identification */
26#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
27#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
28#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
29#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
30#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
31#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
32#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
33#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
34#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
35#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
36#define IIO_LLP_LOG IIO_ILLR /* LLP log */
37#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
38#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
39#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
40#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
41
42#define IIO_LLP_CSR_IS_UP 0x00002000
43#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
44#define IIO_LLP_CSR_LLP_STAT_SHFT 12
45
46/* key to IIO_PROTECT_OVRRD */
47#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
48
49/* BTE register names */
50#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
51#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
52#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
53#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
54#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
55#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
56#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
57#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
58
59/* BTE register offsets from base */
60#define BTEOFF_STAT 0
61#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
62#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
63#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
64#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
65#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
66
67
68/*
69 * The following definitions use the names defined in the IO interface
70 * document for ease of reference. When possible, software should
71 * generally use the longer but clearer names defined above.
72 */
73
74#define IIO_BASE 0x400000
75#define IIO_BASE_BTE0 0x410000
76#define IIO_BASE_BTE1 0x420000
77#define IIO_BASE_PERF 0x430000
78#define IIO_PERF_CNT 0x430008
79
80#define IO_PERF_SETS 32
81
82#define IIO_WID 0x400000 /* Widget identification */
83#define IIO_WSTAT 0x400008 /* Widget status */
84#define IIO_WCR 0x400020 /* Widget control */
85
86#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
87#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
88#define IIO_WSTAT_TXRETRY_MASK (0x7F)
89#define IIO_WSTAT_TXRETRY_SHFT (16)
90#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
91 IIO_WSTAT_TXRETRY_MASK)
92
93#define IIO_ILAPR 0x400100 /* Local Access Protection */
94#define IIO_ILAPO 0x400108 /* Protection override */
95#define IIO_IOWA 0x400110 /* outbound widget access */
96#define IIO_IIWA 0x400118 /* inbound widget access */
97#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
98#define IIO_ILCSR 0x400128 /* LLP control and status */
99#define IIO_ILLR 0x400130 /* LLP Log */
100#define IIO_IIDSR 0x400138 /* Interrupt destination */
101
102#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
103
104/* IO Interrupt Destination Register */
105#define IIO_IIDSR_SENT_SHIFT 28
106#define IIO_IIDSR_SENT_MASK 0x10000000
107#define IIO_IIDSR_ENB_SHIFT 24
108#define IIO_IIDSR_ENB_MASK 0x01000000
109#define IIO_IIDSR_NODE_SHIFT 8
110#define IIO_IIDSR_NODE_MASK 0x0000ff00
111#define IIO_IIDSR_LVL_SHIFT 0
112#define IIO_IIDSR_LVL_MASK 0x0000003f
113
114
115/* GFX Flow Control Node/Widget Register */
116#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
117#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
118#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
119#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
120#define IIO_IGFX_W_NUM_SHIFT 0
121#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
122#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
123#define IIO_IGFX_N_NUM_SHIFT 4
124#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
125#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
126#define IIO_IGFX_P_NUM_SHIFT 16
127#define IIO_IGFX_VLD_BITS 1 /* size of valid field */
128#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
129#define IIO_IGFX_VLD_SHIFT 20
130#define IIO_IGFX_INIT(widget, node, cpu, valid) (\
131 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
132 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
133 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
134 (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
135
136/* Scratch registers (not all bits available) */
137#define IIO_SCRATCH_REG0 0x400150
138#define IIO_SCRATCH_REG1 0x400158
139#define IIO_SCRATCH_MASK 0x0000000f00f11fff
140
141#define IIO_SCRATCH_BIT0_0 0x0000000800000000
142#define IIO_SCRATCH_BIT0_1 0x0000000400000000
143#define IIO_SCRATCH_BIT0_2 0x0000000200000000
144#define IIO_SCRATCH_BIT0_3 0x0000000100000000
145#define IIO_SCRATCH_BIT0_4 0x0000000000800000
146#define IIO_SCRATCH_BIT0_5 0x0000000000400000
147#define IIO_SCRATCH_BIT0_6 0x0000000000200000
148#define IIO_SCRATCH_BIT0_7 0x0000000000100000
149#define IIO_SCRATCH_BIT0_8 0x0000000000010000
150#define IIO_SCRATCH_BIT0_9 0x0000000000001000
151#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
152
153/* IO Translation Table Entries */
154#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
155 /* Hw manuals number them 1..7! */
156
157/*
158 * As a permanent workaround for a bug in the PI side of the hub, we've
159 * redefined big window 7 as small window 0.
160 */
161#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
162
163/*
164 * Use the top big window as a surrogate for the first small window
165 */
166#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
167
168#define ILCSR_WARM_RESET 0x100
169/*
170 * The IO LLP control status register and widget control register
171 */
172#ifndef __ASSEMBLY__
173
174typedef union hubii_wid_u {
175 u64 wid_reg_value;
176 struct {
177 u64 wid_rsvd: 32, /* unused */
178 wid_rev_num: 4, /* revision number */
179 wid_part_num: 16, /* the widget type: hub=c101 */
180 wid_mfg_num: 11, /* Manufacturer id (IBM) */
181 wid_rsvd1: 1; /* Reserved */
182 } wid_fields_s;
183} hubii_wid_t;
184
185
186typedef union hubii_wcr_u {
187 u64 wcr_reg_value;
188 struct {
189 u64 wcr_rsvd: 41, /* unused */
190 wcr_e_thresh: 5, /* elasticity threshold */
191 wcr_dir_con: 1, /* widget direct connect */
192 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
193 wcr_xbar_crd: 3, /* LLP crossbar credit */
194 wcr_rsvd1: 8, /* Reserved */
195 wcr_tag_mode: 1, /* Tag mode */
196 wcr_widget_id: 4; /* LLP crossbar credit */
197 } wcr_fields_s;
198} hubii_wcr_t;
199
200#define iwcr_dir_con wcr_fields_s.wcr_dir_con
201
202typedef union hubii_wstat_u {
203 u64 reg_value;
204 struct {
205 u64 rsvd1: 31,
206 crazy: 1, /* Crazy bit */
207 rsvd2: 8,
208 llp_tx_cnt: 8, /* LLP Xmit retry counter */
209 rsvd3: 6,
210 tx_max_rtry: 1, /* LLP Retry Timeout Signal */
211 rsvd4: 2,
212 xt_tail_to: 1, /* Xtalk Tail Timeout */
213 xt_crd_to: 1, /* Xtalk Credit Timeout */
214 pending: 4; /* Pending Requests */
215 } wstat_fields_s;
216} hubii_wstat_t;
217
218
219typedef union hubii_ilcsr_u {
220 u64 icsr_reg_value;
221 struct {
222 u64 icsr_rsvd: 22, /* unused */
223 icsr_max_burst: 10, /* max burst */
224 icsr_rsvd4: 6, /* reserved */
225 icsr_max_retry: 10, /* max retry */
226 icsr_rsvd3: 2, /* reserved */
227 icsr_lnk_stat: 2, /* link status */
228 icsr_bm8: 1, /* Bit mode 8 */
229 icsr_llp_en: 1, /* LLP enable bit */
230 icsr_rsvd2: 1, /* reserver */
231 icsr_wrm_reset: 1, /* Warm reset bit */
232 icsr_rsvd1: 2, /* Data ready offset */
233 icsr_null_to: 6; /* Null timeout */
234
235 } icsr_fields_s;
236} hubii_ilcsr_t;
237
238
239typedef union hubii_iowa_u {
240 u64 iowa_reg_value;
241 struct {
242 u64 iowa_rsvd: 48, /* unused */
243 iowa_wxoac: 8, /* xtalk widget access bits */
244 iowa_rsvd1: 7, /* xtalk widget access bits */
245 iowa_w0oac: 1; /* xtalk widget access bits */
246 } iowa_fields_s;
247} hubii_iowa_t;
248
249typedef union hubii_iiwa_u {
250 u64 iiwa_reg_value;
251 struct {
252 u64 iiwa_rsvd: 48, /* unused */
253 iiwa_wxiac: 8, /* hub wid access bits */
254 iiwa_rsvd1: 7, /* reserved */
255 iiwa_w0iac: 1; /* hub wid0 access */
256 } iiwa_fields_s;
257} hubii_iiwa_t;
258
259typedef union hubii_illr_u {
260 u64 illr_reg_value;
261 struct {
262 u64 illr_rsvd: 32, /* unused */
263 illr_cb_cnt: 16, /* checkbit error count */
264 illr_sn_cnt: 16; /* sequence number count */
265 } illr_fields_s;
266} hubii_illr_t;
267
268/* The structures below are defined to extract and modify the ii
269performance registers */
270
271/* io_perf_sel allows the caller to specify what tests will be
272 performed */
273typedef union io_perf_sel {
274 u64 perf_sel_reg;
275 struct {
276 u64 perf_rsvd : 48,
277 perf_icct : 8,
278 perf_ippr1 : 4,
279 perf_ippr0 : 4;
280 } perf_sel_bits;
281} io_perf_sel_t;
282
283/* io_perf_cnt is to extract the count from the hub registers. Due to
284 hardware problems there is only one counter, not two. */
285
286typedef union io_perf_cnt {
287 u64 perf_cnt;
288 struct {
289 u64 perf_rsvd1 : 32,
290 perf_rsvd2 : 12,
291 perf_cnt : 20;
292 } perf_cnt_bits;
293} io_perf_cnt_t;
294
295#endif /* !__ASSEMBLY__ */
296
297
298#define LNK_STAT_WORKING 0x2
299
300#define IIO_LLP_CB_MAX 0xffff
301#define IIO_LLP_SN_MAX 0xffff
302
303/* IO PRB Entries */
304#define IIO_NUM_IPRBS (9)
305#define IIO_IOPRB_0 0x400198 /* PRB entry 0 */
306#define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */
307#define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */
308#define IIO_IOPRB_A 0x4001b0 /* PRB entry a */
309#define IIO_IOPRB_B 0x4001b8 /* PRB entry b */
310#define IIO_IOPRB_C 0x4001c0 /* PRB entry c */
311#define IIO_IOPRB_D 0x4001c8 /* PRB entry d */
312#define IIO_IOPRB_E 0x4001d0 /* PRB entry e */
313#define IIO_IOPRB_F 0x4001d8 /* PRB entry f */
314
315
316#define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */
317#define IIO_IXTCC IIO_IXCC
318#define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */
319#define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */
320#define IIO_IECLR 0x4001f8 /* IO error clear */
321#define IIO_IBCN 0x400200 /* IO BTE CRB count */
322
323/*
324 * IIO_IMEM Register fields.
325 */
326#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
327#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
328#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
329
330/* PIO Read address Table Entries */
331#define IIO_IPCA 0x400300 /* PRB Counter adjust */
332#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
333#define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */
334#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
335#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
336#define IIO_IPDR 0x400388 /* PIO table entry deallocation */
337#define IIO_ICDR 0x400390 /* CRB Entry Deallocation */
338#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
339#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
340#define IIO_IMMR IIO_IIAP
341#define IIO_ICMR 0x4003a8 /* CRB Management Register */
342#define IIO_ICCR 0x4003b0 /* CRB Control Register */
343#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
344#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
345
346
347/*
348 * ICMR register fields
349 */
350#define IIO_ICMR_PC_VLD_SHFT 36
351#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
352
353#define IIO_ICMR_CRB_VLD_SHFT 20
354#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
355
356#define IIO_ICMR_FC_CNT_SHFT 16
357#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
358
359#define IIO_ICMR_C_CNT_SHFT 4
360#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
361
362#define IIO_ICMR_P_CNT_SHFT 0
363#define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
364
365#define IIO_ICMR_PRECISE (1UL << 52)
366#define IIO_ICMR_CLR_RPPD (1UL << 13)
367#define IIO_ICMR_CLR_RQPD (1UL << 12)
368
369/*
370 * IIO PIO Deallocation register field masks : (IIO_IPDR)
371 */
372#define IIO_IPDR_PND (1 << 4)
373
374/*
375 * IIO CRB deallocation register field masks: (IIO_ICDR)
376 */
377#define IIO_ICDR_PND (1 << 4)
378
379/*
380 * IIO CRB control register Fields: IIO_ICCR
381 */
382#define IIO_ICCR_PENDING (0x10000)
383#define IIO_ICCR_CMD_MASK (0xFF)
384#define IIO_ICCR_CMD_SHFT (7)
385#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
386#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
387#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
388#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
389 * via a WB
390 */
391#define IIO_ICCR_CMD_FLUSH (0x800)
392
393/*
394 * CRB manipulation macros
395 * The CRB macros are slightly complicated, since there are up to
396 * four registers associated with each CRB entry.
397 */
398#define IIO_NUM_CRBS 15 /* Number of CRBs */
399#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */
400#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
401#define IIO_ICRB_OFFSET 8
402#define IIO_ICRB_0 0x400400
403/* XXX - This is now tuneable:
404 #define IIO_FIRST_PC_ENTRY 12
405 */
406
407#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
408#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
409#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
410#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
411
412/* XXX - IBUE register coming for Hub 2 */
413
414/*
415 *
416 * CRB Register description.
417 *
418 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
419 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
420 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
421 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
422 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
423 *
424 * Many of the fields in CRB are status bits used by hardware
425 * for implementation of the protocol. It's very dangerous to
426 * mess around with the CRB registers.
427 *
428 * It's OK to read the CRB registers and try to make sense out of the
429 * fields in CRB.
430 *
431 * Updating CRB requires all activities in Hub IIO to be quiesced.
432 * otherwise, a write to CRB could corrupt other CRB entries.
433 * CRBs are here only as a back door peek to hub IIO's status.
434 * Quiescing implies no dmas no PIOs
435 * either directly from the cpu or from sn0net.
436 * this is not something that can be done easily. So, AVOID updating
437 * CRBs.
438 */
439
440/*
441 * Fields in CRB Register A
442 */
443#ifndef __ASSEMBLY__
444typedef union icrba_u {
445 u64 reg_value;
446 struct {
447 u64 resvd: 6,
448 stall_bte0: 1, /* Stall BTE 0 */
449 stall_bte1: 1, /* Stall BTE 1 */
450 error: 1, /* CRB has an error */
451 ecode: 3, /* Error Code */
452 lnetuce: 1, /* SN0net Uncorrectable error */
453 mark: 1, /* CRB Has been marked */
454 xerr: 1, /* Error bit set in xtalk header */
455 sidn: 4, /* SIDN field from xtalk */
456 tnum: 5, /* TNUM field in xtalk */
457 addr: 38, /* Address of request */
458 valid: 1, /* Valid status */
459 iow: 1; /* IO Write operation */
460 } icrba_fields_s;
461} icrba_t;
462
463/* This is an alternate typedef for the HUB1 CRB A in order to allow
464 runtime selection of the format based on the REV_ID field of the
465 NI_STATUS_REV_ID register. */
466typedef union h1_icrba_u {
467 u64 reg_value;
468
469 struct {
470 u64 resvd: 6,
471 unused: 1, /* Unused but RW!! */
472 error: 1, /* CRB has an error */
473 ecode: 4, /* Error Code */
474 lnetuce: 1, /* SN0net Uncorrectable error */
475 mark: 1, /* CRB Has been marked */
476 xerr: 1, /* Error bit set in xtalk header */
477 sidn: 4, /* SIDN field from xtalk */
478 tnum: 5, /* TNUM field in xtalk */
479 addr: 38, /* Address of request */
480 valid: 1, /* Valid status */
481 iow: 1; /* IO Write operation */
482 } h1_icrba_fields_s;
483} h1_icrba_t;
484
485/* XXX - Is this still right? Check the spec. */
486#define ICRBN_A_CERR_SHFT 54
487#define ICRBN_A_ERR_MASK 0x3ff
488
489#endif /* !__ASSEMBLY__ */
490
491#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
492
493/*
494 * values for "ecode" field
495 */
496#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
497#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
498#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
499 * e.g. WINV to a Read only line.
500 */
501#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
502#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
503#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
504#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
505#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
506
507
508
509/*
510 * Fields in CRB Register B
511 */
512#ifndef __ASSEMBLY__
513typedef union icrbb_u {
514 u64 reg_value;
515 struct {
516 u64 rsvd1: 5,
517 btenum: 1, /* BTE to which entry belongs to */
518 cohtrans: 1, /* Coherent transaction */
519 xtsize: 2, /* Xtalk operation size
520 * 0: Double Word
521 * 1: 32 Bytes.
522 * 2: 128 Bytes,
523 * 3: Reserved.
524 */
525 srcnode: 9, /* Source Node ID */
526 srcinit: 2, /* Source Initiator:
527 * See below for field values.
528 */
529 useold: 1, /* Use OLD command for processing */
530 imsgtype: 2, /* Incoming message type
531 * see below for field values
532 */
533 imsg: 8, /* Incoming message */
534 initator: 3, /* Initiator of original request
535 * See below for field values.
536 */
537 reqtype: 5, /* Identifies type of request
538 * See below for field values.
539 */
540 rsvd2: 7,
541 ackcnt: 11, /* Invalidate ack count */
542 resp: 1, /* data response given to processor */
543 ack: 1, /* indicates data ack received */
544 hold: 1, /* entry is gathering inval acks */
545 wb_pend:1, /* waiting for writeback to complete */
546 intvn: 1, /* Intervention */
547 stall_ib: 1, /* Stall Ibuf (from crosstalk) */
548 stall_intr: 1; /* Stall internal interrupts */
549 } icrbb_field_s;
550} icrbb_t;
551
552/* This is an alternate typedef for the HUB1 CRB B in order to allow
553 runtime selection of the format based on the REV_ID field of the
554 NI_STATUS_REV_ID register. */
555typedef union h1_icrbb_u {
556 u64 reg_value;
557 struct {
558 u64 rsvd1: 5,
559 btenum: 1, /* BTE to which entry belongs to */
560 cohtrans: 1, /* Coherent transaction */
561 xtsize: 2, /* Xtalk operation size
562 * 0: Double Word
563 * 1: 32 Bytes.
564 * 2: 128 Bytes,
565 * 3: Reserved.
566 */
567 srcnode: 9, /* Source Node ID */
568 srcinit: 2, /* Source Initiator:
569 * See below for field values.
570 */
571 useold: 1, /* Use OLD command for processing */
572 imsgtype: 2, /* Incoming message type
573 * see below for field values
574 */
575 imsg: 8, /* Incoming message */
576 initator: 3, /* Initiator of original request
577 * See below for field values.
578 */
579 rsvd2: 1,
580 pcache: 1, /* entry belongs to partial cache */
581 reqtype: 5, /* Identifies type of request
582 * See below for field values.
583 */
584 stl_ib: 1, /* stall Ibus coming from xtalk */
585 stl_intr: 1, /* Stall internal interrupts */
586 stl_bte0: 1, /* Stall BTE 0 */
587 stl_bte1: 1, /* Stall BTE 1 */
588 intrvn: 1, /* Req was target of intervention */
589 ackcnt: 11, /* Invalidate ack count */
590 resp: 1, /* data response given to processor */
591 ack: 1, /* indicates data ack received */
592 hold: 1, /* entry is gathering inval acks */
593 wb_pend:1, /* waiting for writeback to complete */
594 sleep: 1, /* xtalk req sleeping till IO-sync */
595 pnd_reply: 1, /* replies not issed due to IOQ full */
596 pnd_req: 1; /* reqs not issued due to IOQ full */
597 } h1_icrbb_field_s;
598} h1_icrbb_t;
599
600
601#define b_imsgtype icrbb_field_s.imsgtype
602#define b_btenum icrbb_field_s.btenum
603#define b_cohtrans icrbb_field_s.cohtrans
604#define b_xtsize icrbb_field_s.xtsize
605#define b_srcnode icrbb_field_s.srcnode
606#define b_srcinit icrbb_field_s.srcinit
607#define b_imsgtype icrbb_field_s.imsgtype
608#define b_imsg icrbb_field_s.imsg
609#define b_initiator icrbb_field_s.initiator
610
611#endif /* !__ASSEMBLY__ */
612
613/*
614 * values for field xtsize
615 */
616#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */
617#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */
618#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */
619
620/*
621 * values for field srcinit
622 */
623#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
624#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
625#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */
626#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
627
628/*
629 * Values for field imsgtype
630 */
631#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
632#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
633#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
634#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
635
636/*
637 * values for field initiator.
638 */
639#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
640#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
641#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */
642#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
643#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
644
645/*
646 * Values for field reqtype.
647 */
648/* XXX - Need to fix this for Hub 2 */
649#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */
650#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */
651#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */
652#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */
653#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */
654#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */
655#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */
656#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */
657#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */
658#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */
659#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */
660#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */
661#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */
662#define IIO_ICRB_REQ_WB 16 /* Request is Write back */
663#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */
664
665/*
666 * Fields in CRB Register C
667 */
668
669#ifndef __ASSEMBLY__
670
671typedef union icrbc_s {
672 u64 reg_value;
673 struct {
674 u64 rsvd: 6,
675 sleep: 1,
676 pricnt: 4, /* Priority count sent with Read req */
677 pripsc: 4, /* Priority Pre scalar */
678 bteop: 1, /* BTE Operation */
679 push_be: 34, /* Push address Byte enable
680 * Holds push addr, if CRB is for BTE
681 * If CRB belongs to Partial cache,
682 * this contains byte enables bits
683 * ([47:46] = 0)
684 */
685 suppl: 11, /* Supplemental field */
686 barrop: 1, /* Barrier Op bit set in xtalk req */
687 doresp: 1, /* Xtalk req needs a response */
688 gbr: 1; /* GBR bit set in xtalk packet */
689 } icrbc_field_s;
690} icrbc_t;
691
692#define c_pricnt icrbc_field_s.pricnt
693#define c_pripsc icrbc_field_s.pripsc
694#define c_bteop icrbc_field_s.bteop
695#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */
696#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */
697#define c_suppl icrbc_field_s.suppl
698#define c_barrop icrbc_field_s.barrop
699#define c_doresp icrbc_field_s.doresp
700#define c_gbr icrbc_field_s.gbr
701#endif /* !__ASSEMBLY__ */
702
703/*
704 * Fields in CRB Register D
705 */
706
707#ifndef __ASSEMBLY__
708typedef union icrbd_s {
709 u64 reg_value;
710 struct {
711 u64 rsvd: 38,
712 toutvld: 1, /* Timeout in progress for this CRB */
713 ctxtvld: 1, /* Context field below is valid */
714 rsvd2: 1,
715 context: 15, /* Bit vector:
716 * Has a bit set for each CRB entry
717 * which needs to be deallocated
718 * before this CRB entry is processed.
719 * Set only for barrier operations.
720 */
721 timeout: 8; /* Timeout Upper 8 bits */
722 } icrbd_field_s;
723} icrbd_t;
724
725#define icrbd_toutvld icrbd_field_s.toutvld
726#define icrbd_ctxtvld icrbd_field_s.ctxtvld
727#define icrbd_context icrbd_field_s.context
728
729
730typedef union hubii_ifdr_u {
731 u64 hi_ifdr_value;
732 struct {
733 u64 ifdr_rsvd: 49,
734 ifdr_maxrp: 7,
735 ifdr_rsvd1: 1,
736 ifdr_maxrq: 7;
737 } hi_ifdr_fields;
738} hubii_ifdr_t;
739
740#endif /* !__ASSEMBLY__ */
741
742/*
743 * Hardware designed names for the BTE control registers.
744 */
745#define IIO_IBLS_0 0x410000 /* BTE length/status 0 */
746#define IIO_IBSA_0 0x410008 /* BTE source address 0 */
747#define IIO_IBDA_0 0x410010 /* BTE destination address 0 */
748#define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */
749#define IIO_IBNA_0 0x410020 /* BTE notification address 0 */
750#define IIO_IBNR_0 IIO_IBNA_0
751#define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */
752
753#define IIO_IBLS_1 0x420000 /* BTE length/status 1 */
754#define IIO_IBSA_1 0x420008 /* BTE source address 1 */
755#define IIO_IBDA_1 0x420010 /* BTE destination address 1 */
756#define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */
757#define IIO_IBNA_1 0x420020 /* BTE notification address 1 */
758#define IIO_IBNR_1 IIO_IBNA_1
759#define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */
760
761/*
762 * More miscellaneous registers
763 */
764#define IIO_IPCR 0x430000 /* Performance Control */
765#define IIO_IPPR 0x430008 /* Performance Profiling */
766
767/*
768 * IO Error Clear register bit field definitions
769 */
770#define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */
771#define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */
772#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
773#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
774#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
775#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
776#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
777#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
778#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
779#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
780#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
781#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
782
783/*
784 * IO PIO Read Table Entry format
785 */
786
787#ifndef __ASSEMBLY__
788
789typedef union iprte_a {
790 u64 entry;
791 struct {
792 u64 rsvd1 : 7, /* Reserved field */
793 valid : 1, /* Maps to a timeout entry */
794 rsvd2 : 1,
795 srcnode : 9, /* Node which did this PIO */
796 initiator : 2, /* If T5A or T5B or IO */
797 rsvd3 : 3,
798 addr : 38, /* Physical address of PIO */
799 rsvd4 : 3;
800 } iprte_fields;
801} iprte_a_t;
802
803#define iprte_valid iprte_fields.valid
804#define iprte_timeout iprte_fields.timeout
805#define iprte_srcnode iprte_fields.srcnode
806#define iprte_init iprte_fields.initiator
807#define iprte_addr iprte_fields.addr
808
809#endif /* !__ASSEMBLY__ */
810
811#define IPRTE_ADDRSHFT 3
812
813/*
814 * Hub IIO PRB Register format.
815 */
816
817#ifndef __ASSEMBLY__
818/*
819 * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
820 * "Status" fields, and should only be used in case of clean up after errors.
821 */
822
823typedef union iprb_u {
824 u64 reg_value;
825 struct {
826 u64 rsvd1: 15,
827 error: 1, /* Widget rcvd wr resp pkt w/ error */
828 ovflow: 5, /* Over flow count. perf measurement */
829 fire_and_forget: 1, /* Launch Write without response */
830 mode: 2, /* Widget operation Mode */
831 rsvd2: 2,
832 bnakctr: 14,
833 rsvd3: 2,
834 anakctr: 14,
835 xtalkctr: 8;
836 } iprb_fields_s;
837} iprb_t;
838
839#define iprb_regval reg_value
840
841#define iprb_error iprb_fields_s.error
842#define iprb_ovflow iprb_fields_s.ovflow
843#define iprb_ff iprb_fields_s.fire_and_forget
844#define iprb_mode iprb_fields_s.mode
845#define iprb_bnakctr iprb_fields_s.bnakctr
846#define iprb_anakctr iprb_fields_s.anakctr
847#define iprb_xtalkctr iprb_fields_s.xtalkctr
848
849#endif /* !__ASSEMBLY__ */
850
851/*
852 * values for mode field in iprb_t.
853 * For details of the meanings of NAK and Accept, refer the PIO flow
854 * document
855 */
856#define IPRB_MODE_NORMAL (0)
857#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
858#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
859#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
860
861/*
862 * IO CRB entry C_A to E_A : Partial (cache) CRBS
863 */
864#ifndef __ASSEMBLY__
865typedef union icrbp_a {
866 u64 ip_reg; /* the entire register value */
867 struct {
868 u64 error: 1, /* 63, error occurred */
869 ln_uce: 1, /* 62: uncorrectable memory */
870 ln_ae: 1, /* 61: protection violation */
871 ln_werr:1, /* 60: write access error */
872 ln_aerr:1, /* 59: sn0net: Address error */
873 ln_perr:1, /* 58: sn0net: poison error */
874 timeout:1, /* 57: CRB timed out */
875 l_bdpkt:1, /* 56: truncated pkt on sn0net */
876 c_bdpkt:1, /* 55: truncated pkt on xtalk */
877 c_err: 1, /* 54: incoming xtalk req, err set*/
878 rsvd1: 12, /* 53-42: reserved */
879 valid: 1, /* 41: Valid status */
880 sidn: 4, /* 40-37: SIDN field of xtalk rqst */
881 tnum: 5, /* 36-32: TNUM of xtalk request */
882 bo: 1, /* 31: barrier op set in xtalk rqst*/
883 resprqd:1, /* 30: xtalk rqst requires response*/
884 gbr: 1, /* 29: gbr bit set in xtalk rqst */
885 size: 2, /* 28-27: size of xtalk request */
886 excl: 4, /* 26-23: exclusive bit(s) */
887 stall: 3, /* 22-20: stall (xtalk, bte 0/1) */
888 intvn: 1, /* 19: rqst target of intervention*/
889 resp: 1, /* 18: Data response given to t5 */
890 ack: 1, /* 17: Data ack received. */
891 hold: 1, /* 16: crb gathering invalidate acks*/
892 wb: 1, /* 15: writeback pending. */
893 ack_cnt:11, /* 14-04: counter of invalidate acks*/
894 tscaler:4; /* 03-00: Timeout prescaler */
895 } ip_fmt;
896} icrbp_a_t;
897
898#endif /* !__ASSEMBLY__ */
899
900/*
901 * A couple of defines to go with the above structure.
902 */
903#define ICRBP_A_CERR_SHFT 54
904#define ICRBP_A_ERR_MASK 0x3ff
905
906#ifndef __ASSEMBLY__
907typedef union hubii_idsr {
908 u64 iin_reg;
909 struct {
910 u64 rsvd1 : 35,
911 isent : 1,
912 rsvd2 : 3,
913 ienable: 1,
914 rsvd : 7,
915 node : 9,
916 rsvd4 : 1,
917 level : 7;
918 } iin_fmt;
919} hubii_idsr_t;
920#endif /* !__ASSEMBLY__ */
921
922/*
923 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
924 */
925#define IBLS_BUSY (0x1 << 20)
926#define IBLS_ERROR_SHFT 16
927#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
928#define IBLS_LENGTH_MASK 0xffff
929
930/*
931 * IO BTE Control/Terminate register (IBCT) register bit field definitions
932 */
933#define IBCT_POISON (0x1 << 8)
934#define IBCT_NOTIFY (0x1 << 4)
935#define IBCT_ZFIL_MODE (0x1 << 0)
936
937/*
938 * IO BTE Interrupt Address Register (IBIA) register bit field definitions
939 */
940#define IBIA_LEVEL_SHFT 16
941#define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT)
942#define IBIA_NODE_ID_SHFT 0
943#define IBIA_NODE_ID_MASK (0x1ff)
944
945/*
946 * Miscellaneous hub constants
947 */
948
949/* Number of widgets supported by hub */
950#define HUB_NUM_WIDGET 9
951#define HUB_WIDGET_ID_MIN 0x8
952#define HUB_WIDGET_ID_MAX 0xf
953
954#define HUB_WIDGET_PART_NUM 0xc101
955#define MAX_HUBS_PER_XBOW 2
956
957/*
958 * Get a hub's widget id from widget control register
959 */
960#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
961#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
962
963/*
964 * Number of credits Hub widget has while sending req/response to
965 * xbow.
966 * Value of 3 is required by Xbow 1.1
967 * We may be able to increase this to 4 with Xbow 1.2.
968 */
969#define HUBII_XBOW_CREDIT 3
970#define HUBII_XBOW_REV2_CREDIT 4
971
972#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
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