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-rw-r--r--include/asm-mips/sibyte/bcm1480_int.h2
-rw-r--r--include/asm-mips/sibyte/bcm1480_mc.h32
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h20
-rw-r--r--include/asm-mips/sibyte/bcm1480_scd.h94
-rw-r--r--include/asm-mips/sibyte/board.h14
-rw-r--r--include/asm-mips/sibyte/carmel.h1
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h5
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h24
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h46
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h30
-rw-r--r--include/asm-mips/sibyte/swarm.h12
12 files changed, 175 insertions, 107 deletions
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
index 42d4cf00efd3..c0d5206020fd 100644
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -157,6 +157,7 @@
157 * Mask values for each interrupt 157 * Mask values for each interrupt
158 */ 158 */
159 159
160#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F))
160#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) 161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
161#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) 162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
162 163
@@ -195,6 +196,7 @@
195#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) 196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
196#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) 197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
197#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) 198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0)
198#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) 200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
199#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) 201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
200#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) 202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
index 6bdc941afc91..a6a437451da4 100644
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -382,6 +382,10 @@
382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
384 384
385#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0)
386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0)
387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0)
388
385#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
386 390
387/* 391/*
@@ -412,6 +416,8 @@
412#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 416#define K_BCM1480_MC_DRAM_TYPE_DDR2 2
413#endif 417#endif
414 418
419#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0
420
415#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) 421#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
416#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) 422#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
417 423
@@ -511,6 +517,22 @@
511#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) 517#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
512 518
513#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
520
521#define S_BCM1480_MC_ODT0 0
522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0)
523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0)
524
525#define S_BCM1480_MC_ODT2 8
526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2)
527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2)
528
529#define S_BCM1480_MC_ODT4 16
530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4)
531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4)
532
533#define S_BCM1480_MC_ODT6 24
534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6)
535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6)
514#endif 536#endif
515 537
516/* 538/*
@@ -588,11 +610,11 @@
588#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) 610#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
589#endif 611#endif
590 612
591#define S_BCM1480_MC_DLL_DEFAULT 48 613#define S_BCM1480_MC_DLL_DEFAULT 48
592#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT)
593#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT)
594#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT)
595#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
596 618
597#if SIBYTE_HDR_FEATURE(1480, PASS2) 619#if SIBYTE_HDR_FEATURE(1480, PASS2)
598#define S_BCM1480_MC_DLL_REGCTRL 54 620#define S_BCM1480_MC_DLL_REGCTRL 54
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index c2dd2fe3047c..bda391d3af85 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -230,6 +230,7 @@
230 230
231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) 231#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) 232#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
233#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT)
233 234
234/* 235/*
235 * These constants are the absolute addresses. 236 * These constants are the absolute addresses.
@@ -404,6 +405,21 @@
404#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 405#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
405#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 406#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
406 407
408/*
409 * these macros work together to build the address of a mailbox
410 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
411 * for mbox_0_set_cpu2 returns 0x00100240C8
412 */
413#define R_BCM1480_IMR_MAILBOX_CPU 0x00
414#define R_BCM1480_IMR_MAILBOX_SET 0x08
415#define R_BCM1480_IMR_MAILBOX_CLR 0x10
416#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
417#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \
418 (A_BCM1480_IMR_CPU0_BASE + \
419 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
420 (cpu * BCM1480_IMR_REGISTER_SPACING) + \
421 (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
422
407/* ********************************************************************* 423/* *********************************************************************
408 * System Performance Counter Registers (Section 4.7) 424 * System Performance Counter Registers (Section 4.7)
409 ********************************************************************* */ 425 ********************************************************************* */
@@ -428,6 +444,10 @@
428#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 444#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
429#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 445#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
430 446
447#define BCM1480_SCD_NUM_PERF_CNT 8
448#define BCM1480_SCD_PERF_CNT_SPACING 8
449#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
450
431/* ********************************************************************* 451/* *********************************************************************
432 * System Bus Watcher Registers (Section 4.8) 452 * System Bus Watcher Registers (Section 4.8)
433 ********************************************************************* */ 453 ********************************************************************* */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
index 648bed96780f..6111d6dcf117 100644
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003,2004,2005
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -78,6 +78,7 @@
78#define K_SYS_PART_BCM1280 0x1206 78#define K_SYS_PART_BCM1280 0x1206
79#define K_SYS_PART_BCM1455 0x1407 79#define K_SYS_PART_BCM1455 0x1407
80#define K_SYS_PART_BCM1255 0x1257 80#define K_SYS_PART_BCM1255 0x1257
81#define K_SYS_PART_BCM1158 0x1156
81 82
82/* 83/*
83 * Manufacturing Information Register (Table 14) 84 * Manufacturing Information Register (Table 14)
@@ -237,58 +238,42 @@
237 * System Performance Counter Configuration Register (Table 31) 238 * System Performance Counter Configuration Register (Table 31)
238 * Register: PERF_CNT_CFG_0 239 * Register: PERF_CNT_CFG_0
239 * 240 *
240 * Since the clear/enable bits are moved compared to the 241 * SPC_CFG_SRC[0-3] is the same as the 1250.
241 * 1250 and there are more fields, this register will be BCM1480 specific. 242 * SPC_CFG_SRC[4-7] only exist on the 1480
243 * The clear/enable bits are in different locations on the 1250 and 1480.
242 */ 244 */
243 245
244#define S_BCM1480_SPC_CFG_SRC0 0 246#define S_SPC_CFG_SRC4 32
245#define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0) 247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4)
246#define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0) 248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4)
247#define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0) 249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4)
248 250
249#define S_BCM1480_SPC_CFG_SRC1 8 251#define S_SPC_CFG_SRC5 40
250#define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1) 252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5)
251#define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1) 253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5)
252#define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1) 254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5)
253 255
254#define S_BCM1480_SPC_CFG_SRC2 16 256#define S_SPC_CFG_SRC6 48
255#define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2) 257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6)
256#define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2) 258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6)
257#define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2) 259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6)
258 260
259#define S_BCM1480_SPC_CFG_SRC3 24 261#define S_SPC_CFG_SRC7 56
260#define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3) 262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7)
261#define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3) 263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7)
262#define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3) 264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7)
263
264#define S_BCM1480_SPC_CFG_SRC4 32
265#define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)
266#define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)
267#define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)
268
269#define S_BCM1480_SPC_CFG_SRC5 40
270#define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)
271#define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)
272#define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)
273
274#define S_BCM1480_SPC_CFG_SRC6 48
275#define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)
276#define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)
277#define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)
278
279#define S_BCM1480_SPC_CFG_SRC7 56
280#define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)
281#define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)
282#define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)
283 265
284/* 266/*
285 * System Performance Counter Control Register (Table 32) 267 * System Performance Counter Control Register (Table 32)
286 * Register: PERF_CNT_CFG_1 268 * Register: PERF_CNT_CFG_1
287 * BCM1480 specific 269 * BCM1480 specific
288 */ 270 */
289 271#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
290#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) 272#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
291#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) 273#if SIBYTE_HDR_FEATURE_CHIP(1480)
274#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR
275#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE
276#endif
292 277
293/* 278/*
294 * System Performance Counters (Table 33) 279 * System Performance Counters (Table 33)
@@ -405,20 +390,10 @@
405 * Trace Control Register (Table 49) 390 * Trace Control Register (Table 49)
406 * Register: TRACE_CFG 391 * Register: TRACE_CFG
407 * 392 *
408 * Bits 0..8 are the same as the BCM1250, rest are different. 393 * BCM1480 changes to this register (other than location of the CUR_ADDR field)
409 * Entire register is redefined below. 394 * are defined below.
410 */ 395 */
411 396
412#define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
413#define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
414#define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
415#define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
416#define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
417#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
418#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
419#define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
420#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8)
421
422#define S_BCM1480_SCD_TRACE_CFG_MODE 16 397#define S_BCM1480_SCD_TRACE_CFG_MODE 16
423#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) 398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)
424#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) 399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
@@ -428,9 +403,4 @@
428#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
429#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 404#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
430 405
431#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24
432#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
433#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
434#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)
435
436#endif /* _BCM1480_SCD_H */ 406#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index 3dfe29ed42a8..73bce901a378 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -19,8 +19,8 @@
19#ifndef _SIBYTE_BOARD_H 19#ifndef _SIBYTE_BOARD_H
20#define _SIBYTE_BOARD_H 20#define _SIBYTE_BOARD_H
21 21
22
23#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ 22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
23 defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \
24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \ 24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
25 defined(CONFIG_SIBYTE_LITTLESUR) 25 defined(CONFIG_SIBYTE_LITTLESUR)
26#include <asm/sibyte/swarm.h> 26#include <asm/sibyte/swarm.h>
@@ -55,6 +55,16 @@
55#define setleds(t0,t1,c0,c1,c2,c3) 55#define setleds(t0,t1,c0,c1,c2,c3)
56#endif /* LEDS_PHYS */ 56#endif /* LEDS_PHYS */
57 57
58#else
59
60void swarm_setup(void);
61
62#ifdef LEDS_PHYS
63extern void setleds(char *str);
64#else
65#define setleds(s) do { } while (0)
66#endif /* LEDS_PHYS */
67
58#endif /* __ASSEMBLY__ */ 68#endif /* __ASSEMBLY__ */
59 69
60#endif /* _SIBYTE_BOARD_H */ 70#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 57c53e62a37a..11cad71323e8 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -18,7 +18,6 @@
18#ifndef __ASM_SIBYTE_CARMEL_H 18#ifndef __ASM_SIBYTE_CARMEL_H
19#define __ASM_SIBYTE_CARMEL_H 19#define __ASM_SIBYTE_CARMEL_H
20 20
21
22#include <asm/sibyte/sb1250.h> 21#include <asm/sibyte/sb1250.h>
23#include <asm/sibyte/sb1250_int.h> 22#include <asm/sibyte/sb1250_int.h>
24 23
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index 05c7b39f1b02..94e8299b0a2a 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -45,8 +45,6 @@
45 * First, the interrupt numbers. 45 * First, the interrupt numbers.
46 */ 46 */
47 47
48#if SIBYTE_HDR_FEATURE_1250_112x
49
50#define K_INT_SOURCES 64 48#define K_INT_SOURCES 64
51 49
52#define K_INT_WATCHDOG_TIMER_0 0 50#define K_INT_WATCHDOG_TIMER_0 0
@@ -152,6 +150,7 @@
152#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) 150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
153#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) 151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
154#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) 152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
153#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0)
155#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
156#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) 155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
157#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) 156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
@@ -247,5 +246,3 @@
247 246
248 247
249#endif /* 1250/112x */ 248#endif /* 1250/112x */
250
251#endif
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index adfc688fa559..833c8b59d687 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -129,9 +129,9 @@
129#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 129#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
130#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 130#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
131 131
132#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 132#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
133#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 133#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
134#endif /* 1250 PASS2 || 112x PASS1 */ 134#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
135 135
136#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 136#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
137#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 137#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
@@ -223,9 +223,9 @@
223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
225#endif /* up to 1250 PASS1 */ 225#endif /* up to 1250 PASS1 */
226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
228#endif /* 1250 PASS2 || 112x PASS1 */ 228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
231 231
@@ -234,9 +234,9 @@
234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
236#endif /* up to 1250 PASS1 */ 236#endif /* up to 1250 PASS1 */
237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
239#endif /* 1250 PASS2 || 112x PASS1 */ 239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
242 242
@@ -260,12 +260,12 @@
260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
262 262
263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
268#endif /* 1250 PASS2 || 112x PASS1 */ 268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
269 269
270/* 270/*
271 * MAC Frame Configuration Registers (Table 9-15) 271 * MAC Frame Configuration Registers (Table 9-15)
@@ -462,9 +462,9 @@
462#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 462#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
463#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 463#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
464#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 464#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
465#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 465#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 466#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
467#endif /* 1250 PASS2 || 112x PASS1 */ 467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
468 468
469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
@@ -598,9 +598,9 @@
598#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 598#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
599#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 599#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
600#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 600#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
601#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 601#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
602#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 602#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
603#endif /* 1250 PASS2 || 112x PASS1 */ 603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
604 604
605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 26e421498c97..4fe848ffbc31 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -295,7 +295,7 @@
295 295
296#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 296#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
297#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 297#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
298#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) 298#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
299#endif /* 1250 PASS3 || 112x PASS1 */ 299#endif /* 1250 PASS3 || 112x PASS1 */
300 300
301 301
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index bab3a4580a36..da7c188993c9 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -131,6 +131,7 @@
131 131
132#endif 132#endif
133 133
134
134/* ********************************************************************* 135/* *********************************************************************
135 * PCI Interface Registers 136 * PCI Interface Registers
136 ********************************************************************* */ 137 ********************************************************************* */
@@ -239,14 +240,14 @@
239#define R_MAC_VLANTAG 0x00000110 240#define R_MAC_VLANTAG 0x00000110
240#define R_MAC_FRAMECFG 0x00000118 241#define R_MAC_FRAMECFG 0x00000118
241#define R_MAC_EOPCNT 0x00000120 242#define R_MAC_EOPCNT 0x00000120
242#define R_MAC_FIFO_PTRS 0x00000130 243#define R_MAC_FIFO_PTRS 0x00000128
243#define R_MAC_ADFILTER_CFG 0x00000200 244#define R_MAC_ADFILTER_CFG 0x00000200
244#define R_MAC_ETHERNET_ADDR 0x00000208 245#define R_MAC_ETHERNET_ADDR 0x00000208
245#define R_MAC_PKT_TYPE 0x00000210 246#define R_MAC_PKT_TYPE 0x00000210
246#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 247#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
247#define R_MAC_ADMASK0 0x00000218 248#define R_MAC_ADMASK0 0x00000218
248#define R_MAC_ADMASK1 0x00000220 249#define R_MAC_ADMASK1 0x00000220
249#endif /* 1250 PASS3 || 112x PASS1 */ 250#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
250#define R_MAC_HASH_BASE 0x00000240 251#define R_MAC_HASH_BASE 0x00000240
251#define R_MAC_ADDR_BASE 0x00000280 252#define R_MAC_ADDR_BASE 0x00000280
252#define R_MAC_CHLO0_BASE 0x00000300 253#define R_MAC_CHLO0_BASE 0x00000300
@@ -256,9 +257,9 @@
256#define R_MAC_INT_MASK 0x00000410 257#define R_MAC_INT_MASK 0x00000410
257#define R_MAC_TXD_CTL 0x00000420 258#define R_MAC_TXD_CTL 0x00000420
258#define R_MAC_MDIO 0x00000428 259#define R_MAC_MDIO 0x00000428
259#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 260#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
260#define R_MAC_STATUS1 0x00000430 261#define R_MAC_STATUS1 0x00000430
261#endif /* 1250 PASS2 || 112x PASS1 */ 262#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
262#define R_MAC_DEBUG_STATUS 0x00000448 263#define R_MAC_DEBUG_STATUS 0x00000448
263 264
264#define MAC_HASH_COUNT 8 265#define MAC_HASH_COUNT 8
@@ -289,11 +290,11 @@
289#define R_DUART_RX_HOLD 0x160 290#define R_DUART_RX_HOLD 0x160
290#define R_DUART_TX_HOLD 0x170 291#define R_DUART_TX_HOLD 0x170
291 292
292#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 293#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
293#define R_DUART_FULL_CTL 0x140 294#define R_DUART_FULL_CTL 0x140
294#define R_DUART_OPCR_X 0x180 295#define R_DUART_OPCR_X 0x180
295#define R_DUART_AUXCTL_X 0x190 296#define R_DUART_AUXCTL_X 0x190
296#endif /* 1250 PASS2 || 112x PASS1 */ 297#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
297 298
298 299
299/* 300/*
@@ -308,6 +309,7 @@
308#define R_DUART_IMR_B 0x350 309#define R_DUART_IMR_B 0x350
309#define R_DUART_OUT_PORT 0x360 310#define R_DUART_OUT_PORT 0x360
310#define R_DUART_OPCR 0x370 311#define R_DUART_OPCR 0x370
312#define R_DUART_IN_PORT 0x380
311 313
312#define R_DUART_SET_OPR 0x3B0 314#define R_DUART_SET_OPR 0x3B0
313#define R_DUART_CLEAR_OPR 0x3C0 315#define R_DUART_CLEAR_OPR 0x3C0
@@ -685,12 +687,17 @@
685#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 687#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
686#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 688#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
687 689
690#define ADDR_TRAP_SPACING 8
691#define NUM_ADDR_TRAP 4
692#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
693#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
694#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
695
688 696
689/* ********************************************************************* 697/* *********************************************************************
690 * System Interrupt Mapper Registers 698 * System Interrupt Mapper Registers
691 ********************************************************************* */ 699 ********************************************************************* */
692 700
693#if SIBYTE_HDR_FEATURE_1250_112x
694#define A_IMR_CPU0_BASE 0x0010020000 701#define A_IMR_CPU0_BASE 0x0010020000
695#define A_IMR_CPU1_BASE 0x0010022000 702#define A_IMR_CPU1_BASE 0x0010022000
696#define IMR_REGISTER_SPACING 0x2000 703#define IMR_REGISTER_SPACING 0x2000
@@ -700,6 +707,7 @@
700#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 707#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
701 708
702#define R_IMR_INTERRUPT_DIAG 0x0010 709#define R_IMR_INTERRUPT_DIAG 0x0010
710#define R_IMR_INTERRUPT_LDT 0x0018
703#define R_IMR_INTERRUPT_MASK 0x0028 711#define R_IMR_INTERRUPT_MASK 0x0028
704#define R_IMR_INTERRUPT_TRACE 0x0038 712#define R_IMR_INTERRUPT_TRACE 0x0038
705#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 713#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
@@ -715,7 +723,14 @@
715#define R_IMR_INTERRUPT_STATUS_COUNT 7 723#define R_IMR_INTERRUPT_STATUS_COUNT 7
716#define R_IMR_INTERRUPT_MAP_BASE 0x0200 724#define R_IMR_INTERRUPT_MAP_BASE 0x0200
717#define R_IMR_INTERRUPT_MAP_COUNT 64 725#define R_IMR_INTERRUPT_MAP_COUNT 64
718#endif /* 1250/112x */ 726
727/*
728 * these macros work together to build the address of a mailbox
729 * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
730 * for mbox_0_set_cpu2 returns 0x00100240C8
731 */
732#define A_MAILBOX_REGISTER(reg,cpu) \
733 (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
719 734
720/* ********************************************************************* 735/* *********************************************************************
721 * System Performance Counter Registers 736 * System Performance Counter Registers
@@ -727,6 +742,10 @@
727#define A_SCD_PERF_CNT_2 0x00100204E0 742#define A_SCD_PERF_CNT_2 0x00100204E0
728#define A_SCD_PERF_CNT_3 0x00100204E8 743#define A_SCD_PERF_CNT_3 0x00100204E8
729 744
745#define SCD_NUM_PERF_CNT 4
746#define SCD_PERF_CNT_SPACING 8
747#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
748
730/* ********************************************************************* 749/* *********************************************************************
731 * System Bus Watcher Registers 750 * System Bus Watcher Registers
732 ********************************************************************* */ 751 ********************************************************************* */
@@ -772,6 +791,15 @@
772#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 791#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
773#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 792#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
774 793
794#define TRACE_REGISTER_SPACING 8
795#define TRACE_NUM_REGISTERS 8
796#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
797 (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
798 (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
799#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
800 (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
801 (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
802
775/* ********************************************************************* 803/* *********************************************************************
776 * System Generic DMA Registers 804 * System Generic DMA Registers
777 ********************************************************************* */ 805 ********************************************************************* */
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index b6a7d8f6ced5..9ea3da367ab6 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003,2004,2005
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -150,7 +150,7 @@
150 * (For the assembler version, sysrev and dest may be the same register. 150 * (For the assembler version, sysrev and dest may be the same register.
151 * Also, it clobbers AT.) 151 * Also, it clobbers AT.)
152 */ 152 */
153#ifdef __ASSEMBLY__ 153#ifdef __ASSEMBLER__
154#define SYS_SOC_TYPE(dest, sysrev) \ 154#define SYS_SOC_TYPE(dest, sysrev) \
155 .set push ; \ 155 .set push ; \
156 .set reorder ; \ 156 .set reorder ; \
@@ -214,6 +214,7 @@
214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
215#endif 215#endif
216 216
217
217/* 218/*
218 * System Config Register (Table 4-2) 219 * System Config Register (Table 4-2)
219 * Register: SCD_SYSTEM_CFG 220 * Register: SCD_SYSTEM_CFG
@@ -360,13 +361,13 @@
360 */ 361 */
361 362
362#define V_SCD_TIMER_FREQ 1000000 363#define V_SCD_TIMER_FREQ 1000000
363#define V_SCD_TIMER_WIDTH 23
364 364
365#define S_SCD_TIMER_INIT 0 365#define S_SCD_TIMER_INIT 0
366#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT) 366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT)
367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
369 369
370#define V_SCD_TIMER_WIDTH 23
370#define S_SCD_TIMER_CNT 0 371#define S_SCD_TIMER_CNT 0
371#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
372#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
@@ -380,7 +381,6 @@
380 * System Performance Counters 381 * System Performance Counters
381 */ 382 */
382 383
383#if SIBYTE_HDR_FEATURE_1250_112x
384#define S_SPC_CFG_SRC0 0 384#define S_SPC_CFG_SRC0 0
385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -401,6 +401,7 @@
401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
403 403
404#if SIBYTE_HDR_FEATURE_1250_112x
404#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
405#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 406#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
406#endif 407#endif
@@ -516,8 +517,6 @@
516 * Trace Buffer Config register 517 * Trace Buffer Config register
517 */ 518 */
518 519
519#if SIBYTE_HDR_FEATURE_1250_112x
520
521#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 520#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
522#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 521#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
523#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 522#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
@@ -526,17 +525,26 @@
526#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 525#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
527#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 526#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
528#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 527#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
529#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 528#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
530#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 529#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
531#endif /* 1250 PASS2 || 112x PASS1 */ 530#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
532 531
532/*
533 * This field is the same on the 1250/112x and 1480, just located in
534 * a slightly different place in the register.
535 */
536#if SIBYTE_HDR_FEATURE_1250_112x
533#define S_SCD_TRACE_CFG_CUR_ADDR 10 537#define S_SCD_TRACE_CFG_CUR_ADDR 10
538#else
539#if SIBYTE_HDR_FEATURE_CHIP(1480)
540#define S_SCD_TRACE_CFG_CUR_ADDR 24
541#endif /* 1480 */
542#endif /* 1250/112x */
543
534#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
535#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
536#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
537 547
538#endif /* 1250/112x */
539
540/* 548/*
541 * Trace Event registers 549 * Trace Event registers
542 */ 550 */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 86db37e5ad85..540865fa7ec3 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -32,6 +32,18 @@
32#define SIBYTE_HAVE_IDE 1 32#define SIBYTE_HAVE_IDE 1
33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" 33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
34#endif 34#endif
35#ifdef CONFIG_SIBYTE_PT1120
36#define SIBYTE_BOARD_NAME "PT1120"
37#define SIBYTE_HAVE_PCMCIA 1
38#define SIBYTE_HAVE_IDE 1
39#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
40#endif
41#ifdef CONFIG_SIBYTE_PT1125
42#define SIBYTE_BOARD_NAME "PT1125"
43#define SIBYTE_HAVE_PCMCIA 1
44#define SIBYTE_HAVE_IDE 1
45#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
46#endif
35#ifdef CONFIG_SIBYTE_LITTLESUR 47#ifdef CONFIG_SIBYTE_LITTLESUR
36#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" 48#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
37#define SIBYTE_HAVE_PCMCIA 0 49#define SIBYTE_HAVE_PCMCIA 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 00:08:11 -0500