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-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h31
1 files changed, 20 insertions, 11 deletions
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 7ed0bb611e56..9ea3da367ab6 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000,2001,2002,2003,2004,2005
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -84,6 +84,7 @@
84#define K_SYS_REVISION_BCM112x_A2 0x21 84#define K_SYS_REVISION_BCM112x_A2 0x21
85#define K_SYS_REVISION_BCM112x_A3 0x22 85#define K_SYS_REVISION_BCM112x_A3 0x22
86#define K_SYS_REVISION_BCM112x_A4 0x23 86#define K_SYS_REVISION_BCM112x_A4 0x23
87#define K_SYS_REVISION_BCM112x_B0 0x30
87 88
88#define K_SYS_REVISION_BCM1480_S0 0x01 89#define K_SYS_REVISION_BCM1480_S0 0x01
89#define K_SYS_REVISION_BCM1480_A1 0x02 90#define K_SYS_REVISION_BCM1480_A1 0x02
@@ -149,7 +150,7 @@
149 * (For the assembler version, sysrev and dest may be the same register. 150 * (For the assembler version, sysrev and dest may be the same register.
150 * Also, it clobbers AT.) 151 * Also, it clobbers AT.)
151 */ 152 */
152#ifdef __ASSEMBLY__ 153#ifdef __ASSEMBLER__
153#define SYS_SOC_TYPE(dest, sysrev) \ 154#define SYS_SOC_TYPE(dest, sysrev) \
154 .set push ; \ 155 .set push ; \
155 .set reorder ; \ 156 .set reorder ; \
@@ -213,6 +214,7 @@
213#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
214#endif 215#endif
215 216
217
216/* 218/*
217 * System Config Register (Table 4-2) 219 * System Config Register (Table 4-2)
218 * Register: SCD_SYSTEM_CFG 220 * Register: SCD_SYSTEM_CFG
@@ -359,13 +361,13 @@
359 */ 361 */
360 362
361#define V_SCD_TIMER_FREQ 1000000 363#define V_SCD_TIMER_FREQ 1000000
362#define V_SCD_TIMER_WIDTH 23
363 364
364#define S_SCD_TIMER_INIT 0 365#define S_SCD_TIMER_INIT 0
365#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT) 366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT)
366#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
367#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
368 369
370#define V_SCD_TIMER_WIDTH 23
369#define S_SCD_TIMER_CNT 0 371#define S_SCD_TIMER_CNT 0
370#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
371#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
@@ -379,7 +381,6 @@
379 * System Performance Counters 381 * System Performance Counters
380 */ 382 */
381 383
382#if SIBYTE_HDR_FEATURE_1250_112x
383#define S_SPC_CFG_SRC0 0 384#define S_SPC_CFG_SRC0 0
384#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
385#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
@@ -400,6 +401,7 @@
400#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
401#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
402 403
404#if SIBYTE_HDR_FEATURE_1250_112x
403#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
404#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 406#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
405#endif 407#endif
@@ -515,8 +517,6 @@
515 * Trace Buffer Config register 517 * Trace Buffer Config register
516 */ 518 */
517 519
518#if SIBYTE_HDR_FEATURE_1250_112x
519
520#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 520#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
521#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 521#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
522#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 522#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
@@ -525,17 +525,26 @@
525#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 525#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
526#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 526#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
527#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 527#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
528#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 528#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
529#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 529#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
530#endif /* 1250 PASS2 || 112x PASS1 */ 530#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
531 531
532/*
533 * This field is the same on the 1250/112x and 1480, just located in
534 * a slightly different place in the register.
535 */
536#if SIBYTE_HDR_FEATURE_1250_112x
532#define S_SCD_TRACE_CFG_CUR_ADDR 10 537#define S_SCD_TRACE_CFG_CUR_ADDR 10
538#else
539#if SIBYTE_HDR_FEATURE_CHIP(1480)
540#define S_SCD_TRACE_CFG_CUR_ADDR 24
541#endif /* 1480 */
542#endif /* 1250/112x */
543
533#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
534#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
535#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
536 547
537#endif /* 1250/112x */
538
539/* 548/*
540 * Trace Event registers 549 * Trace Event registers
541 */ 550 */