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-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h68
1 files changed, 34 insertions, 34 deletions
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 5d496c6faba6..9db80cd13a79 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -1,23 +1,23 @@
1/* ********************************************************************* 1/* *********************************************************************
2 * SB1250 Board Support Package 2 * SB1250 Board Support Package
3 * 3 *
4 * Register Definitions File: sb1250_regs.h 4 * Register Definitions File: sb1250_regs.h
5 * 5 *
6 * This module contains the addresses of the on-chip peripherals 6 * This module contains the addresses of the on-chip peripherals
7 * on the SB1250. 7 * on the SB1250.
8 * 8 *
9 * SB1250 specification level: 01/02/2002 9 * SB1250 specification level: 01/02/2002
10 * 10 *
11 * Author: Mitch Lichtenberg 11 * Author: Mitch Lichtenberg
12 * 12 *
13 ********************************************************************* 13 *********************************************************************
14 * 14 *
15 * Copyright 2000,2001,2002,2003 15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved. 16 * Broadcom Corporation. All rights reserved.
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 ********************************************************************* */ 32 ********************************************************************* */
33 33
@@ -40,20 +40,20 @@
40 40
41/* ********************************************************************* 41/* *********************************************************************
42 * Some general notes: 42 * Some general notes:
43 * 43 *
44 * For the most part, when there is more than one peripheral 44 * For the most part, when there is more than one peripheral
45 * of the same type on the SOC, the constants below will be 45 * of the same type on the SOC, the constants below will be
46 * offsets from the base of each peripheral. For example, 46 * offsets from the base of each peripheral. For example,
47 * the MAC registers are described as offsets from the first 47 * the MAC registers are described as offsets from the first
48 * MAC register, and there will be a MAC_REGISTER() macro 48 * MAC register, and there will be a MAC_REGISTER() macro
49 * to calculate the base address of a given MAC. 49 * to calculate the base address of a given MAC.
50 * 50 *
51 * The information in this file is based on the SB1250 SOC 51 * The information in this file is based on the SB1250 SOC
52 * manual version 0.2, July 2000. 52 * manual version 0.2, July 2000.
53 ********************************************************************* */ 53 ********************************************************************* */
54 54
55 55
56/* ********************************************************************* 56/* *********************************************************************
57 * Memory Controller Registers 57 * Memory Controller Registers
58 ********************************************************************* */ 58 ********************************************************************* */
59 59
@@ -101,7 +101,7 @@
101#define R_MC_TEST_ECC 0x0000000420 101#define R_MC_TEST_ECC 0x0000000420
102#define R_MC_MCLK_CFG 0x0000000500 102#define R_MC_MCLK_CFG 0x0000000500
103 103
104/* ********************************************************************* 104/* *********************************************************************
105 * L2 Cache Control Registers 105 * L2 Cache Control Registers
106 ********************************************************************* */ 106 ********************************************************************* */
107 107
@@ -126,7 +126,7 @@
126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
127 127
128 128
129/* ********************************************************************* 129/* *********************************************************************
130 * PCI Interface Registers 130 * PCI Interface Registers
131 ********************************************************************* */ 131 ********************************************************************* */
132 132
@@ -134,7 +134,7 @@
134#define A_PCI_TYPE01_HEADER 0x00DE000800 134#define A_PCI_TYPE01_HEADER 0x00DE000800
135 135
136 136
137/* ********************************************************************* 137/* *********************************************************************
138 * Ethernet DMA and MACs 138 * Ethernet DMA and MACs
139 ********************************************************************* */ 139 ********************************************************************* */
140 140
@@ -184,7 +184,7 @@
184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \
185 (reg)) 185 (reg))
186 186
187/* 187/*
188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
189 */ 189 */
190 190
@@ -259,7 +259,7 @@
259#define MAC_CHMAP_COUNT 4 259#define MAC_CHMAP_COUNT 4
260 260
261 261
262/* ********************************************************************* 262/* *********************************************************************
263 * DUART Registers 263 * DUART Registers
264 ********************************************************************* */ 264 ********************************************************************* */
265 265
@@ -363,7 +363,7 @@
363#endif /* 1250 PASS2 || 112x PASS1 */ 363#endif /* 1250 PASS2 || 112x PASS1 */
364 364
365 365
366/* ********************************************************************* 366/* *********************************************************************
367 * Synchronous Serial Registers 367 * Synchronous Serial Registers
368 ********************************************************************* */ 368 ********************************************************************* */
369 369
@@ -397,7 +397,7 @@
397 (reg)) 397 (reg))
398 398
399 399
400/* 400/*
401 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 401 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
402 */ 402 */
403 403
@@ -457,7 +457,7 @@
457#define R_SER_RMON_RX_ERRORS 0x000001F0 457#define R_SER_RMON_RX_ERRORS 0x000001F0
458#define R_SER_RMON_RX_BADADDR 0x000001F8 458#define R_SER_RMON_RX_BADADDR 0x000001F8
459 459
460/* ********************************************************************* 460/* *********************************************************************
461 * Generic Bus Registers 461 * Generic Bus Registers
462 ********************************************************************* */ 462 ********************************************************************* */
463 463
@@ -513,7 +513,7 @@
513#define R_IO_PCMCIA_CFG 0x0A60 513#define R_IO_PCMCIA_CFG 0x0A60
514#define R_IO_PCMCIA_STATUS 0x0A70 514#define R_IO_PCMCIA_STATUS 0x0A70
515 515
516/* ********************************************************************* 516/* *********************************************************************
517 * GPIO Registers 517 * GPIO Registers
518 ********************************************************************* */ 518 ********************************************************************* */
519 519
@@ -537,7 +537,7 @@
537#define R_GPIO_PIN_CLR 0x30 537#define R_GPIO_PIN_CLR 0x30
538#define R_GPIO_PIN_SET 0x38 538#define R_GPIO_PIN_SET 0x38
539 539
540/* ********************************************************************* 540/* *********************************************************************
541 * SMBus Registers 541 * SMBus Registers
542 ********************************************************************* */ 542 ********************************************************************* */
543 543
@@ -573,7 +573,7 @@
573#define R_SMB_CONTROL 0x0000000060 573#define R_SMB_CONTROL 0x0000000060
574#define R_SMB_PEC 0x0000000070 574#define R_SMB_PEC 0x0000000070
575 575
576/* ********************************************************************* 576/* *********************************************************************
577 * Timer Registers 577 * Timer Registers
578 ********************************************************************* */ 578 ********************************************************************* */
579 579
@@ -641,7 +641,7 @@
641#endif /* 1250 PASS2 || 112x PASS1 */ 641#endif /* 1250 PASS2 || 112x PASS1 */
642 642
643 643
644/* ********************************************************************* 644/* *********************************************************************
645 * System Control Registers 645 * System Control Registers
646 ********************************************************************* */ 646 ********************************************************************* */
647 647
@@ -649,7 +649,7 @@
649#define A_SCD_SYSTEM_CFG 0x0010020008 649#define A_SCD_SYSTEM_CFG 0x0010020008
650#define A_SCD_SYSTEM_MANUF 0x0010038000 650#define A_SCD_SYSTEM_MANUF 0x0010038000
651 651
652/* ********************************************************************* 652/* *********************************************************************
653 * System Address Trap Registers 653 * System Address Trap Registers
654 ********************************************************************* */ 654 ********************************************************************* */
655 655
@@ -672,7 +672,7 @@
672#endif /* 1250 PASS2 || 112x PASS1 */ 672#endif /* 1250 PASS2 || 112x PASS1 */
673 673
674 674
675/* ********************************************************************* 675/* *********************************************************************
676 * System Interrupt Mapper Registers 676 * System Interrupt Mapper Registers
677 ********************************************************************* */ 677 ********************************************************************* */
678 678
@@ -701,7 +701,7 @@
701#define R_IMR_INTERRUPT_MAP_BASE 0x0200 701#define R_IMR_INTERRUPT_MAP_BASE 0x0200
702#define R_IMR_INTERRUPT_MAP_COUNT 64 702#define R_IMR_INTERRUPT_MAP_COUNT 64
703 703
704/* ********************************************************************* 704/* *********************************************************************
705 * System Performance Counter Registers 705 * System Performance Counter Registers
706 ********************************************************************* */ 706 ********************************************************************* */
707 707
@@ -711,7 +711,7 @@
711#define A_SCD_PERF_CNT_2 0x00100204E0 711#define A_SCD_PERF_CNT_2 0x00100204E0
712#define A_SCD_PERF_CNT_3 0x00100204E8 712#define A_SCD_PERF_CNT_3 0x00100204E8
713 713
714/* ********************************************************************* 714/* *********************************************************************
715 * System Bus Watcher Registers 715 * System Bus Watcher Registers
716 ********************************************************************* */ 716 ********************************************************************* */
717 717
@@ -726,13 +726,13 @@
726#define A_BUS_L2_ERRORS 0x00100208C0 726#define A_BUS_L2_ERRORS 0x00100208C0
727#define A_BUS_MEM_IO_ERRORS 0x00100208C8 727#define A_BUS_MEM_IO_ERRORS 0x00100208C8
728 728
729/* ********************************************************************* 729/* *********************************************************************
730 * System Debug Controller Registers 730 * System Debug Controller Registers
731 ********************************************************************* */ 731 ********************************************************************* */
732 732
733#define A_SCD_JTAG_BASE 0x0010000000 733#define A_SCD_JTAG_BASE 0x0010000000
734 734
735/* ********************************************************************* 735/* *********************************************************************
736 * System Trace Buffer Registers 736 * System Trace Buffer Registers
737 ********************************************************************* */ 737 ********************************************************************* */
738 738
@@ -755,7 +755,7 @@
755#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 755#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
756#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 756#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
757 757
758/* ********************************************************************* 758/* *********************************************************************
759 * System Generic DMA Registers 759 * System Generic DMA Registers
760 ********************************************************************* */ 760 ********************************************************************* */
761 761
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 11:48:14 -0500